| 1 | Patches for rc1: nothing major, just some minor bugfixes and | 1 | Nothing exciting here: two minor bug fixes, some fixes for |
|---|---|---|---|
| 2 | code cleanups. | 2 | running on a 32-bit host, and a docs tweak. |
| 3 | 3 | ||
| 4 | thanks | ||
| 4 | -- PMM | 5 | -- PMM |
| 5 | 6 | ||
| 6 | The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f: | 7 | The following changes since commit 6af9d12c88b9720f209912f6e4b01fefe5906d59: |
| 7 | 8 | ||
| 8 | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000) | 9 | Merge tag 'migration-20240331-pull-request' of https://gitlab.com/peterx/qemu into staging (2024-04-01 13:12:40 +0100) |
| 9 | 10 | ||
| 10 | are available in the Git repository at: | 11 | are available in the Git repository at: |
| 11 | 12 | ||
| 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110 | 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240402 |
| 13 | 14 | ||
| 14 | for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa: | 15 | for you to fetch changes up to 393770d7a02135e7468018f52da610712f151ec0: |
| 15 | 16 | ||
| 16 | target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000) | 17 | raspi4b: Reduce RAM to 1Gb on 32-bit hosts (2024-04-02 10:13:48 +0100) |
| 17 | 18 | ||
| 18 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
| 19 | target-arm queue: | 20 | target-arm queue: |
| 20 | * hw/arm/Kconfig: ARM_V7M depends on PTIMER | 21 | * take HSTR traps of cp15 accesses to EL2, not EL1 |
| 21 | * Minor coding style fixes | 22 | * docs: sbsa: update specs, add dt note |
| 22 | * docs: add some notes on the sbsa-ref machine | 23 | * hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled |
| 23 | * hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals | 24 | * tests/qtest: Fix STM32L4x5 GPIO test on 32-bit |
| 24 | * target/arm: Fix neon VTBL/VTBX for len > 1 | 25 | * raspi4b: Reduce RAM to 1Gb on 32-bit hosts |
| 25 | * hw/arm/armsse: Correct expansion MPC interrupt lines | ||
| 26 | * hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ | ||
| 27 | * hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() | ||
| 28 | * hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input | ||
| 29 | * hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary | ||
| 30 | * hw/arm/nseries: Check return value from load_image_targphys() | ||
| 31 | * tests/qtest/npcm7xx_rng-test: count runs properly | ||
| 32 | * target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check | ||
| 33 | 26 | ||
| 34 | ---------------------------------------------------------------- | 27 | ---------------------------------------------------------------- |
| 35 | Alex Bennée (1): | 28 | Cédric Le Goater (2): |
| 36 | docs: add some notes on the sbsa-ref machine | 29 | tests/qtest: Fix STM32L4x5 GPIO test on 32-bit |
| 30 | raspi4b: Reduce RAM to 1Gb on 32-bit hosts | ||
| 37 | 31 | ||
| 38 | AlexChen (1): | 32 | Marcin Juszkiewicz (1): |
| 39 | ssi: Fix bad printf format specifiers | 33 | docs: sbsa: update specs, add dt note |
| 40 | |||
| 41 | Andrew Jones (1): | ||
| 42 | hw/arm/Kconfig: ARM_V7M depends on PTIMER | ||
| 43 | |||
| 44 | Havard Skinnemoen (1): | ||
| 45 | tests/qtest/npcm7xx_rng-test: count runs properly | ||
| 46 | 34 | ||
| 47 | Peter Maydell (2): | 35 | Peter Maydell (2): |
| 48 | hw/arm/nseries: Check return value from load_image_targphys() | 36 | target/arm: take HSTR traps of cp15 accesses to EL2, not EL1 |
| 49 | target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check | 37 | hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled |
| 50 | 38 | ||
| 51 | Philippe Mathieu-Daudé (6): | 39 | docs/system/arm/sbsa.rst | 35 +++++++++++++++++------ |
| 52 | hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals | 40 | hw/arm/raspi4b.c | 4 +++ |
| 53 | hw/arm/armsse: Correct expansion MPC interrupt lines | 41 | hw/intc/arm_gicv3_cpuif.c | 4 +-- |
| 54 | hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ | 42 | target/arm/tcg/translate.c | 2 +- |
| 55 | hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup() | 43 | tests/qtest/stm32l4x5_gpio-test.c | 59 +++++++++++++++++++++++---------------- |
| 56 | hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input | 44 | 5 files changed, 68 insertions(+), 36 deletions(-) |
| 57 | hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary | ||
| 58 | 45 | ||
| 59 | Richard Henderson (1): | ||
| 60 | target/arm: Fix neon VTBL/VTBX for len > 1 | ||
| 61 | |||
| 62 | Xinhao Zhang (3): | ||
| 63 | target/arm: add spaces around operator | ||
| 64 | target/arm: Don't use '#' flag of printf format | ||
| 65 | target/arm: add space before the open parenthesis '(' | ||
| 66 | |||
| 67 | docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++ | ||
| 68 | docs/system/target-arm.rst | 1 + | ||
| 69 | include/hw/misc/stm32f2xx_syscfg.h | 2 -- | ||
| 70 | target/arm/helper.h | 2 +- | ||
| 71 | hw/arm/armsse.c | 3 +- | ||
| 72 | hw/arm/musicpal.c | 40 +++++++++++++++++---------- | ||
| 73 | hw/arm/nseries.c | 26 ++++++++---------- | ||
| 74 | hw/arm/stm32f205_soc.c | 1 - | ||
| 75 | hw/misc/stm32f2xx_syscfg.c | 2 -- | ||
| 76 | hw/ssi/imx_spi.c | 2 +- | ||
| 77 | hw/ssi/xilinx_spi.c | 2 +- | ||
| 78 | target/arm/arch_dump.c | 8 +++--- | ||
| 79 | target/arm/arm-semi.c | 8 +++--- | ||
| 80 | target/arm/helper.c | 2 +- | ||
| 81 | target/arm/op_helper.c | 23 +++++++++------- | ||
| 82 | target/arm/translate-a64.c | 4 +-- | ||
| 83 | target/arm/translate.c | 2 +- | ||
| 84 | tests/qtest/npcm7xx_rng-test.c | 2 +- | ||
| 85 | hw/arm/Kconfig | 3 +- | ||
| 86 | target/arm/translate-neon.c.inc | 56 ++++++++++++++------------------------ | ||
| 87 | 20 files changed, 123 insertions(+), 98 deletions(-) | ||
| 88 | create mode 100644 docs/system/arm/sbsa.rst | ||
| 89 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Andrew Jones <drjones@redhat.com> | ||
| 2 | 1 | ||
| 3 | commit 32bd322a0134 ("hw/timer/armv7m_systick: Rewrite to use ptimers") | ||
| 4 | changed armv7m_systick to build on ptimers. Make sure we have ptimers | ||
| 5 | in the build when building armv7m_systick. | ||
| 6 | |||
| 7 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
| 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 9 | Message-id: 20201104103343.30392-1-drjones@redhat.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | hw/arm/Kconfig | 1 + | ||
| 13 | 1 file changed, 1 insertion(+) | ||
| 14 | |||
| 15 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/arm/Kconfig | ||
| 18 | +++ b/hw/arm/Kconfig | ||
| 19 | @@ -XXX,XX +XXX,XX @@ config ZYNQ | ||
| 20 | |||
| 21 | config ARM_V7M | ||
| 22 | bool | ||
| 23 | + select PTIMER | ||
| 24 | |||
| 25 | config ALLWINNER_A10 | ||
| 26 | bool | ||
| 27 | -- | ||
| 28 | 2.20.1 | ||
| 29 | |||
| 30 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: AlexChen <alex.chen@huawei.com> | ||
| 2 | 1 | ||
| 3 | We should use printf format specifier "%u" instead of "%d" for | ||
| 4 | argument of type "unsigned int". | ||
| 5 | |||
| 6 | Reported-by: Euler Robot <euler.robot@huawei.com> | ||
| 7 | Signed-off-by: Alex Chen <alex.chen@huawei.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-id: 5FA280F5.8060902@huawei.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | hw/ssi/imx_spi.c | 2 +- | ||
| 13 | hw/ssi/xilinx_spi.c | 2 +- | ||
| 14 | 2 files changed, 2 insertions(+), 2 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/hw/ssi/imx_spi.c | ||
| 19 | +++ b/hw/ssi/imx_spi.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static const char *imx_spi_reg_name(uint32_t reg) | ||
| 21 | case ECSPI_MSGDATA: | ||
| 22 | return "ECSPI_MSGDATA"; | ||
| 23 | default: | ||
| 24 | - sprintf(unknown, "%d ?", reg); | ||
| 25 | + sprintf(unknown, "%u ?", reg); | ||
| 26 | return unknown; | ||
| 27 | } | ||
| 28 | } | ||
| 29 | diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c | ||
| 30 | index XXXXXXX..XXXXXXX 100644 | ||
| 31 | --- a/hw/ssi/xilinx_spi.c | ||
| 32 | +++ b/hw/ssi/xilinx_spi.c | ||
| 33 | @@ -XXX,XX +XXX,XX @@ static void xlx_spi_update_irq(XilinxSPI *s) | ||
| 34 | irq chain unless things really changed. */ | ||
| 35 | if (pending != s->irqline) { | ||
| 36 | s->irqline = pending; | ||
| 37 | - DB_PRINT("irq_change of state %d ISR:%x IER:%X\n", | ||
| 38 | + DB_PRINT("irq_change of state %u ISR:%x IER:%X\n", | ||
| 39 | pending, s->regs[R_IPISR], s->regs[R_IPIER]); | ||
| 40 | qemu_set_irq(s->irq, pending); | ||
| 41 | } | ||
| 42 | -- | ||
| 43 | 2.20.1 | ||
| 44 | |||
| 45 | diff view generated by jsdifflib |
| 1 | From: Havard Skinnemoen <hskinnemoen@google.com> | 1 | The HSTR_EL2 register allows the hypervisor to trap AArch32 EL1 and |
|---|---|---|---|
| 2 | EL0 accesses to cp15 registers. We incorrectly implemented this so | ||
| 3 | they trap to EL1 when we detect the need for a HSTR trap at code | ||
| 4 | generation time. (The check in access_check_cp_reg() which we do at | ||
| 5 | runtime to catch traps from EL0 is correctly routing them to EL2.) | ||
| 2 | 6 | ||
| 3 | The number of runs is equal to the number of 0-1 and 1-0 transitions, | 7 | Use the correct target EL when generating the code to take the trap. |
| 4 | plus one. Currently, it's counting the number of times these transitions | ||
| 5 | do _not_ happen, plus one. | ||
| 6 | 8 | ||
| 7 | Source: | 9 | Cc: qemu-stable@nongnu.org |
| 8 | https://nvlpubs.nist.gov/nistpubs/Legacy/SP/nistspecialpublication800-22r1a.pdf | 10 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2226 |
| 9 | section 2.3.4 point (3). | 11 | Fixes: 049edada5e93df ("target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1") |
| 10 | |||
| 11 | Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> | ||
| 12 | Message-id: 20201103011457.2959989-2-hskinnemoen@google.com | ||
| 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Message-id: 20240325133116.2075362-1-peter.maydell@linaro.org | ||
| 15 | --- | 15 | --- |
| 16 | tests/qtest/npcm7xx_rng-test.c | 2 +- | 16 | target/arm/tcg/translate.c | 2 +- |
| 17 | 1 file changed, 1 insertion(+), 1 deletion(-) | 17 | 1 file changed, 1 insertion(+), 1 deletion(-) |
| 18 | 18 | ||
| 19 | diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c | 19 | diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c |
| 20 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/tests/qtest/npcm7xx_rng-test.c | 21 | --- a/target/arm/tcg/translate.c |
| 22 | +++ b/tests/qtest/npcm7xx_rng-test.c | 22 | +++ b/target/arm/tcg/translate.c |
| 23 | @@ -XXX,XX +XXX,XX @@ static double calc_runs_p(const unsigned long *buf, unsigned int nr_bits) | 23 | @@ -XXX,XX +XXX,XX @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, |
| 24 | pi = (double)nr_ones / nr_bits; | 24 | tcg_gen_andi_i32(t, t, 1u << maskbit); |
| 25 | 25 | tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); | |
| 26 | for (k = 0; k < nr_bits - 1; k++) { | 26 | |
| 27 | - vn_obs += !(test_bit(k, buf) ^ test_bit(k + 1, buf)); | 27 | - gen_exception_insn(s, 0, EXCP_UDEF, syndrome); |
| 28 | + vn_obs += (test_bit(k, buf) ^ test_bit(k + 1, buf)); | 28 | + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); |
| 29 | } | 29 | /* |
| 30 | vn_obs += 1; | 30 | * gen_exception_insn() will set is_jmp to DISAS_NORETURN, |
| 31 | 31 | * but since we're conditionally branching over it, we want | |
| 32 | -- | 32 | -- |
| 33 | 2.20.1 | 33 | 2.34.1 |
| 34 | |||
| 35 | diff view generated by jsdifflib |
| 1 | From: Alex Bennée <alex.bennee@linaro.org> | 1 | From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | We should at least document what this machine is about. | 3 | Hardware of sbsa-ref board is nowadays defined by both BSA and SBSA |
| 4 | specifications. Then BBR defines firmware interface. | ||
| 4 | 5 | ||
| 5 | Reviewed-by: Graeme Gregory <graeme@nuviainc.com> | 6 | Added note about DeviceTree data passed from QEMU to firmware. It is |
| 6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 7 | very minimal and provides only data we use in firmware. |
| 7 | Message-id: 20201104165254.24822-1-alex.bennee@linaro.org | 8 | |
| 8 | Cc: Leif Lindholm <leif@nuviainc.com> | 9 | Added NUMA information to list of things reported by DeviceTree. |
| 9 | Cc: Shashi Mallela <shashi.mallela@linaro.org> | 10 | |
| 10 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | 11 | Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
| 11 | [PMM: fixed filename mismatch] | 12 | Message-id: 20240328163851.1386176-1-marcin.juszkiewicz@linaro.org |
| 13 | Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> | ||
| 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 13 | --- | 15 | --- |
| 14 | docs/system/arm/sbsa.rst | 32 ++++++++++++++++++++++++++++++++ | 16 | docs/system/arm/sbsa.rst | 35 ++++++++++++++++++++++++++--------- |
| 15 | docs/system/target-arm.rst | 1 + | 17 | 1 file changed, 26 insertions(+), 9 deletions(-) |
| 16 | 2 files changed, 33 insertions(+) | ||
| 17 | create mode 100644 docs/system/arm/sbsa.rst | ||
| 18 | 18 | ||
| 19 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst | 19 | diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst |
| 20 | new file mode 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
| 21 | index XXXXXXX..XXXXXXX | 21 | --- a/docs/system/arm/sbsa.rst |
| 22 | --- /dev/null | ||
| 23 | +++ b/docs/system/arm/sbsa.rst | 22 | +++ b/docs/system/arm/sbsa.rst |
| 24 | @@ -XXX,XX +XXX,XX @@ | 23 | @@ -XXX,XX +XXX,XX @@ |
| 25 | +Arm Server Base System Architecture Reference board (``sbsa-ref``) | 24 | Arm Server Base System Architecture Reference board (``sbsa-ref``) |
| 26 | +================================================================== | 25 | ================================================================== |
| 26 | |||
| 27 | -While the ``virt`` board is a generic board platform that doesn't match | ||
| 28 | -any real hardware the ``sbsa-ref`` board intends to look like real | ||
| 29 | -hardware. The `Server Base System Architecture | ||
| 30 | -<https://developer.arm.com/documentation/den0029/latest>`_ defines a | ||
| 31 | -minimum base line of hardware support and importantly how the firmware | ||
| 32 | -reports that to any operating system. | ||
| 33 | +The ``sbsa-ref`` board intends to look like real hardware (while the ``virt`` | ||
| 34 | +board is a generic board platform that doesn't match any real hardware). | ||
| 27 | + | 35 | + |
| 28 | +While the `virt` board is a generic board platform that doesn't match | 36 | +The hardware part is defined by two specifications: |
| 29 | +any real hardware the `sbsa-ref` board intends to look like real | ||
| 30 | +hardware. The `Server Base System Architecture | ||
| 31 | +<https://developer.arm.com/documentation/den0029/latest>` defines a | ||
| 32 | +minimum base line of hardware support and importantly how the firmware | ||
| 33 | +reports that to any operating system. It is a static system that | ||
| 34 | +reports a very minimal DT to the firmware for non-discoverable | ||
| 35 | +information about components affected by the qemu command line (i.e. | ||
| 36 | +cpus and memory). As a result it must have a firmware specifically | ||
| 37 | +built to expect a certain hardware layout (as you would in a real | ||
| 38 | +machine). | ||
| 39 | + | 37 | + |
| 40 | +It is intended to be a machine for developing firmware and testing | 38 | + - `Base System Architecture <https://developer.arm.com/documentation/den0094/>`__ (BSA) |
| 41 | +standards compliance with operating systems. | 39 | + - `Server Base System Architecture <https://developer.arm.com/documentation/den0029/>`__ (SBSA) |
| 42 | + | 40 | + |
| 43 | +Supported devices | 41 | +The `Arm Base Boot Requirements <https://developer.arm.com/documentation/den0044/>`__ (BBR) |
| 44 | +""""""""""""""""" | 42 | +specification defines how the firmware reports that to any operating system. |
| 43 | |||
| 44 | It is intended to be a machine for developing firmware and testing | ||
| 45 | standards compliance with operating systems. | ||
| 46 | @@ -XXX,XX +XXX,XX @@ includes both internal hardware and parts affected by the qemu command line | ||
| 47 | (i.e. CPUs and memory). As a result it must have a firmware specifically built | ||
| 48 | to expect a certain hardware layout (as you would in a real machine). | ||
| 49 | |||
| 50 | +Note | ||
| 51 | +'''' | ||
| 45 | + | 52 | + |
| 46 | +The sbsa-ref board supports: | 53 | +QEMU provides the guest EL3 firmware with minimal information about hardware |
| 54 | +platform using minimalistic devicetree. This is not a Linux devicetree. It is | ||
| 55 | +not even a firmware devicetree. | ||
| 47 | + | 56 | + |
| 48 | + - A configurable number of AArch64 CPUs | 57 | +It is information passed from QEMU to describe the information a hardware |
| 49 | + - GIC version 3 | 58 | +platform would have other mechanisms to discover at runtime, that are affected |
| 50 | + - System bus AHCI controller | 59 | +by the QEMU command line. |
| 51 | + - System bus EHCI controller | ||
| 52 | + - CDROM and hard disc on AHCI bus | ||
| 53 | + - E1000E ethernet card on PCIe bus | ||
| 54 | + - VGA display adaptor on PCIe bus | ||
| 55 | + - A generic SBSA watchdog device | ||
| 56 | + | 60 | + |
| 57 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | 61 | +Ultimately this devicetree may be replaced by IPC calls to an emulated SCP. |
| 58 | index XXXXXXX..XXXXXXX 100644 | 62 | + |
| 59 | --- a/docs/system/target-arm.rst | 63 | DeviceTree information |
| 60 | +++ b/docs/system/target-arm.rst | 64 | '''''''''''''''''''''' |
| 61 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running | 65 | |
| 62 | arm/mps2 | 66 | -The devicetree provided by the board model to the firmware is not intended |
| 63 | arm/musca | 67 | -to be a complete compliant DT. It currently reports: |
| 64 | arm/realview | 68 | +The devicetree reports: |
| 65 | + arm/sbsa | 69 | |
| 66 | arm/versatile | 70 | - CPUs |
| 67 | arm/vexpress | 71 | - memory |
| 68 | arm/aspeed | 72 | - platform version |
| 73 | - GIC addresses | ||
| 74 | + - NUMA node id for CPUs and memory | ||
| 75 | |||
| 76 | Platform version | ||
| 77 | '''''''''''''''' | ||
| 78 | @@ -XXX,XX +XXX,XX @@ Platform version changes: | ||
| 79 | GIC ITS information is present in devicetree. | ||
| 80 | |||
| 81 | 0.3 | ||
| 82 | - The USB controller is an XHCI device, not EHCI | ||
| 83 | + The USB controller is an XHCI device, not EHCI. | ||
| 69 | -- | 84 | -- |
| 70 | 2.20.1 | 85 | 2.34.1 |
| 71 | |||
| 72 | diff view generated by jsdifflib |
| 1 | Checks for UNDEF cases should go before the "is VFP enabled?" access | 1 | If the group of the highest priority pending interrupt is disabled |
|---|---|---|---|
| 2 | check, except in special cases. Move a stray UNDEF check in the VTBL | 2 | via ICC_IGRPEN*, the ICC_HPPIR* registers should return |
| 3 | trans function up above the access check. | 3 | INTID_SPURIOUS, not the interrupt ID. (See the GIC architecture |
| 4 | specification pseudocode functions ICC_HPPIR1_EL1[] and | ||
| 5 | HighestPriorityPendingInterrupt().) | ||
| 4 | 6 | ||
| 7 | Make HPPIR reads honour the group disable, the way we already do | ||
| 8 | when determining whether to preempt in icc_hppi_can_preempt(). | ||
| 9 | |||
| 10 | Cc: qemu-stable@nongnu.org | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | Message-id: 20201109145324.2859-1-peter.maydell@linaro.org | 13 | Message-id: 20240328153333.2522667-1-peter.maydell@linaro.org |
| 8 | --- | 14 | --- |
| 9 | target/arm/translate-neon.c.inc | 8 ++++---- | 15 | hw/intc/arm_gicv3_cpuif.c | 4 ++-- |
| 10 | 1 file changed, 4 insertions(+), 4 deletions(-) | 16 | 1 file changed, 2 insertions(+), 2 deletions(-) |
| 11 | 17 | ||
| 12 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | 18 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c |
| 13 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/target/arm/translate-neon.c.inc | 20 | --- a/hw/intc/arm_gicv3_cpuif.c |
| 15 | +++ b/target/arm/translate-neon.c.inc | 21 | +++ b/hw/intc/arm_gicv3_cpuif.c |
| 16 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | 22 | @@ -XXX,XX +XXX,XX @@ static uint64_t icc_hppir0_value(GICv3CPUState *cs, CPUARMState *env) |
| 17 | return false; | 23 | */ |
| 24 | bool irq_is_secure; | ||
| 25 | |||
| 26 | - if (cs->hppi.prio == 0xff) { | ||
| 27 | + if (icc_no_enabled_hppi(cs)) { | ||
| 28 | return INTID_SPURIOUS; | ||
| 18 | } | 29 | } |
| 19 | 30 | ||
| 20 | - if (!vfp_access_check(s)) { | 31 | @@ -XXX,XX +XXX,XX @@ static uint64_t icc_hppir1_value(GICv3CPUState *cs, CPUARMState *env) |
| 21 | - return true; | 32 | */ |
| 22 | - } | 33 | bool irq_is_secure; |
| 23 | - | 34 | |
| 24 | if ((a->vn + a->len + 1) > 32) { | 35 | - if (cs->hppi.prio == 0xff) { |
| 25 | /* | 36 | + if (icc_no_enabled_hppi(cs)) { |
| 26 | * This is UNPREDICTABLE; we choose to UNDEF to avoid the | 37 | return INTID_SPURIOUS; |
| 27 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
| 28 | return false; | ||
| 29 | } | 38 | } |
| 30 | 39 | ||
| 31 | + if (!vfp_access_check(s)) { | ||
| 32 | + return true; | ||
| 33 | + } | ||
| 34 | + | ||
| 35 | desc = tcg_const_i32((a->vn << 2) | a->len); | ||
| 36 | def = tcg_temp_new_i64(); | ||
| 37 | if (a->op) { | ||
| 38 | -- | 40 | -- |
| 39 | 2.20.1 | 41 | 2.34.1 |
| 40 | |||
| 41 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Cédric Le Goater <clg@redhat.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The system configuration controller (SYSCFG) doesn't have | 3 | The test mangles the GPIO address and the pin number in the |
| 4 | any output IRQ (and the INTC input #71 belongs to the UART6). | 4 | qtest_add_data_func data parameter. Doing so, it assumes that the host |
| 5 | Remove the invalid code. | 5 | pointer size is always 64-bit, which breaks on 32-bit : |
| 6 | 6 | ||
| 7 | Fixes: db635521a02 ("stm32f205: Add the stm32f205 SoC") | 7 | ../tests/qtest/stm32l4x5_gpio-test.c: In function ‘test_gpio_output_mode’: |
| 8 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | ../tests/qtest/stm32l4x5_gpio-test.c:272:25: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] |
| 9 | Message-id: 20201107193403.436146-3-f4bug@amsat.org | 9 | 272 | unsigned int pin = ((uint64_t)data) & 0xF; |
| 10 | | ^ | ||
| 11 | ../tests/qtest/stm32l4x5_gpio-test.c:273:22: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast] | ||
| 12 | 273 | uint32_t gpio = ((uint64_t)data) >> 32; | ||
| 13 | | ^ | ||
| 14 | |||
| 15 | To fix, improve the mangling of the GPIO address and pin number fields | ||
| 16 | by using GPIO_SIZE so that the resulting value fits in a 32-bit pointer. | ||
| 17 | While at it, include some helpers to hide the details. | ||
| 18 | |||
| 19 | Cc: Arnaud Minier <arnaud.minier@telecom-paris.fr> | ||
| 20 | Cc: Inès Varhol <ines.varhol@telecom-paris.fr> | ||
| 21 | Signed-off-by: Cédric Le Goater <clg@redhat.com> | ||
| 22 | Message-id: 20240329092747.298259-1-clg@redhat.com | ||
| 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 23 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | --- | 25 | --- |
| 13 | include/hw/misc/stm32f2xx_syscfg.h | 2 -- | 26 | tests/qtest/stm32l4x5_gpio-test.c | 59 ++++++++++++++++++------------- |
| 14 | hw/arm/stm32f205_soc.c | 1 - | 27 | 1 file changed, 35 insertions(+), 24 deletions(-) |
| 15 | hw/misc/stm32f2xx_syscfg.c | 2 -- | ||
| 16 | 3 files changed, 5 deletions(-) | ||
| 17 | 28 | ||
| 18 | diff --git a/include/hw/misc/stm32f2xx_syscfg.h b/include/hw/misc/stm32f2xx_syscfg.h | 29 | diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio-test.c |
| 19 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/include/hw/misc/stm32f2xx_syscfg.h | 31 | --- a/tests/qtest/stm32l4x5_gpio-test.c |
| 21 | +++ b/include/hw/misc/stm32f2xx_syscfg.h | 32 | +++ b/tests/qtest/stm32l4x5_gpio-test.c |
| 22 | @@ -XXX,XX +XXX,XX @@ struct STM32F2XXSyscfgState { | 33 | @@ -XXX,XX +XXX,XX @@ const uint32_t idr_reset[NUM_GPIOS] = { |
| 23 | uint32_t syscfg_exticr3; | 34 | 0x00000000 |
| 24 | uint32_t syscfg_exticr4; | ||
| 25 | uint32_t syscfg_cmpcr; | ||
| 26 | - | ||
| 27 | - qemu_irq irq; | ||
| 28 | }; | 35 | }; |
| 29 | 36 | ||
| 30 | #endif /* HW_STM32F2XX_SYSCFG_H */ | 37 | +#define PIN_MASK 0xF |
| 31 | diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c | 38 | +#define GPIO_ADDR_MASK (~(GPIO_SIZE - 1)) |
| 32 | index XXXXXXX..XXXXXXX 100644 | 39 | + |
| 33 | --- a/hw/arm/stm32f205_soc.c | 40 | +static inline void *test_data(uint32_t gpio_addr, uint8_t pin) |
| 34 | +++ b/hw/arm/stm32f205_soc.c | 41 | +{ |
| 35 | @@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) | 42 | + return (void *)(uintptr_t)((gpio_addr & GPIO_ADDR_MASK) | (pin & PIN_MASK)); |
| 36 | } | 43 | +} |
| 37 | busdev = SYS_BUS_DEVICE(dev); | 44 | + |
| 38 | sysbus_mmio_map(busdev, 0, 0x40013800); | 45 | +#define test_gpio_addr(data) ((uintptr_t)(data) & GPIO_ADDR_MASK) |
| 39 | - sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71)); | 46 | +#define test_pin(data) ((uintptr_t)(data) & PIN_MASK) |
| 40 | 47 | + | |
| 41 | /* Attach UART (uses USART registers) and USART controllers */ | 48 | static uint32_t gpio_readl(unsigned int gpio, unsigned int offset) |
| 42 | for (i = 0; i < STM_NUM_USARTS; i++) { | ||
| 43 | diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c | ||
| 44 | index XXXXXXX..XXXXXXX 100644 | ||
| 45 | --- a/hw/misc/stm32f2xx_syscfg.c | ||
| 46 | +++ b/hw/misc/stm32f2xx_syscfg.c | ||
| 47 | @@ -XXX,XX +XXX,XX @@ static void stm32f2xx_syscfg_init(Object *obj) | ||
| 48 | { | 49 | { |
| 49 | STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj); | 50 | return readl(gpio + offset); |
| 50 | 51 | @@ -XXX,XX +XXX,XX @@ static void test_gpio_output_mode(const void *data) | |
| 51 | - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); | 52 | * Additionally, it checks that values written to ODR |
| 52 | - | 53 | * when not in output mode are stored and not discarded. |
| 53 | memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s, | 54 | */ |
| 54 | TYPE_STM32F2XX_SYSCFG, 0x400); | 55 | - unsigned int pin = ((uint64_t)data) & 0xF; |
| 55 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); | 56 | - uint32_t gpio = ((uint64_t)data) >> 32; |
| 57 | + unsigned int pin = test_pin(data); | ||
| 58 | + uint32_t gpio = test_gpio_addr(data); | ||
| 59 | unsigned int gpio_id = get_gpio_id(gpio); | ||
| 60 | |||
| 61 | qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); | ||
| 62 | @@ -XXX,XX +XXX,XX @@ static void test_gpio_input_mode(const void *data) | ||
| 63 | * corresponding GPIO line high/low : it should set the | ||
| 64 | * right bit in IDR and send an irq to syscfg. | ||
| 65 | */ | ||
| 66 | - unsigned int pin = ((uint64_t)data) & 0xF; | ||
| 67 | - uint32_t gpio = ((uint64_t)data) >> 32; | ||
| 68 | + unsigned int pin = test_pin(data); | ||
| 69 | + uint32_t gpio = test_gpio_addr(data); | ||
| 70 | unsigned int gpio_id = get_gpio_id(gpio); | ||
| 71 | |||
| 72 | qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); | ||
| 73 | @@ -XXX,XX +XXX,XX @@ static void test_pull_up_pull_down(const void *data) | ||
| 74 | * Test that a floating pin with pull-up sets the pin | ||
| 75 | * high and vice-versa. | ||
| 76 | */ | ||
| 77 | - unsigned int pin = ((uint64_t)data) & 0xF; | ||
| 78 | - uint32_t gpio = ((uint64_t)data) >> 32; | ||
| 79 | + unsigned int pin = test_pin(data); | ||
| 80 | + uint32_t gpio = test_gpio_addr(data); | ||
| 81 | unsigned int gpio_id = get_gpio_id(gpio); | ||
| 82 | |||
| 83 | qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); | ||
| 84 | @@ -XXX,XX +XXX,XX @@ static void test_push_pull(const void *data) | ||
| 85 | * disconnects the pin, that the pin can't be set or reset | ||
| 86 | * externally afterwards. | ||
| 87 | */ | ||
| 88 | - unsigned int pin = ((uint64_t)data) & 0xF; | ||
| 89 | - uint32_t gpio = ((uint64_t)data) >> 32; | ||
| 90 | + unsigned int pin = test_pin(data); | ||
| 91 | + uint32_t gpio = test_gpio_addr(data); | ||
| 92 | uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio); | ||
| 93 | |||
| 94 | qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); | ||
| 95 | @@ -XXX,XX +XXX,XX @@ static void test_open_drain(const void *data) | ||
| 96 | * However a pin set low externally shouldn't be disconnected, | ||
| 97 | * and it can be set low externally when in open-drain mode. | ||
| 98 | */ | ||
| 99 | - unsigned int pin = ((uint64_t)data) & 0xF; | ||
| 100 | - uint32_t gpio = ((uint64_t)data) >> 32; | ||
| 101 | + unsigned int pin = test_pin(data); | ||
| 102 | + uint32_t gpio = test_gpio_addr(data); | ||
| 103 | uint32_t gpio2 = GPIO_BASE_ADDR + (GPIO_H - gpio); | ||
| 104 | |||
| 105 | qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); | ||
| 106 | @@ -XXX,XX +XXX,XX @@ static void test_bsrr_brr(const void *data) | ||
| 107 | * has the desired effect on ODR. | ||
| 108 | * In BSRR, BSx has priority over BRx. | ||
| 109 | */ | ||
| 110 | - unsigned int pin = ((uint64_t)data) & 0xF; | ||
| 111 | - uint32_t gpio = ((uint64_t)data) >> 32; | ||
| 112 | + unsigned int pin = test_pin(data); | ||
| 113 | + uint32_t gpio = test_gpio_addr(data); | ||
| 114 | |||
| 115 | gpio_writel(gpio, BSRR, (1 << pin)); | ||
| 116 | g_assert_cmphex(gpio_readl(gpio, ODR), ==, reset(gpio, ODR) | (1 << pin)); | ||
| 117 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv) | ||
| 118 | * is problematic since the pin was already high. | ||
| 119 | */ | ||
| 120 | qtest_add_data_func("stm32l4x5/gpio/test_gpioc5_output_mode", | ||
| 121 | - (void *)((uint64_t)GPIO_C << 32 | 5), | ||
| 122 | + test_data(GPIO_C, 5), | ||
| 123 | test_gpio_output_mode); | ||
| 124 | qtest_add_data_func("stm32l4x5/gpio/test_gpioh3_output_mode", | ||
| 125 | - (void *)((uint64_t)GPIO_H << 32 | 3), | ||
| 126 | + test_data(GPIO_H, 3), | ||
| 127 | test_gpio_output_mode); | ||
| 128 | qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode1", | ||
| 129 | - (void *)((uint64_t)GPIO_D << 32 | 6), | ||
| 130 | + test_data(GPIO_D, 6), | ||
| 131 | test_gpio_input_mode); | ||
| 132 | qtest_add_data_func("stm32l4x5/gpio/test_gpio_input_mode2", | ||
| 133 | - (void *)((uint64_t)GPIO_C << 32 | 10), | ||
| 134 | + test_data(GPIO_C, 10), | ||
| 135 | test_gpio_input_mode); | ||
| 136 | qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down1", | ||
| 137 | - (void *)((uint64_t)GPIO_B << 32 | 5), | ||
| 138 | + test_data(GPIO_B, 5), | ||
| 139 | test_pull_up_pull_down); | ||
| 140 | qtest_add_data_func("stm32l4x5/gpio/test_gpio_pull_up_pull_down2", | ||
| 141 | - (void *)((uint64_t)GPIO_F << 32 | 1), | ||
| 142 | + test_data(GPIO_F, 1), | ||
| 143 | test_pull_up_pull_down); | ||
| 144 | qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull1", | ||
| 145 | - (void *)((uint64_t)GPIO_G << 32 | 6), | ||
| 146 | + test_data(GPIO_G, 6), | ||
| 147 | test_push_pull); | ||
| 148 | qtest_add_data_func("stm32l4x5/gpio/test_gpio_push_pull2", | ||
| 149 | - (void *)((uint64_t)GPIO_H << 32 | 3), | ||
| 150 | + test_data(GPIO_H, 3), | ||
| 151 | test_push_pull); | ||
| 152 | qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain1", | ||
| 153 | - (void *)((uint64_t)GPIO_C << 32 | 4), | ||
| 154 | + test_data(GPIO_C, 4), | ||
| 155 | test_open_drain); | ||
| 156 | qtest_add_data_func("stm32l4x5/gpio/test_gpio_open_drain2", | ||
| 157 | - (void *)((uint64_t)GPIO_E << 32 | 11), | ||
| 158 | + test_data(GPIO_E, 11), | ||
| 159 | test_open_drain); | ||
| 160 | qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr1", | ||
| 161 | - (void *)((uint64_t)GPIO_A << 32 | 12), | ||
| 162 | + test_data(GPIO_A, 12), | ||
| 163 | test_bsrr_brr); | ||
| 164 | qtest_add_data_func("stm32l4x5/gpio/test_bsrr_brr2", | ||
| 165 | - (void *)((uint64_t)GPIO_D << 32 | 0), | ||
| 166 | + test_data(GPIO_D, 0), | ||
| 167 | test_bsrr_brr); | ||
| 168 | |||
| 169 | qtest_start("-machine b-l475e-iot01a"); | ||
| 56 | -- | 170 | -- |
| 57 | 2.20.1 | 171 | 2.34.1 |
| 58 | 172 | ||
| 59 | 173 | diff view generated by jsdifflib |
| 1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> | 1 | From: Cédric Le Goater <clg@redhat.com> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Fix code style. Operator needs spaces both sides. | 3 | Change the board revision number and RAM size to 1Gb on 32-bit hosts. |
| 4 | On these systems, RAM has a 2047 MB limit and this breaks the tests. | ||
| 4 | 5 | ||
| 5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> | 6 | Fixes: 7785e8ea2204 ("hw/arm: Introduce Raspberry PI 4 machine") |
| 6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | 7 | Signed-off-by: Cédric Le Goater <clg@redhat.com> |
| 7 | Message-id: 20201103114529.638233-1-zhangxinhao1@huawei.com | 8 | Message-id: 20240329150155.357043-1-clg@redhat.com |
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | --- | 11 | --- |
| 11 | target/arm/arch_dump.c | 8 ++++---- | 12 | hw/arm/raspi4b.c | 4 ++++ |
| 12 | target/arm/arm-semi.c | 8 ++++---- | 13 | 1 file changed, 4 insertions(+) |
| 13 | target/arm/helper.c | 2 +- | ||
| 14 | 3 files changed, 9 insertions(+), 9 deletions(-) | ||
| 15 | 14 | ||
| 16 | diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c | 15 | diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/target/arm/arch_dump.c | 17 | --- a/hw/arm/raspi4b.c |
| 19 | +++ b/target/arm/arch_dump.c | 18 | +++ b/hw/arm/raspi4b.c |
| 20 | @@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, | 19 | @@ -XXX,XX +XXX,XX @@ static void raspi4b_machine_class_init(ObjectClass *oc, void *data) |
| 21 | 20 | MachineClass *mc = MACHINE_CLASS(oc); | |
| 22 | for (i = 0; i < 32; ++i) { | 21 | RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc); |
| 23 | uint64_t *q = aa64_vfp_qreg(env, i); | 22 | |
| 24 | - note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]); | 23 | +#if HOST_LONG_BITS == 32 |
| 25 | - note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]); | 24 | + rmc->board_rev = 0xa03111; /* Revision 1.1, 1 Gb RAM */ |
| 26 | + note.vfp.vregs[2 * i + 0] = cpu_to_dump64(s, q[0]); | 25 | +#else |
| 27 | + note.vfp.vregs[2 * i + 1] = cpu_to_dump64(s, q[1]); | 26 | rmc->board_rev = 0xb03115; /* Revision 1.5, 2 Gb RAM */ |
| 28 | } | 27 | +#endif |
| 29 | 28 | raspi_machine_class_common_init(mc, rmc->board_rev); | |
| 30 | if (s->dump_info.d_endian == ELFDATA2MSB) { | 29 | mc->init = raspi4b_machine_init; |
| 31 | @@ -XXX,XX +XXX,XX @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, | ||
| 32 | */ | ||
| 33 | for (i = 0; i < 32; ++i) { | ||
| 34 | uint64_t tmp = note.vfp.vregs[2*i]; | ||
| 35 | - note.vfp.vregs[2*i] = note.vfp.vregs[2*i+1]; | ||
| 36 | - note.vfp.vregs[2*i+1] = tmp; | ||
| 37 | + note.vfp.vregs[2 * i] = note.vfp.vregs[2 * i + 1]; | ||
| 38 | + note.vfp.vregs[2 * i + 1] = tmp; | ||
| 39 | } | ||
| 40 | } | ||
| 41 | |||
| 42 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | ||
| 43 | index XXXXXXX..XXXXXXX 100644 | ||
| 44 | --- a/target/arm/arm-semi.c | ||
| 45 | +++ b/target/arm/arm-semi.c | ||
| 46 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 47 | if (use_gdb_syscalls()) { | ||
| 48 | arm_semi_open_guestfd = guestfd; | ||
| 49 | ret = arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4", arg0, | ||
| 50 | - (int)arg2+1, gdb_open_modeflags[arg1]); | ||
| 51 | + (int)arg2 + 1, gdb_open_modeflags[arg1]); | ||
| 52 | } else { | ||
| 53 | ret = set_swi_errno(env, open(s, open_modeflags[arg1], 0644)); | ||
| 54 | if (ret == (uint32_t)-1) { | ||
| 55 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 56 | GET_ARG(1); | ||
| 57 | if (use_gdb_syscalls()) { | ||
| 58 | ret = arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s", | ||
| 59 | - arg0, (int)arg1+1); | ||
| 60 | + arg0, (int)arg1 + 1); | ||
| 61 | } else { | ||
| 62 | s = lock_user_string(arg0); | ||
| 63 | if (!s) { | ||
| 64 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 65 | GET_ARG(3); | ||
| 66 | if (use_gdb_syscalls()) { | ||
| 67 | return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s", | ||
| 68 | - arg0, (int)arg1+1, arg2, (int)arg3+1); | ||
| 69 | + arg0, (int)arg1 + 1, arg2, (int)arg3 + 1); | ||
| 70 | } else { | ||
| 71 | char *s2; | ||
| 72 | s = lock_user_string(arg0); | ||
| 73 | @@ -XXX,XX +XXX,XX @@ target_ulong do_arm_semihosting(CPUARMState *env) | ||
| 74 | GET_ARG(1); | ||
| 75 | if (use_gdb_syscalls()) { | ||
| 76 | return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s", | ||
| 77 | - arg0, (int)arg1+1); | ||
| 78 | + arg0, (int)arg1 + 1); | ||
| 79 | } else { | ||
| 80 | s = lock_user_string(arg0); | ||
| 81 | if (!s) { | ||
| 82 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 83 | index XXXXXXX..XXXXXXX 100644 | ||
| 84 | --- a/target/arm/helper.c | ||
| 85 | +++ b/target/arm/helper.c | ||
| 86 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(usad8)(uint32_t a, uint32_t b) | ||
| 87 | uint32_t sum; | ||
| 88 | sum = do_usad(a, b); | ||
| 89 | sum += do_usad(a >> 8, b >> 8); | ||
| 90 | - sum += do_usad(a >> 16, b >>16); | ||
| 91 | + sum += do_usad(a >> 16, b >> 16); | ||
| 92 | sum += do_usad(a >> 24, b >> 24); | ||
| 93 | return sum; | ||
| 94 | } | 30 | } |
| 95 | -- | 31 | -- |
| 96 | 2.20.1 | 32 | 2.34.1 |
| 97 | 33 | ||
| 98 | 34 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> | ||
| 2 | 1 | ||
| 3 | Fix code style. Don't use '#' flag of printf format ('%#') in | ||
| 4 | format strings, use '0x' prefix instead | ||
| 5 | |||
| 6 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> | ||
| 7 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | ||
| 8 | Message-id: 20201103114529.638233-2-zhangxinhao1@huawei.com | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/translate-a64.c | 4 ++-- | ||
| 13 | 1 file changed, 2 insertions(+), 2 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/target/arm/translate-a64.c | ||
| 18 | +++ b/target/arm/translate-a64.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) | ||
| 20 | gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst); | ||
| 21 | break; | ||
| 22 | default: | ||
| 23 | - fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", | ||
| 24 | + fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64 "\n", | ||
| 25 | __func__, insn, fpopcode, s->pc_curr); | ||
| 26 | g_assert_not_reached(); | ||
| 27 | } | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) | ||
| 29 | case 0x7f: /* FSQRT (vector) */ | ||
| 30 | break; | ||
| 31 | default: | ||
| 32 | - fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop); | ||
| 33 | + fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fpop); | ||
| 34 | g_assert_not_reached(); | ||
| 35 | } | ||
| 36 | |||
| 37 | -- | ||
| 38 | 2.20.1 | ||
| 39 | |||
| 40 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Xinhao Zhang <zhangxinhao1@huawei.com> | ||
| 2 | 1 | ||
| 3 | Fix code style. Space required before the open parenthesis '('. | ||
| 4 | |||
| 5 | Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com> | ||
| 6 | Signed-off-by: Kai Deng <dengkai1@huawei.com> | ||
| 7 | Message-id: 20201103114529.638233-3-zhangxinhao1@huawei.com | ||
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | --- | ||
| 11 | target/arm/translate.c | 2 +- | ||
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/translate.c | ||
| 17 | +++ b/target/arm/translate.c | ||
| 18 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) | ||
| 19 | - Hardware watchpoints. | ||
| 20 | Hardware breakpoints have already been handled and skip this code. | ||
| 21 | */ | ||
| 22 | - switch(dc->base.is_jmp) { | ||
| 23 | + switch (dc->base.is_jmp) { | ||
| 24 | case DISAS_NEXT: | ||
| 25 | case DISAS_TOO_MANY: | ||
| 26 | gen_goto_tb(dc, 1, dc->base.pc_next); | ||
| 27 | -- | ||
| 28 | 2.20.1 | ||
| 29 | |||
| 30 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 2 | 1 | ||
| 3 | When using a Cortex-A15, the Virt machine does not use any | ||
| 4 | MPCore peripherals. Remove the dependency. | ||
| 5 | |||
| 6 | Fixes: 7951c7b7c05 ("hw/arm: Express dependencies of the virt machine with Kconfig") | ||
| 7 | Reported-by: Miroslav Rezanina <mrezanin@redhat.com> | ||
| 8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
| 9 | Message-id: 20201107114852.271922-1-philmd@redhat.com | ||
| 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | --- | ||
| 13 | hw/arm/Kconfig | 1 - | ||
| 14 | 1 file changed, 1 deletion(-) | ||
| 15 | |||
| 16 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/hw/arm/Kconfig | ||
| 19 | +++ b/hw/arm/Kconfig | ||
| 20 | @@ -XXX,XX +XXX,XX @@ config ARM_VIRT | ||
| 21 | imply VFIO_PLATFORM | ||
| 22 | imply VFIO_XGMAC | ||
| 23 | imply TPM_TIS_SYSBUS | ||
| 24 | - select A15MPCORE | ||
| 25 | select ACPI | ||
| 26 | select ARM_SMMUV3 | ||
| 27 | select GPIO_KEY | ||
| 28 | -- | ||
| 29 | 2.20.1 | ||
| 30 | |||
| 31 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
| 2 | 1 | ||
| 3 | The helper function did not get updated when we reorganized | ||
| 4 | the vector register file for SVE. Since then, the neon dregs | ||
| 5 | are non-sequential and cannot be simply indexed. | ||
| 6 | |||
| 7 | At the same time, make the helper function operate on 64-bit | ||
| 8 | quantities so that we do not have to call it twice. | ||
| 9 | |||
| 10 | Fixes: c39c2b9043e | ||
| 11 | Reported-by: Ard Biesheuvel <ardb@kernel.org> | ||
| 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | [PMM: use aa32_vfp_dreg() rather than opencoding] | ||
| 14 | Message-id: 20201105171126.88014-1-richard.henderson@linaro.org | ||
| 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 17 | --- | ||
| 18 | target/arm/helper.h | 2 +- | ||
| 19 | target/arm/op_helper.c | 23 +++++++++-------- | ||
| 20 | target/arm/translate-neon.c.inc | 44 +++++++++++---------------------- | ||
| 21 | 3 files changed, 29 insertions(+), 40 deletions(-) | ||
| 22 | |||
| 23 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
| 24 | index XXXXXXX..XXXXXXX 100644 | ||
| 25 | --- a/target/arm/helper.h | ||
| 26 | +++ b/target/arm/helper.h | ||
| 27 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) | ||
| 28 | DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) | ||
| 29 | DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) | ||
| 30 | DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) | ||
| 31 | -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32) | ||
| 32 | +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) | ||
| 33 | |||
| 34 | DEF_HELPER_3(shl_cc, i32, env, i32, i32) | ||
| 35 | DEF_HELPER_3(shr_cc, i32, env, i32, i32) | ||
| 36 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
| 37 | index XXXXXXX..XXXXXXX 100644 | ||
| 38 | --- a/target/arm/op_helper.c | ||
| 39 | +++ b/target/arm/op_helper.c | ||
| 40 | @@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, | ||
| 41 | cpu_loop_exit_restore(cs, ra); | ||
| 42 | } | ||
| 43 | |||
| 44 | -uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, | ||
| 45 | - uint32_t maxindex) | ||
| 46 | +uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, | ||
| 47 | + uint64_t ireg, uint64_t def) | ||
| 48 | { | ||
| 49 | - uint32_t val, shift; | ||
| 50 | - uint64_t *table = vn; | ||
| 51 | + uint64_t tmp, val = 0; | ||
| 52 | + uint32_t maxindex = ((desc & 3) + 1) * 8; | ||
| 53 | + uint32_t base_reg = desc >> 2; | ||
| 54 | + uint32_t shift, index, reg; | ||
| 55 | |||
| 56 | - val = 0; | ||
| 57 | - for (shift = 0; shift < 32; shift += 8) { | ||
| 58 | - uint32_t index = (ireg >> shift) & 0xff; | ||
| 59 | + for (shift = 0; shift < 64; shift += 8) { | ||
| 60 | + index = (ireg >> shift) & 0xff; | ||
| 61 | if (index < maxindex) { | ||
| 62 | - uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; | ||
| 63 | - val |= tmp << shift; | ||
| 64 | + reg = base_reg + (index >> 3); | ||
| 65 | + tmp = *aa32_vfp_dreg(env, reg); | ||
| 66 | + tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift; | ||
| 67 | } else { | ||
| 68 | - val |= def & (0xff << shift); | ||
| 69 | + tmp = def & (0xffull << shift); | ||
| 70 | } | ||
| 71 | + val |= tmp; | ||
| 72 | } | ||
| 73 | return val; | ||
| 74 | } | ||
| 75 | diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc | ||
| 76 | index XXXXXXX..XXXXXXX 100644 | ||
| 77 | --- a/target/arm/translate-neon.c.inc | ||
| 78 | +++ b/target/arm/translate-neon.c.inc | ||
| 79 | @@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) | ||
| 80 | |||
| 81 | static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
| 82 | { | ||
| 83 | - int n; | ||
| 84 | - TCGv_i32 tmp, tmp2, tmp3, tmp4; | ||
| 85 | - TCGv_ptr ptr1; | ||
| 86 | + TCGv_i64 val, def; | ||
| 87 | + TCGv_i32 desc; | ||
| 88 | |||
| 89 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
| 90 | return false; | ||
| 91 | @@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) | ||
| 92 | return true; | ||
| 93 | } | ||
| 94 | |||
| 95 | - n = a->len + 1; | ||
| 96 | - if ((a->vn + n) > 32) { | ||
| 97 | + if ((a->vn + a->len + 1) > 32) { | ||
| 98 | /* | ||
| 99 | * This is UNPREDICTABLE; we choose to UNDEF to avoid the | ||
| 100 | * helper function running off the end of the register file. | ||
| 101 | */ | ||
| 102 | return false; | ||
| 103 | } | ||
| 104 | - n <<= 3; | ||
| 105 | - tmp = tcg_temp_new_i32(); | ||
| 106 | - if (a->op) { | ||
| 107 | - read_neon_element32(tmp, a->vd, 0, MO_32); | ||
| 108 | - } else { | ||
| 109 | - tcg_gen_movi_i32(tmp, 0); | ||
| 110 | - } | ||
| 111 | - tmp2 = tcg_temp_new_i32(); | ||
| 112 | - read_neon_element32(tmp2, a->vm, 0, MO_32); | ||
| 113 | - ptr1 = vfp_reg_ptr(true, a->vn); | ||
| 114 | - tmp4 = tcg_const_i32(n); | ||
| 115 | - gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); | ||
| 116 | |||
| 117 | + desc = tcg_const_i32((a->vn << 2) | a->len); | ||
| 118 | + def = tcg_temp_new_i64(); | ||
| 119 | if (a->op) { | ||
| 120 | - read_neon_element32(tmp, a->vd, 1, MO_32); | ||
| 121 | + read_neon_element64(def, a->vd, 0, MO_64); | ||
| 122 | } else { | ||
| 123 | - tcg_gen_movi_i32(tmp, 0); | ||
| 124 | + tcg_gen_movi_i64(def, 0); | ||
| 125 | } | ||
| 126 | - tmp3 = tcg_temp_new_i32(); | ||
| 127 | - read_neon_element32(tmp3, a->vm, 1, MO_32); | ||
| 128 | - gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); | ||
| 129 | - tcg_temp_free_i32(tmp); | ||
| 130 | - tcg_temp_free_i32(tmp4); | ||
| 131 | - tcg_temp_free_ptr(ptr1); | ||
| 132 | + val = tcg_temp_new_i64(); | ||
| 133 | + read_neon_element64(val, a->vm, 0, MO_64); | ||
| 134 | |||
| 135 | - write_neon_element32(tmp2, a->vd, 0, MO_32); | ||
| 136 | - write_neon_element32(tmp3, a->vd, 1, MO_32); | ||
| 137 | - tcg_temp_free_i32(tmp2); | ||
| 138 | - tcg_temp_free_i32(tmp3); | ||
| 139 | + gen_helper_neon_tbl(val, cpu_env, desc, val, def); | ||
| 140 | + write_neon_element64(val, a->vd, 0, MO_64); | ||
| 141 | + | ||
| 142 | + tcg_temp_free_i64(def); | ||
| 143 | + tcg_temp_free_i64(val); | ||
| 144 | + tcg_temp_free_i32(desc); | ||
| 145 | return true; | ||
| 146 | } | ||
| 147 | |||
| 148 | -- | ||
| 149 | 2.20.1 | ||
| 150 | |||
| 151 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 2 | 1 | ||
| 3 | We can use one MPC per SRAM bank, but we currently only wire the | ||
| 4 | IRQ from the first expansion MPC to the IRQ splitter. Fix that. | ||
| 5 | |||
| 6 | Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines") | ||
| 7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 8 | Message-id: 20201107193403.436146-2-f4bug@amsat.org | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | hw/arm/armsse.c | 3 ++- | ||
| 13 | 1 file changed, 2 insertions(+), 1 deletion(-) | ||
| 14 | |||
| 15 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/arm/armsse.c | ||
| 18 | +++ b/hw/arm/armsse.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) | ||
| 20 | qdev_get_gpio_in(dev_splitter, 0)); | ||
| 21 | qdev_connect_gpio_out(dev_splitter, 0, | ||
| 22 | qdev_get_gpio_in_named(dev_secctl, | ||
| 23 | - "mpc_status", 0)); | ||
| 24 | + "mpc_status", | ||
| 25 | + i - IOTS_NUM_EXP_MPC)); | ||
| 26 | } | ||
| 27 | |||
| 28 | qdev_connect_gpio_out(dev_splitter, 1, | ||
| 29 | -- | ||
| 30 | 2.20.1 | ||
| 31 | |||
| 32 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 2 | 1 | ||
| 3 | omap2420_mpu_init() introduced in commit 827df9f3c5f ("Add basic | ||
| 4 | OMAP2 chip support") takes care of creating the 3 UARTs. | ||
| 5 | |||
| 6 | Then commit 58a26b477e9 ("Emulate a serial bluetooth HCI with H4+ | ||
| 7 | extensions and attach to n8x0's UART") added n8x0_uart_setup() | ||
| 8 | which create the UART and connects it to an IRQ output, | ||
| 9 | overwritting the existing peripheral and its IRQ connection. | ||
| 10 | This is incorrect. | ||
| 11 | |||
| 12 | Fortunately we don't need to fix this, because commit 6da68df7f9b | ||
| 13 | ("hw/arm/nseries: Replace the bluetooth chardev with a "null" | ||
| 14 | chardev") removed the use of this peripheral. We can simply | ||
| 15 | remove the code. | ||
| 16 | |||
| 17 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 18 | Message-id: 20201107193403.436146-4-f4bug@amsat.org | ||
| 19 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 21 | --- | ||
| 22 | hw/arm/nseries.c | 11 ----------- | ||
| 23 | 1 file changed, 11 deletions(-) | ||
| 24 | |||
| 25 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | ||
| 27 | --- a/hw/arm/nseries.c | ||
| 28 | +++ b/hw/arm/nseries.c | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static void n8x0_cbus_setup(struct n800_s *s) | ||
| 30 | cbus_attach(cbus, s->tahvo = tahvo_init(tahvo_irq, 1)); | ||
| 31 | } | ||
| 32 | |||
| 33 | -static void n8x0_uart_setup(struct n800_s *s) | ||
| 34 | -{ | ||
| 35 | - Chardev *radio = qemu_chr_new("bt-dummy-uart", "null", NULL); | ||
| 36 | - /* | ||
| 37 | - * Note: We used to connect N8X0_BT_RESET_GPIO and N8X0_BT_WKUP_GPIO | ||
| 38 | - * here, but this code has been removed with the bluetooth backend. | ||
| 39 | - */ | ||
| 40 | - omap_uart_attach(s->mpu->uart[BT_UART], radio); | ||
| 41 | -} | ||
| 42 | - | ||
| 43 | static void n8x0_usb_setup(struct n800_s *s) | ||
| 44 | { | ||
| 45 | SysBusDevice *dev; | ||
| 46 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | ||
| 47 | n8x0_spi_setup(s); | ||
| 48 | n8x0_dss_setup(s); | ||
| 49 | n8x0_cbus_setup(s); | ||
| 50 | - n8x0_uart_setup(s); | ||
| 51 | if (machine_usb(machine)) { | ||
| 52 | n8x0_usb_setup(s); | ||
| 53 | } | ||
| 54 | -- | ||
| 55 | 2.20.1 | ||
| 56 | |||
| 57 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 2 | 1 | ||
| 3 | The MusicPal board code connects both of the IRQ outputs of the UART | ||
| 4 | to the same INTC qemu_irq. Connecting two qemu_irqs outputs directly | ||
| 5 | to the same input is not valid as it produces subtly wrong behaviour | ||
| 6 | (for instance if both the IRQ lines are high, and then one goes | ||
| 7 | low, the INTC input will see this as a high-to-low transition | ||
| 8 | even though the second IRQ line should still be holding it high). | ||
| 9 | |||
| 10 | This kind of wiring needs an explicitly created OR gate; add one. | ||
| 11 | |||
| 12 | Inspired-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 13 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 14 | Message-id: 20201107193403.436146-5-f4bug@amsat.org | ||
| 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 17 | --- | ||
| 18 | hw/arm/musicpal.c | 17 +++++++++++++---- | ||
| 19 | hw/arm/Kconfig | 1 + | ||
| 20 | 2 files changed, 14 insertions(+), 4 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | ||
| 24 | --- a/hw/arm/musicpal.c | ||
| 25 | +++ b/hw/arm/musicpal.c | ||
| 26 | @@ -XXX,XX +XXX,XX @@ | ||
| 27 | #include "ui/console.h" | ||
| 28 | #include "hw/i2c/i2c.h" | ||
| 29 | #include "hw/irq.h" | ||
| 30 | +#include "hw/or-irq.h" | ||
| 31 | #include "hw/audio/wm8750.h" | ||
| 32 | #include "sysemu/block-backend.h" | ||
| 33 | #include "sysemu/runstate.h" | ||
| 34 | @@ -XXX,XX +XXX,XX @@ | ||
| 35 | #define MP_TIMER4_IRQ 7 | ||
| 36 | #define MP_EHCI_IRQ 8 | ||
| 37 | #define MP_ETH_IRQ 9 | ||
| 38 | -#define MP_UART1_IRQ 11 | ||
| 39 | -#define MP_UART2_IRQ 11 | ||
| 40 | +#define MP_UART_SHARED_IRQ 11 | ||
| 41 | #define MP_GPIO_IRQ 12 | ||
| 42 | #define MP_RTC_IRQ 28 | ||
| 43 | #define MP_AUDIO_IRQ 30 | ||
| 44 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
| 45 | ARMCPU *cpu; | ||
| 46 | qemu_irq pic[32]; | ||
| 47 | DeviceState *dev; | ||
| 48 | + DeviceState *uart_orgate; | ||
| 49 | DeviceState *i2c_dev; | ||
| 50 | DeviceState *lcd_dev; | ||
| 51 | DeviceState *key_dev; | ||
| 52 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
| 53 | pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | ||
| 54 | pic[MP_TIMER4_IRQ], NULL); | ||
| 55 | |||
| 56 | - serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], | ||
| 57 | + /* Logically OR both UART IRQs together */ | ||
| 58 | + uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | ||
| 59 | + object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); | ||
| 60 | + qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); | ||
| 61 | + qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]); | ||
| 62 | + | ||
| 63 | + serial_mm_init(address_space_mem, MP_UART1_BASE, 2, | ||
| 64 | + qdev_get_gpio_in(uart_orgate, 0), | ||
| 65 | 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); | ||
| 66 | - serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], | ||
| 67 | + serial_mm_init(address_space_mem, MP_UART2_BASE, 2, | ||
| 68 | + qdev_get_gpio_in(uart_orgate, 1), | ||
| 69 | 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); | ||
| 70 | |||
| 71 | /* Register flash */ | ||
| 72 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
| 73 | index XXXXXXX..XXXXXXX 100644 | ||
| 74 | --- a/hw/arm/Kconfig | ||
| 75 | +++ b/hw/arm/Kconfig | ||
| 76 | @@ -XXX,XX +XXX,XX @@ config MUSCA | ||
| 77 | |||
| 78 | config MUSICPAL | ||
| 79 | bool | ||
| 80 | + select OR_IRQ | ||
| 81 | select BITBANG_I2C | ||
| 82 | select MARVELL_88W8618 | ||
| 83 | select PTIMER | ||
| 84 | -- | ||
| 85 | 2.20.1 | ||
| 86 | |||
| 87 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 2 | 1 | ||
| 3 | We don't need to fill the full pic[] array if we only use | ||
| 4 | few of the interrupt lines. Directly call qdev_get_gpio_in() | ||
| 5 | when necessary. | ||
| 6 | |||
| 7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 8 | Message-id: 20201107193403.436146-6-f4bug@amsat.org | ||
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | hw/arm/musicpal.c | 25 +++++++++++++------------ | ||
| 13 | 1 file changed, 13 insertions(+), 12 deletions(-) | ||
| 14 | |||
| 15 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | ||
| 16 | index XXXXXXX..XXXXXXX 100644 | ||
| 17 | --- a/hw/arm/musicpal.c | ||
| 18 | +++ b/hw/arm/musicpal.c | ||
| 19 | @@ -XXX,XX +XXX,XX @@ static struct arm_boot_info musicpal_binfo = { | ||
| 20 | static void musicpal_init(MachineState *machine) | ||
| 21 | { | ||
| 22 | ARMCPU *cpu; | ||
| 23 | - qemu_irq pic[32]; | ||
| 24 | DeviceState *dev; | ||
| 25 | + DeviceState *pic; | ||
| 26 | DeviceState *uart_orgate; | ||
| 27 | DeviceState *i2c_dev; | ||
| 28 | DeviceState *lcd_dev; | ||
| 29 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
| 30 | &error_fatal); | ||
| 31 | memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); | ||
| 32 | |||
| 33 | - dev = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, | ||
| 34 | + pic = sysbus_create_simple(TYPE_MV88W8618_PIC, MP_PIC_BASE, | ||
| 35 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); | ||
| 36 | - for (i = 0; i < 32; i++) { | ||
| 37 | - pic[i] = qdev_get_gpio_in(dev, i); | ||
| 38 | - } | ||
| 39 | - sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, pic[MP_TIMER1_IRQ], | ||
| 40 | - pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], | ||
| 41 | - pic[MP_TIMER4_IRQ], NULL); | ||
| 42 | + sysbus_create_varargs(TYPE_MV88W8618_PIT, MP_PIT_BASE, | ||
| 43 | + qdev_get_gpio_in(pic, MP_TIMER1_IRQ), | ||
| 44 | + qdev_get_gpio_in(pic, MP_TIMER2_IRQ), | ||
| 45 | + qdev_get_gpio_in(pic, MP_TIMER3_IRQ), | ||
| 46 | + qdev_get_gpio_in(pic, MP_TIMER4_IRQ), NULL); | ||
| 47 | |||
| 48 | /* Logically OR both UART IRQs together */ | ||
| 49 | uart_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | ||
| 50 | object_property_set_int(OBJECT(uart_orgate), "num-lines", 2, &error_fatal); | ||
| 51 | qdev_realize_and_unref(uart_orgate, NULL, &error_fatal); | ||
| 52 | - qdev_connect_gpio_out(DEVICE(uart_orgate), 0, pic[MP_UART_SHARED_IRQ]); | ||
| 53 | + qdev_connect_gpio_out(DEVICE(uart_orgate), 0, | ||
| 54 | + qdev_get_gpio_in(pic, MP_UART_SHARED_IRQ)); | ||
| 55 | |||
| 56 | serial_mm_init(address_space_mem, MP_UART1_BASE, 2, | ||
| 57 | qdev_get_gpio_in(uart_orgate, 0), | ||
| 58 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
| 59 | OBJECT(get_system_memory()), &error_fatal); | ||
| 60 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); | ||
| 61 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE); | ||
| 62 | - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]); | ||
| 63 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, | ||
| 64 | + qdev_get_gpio_in(pic, MP_ETH_IRQ)); | ||
| 65 | |||
| 66 | sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); | ||
| 67 | |||
| 68 | sysbus_create_simple(TYPE_MUSICPAL_MISC, MP_MISC_BASE, NULL); | ||
| 69 | |||
| 70 | dev = sysbus_create_simple(TYPE_MUSICPAL_GPIO, MP_GPIO_BASE, | ||
| 71 | - pic[MP_GPIO_IRQ]); | ||
| 72 | + qdev_get_gpio_in(pic, MP_GPIO_IRQ)); | ||
| 73 | i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL); | ||
| 74 | i2c = (I2CBus *)qdev_get_child_bus(i2c_dev, "i2c"); | ||
| 75 | |||
| 76 | @@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine) | ||
| 77 | NULL); | ||
| 78 | sysbus_realize_and_unref(s, &error_fatal); | ||
| 79 | sysbus_mmio_map(s, 0, MP_AUDIO_BASE); | ||
| 80 | - sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]); | ||
| 81 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in(pic, MP_AUDIO_IRQ)); | ||
| 82 | |||
| 83 | musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; | ||
| 84 | arm_load_kernel(cpu, machine, &musicpal_binfo); | ||
| 85 | -- | ||
| 86 | 2.20.1 | ||
| 87 | |||
| 88 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The nseries machines have a codepath that allows them to load a | ||
| 2 | secondary bootloader. This code wasn't checking that the | ||
| 3 | load_image_targphys() succeeded. Check the return value and report | ||
| 4 | the error to the user. | ||
| 5 | 1 | ||
| 6 | While we're in the vicinity, fix the comment style of the | ||
| 7 | comment documenting what this image load is doing. | ||
| 8 | |||
| 9 | Fixes: Coverity CID 1192904 | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 12 | Message-id: 20201103114918.11807-1-peter.maydell@linaro.org | ||
| 13 | --- | ||
| 14 | hw/arm/nseries.c | 15 +++++++++++---- | ||
| 15 | 1 file changed, 11 insertions(+), 4 deletions(-) | ||
| 16 | |||
| 17 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | ||
| 18 | index XXXXXXX..XXXXXXX 100644 | ||
| 19 | --- a/hw/arm/nseries.c | ||
| 20 | +++ b/hw/arm/nseries.c | ||
| 21 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | ||
| 22 | /* No, wait, better start at the ROM. */ | ||
| 23 | s->mpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000; | ||
| 24 | |||
| 25 | - /* This is intended for loading the `secondary.bin' program from | ||
| 26 | + /* | ||
| 27 | + * This is intended for loading the `secondary.bin' program from | ||
| 28 | * Nokia images (the NOLO bootloader). The entry point seems | ||
| 29 | * to be at OMAP2_Q2_BASE + 0x400000. | ||
| 30 | * | ||
| 31 | @@ -XXX,XX +XXX,XX @@ static void n8x0_init(MachineState *machine, | ||
| 32 | * for them the entry point needs to be set to OMAP2_SRAM_BASE. | ||
| 33 | * | ||
| 34 | * The code above is for loading the `zImage' file from Nokia | ||
| 35 | - * images. */ | ||
| 36 | - load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000, | ||
| 37 | - machine->ram_size - 0x400000); | ||
| 38 | + * images. | ||
| 39 | + */ | ||
| 40 | + if (load_image_targphys(option_rom[0].name, | ||
| 41 | + OMAP2_Q2_BASE + 0x400000, | ||
| 42 | + machine->ram_size - 0x400000) < 0) { | ||
| 43 | + error_report("Failed to load secondary bootloader %s", | ||
| 44 | + option_rom[0].name); | ||
| 45 | + exit(EXIT_FAILURE); | ||
| 46 | + } | ||
| 47 | |||
| 48 | n800_setup_nolo_tags(nolo_tags); | ||
| 49 | cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); | ||
| 50 | -- | ||
| 51 | 2.20.1 | ||
| 52 | |||
| 53 | diff view generated by jsdifflib |