This patches supported RISC-V migration based on tcg accel. And we have
verified related migration features such as snapshot and live migration.
A few weeks ago, we submitted RFC patches about supporting RISC-V migration
based on kvm accel: https://www.spinics.net/lists/kvm/msg223605.html.
And we found that tcg accelerated migration can be supported with a few
changes. Most of the devices have already implemented the migration
interface, so, to achieve the tcg accelerated migration, we just need to
add vmstate of both cpu and sifive_plic.
Changes since v2:
1. Move vmstate_riscv_cpu declaration to internals.h.
2. Merge m/vsstatus and m/vsstatush into one uint64_t unit.
Changes since v1:
1. Add license head to target/riscv/machine.c.
2. Regenerate some state of PMP at post_load hook.
Yifei Jiang (6):
target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
target/riscv: Add basic vmstate description of CPU
target/riscv: Add PMP state description
target/riscv: Add H extension state description
target/riscv: Add V extension state description
target/riscv: Add sifive_plic vmstate
hw/intc/sifive_plic.c | 26 ++++-
hw/intc/sifive_plic.h | 1 +
target/riscv/cpu.c | 16 ++--
target/riscv/cpu.h | 16 +---
target/riscv/cpu_bits.h | 16 ++--
target/riscv/cpu_helper.c | 72 ++++++--------
target/riscv/csr.c | 28 +++---
target/riscv/internals.h | 4 +
target/riscv/machine.c | 196 ++++++++++++++++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
target/riscv/op_helper.c | 49 +++++-----
target/riscv/pmp.c | 29 +++---
target/riscv/pmp.h | 2 +
13 files changed, 331 insertions(+), 127 deletions(-)
create mode 100644 target/riscv/machine.c
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2.19.1