From nobody Sun May 19 00:42:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1603444651; cv=none; d=zohomail.com; s=zohoarc; b=HJ8Tt2JdkDFLVBXR9aTQ2ix98hgX5Bvm4RcAZm+64MOPVAdvSmnpozVumNmm5xMz1vyDMvGisZjqi+xY4KtvkWfcU0qRmiGgLFz0LXeaGwWQrT588X6z3IUzGI3i/3FSOGGL1cLNd8ZffbcxH/wyHDMHvQkY06XjtJ2f6TIJWIQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603444651; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dFXjDJD4xm0/G64SRqmtWJj2mtxGqqPh7jvfsK/6t6o=; b=gAG7gr28NtLXV2/f+srbTEjtM/hUrwOgI+A41WLvTVTo+Kb58ufU7G60LfhVrA1MpkP6wKsSB/XNtG3JaQk9cOK1lwCi7B7Wi2i/mA8hXTvjk0Qr3D/fo+sdly7nSN0FFxXgUuB5nsMGfx3vwJ5S8fZHFh85i+hBhK/DCxZnQvE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1603444651480631.4468526456828; Fri, 23 Oct 2020 02:17:31 -0700 (PDT) Received: from localhost ([::1]:51082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVtCU-0001Eo-Bo for importer@patchew.org; Fri, 23 Oct 2020 05:17:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVt88-0004bM-Tc; Fri, 23 Oct 2020 05:13:00 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:46360 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVt84-0004iR-GD; Fri, 23 Oct 2020 05:13:00 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 3FD9C1FF252EE2C92632; Fri, 23 Oct 2020 17:12:46 +0800 (CST) Received: from huawei.com (10.174.186.209) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 23 Oct 2020 17:12:38 +0800 From: Yifei Jiang To: , Subject: [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Date: Fri, 23 Oct 2020 17:12:20 +0800 Message-ID: <20201023091225.224-2-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201023091225.224-1-jiangyifei@huawei.com> References: <20201023091225.224-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.209] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 05:12:47 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, richard.henderson@linaro.org, Yifei Jiang , Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, wu.wubin@huawei.com, dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" mstatus/mstatush and vsstatus/vsstatush are two halved for RISCV32. This patch expands mstatus and vsstatus to uint64_t instead of target_ulong so that it can be saved as one unit and reduce some ifdefs in the code. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 8 +++-- target/riscv/cpu.h | 16 ++------- target/riscv/cpu_bits.h | 16 ++++----- target/riscv/cpu_helper.c | 72 ++++++++++++++++----------------------- target/riscv/csr.c | 28 ++++++++------- target/riscv/op_helper.c | 49 +++++++++++++------------- 6 files changed, 82 insertions(+), 107 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..dd05a220c7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -216,13 +216,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *= f, int flags) qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)e= nv->mstatus); #ifdef TARGET_RISCV32 - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", + (target_ulong)(env->mstatus >> 32)); #endif if (riscv_has_ext(env, RVH)) { qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatu= s); - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vssta= tus); + qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", + (target_ulong)env->vsstatus); } qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de275782e6..57050f2268 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -140,14 +140,10 @@ struct CPURISCVState { target_ulong resetvec; =20 target_ulong mhartid; - target_ulong mstatus; + uint64_t mstatus; =20 target_ulong mip; =20 -#ifdef TARGET_RISCV32 - target_ulong mstatush; -#endif - uint32_t miclaim; =20 target_ulong mie; @@ -179,16 +175,13 @@ struct CPURISCVState { uint64_t htimedelta; =20 /* Virtual CSRs */ - target_ulong vsstatus; + uint64_t vsstatus; target_ulong vstvec; target_ulong vsscratch; target_ulong vsepc; target_ulong vscause; target_ulong vstval; target_ulong vsatp; -#ifdef TARGET_RISCV32 - target_ulong vsstatush; -#endif =20 target_ulong mtval2; target_ulong mtinst; @@ -200,10 +193,7 @@ struct CPURISCVState { target_ulong scause_hs; target_ulong stval_hs; target_ulong satp_hs; - target_ulong mstatus_hs; -#ifdef TARGET_RISCV32 - target_ulong mstatush_hs; -#endif + uint64_t mstatus_hs; =20 target_ulong scounteren; target_ulong mcounteren; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bd36062877..62ca6b6f89 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -5,9 +5,14 @@ =20 #define get_field(reg, mask) (((reg) & \ (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) +#define get_field64(reg, mask) (((reg) & \ + (uint64_t)(mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \ (target_ulong)(mask))) +#define set_field64(reg, mask, val) (((reg) & ~(uint64_t)(mask)) | \ + (((uint64_t)(val) * ((mask) & ~((mask) << 1))) & \ + (uint64_t)(mask))) =20 /* Floating point round mode */ #define FSR_RD_SHIFT 5 @@ -381,19 +386,10 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ -#if defined(TARGET_RISCV64) #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL -#elif defined(TARGET_RISCV32) -#define MSTATUS_GVA 0x00000040 -#define MSTATUS_MPV 0x00000080 -#endif =20 -#ifdef TARGET_RISCV32 -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV) -#else -# define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV) -#endif +#define MSTATUS_MPV_ISSET(env) get_field64(env->mstatus, MSTATUS_MPV) =20 #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 904899054d..0430cbe4e3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -39,9 +39,9 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env) { target_ulong irqs; =20 - target_ulong mstatus_mie =3D get_field(env->mstatus, MSTATUS_MIE); - target_ulong mstatus_sie =3D get_field(env->mstatus, MSTATUS_SIE); - target_ulong hs_mstatus_sie =3D get_field(env->mstatus_hs, MSTATUS_SIE= ); + target_ulong mstatus_mie =3D get_field64(env->mstatus, MSTATUS_MIE); + target_ulong mstatus_sie =3D get_field64(env->mstatus, MSTATUS_SIE); + target_ulong hs_mstatus_sie =3D get_field64(env->mstatus_hs, MSTATUS_S= IE); =20 target_ulong pending =3D env->mip & env->mie & ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); @@ -110,14 +110,20 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) =20 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - target_ulong mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | - MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + uint64_t mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; bool current_virt =3D riscv_cpu_virt_enabled(env); =20 g_assert(riscv_has_ext(env, RVH)); =20 #if defined(TARGET_RISCV64) mstatus_mask |=3D MSTATUS64_UXL; +#elif defined(TARGET_RISCV32) + /* + * The upper 32 bits of env->mstatus is mstatush + * register in RISCV32. We need to backup it. + */ + mstatus_mask |=3D (~0ULL << 32); #endif =20 if (current_virt) { @@ -126,11 +132,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->mstatus &=3D ~mstatus_mask; env->mstatus |=3D env->mstatus_hs; =20 -#if defined(TARGET_RISCV32) - env->vsstatush =3D env->mstatush; - env->mstatush |=3D env->mstatush_hs; -#endif - env->vstvec =3D env->stvec; env->stvec =3D env->stvec_hs; =20 @@ -154,11 +155,6 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) env->mstatus &=3D ~mstatus_mask; env->mstatus |=3D env->vsstatus; =20 -#if defined(TARGET_RISCV32) - env->mstatush_hs =3D env->mstatush; - env->mstatush |=3D env->vsstatush; -#endif - env->stvec_hs =3D env->stvec; env->stvec =3D env->vstvec; =20 @@ -347,8 +343,8 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, } =20 if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); + if (get_field64(env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field64(env->mstatus, MSTATUS_MPP); } } =20 @@ -370,9 +366,9 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, int levels, ptidxbits, ptesize, vm, sum, mxr, widened; =20 if (first_stage =3D=3D true) { - mxr =3D get_field(env->mstatus, MSTATUS_MXR); + mxr =3D get_field64(env->mstatus, MSTATUS_MXR); } else { - mxr =3D get_field(env->vsstatus, MSTATUS_MXR); + mxr =3D get_field64(env->vsstatus, MSTATUS_MXR); } =20 if (first_stage =3D=3D true) { @@ -389,7 +385,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, vm =3D get_field(env->hgatp, HGATP_MODE); widened =3D 2; } - sum =3D get_field(env->mstatus, MSTATUS_SUM); + sum =3D get_field64(env->mstatus, MSTATUS_SUM); switch (vm) { case VM_1_10_SV32: levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; @@ -712,14 +708,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, __func__, address, access_type, mmu_idx); =20 if (mode =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH) { - if (get_field(env->mstatus, MSTATUS_MPRV)) { - mode =3D get_field(env->mstatus, MSTATUS_MPP); + if (get_field64(env->mstatus, MSTATUS_MPRV)) { + mode =3D get_field64(env->mstatus, MSTATUS_MPP); } } =20 if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV) && + get_field64(env->mstatus, MSTATUS_MPRV) && MSTATUS_MPV_ISSET(env)) { riscv_cpu_set_two_stage_lookup(env, true); } @@ -780,7 +776,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, /* We did the two stage lookup based on MPRV, unset the lookup */ if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && access_type !=3D MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV) && + get_field64(env->mstatus, MSTATUS_MPRV) && MSTATUS_MPV_ISSET(env)) { riscv_cpu_set_two_stage_lookup(env, false); } @@ -844,7 +840,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; bool force_hs_execp =3D riscv_cpu_force_hs_excep_enabled(env); - target_ulong s; + uint64_t s; =20 /* cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide * so we mask off the MSB and separate into trap type and cause. @@ -932,7 +928,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* Trap into HS mode, from virt */ riscv_cpu_swap_hypervisor_regs(env); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPVP, - get_field(env->mstatus, SSTATUS_S= PP)); + get_field64(env->mstatus, SSTATUS= _SPP)); env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); =20 @@ -952,9 +948,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) } =20 s =3D env->mstatus; - s =3D set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); - s =3D set_field(s, MSTATUS_SPP, env->priv); - s =3D set_field(s, MSTATUS_SIE, 0); + s =3D set_field64(s, MSTATUS_SPIE, get_field64(s, MSTATUS_SIE)); + s =3D set_field64(s, MSTATUS_SPP, env->priv); + s =3D set_field64(s, MSTATUS_SIE, 0); env->mstatus =3D s; env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); env->sepc =3D env->pc; @@ -969,19 +965,11 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (riscv_cpu_virt_enabled(env)) { riscv_cpu_swap_hypervisor_regs(env); } -#ifdef TARGET_RISCV32 - env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, + env->mstatus =3D set_field64(env->mstatus, MSTATUS_MPV, riscv_cpu_virt_enabled(env)); if (riscv_cpu_virt_enabled(env) && tval) { - env->mstatush =3D set_field(env->mstatush, MSTATUS_GVA, 1); - } -#else - env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, - riscv_cpu_virt_enabled(env)); - if (riscv_cpu_virt_enabled(env) && tval) { - env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); + env->mstatus =3D set_field64(env->mstatus, MSTATUS_GVA, 1); } -#endif =20 mtval2 =3D env->guest_phys_fault_addr; =20 @@ -991,9 +979,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) } =20 s =3D env->mstatus; - s =3D set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); - s =3D set_field(s, MSTATUS_MPP, env->priv); - s =3D set_field(s, MSTATUS_MIE, 0); + s =3D set_field64(s, MSTATUS_MPIE, get_field64(s, MSTATUS_MIE)); + s =3D set_field64(s, MSTATUS_MPP, env->priv); + s =3D set_field64(s, MSTATUS_MIE, 0); env->mstatus =3D s; env->mcause =3D cause | ~(((target_ulong)-1) >> async); env->mepc =3D env->pc; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aaef6c6f20..d4b6371719 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -446,8 +446,8 @@ static int validate_vm(CPURISCVState *env, target_ulong= vm) =20 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong mstatus =3D env->mstatus; - target_ulong mask =3D 0; + uint64_t mstatus =3D env->mstatus; + uint64_t mask =3D 0; int dirty; =20 /* flush tlb on mstatus fields that affect VM */ @@ -471,7 +471,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,= target_ulong val) =20 dirty =3D ((mstatus & MSTATUS_FS) =3D=3D MSTATUS_FS) | ((mstatus & MSTATUS_XS) =3D=3D MSTATUS_XS); - mstatus =3D set_field(mstatus, MSTATUS_SD, dirty); + mstatus =3D set_field64(mstatus, MSTATUS_SD, dirty); env->mstatus =3D mstatus; =20 return 0; @@ -480,19 +480,20 @@ static int write_mstatus(CPURISCVState *env, int csrn= o, target_ulong val) #ifdef TARGET_RISCV32 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->mstatush; + *val =3D env->mstatus >> 32; return 0; } =20 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val) { - if ((val ^ env->mstatush) & (MSTATUS_MPV)) { + uint64_t valh =3D (uint64_t)val << 32; + uint64_t mask =3D MSTATUS_MPV | MSTATUS_GVA; + + if ((valh ^ env->mstatus) & (MSTATUS_MPV)) { tlb_flush(env_cpu(env)); } =20 - val &=3D MSTATUS_MPV | MSTATUS_GVA; - - env->mstatush =3D val; + env->mstatus =3D (env->mstatus & ~mask) | (valh & mask); =20 return 0; } @@ -718,14 +719,14 @@ static int rmw_mip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { target_ulong mask =3D (sstatus_v1_10_mask); - *val =3D env->mstatus & mask; + *val =3D (target_ulong)env->mstatus & mask; return 0; } =20 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) { target_ulong mask =3D (sstatus_v1_10_mask); - target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); + target_ulong newval =3D ((target_ulong)env->mstatus & ~mask) | (val & = mask); return write_mstatus(env, CSR_MSTATUS, newval); } =20 @@ -861,7 +862,7 @@ static int read_satp(CPURISCVState *env, int csrno, tar= get_ulong *val) return 0; } =20 - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { + if (env->priv =3D=3D PRV_S && get_field64(env->mstatus, MSTATUS_TVM)) { return -RISCV_EXCP_ILLEGAL_INST; } else { *val =3D env->satp; @@ -878,7 +879,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) if (validate_vm(env, get_field(val, SATP_MODE)) && ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) { - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { + if (env->priv =3D=3D PRV_S && get_field64(env->mstatus, MSTATUS_TV= M)) { return -RISCV_EXCP_ILLEGAL_INST; } else { if((val ^ env->satp) & SATP_ASID) { @@ -1105,7 +1106,8 @@ static int read_vsstatus(CPURISCVState *env, int csrn= o, target_ulong *val) =20 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) { - env->vsstatus =3D val; + uint64_t mask =3D (target_ulong)-1; + env->vsstatus =3D (env->vsstatus & ~mask) | (uint64_t)val; return 0; } =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 9b9ada45a9..18cdffc738 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -79,7 +79,8 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulon= g src, =20 target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) { - target_ulong prev_priv, prev_virt, mstatus; + uint64_t mstatus; + target_ulong prev_priv, prev_virt; =20 if (!(env->priv >=3D PRV_S)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); @@ -90,7 +91,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong= cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 - if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >=3D PRV_M)) { + if (get_field64(env->mstatus, MSTATUS_TSR) && !(env->priv >=3D PRV_M))= { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 @@ -105,14 +106,14 @@ target_ulong helper_sret(CPURISCVState *env, target_u= long cpu_pc_deb) /* We support Hypervisor extensions and virtulisation is disabled = */ target_ulong hstatus =3D env->hstatus; =20 - prev_priv =3D get_field(mstatus, MSTATUS_SPP); + prev_priv =3D get_field64(mstatus, MSTATUS_SPP); prev_virt =3D get_field(hstatus, HSTATUS_SPV); =20 hstatus =3D set_field(hstatus, HSTATUS_SPV, 0); - mstatus =3D set_field(mstatus, MSTATUS_SPP, 0); - mstatus =3D set_field(mstatus, SSTATUS_SIE, - get_field(mstatus, SSTATUS_SPIE)); - mstatus =3D set_field(mstatus, SSTATUS_SPIE, 1); + mstatus =3D set_field64(mstatus, MSTATUS_SPP, 0); + mstatus =3D set_field64(mstatus, SSTATUS_SIE, + get_field64(mstatus, SSTATUS_SPIE)); + mstatus =3D set_field64(mstatus, SSTATUS_SPIE, 1); =20 env->mstatus =3D mstatus; env->hstatus =3D hstatus; @@ -123,12 +124,12 @@ target_ulong helper_sret(CPURISCVState *env, target_u= long cpu_pc_deb) =20 riscv_cpu_set_virt_enabled(env, prev_virt); } else { - prev_priv =3D get_field(mstatus, MSTATUS_SPP); + prev_priv =3D get_field64(mstatus, MSTATUS_SPP); =20 - mstatus =3D set_field(mstatus, MSTATUS_SIE, - get_field(mstatus, MSTATUS_SPIE)); - mstatus =3D set_field(mstatus, MSTATUS_SPIE, 1); - mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); + mstatus =3D set_field64(mstatus, MSTATUS_SIE, + get_field64(mstatus, MSTATUS_SPIE)); + mstatus =3D set_field64(mstatus, MSTATUS_SPIE, 1); + mstatus =3D set_field64(mstatus, MSTATUS_SPP, PRV_U); env->mstatus =3D mstatus; } =20 @@ -148,18 +149,14 @@ target_ulong helper_mret(CPURISCVState *env, target_u= long cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 - target_ulong mstatus =3D env->mstatus; - target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); + uint64_t mstatus =3D env->mstatus; + target_ulong prev_priv =3D get_field64(mstatus, MSTATUS_MPP); target_ulong prev_virt =3D MSTATUS_MPV_ISSET(env); - mstatus =3D set_field(mstatus, MSTATUS_MIE, - get_field(mstatus, MSTATUS_MPIE)); - mstatus =3D set_field(mstatus, MSTATUS_MPIE, 1); - mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); -#ifdef TARGET_RISCV32 - env->mstatush =3D set_field(env->mstatush, MSTATUS_MPV, 0); -#else - mstatus =3D set_field(mstatus, MSTATUS_MPV, 0); -#endif + mstatus =3D set_field64(mstatus, MSTATUS_MIE, + get_field64(mstatus, MSTATUS_MPIE)); + mstatus =3D set_field64(mstatus, MSTATUS_MPIE, 1); + mstatus =3D set_field64(mstatus, MSTATUS_MPP, PRV_U); + mstatus =3D set_field64(mstatus, MSTATUS_MPV, 0); env->mstatus =3D mstatus; riscv_cpu_set_mode(env, prev_priv); =20 @@ -179,7 +176,7 @@ void helper_wfi(CPURISCVState *env) CPUState *cs =3D env_cpu(env); =20 if ((env->priv =3D=3D PRV_S && - get_field(env->mstatus, MSTATUS_TW)) || + get_field64(env->mstatus, MSTATUS_TW)) || riscv_cpu_virt_enabled(env)) { riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); } else { @@ -194,7 +191,7 @@ void helper_tlb_flush(CPURISCVState *env) CPUState *cs =3D env_cpu(env); if (!(env->priv >=3D PRV_S) || (env->priv =3D=3D PRV_S && - get_field(env->mstatus, MSTATUS_TVM))) { + get_field64(env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_VTVM)) { @@ -224,7 +221,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env) void helper_hyp_gvma_tlb_flush(CPURISCVState *env) { if (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env) && - get_field(env->mstatus, MSTATUS_TVM)) { + get_field64(env->mstatus, MSTATUS_TVM)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 --=20 2.19.1 From nobody Sun May 19 00:42:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Add basic CPU state description to the newly created machine.c Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 +---- target/riscv/internals.h | 4 +++ target/riscv/machine.c | 74 ++++++++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 3 +- 4 files changed, 81 insertions(+), 8 deletions(-) create mode 100644 target/riscv/machine.c diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dd05a220c7..6a0264fc6b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "internals.h" #include "exec/exec-all.h" #include "qapi/error.h" #include "qemu/error-report.h" @@ -498,13 +499,6 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); } =20 -#ifndef CONFIG_USER_ONLY -static const VMStateDescription vmstate_riscv_cpu =3D { - .name =3D "cpu", - .unmigratable =3D 1, -}; -#endif - static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), diff --git a/target/riscv/internals.h b/target/riscv/internals.h index f1a546dba6..b15ad394bb 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -38,6 +38,10 @@ target_ulong fclass_d(uint64_t frs1); #define SEW32 2 #define SEW64 3 =20 +#ifndef CONFIG_USER_ONLY +extern const VMStateDescription vmstate_riscv_cpu; +#endif + static inline uint64_t nanbox_s(float32 f) { return f | MAKE_64BIT_MASK(32, 32); diff --git a/target/riscv/machine.c b/target/riscv/machine.c new file mode 100644 index 0000000000..32edbcba7c --- /dev/null +++ b/target/riscv/machine.c @@ -0,0 +1,74 @@ +/* + * RISC-V VMState Description + * + * Copyright (c) 2020 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/error-report.h" +#include "sysemu/kvm.h" +#include "migration/cpu.h" + +const VMStateDescription vmstate_riscv_cpu =3D { + .name =3D "cpu", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), + VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32), + VMSTATE_UINTTL(env.pc, RISCVCPU), + VMSTATE_UINTTL(env.load_res, RISCVCPU), + VMSTATE_UINTTL(env.load_val, RISCVCPU), + VMSTATE_UINTTL(env.frm, RISCVCPU), + VMSTATE_UINTTL(env.badaddr, RISCVCPU), + VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU), + VMSTATE_UINTTL(env.priv_ver, RISCVCPU), + VMSTATE_UINTTL(env.vext_ver, RISCVCPU), + VMSTATE_UINTTL(env.misa, RISCVCPU), + VMSTATE_UINTTL(env.misa_mask, RISCVCPU), + VMSTATE_UINT32(env.features, RISCVCPU), + VMSTATE_UINTTL(env.priv, RISCVCPU), + VMSTATE_UINTTL(env.virt, RISCVCPU), + VMSTATE_UINTTL(env.resetvec, RISCVCPU), + VMSTATE_UINTTL(env.mhartid, RISCVCPU), + VMSTATE_UINT64(env.mstatus, RISCVCPU), + VMSTATE_UINTTL(env.mip, RISCVCPU), + VMSTATE_UINT32(env.miclaim, RISCVCPU), + VMSTATE_UINTTL(env.mie, RISCVCPU), + VMSTATE_UINTTL(env.mideleg, RISCVCPU), + VMSTATE_UINTTL(env.sptbr, RISCVCPU), + VMSTATE_UINTTL(env.satp, RISCVCPU), + VMSTATE_UINTTL(env.sbadaddr, RISCVCPU), + VMSTATE_UINTTL(env.mbadaddr, RISCVCPU), + VMSTATE_UINTTL(env.medeleg, RISCVCPU), + VMSTATE_UINTTL(env.stvec, RISCVCPU), + VMSTATE_UINTTL(env.sepc, RISCVCPU), + VMSTATE_UINTTL(env.scause, RISCVCPU), + VMSTATE_UINTTL(env.mtvec, RISCVCPU), + VMSTATE_UINTTL(env.mepc, RISCVCPU), + VMSTATE_UINTTL(env.mcause, RISCVCPU), + VMSTATE_UINTTL(env.mtval, RISCVCPU), + VMSTATE_UINTTL(env.scounteren, RISCVCPU), + VMSTATE_UINTTL(env.mcounteren, RISCVCPU), + VMSTATE_UINTTL(env.sscratch, RISCVCPU), + VMSTATE_UINTTL(env.mscratch, RISCVCPU), + VMSTATE_UINT64(env.mfromhost, RISCVCPU), + VMSTATE_UINT64(env.mtohost, RISCVCPU), + VMSTATE_UINT64(env.timecmp, RISCVCPU), + + VMSTATE_END_OF_LIST() + } +}; diff --git a/target/riscv/meson.build b/target/riscv/meson.build index abd647fea1..14a5c62dac 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -27,7 +27,8 @@ riscv_ss.add(files( riscv_softmmu_ss =3D ss.source_set() riscv_softmmu_ss.add(files( 'pmp.c', - 'monitor.c' + 'monitor.c', + 'machine.c' )) =20 target_arch +=3D {'riscv': riscv_ss} --=20 2.19.1 From nobody Sun May 19 00:42:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1603444652; cv=none; d=zohomail.com; s=zohoarc; b=ieqs8wnzSc17TP+L07G4dy/4hAaEWIved9ckbiRCqWptgQbDzgdAH4svnHggVZ2hqamBMGlOGt5wNXV2dDZoyAeCOcUSOrMNKXp33MY5v/srie2oT1P84UfbEg4UCyI2w9dlnRTA/lw9vhhtL8eLuJc7duHXbI9Sk1mr+l80Wqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603444652; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 23 Oct 2020 05:13:01 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 4246D1897854D9784819; Fri, 23 Oct 2020 17:12:51 +0800 (CST) Received: from huawei.com (10.174.186.209) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 23 Oct 2020 17:12:42 +0800 From: Yifei Jiang To: , Subject: [PATCH V3 3/6] target/riscv: Add PMP state description Date: Fri, 23 Oct 2020 17:12:22 +0800 Message-ID: <20201023091225.224-4-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201023091225.224-1-jiangyifei@huawei.com> References: <20201023091225.224-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.209] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 05:12:52 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, richard.henderson@linaro.org, Yifei Jiang , Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, wu.wubin@huawei.com, dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" In the case of supporting PMP feature, add PMP state description to vmstate_riscv_cpu. 'vmstate_pmp_addr' and 'num_rules' could be regenerated by pmp_update_rule(). But there exists the problem of updating num_rules repeatedly in pmp_update_rule(). So here extracts pmp_update_rule_addr() and pmp_update_rule_nums() to update 'vmstate_pmp_addr' and 'num_rules' respectively. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- target/riscv/machine.c | 50 ++++++++++++++++++++++++++++++++++++++++++ target/riscv/pmp.c | 29 ++++++++++++++---------- target/riscv/pmp.h | 2 ++ 3 files changed, 70 insertions(+), 11 deletions(-) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 32edbcba7c..fc1461d88e 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -22,6 +22,52 @@ #include "sysemu/kvm.h" #include "migration/cpu.h" =20 +static bool pmp_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + return riscv_feature(env, RISCV_FEATURE_PMP); +} + +static int pmp_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + int i; + + for (i =3D 0; i < MAX_RISCV_PMPS; i++) { + pmp_update_rule_addr(env, i); + } + pmp_update_rule_nums(env); + + return 0; +} + +static const VMStateDescription vmstate_pmp_entry =3D { + .name =3D "cpu/pmp/entry", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(addr_reg, pmp_entry_t), + VMSTATE_UINT8(cfg_reg, pmp_entry_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_pmp =3D { + .name =3D "cpu/pmp", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmp_needed, + .post_load =3D pmp_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS, + 0, vmstate_pmp_entry, pmp_entry_t), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 1, @@ -70,5 +116,9 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64(env.timecmp, RISCVCPU), =20 VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_pmp, + NULL } }; diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index c394e867f8..2eda8e1e2f 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -136,18 +136,8 @@ static void pmp_decode_napot(target_ulong a, target_ul= ong *sa, target_ulong *ea) } } =20 - -/* Convert cfg/addr reg values here into simple 'sa' --> start address and= 'ea' - * end address values. - * This function is called relatively infrequently whereas the check that - * an address is within a pmp rule is called often, so optimise that one - */ -static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) { - int i; - - env->pmp_state.num_rules =3D 0; - uint8_t this_cfg =3D env->pmp_state.pmp[pmp_index].cfg_reg; target_ulong this_addr =3D env->pmp_state.pmp[pmp_index].addr_reg; target_ulong prev_addr =3D 0u; @@ -186,7 +176,13 @@ static void pmp_update_rule(CPURISCVState *env, uint32= _t pmp_index) =20 env->pmp_state.addr[pmp_index].sa =3D sa; env->pmp_state.addr[pmp_index].ea =3D ea; +} =20 +void pmp_update_rule_nums(CPURISCVState *env) +{ + int i; + + env->pmp_state.num_rules =3D 0; for (i =3D 0; i < MAX_RISCV_PMPS; i++) { const uint8_t a_field =3D pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); @@ -196,6 +192,17 @@ static void pmp_update_rule(CPURISCVState *env, uint32= _t pmp_index) } } =20 +/* Convert cfg/addr reg values here into simple 'sa' --> start address and= 'ea' + * end address values. + * This function is called relatively infrequently whereas the check that + * an address is within a pmp rule is called often, so optimise that one + */ +static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) +{ + pmp_update_rule_addr(env, pmp_index); + pmp_update_rule_nums(env); +} + static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong= addr) { int result =3D 0; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index 6a8f072871..6c6b4c9bef 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -62,5 +62,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong = addr, target_ulong size, pmp_priv_t priv, target_ulong mode); bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, target_ulong *tlb_size); +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); +void pmp_update_rule_nums(CPURISCVState *env); =20 #endif --=20 2.19.1 From nobody Sun May 19 00:42:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1603444653; cv=none; d=zohomail.com; s=zohoarc; b=hiy5n7YHjVSnHwpz3rfqBsnZUyG2YH7qWK7HdD6bRZa8L90DbQ77GpIpqkhjjOGpf/aQ1x0x9kd68fKy/YDesPeI38cdAGX8GV5foXsyCBFbe6xVbPBZU2RLKm/riCP4nqVd0ZX/KLGXRMTpXxRYDqNXFc7jLWxEQS4k9dOQKNA= ARC-Message-Signature: i=1; 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Fri, 23 Oct 2020 05:17:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54460) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVt88-0004a6-4C; Fri, 23 Oct 2020 05:13:00 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:5207 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVt85-0004kg-LV; Fri, 23 Oct 2020 05:12:59 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 48C1243186EAF3CA9A72; Fri, 23 Oct 2020 17:12:51 +0800 (CST) Received: from huawei.com (10.174.186.209) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 23 Oct 2020 17:12:44 +0800 From: Yifei Jiang To: , Subject: [PATCH V3 4/6] target/riscv: Add H extension state description Date: Fri, 23 Oct 2020 17:12:23 +0800 Message-ID: <20201023091225.224-5-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201023091225.224-1-jiangyifei@huawei.com> References: <20201023091225.224-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.209] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" In the case of supporting H extension, add H extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- target/riscv/machine.c | 47 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index fc1461d88e..ae60050898 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -68,6 +68,52 @@ static const VMStateDescription vmstate_pmp =3D { } }; =20 +static bool hyper_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + return riscv_has_ext(env, RVH); +} + +static const VMStateDescription vmstate_hyper =3D { + .name =3D "cpu/hyper", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D hyper_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(env.hstatus, RISCVCPU), + VMSTATE_UINTTL(env.hedeleg, RISCVCPU), + VMSTATE_UINTTL(env.hideleg, RISCVCPU), + VMSTATE_UINTTL(env.hcounteren, RISCVCPU), + VMSTATE_UINTTL(env.htval, RISCVCPU), + VMSTATE_UINTTL(env.htinst, RISCVCPU), + VMSTATE_UINTTL(env.hgatp, RISCVCPU), + VMSTATE_UINT64(env.htimedelta, RISCVCPU), + + VMSTATE_UINT64(env.vsstatus, RISCVCPU), + VMSTATE_UINTTL(env.vstvec, RISCVCPU), + VMSTATE_UINTTL(env.vsscratch, RISCVCPU), + VMSTATE_UINTTL(env.vsepc, RISCVCPU), + VMSTATE_UINTTL(env.vscause, RISCVCPU), + VMSTATE_UINTTL(env.vstval, RISCVCPU), + VMSTATE_UINTTL(env.vsatp, RISCVCPU), + + VMSTATE_UINTTL(env.mtval2, RISCVCPU), + VMSTATE_UINTTL(env.mtinst, RISCVCPU), + + VMSTATE_UINTTL(env.stvec_hs, RISCVCPU), + VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU), + VMSTATE_UINTTL(env.sepc_hs, RISCVCPU), + VMSTATE_UINTTL(env.scause_hs, RISCVCPU), + VMSTATE_UINTTL(env.stval_hs, RISCVCPU), + VMSTATE_UINTTL(env.satp_hs, RISCVCPU), + VMSTATE_UINT64(env.mstatus_hs, RISCVCPU), + + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 1, @@ -119,6 +165,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { }, .subsections =3D (const VMStateDescription * []) { &vmstate_pmp, + &vmstate_hyper, NULL } }; --=20 2.19.1 From nobody Sun May 19 00:42:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1603444787; cv=none; d=zohomail.com; s=zohoarc; b=BoYhlIo5pZHDSN/pFlLbsNYi4AMfBtxwwGRloqZMMxfBMiuynF/vrSVctmINCsoGWc43yrKgFatUAOhXETYlvt61sbHkOoaDnq8jo+yOo1wiCFw8AezgmipcgzIgiZYVxcTSUOlGYuM3a1ZMfmOgubQ8jSpr/a5xRfRQtLSJxBU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603444787; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 23 Oct 2020 05:13:01 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 53652F5524677535EE1F; Fri, 23 Oct 2020 17:12:56 +0800 (CST) Received: from huawei.com (10.174.186.209) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 23 Oct 2020 17:12:45 +0800 From: Yifei Jiang To: , Subject: [PATCH V3 5/6] target/riscv: Add V extension state description Date: Fri, 23 Oct 2020 17:12:24 +0800 Message-ID: <20201023091225.224-6-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201023091225.224-1-jiangyifei@huawei.com> References: <20201023091225.224-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.209] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" In the case of supporting V extension, add V extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/machine.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ae60050898..44d4015bd6 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -76,6 +76,30 @@ static bool hyper_needed(void *opaque) return riscv_has_ext(env, RVH); } =20 +static bool vector_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + return riscv_has_ext(env, RVV); +} + +static const VMStateDescription vmstate_vector =3D { + .name =3D "cpu/vector", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D vector_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64= ), + VMSTATE_UINTTL(env.vxrm, RISCVCPU), + VMSTATE_UINTTL(env.vxsat, RISCVCPU), + VMSTATE_UINTTL(env.vl, RISCVCPU), + VMSTATE_UINTTL(env.vstart, RISCVCPU), + VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_hyper =3D { .name =3D "cpu/hyper", .version_id =3D 1, @@ -166,6 +190,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { .subsections =3D (const VMStateDescription * []) { &vmstate_pmp, &vmstate_hyper, + &vmstate_vector, NULL } }; --=20 2.19.1 From nobody Sun May 19 00:42:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1603444477; cv=none; d=zohomail.com; s=zohoarc; b=ckk9abUu5dE/G+REBbRZqtrD4uQQnfjcW8NwfyaHWhunzDJsYaS7SxxV3XHuWVXyBF6Xc5QjWEVO8B/WiXRr615x9YaDUaq9pWD00DzgYS6sVcWUGwxS8mRXHDCokFAn4TCyumnG7rez6z1gNK66/BxXySgp916G+tSpkotK5Ss= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603444477; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 23 Oct 2020 05:13:01 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 4D27CCA9D5FC383C5835; Fri, 23 Oct 2020 17:12:56 +0800 (CST) Received: from huawei.com (10.174.186.209) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 23 Oct 2020 17:12:47 +0800 From: Yifei Jiang To: , Subject: [PATCH V3 6/6] target/riscv: Add sifive_plic vmstate Date: Fri, 23 Oct 2020 17:12:25 +0800 Message-ID: <20201023091225.224-7-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201023091225.224-1-jiangyifei@huawei.com> References: <20201023091225.224-1-jiangyifei@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.209] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 05:12:47 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, richard.henderson@linaro.org, Yifei Jiang , Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, wu.wubin@huawei.com, dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add sifive_plic vmstate for supporting sifive_plic migration. Current vmstate framework only supports one structure parameter as num field to describe variable length arrays, so introduce num_enables. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- hw/intc/sifive_plic.c | 26 +++++++++++++++++++++++++- hw/intc/sifive_plic.h | 1 + 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index f42fd695d8..97a1a27a9a 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -30,6 +30,7 @@ #include "hw/intc/sifive_plic.h" #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" +#include "migration/vmstate.h" =20 #define RISCV_DEBUG_PLIC 0 =20 @@ -448,11 +449,12 @@ static void sifive_plic_realize(DeviceState *dev, Err= or **errp) TYPE_SIFIVE_PLIC, plic->aperture_size); parse_hart_config(plic); plic->bitfield_words =3D (plic->num_sources + 31) >> 5; + plic->num_enables =3D plic->bitfield_words * plic->num_addrs; plic->source_priority =3D g_new0(uint32_t, plic->num_sources); plic->target_priority =3D g_new(uint32_t, plic->num_addrs); plic->pending =3D g_new0(uint32_t, plic->bitfield_words); plic->claimed =3D g_new0(uint32_t, plic->bitfield_words); - plic->enable =3D g_new0(uint32_t, plic->bitfield_words * plic->num_add= rs); + plic->enable =3D g_new0(uint32_t, plic->num_enables); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio); qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources); =20 @@ -472,12 +474,34 @@ static void sifive_plic_realize(DeviceState *dev, Err= or **errp) msi_nonbroken =3D true; } =20 +static const VMStateDescription vmstate_sifive_plic =3D { + .name =3D "riscv_sifive_plic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState, + num_sources, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState, + num_addrs, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words= , 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words= , 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_END_OF_LIST() + } +}; + static void sifive_plic_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 device_class_set_props(dc, sifive_plic_properties); dc->realize =3D sifive_plic_realize; + dc->vmsd =3D &vmstate_sifive_plic; } =20 static const TypeInfo sifive_plic_info =3D { diff --git a/hw/intc/sifive_plic.h b/hw/intc/sifive_plic.h index b75b1f145d..1e451a270c 100644 --- a/hw/intc/sifive_plic.h +++ b/hw/intc/sifive_plic.h @@ -52,6 +52,7 @@ struct SiFivePLICState { uint32_t num_addrs; uint32_t num_harts; uint32_t bitfield_words; + uint32_t num_enables; PLICAddr *addr_config; uint32_t *source_priority; uint32_t *target_priority; --=20 2.19.1