Series comparison

-[PULL 00/30] riscv-to-apply queue
+[PULL 00/33] riscv-to-apply queue
-The following changes since commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a:
+From: Alistair Francis <alistair.francis@wdc.com>
-  Merge remote-tracking branch 'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging (2020-09-08 21:21:13 +0100)
+The following changes since commit 4c127fdbe81d66e7cafed90908d0fd1f6f2a6cd0:
   Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into staging (2021-10-21 09:53:27 -0700)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910
+  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211022-2
-for you to fetch changes up to 7595a65818ea9b49c36650a8c217a1ef9bd6e62a:
+for you to fetch changes up to 11ec06f9eaedc801ded34c79861367b76ab2b731:
-  hw/riscv: Sort the Kconfig options in alphabetical order (2020-09-09 15:54:19 -0700)
+  hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id (2021-10-22 23:35:47 +1000)
 ----------------------------------------------------------------
-This PR includes multiple fixes and features for RISC-V:
+Fourth RISC-V PR for QEMU 6.2
- - Fixes a bug in printing trap causes
- - Allows 16-bit writes to the SiFive test device. This fixes the
+ - Vector extension bug fixes
-   failure to reboot the RISC-V virt machine
+ - Bit manipulation extension bug fix
- - Support for the Microchip PolarFire SoC and Icicle Kit
+ - Support vhost-user and numa mem options on all boards
- - A reafactor of RISC-V code out of hw/riscv
+ - Rationalise XLEN and operand lengths
  - Bump the OpenTitan FPGA support
  - Remove the Ibex PLIC
  - General code cleanup
 ----------------------------------------------------------------
-Bin Meng (28):
+Alistair Francis (7):
-      target/riscv: cpu: Add a new 'resetvec' property
+      target/riscv: Remove some unused macros
-      hw/riscv: hart: Add a new 'resetvec' property
+      target/riscv: Organise the CPU properties
-      target/riscv: cpu: Set reset vector based on the configured property value
+      hw/riscv: opentitan: Update to the latest build
-      hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
+      hw/intc: Remove the Ibex PLIC
-      hw/char: Add Microchip PolarFire SoC MMUART emulation
+      hw/intc: sifive_plic: Move the properties
-      hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
+      hw/intc: sifive_plic: Cleanup the realize function
-      hw/sd: Add Cadence SDHCI emulation
+      hw/intc: sifive_plic: Cleanup the irq_request function
       hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
       hw/dma: Add SiFive platform DMA controller emulation
       hw/riscv: microchip_pfsoc: Connect a DMA controller
       hw/net: cadence_gem: Add a new 'phy-addr' property
       hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
       hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
       hw/riscv: microchip_pfsoc: Hook GPIO controllers
       hw/riscv: clint: Avoid using hard-coded timebase frequency
       hw/riscv: sifive_u: Connect a DMA controller
       hw/riscv: Move sifive_e_prci model to hw/misc
       hw/riscv: Move sifive_u_prci model to hw/misc
       hw/riscv: Move sifive_u_otp model to hw/misc
       hw/riscv: Move sifive_gpio model to hw/gpio
       hw/riscv: Move sifive_clint model to hw/intc
       hw/riscv: Move sifive_plic model to hw/intc
       hw/riscv: Move riscv_htif model to hw/char
       hw/riscv: Move sifive_uart model to hw/char
       hw/riscv: Move sifive_test model to hw/misc
       hw/riscv: Always build riscv_hart.c
       hw/riscv: Drop CONFIG_SIFIVE
       hw/riscv: Sort the Kconfig options in alphabetical order
-Nathan Chancellor (1):
+Bin Meng (6):
-      riscv: sifive_test: Allow 16-bit writes to memory region
+      hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
       hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
       hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
       hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
       hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
       hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
-Yifei Jiang (1):
+Frank Chang (2):
-      target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
+      target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
       target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
- default-configs/riscv64-softmmu.mak         |   1 +
+Mingwang Li (1):
- {include/hw/riscv => hw/intc}/sifive_plic.h |   0
+      hw/riscv: virt: Use machine->ram as the system memory
  hw/riscv/trace.h                            |   1 -
  include/hw/char/mchp_pfsoc_mmuart.h         |  61 ++++
  include/hw/{riscv => char}/riscv_htif.h     |   0
  include/hw/{riscv => char}/sifive_uart.h    |   0
  include/hw/dma/sifive_pdma.h                |  57 ++++
  include/hw/{riscv => gpio}/sifive_gpio.h    |   0
  include/hw/{riscv => intc}/sifive_clint.h   |   4 +-
  include/hw/{riscv => misc}/sifive_e_prci.h  |   0
  include/hw/{riscv => misc}/sifive_test.h    |   0
  include/hw/{riscv => misc}/sifive_u_otp.h   |   0
  include/hw/{riscv => misc}/sifive_u_prci.h  |   0
  include/hw/net/cadence_gem.h                |   2 +
  include/hw/riscv/microchip_pfsoc.h          | 133 +++++++++
  include/hw/riscv/riscv_hart.h               |   1 +
  include/hw/riscv/sifive_e.h                 |   2 +-
  include/hw/riscv/sifive_u.h                 |  17 +-
  include/hw/sd/cadence_sdhci.h               |  47 +++
  target/riscv/cpu.h                          |   8 +-
  hw/arm/xilinx_zynq.c                        |   1 +
  hw/arm/xlnx-versal.c                        |   1 +
  hw/arm/xlnx-zynqmp.c                        |   2 +
  hw/char/mchp_pfsoc_mmuart.c                 |  86 ++++++
  hw/{riscv => char}/riscv_htif.c             |   2 +-
  hw/{riscv => char}/sifive_uart.c            |   2 +-
  hw/dma/sifive_pdma.c                        | 313 ++++++++++++++++++++
  hw/{riscv => gpio}/sifive_gpio.c            |   2 +-
  hw/{riscv => intc}/sifive_clint.c           |  28 +-
  hw/{riscv => intc}/sifive_plic.c            |   2 +-
  hw/{riscv => misc}/sifive_e_prci.c          |   2 +-
  hw/{riscv => misc}/sifive_test.c            |   4 +-
  hw/{riscv => misc}/sifive_u_otp.c           |   2 +-
  hw/{riscv => misc}/sifive_u_prci.c          |   2 +-
  hw/net/cadence_gem.c                        |   7 +-
  hw/riscv/microchip_pfsoc.c                  | 437 ++++++++++++++++++++++++++++
  hw/riscv/opentitan.c                        |   1 +
  hw/riscv/riscv_hart.c                       |   3 +
  hw/riscv/sifive_e.c                         |  12 +-
  hw/riscv/sifive_u.c                         |  41 ++-
  hw/riscv/spike.c                            |   7 +-
  hw/riscv/virt.c                             |   9 +-
  hw/sd/cadence_sdhci.c                       | 193 ++++++++++++
  target/riscv/cpu.c                          |  19 +-
  target/riscv/cpu_helper.c                   |   8 +-
  target/riscv/csr.c                          |   4 +-
  MAINTAINERS                                 |   9 +
  hw/char/Kconfig                             |   9 +
  hw/char/meson.build                         |   3 +
  hw/dma/Kconfig                              |   3 +
  hw/dma/meson.build                          |   1 +
  hw/gpio/Kconfig                             |   3 +
  hw/gpio/meson.build                         |   1 +
  hw/gpio/trace-events                        |   6 +
  hw/intc/Kconfig                             |   6 +
  hw/intc/meson.build                         |   2 +
  hw/misc/Kconfig                             |  12 +
  hw/misc/meson.build                         |   6 +
  hw/riscv/Kconfig                            |  70 +++--
  hw/riscv/meson.build                        |  12 +-
  hw/riscv/trace-events                       |   7 -
  hw/sd/Kconfig                               |   4 +
  hw/sd/meson.build                           |   1 +
  meson.build                                 |   1 -
 files changed, 1575 insertions(+), 105 deletions(-)
  rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
  delete mode 100644 hw/riscv/trace.h
  create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
  rename include/hw/{riscv => char}/riscv_htif.h (100%)
  rename include/hw/{riscv => char}/sifive_uart.h (100%)
  create mode 100644 include/hw/dma/sifive_pdma.h
  rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
  rename include/hw/{riscv => intc}/sifive_clint.h (92%)
  rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
  rename include/hw/{riscv => misc}/sifive_test.h (100%)
  rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
  rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
  create mode 100644 include/hw/riscv/microchip_pfsoc.h
  create mode 100644 include/hw/sd/cadence_sdhci.h
  create mode 100644 hw/char/mchp_pfsoc_mmuart.c
  rename hw/{riscv => char}/riscv_htif.c (99%)
  rename hw/{riscv => char}/sifive_uart.c (99%)
  create mode 100644 hw/dma/sifive_pdma.c
  rename hw/{riscv => gpio}/sifive_gpio.c (99%)
  rename hw/{riscv => intc}/sifive_clint.c (90%)
  rename hw/{riscv => intc}/sifive_plic.c (99%)
  rename hw/{riscv => misc}/sifive_e_prci.c (99%)
  rename hw/{riscv => misc}/sifive_test.c (97%)
  rename hw/{riscv => misc}/sifive_u_otp.c (99%)
  rename hw/{riscv => misc}/sifive_u_prci.c (99%)
  create mode 100644 hw/riscv/microchip_pfsoc.c
  create mode 100644 hw/sd/cadence_sdhci.c
  delete mode 100644 hw/riscv/trace-events
+Philipp Tomsich (1):
+      target/riscv: Fix orc.b implementation
+Richard Henderson (15):
+      target/riscv: Move cpu_get_tb_cpu_state out of line
+      target/riscv: Create RISCVMXL enumeration
+      target/riscv: Split misa.mxl and misa.ext
+      target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
+      target/riscv: Add MXL/SXL/UXL to TB_FLAGS
+      target/riscv: Use REQUIRE_64BIT in amo_check64
+      target/riscv: Properly check SEW in amo_op
+      target/riscv: Replace is_32bit with get_xl/get_xlen
+      target/riscv: Replace DisasContext.w with DisasContext.ol
+      target/riscv: Use gen_arith_per_ol for RVM
+      target/riscv: Adjust trans_rev8_32 for riscv64
+      target/riscv: Use gen_unary_per_ol for RVB
+      target/riscv: Use gen_shift*_per_ol for RVB, RVI
+      target/riscv: Use riscv_csrrw_debug for cpu_dump
+      target/riscv: Compute mstatus.sd on demand
+Travis Geiselbrecht (1):
+      target/riscv: line up all of the registers in the info register dump
+ include/hw/riscv/opentitan.h            |   6 +-
+ target/riscv/cpu.h                      |  87 +++------
+ target/riscv/cpu_bits.h                 |  16 +-
+ hw/intc/ibex_plic.c                     | 307 --------------------------------
+ hw/intc/sifive_plic.c                   |  85 ++++-----
+ hw/riscv/boot.c                         |   2 +-
+ hw/riscv/microchip_pfsoc.c              |  36 ++--
+ hw/riscv/opentitan.c                    |  38 +++-
+ hw/riscv/shakti_c.c                     |   6 +-
+ hw/riscv/sifive_e.c                     |  16 +-
+ hw/riscv/sifive_u.c                     |   6 +-
+ hw/riscv/spike.c                        |   6 +-
+ hw/riscv/virt.c                         |   6 +-
+ linux-user/elfload.c                    |   2 +-
+ linux-user/riscv/cpu_loop.c             |   2 +-
+ semihosting/arm-compat-semi.c           |   2 +-
+ target/riscv/cpu.c                      | 216 ++++++++++++----------
+ target/riscv/cpu_helper.c               |  92 +++++++++-
+ target/riscv/csr.c                      | 104 ++++++-----
+ target/riscv/gdbstub.c                  |  10 +-
+ target/riscv/machine.c                  |  10 +-
+ target/riscv/monitor.c                  |   4 +-
+ target/riscv/translate.c                | 174 +++++++++++++-----
+ target/riscv/insn_trans/trans_rvb.c.inc | 153 +++++++++-------
+ target/riscv/insn_trans/trans_rvi.c.inc |  44 ++---
+ target/riscv/insn_trans/trans_rvm.c.inc |  36 +++-
+ target/riscv/insn_trans/trans_rvv.c.inc |  32 ++--
+ hw/intc/meson.build                     |   1 -
+files changed, 720 insertions(+), 779 deletions(-)
+ delete mode 100644 hw/intc/ibex_plic.c

-[PULL 30/30] hw/riscv: Sort the Kconfig options in alphabetical order
+[PULL 01/33] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
-From: Bin Meng <bin.meng@windriver.com>
+From: Frank Chang <frank.chang@sifive.com>
-At present the Kconfig file is in disorder. Let's sort the options.
+oprsz and maxsz are passed with the same value in commit: eee2d61e202.
 However, vmv.v.v was missed in that commit and should pass the same
 value as well in its tcg_gen_gvec_2_ptr() call.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-Id: <1599129623-68957-13-git-send-email-bmeng.cn@gmail.com>
+Message-id: 20211007081803.1705656-1-frank.chang@sifive.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/Kconfig | 58 ++++++++++++++++++++++++------------------------
+ target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
-file changed, 29 insertions(+), 29 deletions(-)
+file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/hw/riscv/Kconfig
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
- config IBEX
+             tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-     bool
+             tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
--config SIFIVE_E
+-                               cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
--    bool
++                               cpu_env, s->vlen / 8, s->vlen / 8, data,
--    select MSI_NONBROKEN
++                               fns[s->sew]);
--    select SIFIVE_CLINT
+             gen_set_label(over);
--    select SIFIVE_GPIO
+         }
--    select SIFIVE_PLIC
+         return true;
 -    select SIFIVE_UART
 -    select SIFIVE_E_PRCI
 -    select UNIMP
 -
 -config SIFIVE_U
 +config MICROCHIP_PFSOC
      bool
 -    select CADENCE
 +    select CADENCE_SDHCI
 +    select MCHP_PFSOC_MMUART
      select MSI_NONBROKEN
      select SIFIVE_CLINT
 -    select SIFIVE_GPIO
      select SIFIVE_PDMA
      select SIFIVE_PLIC
 -    select SIFIVE_UART
 -    select SIFIVE_U_OTP
 -    select SIFIVE_U_PRCI
      select UNIMP
 -config SPIKE
 -    bool
 -    select HTIF
 -    select MSI_NONBROKEN
 -    select SIFIVE_CLINT
 -    select SIFIVE_PLIC
 -
  config OPENTITAN
      bool
      select IBEX
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      bool
      imply PCI_DEVICES
      imply TEST_DEVICES
 +    select GOLDFISH_RTC
      select MSI_NONBROKEN
      select PCI
 -    select SERIAL
 -    select GOLDFISH_RTC
 -    select VIRTIO_MMIO
      select PCI_EXPRESS_GENERIC_BRIDGE
      select PFLASH_CFI01
 +    select SERIAL
      select SIFIVE_CLINT
      select SIFIVE_PLIC
      select SIFIVE_TEST
 +    select VIRTIO_MMIO
 -config MICROCHIP_PFSOC
 +config SIFIVE_E
      bool
      select MSI_NONBROKEN
      select SIFIVE_CLINT
 +    select SIFIVE_GPIO
 +    select SIFIVE_PLIC
 +    select SIFIVE_UART
 +    select SIFIVE_E_PRCI
      select UNIMP
 -    select MCHP_PFSOC_MMUART
 +
 +config SIFIVE_U
 +    bool
 +    select CADENCE
 +    select MSI_NONBROKEN
 +    select SIFIVE_CLINT
 +    select SIFIVE_GPIO
      select SIFIVE_PDMA
      select SIFIVE_PLIC
 -    select CADENCE_SDHCI
 +    select SIFIVE_UART
 +    select SIFIVE_U_OTP
 +    select SIFIVE_U_PRCI
 +    select UNIMP
 +
 +config SPIKE
 +    bool
 +    select HTIF
 +    select MSI_NONBROKEN
 +    select SIFIVE_CLINT
 +    select SIFIVE_PLIC
 --
-.28.0
+.31.1

-[PULL 29/30] hw/riscv: Drop CONFIG_SIFIVE
+[PULL 02/33] target/riscv: line up all of the registers in the info register dump
-From: Bin Meng <bin.meng@windriver.com>
+From: Travis Geiselbrecht <travisg@gmail.com>
-The name SIFIVE is too vague to convey the required component of
+Ensure the columns for all of the register names and values line up.
-MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
+No functional change, just a minor tweak to the output.
 each machine instead.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-12-git-send-email-bmeng.cn@gmail.com>
+Message-id: 20211009055019.545153-1-travisg@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/Kconfig | 14 +++++---------
+ target/riscv/cpu.c | 10 +++++-----
-file changed, 5 insertions(+), 9 deletions(-)
+file changed, 5 insertions(+), 5 deletions(-)
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
+--- a/target/riscv/cpu.c
-+++ b/hw/riscv/Kconfig
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
- config IBEX
+     }
-     bool
+     if (riscv_has_ext(env, RVH)) {
+         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
--config SIFIVE
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ",
--    bool
++        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus",
--    select MSI_NONBROKEN
+                      (target_ulong)env->vsstatus);
--
+     }
- config SIFIVE_E
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
-     bool
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
--    select SIFIVE
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
-+    select MSI_NONBROKEN
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
-     select SIFIVE_CLINT
+     if (riscv_has_ext(env, RVH)) {
-     select SIFIVE_GPIO
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
-     select SIFIVE_PLIC
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
++        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval   ", env->htval);
- config SIFIVE_U
++        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2  ", env->mtval2);
-     bool
+     }
-     select CADENCE
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
--    select SIFIVE
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
-+    select MSI_NONBROKEN
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-     select SIFIVE_CLINT
+ #endif
-     select SIFIVE_GPIO
-     select SIFIVE_PDMA
+     for (i = 0; i < 32; i++) {
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx,
- config SPIKE
++        qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
-     bool
+                      riscv_int_regnames[i], env->gpr[i]);
-     select HTIF
+         if ((i & 3) == 3) {
--    select SIFIVE
+             qemu_fprintf(f, "\n");
-+    select MSI_NONBROKEN
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-     select SIFIVE_CLINT
+     }
-     select SIFIVE_PLIC
+     if (flags & CPU_DUMP_FPU) {
+         for (i = 0; i < 32; i++) {
-@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
+-            qemu_fprintf(f, " %s %016" PRIx64,
-     bool
++            qemu_fprintf(f, " %-8s %016" PRIx64,
-     imply PCI_DEVICES
+                          riscv_fpr_regnames[i], env->fpr[i]);
-     imply TEST_DEVICES
+             if ((i & 3) == 3) {
-+    select MSI_NONBROKEN
+                 qemu_fprintf(f, "\n");
      select PCI
      select SERIAL
      select GOLDFISH_RTC
      select VIRTIO_MMIO
      select PCI_EXPRESS_GENERIC_BRIDGE
      select PFLASH_CFI01
 -    select SIFIVE
      select SIFIVE_CLINT
      select SIFIVE_PLIC
      select SIFIVE_TEST
  config MICROCHIP_PFSOC
      bool
 -    select SIFIVE
 +    select MSI_NONBROKEN
      select SIFIVE_CLINT
      select UNIMP
      select MCHP_PFSOC_MMUART
 --
-.28.0
+.31.1

-[PULL 28/30] hw/riscv: Always build riscv_hart.c
+[PULL 03/33] target/riscv: Fix orc.b implementation
-From: Bin Meng <bin.meng@windriver.com>
+From: Philipp Tomsich <philipp.tomsich@vrull.eu>
-Every RISC-V machine needs riscv_hart hence there is no need to
+The earlier implementation fell into a corner case for bytes that were
-have a dedicated Kconfig option for it. Drop the Kconfig option
+x01, giving a wrong result (but not affecting our application test
-and always build riscv_hart.c.
+cases for strings, as an ASCII value 0x01 is rare in those...).
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+This changes the algorithm to:
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+. Mask out the high-bit of each bytes (so that each byte is <= 127).
-Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com>
+. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will overflow
     into the highest bit of each byte).
 . Bitwise-or the original value back in (to cover those cases where the
     source byte was exactly 128) to saturate the high-bit.
 . Shift-and-mask (implemented as a mask-and-shift) to extract the MSB of
     each byte into its LSB.
 . Multiply with 0xff to fan out the LSB to all bits of each byte.
 Fixes: d7a4fcb034 ("target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci")
 Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
 Reported-by: Vincent Palatin <vpalatin@rivosinc.com>
 Tested-by: Vincent Palatin <vpalatin@rivosinc.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/Kconfig     | 9 ---------
+ target/riscv/insn_trans/trans_rvb.c.inc | 13 ++++++++-----
- hw/riscv/meson.build | 2 +-
+file changed, 8 insertions(+), 5 deletions(-)
 files changed, 1 insertion(+), 10 deletions(-)
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
+--- a/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/hw/riscv/Kconfig
++++ b/target/riscv/insn_trans/trans_rvb.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
--config HART
+ static void gen_orc_b(TCGv ret, TCGv source1)
--    bool
+ {
--
+     TCGv  tmp = tcg_temp_new();
- config IBEX
+-    TCGv  ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
-     bool
++    TCGv  low7 = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
-@@ -XXX,XX +XXX,XX @@ config SIFIVE
+-    /* Set lsb in each byte if the byte was zero. */
+-    tcg_gen_sub_tl(tmp, source1, ones);
- config SIFIVE_E
+-    tcg_gen_andc_tl(tmp, tmp, source1);
-     bool
++    /* Set msb in each byte if the byte was non-zero. */
--    select HART
++    tcg_gen_and_tl(tmp, source1, low7);
-     select SIFIVE
++    tcg_gen_add_tl(tmp, tmp, low7);
-     select SIFIVE_CLINT
++    tcg_gen_or_tl(tmp, tmp, source1);
-     select SIFIVE_GPIO
++
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
++    /* Extract the msb to the lsb in each byte */
- config SIFIVE_U
++    tcg_gen_andc_tl(tmp, tmp, low7);
-     bool
+     tcg_gen_shri_tl(tmp, tmp, 7);
-     select CADENCE
+-    tcg_gen_andc_tl(tmp, ones, tmp);
--    select HART
-     select SIFIVE
+     /* Replicate the lsb of each byte across the byte. */
-     select SIFIVE_CLINT
+     tcg_gen_muli_tl(ret, tmp, 0xff);
      select SIFIVE_GPIO
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
  config SPIKE
      bool
 -    select HART
      select HTIF
      select SIFIVE
      select SIFIVE_CLINT
@@ -XXX,XX +XXX,XX @@ config SPIKE
  config OPENTITAN
      bool
      select IBEX
 -    select HART
      select UNIMP
  config RISCV_VIRT
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      imply PCI_DEVICES
      imply TEST_DEVICES
      select PCI
 -    select HART
      select SERIAL
      select GOLDFISH_RTC
      select VIRTIO_MMIO
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
  config MICROCHIP_PFSOC
      bool
 -    select HART
      select SIFIVE
      select SIFIVE_CLINT
      select UNIMP
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@
  riscv_ss = ss.source_set()
  riscv_ss.add(files('boot.c'), fdt)
  riscv_ss.add(files('numa.c'))
 -riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 +riscv_ss.add(files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 --
-.28.0
+.31.1

-[PULL 27/30] hw/riscv: Move sifive_test model to hw/misc
+[PULL 04/33] hw/riscv: virt: Use machine->ram as the system memory
-From: Bin Meng <bin.meng@windriver.com>
+From: Mingwang Li <limingwang@huawei.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+If default main_mem is used to be registered as the system memory,
-should only contain the RISC-V SoC / machine codes plus generic
+other memory cannot be initialized. Therefore, the system memory
-codes. Let's move sifive_test model to hw/misc directory.
+should be initialized to the machine->ram, which consists of the
 default main_mem and other possible memory required by applications,
 such as shared hugepage memory in DPDK.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Also, the mc->defaul_ram_id should be set to the default main_mem,
 such as "riscv_virt_board.ram" for the virt machine.
 Signed-off-by: Mingwang Li <limingwang@huawei.com>
 Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
+Message-id: 20211016030908.40480-1-limingwang@huawei.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => misc}/sifive_test.h | 0
+ hw/riscv/virt.c | 6 ++----
- hw/{riscv => misc}/sifive_test.c         | 2 +-
+file changed, 2 insertions(+), 4 deletions(-)
  hw/riscv/virt.c                          | 2 +-
  hw/misc/Kconfig                          | 3 +++
  hw/misc/meson.build                      | 1 +
  hw/riscv/Kconfig                         | 1 +
  hw/riscv/meson.build                     | 1 -
 files changed, 7 insertions(+), 3 deletions(-)
  rename include/hw/{riscv => misc}/sifive_test.h (100%)
  rename hw/{riscv => misc}/sifive_test.c (98%)
-diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
-similarity index 100%
-rename from include/hw/riscv/sifive_test.h
-rename to include/hw/misc/sifive_test.h
-diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
-similarity index 98%
-rename from hw/riscv/sifive_test.c
-rename to hw/misc/sifive_test.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_test.c
-+++ b/hw/misc/sifive_test.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/module.h"
- #include "sysemu/runstate.h"
- #include "hw/hw.h"
--#include "hw/riscv/sifive_test.h"
-+#include "hw/misc/sifive_test.h"
- static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
- {
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
- #include "hw/char/serial.h"
+     const MemMapEntry *memmap = virt_memmap;
- #include "target/riscv/cpu.h"
+     RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
- #include "hw/riscv/riscv_hart.h"
+     MemoryRegion *system_memory = get_system_memory();
--#include "hw/riscv/sifive_test.h"
+-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- #include "hw/riscv/virt.h"
+     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
- #include "hw/riscv/boot.h"
+     char *plic_hart_config, *soc_name;
- #include "hw/riscv/numa.h"
+     target_ulong start_addr = memmap[VIRT_DRAM].base;
- #include "hw/intc/sifive_clint.h"
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
- #include "hw/intc/sifive_plic.h"
+     }
-+#include "hw/misc/sifive_test.h"
- #include "chardev/char.h"
+     /* register system main memory (actual RAM) */
- #include "sysemu/arch_init.h"
+-    memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
- #include "sysemu/device_tree.h"
+-                           machine->ram_size, &error_fatal);
-diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
+     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
-index XXXXXXX..XXXXXXX 100644
+-        main_mem);
---- a/hw/misc/Kconfig
++        machine->ram);
-+++ b/hw/misc/Kconfig
-@@ -XXX,XX +XXX,XX @@ config MAC_VIA
+     /* create device tree */
- config AVR_POWER
+     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
-     bool
+@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
+     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
-+config SIFIVE_TEST
+     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
-+    bool
+     mc->numa_mem_supported = true;
-+
++    mc->default_ram_id = "riscv_virt_board.ram";
- config SIFIVE_E_PRCI
-     bool
+     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
  softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
  # RISC-V devices
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      select SIFIVE
      select SIFIVE_CLINT
      select SIFIVE_PLIC
 +    select SIFIVE_TEST
  config MICROCHIP_PFSOC
      bool
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 --
-.28.0
+.31.1

-[PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio
+[PULL 05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
-From: Bin Meng <bin.meng@windriver.com>
+From: Frank Chang <frank.chang@sifive.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
-should only contain the RISC-V SoC / machine codes plus generic
+commit: c445593, but other TB_FLAGS bits for rvv and rvh were
-codes. Let's move sifive_gpio model to hw/gpio directory.
+not shift as well so these bits may overlap with each other when
 rvv is enabled.
-Note this also removes the trace-events in the hw/riscv directory,
+Signed-off-by: Frank Chang <frank.chang@sifive.com>
-since gpio is the only supported trace target in that directory.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
+Message-Id: <20211015074627.3957162-2-frank.chang@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/trace.h                         | 1 -
+ target/riscv/cpu.h       | 14 +++++++-------
- include/hw/{riscv => gpio}/sifive_gpio.h | 0
+ target/riscv/translate.c |  2 +-
- include/hw/riscv/sifive_e.h              | 2 +-
+files changed, 8 insertions(+), 8 deletions(-)
  include/hw/riscv/sifive_u.h              | 2 +-
  hw/{riscv => gpio}/sifive_gpio.c         | 2 +-
  hw/gpio/Kconfig                          | 3 +++
  hw/gpio/meson.build                      | 1 +
  hw/gpio/trace-events                     | 6 ++++++
  hw/riscv/Kconfig                         | 2 ++
  hw/riscv/meson.build                     | 1 -
  hw/riscv/trace-events                    | 7 -------
  meson.build                              | 1 -
 files changed, 15 insertions(+), 13 deletions(-)
  delete mode 100644 hw/riscv/trace.h
  rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
  rename hw/{riscv => gpio}/sifive_gpio.c (99%)
  delete mode 100644 hw/riscv/trace-events
-diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/hw/riscv/trace.h
 +++ /dev/null
@@ -1 +0,0 @@
 -#include "trace/trace-hw_riscv.h"
 diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
 similarity index 100%
 rename from include/hw/riscv/sifive_gpio.h
 rename to include/hw/gpio/sifive_gpio.h
 diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_e.h
+--- a/target/riscv/cpu.h
-+++ b/include/hw/riscv/sifive_e.h
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
+ target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
- #include "hw/riscv/riscv_hart.h"
+ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
- #include "hw/riscv/sifive_cpu.h"
--#include "hw/riscv/sifive_gpio.h"
+-#define TB_FLAGS_MMU_MASK   7
-+#include "hw/gpio/sifive_gpio.h"
+ #define TB_FLAGS_PRIV_MMU_MASK                3
+ #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
- #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
+ #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
- #define RISCV_E_SOC(obj) \
+@@ -XXX,XX +XXX,XX @@ typedef CPURISCVState CPUArchState;
-diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
+ typedef RISCVCPU ArchCPU;
  #include "exec/cpu-all.h"
 -FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
 -FIELD(TB_FLAGS, LMUL, 3, 2)
 -FIELD(TB_FLAGS, SEW, 5, 3)
 -FIELD(TB_FLAGS, VILL, 8, 1)
 +FIELD(TB_FLAGS, MEM_IDX, 0, 3)
 +FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
 +FIELD(TB_FLAGS, LMUL, 4, 2)
 +FIELD(TB_FLAGS, SEW, 6, 3)
 +FIELD(TB_FLAGS, VILL, 9, 1)
  /* Is a Hypervisor instruction load/store allowed? */
 -FIELD(TB_FLAGS, HLSX, 9, 1)
 -FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
 +FIELD(TB_FLAGS, HLSX, 10, 1)
 +FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
  bool riscv_cpu_is_32bit(CPURISCVState *env);
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_u.h
+--- a/target/riscv/translate.c
-+++ b/include/hw/riscv/sifive_u.h
++++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
- #include "hw/net/cadence_gem.h"
+     uint32_t tb_flags = ctx->base.tb->flags;
- #include "hw/riscv/riscv_hart.h"
- #include "hw/riscv/sifive_cpu.h"
+     ctx->pc_succ_insn = ctx->base.pc_first;
--#include "hw/riscv/sifive_gpio.h"
+-    ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
-+#include "hw/gpio/sifive_gpio.h"
++    ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
- #include "hw/misc/sifive_u_otp.h"
+     ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
- #include "hw/misc/sifive_u_prci.h"
+     ctx->priv_ver = env->priv_ver;
+ #if !defined(CONFIG_USER_ONLY)
 diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c
 similarity index 99%
 rename from hw/riscv/sifive_gpio.c
 rename to hw/gpio/sifive_gpio.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_gpio.c
 +++ b/hw/gpio/sifive_gpio.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/log.h"
  #include "hw/irq.h"
  #include "hw/qdev-properties.h"
 -#include "hw/riscv/sifive_gpio.h"
 +#include "hw/gpio/sifive_gpio.h"
  #include "migration/vmstate.h"
  #include "trace.h"
 diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/Kconfig
 +++ b/hw/gpio/Kconfig
@@ -XXX,XX +XXX,XX @@ config PL061
  config GPIO_KEY
      bool
 +
 +config SIFIVE_GPIO
 +    bool
 diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/meson.build
 +++ b/hw/gpio/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
  softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
 diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/trace-events
 +++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
  nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
  nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
  nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 +
 +# sifive_gpio.c
 +sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 +sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
 +sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 +sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
      bool
      select HART
      select SIFIVE
 +    select SIFIVE_GPIO
      select SIFIVE_E_PRCI
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select CADENCE
      select HART
      select SIFIVE
 +    select SIFIVE_GPIO
      select SIFIVE_PDMA
      select SIFIVE_U_OTP
      select SIFIVE_U_PRCI
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
 deleted file mode 100644
 index XXXXXXX..XXXXXXX
 --- a/hw/riscv/trace-events
 +++ /dev/null
@@ -XXX,XX +XXX,XX @@
 -# See docs/devel/tracing.txt for syntax documentation.
 -
 -# hw/gpio/sifive_gpio.c
 -sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 -sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
 -sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 -sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 diff --git a/meson.build b/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/meson.build
 +++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
      'hw/watchdog',
      'hw/xen',
      'hw/gpio',
 -    'hw/riscv',
      'migration',
      'net',
      'ui',
 --
-.28.0
+.31.1

-[PULL 21/30] hw/riscv: Move sifive_u_otp model to hw/misc
+[PULL 06/33] target/riscv: Remove some unused macros
-From: Bin Meng <bin.meng@windriver.com>
+From: Alistair Francis <alistair.francis@wdc.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Since commit 1a9540d1f1a
-should only contain the RISC-V SoC / machine codes plus generic
+("target/riscv: Drop support for ISA spec version 1.09.1")
-codes. Let's move sifive_u_otp model to hw/misc directory.
+these definitions are unused, remove them.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alistair.francis@wdc.com
 ---
- include/hw/{riscv => misc}/sifive_u_otp.h | 0
+ target/riscv/cpu_bits.h | 8 --------
- include/hw/riscv/sifive_u.h               | 2 +-
+file changed, 8 deletions(-)
  hw/{riscv => misc}/sifive_u_otp.c         | 2 +-
  hw/misc/Kconfig                           | 3 +++
  hw/misc/meson.build                       | 1 +
  hw/riscv/Kconfig                          | 1 +
  hw/riscv/meson.build                      | 1 -
 files changed, 7 insertions(+), 3 deletions(-)
  rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
  rename hw/{riscv => misc}/sifive_u_otp.c (99%)
-diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 similarity index 100%
 rename from include/hw/riscv/sifive_u_otp.h
 rename to include/hw/misc/sifive_u_otp.h
 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_u.h
+--- a/target/riscv/cpu_bits.h
-+++ b/include/hw/riscv/sifive_u.h
++++ b/target/riscv/cpu_bits.h
 @@ -XXX,XX +XXX,XX @@
- #include "hw/riscv/riscv_hart.h"
+ #define SATP64_ASID         0x0FFFF00000000000ULL
- #include "hw/riscv/sifive_cpu.h"
+ #define SATP64_PPN          0x00000FFFFFFFFFFFULL
- #include "hw/riscv/sifive_gpio.h"
--#include "hw/riscv/sifive_u_otp.h"
+-/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
-+#include "hw/misc/sifive_u_otp.h"
+-#define VM_1_09_MBARE       0
- #include "hw/misc/sifive_u_prci.h"
+-#define VM_1_09_MBB         1
+-#define VM_1_09_MBBID       2
- #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
+-#define VM_1_09_SV32        8
-diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
+-#define VM_1_09_SV39        9
-similarity index 99%
+-#define VM_1_09_SV48        10
-rename from hw/riscv/sifive_u_otp.c
+-
-rename to hw/misc/sifive_u_otp.c
+ /* VM modes (satp.mode) privileged ISA 1.10 */
-index XXXXXXX..XXXXXXX 100644
+ #define VM_1_10_MBARE       0
---- a/hw/riscv/sifive_u_otp.c
+ #define VM_1_10_SV32        1
 +++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/sysbus.h"
  #include "qemu/log.h"
  #include "qemu/module.h"
 -#include "hw/riscv/sifive_u_otp.h"
 +#include "hw/misc/sifive_u_otp.h"
  static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
  {
 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
  config SIFIVE_E_PRCI
      bool
 +config SIFIVE_U_OTP
 +    bool
 +
  config SIFIVE_U_PRCI
      bool
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
  # RISC-V devices
  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
  softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
  # PKUnity SoC devices
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select HART
      select SIFIVE
      select SIFIVE_PDMA
 +    select SIFIVE_U_OTP
      select SIFIVE_U_PRCI
      select UNIMP
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 --
-.28.0
+.31.1

-[PULL 25/30] hw/riscv: Move riscv_htif model to hw/char
+[PULL 07/33] target/riscv: Organise the CPU properties
-From: Bin Meng <bin.meng@windriver.com>
+From: Alistair Francis <alistair.francis@wdc.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Organise the CPU properties so that standard extensions come first
-should only contain the RISC-V SoC / machine codes plus generic
+then followed by experimental extensions.
 codes. Let's move riscv_htif model to hw/char directory.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com
 ---
- include/hw/{riscv => char}/riscv_htif.h | 0
+ target/riscv/cpu.c | 17 ++++++++++-------
- hw/{riscv => char}/riscv_htif.c         | 2 +-
+file changed, 10 insertions(+), 7 deletions(-)
  hw/riscv/spike.c                        | 2 +-
  hw/char/Kconfig                         | 3 +++
  hw/char/meson.build                     | 1 +
  hw/riscv/Kconfig                        | 3 ---
  hw/riscv/meson.build                    | 1 -
 files changed, 6 insertions(+), 6 deletions(-)
  rename include/hw/{riscv => char}/riscv_htif.h (100%)
  rename hw/{riscv => char}/riscv_htif.c (99%)
-diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 similarity index 100%
 rename from include/hw/riscv/riscv_htif.h
 rename to include/hw/char/riscv_htif.h
 diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
 similarity index 99%
 rename from hw/riscv/riscv_htif.c
 rename to hw/char/riscv_htif.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/riscv_htif.c
+--- a/target/riscv/cpu.c
-+++ b/hw/char/riscv_htif.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
- #include "qapi/error.h"
+ }
- #include "qemu/log.h"
- #include "hw/sysbus.h"
+ static Property riscv_cpu_properties[] = {
-+#include "hw/char/riscv_htif.h"
++    /* Defaults for standard extensions */
- #include "hw/char/serial.h"
+     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
- #include "chardev/char.h"
+     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
- #include "chardev/char-fe.h"
+     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
--#include "hw/riscv/riscv_htif.h"
+@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
- #include "qemu/timer.h"
+     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
- #include "qemu/error-report.h"
+     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
+     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
+-    /* This is experimental so mark with 'x-' */
-index XXXXXXX..XXXXXXX 100644
++    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
---- a/hw/riscv/spike.c
++    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-+++ b/hw/riscv/spike.c
++    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
-@@ -XXX,XX +XXX,XX @@
++    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
- #include "hw/loader.h"
++    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
  #include "hw/sysbus.h"
  #include "target/riscv/cpu.h"
 -#include "hw/riscv/riscv_htif.h"
  #include "hw/riscv/riscv_hart.h"
  #include "hw/riscv/spike.h"
  #include "hw/riscv/boot.h"
  #include "hw/riscv/numa.h"
 +#include "hw/char/riscv_htif.h"
  #include "hw/intc/sifive_clint.h"
  #include "chardev/char.h"
  #include "sysemu/arch_init.h"
 diff --git a/hw/char/Kconfig b/hw/char/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/Kconfig
 +++ b/hw/char/Kconfig
@@ -XXX,XX +XXX,XX @@
  config ESCC
      bool
 +config HTIF
 +    bool
 +
- config PARALLEL
++    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-     bool
++
-     default y
++    /* These are experimental so mark with 'x-' */
-diff --git a/hw/char/meson.build b/hw/char/meson.build
+     DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
-index XXXXXXX..XXXXXXX 100644
+     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
---- a/hw/char/meson.build
+     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
-+++ b/hw/char/meson.build
+     DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
+     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
- softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
+     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
- softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
+-    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+-    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-+specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
+-    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
- specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
+-    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
- specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
+     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
- specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
+     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-index XXXXXXX..XXXXXXX 100644
+-    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
---- a/hw/riscv/Kconfig
+-    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
-+++ b/hw/riscv/Kconfig
+     /* ePMP 0.9.3 */
-@@ -XXX,XX +XXX,XX @@
+     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
 -config HTIF
 -    bool
 -
  config HART
      bool
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 --
-.28.0
+.31.1

-[PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation
+[PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Microchip PolarFire SoC integrates a DMA engine that supports:
+Move the function to cpu_helper.c, as it is large and growing.
 * Independent concurrent DMA transfers using 4 DMA channels
 * Generation of interrupts on various conditions during execution
 which is actually an IP reused from the SiFive FU540 chip.
-This creates a model to support both polling and interrupt modes.
+Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Acked-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20211020031709.359469-2-richard.henderson@linaro.org
 Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/dma/sifive_pdma.h |  57 +++++++
+ target/riscv/cpu.h        | 47 ++-------------------------------------
- hw/dma/sifive_pdma.c         | 313 +++++++++++++++++++++++++++++++++++
+ target/riscv/cpu_helper.c | 46 ++++++++++++++++++++++++++++++++++++++
- hw/dma/Kconfig               |   3 +
+files changed, 48 insertions(+), 45 deletions(-)
  hw/dma/meson.build           |   1 +
 files changed, 374 insertions(+)
  create mode 100644 include/hw/dma/sifive_pdma.h
  create mode 100644 hw/dma/sifive_pdma.c
-diff --git a/include/hw/dma/sifive_pdma.h b/include/hw/dma/sifive_pdma.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/target/riscv/cpu.h
---- /dev/null
++++ b/target/riscv/cpu.h
-+++ b/include/hw/dma/sifive_pdma.h
+@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
-@@ -XXX,XX +XXX,XX @@
+     return cpu->cfg.vlen >> (sew + 3 - lmul);
-+/*
+ }
-+ * SiFive Platform DMA emulation
-+ *
+-static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-+ * Copyright (c) 2020 Wind River Systems, Inc.
+-                                        target_ulong *cs_base, uint32_t *pflags)
-+ *
+-{
-+ * Author:
+-    uint32_t flags = 0;
-+ *   Bin Meng <bin.meng@windriver.com>
+-
-+ *
+-    *pc = env->pc;
-+ * This program is free software; you can redistribute it and/or
+-    *cs_base = 0;
-+ * modify it under the terms of the GNU General Public License as
+-
-+ * published by the Free Software Foundation; either version 2 or
+-    if (riscv_has_ext(env, RVV)) {
-+ * (at your option) version 3 of the License.
+-        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
-+ *
+-        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
-+ * This program is distributed in the hope that it will be useful,
+-        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+-                    FIELD_EX64(env->vtype, VTYPE, VILL));
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
-+ * GNU General Public License for more details.
+-                    FIELD_EX64(env->vtype, VTYPE, VSEW));
-+ *
+-        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
-+ * You should have received a copy of the GNU General Public License along
+-                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
-+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+-        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
-+ */
+-    } else {
 -        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
 -    }
 -
 -#ifdef CONFIG_USER_ONLY
 -    flags |= TB_FLAGS_MSTATUS_FS;
 -#else
 -    flags |= cpu_mmu_index(env, 0);
 -    if (riscv_cpu_fp_enabled(env)) {
 -        flags |= env->mstatus & MSTATUS_FS;
 -    }
 -
 -    if (riscv_has_ext(env, RVH)) {
 -        if (env->priv == PRV_M ||
 -            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 -            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
 -                get_field(env->hstatus, HSTATUS_HU))) {
 -            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
 -        }
 -
 -        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
 -                           get_field(env->mstatus_hs, MSTATUS_FS));
 -    }
 -#endif
 -
 -    *pflags = flags;
 -}
 +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 +                          target_ulong *cs_base, uint32_t *pflags);
  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                             target_ulong *ret_value,
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
  #endif
  }
 +void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 +                          target_ulong *cs_base, uint32_t *pflags)
 +{
 +    uint32_t flags = 0;
 +
-+#ifndef SIFIVE_PDMA_H
++    *pc = env->pc;
-+#define SIFIVE_PDMA_H
++    *cs_base = 0;
 +
-+struct sifive_pdma_chan {
++    if (riscv_has_ext(env, RVV)) {
-+    uint32_t control;
++        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
-+    uint32_t next_config;
++        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
-+    uint64_t next_bytes;
++        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
-+    uint64_t next_dst;
++                    FIELD_EX64(env->vtype, VTYPE, VILL));
-+    uint64_t next_src;
++        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
-+    uint32_t exec_config;
++                    FIELD_EX64(env->vtype, VTYPE, VSEW));
-+    uint64_t exec_bytes;
++        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
-+    uint64_t exec_dst;
++                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
-+    uint64_t exec_src;
++        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
-+    int state;
++    } else {
-+};
++        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
 +
 +#define SIFIVE_PDMA_CHANS           4
 +#define SIFIVE_PDMA_IRQS            (SIFIVE_PDMA_CHANS * 2)
 +#define SIFIVE_PDMA_REG_SIZE        0x100000
 +#define SIFIVE_PDMA_CHAN_NO(reg)    ((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >> 12)
 +
 +typedef struct SiFivePDMAState {
 +    SysBusDevice parent;
 +    MemoryRegion iomem;
 +    qemu_irq irq[SIFIVE_PDMA_IRQS];
 +
 +    struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS];
 +} SiFivePDMAState;
 +
 +#define TYPE_SIFIVE_PDMA    "sifive.pdma"
 +
 +#define SIFIVE_PDMA(obj)    \
 +    OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA)
 +
 +#endif /* SIFIVE_PDMA_H */
 diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/dma/sifive_pdma.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * SiFive Platform DMA emulation
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "qemu/log.h"
 +#include "qapi/error.h"
 +#include "hw/hw.h"
 +#include "hw/irq.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/sysbus.h"
 +#include "migration/vmstate.h"
 +#include "sysemu/dma.h"
 +#include "hw/dma/sifive_pdma.h"
 +
 +#define DMA_CONTROL         0x000
 +#define   CONTROL_CLAIM     BIT(0)
 +#define   CONTROL_RUN       BIT(1)
 +#define   CONTROL_DONE_IE   BIT(14)
 +#define   CONTROL_ERR_IE    BIT(15)
 +#define   CONTROL_DONE      BIT(30)
 +#define   CONTROL_ERR       BIT(31)
 +
 +#define DMA_NEXT_CONFIG     0x004
 +#define   CONFIG_REPEAT     BIT(2)
 +#define   CONFIG_ORDER      BIT(3)
 +#define   CONFIG_WRSZ_SHIFT 24
 +#define   CONFIG_RDSZ_SHIFT 28
 +#define   CONFIG_SZ_MASK    0xf
 +
 +#define DMA_NEXT_BYTES      0x008
 +#define DMA_NEXT_DST        0x010
 +#define DMA_NEXT_SRC        0x018
 +#define DMA_EXEC_CONFIG     0x104
 +#define DMA_EXEC_BYTES      0x108
 +#define DMA_EXEC_DST        0x110
 +#define DMA_EXEC_SRC        0x118
 +
 +enum dma_chan_state {
 +    DMA_CHAN_STATE_IDLE,
 +    DMA_CHAN_STATE_STARTED,
 +    DMA_CHAN_STATE_ERROR,
 +    DMA_CHAN_STATE_DONE
 +};
 +
 +static void sifive_pdma_run(SiFivePDMAState *s, int ch)
 +{
 +    uint64_t bytes = s->chan[ch].next_bytes;
 +    uint64_t dst = s->chan[ch].next_dst;
 +    uint64_t src = s->chan[ch].next_src;
 +    uint32_t config = s->chan[ch].next_config;
 +    int wsize, rsize, size;
 +    uint8_t buf[64];
 +    int n;
 +
 +    /* do nothing if bytes to transfer is zero */
 +    if (!bytes) {
 +        goto error;
 +    }
 +
-+    /*
++#ifdef CONFIG_USER_ONLY
-+     * The manual does not describe how the hardware behaviors when
++    flags |= TB_FLAGS_MSTATUS_FS;
-+     * config.wsize and config.rsize are given different values.
++#else
-+     * A common case is memory to memory DMA, and in this case they
++    flags |= cpu_mmu_index(env, 0);
-+     * are normally the same. Abort if this expectation fails.
++    if (riscv_cpu_fp_enabled(env)) {
-+     */
++        flags |= env->mstatus & MSTATUS_FS;
 +    wsize = (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK;
 +    rsize = (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK;
 +    if (wsize != rsize) {
 +        goto error;
 +    }
 +
-+    /*
++    if (riscv_has_ext(env, RVH)) {
-+     * Calculate the transaction size
++        if (env->priv == PRV_M ||
-+     *
++            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-+     * size field is base 2 logarithm of DMA transaction size,
++            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-+     * but there is an upper limit of 64 bytes per transaction.
++                get_field(env->hstatus, HSTATUS_HU))) {
-+     */
++            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
-+    size = wsize;
++        }
-+    if (size > 6) {
++
-+        size = 6;
++        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
 +                           get_field(env->mstatus_hs, MSTATUS_FS));
 +    }
-+    size = 1 << size;
++#endif
 +
-+    /* the bytes to transfer should be multiple of transaction size */
++    *pflags = flags;
 +    if (bytes % size) {
 +        goto error;
 +    }
 +
 +    /* indicate a DMA transfer is started */
 +    s->chan[ch].state = DMA_CHAN_STATE_STARTED;
 +    s->chan[ch].control &= ~CONTROL_DONE;
 +    s->chan[ch].control &= ~CONTROL_ERR;
 +
 +    /* load the next_ registers into their exec_ counterparts */
 +    s->chan[ch].exec_config = config;
 +    s->chan[ch].exec_bytes = bytes;
 +    s->chan[ch].exec_dst = dst;
 +    s->chan[ch].exec_src = src;
 +
 +    for (n = 0; n < bytes / size; n++) {
 +        cpu_physical_memory_read(s->chan[ch].exec_src, buf, size);
 +        cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size);
 +        s->chan[ch].exec_src += size;
 +        s->chan[ch].exec_dst += size;
 +        s->chan[ch].exec_bytes -= size;
 +    }
 +
 +    /* indicate a DMA transfer is done */
 +    s->chan[ch].state = DMA_CHAN_STATE_DONE;
 +    s->chan[ch].control &= ~CONTROL_RUN;
 +    s->chan[ch].control |= CONTROL_DONE;
 +
 +    /* reload exec_ registers if repeat is required */
 +    if (s->chan[ch].next_config & CONFIG_REPEAT) {
 +        s->chan[ch].exec_bytes = bytes;
 +        s->chan[ch].exec_dst = dst;
 +        s->chan[ch].exec_src = src;
 +    }
 +
 +    return;
 +
 +error:
 +    s->chan[ch].state = DMA_CHAN_STATE_ERROR;
 +    s->chan[ch].control |= CONTROL_ERR;
 +    return;
 +}
 +
-+static inline void sifive_pdma_update_irq(SiFivePDMAState *s, int ch)
+ #ifndef CONFIG_USER_ONLY
-+{
+ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
-+    bool done_ie, err_ie;
+ {
 +
 +    done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE);
 +    err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE);
 +
 +    if (done_ie && (s->chan[ch].control & CONTROL_DONE)) {
 +        qemu_irq_raise(s->irq[ch * 2]);
 +    } else {
 +        qemu_irq_lower(s->irq[ch * 2]);
 +    }
 +
 +    if (err_ie && (s->chan[ch].control & CONTROL_ERR)) {
 +        qemu_irq_raise(s->irq[ch * 2 + 1]);
 +    } else {
 +        qemu_irq_lower(s->irq[ch * 2 + 1]);
 +    }
 +
 +    s->chan[ch].state = DMA_CHAN_STATE_IDLE;
 +}
 +
 +static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    SiFivePDMAState *s = opaque;
 +    int ch = SIFIVE_PDMA_CHAN_NO(offset);
 +    uint64_t val = 0;
 +
 +    if (ch >= SIFIVE_PDMA_CHANS) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
 +                      __func__, ch);
 +        return 0;
 +    }
 +
 +    offset &= 0xfff;
 +    switch (offset) {
 +    case DMA_CONTROL:
 +        val = s->chan[ch].control;
 +        break;
 +    case DMA_NEXT_CONFIG:
 +        val = s->chan[ch].next_config;
 +        break;
 +    case DMA_NEXT_BYTES:
 +        val = s->chan[ch].next_bytes;
 +        break;
 +    case DMA_NEXT_DST:
 +        val = s->chan[ch].next_dst;
 +        break;
 +    case DMA_NEXT_SRC:
 +        val = s->chan[ch].next_src;
 +        break;
 +    case DMA_EXEC_CONFIG:
 +        val = s->chan[ch].exec_config;
 +        break;
 +    case DMA_EXEC_BYTES:
 +        val = s->chan[ch].exec_bytes;
 +        break;
 +    case DMA_EXEC_DST:
 +        val = s->chan[ch].exec_dst;
 +        break;
 +    case DMA_EXEC_SRC:
 +        val = s->chan[ch].exec_src;
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +
 +    return val;
 +}
 +
 +static void sifive_pdma_write(void *opaque, hwaddr offset,
 +                              uint64_t value, unsigned size)
 +{
 +    SiFivePDMAState *s = opaque;
 +    int ch = SIFIVE_PDMA_CHAN_NO(offset);
 +
 +    if (ch >= SIFIVE_PDMA_CHANS) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
 +                      __func__, ch);
 +        return;
 +    }
 +
 +    offset &= 0xfff;
 +    switch (offset) {
 +    case DMA_CONTROL:
 +        s->chan[ch].control = value;
 +
 +        if (value & CONTROL_RUN) {
 +            sifive_pdma_run(s, ch);
 +        }
 +
 +        sifive_pdma_update_irq(s, ch);
 +        break;
 +    case DMA_NEXT_CONFIG:
 +        s->chan[ch].next_config = value;
 +        break;
 +    case DMA_NEXT_BYTES:
 +        s->chan[ch].next_bytes = value;
 +        break;
 +    case DMA_NEXT_DST:
 +        s->chan[ch].next_dst = value;
 +        break;
 +    case DMA_NEXT_SRC:
 +        s->chan[ch].next_src = value;
 +        break;
 +    case DMA_EXEC_CONFIG:
 +    case DMA_EXEC_BYTES:
 +    case DMA_EXEC_DST:
 +    case DMA_EXEC_SRC:
 +        /* these are read-only registers */
 +        break;
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
 +                      __func__, offset);
 +        break;
 +    }
 +}
 +
 +static const MemoryRegionOps sifive_pdma_ops = {
 +    .read = sifive_pdma_read,
 +    .write = sifive_pdma_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    /* there are 32-bit and 64-bit wide registers */
 +    .impl = {
 +        .min_access_size = 4,
 +        .max_access_size = 8,
 +    }
 +};
 +
 +static void sifive_pdma_realize(DeviceState *dev, Error **errp)
 +{
 +    SiFivePDMAState *s = SIFIVE_PDMA(dev);
 +    int i;
 +
 +    memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s,
 +                          TYPE_SIFIVE_PDMA, SIFIVE_PDMA_REG_SIZE);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 +
 +    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
 +        sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
 +    }
 +}
 +
 +static void sifive_pdma_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->desc = "SiFive Platform DMA controller";
 +    dc->realize = sifive_pdma_realize;
 +}
 +
 +static const TypeInfo sifive_pdma_info = {
 +    .name          = TYPE_SIFIVE_PDMA,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(SiFivePDMAState),
 +    .class_init    = sifive_pdma_class_init,
 +};
 +
 +static void sifive_pdma_register_types(void)
 +{
 +    type_register_static(&sifive_pdma_info);
 +}
 +
 +type_init(sifive_pdma_register_types)
 diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/dma/Kconfig
 +++ b/hw/dma/Kconfig
@@ -XXX,XX +XXX,XX @@ config ZYNQ_DEVCFG
  config STP2000
      bool
 +
 +config SIFIVE_PDMA
 +    bool
 diff --git a/hw/dma/meson.build b/hw/dma/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/dma/meson.build
 +++ b/hw/dma/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c'))
  softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c'))
  softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c'))
  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c'))
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c'))
 --
-.28.0
+.31.1

-[PULL 20/30] hw/riscv: Move sifive_u_prci model to hw/misc
+[PULL 09/33] target/riscv: Create RISCVMXL enumeration
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Move the MXL_RV* defines to enumerators.
 should only contain the RISC-V SoC / machine codes plus generic
 codes. Let's move sifive_u_prci model to hw/misc directory.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-3-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => misc}/sifive_u_prci.h | 0
+ target/riscv/cpu_bits.h | 8 +++++---
- include/hw/riscv/sifive_u.h                | 2 +-
+file changed, 5 insertions(+), 3 deletions(-)
  hw/{riscv => misc}/sifive_u_prci.c         | 2 +-
  hw/misc/Kconfig                            | 3 +++
  hw/misc/meson.build                        | 1 +
  hw/riscv/Kconfig                           | 1 +
  hw/riscv/meson.build                       | 1 -
 files changed, 7 insertions(+), 3 deletions(-)
  rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
  rename hw/{riscv => misc}/sifive_u_prci.c (99%)
-diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
+diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 similarity index 100%
 rename from include/hw/riscv/sifive_u_prci.h
 rename to include/hw/misc/sifive_u_prci.h
 diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_u.h
+--- a/target/riscv/cpu_bits.h
-+++ b/include/hw/riscv/sifive_u.h
++++ b/target/riscv/cpu_bits.h
 @@ -XXX,XX +XXX,XX @@
- #include "hw/riscv/riscv_hart.h"
+ #define MISA32_MXL          0xC0000000
- #include "hw/riscv/sifive_cpu.h"
+ #define MISA64_MXL          0xC000000000000000ULL
- #include "hw/riscv/sifive_gpio.h"
--#include "hw/riscv/sifive_u_prci.h"
+-#define MXL_RV32            1
- #include "hw/riscv/sifive_u_otp.h"
+-#define MXL_RV64            2
-+#include "hw/misc/sifive_u_prci.h"
+-#define MXL_RV128           3
++typedef enum {
- #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
++    MXL_RV32  = 1,
- #define RISCV_U_SOC(obj) \
++    MXL_RV64  = 2,
-diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
++    MXL_RV128 = 3,
-similarity index 99%
++} RISCVMXL;
-rename from hw/riscv/sifive_u_prci.c
-rename to hw/misc/sifive_u_prci.c
+ /* sstatus CSR bits */
-index XXXXXXX..XXXXXXX 100644
+ #define SSTATUS_UIE         0x00000001
 --- a/hw/riscv/sifive_u_prci.c
 +++ b/hw/misc/sifive_u_prci.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/sysbus.h"
  #include "qemu/log.h"
  #include "qemu/module.h"
 -#include "hw/riscv/sifive_u_prci.h"
 +#include "hw/misc/sifive_u_prci.h"
  static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
  {
 diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/Kconfig
 +++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
  config SIFIVE_E_PRCI
      bool
 +config SIFIVE_U_PRCI
 +    bool
 +
  source macio/Kconfig
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
  # RISC-V devices
  softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
  # PKUnity SoC devices
  softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select HART
      select SIFIVE
      select SIFIVE_PDMA
 +    select SIFIVE_U_PRCI
      select UNIMP
  config SPIKE
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
  riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 --
-.28.0
+.31.1

-[PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property
+[PULL 10/33] target/riscv: Split misa.mxl and misa.ext
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Currently the reset vector address is hard-coded in a RISC-V CPU's
+The hw representation of misa.mxl is at the high bits of the
-instance_init() routine. In a real world we can have 2 exact same
+misa csr.  Representing this in the same way inside QEMU
-CPUs except for the reset vector address, which is pretty common in
+results in overly complex code trying to check that field.
 the RISC-V core IP licensing business.
-Normally reset vector address is a configurable parameter. Let's
+Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 create a 64-bit property to store the reset vector address which
 covers both 32-bit and 64-bit CPUs.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com>
+Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h | 1 +
+ target/riscv/cpu.h          | 15 +++----
- target/riscv/cpu.c | 1 +
+ linux-user/elfload.c        |  2 +-
-files changed, 2 insertions(+)
+ linux-user/riscv/cpu_loop.c |  2 +-
  target/riscv/cpu.c          | 78 +++++++++++++++++++++----------------
  target/riscv/csr.c          | 44 ++++++++++++++-------
  target/riscv/gdbstub.c      |  8 ++--
  target/riscv/machine.c      | 10 +++--
  target/riscv/translate.c    | 10 +++--
 files changed, 100 insertions(+), 69 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPU {
+@@ -XXX,XX +XXX,XX @@
-         uint16_t elen;
+ #include "exec/cpu-defs.h"
-         bool mmu;
+ #include "fpu/softfloat-types.h"
-         bool pmp;
+ #include "qom/object.h"
-+        uint64_t resetvec;
++#include "cpu_bits.h"
-     } cfg;
- } RISCVCPU;
+ #define TCG_GUEST_DEFAULT_MO 0
@@ -XXX,XX +XXX,XX @@
  # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
  #endif
 -#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
 -#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
 -
  #define RV(x) ((target_ulong)1 << (x - 'A'))
  #define RVI RV('I')
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
      target_ulong priv_ver;
      target_ulong bext_ver;
      target_ulong vext_ver;
 -    target_ulong misa;
 -    target_ulong misa_mask;
 +
 +    /* RISCVMXL, but uint32_t for vmstate migration */
 +    uint32_t misa_mxl;      /* current mxl */
 +    uint32_t misa_mxl_max;  /* max mxl for this cpu */
 +    uint32_t misa_ext;      /* current extensions */
 +    uint32_t misa_ext_mask; /* max ext for this cpu */
      uint32_t features;
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
  static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
  {
 -    return (env->misa & ext) != 0;
 +    return (env->misa_ext & ext) != 0;
  }
  static inline bool riscv_feature(CPURISCVState *env, int feature)
@@ -XXX,XX +XXX,XX @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
  }
  #include "cpu_user.h"
 -#include "cpu_bits.h"
  extern const char * const riscv_int_regnames[];
  extern const char * const riscv_fpr_regnames[];
 diff --git a/linux-user/elfload.c b/linux-user/elfload.c
 index XXXXXXX..XXXXXXX 100644
 --- a/linux-user/elfload.c
 +++ b/linux-user/elfload.c
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
      uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
                      | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
 -    return cpu->env.misa & mask;
 +    return cpu->env.misa_ext & mask;
  #undef MISA_BIT
  }
 diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
 index XXXXXXX..XXXXXXX 100644
 --- a/linux-user/riscv/cpu_loop.c
 +++ b/linux-user/riscv/cpu_loop.c
@@ -XXX,XX +XXX,XX @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
      env->gpr[xSP] = regs->sp;
      env->elf_flags = info->elf_flags;
 -    if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
 +    if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
          error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
          exit(EXIT_FAILURE);
      }
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
+@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
-     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+ bool riscv_cpu_is_32bit(CPURISCVState *env)
-     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ {
-+    DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+-    if (env->misa & RV64) {
-     DEFINE_PROP_END_OF_LIST(),
+-        return false;
- };
+-    }
+-
 -    return true;
 +    return env->misa_mxl == MXL_RV32;
  }
 -static void set_misa(CPURISCVState *env, target_ulong misa)
 +static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
  {
 -    env->misa_mask = env->misa = misa;
 +    env->misa_mxl_max = env->misa_mxl = mxl;
 +    env->misa_ext_mask = env->misa_ext = ext;
  }
  static void set_priv_version(CPURISCVState *env, int priv_ver)
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
  #if defined(TARGET_RISCV32)
 -    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 +    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
  #elif defined(TARGET_RISCV64)
 -    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 +    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
  #endif
      set_priv_version(env, PRIV_VERSION_1_11_0);
  }
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
 -    set_misa(env, RV64);
 +    set_misa(env, MXL_RV64, 0);
  }
  static void rv64_sifive_u_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 +    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
  }
  static void rv64_sifive_e_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
 +    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
  }
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
 -    set_misa(env, RV32);
 +    set_misa(env, MXL_RV32, 0);
  }
  static void rv32_sifive_u_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
 +    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
  }
  static void rv32_sifive_e_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
 +    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
  }
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
  static void rv32_ibex_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV32 | RVI | RVM | RVC | RVU);
 +    set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
      qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
  static void rv32_imafcu_nommu_cpu_init(Object *obj)
  {
      CPURISCVState *env = &RISCV_CPU(obj)->env;
 -    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
 +    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
      set_resetvec(env, DEFAULT_RSTVEC);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
      mcc->parent_reset(dev);
  #ifndef CONFIG_USER_ONLY
 +    env->misa_mxl = env->misa_mxl_max;
      env->priv = PRV_M;
      env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
      env->mcause = 0;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
      CPURISCVState *env = &cpu->env;
      RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
      int priv_version = 0;
 -    target_ulong target_misa = env->misa;
      Error *local_err = NULL;
      cpu_exec_realizefn(cs, &local_err);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
      set_resetvec(env, cpu->cfg.resetvec);
 -    /* If only XLEN is set for misa, then set misa from properties */
 -    if (env->misa == RV32 || env->misa == RV64) {
 +    /* Validate that MISA_MXL is set properly. */
 +    switch (env->misa_mxl_max) {
 +#ifdef TARGET_RISCV64
 +    case MXL_RV64:
 +        break;
 +#endif
 +    case MXL_RV32:
 +        break;
 +    default:
 +        g_assert_not_reached();
 +    }
 +    assert(env->misa_mxl_max == env->misa_mxl);
 +
 +    /* If only MISA_EXT is unset for misa, then set it from properties */
 +    if (env->misa_ext == 0) {
 +        uint32_t ext = 0;
 +
          /* Do some ISA extension error checking */
          if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
              error_setg(errp,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
          /* Set the ISA extensions, checks should have happened above */
          if (cpu->cfg.ext_i) {
 -            target_misa |= RVI;
 +            ext |= RVI;
          }
          if (cpu->cfg.ext_e) {
 -            target_misa |= RVE;
 +            ext |= RVE;
          }
          if (cpu->cfg.ext_m) {
 -            target_misa |= RVM;
 +            ext |= RVM;
          }
          if (cpu->cfg.ext_a) {
 -            target_misa |= RVA;
 +            ext |= RVA;
          }
          if (cpu->cfg.ext_f) {
 -            target_misa |= RVF;
 +            ext |= RVF;
          }
          if (cpu->cfg.ext_d) {
 -            target_misa |= RVD;
 +            ext |= RVD;
          }
          if (cpu->cfg.ext_c) {
 -            target_misa |= RVC;
 +            ext |= RVC;
          }
          if (cpu->cfg.ext_s) {
 -            target_misa |= RVS;
 +            ext |= RVS;
          }
          if (cpu->cfg.ext_u) {
 -            target_misa |= RVU;
 +            ext |= RVU;
          }
          if (cpu->cfg.ext_h) {
 -            target_misa |= RVH;
 +            ext |= RVH;
          }
          if (cpu->cfg.ext_v) {
              int vext_version = VEXT_VERSION_0_07_1;
 -            target_misa |= RVV;
 +            ext |= RVV;
              if (!is_power_of_2(cpu->cfg.vlen)) {
                  error_setg(errp,
                          "Vector extension VLEN must be power of 2");
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
              set_vext_version(env, vext_version);
          }
 -        set_misa(env, target_misa);
 +        set_misa(env, env->misa_mxl, ext);
      }
      riscv_cpu_register_gdb_regs_for_features(cs);
@@ -XXX,XX +XXX,XX @@ char *riscv_isa_string(RISCVCPU *cpu)
      char *isa_str = g_new(char, maxlen);
      char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
      for (i = 0; i < sizeof(riscv_exts); i++) {
 -        if (cpu->env.misa & RV(riscv_exts[i])) {
 +        if (cpu->env.misa_ext & RV(riscv_exts[i])) {
              *p++ = qemu_tolower(riscv_exts[i]);
          }
      }
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
  {
  #if !defined(CONFIG_USER_ONLY)
      /* loose check condition for fcsr in vector extension */
 -    if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
 +    if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) {
          return RISCV_EXCP_NONE;
      }
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
  static RISCVException vs(CPURISCVState *env, int csrno)
  {
 -    if (env->misa & RVV) {
 +    if (env->misa_ext & RVV) {
          return RISCV_EXCP_NONE;
      }
      return RISCV_EXCP_ILLEGAL_INST;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
  static RISCVException read_misa(CPURISCVState *env, int csrno,
                                  target_ulong *val)
  {
 -    *val = env->misa;
 +    target_ulong misa;
 +
 +    switch (env->misa_mxl) {
 +    case MXL_RV32:
 +        misa = (target_ulong)MXL_RV32 << 30;
 +        break;
 +#ifdef TARGET_RISCV64
 +    case MXL_RV64:
 +        misa = (target_ulong)MXL_RV64 << 62;
 +        break;
 +#endif
 +    default:
 +        g_assert_not_reached();
 +    }
 +
 +    *val = misa | env->misa_ext;
      return RISCV_EXCP_NONE;
  }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
 +    /*
 +     * misa.MXL writes are not supported by QEMU.
 +     * Drop writes to those bits.
 +     */
 +
      /* Mask extensions that are not supported by this hart */
 -    val &= env->misa_mask;
 +    val &= env->misa_ext_mask;
      /* Mask extensions that are not supported by QEMU */
      val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
          val &= ~RVC;
      }
 -    /* misa.MXL writes are not supported by QEMU */
 -    if (riscv_cpu_is_32bit(env)) {
 -        val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
 -    } else {
 -        val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
 +    /* If nothing changed, do nothing. */
 +    if (val == env->misa_ext) {
 +        return RISCV_EXCP_NONE;
      }
      /* flush translation cache */
 -    if (val != env->misa) {
 -        tb_flush(env_cpu(env));
 -    }
 -
 -    env->misa = val;
 -
 +    tb_flush(env_cpu(env));
 +    env->misa_ext = val;
      return RISCV_EXCP_NONE;
  }
 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/gdbstub.c
 +++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
  static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
  {
      if (n < 32) {
 -        if (env->misa & RVD) {
 +        if (env->misa_ext & RVD) {
              return gdb_get_reg64(buf, env->fpr[n]);
          }
 -        if (env->misa & RVF) {
 +        if (env->misa_ext & RVF) {
              return gdb_get_reg32(buf, env->fpr[n]);
          }
      /* there is hole between ft11 and fflags in fpu.xml */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
  {
      RISCVCPU *cpu = RISCV_CPU(cs);
      CPURISCVState *env = &cpu->env;
 -    if (env->misa & RVD) {
 +    if (env->misa_ext & RVD) {
          gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
 , "riscv-64bit-fpu.xml", 0);
 -    } else if (env->misa & RVF) {
 +    } else if (env->misa_ext & RVF) {
          gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
 , "riscv-32bit-fpu.xml", 0);
      }
 diff --git a/target/riscv/machine.c b/target/riscv/machine.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/machine.c
 +++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
  const VMStateDescription vmstate_riscv_cpu = {
      .name = "cpu",
 -    .version_id = 2,
 -    .minimum_version_id = 2,
 +    .version_id = 3,
 +    .minimum_version_id = 3,
      .fields = (VMStateField[]) {
          VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
          VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
          VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
          VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
          VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
 -        VMSTATE_UINTTL(env.misa, RISCVCPU),
 -        VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
 +        VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
 +        VMSTATE_UINT32(env.misa_ext, RISCVCPU),
 +        VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
 +        VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
          VMSTATE_UINT32(env.features, RISCVCPU),
          VMSTATE_UINTTL(env.priv, RISCVCPU),
          VMSTATE_UINTTL(env.virt, RISCVCPU),
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      /* pc_succ_insn points to the instruction following base.pc_next */
      target_ulong pc_succ_insn;
      target_ulong priv_ver;
 -    target_ulong misa;
 +    RISCVMXL xl;
 +    uint32_t misa_ext;
      uint32_t opcode;
      uint32_t mstatus_fs;
      uint32_t mstatus_hs_fs;
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
  {
 -    return ctx->misa & ext;
 +    return ctx->misa_ext & ext;
  }
  #ifdef TARGET_RISCV32
@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
  #else
  static inline bool is_32bit(DisasContext *ctx)
  {
 -    return (ctx->misa & RV32) == RV32;
 +    return ctx->xl == MXL_RV32;
  }
  #endif
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
  #else
      ctx->virt_enabled = false;
  #endif
 -    ctx->misa = env->misa;
 +    ctx->xl = env->misa_mxl;
 +    ctx->misa_ext = env->misa_ext;
      ctx->frm = -1;  /* unknown rounding mode */
      ctx->ext_ifencei = cpu->cfg.ext_ifencei;
      ctx->vlen = cpu->cfg.vlen;
 --
-.28.0
+.31.1

-[PULL 17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency
+[PULL 11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-At present the CLINT timestamp is using a hard-coded timebase
+Shortly, the set of supported XL will not be just 32 and 64,
-frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
+and representing that properly using the enumeration will be
-true for all boards.
+imperative.
-Add a new 'timebase-freq' property to the CLINT device, and
+Two places, booting and gdb, intentionally use misa_mxl_max
-update various functions to accept this as a parameter.
+to emphasize the use of the reset value of misa.mxl, and not
+the current cpu state.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/sifive_clint.h |  4 +++-
+ target/riscv/cpu.h            |  9 ++++++++-
- target/riscv/cpu.h              |  6 ++++--
+ hw/riscv/boot.c               |  2 +-
- hw/riscv/microchip_pfsoc.c      |  6 +++++-
+ semihosting/arm-compat-semi.c |  2 +-
- hw/riscv/sifive_clint.c         | 26 +++++++++++++++-----------
+ target/riscv/cpu.c            | 24 ++++++++++++++----------
- hw/riscv/sifive_e.c             |  3 ++-
+ target/riscv/cpu_helper.c     | 12 ++++++------
- hw/riscv/sifive_u.c             |  3 ++-
+ target/riscv/csr.c            | 24 ++++++++++++------------
- hw/riscv/spike.c                |  3 ++-
+ target/riscv/gdbstub.c        |  2 +-
- hw/riscv/virt.c                 |  3 ++-
+ target/riscv/monitor.c        |  4 ++--
- target/riscv/cpu_helper.c       |  4 +++-
+files changed, 45 insertions(+), 34 deletions(-)
- target/riscv/csr.c              |  4 ++--
 files changed, 40 insertions(+), 22 deletions(-)
 diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/riscv/sifive_clint.h
 +++ b/include/hw/riscv/sifive_clint.h
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState {
      uint32_t timecmp_base;
      uint32_t time_base;
      uint32_t aperture_size;
 +    uint32_t timebase_freq;
  } SiFiveCLINTState;
  DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
      uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
 -    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
 +    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
 +    bool provide_rdtime);
  enum {
      SIFIVE_SIP_BASE     = 0x0,
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
+@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VILL, 9, 1)
-     pmp_table_t pmp_state;
+ FIELD(TB_FLAGS, HLSX, 10, 1)
+ FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
-     /* machine specific rdtime callback */
--    uint64_t (*rdtime_fn)(void);
+-bool riscv_cpu_is_32bit(CPURISCVState *env);
-+    uint64_t (*rdtime_fn)(uint32_t);
++#ifdef TARGET_RISCV32
-+    uint32_t rdtime_fn_arg;
++#define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
++#else
-     /* True if in debugger mode.  */
++static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
-     bool debugger;
++{
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
++    return env->misa_mxl;
- int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
++}
- uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
++#endif
- #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
--void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
+ /*
-+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+  * A simplification for VLMAX
-+                             uint32_t arg);
+diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/boot.c
 +++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@
  bool riscv_is_32bit(RISCVHartArrayState *harts)
  {
 -    return riscv_cpu_is_32bit(&harts->harts[0].env);
 +    return harts->harts[0].env.misa_mxl_max == MXL_RV32;
  }
  target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
 diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/semihosting/arm-compat-semi.c
 +++ b/semihosting/arm-compat-semi.c
@@ -XXX,XX +XXX,XX @@ static inline bool is_64bit_semihosting(CPUArchState *env)
  #if defined(TARGET_ARM)
      return is_a64(env);
  #elif defined(TARGET_RISCV)
 -    return !riscv_cpu_is_32bit(env);
 +    return riscv_cpu_mxl(env) != MXL_RV32;
  #else
  #error un-handled architecture
  #endif
- void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
+--- a/target/riscv/cpu.c
-index XXXXXXX..XXXXXXX 100644
++++ b/target/riscv/cpu.c
---- a/hw/riscv/microchip_pfsoc.c
+@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
-+++ b/hw/riscv/microchip_pfsoc.c
+     }
-@@ -XXX,XX +XXX,XX @@
+ }
- #define BIOS_FILENAME   "hss.bin"
- #define RESET_VECTOR    0x20220000
+-bool riscv_cpu_is_32bit(CPURISCVState *env)
+-{
-+/* CLINT timebase frequency */
+-    return env->misa_mxl == MXL_RV32;
-+#define CLINT_TIMEBASE_FREQ 1000000
+-}
 -
  static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
  {
      env->misa_mxl_max = env->misa_mxl = mxl;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
  #ifndef CONFIG_USER_ONLY
      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
      qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
                       (target_ulong)(env->mstatus >> 32));
      }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
  static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
  {
      RISCVCPU *cpu = RISCV_CPU(s);
 -    if (riscv_cpu_is_32bit(&cpu->env)) {
 +
- /* GEM version */
++    switch (riscv_cpu_mxl(&cpu->env)) {
- #define GEM_REVISION    0x0107010c
++    case MXL_RV32:
+         info->print_insn = print_insn_riscv32;
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+-    } else {
-     /* CLINT */
++        break;
-     sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
++    case MXL_RV64:
-         memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
+         info->print_insn = print_insn_riscv64;
--        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
++        break;
-+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
++    default:
-+        CLINT_TIMEBASE_FREQ, false);
++        g_assert_not_reached();
+     }
      /* L2 cache controller */
      create_unimplemented_device("microchip.pfsoc.l2cc",
 diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_clint.c
 +++ b/hw/riscv/sifive_clint.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/riscv/sifive_clint.h"
  #include "qemu/timer.h"
 -static uint64_t cpu_riscv_read_rtc(void)
 +static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
  {
      return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 -        SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
 +        timebase_freq, NANOSECONDS_PER_SECOND);
  }
- /*
+@@ -XXX,XX +XXX,XX @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
-  * Called when timecmp is written to update the QEMU timer or immediately
+     RISCVCPU *cpu = RISCV_CPU(cs);
-  * trigger timer interrupt if mtimecmp <= current timer value.
+     CPURISCVState *env = &cpu->env;
-  */
--static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
+-    if (riscv_cpu_is_32bit(env)) {
-+static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
++    switch (riscv_cpu_mxl(env)) {
-+                                       uint32_t timebase_freq)
++    case MXL_RV32:
- {
+         return g_strdup("riscv:rv32");
-     uint64_t next;
+-    } else {
-     uint64_t diff;
++    case MXL_RV64:
+         return g_strdup("riscv:rv64");
--    uint64_t rtc_r = cpu_riscv_read_rtc();
++    default:
-+    uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
++        g_assert_not_reached();
+     }
      cpu->env.timecmp = value;
      if (cpu->env.timecmp <= rtc_r) {
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
      diff = cpu->env.timecmp - rtc_r;
      /* back to ns (note args switched in muldiv64) */
      next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
 -        muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
 +        muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
      timer_mod(cpu->env.timer, next);
  }
-@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
-         }
-     } else if (addr == clint->time_base) {
-         /* time_lo */
--        return cpu_riscv_read_rtc() & 0xFFFFFFFF;
-+        return cpu_riscv_read_rtc(clint->timebase_freq) & 0xFFFFFFFF;
-     } else if (addr == clint->time_base + 4) {
-         /* time_hi */
--        return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
-+        return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0xFFFFFFFF;
-     }
-     error_report("clint: invalid read: %08x", (uint32_t)addr);
-@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
-             /* timecmp_lo */
-             uint64_t timecmp_hi = env->timecmp >> 32;
-             sifive_clint_write_timecmp(RISCV_CPU(cpu),
--                timecmp_hi << 32 | (value & 0xFFFFFFFF));
-+                timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_freq);
-             return;
-         } else if ((addr & 0x7) == 4) {
-             /* timecmp_hi */
-             uint64_t timecmp_lo = env->timecmp;
-             sifive_clint_write_timecmp(RISCV_CPU(cpu),
--                value << 32 | (timecmp_lo & 0xFFFFFFFF));
-+                value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_freq);
-         } else {
-             error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
-         }
-@@ -XXX,XX +XXX,XX @@ static Property sifive_clint_properties[] = {
-     DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
-     DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
-     DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
-+    DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0),
-     DEFINE_PROP_END_OF_LIST(),
- };
-@@ -XXX,XX +XXX,XX @@ type_init(sifive_clint_register_types)
-  */
- DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
-     uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
--    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
-+    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
-+    bool provide_rdtime)
- {
-     int i;
-     for (i = 0; i < num_harts; i++) {
-@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
-             continue;
-         }
-         if (provide_rdtime) {
--            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc);
-+            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
-         }
-         env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
-                                   &sifive_clint_timer_cb, cpu);
-@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
-     qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
-     qdev_prop_set_uint32(dev, "time-base", time_base);
-     qdev_prop_set_uint32(dev, "aperture-size", size);
-+    qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
-     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
-     return dev;
-diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_e.c
-+++ b/hw/riscv/sifive_e.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
-         memmap[SIFIVE_E_PLIC].size);
-     sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
-         memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
--        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
-+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-+        SIFIVE_CLINT_TIMEBASE_FREQ, false);
-     create_unimplemented_device("riscv.sifive.e.aon",
-         memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
-     sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
-         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
-     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
-         memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
--        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
-+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-+        SIFIVE_CLINT_TIMEBASE_FREQ, false);
-     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
-         return;
-diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
-+++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
-         sifive_clint_create(
-             memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
-             memmap[SPIKE_CLINT].size, base_hartid, hart_count,
--            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
-+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-+            SIFIVE_CLINT_TIMEBASE_FREQ, false);
-     }
-     /* register system main memory (actual RAM) */
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/virt.c
-+++ b/hw/riscv/virt.c
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
-         sifive_clint_create(
-             memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
-             memmap[VIRT_CLINT].size, base_hartid, hart_count,
--            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
-+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-+            SIFIVE_CLINT_TIMEBASE_FREQ, true);
-         /* Per-socket PLIC hart topology configuration string */
-         plic_hart_config_len =
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
-     return old;
- }
+ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
+ {
--void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
+-    uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
-+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
++    uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
-+                             uint32_t arg)
+     uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
- {
+                             MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
-     env->rdtime_fn = fn;
+                             MSTATUS64_UXL | sd;
-+    env->rdtime_fn_arg = arg;
+@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
- }
+     if (first_stage == true) {
- void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
+         if (use_background) {
 -            if (riscv_cpu_is_32bit(env)) {
 +            if (riscv_cpu_mxl(env) == MXL_RV32) {
                  base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
                  vm = get_field(env->vsatp, SATP32_MODE);
              } else {
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
                  vm = get_field(env->vsatp, SATP64_MODE);
              }
          } else {
 -            if (riscv_cpu_is_32bit(env)) {
 +            if (riscv_cpu_mxl(env) == MXL_RV32) {
                  base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
                  vm = get_field(env->satp, SATP32_MODE);
              } else {
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
          }
          widened = 0;
      } else {
 -        if (riscv_cpu_is_32bit(env)) {
 +        if (riscv_cpu_mxl(env) == MXL_RV32) {
              base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
              vm = get_field(env->hgatp, SATP32_MODE);
          } else {
@@ -XXX,XX +XXX,XX @@ restart:
          }
          target_ulong pte;
 -        if (riscv_cpu_is_32bit(env)) {
 +        if (riscv_cpu_mxl(env) == MXL_RV32) {
              pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
          } else {
              pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
      int page_fault_exceptions, vm;
      uint64_t stap_mode;
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          stap_mode = SATP32_MODE;
      } else {
          stap_mode = SATP64_MODE;
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
+@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
-         return -RISCV_EXCP_ILLEGAL_INST;
+             }
-     }
+             break;
+         }
--    *val = env->rdtime_fn() + delta;
+-        if (riscv_cpu_is_32bit(env)) {
-+    *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
++        if (riscv_cpu_mxl(env) == MXL_RV32) {
-     return 0;
+             switch (csrno) {
- }
+             case CSR_CYCLEH:
+                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
-@@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
+@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
-         return -RISCV_EXCP_ILLEGAL_INST;
-     }
+ static RISCVException ctr32(CPURISCVState *env, int csrno)
+ {
--    *val = (env->rdtime_fn() + delta) >> 32;
+-    if (!riscv_cpu_is_32bit(env)) {
-+    *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
++    if (riscv_cpu_mxl(env) != MXL_RV32) {
-     return 0;
+         return RISCV_EXCP_ILLEGAL_INST;
- }
+     }
- #endif
@@ -XXX,XX +XXX,XX @@ static RISCVException any(CPURISCVState *env, int csrno)
  static RISCVException any32(CPURISCVState *env, int csrno)
  {
 -    if (!riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) != MXL_RV32) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException hmode(CPURISCVState *env, int csrno)
  static RISCVException hmode32(CPURISCVState *env, int csrno)
  {
 -    if (!riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) != MXL_RV32) {
          if (riscv_cpu_virt_enabled(env)) {
              return RISCV_EXCP_ILLEGAL_INST;
          } else {
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
  static int validate_vm(CPURISCVState *env, target_ulong vm)
  {
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          return valid_vm_1_10_32[vm & 0xf];
      } else {
          return valid_vm_1_10_64[vm & 0xf];
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
          MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
          MSTATUS_TW;
 -    if (!riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) != MXL_RV32) {
          /*
           * RV32: MPV and GVA are not in mstatus. The current plan is to
           * add them to mstatush. For now, we just don't support it.
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
      dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
              ((mstatus & MSTATUS_XS) == MSTATUS_XS);
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
      } else {
          mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
  {
      target_ulong mask = (sstatus_v1_10_mask);
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          mask |= SSTATUS32_SD;
      } else {
          mask |= SSTATUS64_SD;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
          return RISCV_EXCP_NONE;
      }
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          vm = validate_vm(env, get_field(val, SATP32_MODE));
          mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
          asid = (val ^ env->satp) & SATP32_ASID;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
                                     target_ulong *val)
  {
      *val = env->hstatus;
 -    if (!riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) != MXL_RV32) {
          /* We only support 64-bit VSXL */
          *val = set_field(*val, HSTATUS_VSXL, 2);
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno,
                                      target_ulong val)
  {
      env->hstatus = val;
 -    if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
 +    if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
          qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
      }
      if (get_field(val, HSTATUS_VSBE) != 0) {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
          return RISCV_EXCP_ILLEGAL_INST;
      }
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
      } else {
          env->htimedelta = val;
 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/gdbstub.c
 +++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
      CPURISCVState *env = &cpu->env;
      GString *s = g_string_new(NULL);
      riscv_csr_predicate_fn predicate;
 -    int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
 +    int bitsize = 16 << env->misa_mxl_max;
      int i;
      g_string_printf(s, "<?xml version=\"1.0\"?>");
 diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/monitor.c
 +++ b/target/riscv/monitor.c
@@ -XXX,XX +XXX,XX @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
      target_ulong last_size;
      int last_attr;
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
          vm = get_field(env->satp, SATP32_MODE);
      } else {
@@ -XXX,XX +XXX,XX @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
          return;
      }
 -    if (riscv_cpu_is_32bit(env)) {
 +    if (riscv_cpu_mxl(env) == MXL_RV32) {
          if (!(env->satp & SATP32_MODE)) {
              monitor_printf(mon, "No translation or protection\n");
              return;
 --
-.28.0
+.31.1

-[PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap
+[PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS
-From: Yifei Jiang <jiangyifei@huawei.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-When the cause number is equal to or greater than 23, print "(unknown)" in
+Begin adding support for switching XLEN at runtime.  Extract the
-trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
+effective XLEN from MISA and MSTATUS and store for use during translation.
 excpetion "guest_store_page_fault" can not be printed.
-In addition, the current check of cause is invalid for riscv_intr_names. So
+Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 introduce riscv_cpu_get_trap_name to get the trap cause name.
 Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
 Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-6-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  1 +
+ target/riscv/cpu.h        |  2 ++
- target/riscv/cpu.c        | 11 +++++++++++
+ target/riscv/cpu.c        |  8 ++++++++
- target/riscv/cpu_helper.c |  4 ++--
+ target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++
-files changed, 14 insertions(+), 2 deletions(-)
+ target/riscv/csr.c        |  3 +++
  target/riscv/translate.c  |  2 +-
 files changed, 47 insertions(+), 1 deletion(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ extern const char * const riscv_fpr_regnames[];
+@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VILL, 9, 1)
- extern const char * const riscv_excp_names[];
+ /* Is a Hypervisor instruction load/store allowed? */
- extern const char * const riscv_intr_names[];
+ FIELD(TB_FLAGS, HLSX, 10, 1)
+ FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
-+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
++/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
- void riscv_cpu_do_interrupt(CPUState *cpu);
++FIELD(TB_FLAGS, XL, 13, 2)
- int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
- int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+ #ifdef TARGET_RISCV32
  #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ const char * const riscv_intr_names[] = {
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
-     "reserved"
+     env->misa_mxl = env->misa_mxl_max;
- };
+     env->priv = PRV_M;
+     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
-+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
++    if (env->misa_mxl > MXL_RV32) {
-+{
++        /*
-+    if (async) {
++         * The reset status of SXL/UXL is undefined, but mstatus is WARL
-+        return (cause < ARRAY_SIZE(riscv_intr_names)) ?
++         * and we must ensure that the value after init is valid for read.
-+               riscv_intr_names[cause] : "(unknown)";
++         */
-+    } else {
++        env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
-+        return (cause < ARRAY_SIZE(riscv_excp_names)) ?
++        env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
 +               riscv_excp_names[cause] : "(unknown)";
 +    }
-+}
+     env->mcause = 0;
-+
+     env->pc = env->resetvec;
- static void set_misa(CPURISCVState *env, target_ulong misa)
+     env->two_stage_lookup = false;
  {
      env->misa_mask = env->misa = misa;
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
-         }
+ #endif
  }
 +static RISCVMXL cpu_get_xl(CPURISCVState *env)
 +{
 +#if defined(TARGET_RISCV32)
 +    return MXL_RV32;
 +#elif defined(CONFIG_USER_ONLY)
 +    return MXL_RV64;
 +#else
 +    RISCVMXL xl = riscv_cpu_mxl(env);
 +
 +    /*
 +     * When emulating a 32-bit-only cpu, use RV32.
 +     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
 +     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
 +     * back to RV64 for lower privs.
 +     */
 +    if (xl != MXL_RV32) {
 +        switch (env->priv) {
 +        case PRV_M:
 +            break;
 +        case PRV_U:
 +            xl = get_field(env->mstatus, MSTATUS64_UXL);
 +            break;
 +        default: /* PRV_S | PRV_H */
 +            xl = get_field(env->mstatus, MSTATUS64_SXL);
 +            break;
 +        }
 +    }
 +    return xl;
 +#endif
 +}
 +
  void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                            target_ulong *cs_base, uint32_t *pflags)
  {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
      }
+ #endif
--    trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
--        (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
++    flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
-+    trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
++
-+        riscv_cpu_get_trap_name(cause, async));
+     *pflags = flags;
+ }
-     if (env->priv <= PRV_S &&
-             cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
          mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
      } else {
          mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
 +        /* SXL and UXL fields are for now read only */
 +        mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
 +        mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
      }
      env->mstatus = mstatus;
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
  #else
      ctx->virt_enabled = false;
  #endif
 -    ctx->xl = env->misa_mxl;
      ctx->misa_ext = env->misa_ext;
      ctx->frm = -1;  /* unknown rounding mode */
      ctx->ext_ifencei = cpu->cfg.ext_ifencei;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
      ctx->mlen = 1 << (ctx->sew  + 3 - ctx->lmul);
      ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
 +    ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
      ctx->cs = cs;
      ctx->w = false;
      ctx->ntemp = 0;
 --
-.28.0
+.31.1

-[PULL 18/30] hw/riscv: sifive_u: Connect a DMA controller
+[PULL 13/33] target/riscv: Use REQUIRE_64BIT in amo_check64
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
+Use the same REQUIRE_64BIT check that we use elsewhere,
-channels. This connects the exsiting SiFive PDMA model to the SoC,
+rather than open-coding the use of is_32bit.
 and adds its device tree data as well.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-7-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/sifive_u.h | 11 +++++++++++
+ target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
- hw/riscv/sifive_u.c         | 30 ++++++++++++++++++++++++++++++
+file changed, 2 insertions(+), 1 deletion(-)
  hw/riscv/Kconfig            |  1 +
 files changed, 42 insertions(+)
-diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_u.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/include/hw/riscv/sifive_u.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
- #ifndef HW_SIFIVE_U_H
- #define HW_SIFIVE_U_H
+ static bool amo_check64(DisasContext *s, arg_rwdvm* a)
+ {
-+#include "hw/dma/sifive_pdma.h"
+-    return !is_32bit(s) && amo_check(s, a);
- #include "hw/net/cadence_gem.h"
++    REQUIRE_64BIT(s);
- #include "hw/riscv/riscv_hart.h"
++    return amo_check(s, a);
  #include "hw/riscv/sifive_cpu.h"
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveUSoCState {
      SiFiveUPRCIState prci;
      SIFIVEGPIOState gpio;
      SiFiveUOTPState otp;
 +    SiFivePDMAState dma;
      CadenceGEMState gem;
      uint32_t serial;
@@ -XXX,XX +XXX,XX @@ enum {
      SIFIVE_U_MROM,
      SIFIVE_U_CLINT,
      SIFIVE_U_L2CC,
 +    SIFIVE_U_PDMA,
      SIFIVE_U_L2LIM,
      SIFIVE_U_PLIC,
      SIFIVE_U_PRCI,
@@ -XXX,XX +XXX,XX @@ enum {
      SIFIVE_U_GPIO_IRQ13 = 20,
      SIFIVE_U_GPIO_IRQ14 = 21,
      SIFIVE_U_GPIO_IRQ15 = 22,
 +    SIFIVE_U_PDMA_IRQ0 = 23,
 +    SIFIVE_U_PDMA_IRQ1 = 24,
 +    SIFIVE_U_PDMA_IRQ2 = 25,
 +    SIFIVE_U_PDMA_IRQ3 = 26,
 +    SIFIVE_U_PDMA_IRQ4 = 27,
 +    SIFIVE_U_PDMA_IRQ5 = 28,
 +    SIFIVE_U_PDMA_IRQ6 = 29,
 +    SIFIVE_U_PDMA_IRQ7 = 30,
      SIFIVE_U_GEM_IRQ = 0x35
  };
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
   * 4) GPIO (General Purpose Input/Output Controller)
   * 5) OTP (One-Time Programmable) memory with stored serial number
   * 6) GEM (Gigabit Ethernet Controller) and management block
 + * 7) DMA (Direct Memory Access Controller)
   *
   * This board currently generates devicetree dynamically that indicates at least
   * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
      [SIFIVE_U_MROM] =     {     0x1000,     0xf000 },
      [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
      [SIFIVE_U_L2CC] =     {  0x2010000,     0x1000 },
 +    [SIFIVE_U_PDMA] =     {  0x3000000,   0x100000 },
      [SIFIVE_U_L2LIM] =    {  0x8000000,  0x2000000 },
      [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
      [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
      qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
      g_free(nodename);
 +    nodename = g_strdup_printf("/soc/dma@%lx",
 +        (long)memmap[SIFIVE_U_PDMA].base);
 +    qemu_fdt_add_subnode(fdt, nodename);
 +    qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
 +    qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
 +        SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
 +        SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
 +        SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
 +    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
 +    qemu_fdt_setprop_cells(fdt, nodename, "reg",
 +        0x0, memmap[SIFIVE_U_PDMA].base,
 +        0x0, memmap[SIFIVE_U_PDMA].size);
 +    qemu_fdt_setprop_string(fdt, nodename, "compatible",
 +                            "sifive,fu540-c000-pdma");
 +    g_free(nodename);
 +
      nodename = g_strdup_printf("/soc/cache-controller@%lx",
          (long)memmap[SIFIVE_U_L2CC].base);
      qemu_fdt_add_subnode(fdt, nodename);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
      object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
      object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
      object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
 +    object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
  }
- static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
+ GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
                                              SIFIVE_U_GPIO_IRQ0 + i));
      }
 +    /* PDMA */
 +    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
 +
 +    /* Connect PDMA interrupts to the PLIC */
 +    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
 +                           qdev_get_gpio_in(DEVICE(s->plic),
 +                                            SIFIVE_U_PDMA_IRQ0 + i));
 +    }
 +
      qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
      if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
          return;
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select CADENCE
      select HART
      select SIFIVE
 +    select SIFIVE_PDMA
      select UNIMP
  config SPIKE
 --
-.28.0
+.31.1

-[PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
+[PULL 14/33] target/riscv: Properly check SEW in amo_op
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Microchip PolarFire SoC integrates 2 Candence GEMs to provide
+We're currently assuming SEW <= 3, and the "else" from
-IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.
+the SEW == 3 must be less.  Use a switch and explicitly
 bound both SEW and SEQ for all cases.
-On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
+Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 GEM1 connects to a PHY at address 9.
 The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
 must specify 2 '-nic' options from the command line in order to get
 a working ethernet.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com>
+Message-id: 20211020031709.359469-8-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h |  7 ++++++
+ target/riscv/insn_trans/trans_rvv.c.inc | 26 +++++++++++++------------
- hw/riscv/microchip_pfsoc.c         | 39 ++++++++++++++++++++++++++++++
+file changed, 14 insertions(+), 12 deletions(-)
 files changed, 46 insertions(+)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
+         gen_helper_exit_atomic(cpu_env);
- #include "hw/char/mchp_pfsoc_mmuart.h"
+         s->base.is_jmp = DISAS_NORETURN;
- #include "hw/dma/sifive_pdma.h"
+         return true;
-+#include "hw/net/cadence_gem.h"
+-    } else {
- #include "hw/sd/cadence_sdhci.h"
+-        if (s->sew == 3) {
+-            if (!is_32bit(s)) {
- typedef struct MicrochipPFSoCState {
+-                fn = fnsd[seq];
-@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
+-            } else {
-     MchpPfSoCMMUartState *serial3;
+-                /* Check done in amo_check(). */
-     MchpPfSoCMMUartState *serial4;
+-                g_assert_not_reached();
-     SiFivePDMAState dma;
+-            }
-+    CadenceGEMState gem0;
+-        } else {
-+    CadenceGEMState gem1;
+-            assert(seq < ARRAY_SIZE(fnsw));
-     CadenceSDHCIState sdhci;
+-            fn = fnsw[seq];
- } MicrochipPFSoCState;
+-        }
@@ -XXX,XX +XXX,XX @@ enum {
      MICROCHIP_PFSOC_MMUART2,
      MICROCHIP_PFSOC_MMUART3,
      MICROCHIP_PFSOC_MMUART4,
 +    MICROCHIP_PFSOC_GEM0,
 +    MICROCHIP_PFSOC_GEM1,
      MICROCHIP_PFSOC_ENVM_CFG,
      MICROCHIP_PFSOC_ENVM_DATA,
      MICROCHIP_PFSOC_IOSCB_CFG,
@@ -XXX,XX +XXX,XX @@ enum {
      MICROCHIP_PFSOC_DMA_IRQ5 = 10,
      MICROCHIP_PFSOC_DMA_IRQ6 = 11,
      MICROCHIP_PFSOC_DMA_IRQ7 = 12,
 +    MICROCHIP_PFSOC_GEM0_IRQ = 64,
 +    MICROCHIP_PFSOC_GEM1_IRQ = 70,
      MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
      MICROCHIP_PFSOC_MMUART0_IRQ = 90,
      MICROCHIP_PFSOC_MMUART1_IRQ = 91,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
   * 3) MMUARTs (Multi-Mode UART)
   * 4) Cadence eMMC/SDHC controller and an SD card connected to it
   * 5) SiFive Platform DMA (Direct Memory Access Controller)
 + * 6) GEM (Gigabit Ethernet MAC Controller)
   *
   * This board currently generates devicetree dynamically that indicates at least
   * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@
  #define BIOS_FILENAME   "hss.bin"
  #define RESET_VECTOR    0x20220000
 +/* GEM version */
 +#define GEM_REVISION    0x0107010c
 +
  static const struct MemmapEntry {
      hwaddr base;
      hwaddr size;
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
      [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
 +    [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
 +    [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
      [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
      [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
      [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
      object_initialize_child(obj, "dma-controller", &s->dma,
                              TYPE_SIFIVE_PDMA);
 +    object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
 +    object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
 +
      object_initialize_child(obj, "sd-controller", &s->sdhci,
                              TYPE_CADENCE_SDHCI);
  }
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
      MemoryRegion *envm_data = g_new(MemoryRegion, 1);
      char *plic_hart_config;
      size_t plic_hart_config_len;
 +    NICInfo *nd;
      int i;
      sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
          qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
          serial_hd(4));
 +    /* GEMs */
 +
 +    nd = &nd_table[0];
 +    if (nd->used) {
 +        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 +        qdev_set_nic_properties(DEVICE(&s->gem0), nd);
 +    }
 +    nd = &nd_table[1];
 +    if (nd->used) {
 +        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 +        qdev_set_nic_properties(DEVICE(&s->gem1), nd);
 +    }
 +
-+    object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
++    switch (s->sew) {
-+    object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
++    case 0 ... 2:
-+    sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
++        assert(seq < ARRAY_SIZE(fnsw));
-+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
++        fn = fnsw[seq];
-+                    memmap[MICROCHIP_PFSOC_GEM0].base);
++        break;
-+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
++    case 3:
-+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
++        /* XLEN check done in amo_check(). */
-+
++        assert(seq < ARRAY_SIZE(fnsd));
-+    object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
++        fn = fnsd[seq];
-+    object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
++        break;
-+    sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
++    default:
-+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
++        g_assert_not_reached();
-+                    memmap[MICROCHIP_PFSOC_GEM1].base);
+     }
-+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
-+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
+     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
 +
      /* eNVM */
      memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
                             memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
 --
-.28.0
+.31.1

-[PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
+[PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-When cadence_gem model was created for Xilinx boards, the PHY address
+In preparation for RV128, replace a simple predicate
-was hard-coded to 23 in the GEM model. Now that we have introduced a
+with a more versatile test.
 property we can use that to tell GEM model what our PHY address is.
 Change all boards' GEM 'phy-addr' property value to 23, and set the
 PHY address default value to 0 in the GEM model.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-9-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/arm/xilinx_zynq.c | 1 +
+ target/riscv/translate.c | 31 +++++++++++++++++--------------
- hw/arm/xlnx-versal.c | 1 +
+file changed, 17 insertions(+), 14 deletions(-)
  hw/arm/xlnx-zynqmp.c | 2 ++
  hw/net/cadence_gem.c | 6 +++---
 files changed, 7 insertions(+), 3 deletions(-)
-diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xilinx_zynq.c
+--- a/target/riscv/translate.c
-+++ b/hw/arm/xilinx_zynq.c
++++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
+@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
-         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+ }
-         qdev_set_nic_properties(dev, nd);
-     }
+ #ifdef TARGET_RISCV32
-+    object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
+-# define is_32bit(ctx)  true
-     s = SYS_BUS_DEVICE(dev);
++#define get_xl(ctx)    MXL_RV32
-     sysbus_realize_and_unref(s, &error_fatal);
+ #elif defined(CONFIG_USER_ONLY)
-     sysbus_mmio_map(s, 0, base);
+-# define is_32bit(ctx)  false
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
++#define get_xl(ctx)    MXL_RV64
-index XXXXXXX..XXXXXXX 100644
+ #else
---- a/hw/arm/xlnx-versal.c
+-static inline bool is_32bit(DisasContext *ctx)
-+++ b/hw/arm/xlnx-versal.c
++#define get_xl(ctx)    ((ctx)->xl)
-@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
++#endif
-             qemu_check_nic_model(nd, "cadence_gem");
++
-             qdev_set_nic_properties(dev, nd);
++/* The word size for this machine mode. */
-         }
++static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
-+        object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
+ {
-         object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
+-    return ctx->xl == MXL_RV32;
-                                 &error_abort);
++    return 16 << get_xl(ctx);
-         object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
+ }
-diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
+-#endif
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-zynqmp.c
+ /* The word size for this operation. */
-+++ b/hw/arm/xlnx-zynqmp.c
+ static inline int oper_len(DisasContext *ctx)
-@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
-         }
+ static void mark_fs_dirty(DisasContext *ctx)
-         object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
+ {
-                                 &error_abort);
+     TCGv tmp;
-+        object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
+-    target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
-+                                &error_abort);
++    target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
-         object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
-                                 &error_abort);
+     if (ctx->mstatus_fs != MSTATUS_FS) {
-         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
+         /* Remember the state change for the rest of the TB. */
-diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
+@@ -XXX,XX +XXX,XX @@ EX_SH(12)
-index XXXXXXX..XXXXXXX 100644
+     }                              \
---- a/hw/net/cadence_gem.c
+ } while (0)
-+++ b/hw/net/cadence_gem.c
-@@ -XXX,XX +XXX,XX @@
+-#define REQUIRE_32BIT(ctx) do { \
- #define GEM_PHYMNTNC_REG_SHIFT 18
+-    if (!is_32bit(ctx)) {       \
+-        return false;           \
- /* Marvell PHY definitions */
+-    }                           \
--#define BOARD_PHY_ADDRESS    23 /* PHY address we will emulate a device at */
++#define REQUIRE_32BIT(ctx) do {    \
-+#define BOARD_PHY_ADDRESS    0 /* PHY address we will emulate a device at */
++    if (get_xl(ctx) != MXL_RV32) { \
++        return false;              \
- #define PHY_REG_CONTROL      0
++    }                              \
- #define PHY_REG_STATUS       1
+ } while (0)
-@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
-             uint32_t phy_addr, reg_num;
+-#define REQUIRE_64BIT(ctx) do { \
+-    if (is_32bit(ctx)) {        \
-             phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
+-        return false;           \
--            if (phy_addr == s->phy_addr || phy_addr == 0) {
+-    }                           \
-+            if (phy_addr == s->phy_addr) {
++#define REQUIRE_64BIT(ctx) do {    \
-                 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
++    if (get_xl(ctx) < MXL_RV64) {  \
-                 retval &= 0xFFFF0000;
++        return false;              \
-                 retval |= gem_phy_read(s, reg_num);
++    }                              \
-@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
+ } while (0)
-             uint32_t phy_addr, reg_num;
+ static int ex_rvc_register(DisasContext *ctx, int reg)
              phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
 -            if (phy_addr == s->phy_addr || phy_addr == 0) {
 +            if (phy_addr == s->phy_addr) {
                  reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                  gem_phy_write(s, reg_num, val);
              }
 --
-.28.0
+.31.1

-New patch
+[PULL 16/33] target/riscv: Replace DisasContext.w with DisasContext.ol
+From: Richard Henderson <richard.henderson@linaro.org>
 In preparation for RV128, consider more than just "w" for
 operand size modification.  This will be used for the "d"
 insns from RV128 as well.
 Rename oper_len to get_olen to better match get_xlen.
 Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-10-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/translate.c                | 69 ++++++++++++++++---------
  target/riscv/insn_trans/trans_rvb.c.inc |  8 +--
  target/riscv/insn_trans/trans_rvi.c.inc | 18 +++----
  target/riscv/insn_trans/trans_rvm.c.inc | 10 ++--
 files changed, 62 insertions(+), 43 deletions(-)
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
         to any system register, which includes CSR_FRM, so we do not have
         to reset this known value.  */
      int frm;
 -    bool w;
 +    RISCVMXL ol;
      bool virt_enabled;
      bool ext_ifencei;
      bool hlsx;
@@ -XXX,XX +XXX,XX @@ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
      return 16 << get_xl(ctx);
  }
 -/* The word size for this operation. */
 -static inline int oper_len(DisasContext *ctx)
 +/* The operation length, as opposed to the xlen. */
 +#ifdef TARGET_RISCV32
 +#define get_ol(ctx)    MXL_RV32
 +#else
 +#define get_ol(ctx)    ((ctx)->ol)
 +#endif
 +
 +static inline int get_olen(DisasContext *ctx)
  {
 -    return ctx->w ? 32 : TARGET_LONG_BITS;
 +    return 16 << get_ol(ctx);
  }
 -
  /*
   * RISC-V requires NaN-boxing of narrower width floating point values.
   * This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -XXX,XX +XXX,XX @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
          return ctx->zero;
      }
 -    switch (ctx->w ? ext : EXT_NONE) {
 -    case EXT_NONE:
 -        return cpu_gpr[reg_num];
 -    case EXT_SIGN:
 -        t = temp_new(ctx);
 -        tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
 -        return t;
 -    case EXT_ZERO:
 -        t = temp_new(ctx);
 -        tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
 -        return t;
 +    switch (get_ol(ctx)) {
 +    case MXL_RV32:
 +        switch (ext) {
 +        case EXT_NONE:
 +            break;
 +        case EXT_SIGN:
 +            t = temp_new(ctx);
 +            tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
 +            return t;
 +        case EXT_ZERO:
 +            t = temp_new(ctx);
 +            tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
 +            return t;
 +        default:
 +            g_assert_not_reached();
 +        }
 +        break;
 +    case MXL_RV64:
 +        break;
 +    default:
 +        g_assert_not_reached();
      }
 -    g_assert_not_reached();
 +    return cpu_gpr[reg_num];
  }
  static TCGv dest_gpr(DisasContext *ctx, int reg_num)
  {
 -    if (reg_num == 0 || ctx->w) {
 +    if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
          return temp_new(ctx);
      }
      return cpu_gpr[reg_num];
@@ -XXX,XX +XXX,XX @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
  static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
  {
      if (reg_num != 0) {
 -        if (ctx->w) {
 +        switch (get_ol(ctx)) {
 +        case MXL_RV32:
              tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
 -        } else {
 +            break;
 +        case MXL_RV64:
              tcg_gen_mov_tl(cpu_gpr[reg_num], t);
 +            break;
 +        default:
 +            g_assert_not_reached();
          }
      }
  }
@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                               void (*func)(TCGv, TCGv, target_long))
  {
      TCGv dest, src1;
 -    int max_len = oper_len(ctx);
 +    int max_len = get_olen(ctx);
      if (a->shamt >= max_len) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                               void (*func)(TCGv, TCGv, TCGv))
  {
      TCGv dest, src1, src2;
 -    int max_len = oper_len(ctx);
 +    int max_len = get_olen(ctx);
      if (a->shamt >= max_len) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
      TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
      TCGv ext2 = tcg_temp_new();
 -    tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
 +    tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);
      func(dest, src1, ext2);
      gen_set_gpr(ctx, a->rd, dest);
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
      ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
      ctx->cs = cs;
 -    ctx->w = false;
      ctx->ntemp = 0;
      memset(ctx->temp, 0, sizeof(ctx->temp));
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
      CPURISCVState *env = cpu->env_ptr;
      uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
 +    ctx->ol = ctx->xl;
      decode_opc(env, ctx, opcode16);
      ctx->base.pc_next = ctx->pc_succ_insn;
 -    ctx->w = false;
      for (int i = ctx->ntemp - 1; i >= 0; --i) {
          tcg_temp_free(ctx->temp[i]);
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_ZBB(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_ZBB(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_shift(ctx, a, EXT_NONE, gen_rorw);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_ZBB(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_ZBB(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_shift(ctx, a, EXT_NONE, gen_rolw);
  }
 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvi.c.inc
 +++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_and(DisasContext *ctx, arg_and *a)
  static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
  {
      REQUIRE_64BIT(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
  }
  static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
  {
      REQUIRE_64BIT(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
  static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
  {
      REQUIRE_64BIT(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
  }
@@ -XXX,XX +XXX,XX @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
  static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
  {
      REQUIRE_64BIT(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
  }
  static bool trans_addw(DisasContext *ctx, arg_addw *a)
  {
      REQUIRE_64BIT(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
  }
  static bool trans_subw(DisasContext *ctx, arg_subw *a)
  {
      REQUIRE_64BIT(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
  }
  static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
  {
      REQUIRE_64BIT(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
  }
  static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
  {
      REQUIRE_64BIT(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
  }
  static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
  {
      REQUIRE_64BIT(ctx);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
  }
 diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvm.c.inc
 +++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_arith(ctx, a, EXT_SIGN, gen_div);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_arith(ctx, a, EXT_ZERO, gen_divu);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_arith(ctx, a, EXT_SIGN, gen_rem);
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
  {
      REQUIRE_64BIT(ctx);
      REQUIRE_EXT(ctx, RVM);
 -    ctx->w = true;
 +    ctx->ol = MXL_RV32;
      return gen_arith(ctx, a, EXT_ZERO, gen_remu);
  }
 --
 .31.1

-[PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
+[PULL 17/33] target/riscv: Use gen_arith_per_ol for RVM
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-This is an initial support for Microchip PolarFire SoC Icicle Kit.
+The multiply high-part instructions require a separate
-The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
+implementation for RV32 when TARGET_LONG_BITS == 64.
 E51 plus four U54 cores and many on-chip peripherals and an FPGA.
-For more details about Microchip PolarFire Soc, please see:
+Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
 Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
 The following perepherals are created as an unimplemented device:
 - Bus Error Uint 0/1/2/3/4
 - L2 cache controller
 - SYSREG
 - MPUCFG
 - IOSCBCFG
 More devices will be added later.
 The BIOS image used by this machine is hss.bin, aka Hart Software
 Services, which can be built from:
 https://github.com/polarfire-soc/hart-software-services
 To launch this machine:
 $ qemu-system-riscv64 -nographic -M microchip-icicle-kit
 The memory is set to 1 GiB by default to match the hardware.
 A sanity check on ram size is performed in the machine init routine
 to prompt user to increase the RAM size to > 1 GiB when less than
 GiB ram is detected.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-11-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- default-configs/riscv64-softmmu.mak |   1 +
+ target/riscv/translate.c                | 16 +++++++++++++++
- include/hw/riscv/microchip_pfsoc.h  |  88 ++++++++
+ target/riscv/insn_trans/trans_rvm.c.inc | 26 ++++++++++++++++++++++---
- hw/riscv/microchip_pfsoc.c          | 312 ++++++++++++++++++++++++++++
+files changed, 39 insertions(+), 3 deletions(-)
  MAINTAINERS                         |   7 +
  hw/riscv/Kconfig                    |   6 +
  hw/riscv/meson.build                |   1 +
 files changed, 415 insertions(+)
  create mode 100644 include/hw/riscv/microchip_pfsoc.h
  create mode 100644 hw/riscv/microchip_pfsoc.c
-diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/default-configs/riscv64-softmmu.mak
+--- a/target/riscv/translate.c
-+++ b/default-configs/riscv64-softmmu.mak
++++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ CONFIG_SPIKE=y
+@@ -XXX,XX +XXX,XX @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
- CONFIG_SIFIVE_E=y
+     return true;
- CONFIG_SIFIVE_U=y
+ }
- CONFIG_RISCV_VIRT=y
-+CONFIG_MICROCHIP_PFSOC=y
++static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
++                             void (*f_tl)(TCGv, TCGv, TCGv),
-new file mode 100644
++                             void (*f_32)(TCGv, TCGv, TCGv))
-index XXXXXXX..XXXXXXX
++{
---- /dev/null
++    int olen = get_olen(ctx);
 +++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Microchip PolarFire SoC machine interface
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#ifndef HW_MICROCHIP_PFSOC_H
++    if (olen != TARGET_LONG_BITS) {
-+#define HW_MICROCHIP_PFSOC_H
++        if (olen == 32) {
-+
++            f_tl = f_32;
-+typedef struct MicrochipPFSoCState {
++        } else {
-+    /*< private >*/
++            g_assert_not_reached();
-+    DeviceState parent_obj;
++        }
-+
++    }
-+    /*< public >*/
++    return gen_arith(ctx, a, ext, f_tl);
 +    CPUClusterState e_cluster;
 +    CPUClusterState u_cluster;
 +    RISCVHartArrayState e_cpus;
 +    RISCVHartArrayState u_cpus;
 +    DeviceState *plic;
 +} MicrochipPFSoCState;
 +
 +#define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
 +#define MICROCHIP_PFSOC(obj) \
 +    OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
 +
 +typedef struct MicrochipIcicleKitState {
 +    /*< private >*/
 +    MachineState parent_obj;
 +
 +    /*< public >*/
 +    MicrochipPFSoCState soc;
 +} MicrochipIcicleKitState;
 +
 +#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
 +    MACHINE_TYPE_NAME("microchip-icicle-kit")
 +#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
 +    OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
 +                 TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
 +
 +enum {
 +    MICROCHIP_PFSOC_DEBUG,
 +    MICROCHIP_PFSOC_E51_DTIM,
 +    MICROCHIP_PFSOC_BUSERR_UNIT0,
 +    MICROCHIP_PFSOC_BUSERR_UNIT1,
 +    MICROCHIP_PFSOC_BUSERR_UNIT2,
 +    MICROCHIP_PFSOC_BUSERR_UNIT3,
 +    MICROCHIP_PFSOC_BUSERR_UNIT4,
 +    MICROCHIP_PFSOC_CLINT,
 +    MICROCHIP_PFSOC_L2CC,
 +    MICROCHIP_PFSOC_L2LIM,
 +    MICROCHIP_PFSOC_PLIC,
 +    MICROCHIP_PFSOC_SYSREG,
 +    MICROCHIP_PFSOC_MPUCFG,
 +    MICROCHIP_PFSOC_ENVM_CFG,
 +    MICROCHIP_PFSOC_ENVM_DATA,
 +    MICROCHIP_PFSOC_IOSCB_CFG,
 +    MICROCHIP_PFSOC_DRAM,
 +};
 +
 +#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
 +#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
 +
 +#define MICROCHIP_PFSOC_PLIC_HART_CONFIG        "MS"
 +#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        185
 +#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES     7
 +#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x04
 +#define MICROCHIP_PFSOC_PLIC_PENDING_BASE       0x1000
 +#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE        0x2000
 +#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE      0x80
 +#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE       0x200000
 +#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE     0x1000
 +
 +#endif /* HW_MICROCHIP_PFSOC_H */
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
 + *
 + * 0) CLINT (Core Level Interruptor)
 + * 1) PLIC (Platform Level Interrupt Controller)
 + * 2) eNVM (Embedded Non-Volatile Memory)
 + *
 + * This board currently generates devicetree dynamically that indicates at least
 + * two harts and up to five harts.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/error-report.h"
 +#include "qemu/log.h"
 +#include "qemu/units.h"
 +#include "qemu/cutils.h"
 +#include "qapi/error.h"
 +#include "hw/boards.h"
 +#include "hw/irq.h"
 +#include "hw/loader.h"
 +#include "hw/sysbus.h"
 +#include "hw/cpu/cluster.h"
 +#include "target/riscv/cpu.h"
 +#include "hw/misc/unimp.h"
 +#include "hw/riscv/boot.h"
 +#include "hw/riscv/riscv_hart.h"
 +#include "hw/riscv/sifive_clint.h"
 +#include "hw/riscv/sifive_plic.h"
 +#include "hw/riscv/microchip_pfsoc.h"
 +
 +/*
 + * The BIOS image used by this machine is called Hart Software Services (HSS).
 + * See https://github.com/polarfire-soc/hart-software-services
 + */
 +#define BIOS_FILENAME   "hss.bin"
 +#define RESET_VECTOR    0x20220000
 +
 +static const struct MemmapEntry {
 +    hwaddr base;
 +    hwaddr size;
 +} microchip_pfsoc_memmap[] = {
 +    [MICROCHIP_PFSOC_DEBUG] =           {        0x0,     0x1000 },
 +    [MICROCHIP_PFSOC_E51_DTIM] =        {  0x1000000,     0x2000 },
 +    [MICROCHIP_PFSOC_BUSERR_UNIT0] =    {  0x1700000,     0x1000 },
 +    [MICROCHIP_PFSOC_BUSERR_UNIT1] =    {  0x1701000,     0x1000 },
 +    [MICROCHIP_PFSOC_BUSERR_UNIT2] =    {  0x1702000,     0x1000 },
 +    [MICROCHIP_PFSOC_BUSERR_UNIT3] =    {  0x1703000,     0x1000 },
 +    [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
 +    [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
 +    [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
 +    [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
 +    [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
 +    [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
 +    [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
 +    [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
 +    [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
 +    [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
 +    [MICROCHIP_PFSOC_DRAM] =            { 0x80000000,        0x0 },
 +};
 +
 +static void microchip_pfsoc_soc_instance_init(Object *obj)
 +{
 +    MachineState *ms = MACHINE(qdev_get_machine());
 +    MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
 +
 +    object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
 +    qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
 +
 +    object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
 +                            TYPE_RISCV_HART_ARRAY);
 +    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
 +    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
 +    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
 +                         TYPE_RISCV_CPU_SIFIVE_E51);
 +    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
 +
 +    object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
 +    qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
 +
 +    object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
 +                            TYPE_RISCV_HART_ARRAY);
 +    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
 +    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
 +    qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
 +                         TYPE_RISCV_CPU_SIFIVE_U54);
 +    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
 +}
 +
-+static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                               void (*func)(TCGv, TCGv, target_long))
  {
 diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvm.c.inc
 +++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
      tcg_temp_free(discard);
  }
 +static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2)
 +{
-+    MachineState *ms = MACHINE(qdev_get_machine());
++    tcg_gen_mul_tl(ret, s1, s2);
-+    MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
++    tcg_gen_sari_tl(ret, ret, 32);
 +    const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
 +    MemoryRegion *system_memory = get_system_memory();
 +    MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
 +    MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
 +    MemoryRegion *envm_data = g_new(MemoryRegion, 1);
 +    char *plic_hart_config;
 +    size_t plic_hart_config_len;
 +    int i;
 +
 +    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
 +    /*
 +     * The cluster must be realized after the RISC-V hart array container,
 +     * as the container's CPU object is only created on realize, and the
 +     * CPU must exist and have been parented into the cluster before the
 +     * cluster is realized.
 +     */
 +    qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
 +    qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
 +
 +    /* E51 DTIM */
 +    memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
 +                           memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_E51_DTIM].base,
 +                                e51_dtim_mem);
 +
 +    /* Bus Error Units */
 +    create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
 +    create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
 +    create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
 +    create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
 +    create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
 +        memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
 +
 +    /* CLINT */
 +    sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
 +        memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
 +        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
 +
 +    /* L2 cache controller */
 +    create_unimplemented_device("microchip.pfsoc.l2cc",
 +        memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
 +
 +    /*
 +     * Add L2-LIM at reset size.
 +     * This should be reduced in size as the L2 Cache Controller WayEnable
 +     * register is incremented. Unfortunately I don't see a nice (or any) way
 +     * to handle reducing or blocking out the L2 LIM while still allowing it
 +     * be re returned to all enabled after a reset. For the time being, just
 +     * leave it enabled all the time. This won't break anything, but will be
 +     * too generous to misbehaving guests.
 +     */
 +    memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
 +                           memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_L2LIM].base,
 +                                l2lim_mem);
 +
 +    /* create PLIC hart topology configuration string */
 +    plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
 +                           ms->smp.cpus;
 +    plic_hart_config = g_malloc0(plic_hart_config_len);
 +    for (i = 0; i < ms->smp.cpus; i++) {
 +        if (i != 0) {
 +            strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
 +                    plic_hart_config_len);
 +        } else {
 +            strncat(plic_hart_config, "M", plic_hart_config_len);
 +        }
 +        plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
 +    }
 +
 +    /* PLIC */
 +    s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
 +        plic_hart_config, 0,
 +        MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
 +        MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
 +        MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
 +        MICROCHIP_PFSOC_PLIC_PENDING_BASE,
 +        MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
 +        MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
 +        MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
 +        MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
 +        memmap[MICROCHIP_PFSOC_PLIC].size);
 +    g_free(plic_hart_config);
 +
 +    /* SYSREG */
 +    create_unimplemented_device("microchip.pfsoc.sysreg",
 +        memmap[MICROCHIP_PFSOC_SYSREG].base,
 +        memmap[MICROCHIP_PFSOC_SYSREG].size);
 +
 +    /* MPUCFG */
 +    create_unimplemented_device("microchip.pfsoc.mpucfg",
 +        memmap[MICROCHIP_PFSOC_MPUCFG].base,
 +        memmap[MICROCHIP_PFSOC_MPUCFG].size);
 +
 +    /* eNVM */
 +    memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
 +                           memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
 +                           &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
 +                                envm_data);
 +
 +    /* IOSCBCFG */
 +    create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
 +        memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
 +        memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
 +}
 +
-+static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
+ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
  {
      REQUIRE_EXT(ctx, RVM);
 -    return gen_arith(ctx, a, EXT_NONE, gen_mulh);
 +    return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w);
  }
  static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
      tcg_temp_free(rh);
  }
 +static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
 +{
-+    DeviceClass *dc = DEVICE_CLASS(oc);
++    TCGv t1 = tcg_temp_new();
 +    TCGv t2 = tcg_temp_new();
 +
-+    dc->realize = microchip_pfsoc_soc_realize;
++    tcg_gen_ext32s_tl(t1, arg1);
-+    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
++    tcg_gen_ext32u_tl(t2, arg2);
-+    dc->user_creatable = false;
++    tcg_gen_mul_tl(ret, t1, t2);
 +    tcg_temp_free(t1);
 +    tcg_temp_free(t2);
 +    tcg_gen_sari_tl(ret, ret, 32);
 +}
 +
-+static const TypeInfo microchip_pfsoc_soc_type_info = {
+ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
-+    .name = TYPE_MICROCHIP_PFSOC,
+ {
-+    .parent = TYPE_DEVICE,
+     REQUIRE_EXT(ctx, RVM);
-+    .instance_size = sizeof(MicrochipPFSoCState),
+-    return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
-+    .instance_init = microchip_pfsoc_soc_instance_init,
++    return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w);
-+    .class_init = microchip_pfsoc_soc_class_init,
+ }
-+};
-+
+ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
-+static void microchip_pfsoc_soc_register_types(void)
+@@ -XXX,XX +XXX,XX @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
-+{
+ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
-+    type_register_static(&microchip_pfsoc_soc_type_info);
+ {
-+}
+     REQUIRE_EXT(ctx, RVM);
-+
+-    return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
-+type_init(microchip_pfsoc_soc_register_types)
++    /* gen_mulh_w works for either sign as input. */
-+
++    return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w);
-+static void microchip_icicle_kit_machine_init(MachineState *machine)
+ }
-+{
-+    MachineClass *mc = MACHINE_GET_CLASS(machine);
+ static void gen_div(TCGv ret, TCGv source1, TCGv source2)
 +    const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
 +    MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
 +    MemoryRegion *system_memory = get_system_memory();
 +    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 +
 +    /* Sanity check on RAM size */
 +    if (machine->ram_size < mc->default_ram_size) {
 +        char *sz = size_to_str(mc->default_ram_size);
 +        error_report("Invalid RAM size, should be bigger than %s", sz);
 +        g_free(sz);
 +        exit(EXIT_FAILURE);
 +    }
 +
 +    /* Initialize SoC */
 +    object_initialize_child(OBJECT(machine), "soc", &s->soc,
 +                            TYPE_MICROCHIP_PFSOC);
 +    qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 +
 +    /* Register RAM */
 +    memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
 +                           machine->ram_size, &error_fatal);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
 +
 +    /* Load the firmware */
 +    riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
 +}
 +
 +static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
 +{
 +    MachineClass *mc = MACHINE_CLASS(oc);
 +
 +    mc->desc = "Microchip PolarFire SoC Icicle Kit";
 +    mc->init = microchip_icicle_kit_machine_init;
 +    mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
 +                   MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
 +    mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
 +    mc->default_cpus = mc->min_cpus;
 +    mc->default_ram_size = 1 * GiB;
 +}
 +
 +static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
 +    .name       = MACHINE_TYPE_NAME("microchip-icicle-kit"),
 +    .parent     = TYPE_MACHINE,
 +    .class_init = microchip_icicle_kit_machine_class_init,
 +    .instance_size = sizeof(MicrochipIcicleKitState),
 +};
 +
 +static void microchip_icicle_kit_machine_init_register_types(void)
 +{
 +    type_register_static(&microchip_icicle_kit_machine_typeinfo);
 +}
 +
 +type_init(microchip_icicle_kit_machine_init_register_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/opentitan.h
  F: include/hw/char/ibex_uart.h
  F: include/hw/intc/ibex_plic.h
 +Microchip PolarFire SoC Icicle Kit
 +M: Bin Meng <bin.meng@windriver.com>
 +L: qemu-riscv@nongnu.org
 +S: Supported
 +F: hw/riscv/microchip_pfsoc.c
 +F: include/hw/riscv/microchip_pfsoc.h
 +
  RX Machines
  -----------
  rx-gdbsim
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      select PCI_EXPRESS_GENERIC_BRIDGE
      select PFLASH_CFI01
      select SIFIVE
 +
 +config MICROCHIP_PFSOC
 +    bool
 +    select HART
 +    select SIFIVE
 +    select UNIMP
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 +riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
  hw_arch += {'riscv': riscv_ss}
 --
-.28.0
+.31.1

-[PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation
+[PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Microchip PolarFire SoC MMUART is ns16550 compatible, with some
+When target_long is 64-bit, we still want a 32-bit bswap for rev8.
-additional registers. Create a simple MMUART model built on top
+Since this opcode is specific to RV32, we need not conditionalize.
 of the existing ns16550 model.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-12-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++++++++++++++++++
+ target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
- hw/char/mchp_pfsoc_mmuart.c         | 86 +++++++++++++++++++++++++++++
+file changed, 6 insertions(+), 1 deletion(-)
  MAINTAINERS                         |  2 +
  hw/char/Kconfig                     |  3 +
  hw/char/meson.build                 |  1 +
 files changed, 153 insertions(+)
  create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
  create mode 100644 hw/char/mchp_pfsoc_mmuart.c
-diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
+diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/target/riscv/insn_trans/trans_rvb.c.inc
---- /dev/null
++++ b/target/riscv/insn_trans/trans_rvb.c.inc
-+++ b/include/hw/char/mchp_pfsoc_mmuart.h
+@@ -XXX,XX +XXX,XX @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
-@@ -XXX,XX +XXX,XX @@
+     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
-+/*
+ }
-+ * Microchip PolarFire SoC MMUART emulation
-+ *
++static void gen_rev8_32(TCGv ret, TCGv src1)
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a copy
 + * of this software and associated documentation files (the "Software"), to deal
 + * in the Software without restriction, including without limitation the rights
 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 + * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
 +#ifndef HW_MCHP_PFSOC_MMUART_H
 +#define HW_MCHP_PFSOC_MMUART_H
 +
 +#include "hw/char/serial.h"
 +
 +#define MCHP_PFSOC_MMUART_REG_SIZE  52
 +
 +typedef struct MchpPfSoCMMUartState {
 +    MemoryRegion iomem;
 +    hwaddr base;
 +    qemu_irq irq;
 +
 +    SerialMM *serial;
 +
 +    uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
 +} MchpPfSoCMMUartState;
 +
 +/**
 + * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
 + *
 + * This is a helper routine for board to create a MMUART device that is
 + * compatible with Microchip PolarFire SoC.
 + *
 + * @sysmem: system memory region to map
 + * @base: base address of the MMUART registers
 + * @irq: IRQ number of the MMUART device
 + * @chr: character device to associate to
 + *
 + * @return: a pointer to the device specific control structure
 + */
 +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
 +    hwaddr base, qemu_irq irq, Chardev *chr);
 +
 +#endif /* HW_MCHP_PFSOC_MMUART_H */
 diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Microchip PolarFire SoC MMUART emulation
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
 +#include "chardev/char.h"
 +#include "exec/address-spaces.h"
 +#include "hw/char/mchp_pfsoc_mmuart.h"
 +
 +static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
 +{
-+    MchpPfSoCMMUartState *s = opaque;
++    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
 +
 +    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
 +                      __func__, addr);
 +        return 0;
 +    }
 +
 +    return s->reg[addr / sizeof(uint32_t)];
 +}
 +
-+static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
+ static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
-+                                    uint64_t value, unsigned size)
+ {
-+{
+     REQUIRE_32BIT(ctx);
-+    MchpPfSoCMMUartState *s = opaque;
+     REQUIRE_ZBB(ctx);
-+    uint32_t val32 = (uint32_t)value;
+-    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
-+
++    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
-+    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
+ }
-+        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
-+                      " v=0x%x\n", __func__, addr, val32);
+ static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
 +        return;
 +    }
 +
 +    s->reg[addr / sizeof(uint32_t)] = val32;
 +}
 +
 +static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
 +    .read = mchp_pfsoc_mmuart_read,
 +    .write = mchp_pfsoc_mmuart_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .impl = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +    },
 +};
 +
 +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
 +    hwaddr base, qemu_irq irq, Chardev *chr)
 +{
 +    MchpPfSoCMMUartState *s;
 +
 +    s = g_new0(MchpPfSoCMMUartState, 1);
 +
 +    memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
 +                          "mchp.pfsoc.mmuart", 0x1000);
 +
 +    s->base = base;
 +    s->irq = irq;
 +
 +    s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
 +                               DEVICE_LITTLE_ENDIAN);
 +
 +    memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
 +
 +    return s;
 +}
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Bin Meng <bin.meng@windriver.com>
  L: qemu-riscv@nongnu.org
  S: Supported
  F: hw/riscv/microchip_pfsoc.c
 +F: hw/char/mchp_pfsoc_mmuart.c
  F: include/hw/riscv/microchip_pfsoc.h
 +F: include/hw/char/mchp_pfsoc_mmuart.h
  RX Machines
  -----------
 diff --git a/hw/char/Kconfig b/hw/char/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/Kconfig
 +++ b/hw/char/Kconfig
@@ -XXX,XX +XXX,XX @@ config RENESAS_SCI
  config AVR_USART
      bool
 +
 +config MCHP_PFSOC_MMUART
 +    bool
 diff --git a/hw/char/meson.build b/hw/char/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/char/meson.build
 +++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
  softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
  softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
 +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
  specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
  specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
 --
-.28.0
+.31.1

-[PULL 09/30] hw/sd: Add Cadence SDHCI emulation
+[PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
+The count zeros instructions require a separate implementation
-controller. The SDHCI compatible registers start from offset 0x200,
+for RV32 when TARGET_LONG_BITS == 64.
 which are called Slot Register Set (SRS) in its datasheet.
-This creates a Cadence SDHCI model built on top of the existing
+Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
-generic SDHCI model. Cadence specific Host Register Set (HRS) is
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-implemented to make guest software happy.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20211020031709.359469-13-richard.henderson@linaro.org
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/sd/cadence_sdhci.h |  47 +++++++++
+ target/riscv/translate.c                | 16 ++++++++++++
- hw/sd/cadence_sdhci.c         | 193 ++++++++++++++++++++++++++++++++++
+ target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++-------------
- hw/sd/Kconfig                 |   4 +
+files changed, 32 insertions(+), 17 deletions(-)
  hw/sd/meson.build             |   1 +
 files changed, 245 insertions(+)
  create mode 100644 include/hw/sd/cadence_sdhci.h
  create mode 100644 hw/sd/cadence_sdhci.c
-diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-new file mode 100644
+index XXXXXXX..XXXXXXX 100644
-index XXXXXXX..XXXXXXX
+--- a/target/riscv/translate.c
---- /dev/null
++++ b/target/riscv/translate.c
-+++ b/include/hw/sd/cadence_sdhci.h
+@@ -XXX,XX +XXX,XX @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
-@@ -XXX,XX +XXX,XX @@
+     return true;
-+/*
+ }
-+ * Cadence SDHCI emulation
-+ *
++static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
-+ * Copyright (c) 2020 Wind River Systems, Inc.
++                             void (*f_tl)(TCGv, TCGv),
-+ *
++                             void (*f_32)(TCGv, TCGv))
-+ * Author:
++{
-+ *   Bin Meng <bin.meng@windriver.com>
++    int olen = get_olen(ctx);
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
-+#ifndef CADENCE_SDHCI_H
++    if (olen != TARGET_LONG_BITS) {
-+#define CADENCE_SDHCI_H
++        if (olen == 32) {
-+
++            f_tl = f_32;
-+#include "hw/sd/sdhci.h"
++        } else {
-+
++            g_assert_not_reached();
-+#define CADENCE_SDHCI_REG_SIZE  0x100
++        }
-+#define CADENCE_SDHCI_NUM_REGS  (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t))
++    }
-+
++    return gen_unary(ctx, a, ext, f_tl);
 +typedef struct CadenceSDHCIState {
 +    SysBusDevice parent;
 +
 +    MemoryRegion container;
 +    MemoryRegion iomem;
 +    BusState *bus;
 +
 +    uint32_t regs[CADENCE_SDHCI_NUM_REGS];
 +
 +    SDHCIState sdhci;
 +} CadenceSDHCIState;
 +
 +#define TYPE_CADENCE_SDHCI  "cadence.sdhci"
 +#define CADENCE_SDHCI(obj)  OBJECT_CHECK(CadenceSDHCIState, (obj), \
 +                                         TYPE_CADENCE_SDHCI)
 +
 +#endif /* CADENCE_SDHCI_H */
 diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/sd/cadence_sdhci.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * Cadence SDHCI emulation
 + *
 + * Copyright (c) 2020 Wind River Systems, Inc.
 + *
 + * Author:
 + *   Bin Meng <bin.meng@windriver.com>
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 or
 + * (at your option) version 3 of the License.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License along
 + * with this program; if not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/bitops.h"
 +#include "qemu/error-report.h"
 +#include "qemu/log.h"
 +#include "qapi/error.h"
 +#include "migration/vmstate.h"
 +#include "hw/irq.h"
 +#include "hw/sd/cadence_sdhci.h"
 +#include "sdhci-internal.h"
 +
 +/* HRS - Host Register Set (specific to Cadence) */
 +
 +#define CADENCE_SDHCI_HRS00             0x00    /* general information */
 +#define CADENCE_SDHCI_HRS00_SWR             BIT(0)
 +#define CADENCE_SDHCI_HRS00_POR_VAL         0x00010000
 +
 +#define CADENCE_SDHCI_HRS04             0x10    /* PHY access port */
 +#define CADENCE_SDHCI_HRS04_WR              BIT(24)
 +#define CADENCE_SDHCI_HRS04_RD              BIT(25)
 +#define CADENCE_SDHCI_HRS04_ACK             BIT(26)
 +
 +#define CADENCE_SDHCI_HRS06             0x18    /* eMMC control */
 +#define CADENCE_SDHCI_HRS06_TUNE_UP         BIT(15)
 +
 +/* SRS - Slot Register Set (SDHCI-compatible) */
 +
 +#define CADENCE_SDHCI_SRS_BASE          0x200
 +
 +#define TO_REG(addr)    ((addr) / sizeof(uint32_t))
 +
 +static void cadence_sdhci_instance_init(Object *obj)
 +{
 +    CadenceSDHCIState *s = CADENCE_SDHCI(obj);
 +
 +    object_initialize_child(OBJECT(s), "generic-sdhci",
 +                            &s->sdhci, TYPE_SYSBUS_SDHCI);
 +}
 +
-+static void cadence_sdhci_reset(DeviceState *dev)
+ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
  {
      DisasContext *ctx = container_of(dcbase, DisasContext, base);
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
      tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
  }
 +static void gen_clzw(TCGv ret, TCGv arg1)
 +{
-+    CadenceSDHCIState *s = CADENCE_SDHCI(dev);
++    TCGv t = tcg_temp_new();
-+
++    tcg_gen_shli_tl(t, arg1, 32);
-+    memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE);
++    tcg_gen_clzi_tl(ret, t, 32);
-+    s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL;
++    tcg_temp_free(t);
 +
 +    device_cold_reset(DEVICE(&s->sdhci));
 +}
 +
-+static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
+ static bool trans_clz(DisasContext *ctx, arg_clz *a)
  {
      REQUIRE_ZBB(ctx);
 -    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
 +    return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
  }
  static void gen_ctz(TCGv ret, TCGv arg1)
@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
      tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
  }
 +static void gen_ctzw(TCGv ret, TCGv arg1)
 +{
-+    CadenceSDHCIState *s = opaque;
++    tcg_gen_ctzi_tl(ret, arg1, 32);
 +    uint32_t val;
 +
 +    val = s->regs[TO_REG(addr)];
 +
 +    return (uint64_t)val;
 +}
 +
-+static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
+ static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
-+                                unsigned int size)
+ {
-+{
+     REQUIRE_ZBB(ctx);
-+    CadenceSDHCIState *s = opaque;
+-    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
-+    uint32_t val32 = (uint32_t)val;
++    return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
-+
+ }
-+    switch (addr) {
-+    case CADENCE_SDHCI_HRS00:
+ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
-+        /*
+@@ -XXX,XX +XXX,XX @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
-+         * The only writable bit is SWR (software reset) and it automatically
+     return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
-+         * clears to zero, so essentially this register remains unchanged.
+ }
-+         */
-+        if (val32 & CADENCE_SDHCI_HRS00_SWR) {
+-static void gen_clzw(TCGv ret, TCGv arg1)
-+            cadence_sdhci_reset(DEVICE(s));
+-{
-+        }
+-    TCGv t = tcg_temp_new();
-+
+-    tcg_gen_shli_tl(t, arg1, 32);
-+        break;
+-    tcg_gen_clzi_tl(ret, t, 32);
-+    case CADENCE_SDHCI_HRS04:
+-    tcg_temp_free(t);
-+        /*
+-}
-+         * Only emulate the ACK bit behavior when read or write transaction
+-
-+         * are requested.
+ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
-+         */
+ {
-+        if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) {
+     REQUIRE_64BIT(ctx);
-+            val32 |= CADENCE_SDHCI_HRS04_ACK;
+@@ -XXX,XX +XXX,XX @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
-+        } else {
+     return gen_unary(ctx, a, EXT_NONE, gen_clzw);
-+            val32 &= ~CADENCE_SDHCI_HRS04_ACK;
+ }
-+        }
-+
+-static void gen_ctzw(TCGv ret, TCGv arg1)
-+        s->regs[TO_REG(addr)] = val32;
+-{
-+        break;
+-    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-+    case CADENCE_SDHCI_HRS06:
+-    tcg_gen_ctzi_tl(ret, ret, 64);
-+        if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) {
+-}
-+            val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP;
+-
-+        }
+ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
-+
+ {
-+        s->regs[TO_REG(addr)] = val32;
+     REQUIRE_64BIT(ctx);
-+        break;
+     REQUIRE_ZBB(ctx);
-+    default:
+-    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
-+        s->regs[TO_REG(addr)] = val32;
++    return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
-+        break;
+ }
-+    }
-+}
+ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
 +
 +static const MemoryRegionOps cadence_sdhci_ops = {
 +    .read = cadence_sdhci_read,
 +    .write = cadence_sdhci_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .impl = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +    },
 +    .valid = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +    }
 +};
 +
 +static void cadence_sdhci_realize(DeviceState *dev, Error **errp)
 +{
 +    CadenceSDHCIState *s = CADENCE_SDHCI(dev);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 +    SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci);
 +
 +    memory_region_init(&s->container, OBJECT(s),
 +                       "cadence.sdhci-container", 0x1000);
 +    sysbus_init_mmio(sbd, &s->container);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops,
 +                          s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE);
 +    memory_region_add_subregion(&s->container, 0, &s->iomem);
 +
 +    sysbus_realize(sbd_sdhci, errp);
 +    memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE,
 +                                sysbus_mmio_get_region(sbd_sdhci, 0));
 +
 +    /* propagate irq and "sd-bus" from generic-sdhci */
 +    sysbus_pass_irq(sbd, sbd_sdhci);
 +    s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus");
 +}
 +
 +static const VMStateDescription vmstate_cadence_sdhci = {
 +    .name = TYPE_CADENCE_SDHCI,
 +    .version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS),
 +        VMSTATE_END_OF_LIST(),
 +    },
 +};
 +
 +static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(classp);
 +
 +    dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)";
 +    dc->realize = cadence_sdhci_realize;
 +    dc->reset = cadence_sdhci_reset;
 +    dc->vmsd = &vmstate_cadence_sdhci;
 +}
 +
 +static TypeInfo cadence_sdhci_info = {
 +    .name          = TYPE_CADENCE_SDHCI,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(CadenceSDHCIState),
 +    .instance_init = cadence_sdhci_instance_init,
 +    .class_init    = cadence_sdhci_class_init,
 +};
 +
 +static void cadence_sdhci_register_types(void)
 +{
 +    type_register_static(&cadence_sdhci_info);
 +}
 +
 +type_init(cadence_sdhci_register_types)
 diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/sd/Kconfig
 +++ b/hw/sd/Kconfig
@@ -XXX,XX +XXX,XX @@ config SDHCI_PCI
      default y if PCI_DEVICES
      depends on PCI
      select SDHCI
 +
 +config CADENCE_SDHCI
 +    bool
 +    select SDHCI
 diff --git a/hw/sd/meson.build b/hw/sd/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/sd/meson.build
 +++ b/hw/sd/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_mmci.c'))
  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c'))
  softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))
  softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))
 +softmmu_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))
 --
-.28.0
+.31.1

-New patch
+[PULL 20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI
+From: Richard Henderson <richard.henderson@linaro.org>
 Most shift instructions require a separate implementation
 for RV32 when TARGET_LONG_BITS == 64.
 Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-14-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  target/riscv/translate.c                | 31 +++++++++
  target/riscv/insn_trans/trans_rvb.c.inc | 92 ++++++++++++++-----------
  target/riscv/insn_trans/trans_rvi.c.inc | 26 +++----
 files changed, 97 insertions(+), 52 deletions(-)
 diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
      return true;
  }
 +static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a,
 +                                    DisasExtend ext,
 +                                    void (*f_tl)(TCGv, TCGv, target_long),
 +                                    void (*f_32)(TCGv, TCGv, target_long))
 +{
 +    int olen = get_olen(ctx);
 +    if (olen != TARGET_LONG_BITS) {
 +        if (olen == 32) {
 +            f_tl = f_32;
 +        } else {
 +            g_assert_not_reached();
 +        }
 +    }
 +    return gen_shift_imm_fn(ctx, a, ext, f_tl);
 +}
 +
  static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                               void (*func)(TCGv, TCGv, TCGv))
  {
@@ -XXX,XX +XXX,XX @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
      return true;
  }
 +static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
 +                             void (*f_tl)(TCGv, TCGv, TCGv),
 +                             void (*f_32)(TCGv, TCGv, TCGv))
 +{
 +    int olen = get_olen(ctx);
 +    if (olen != TARGET_LONG_BITS) {
 +        if (olen == 32) {
 +            f_tl = f_32;
 +        } else {
 +            g_assert_not_reached();
 +        }
 +    }
 +    return gen_shift(ctx, a, ext, f_tl);
 +}
 +
  static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
                        void (*func)(TCGv, TCGv))
  {
 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvb.c.inc
 +++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
      return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
  }
 +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    TCGv_i32 t1 = tcg_temp_new_i32();
 +    TCGv_i32 t2 = tcg_temp_new_i32();
 +
 +    /* truncate to 32-bits */
 +    tcg_gen_trunc_tl_i32(t1, arg1);
 +    tcg_gen_trunc_tl_i32(t2, arg2);
 +
 +    tcg_gen_rotr_i32(t1, t1, t2);
 +
 +    /* sign-extend 64-bits */
 +    tcg_gen_ext_i32_tl(ret, t1);
 +
 +    tcg_temp_free_i32(t1);
 +    tcg_temp_free_i32(t2);
 +}
 +
  static bool trans_ror(DisasContext *ctx, arg_ror *a)
  {
      REQUIRE_ZBB(ctx);
 -    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
 +    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw);
 +}
 +
 +static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
 +{
 +    TCGv_i32 t1 = tcg_temp_new_i32();
 +
 +    tcg_gen_trunc_tl_i32(t1, arg1);
 +    tcg_gen_rotri_i32(t1, t1, shamt);
 +    tcg_gen_ext_i32_tl(ret, t1);
 +
 +    tcg_temp_free_i32(t1);
  }
  static bool trans_rori(DisasContext *ctx, arg_rori *a)
  {
      REQUIRE_ZBB(ctx);
 -    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
 +    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
 +                                   tcg_gen_rotri_tl, gen_roriw);
 +}
 +
 +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
 +{
 +    TCGv_i32 t1 = tcg_temp_new_i32();
 +    TCGv_i32 t2 = tcg_temp_new_i32();
 +
 +    /* truncate to 32-bits */
 +    tcg_gen_trunc_tl_i32(t1, arg1);
 +    tcg_gen_trunc_tl_i32(t2, arg2);
 +
 +    tcg_gen_rotl_i32(t1, t1, t2);
 +
 +    /* sign-extend 64-bits */
 +    tcg_gen_ext_i32_tl(ret, t1);
 +
 +    tcg_temp_free_i32(t1);
 +    tcg_temp_free_i32(t2);
  }
  static bool trans_rol(DisasContext *ctx, arg_rol *a)
  {
      REQUIRE_ZBB(ctx);
 -    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
 +    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw);
  }
  static void gen_rev8_32(TCGv ret, TCGv src1)
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
      return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
  }
 -static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv_i32 t1 = tcg_temp_new_i32();
 -    TCGv_i32 t2 = tcg_temp_new_i32();
 -
 -    /* truncate to 32-bits */
 -    tcg_gen_trunc_tl_i32(t1, arg1);
 -    tcg_gen_trunc_tl_i32(t2, arg2);
 -
 -    tcg_gen_rotr_i32(t1, t1, t2);
 -
 -    /* sign-extend 64-bits */
 -    tcg_gen_ext_i32_tl(ret, t1);
 -
 -    tcg_temp_free_i32(t1);
 -    tcg_temp_free_i32(t2);
 -}
 -
  static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
      REQUIRE_64BIT(ctx);
      REQUIRE_ZBB(ctx);
      ctx->ol = MXL_RV32;
 -    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
 -}
 -
 -static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
 -{
 -    TCGv_i32 t1 = tcg_temp_new_i32();
 -    TCGv_i32 t2 = tcg_temp_new_i32();
 -
 -    /* truncate to 32-bits */
 -    tcg_gen_trunc_tl_i32(t1, arg1);
 -    tcg_gen_trunc_tl_i32(t2, arg2);
 -
 -    tcg_gen_rotl_i32(t1, t1, t2);
 -
 -    /* sign-extend 64-bits */
 -    tcg_gen_ext_i32_tl(ret, t1);
 -
 -    tcg_temp_free_i32(t1);
 -    tcg_temp_free_i32(t2);
 +    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw);
  }
  static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
 diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvi.c.inc
 +++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_slli(DisasContext *ctx, arg_slli *a)
      return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
  }
 +static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
 +{
 +    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
 +}
 +
  static bool trans_srli(DisasContext *ctx, arg_srli *a)
  {
 -    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
 +    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
 +                                   tcg_gen_shri_tl, gen_srliw);
 +}
 +
 +static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
 +{
 +    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
  }
  static bool trans_srai(DisasContext *ctx, arg_srai *a)
  {
 -    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
 +    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
 +                                   tcg_gen_sari_tl, gen_sraiw);
  }
  static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
      return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
  }
 -static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
 -{
 -    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
 -}
 -
  static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
  {
      REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
  }
 -static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
 -{
 -    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
 -}
 -
  static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
  {
      REQUIRE_64BIT(ctx);
 --
 .31.1

-[PULL 13/30] hw/net: cadence_gem: Add a new 'phy-addr' property
+[PULL 21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-At present the PHY address of the PHY connected to GEM is hard-coded
+Use the official debug read interface to the csrs,
-to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
+rather than referencing the env slots directly.
-all boards. Add a new 'phy-addr' property so that board can specify
+Put the list of csrs to dump into a table.
 the PHY address for each GEM instance.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-15-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/net/cadence_gem.h | 2 ++
+ target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
- hw/net/cadence_gem.c         | 5 +++--
+file changed, 45 insertions(+), 44 deletions(-)
 files changed, 5 insertions(+), 2 deletions(-)
-diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/net/cadence_gem.h
+--- a/target/riscv/cpu.c
-+++ b/include/hw/net/cadence_gem.h
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
+@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-     /* Mask of register bits which are write 1 to clear */
+ #endif
-     uint32_t regs_w1c[CADENCE_GEM_MAXREG];
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
+ #ifndef CONFIG_USER_ONLY
-+    /* PHY address */
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
-+    uint8_t phy_addr;
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
-     /* PHY registers backing store */
+-    if (riscv_cpu_mxl(env) == MXL_RV32) {
-     uint16_t phy_regs[32];
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
+-                     (target_ulong)(env->mstatus >> 32));
-diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
+-    }
-index XXXXXXX..XXXXXXX 100644
+-    if (riscv_has_ext(env, RVH)) {
---- a/hw/net/cadence_gem.c
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
-+++ b/hw/net/cadence_gem.c
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus",
-@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
+-                     (target_ulong)env->vsstatus);
-             uint32_t phy_addr, reg_num;
+-    }
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
-             phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
--            if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
-+            if (phy_addr == s->phy_addr || phy_addr == 0) {
+-    if (riscv_has_ext(env, RVH)) {
-                 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
-                 retval &= 0xFFFF0000;
+-    }
-                 retval |= gem_phy_read(s, reg_num);
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
-@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
+-    if (riscv_has_ext(env, RVH)) {
-             uint32_t phy_addr, reg_num;
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
+-    }
-             phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
--            if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
-+            if (phy_addr == s->phy_addr || phy_addr == 0) {
+-    if (riscv_has_ext(env, RVH)) {
-                 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
-                 gem_phy_write(s, reg_num, val);
+-    }
-             }
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
-@@ -XXX,XX +XXX,XX @@ static Property gem_properties[] = {
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
-     DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
+-    if (riscv_has_ext(env, RVH)) {
-     DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
-                        GEM_MODID_VALUE),
+-    }
-+    DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
-     DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
+-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
-                       num_priority_queues, 1),
+-    if (riscv_has_ext(env, RVH)) {
-     DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
+-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
 -    }
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
 -    if (riscv_has_ext(env, RVH)) {
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval   ", env->htval);
 -        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2  ", env->mtval2);
 +    {
 +        static const int dump_csrs[] = {
 +            CSR_MHARTID,
 +            CSR_MSTATUS,
 +            CSR_MSTATUSH,
 +            CSR_HSTATUS,
 +            CSR_VSSTATUS,
 +            CSR_MIP,
 +            CSR_MIE,
 +            CSR_MIDELEG,
 +            CSR_HIDELEG,
 +            CSR_MEDELEG,
 +            CSR_HEDELEG,
 +            CSR_MTVEC,
 +            CSR_STVEC,
 +            CSR_VSTVEC,
 +            CSR_MEPC,
 +            CSR_SEPC,
 +            CSR_VSEPC,
 +            CSR_MCAUSE,
 +            CSR_SCAUSE,
 +            CSR_VSCAUSE,
 +            CSR_MTVAL,
 +            CSR_STVAL,
 +            CSR_HTVAL,
 +            CSR_MTVAL2,
 +            CSR_MSCRATCH,
 +            CSR_SSCRATCH,
 +            CSR_SATP,
 +        };
 +
 +        for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
 +            int csrno = dump_csrs[i];
 +            target_ulong val = 0;
 +            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
 +
 +            /*
 +             * Rely on the smode, hmode, etc, predicates within csr.c
 +             * to do the filtering of the registers that are present.
 +             */
 +            if (res == RISCV_EXCP_NONE) {
 +                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
 +                             csr_ops[csrno].name, val);
 +            }
 +        }
      }
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
 -    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp    ", env->satp);
  #endif
      for (i = 0; i < 32; i++) {
 --
-.28.0
+.31.1

-[PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
+[PULL 22/33] target/riscv: Compute mstatus.sd on demand
-From: Bin Meng <bin.meng@windriver.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Microchip PolarFire SoC integrates one Cadence SDHCI controller.
+The position of this read-only field is dependent on the current xlen.
-On the Icicle Kit board, one eMMC chip and an external SD card
+Rather than having to compute that difference in many places, compute
-connect to this controller depending on different configuration.
+it only on read.
-As QEMU does not support eMMC yet, we just emulate the SD card
-configuration. To test this, the Hart Software Services (HSS)
-should choose the SD card configuration:
-$ cp boards/icicle-kit-es/def_config.sdcard .config
-$ make BOARD=icicle-kit-es
-The SD card image can be built from the Yocto BSP at:
-https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp
-Note the generated SD card image should be resized before use:
-$ qemu-img resize /path/to/sdcard.img 4G
-Launch QEMU with the following command:
-$ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20211020031709.359469-16-richard.henderson@linaro.org
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h |  4 ++++
+ target/riscv/cpu_helper.c |  3 +--
- hw/riscv/microchip_pfsoc.c         | 23 +++++++++++++++++++++++
+ target/riscv/csr.c        | 37 ++++++++++++++++++++++---------------
- hw/riscv/Kconfig                   |  1 +
+ target/riscv/translate.c  |  5 ++---
-files changed, 28 insertions(+)
+files changed, 25 insertions(+), 20 deletions(-)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/target/riscv/cpu_helper.c
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
- #define HW_MICROCHIP_PFSOC_H
+ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
- #include "hw/char/mchp_pfsoc_mmuart.h"
+ {
-+#include "hw/sd/cadence_sdhci.h"
+-    uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
+     uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
- typedef struct MicrochipPFSoCState {
+                             MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
-     /*< private >*/
+-                            MSTATUS64_UXL | sd;
-@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
++                            MSTATUS64_UXL;
-     MchpPfSoCMMUartState *serial2;
+     bool current_virt = riscv_cpu_virt_enabled(env);
-     MchpPfSoCMMUartState *serial3;
-     MchpPfSoCMMUartState *serial4;
+     g_assert(riscv_has_ext(env, RVH));
-+    CadenceSDHCIState sdhci;
+diff --git a/target/riscv/csr.c b/target/riscv/csr.c
  } MicrochipPFSoCState;
  #define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
@@ -XXX,XX +XXX,XX @@ enum {
      MICROCHIP_PFSOC_MMUART0,
      MICROCHIP_PFSOC_SYSREG,
      MICROCHIP_PFSOC_MPUCFG,
 +    MICROCHIP_PFSOC_EMMC_SD,
      MICROCHIP_PFSOC_MMUART1,
      MICROCHIP_PFSOC_MMUART2,
      MICROCHIP_PFSOC_MMUART3,
@@ -XXX,XX +XXX,XX @@ enum {
  };
  enum {
 +    MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
      MICROCHIP_PFSOC_MMUART0_IRQ = 90,
      MICROCHIP_PFSOC_MMUART1_IRQ = 91,
      MICROCHIP_PFSOC_MMUART2_IRQ = 92,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
+--- a/target/riscv/csr.c
-+++ b/hw/riscv/microchip_pfsoc.c
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno,
-  * 1) PLIC (Platform Level Interrupt Controller)
+ }
-  * 2) eNVM (Embedded Non-Volatile Memory)
-  * 3) MMUARTs (Multi-Mode UART)
+ /* Machine Trap Setup */
 + * 4) Cadence eMMC/SDHC controller and an SD card connected to it
   *
   * This board currently generates devicetree dynamically that indicates at least
   * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
      [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
      [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
      [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
 +    [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
      [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
      qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
                           TYPE_RISCV_CPU_SIFIVE_U54);
      qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
 +
-+    object_initialize_child(obj, "sd-controller", &s->sdhci,
++/* We do not store SD explicitly, only compute it on demand. */
-+                            TYPE_CADENCE_SDHCI);
++static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
 +{
 +    if ((status & MSTATUS_FS) == MSTATUS_FS ||
 +        (status & MSTATUS_XS) == MSTATUS_XS) {
 +        switch (xl) {
 +        case MXL_RV32:
 +            return status | MSTATUS32_SD;
 +        case MXL_RV64:
 +            return status | MSTATUS64_SD;
 +        default:
 +            g_assert_not_reached();
 +        }
 +    }
 +    return status;
 +}
 +
  static RISCVException read_mstatus(CPURISCVState *env, int csrno,
                                     target_ulong *val)
  {
 -    *val = env->mstatus;
 +    *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
      return RISCV_EXCP_NONE;
  }
- static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+ {
-         memmap[MICROCHIP_PFSOC_MPUCFG].base,
+     uint64_t mstatus = env->mstatus;
-         memmap[MICROCHIP_PFSOC_MPUCFG].size);
+     uint64_t mask = 0;
+-    int dirty;
-+    /* SDHCI */
-+    sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
+     /* flush tlb on mstatus fields that affect VM */
-+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
+     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
-+                    memmap[MICROCHIP_PFSOC_EMMC_SD].base);
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
-+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
-+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
+     mstatus = (mstatus & ~mask) | (val & mask);
-+
-     /* MMUARTs */
+-    dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
-     s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
+-            ((mstatus & MSTATUS_XS) == MSTATUS_XS);
-         memmap[MICROCHIP_PFSOC_MMUART0].base,
+-    if (riscv_cpu_mxl(env) == MXL_RV32) {
-@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
+-        mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
-     MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
+-    } else {
-     MemoryRegion *system_memory = get_system_memory();
+-        mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
-     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
++    if (riscv_cpu_mxl(env) == MXL_RV64) {
-+    DriveInfo *dinfo = drive_get_next(IF_SD);
+         /* SXL and UXL fields are for now read only */
+         mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
-     /* Sanity check on RAM size */
+         mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
-     if (machine->ram_size < mc->default_ram_size) {
+@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
-@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
+ {
+     target_ulong mask = (sstatus_v1_10_mask);
-     /* Load the firmware */
-     riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
+-    if (riscv_cpu_mxl(env) == MXL_RV32) {
-+
+-        mask |= SSTATUS32_SD;
-+    /* Attach an SD card */
+-    } else {
-+    if (dinfo) {
+-        mask |= SSTATUS64_SD;
-+        CadenceSDHCIState *sdhci = &(s->soc.sdhci);
+-    }
-+        DeviceState *card = qdev_new(TYPE_SD_CARD);
+-
-+
+-    *val = env->mstatus & mask;
-+        qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
++    /* TODO: Use SXL not MXL. */
-+                                &error_fatal);
++    *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
-+        qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
+     return RISCV_EXCP_NONE;
 +    }
  }
- static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/Kconfig
+--- a/target/riscv/translate.c
-+++ b/hw/riscv/Kconfig
++++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
+@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
-     select SIFIVE
+ static void mark_fs_dirty(DisasContext *ctx)
-     select UNIMP
+ {
-     select MCHP_PFSOC_MMUART
+     TCGv tmp;
-+    select CADENCE_SDHCI
+-    target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
      if (ctx->mstatus_fs != MSTATUS_FS) {
          /* Remember the state change for the rest of the TB. */
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
          tmp = tcg_temp_new();
          tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
 -        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 +        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
          tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
          tcg_temp_free(tmp);
      }
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
          tmp = tcg_temp_new();
          tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
 -        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
 +        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
          tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
          tcg_temp_free(tmp);
      }
 --
-.28.0
+.31.1

-[PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller
+[PULL 23/33] hw/riscv: opentitan: Update to the latest build
-From: Bin Meng <bin.meng@windriver.com>
+From: Alistair Francis <alistair.francis@wdc.com>
-On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
+Update the OpenTitan machine model to match the latest OpenTitan FPGA
-controller to move the 2nd stage bootloader in the system memory.
+design.
 Let's connect a DMA controller to Microchip PolarFire SoC.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
 ---
- include/hw/riscv/microchip_pfsoc.h | 11 +++++++++++
+ include/hw/riscv/opentitan.h |  6 +++---
- hw/riscv/microchip_pfsoc.c         | 15 +++++++++++++++
+ hw/riscv/opentitan.c         | 22 +++++++++++++++++-----
- hw/riscv/Kconfig                   |  1 +
+files changed, 20 insertions(+), 8 deletions(-)
 files changed, 27 insertions(+)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
+diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/include/hw/riscv/opentitan.h
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/include/hw/riscv/opentitan.h
 @@ -XXX,XX +XXX,XX @@
- #define HW_MICROCHIP_PFSOC_H
+ #define HW_OPENTITAN_H
- #include "hw/char/mchp_pfsoc_mmuart.h"
+ #include "hw/riscv/riscv_hart.h"
-+#include "hw/dma/sifive_pdma.h"
+-#include "hw/intc/ibex_plic.h"
- #include "hw/sd/cadence_sdhci.h"
++#include "hw/intc/sifive_plic.h"
+ #include "hw/char/ibex_uart.h"
- typedef struct MicrochipPFSoCState {
+ #include "hw/timer/ibex_timer.h"
-@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
+ #include "qom/object.h"
-     MchpPfSoCMMUartState *serial2;
+@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {
-     MchpPfSoCMMUartState *serial3;
-     MchpPfSoCMMUartState *serial4;
+     /*< public >*/
-+    SiFivePDMAState dma;
+     RISCVHartArrayState cpus;
-     CadenceSDHCIState sdhci;
+-    IbexPlicState plic;
- } MicrochipPFSoCState;
++    SiFivePLICState plic;
+     IbexUartState uart;
-@@ -XXX,XX +XXX,XX @@ enum {
+     IbexTimerState timer;
-     MICROCHIP_PFSOC_BUSERR_UNIT4,
      MICROCHIP_PFSOC_CLINT,
      MICROCHIP_PFSOC_L2CC,
 +    MICROCHIP_PFSOC_DMA,
      MICROCHIP_PFSOC_L2LIM,
      MICROCHIP_PFSOC_PLIC,
      MICROCHIP_PFSOC_MMUART0,
 @@ -XXX,XX +XXX,XX @@ enum {
  };
  enum {
-+    MICROCHIP_PFSOC_DMA_IRQ0 = 5,
+-    IBEX_TIMER_TIMEREXPIRED0_0 = 125,
-+    MICROCHIP_PFSOC_DMA_IRQ1 = 6,
++    IBEX_TIMER_TIMEREXPIRED0_0 = 126,
-+    MICROCHIP_PFSOC_DMA_IRQ2 = 7,
+     IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
-+    MICROCHIP_PFSOC_DMA_IRQ3 = 8,
+     IBEX_UART0_RX_TIMEOUT_IRQ = 7,
-+    MICROCHIP_PFSOC_DMA_IRQ4 = 9,
+     IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
-+    MICROCHIP_PFSOC_DMA_IRQ5 = 10,
+diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
 +    MICROCHIP_PFSOC_DMA_IRQ6 = 11,
 +    MICROCHIP_PFSOC_DMA_IRQ7 = 12,
      MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
      MICROCHIP_PFSOC_MMUART0_IRQ = 90,
      MICROCHIP_PFSOC_MMUART1_IRQ = 91,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
+--- a/hw/riscv/opentitan.c
-+++ b/hw/riscv/microchip_pfsoc.c
++++ b/hw/riscv/opentitan.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
-  * 2) eNVM (Embedded Non-Volatile Memory)
+     [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
-  * 3) MMUARTs (Multi-Mode UART)
+     [IBEX_DEV_PADCTRL] =        {  0x40470000,  0x1000  },
-  * 4) Cadence eMMC/SDHC controller and an SD card connected to it
+     [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
-+ * 5) SiFive Platform DMA (Direct Memory Access Controller)
+-    [IBEX_DEV_PLIC] =           {  0x41010000,  0x1000  },
-  *
+     [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
-  * This board currently generates devicetree dynamically that indicates at least
+     [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
-  * two harts and up to five harts.
+     [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
-@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
+-    [IBEX_DEV_KEYMGR] =         {  0x41130000,  0x1000  },
-     [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
++    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
-     [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
++    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
-     [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
+     [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
-+    [MICROCHIP_PFSOC_DMA] =             {  0x3000000,   0x100000 },
+     [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
-     [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
+     [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
-     [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
+     [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
-     [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
+     [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
+     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
-                          TYPE_RISCV_CPU_SIFIVE_U54);
+-    [IBEX_DEV_OTBN] =           {  0x411d0000,  0x10000 },
-     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
+     [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
++    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000  },
-+    object_initialize_child(obj, "dma-controller", &s->dma,
+     [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
-+                            TYPE_SIFIVE_PDMA);
+ };
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_init(Object *obj)
      object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
 -    object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
 +    object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
      object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                                  &s->flash_alias);
      /* PLIC */
 +    qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
 +    qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
 +    qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
 +    qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
 +    qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
 +    qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
 +    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
 +    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
 +    qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004);
 +    qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4);
 +    qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
 +
-     object_initialize_child(obj, "sd-controller", &s->sdhci,
+     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
-                             TYPE_CADENCE_SDHCI);
+         return;
- }
+     }
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
-         memmap[MICROCHIP_PFSOC_PLIC].size);
+     for (i = 0; i < ms->smp.cpus; i++) {
-     g_free(plic_hart_config);
+         CPUState *cpu = qemu_get_cpu(i);
-+    /* DMA */
+-        qdev_connect_gpio_out(DEVICE(&s->plic), i,
-+    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
++        qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
-+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
+                               qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
-+                    memmap[MICROCHIP_PFSOC_DMA].base);
+     }
-+    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
 +                           qdev_get_gpio_in(DEVICE(s->plic),
 +                                            MICROCHIP_PFSOC_DMA_IRQ0 + i));
 +    }
 +
      /* SYSREG */
      create_unimplemented_device("microchip.pfsoc.sysreg",
          memmap[MICROCHIP_PFSOC_SYSREG].base,
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
      select SIFIVE
      select UNIMP
      select MCHP_PFSOC_MMUART
 +    select SIFIVE_PDMA
      select CADENCE_SDHCI
 --
-.28.0
+.31.1

-[PULL 24/30] hw/riscv: Move sifive_plic model to hw/intc
+[PULL 24/33] hw/intc: Remove the Ibex PLIC
-From: Bin Meng <bin.meng@windriver.com>
+From: Alistair Francis <alistair.francis@wdc.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and
-should only contain the RISC-V SoC / machine codes plus generic
+instead use the SiFive PLIC.
-codes. Let's move sifive_plic model to hw/intc directory.
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
 ---
- {include/hw/riscv => hw/intc}/sifive_plic.h | 0
+ hw/intc/ibex_plic.c | 307 --------------------------------------------
- hw/{riscv => intc}/sifive_plic.c            | 2 +-
+ hw/intc/meson.build |   1 -
- hw/riscv/microchip_pfsoc.c                  | 2 +-
+files changed, 308 deletions(-)
- hw/riscv/sifive_e.c                         | 2 +-
+ delete mode 100644 hw/intc/ibex_plic.c
- hw/riscv/sifive_u.c                         | 2 +-
- hw/riscv/virt.c                             | 2 +-
+diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
- hw/intc/Kconfig                             | 3 +++
+deleted file mode 100644
- hw/intc/meson.build                         | 1 +
+index XXXXXXX..XXXXXXX
- hw/riscv/Kconfig                            | 5 +++++
+--- a/hw/intc/ibex_plic.c
- hw/riscv/meson.build                        | 1 -
++++ /dev/null
 files changed, 14 insertions(+), 6 deletions(-)
  rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
  rename hw/{riscv => intc}/sifive_plic.c (99%)
 diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
 similarity index 100%
 rename from include/hw/riscv/sifive_plic.h
 rename to hw/intc/sifive_plic.h
 diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
 similarity index 99%
 rename from hw/riscv/sifive_plic.c
 rename to hw/intc/sifive_plic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_plic.c
 +++ b/hw/intc/sifive_plic.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/pci/msi.h"
+-/*
- #include "hw/boards.h"
+- * QEMU RISC-V lowRISC Ibex PLIC
- #include "hw/qdev-properties.h"
+- *
-+#include "hw/intc/sifive_plic.h"
+- * Copyright (c) 2020 Western Digital
- #include "target/riscv/cpu.h"
+- *
- #include "sysemu/sysemu.h"
+- * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
--#include "hw/riscv/sifive_plic.h"
+- *
+- * This program is free software; you can redistribute it and/or modify it
- #define RISCV_DEBUG_PLIC 0
+- * under the terms and conditions of the GNU General Public License,
+- * version 2 or later, as published by the Free Software Foundation.
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
+- *
-index XXXXXXX..XXXXXXX 100644
+- * This program is distributed in the hope it will be useful, but WITHOUT
---- a/hw/riscv/microchip_pfsoc.c
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-+++ b/hw/riscv/microchip_pfsoc.c
+- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-@@ -XXX,XX +XXX,XX @@
+- * more details.
- #include "hw/misc/unimp.h"
+- *
- #include "hw/riscv/boot.h"
+- * You should have received a copy of the GNU General Public License along with
- #include "hw/riscv/riscv_hart.h"
+- * this program.  If not, see <http://www.gnu.org/licenses/>.
--#include "hw/riscv/sifive_plic.h"
+- */
- #include "hw/riscv/microchip_pfsoc.h"
+-
- #include "hw/intc/sifive_clint.h"
+-#include "qemu/osdep.h"
-+#include "hw/intc/sifive_plic.h"
+-#include "qemu/log.h"
- #include "sysemu/sysemu.h"
+-#include "hw/qdev-properties.h"
+-#include "hw/core/cpu.h"
- /*
+-#include "hw/boards.h"
-diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
+-#include "hw/pci/msi.h"
-index XXXXXXX..XXXXXXX 100644
+-#include "target/riscv/cpu_bits.h"
---- a/hw/riscv/sifive_e.c
+-#include "target/riscv/cpu.h"
-+++ b/hw/riscv/sifive_e.c
+-#include "hw/intc/ibex_plic.h"
-@@ -XXX,XX +XXX,XX @@
+-#include "hw/irq.h"
- #include "hw/misc/unimp.h"
+-
- #include "target/riscv/cpu.h"
+-static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
- #include "hw/riscv/riscv_hart.h"
+-{
--#include "hw/riscv/sifive_plic.h"
+-    uint32_t end = base + (num * 0x04);
- #include "hw/riscv/sifive_uart.h"
+-
- #include "hw/riscv/sifive_e.h"
+-    if (addr >= base && addr < end) {
- #include "hw/riscv/boot.h"
+-        return true;
- #include "hw/intc/sifive_clint.h"
+-    }
-+#include "hw/intc/sifive_plic.h"
+-
- #include "hw/misc/sifive_e_prci.h"
+-    return false;
- #include "chardev/char.h"
+-}
- #include "sysemu/arch_init.h"
+-
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
+-static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
-index XXXXXXX..XXXXXXX 100644
+-{
---- a/hw/riscv/sifive_u.c
+-    int pending_num = irq / 32;
-+++ b/hw/riscv/sifive_u.c
+-
-@@ -XXX,XX +XXX,XX @@
+-    if (!level) {
- #include "hw/misc/unimp.h"
+-        /*
- #include "target/riscv/cpu.h"
+-         * If the level is low make sure we clear the hidden_pending.
- #include "hw/riscv/riscv_hart.h"
+-         */
--#include "hw/riscv/sifive_plic.h"
+-        s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
- #include "hw/riscv/sifive_uart.h"
+-    }
- #include "hw/riscv/sifive_u.h"
+-
- #include "hw/riscv/boot.h"
+-    if (s->claimed[pending_num] & 1 << (irq % 32)) {
- #include "hw/intc/sifive_clint.h"
+-        /*
-+#include "hw/intc/sifive_plic.h"
+-         * The interrupt has been claimed, but not completed.
- #include "chardev/char.h"
+-         * The pending bit can't be set.
- #include "net/eth.h"
+-         * Save the pending level for after the interrupt is completed.
- #include "sysemu/arch_init.h"
+-         */
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+-        s->hidden_pending[pending_num] |= level << (irq % 32);
-index XXXXXXX..XXXXXXX 100644
+-    } else {
---- a/hw/riscv/virt.c
+-        s->pending[pending_num] |= level << (irq % 32);
-+++ b/hw/riscv/virt.c
+-    }
-@@ -XXX,XX +XXX,XX @@
+-}
- #include "hw/char/serial.h"
+-
- #include "target/riscv/cpu.h"
+-static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
- #include "hw/riscv/riscv_hart.h"
+-{
--#include "hw/riscv/sifive_plic.h"
+-    int i;
- #include "hw/riscv/sifive_test.h"
+-    uint32_t max_irq = 0;
- #include "hw/riscv/virt.h"
+-    uint32_t max_prio = s->threshold;
- #include "hw/riscv/boot.h"
+-
- #include "hw/riscv/numa.h"
+-    for (i = 0; i < s->pending_num; i++) {
- #include "hw/intc/sifive_clint.h"
+-        uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
-+#include "hw/intc/sifive_plic.h"
+-
- #include "chardev/char.h"
+-        if (!(s->pending[i] & s->enable[i])) {
- #include "sysemu/arch_init.h"
+-            /* No pending and enabled IRQ */
- #include "sysemu/device_tree.h"
+-            continue;
-diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
+-        }
-index XXXXXXX..XXXXXXX 100644
+-
---- a/hw/intc/Kconfig
+-        if (s->priority[irq_num] > max_prio) {
-+++ b/hw/intc/Kconfig
+-            max_irq = irq_num;
-@@ -XXX,XX +XXX,XX @@ config LOONGSON_LIOINTC
+-            max_prio = s->priority[irq_num];
+-        }
- config SIFIVE_CLINT
+-    }
-     bool
+-
-+
+-    if (max_irq) {
-+config SIFIVE_PLIC
+-        s->claim = max_irq;
-+    bool
+-        return true;
 -    }
 -
 -    return false;
 -}
 -
 -static void ibex_plic_update(IbexPlicState *s)
 -{
 -    int i;
 -
 -    for (i = 0; i < s->num_cpus; i++) {
 -        qemu_set_irq(s->external_irqs[i], ibex_plic_irqs_pending(s, 0));
 -    }
 -}
 -
 -static void ibex_plic_reset(DeviceState *dev)
 -{
 -    IbexPlicState *s = IBEX_PLIC(dev);
 -
 -    s->threshold = 0x00000000;
 -    s->claim = 0x00000000;
 -}
 -
 -static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
 -                               unsigned int size)
 -{
 -    IbexPlicState *s = opaque;
 -    int offset;
 -    uint32_t ret = 0;
 -
 -    if (addr_between(addr, s->pending_base, s->pending_num)) {
 -        offset = (addr - s->pending_base) / 4;
 -        ret = s->pending[offset];
 -    } else if (addr_between(addr, s->source_base, s->source_num)) {
 -        qemu_log_mask(LOG_UNIMP,
 -                      "%s: Interrupt source mode not supported\n", __func__);
 -    } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 -        offset = (addr - s->priority_base) / 4;
 -        ret = s->priority[offset];
 -    } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 -        offset = (addr - s->enable_base) / 4;
 -        ret = s->enable[offset];
 -    } else if (addr_between(addr, s->threshold_base, 1)) {
 -        ret = s->threshold;
 -    } else if (addr_between(addr, s->claim_base, 1)) {
 -        int pending_num = s->claim / 32;
 -        s->pending[pending_num] &= ~(1 << (s->claim % 32));
 -
 -        /* Set the interrupt as claimed, but not completed */
 -        s->claimed[pending_num] |= 1 << (s->claim % 32);
 -
 -        /* Return the current claimed interrupt */
 -        ret = s->claim;
 -
 -        /* Clear the claimed interrupt */
 -        s->claim = 0x00000000;
 -
 -        /* Update the interrupt status after the claim */
 -        ibex_plic_update(s);
 -    }
 -
 -    return ret;
 -}
 -
 -static void ibex_plic_write(void *opaque, hwaddr addr,
 -                            uint64_t value, unsigned int size)
 -{
 -    IbexPlicState *s = opaque;
 -
 -    if (addr_between(addr, s->pending_base, s->pending_num)) {
 -        qemu_log_mask(LOG_GUEST_ERROR,
 -                      "%s: Pending registers are read only\n", __func__);
 -    } else if (addr_between(addr, s->source_base, s->source_num)) {
 -        qemu_log_mask(LOG_UNIMP,
 -                      "%s: Interrupt source mode not supported\n", __func__);
 -    } else if (addr_between(addr, s->priority_base, s->priority_num)) {
 -        uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
 -        s->priority[irq] = value & 7;
 -        ibex_plic_update(s);
 -    } else if (addr_between(addr, s->enable_base, s->enable_num)) {
 -        uint32_t enable_reg = (addr - s->enable_base) / 4;
 -
 -        s->enable[enable_reg] = value;
 -    } else if (addr_between(addr, s->threshold_base, 1)) {
 -        s->threshold = value & 3;
 -    } else if (addr_between(addr, s->claim_base, 1)) {
 -        if (s->claim == value) {
 -            /* Interrupt was completed */
 -            s->claim = 0;
 -        }
 -        if (s->claimed[value / 32] & 1 << (value % 32)) {
 -            int pending_num = value / 32;
 -
 -            /* This value was already claimed, clear it. */
 -            s->claimed[pending_num] &= ~(1 << (value % 32));
 -
 -            if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
 -                /*
 -                 * If the bit in hidden_pending is set then that means we
 -                 * received an interrupt between claiming and completing
 -                 * the interrupt that hasn't since been de-asserted.
 -                 * On hardware this would trigger an interrupt, so let's
 -                 * trigger one here as well.
 -                 */
 -                s->pending[pending_num] |= 1 << (value % 32);
 -            }
 -        }
 -    }
 -
 -    ibex_plic_update(s);
 -}
 -
 -static const MemoryRegionOps ibex_plic_ops = {
 -    .read = ibex_plic_read,
 -    .write = ibex_plic_write,
 -    .endianness = DEVICE_NATIVE_ENDIAN,
 -    .valid = {
 -        .min_access_size = 4,
 -        .max_access_size = 4
 -    }
 -};
 -
 -static void ibex_plic_irq_request(void *opaque, int irq, int level)
 -{
 -    IbexPlicState *s = opaque;
 -
 -    ibex_plic_irqs_set_pending(s, irq, level > 0);
 -    ibex_plic_update(s);
 -}
 -
 -static Property ibex_plic_properties[] = {
 -    DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
 -    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
 -
 -    DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
 -    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
 -
 -    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
 -    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
 -
 -    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
 -    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
 -
 -    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
 -    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
 -
 -    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
 -
 -    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
 -    DEFINE_PROP_END_OF_LIST(),
 -};
 -
 -static void ibex_plic_init(Object *obj)
 -{
 -    IbexPlicState *s = IBEX_PLIC(obj);
 -
 -    memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
 -                          TYPE_IBEX_PLIC, 0x400);
 -    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 -}
 -
 -static void ibex_plic_realize(DeviceState *dev, Error **errp)
 -{
 -    IbexPlicState *s = IBEX_PLIC(dev);
 -    int i;
 -
 -    s->pending = g_new0(uint32_t, s->pending_num);
 -    s->hidden_pending = g_new0(uint32_t, s->pending_num);
 -    s->claimed = g_new0(uint32_t, s->pending_num);
 -    s->source = g_new0(uint32_t, s->source_num);
 -    s->priority = g_new0(uint32_t, s->priority_num);
 -    s->enable = g_new0(uint32_t, s->enable_num);
 -
 -    qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
 -
 -    s->external_irqs = g_malloc(sizeof(qemu_irq) * s->num_cpus);
 -    qdev_init_gpio_out(dev, s->external_irqs, s->num_cpus);
 -
 -    /*
 -     * We can't allow the supervisor to control SEIP as this would allow the
 -     * supervisor to clear a pending external interrupt which will result in
 -     * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
 -     * hardware controlled when a PLIC is attached.
 -     */
 -    MachineState *ms = MACHINE(qdev_get_machine());
 -    unsigned int smp_cpus = ms->smp.cpus;
 -    for (i = 0; i < smp_cpus; i++) {
 -        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 -        if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
 -            error_report("SEIP already claimed");
 -            exit(1);
 -        }
 -    }
 -
 -    msi_nonbroken = true;
 -}
 -
 -static void ibex_plic_class_init(ObjectClass *klass, void *data)
 -{
 -    DeviceClass *dc = DEVICE_CLASS(klass);
 -
 -    dc->reset = ibex_plic_reset;
 -    device_class_set_props(dc, ibex_plic_properties);
 -    dc->realize = ibex_plic_realize;
 -}
 -
 -static const TypeInfo ibex_plic_info = {
 -    .name          = TYPE_IBEX_PLIC,
 -    .parent        = TYPE_SYS_BUS_DEVICE,
 -    .instance_size = sizeof(IbexPlicState),
 -    .instance_init = ibex_plic_init,
 -    .class_init    = ibex_plic_class_init,
 -};
 -
 -static void ibex_plic_register_types(void)
 -{
 -    type_register_static(&ibex_plic_info);
 -}
 -
 -type_init(ibex_plic_register_types)
 diff --git a/hw/intc/meson.build b/hw/intc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/meson.build
 +++ b/hw/intc/meson.build
-@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
+@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
- specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
+ specific_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))
- specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
+ specific_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_gic.c', 'exynos4210_combiner.c'))
- specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
+ specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
-+specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
+-specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c'))
- specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
+ specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
- specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
+ specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c'))
- specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
+ specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c'))
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
      select SIFIVE
      select SIFIVE_CLINT
      select SIFIVE_GPIO
 +    select SIFIVE_PLIC
      select SIFIVE_E_PRCI
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select SIFIVE_CLINT
      select SIFIVE_GPIO
      select SIFIVE_PDMA
 +    select SIFIVE_PLIC
      select SIFIVE_U_OTP
      select SIFIVE_U_PRCI
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config SPIKE
      select HTIF
      select SIFIVE
      select SIFIVE_CLINT
 +    select SIFIVE_PLIC
  config OPENTITAN
      bool
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      select PFLASH_CFI01
      select SIFIVE
      select SIFIVE_CLINT
 +    select SIFIVE_PLIC
  config MICROCHIP_PFSOC
      bool
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
      select UNIMP
      select MCHP_PFSOC_MMUART
      select SIFIVE_PDMA
 +    select SIFIVE_PLIC
      select CADENCE_SDHCI
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 --
-.28.0
+.31.1

-[PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
+[PULL 25/33] hw/intc: sifive_plic: Move the properties
-From: Bin Meng <bin.meng@windriver.com>
+From: Alistair Francis <alistair.francis@wdc.com>
-Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-wires 4 of them out. Let's connect all 5 MMUARTs.
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
 Message-id: 3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alistair.francis@wdc.com
 ---
  hw/intc/sifive_plic.c | 30 +++++++++++++++---------------
 file changed, 15 insertions(+), 15 deletions(-)
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++
  hw/riscv/microchip_pfsoc.c         | 30 ++++++++++++++++++++++++++++++
  hw/riscv/Kconfig                   |  1 +
 files changed, 51 insertions(+)
 diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
+--- a/hw/intc/sifive_plic.c
-+++ b/include/hw/riscv/microchip_pfsoc.h
++++ b/hw/intc/sifive_plic.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_plic_ops = {
- #ifndef HW_MICROCHIP_PFSOC_H
+     }
  #define HW_MICROCHIP_PFSOC_H
 +#include "hw/char/mchp_pfsoc_mmuart.h"
 +
  typedef struct MicrochipPFSoCState {
      /*< private >*/
      DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
      RISCVHartArrayState e_cpus;
      RISCVHartArrayState u_cpus;
      DeviceState *plic;
 +    MchpPfSoCMMUartState *serial0;
 +    MchpPfSoCMMUartState *serial1;
 +    MchpPfSoCMMUartState *serial2;
 +    MchpPfSoCMMUartState *serial3;
 +    MchpPfSoCMMUartState *serial4;
  } MicrochipPFSoCState;
  #define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
@@ -XXX,XX +XXX,XX @@ enum {
      MICROCHIP_PFSOC_L2CC,
      MICROCHIP_PFSOC_L2LIM,
      MICROCHIP_PFSOC_PLIC,
 +    MICROCHIP_PFSOC_MMUART0,
      MICROCHIP_PFSOC_SYSREG,
      MICROCHIP_PFSOC_MPUCFG,
 +    MICROCHIP_PFSOC_MMUART1,
 +    MICROCHIP_PFSOC_MMUART2,
 +    MICROCHIP_PFSOC_MMUART3,
 +    MICROCHIP_PFSOC_MMUART4,
      MICROCHIP_PFSOC_ENVM_CFG,
      MICROCHIP_PFSOC_ENVM_DATA,
      MICROCHIP_PFSOC_IOSCB_CFG,
      MICROCHIP_PFSOC_DRAM,
  };
-+enum {
+-static Property sifive_plic_properties[] = {
-+    MICROCHIP_PFSOC_MMUART0_IRQ = 90,
+-    DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
-+    MICROCHIP_PFSOC_MMUART1_IRQ = 91,
+-    DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
-+    MICROCHIP_PFSOC_MMUART2_IRQ = 92,
+-    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
-+    MICROCHIP_PFSOC_MMUART3_IRQ = 93,
+-    DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
-+    MICROCHIP_PFSOC_MMUART4_IRQ = 94,
+-    DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
 -    DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
 -    DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
 -    DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
 -    DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
 -    DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
 -    DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
 -    DEFINE_PROP_END_OF_LIST(),
 -};
 -
  /*
   * parse PLIC hart/mode address offset config
   *
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_sifive_plic = {
          }
  };
 +static Property sifive_plic_properties[] = {
 +    DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
 +    DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
 +    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
 +    DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
 +    DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
 +    DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
 +    DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
 +    DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
 +    DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
 +    DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
 +    DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
- #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
+ static void sifive_plic_class_init(ObjectClass *klass, void *data)
- #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
+ {
+     DeviceClass *dc = DEVICE_CLASS(klass);
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
   * 0) CLINT (Core Level Interruptor)
   * 1) PLIC (Platform Level Interrupt Controller)
   * 2) eNVM (Embedded Non-Volatile Memory)
 + * 3) MMUARTs (Multi-Mode UART)
   *
   * This board currently generates devicetree dynamically that indicates at least
   * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@
  #include "hw/irq.h"
  #include "hw/loader.h"
  #include "hw/sysbus.h"
 +#include "chardev/char.h"
  #include "hw/cpu/cluster.h"
  #include "target/riscv/cpu.h"
  #include "hw/misc/unimp.h"
@@ -XXX,XX +XXX,XX @@
  #include "hw/riscv/sifive_clint.h"
  #include "hw/riscv/sifive_plic.h"
  #include "hw/riscv/microchip_pfsoc.h"
 +#include "sysemu/sysemu.h"
  /*
   * The BIOS image used by this machine is called Hart Software Services (HSS).
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
      [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
      [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
      [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
 +    [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
      [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
      [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
 +    [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
 +    [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
 +    [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
 +    [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
      [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
      [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
      [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
          memmap[MICROCHIP_PFSOC_MPUCFG].base,
          memmap[MICROCHIP_PFSOC_MPUCFG].size);
 +    /* MMUARTs */
 +    s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
 +        memmap[MICROCHIP_PFSOC_MMUART0].base,
 +        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
 +        serial_hd(0));
 +    s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
 +        memmap[MICROCHIP_PFSOC_MMUART1].base,
 +        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
 +        serial_hd(1));
 +    s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
 +        memmap[MICROCHIP_PFSOC_MMUART2].base,
 +        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
 +        serial_hd(2));
 +    s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
 +        memmap[MICROCHIP_PFSOC_MMUART3].base,
 +        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
 +        serial_hd(3));
 +    s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
 +        memmap[MICROCHIP_PFSOC_MMUART4].base,
 +        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
 +        serial_hd(4));
 +
      /* eNVM */
      memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
                             memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
      select HART
      select SIFIVE
      select UNIMP
 +    select MCHP_PFSOC_MMUART
 --
-.28.0
+.31.1

-New patch
+[PULL 26/33] hw/intc: sifive_plic: Cleanup the realize function
+From: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Message-id: b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
+---
+ hw/intc/sifive_plic.c | 45 +++++++++++++++++++++++--------------------
+file changed, 24 insertions(+), 21 deletions(-)
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/sifive_plic.c
++++ b/hw/intc/sifive_plic.c
+@@ -XXX,XX +XXX,XX @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
+ static void sifive_plic_realize(DeviceState *dev, Error **errp)
+ {
+-    SiFivePLICState *plic = SIFIVE_PLIC(dev);
++    SiFivePLICState *s = SIFIVE_PLIC(dev);
+     int i;
+-    memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
+-                          TYPE_SIFIVE_PLIC, plic->aperture_size);
+-    parse_hart_config(plic);
+-    plic->bitfield_words = (plic->num_sources + 31) >> 5;
+-    plic->num_enables = plic->bitfield_words * plic->num_addrs;
+-    plic->source_priority = g_new0(uint32_t, plic->num_sources);
+-    plic->target_priority = g_new(uint32_t, plic->num_addrs);
+-    plic->pending = g_new0(uint32_t, plic->bitfield_words);
+-    plic->claimed = g_new0(uint32_t, plic->bitfield_words);
+-    plic->enable = g_new0(uint32_t, plic->num_enables);
+-    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
+-    qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
+-
+-    plic->s_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
+-    qdev_init_gpio_out(dev, plic->s_external_irqs, plic->num_harts);
+-
+-    plic->m_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
+-    qdev_init_gpio_out(dev, plic->m_external_irqs, plic->num_harts);
++    memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s,
++                          TYPE_SIFIVE_PLIC, s->aperture_size);
++    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
++
++    parse_hart_config(s);
++
++    s->bitfield_words = (s->num_sources + 31) >> 5;
++    s->num_enables = s->bitfield_words * s->num_addrs;
++    s->source_priority = g_new0(uint32_t, s->num_sources);
++    s->target_priority = g_new(uint32_t, s->num_addrs);
++    s->pending = g_new0(uint32_t, s->bitfield_words);
++    s->claimed = g_new0(uint32_t, s->bitfield_words);
++    s->enable = g_new0(uint32_t, s->num_enables);
++
++    qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources);
++
++    s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
++    qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts);
++
++    s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
++    qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
+     /* We can't allow the supervisor to control SEIP as this would allow the
+      * supervisor to clear a pending external interrupt which will result in
+      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
+      * hardware controlled when a PLIC is attached.
+      */
+-    for (i = 0; i < plic->num_harts; i++) {
+-        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
++    for (i = 0; i < s->num_harts; i++) {
++        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
+         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
+             error_report("SEIP already claimed");
+             exit(1);
+--
+.31.1

-[PULL 04/30] hw/riscv: hart: Add a new 'resetvec' property
+[PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function
-From: Bin Meng <bin.meng@windriver.com>
+From: Alistair Francis <alistair.francis@wdc.com>
-RISC-V machines do not instantiate RISC-V CPUs directly, instead
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-they do that via the hart array. Add a new property for the reset
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-vector address to allow the value to be passed to the CPU, before
+Message-id: 4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.francis@wdc.com
-CPU is realized.
+---
  hw/intc/sifive_plic.c | 10 ++++------
 file changed, 4 insertions(+), 6 deletions(-)
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
  include/hw/riscv/riscv_hart.h | 1 +
  hw/riscv/riscv_hart.c         | 3 +++
 files changed, 4 insertions(+)
 diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/riscv_hart.h
+--- a/hw/intc/sifive_plic.c
-+++ b/include/hw/riscv/riscv_hart.h
++++ b/hw/intc/sifive_plic.c
-@@ -XXX,XX +XXX,XX @@ typedef struct RISCVHartArrayState {
+@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
-     uint32_t num_harts;
-     uint32_t hartid_base;
+ static void sifive_plic_irq_request(void *opaque, int irq, int level)
      char *cpu_type;
 +    uint64_t resetvec;
      RISCVCPU *harts;
  } RISCVHartArrayState;
 diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/riscv_hart.c
 +++ b/hw/riscv/riscv_hart.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_harts_props[] = {
      DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
      DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
      DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
 +    DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
 +                       DEFAULT_RSTVEC),
      DEFINE_PROP_END_OF_LIST(),
  };
@@ -XXX,XX +XXX,XX @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
                                 char *cpu_type, Error **errp)
  {
-     object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
+-    SiFivePLICState *plic = opaque;
-+    qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
+-    if (RISCV_DEBUG_PLIC) {
-     s->harts[idx].env.mhartid = s->hartid_base + idx;
+-        qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
-     qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
+-    }
-     return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
+-    sifive_plic_set_pending(plic, irq, level > 0);
 -    sifive_plic_update(plic);
 +    SiFivePLICState *s = opaque;
 +
 +    sifive_plic_set_pending(s, irq, level > 0);
 +    sifive_plic_update(s);
  }
  static void sifive_plic_realize(DeviceState *dev, Error **errp)
 --
-.28.0
+.31.1

-[PULL 16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers
+[PULL 28/33] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
-From: Bin Meng <bin.meng@windriver.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
+Using memory_region_init_ram(), which can't possibly handle vhost-user,
-enough to create unimplemented devices to cover their register
+and can't work as expected with '-numa node,memdev' options.
 spaces at this point.
-With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
+Use MachineState::ram instead of manually initializing RAM memory
-all the way to the Linux shell login prompt, with a modified HSS
+region, as well as by providing MachineClass::default_ram_id to
-(1st stage bootloader).
+opt in to memdev scheme.
-For detailed instructions on how to create images for the Icicle
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Kit board, please check QEMU RISC-V WiKi page at:
 https://wiki.qemu.org/Documentation/Platforms/RISCV
 Signed-off-by: Bin Meng <bin.meng@windriver.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Igor Mammedov <imammedo@redhat.com>
-Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com>
+Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/microchip_pfsoc.h |  3 +++
+ hw/riscv/microchip_pfsoc.c | 36 ++++++++++++++++++++----------------
- hw/riscv/microchip_pfsoc.c         | 14 ++++++++++++++
+file changed, 20 insertions(+), 16 deletions(-)
 files changed, 17 insertions(+)
-diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/microchip_pfsoc.h
-+++ b/include/hw/riscv/microchip_pfsoc.h
-@@ -XXX,XX +XXX,XX @@ enum {
-     MICROCHIP_PFSOC_MMUART4,
-     MICROCHIP_PFSOC_GEM0,
-     MICROCHIP_PFSOC_GEM1,
-+    MICROCHIP_PFSOC_GPIO0,
-+    MICROCHIP_PFSOC_GPIO1,
-+    MICROCHIP_PFSOC_GPIO2,
-     MICROCHIP_PFSOC_ENVM_CFG,
-     MICROCHIP_PFSOC_ENVM_DATA,
-     MICROCHIP_PFSOC_IOSCB_CFG,
 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/microchip_pfsoc.c
 +++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
+@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
-     [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
+     MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
-     [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
+     MemoryRegion *mem_high = g_new(MemoryRegion, 1);
-     [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
+     MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
-+    [MICROCHIP_PFSOC_GPIO0] =           { 0x20120000,     0x1000 },
+-    uint64_t mem_high_size;
-+    [MICROCHIP_PFSOC_GPIO1] =           { 0x20121000,     0x1000 },
++    uint64_t mem_low_size, mem_high_size;
-+    [MICROCHIP_PFSOC_GPIO2] =           { 0x20122000,     0x1000 },
+     hwaddr firmware_load_addr;
-     [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
+     const char *firmware_name;
-     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
+     bool kernel_as_payload = false;
-     [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
+@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
-@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+                             TYPE_MICROCHIP_PFSOC);
-     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
+     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
-         qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
++    /* Split RAM into low and high regions using aliases to machine->ram */
-+    /* GPIOs */
++    mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
-+    create_unimplemented_device("microchip.pfsoc.gpio0",
++    mem_high_size = machine->ram_size - mem_low_size;
-+        memmap[MICROCHIP_PFSOC_GPIO0].base,
++    memory_region_init_alias(mem_low, NULL,
-+        memmap[MICROCHIP_PFSOC_GPIO0].size);
++                             "microchip.icicle.kit.ram_low", machine->ram,
-+    create_unimplemented_device("microchip.pfsoc.gpio1",
++                             0, mem_low_size);
-+        memmap[MICROCHIP_PFSOC_GPIO1].base,
++    memory_region_init_alias(mem_high, NULL,
-+        memmap[MICROCHIP_PFSOC_GPIO1].size);
++                             "microchip.icicle.kit.ram_high", machine->ram,
-+    create_unimplemented_device("microchip.pfsoc.gpio2",
++                             mem_low_size, mem_high_size);
 +        memmap[MICROCHIP_PFSOC_GPIO2].base,
 +        memmap[MICROCHIP_PFSOC_GPIO2].size);
 +
-     /* eNVM */
+     /* Register RAM */
-     memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
+-    memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
-                            memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
+-                           memmap[MICROCHIP_PFSOC_DRAM_LO].size,
 -                           &error_fatal);
 -    memory_region_init_alias(mem_low_alias, NULL,
 -                             "microchip.icicle.kit.ram_low.alias",
 -                             mem_low, 0,
 -                             memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
      memory_region_add_subregion(system_memory,
                                  memmap[MICROCHIP_PFSOC_DRAM_LO].base,
                                  mem_low);
 +    memory_region_add_subregion(system_memory,
 +                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
 +                                mem_high);
 +
 +    /* Create aliases for the low and high RAM regions */
 +    memory_region_init_alias(mem_low_alias, NULL,
 +                             "microchip.icicle.kit.ram_low.alias",
 +                             mem_low, 0, mem_low_size);
      memory_region_add_subregion(system_memory,
                                  memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
                                  mem_low_alias);
 -
 -    mem_high_size = machine->ram_size - 1 * GiB;
 -
 -    memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
 -                           mem_high_size, &error_fatal);
      memory_region_init_alias(mem_high_alias, NULL,
                               "microchip.icicle.kit.ram_high.alias",
                               mem_high, 0, mem_high_size);
 -    memory_region_add_subregion(system_memory,
 -                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
 -                                mem_high);
      memory_region_add_subregion(system_memory,
                                  memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
                                  mem_high_alias);
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
                     MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
      mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
      mc->default_cpus = mc->min_cpus;
 +    mc->default_ram_id = "microchip.icicle.kit.ram";
      /*
       * Map 513 MiB high memory, the mimimum required high memory size, because
 --
-.28.0
+.31.1

-[PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value
+[PULL 29/33] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
-From: Bin Meng <bin.meng@windriver.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-Now that we have the newly introduced 'resetvec' property in the
+Using memory_region_init_ram(), which can't possibly handle vhost-user,
-RISC-V CPU and HART, instead of hard-coding the reset vector addr
+and can't work as expected with '-numa node,memdev' options.
 in the CPU's instance_init(), move that to riscv_cpu_realize()
 based on the configured property value from the RISC-V machines.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Use MachineState::ram instead of manually initializing RAM memory
 region, as well as by providing MachineClass::default_ram_id to
 opt in to memdev scheme.
 While at it add check for user supplied RAM size and error out if it
 mismatches board expected value.
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Igor Mammedov <imammedo@redhat.com>
-Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
+Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/opentitan.c | 1 +
+ hw/riscv/opentitan.c | 16 ++++++++++++----
- hw/riscv/sifive_e.c  | 1 +
+file changed, 12 insertions(+), 4 deletions(-)
  hw/riscv/sifive_u.c  | 2 ++
  target/riscv/cpu.c   | 7 ++-----
 files changed, 6 insertions(+), 5 deletions(-)
 diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/opentitan.c
 +++ b/hw/riscv/opentitan.c
-@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+@@ -XXX,XX +XXX,XX @@
-                             &error_abort);
+  */
-     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
-                             &error_abort);
+ #include "qemu/osdep.h"
-+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
++#include "qemu/cutils.h"
-     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+ #include "hw/riscv/opentitan.h"
+ #include "qapi/error.h"
-     /* Boot ROM */
+ #include "hw/boards.h"
-diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
+@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_e.c
+ static void opentitan_board_init(MachineState *machine)
-+++ b/hw/riscv/sifive_e.c
+ {
-@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_init(Object *obj)
++    MachineClass *mc = MACHINE_GET_CLASS(machine);
-     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
+     const MemMapEntry *memmap = ibex_memmap;
-     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
+     OpenTitanState *s = g_new0(OpenTitanState, 1);
-                             &error_abort);
+     MemoryRegion *sys_mem = get_system_memory();
-+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
+-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
-     object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
++
-                             TYPE_SIFIVE_GPIO);
++    if (machine->ram_size != mc->default_ram_size) {
 +        char *sz = size_to_str(mc->default_ram_size);
 +        error_report("Invalid RAM size, should be %s", sz);
 +        g_free(sz);
 +        exit(EXIT_FAILURE);
 +    }
      /* Initialize SoC */
      object_initialize_child(OBJECT(machine), "soc", &s->soc,
                              TYPE_RISCV_IBEX_SOC);
      qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 -    memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
 -        memmap[IBEX_DEV_RAM].size, &error_fatal);
      memory_region_add_subregion(sys_mem,
 -        memmap[IBEX_DEV_RAM].base, main_mem);
 +        memmap[IBEX_DEV_RAM].base, machine->ram);
      if (machine->firmware) {
          riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
@@ -XXX,XX +XXX,XX @@ static void opentitan_machine_init(MachineClass *mc)
      mc->init = opentitan_board_init;
      mc->max_cpus = 1;
      mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
 +    mc->default_ram_id = "riscv.lowrisc.ibex.ram";
 +    mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
  }
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
+ DEFINE_MACHINE("opentitan", opentitan_machine_init)
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
      qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
      qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
      qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
 +    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
      object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
      qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
      qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
      qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
      qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
 +    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
      object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
      object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_11_0);
 -    set_resetvec(env, DEFAULT_RSTVEC);
  }
  static void riscv_base_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void riscv_base_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      /* We set this in the realise function */
      set_misa(env, 0);
 -    set_resetvec(env, DEFAULT_RSTVEC);
  }
  static void rvxx_sifive_u_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_u_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
 -    set_resetvec(env, 0x1004);
  }
  static void rvxx_sifive_e_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_e_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
 -    set_resetvec(env, 0x1004);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
  }
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
      CPURISCVState *env = &RISCV_CPU(obj)->env;
      set_misa(env, RV32 | RVI | RVM | RVC | RVU);
      set_priv_version(env, PRIV_VERSION_1_10_0);
 -    set_resetvec(env, 0x8090);
      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
  }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
          set_feature(env, RISCV_FEATURE_PMP);
      }
 +    set_resetvec(env, cpu->cfg.resetvec);
 +
      /* If misa isn't set (rv32 and rv64 machines) set it here */
      if (!env->misa) {
          /* Do some ISA extension error checking */
 --
-.28.0
+.31.1

-[PULL 02/30] riscv: sifive_test: Allow 16-bit writes to memory region
+[PULL 30/33] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
-From: Nathan Chancellor <natechancellor@gmail.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-When shutting down the machine running a mainline Linux kernel, the
+Using memory_region_init_ram(), which can't possibly handle vhost-user,
-following error happens:
+and can't work as expected with '-numa node,memdev' options.
-$ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \
+Use MachineState::ram instead of manually initializing RAM memory
-    -display none -initrd rootfs.cpio -kernel Image -m 512m \
+region, as well as by providing MachineClass::default_ram_id to
-    -nodefaults -serial mon:stdio
+opt in to memdev scheme.
 ...
 Requesting system poweroff
 [    4.999630] reboot: Power down
 sbi_trap_error: hart0: trap handler failed (error -2)
 sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000
 sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822
 sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78
 sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0
 sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040
 sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024
 sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024
 sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555
 sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158
 sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000
 sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000
 sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000
 sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000
 sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008
 sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000
 sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000
 sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000
 sbi_trap_error: hart0: t6=0x0000000000000000
-The kernel does a 16-bit write when powering off the machine, which
+Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
-was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-mismatching sizes in memory_region_access_valid""). Make min_access_size
+Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 match reality so that the machine can shut down properly now.
 Cc: qemu-stable@nongnu.org
 Fixes: 88a07990fa ("SiFive RISC-V Test Finisher")
 Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"")
 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
 Acked-by: Michael S. Tsirkin <mst@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com>
+Message-id: 20211020014112.7336-4-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- hw/riscv/sifive_test.c | 2 +-
+ hw/riscv/shakti_c.c | 6 ++----
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 2 insertions(+), 4 deletions(-)
-diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
+diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_test.c
+--- a/hw/riscv/shakti_c.c
-+++ b/hw/riscv/sifive_test.c
++++ b/hw/riscv/shakti_c.c
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_test_ops = {
+@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_state_init(MachineState *mstate)
-     .write = sifive_test_write,
+ {
-     .endianness = DEVICE_NATIVE_ENDIAN,
+     ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
-     .valid = {
+     MemoryRegion *system_memory = get_system_memory();
--        .min_access_size = 4,
+-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
-+        .min_access_size = 2,
-         .max_access_size = 4
+     /* Allow only Shakti C CPU for this platform */
-     }
+     if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
- };
+@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_state_init(MachineState *mstate)
      qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
      /* register RAM */
 -    memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
 -                           mstate->ram_size, &error_fatal);
      memory_region_add_subregion(system_memory,
                                  shakti_c_memmap[SHAKTI_C_RAM].base,
 -                                main_mem);
 +                                mstate->ram);
      /* ROM reset vector */
      riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
      mc->desc = "RISC-V Board compatible with Shakti SDK";
      mc->init = shakti_c_machine_state_init;
      mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
 +    mc->default_ram_id = "riscv.shakti.c.ram";
  }
  static const TypeInfo shakti_c_machine_type_info = {
 --
-.28.0
+.31.1

-[PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc
+[PULL 31/33] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
-From: Bin Meng <bin.meng@windriver.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Using memory_region_init_ram(), which can't possibly handle vhost-user,
-should only contain the RISC-V SoC / machine codes plus generic
+and can't work as expected with '-numa node,memdev' options.
 codes. Let's move sifive_e_prci model to hw/misc directory.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Use MachineState::ram instead of manually initializing RAM memory
 region, as well as by providing MachineClass::default_ram_id to
 opt in to memdev scheme.
 While at it add check for user supplied RAM size and error out if it
 mismatches board expected value.
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com>
+Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => misc}/sifive_e_prci.h | 0
+ hw/riscv/sifive_e.c | 16 ++++++++++++----
- hw/{riscv => misc}/sifive_e_prci.c         | 2 +-
+file changed, 12 insertions(+), 4 deletions(-)
  hw/riscv/sifive_e.c                        | 2 +-
  hw/misc/Kconfig                            | 3 +++
  hw/misc/meson.build                        | 3 +++
  hw/riscv/Kconfig                           | 1 +
  hw/riscv/meson.build                       | 1 -
 files changed, 9 insertions(+), 3 deletions(-)
  rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
  rename hw/{riscv => misc}/sifive_e_prci.c (99%)
-diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
-similarity index 100%
-rename from include/hw/riscv/sifive_e_prci.h
-rename to include/hw/misc/sifive_e_prci.h
-diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
-similarity index 99%
-rename from hw/riscv/sifive_e_prci.c
-rename to hw/misc/sifive_e_prci.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_e_prci.c
-+++ b/hw/misc/sifive_e_prci.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/log.h"
- #include "qemu/module.h"
- #include "hw/hw.h"
--#include "hw/riscv/sifive_e_prci.h"
-+#include "hw/misc/sifive_e_prci.h"
- static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
- {
 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_e.c
 +++ b/hw/riscv/sifive_e.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/riscv/sifive_clint.h"
+  */
- #include "hw/riscv/sifive_uart.h"
- #include "hw/riscv/sifive_e.h"
+ #include "qemu/osdep.h"
--#include "hw/riscv/sifive_e_prci.h"
++#include "qemu/cutils.h"
- #include "hw/riscv/boot.h"
+ #include "qemu/error-report.h"
-+#include "hw/misc/sifive_e_prci.h"
+ #include "qapi/error.h"
- #include "chardev/char.h"
+ #include "hw/boards.h"
- #include "sysemu/arch_init.h"
+@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sifive_e_memmap[] = {
- #include "sysemu/sysemu.h"
-diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
+ static void sifive_e_machine_init(MachineState *machine)
-index XXXXXXX..XXXXXXX 100644
+ {
---- a/hw/misc/Kconfig
++    MachineClass *mc = MACHINE_GET_CLASS(machine);
-+++ b/hw/misc/Kconfig
+     const MemMapEntry *memmap = sifive_e_memmap;
-@@ -XXX,XX +XXX,XX @@ config MAC_VIA
- config AVR_POWER
+     SiFiveEState *s = RISCV_E_MACHINE(machine);
-     bool
+     MemoryRegion *sys_mem = get_system_memory();
+-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
-+config SIFIVE_E_PRCI
+     int i;
-+    bool
 +    if (machine->ram_size != mc->default_ram_size) {
 +        char *sz = size_to_str(mc->default_ram_size);
 +        error_report("Invalid RAM size, should be %s", sz);
 +        g_free(sz);
 +        exit(EXIT_FAILURE);
 +    }
 +
- source macio/Kconfig
+     /* Initialize SoC */
-diff --git a/hw/misc/meson.build b/hw/misc/meson.build
+     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
-index XXXXXXX..XXXXXXX 100644
+     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
---- a/hw/misc/meson.build
-+++ b/hw/misc/meson.build
+     /* Data Tightly Integrated Memory */
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
+-    memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
- # Mac devices
+-        memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
- softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
+     memory_region_add_subregion(sys_mem,
+-        memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
-+# RISC-V devices
++        memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
-+softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
-+
+     /* Mask ROM reset vector */
- # PKUnity SoC devices
+     uint32_t reset_vec[4];
- softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
+@@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
+     mc->init = sifive_e_machine_init;
-diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
+     mc->max_cpus = 1;
-index XXXXXXX..XXXXXXX 100644
+     mc->default_cpu_type = SIFIVE_E_CPU;
---- a/hw/riscv/Kconfig
++    mc->default_ram_id = "riscv.sifive.e.ram";
-+++ b/hw/riscv/Kconfig
++    mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
-@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
-     bool
+     object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
-     select HART
+                                    sifive_e_machine_set_revb);
      select SIFIVE
 +    select SIFIVE_E_PRCI
      select UNIMP
  config SIFIVE_U
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
 --
-.28.0
+.31.1

-[PULL 26/30] hw/riscv: Move sifive_uart model to hw/char
+[PULL 32/33] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
-From: Bin Meng <bin.meng@windriver.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Using memory_region_init_ram(), which can't possibly handle vhost-user,
-should only contain the RISC-V SoC / machine codes plus generic
+and can't work as expected with '-numa node,memdev' options.
 codes. Let's move sifive_uart model to hw/char directory.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Use MachineState::ram instead of manually initializing RAM memory
 region, as well as by providing MachineClass::default_ram_id to
 opt in to memdev scheme.
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
+Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => char}/sifive_uart.h | 0
+ hw/riscv/sifive_u.c | 6 ++----
- hw/{riscv => char}/sifive_uart.c         | 2 +-
+file changed, 2 insertions(+), 4 deletions(-)
  hw/riscv/sifive_e.c                      | 2 +-
  hw/riscv/sifive_u.c                      | 2 +-
  hw/char/Kconfig                          | 3 +++
  hw/char/meson.build                      | 1 +
  hw/riscv/Kconfig                         | 2 ++
  hw/riscv/meson.build                     | 1 -
 files changed, 9 insertions(+), 4 deletions(-)
  rename include/hw/{riscv => char}/sifive_uart.h (100%)
  rename hw/{riscv => char}/sifive_uart.c (99%)
-diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
-similarity index 100%
-rename from include/hw/riscv/sifive_uart.h
-rename to include/hw/char/sifive_uart.h
-diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
-similarity index 99%
-rename from hw/riscv/sifive_uart.c
-rename to hw/char/sifive_uart.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_uart.c
-+++ b/hw/char/sifive_uart.c
-@@ -XXX,XX +XXX,XX @@
- #include "chardev/char-fe.h"
- #include "hw/hw.h"
- #include "hw/irq.h"
--#include "hw/riscv/sifive_uart.h"
-+#include "hw/char/sifive_uart.h"
- /*
-  * Not yet implemented:
-diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_e.c
-+++ b/hw/riscv/sifive_e.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/misc/unimp.h"
- #include "target/riscv/cpu.h"
- #include "hw/riscv/riscv_hart.h"
--#include "hw/riscv/sifive_uart.h"
- #include "hw/riscv/sifive_e.h"
- #include "hw/riscv/boot.h"
-+#include "hw/char/sifive_uart.h"
- #include "hw/intc/sifive_clint.h"
- #include "hw/intc/sifive_plic.h"
- #include "hw/misc/sifive_e_prci.h"
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
- #include "hw/misc/unimp.h"
+     const MemMapEntry *memmap = sifive_u_memmap;
- #include "target/riscv/cpu.h"
+     SiFiveUState *s = RISCV_U_MACHINE(machine);
- #include "hw/riscv/riscv_hart.h"
+     MemoryRegion *system_memory = get_system_memory();
--#include "hw/riscv/sifive_uart.h"
+-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- #include "hw/riscv/sifive_u.h"
+     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
- #include "hw/riscv/boot.h"
+     target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
-+#include "hw/char/sifive_uart.h"
+     target_ulong firmware_end_addr, kernel_start_addr;
- #include "hw/intc/sifive_clint.h"
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
- #include "hw/intc/sifive_plic.h"
+     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
- #include "chardev/char.h"
-diff --git a/hw/char/Kconfig b/hw/char/Kconfig
+     /* register RAM */
-index XXXXXXX..XXXXXXX 100644
+-    memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
---- a/hw/char/Kconfig
+-                           machine->ram_size, &error_fatal);
-+++ b/hw/char/Kconfig
+     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
-@@ -XXX,XX +XXX,XX @@ config AVR_USART
+-                                main_mem);
++                                machine->ram);
- config MCHP_PFSOC_MMUART
-     bool
+     /* register QSPI0 Flash */
-+
+     memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
-+config SIFIVE_UART
+@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
-+    bool
+     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
-diff --git a/hw/char/meson.build b/hw/char/meson.build
+     mc->default_cpu_type = SIFIVE_U_CPU;
-index XXXXXXX..XXXXXXX 100644
+     mc->default_cpus = mc->min_cpus;
---- a/hw/char/meson.build
++    mc->default_ram_id = "riscv.sifive.u.ram";
-+++ b/hw/char/meson.build
-@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
+     object_class_property_add_bool(oc, "start-in-flash",
- softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
+                                    sifive_u_machine_get_start_in_flash,
  softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
  softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
 +softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
  softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
  softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
  softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
      select SIFIVE_CLINT
      select SIFIVE_GPIO
      select SIFIVE_PLIC
 +    select SIFIVE_UART
      select SIFIVE_E_PRCI
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select SIFIVE_GPIO
      select SIFIVE_PDMA
      select SIFIVE_PLIC
 +    select SIFIVE_UART
      select SIFIVE_U_OTP
      select SIFIVE_U_PRCI
      select UNIMP
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
  riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 --
-.28.0
+.31.1

-[PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc
+[PULL 33/33] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id
-From: Bin Meng <bin.meng@windriver.com>
+From: Bin Meng <bmeng.cn@gmail.com>
-This is an effort to clean up the hw/riscv directory. Ideally it
+Using memory_region_init_ram(), which can't possibly handle vhost-user,
-should only contain the RISC-V SoC / machine codes plus generic
+and can't work as expected with '-numa node,memdev' options.
 codes. Let's move sifive_clint model to hw/intc directory.
-Signed-off-by: Bin Meng <bin.meng@windriver.com>
+Use MachineState::ram instead of manually initializing RAM memory
 region, as well as by providing MachineClass::default_ram_id to
 opt in to memdev scheme.
 Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
+Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/{riscv => intc}/sifive_clint.h | 0
+ hw/riscv/spike.c | 6 ++----
- hw/{riscv => intc}/sifive_clint.c         | 2 +-
+file changed, 2 insertions(+), 4 deletions(-)
  hw/riscv/microchip_pfsoc.c                | 2 +-
  hw/riscv/sifive_e.c                       | 2 +-
  hw/riscv/sifive_u.c                       | 2 +-
  hw/riscv/spike.c                          | 2 +-
  hw/riscv/virt.c                           | 2 +-
  hw/intc/Kconfig                           | 3 +++
  hw/intc/meson.build                       | 1 +
  hw/riscv/Kconfig                          | 5 +++++
  hw/riscv/meson.build                      | 1 -
 files changed, 15 insertions(+), 7 deletions(-)
  rename include/hw/{riscv => intc}/sifive_clint.h (100%)
  rename hw/{riscv => intc}/sifive_clint.c (99%)
-diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
-similarity index 100%
-rename from include/hw/riscv/sifive_clint.h
-rename to include/hw/intc/sifive_clint.h
-diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
-similarity index 99%
-rename from hw/riscv/sifive_clint.c
-rename to hw/intc/sifive_clint.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_clint.c
-+++ b/hw/intc/sifive_clint.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/sysbus.h"
- #include "target/riscv/cpu.h"
- #include "hw/qdev-properties.h"
--#include "hw/riscv/sifive_clint.h"
-+#include "hw/intc/sifive_clint.h"
- #include "qemu/timer.h"
- static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
-diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/microchip_pfsoc.c
-+++ b/hw/riscv/microchip_pfsoc.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/misc/unimp.h"
- #include "hw/riscv/boot.h"
- #include "hw/riscv/riscv_hart.h"
--#include "hw/riscv/sifive_clint.h"
- #include "hw/riscv/sifive_plic.h"
- #include "hw/riscv/microchip_pfsoc.h"
-+#include "hw/intc/sifive_clint.h"
- #include "sysemu/sysemu.h"
- /*
-diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_e.c
-+++ b/hw/riscv/sifive_e.c
-@@ -XXX,XX +XXX,XX @@
- #include "target/riscv/cpu.h"
- #include "hw/riscv/riscv_hart.h"
- #include "hw/riscv/sifive_plic.h"
--#include "hw/riscv/sifive_clint.h"
- #include "hw/riscv/sifive_uart.h"
- #include "hw/riscv/sifive_e.h"
- #include "hw/riscv/boot.h"
-+#include "hw/intc/sifive_clint.h"
- #include "hw/misc/sifive_e_prci.h"
- #include "chardev/char.h"
- #include "sysemu/arch_init.h"
-diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/sifive_u.c
-+++ b/hw/riscv/sifive_u.c
-@@ -XXX,XX +XXX,XX @@
- #include "target/riscv/cpu.h"
- #include "hw/riscv/riscv_hart.h"
- #include "hw/riscv/sifive_plic.h"
--#include "hw/riscv/sifive_clint.h"
- #include "hw/riscv/sifive_uart.h"
- #include "hw/riscv/sifive_u.h"
- #include "hw/riscv/boot.h"
-+#include "hw/intc/sifive_clint.h"
- #include "chardev/char.h"
- #include "net/eth.h"
- #include "sysemu/arch_init.h"
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/spike.c
 +++ b/hw/riscv/spike.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
- #include "target/riscv/cpu.h"
+     const MemMapEntry *memmap = spike_memmap;
- #include "hw/riscv/riscv_htif.h"
+     SpikeState *s = SPIKE_MACHINE(machine);
- #include "hw/riscv/riscv_hart.h"
+     MemoryRegion *system_memory = get_system_memory();
--#include "hw/riscv/sifive_clint.h"
+-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- #include "hw/riscv/spike.h"
+     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
- #include "hw/riscv/boot.h"
+     target_ulong firmware_end_addr, kernel_start_addr;
- #include "hw/riscv/numa.h"
+     uint32_t fdt_load_addr;
-+#include "hw/intc/sifive_clint.h"
+@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
- #include "chardev/char.h"
+     }
- #include "sysemu/arch_init.h"
- #include "sysemu/device_tree.h"
+     /* register system main memory (actual RAM) */
-diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+-    memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
-index XXXXXXX..XXXXXXX 100644
+-                           machine->ram_size, &error_fatal);
---- a/hw/riscv/virt.c
+     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
-+++ b/hw/riscv/virt.c
+-        main_mem);
-@@ -XXX,XX +XXX,XX @@
++        machine->ram);
- #include "target/riscv/cpu.h"
- #include "hw/riscv/riscv_hart.h"
+     /* create device tree */
- #include "hw/riscv/sifive_plic.h"
+     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
--#include "hw/riscv/sifive_clint.h"
+@@ -XXX,XX +XXX,XX @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
- #include "hw/riscv/sifive_test.h"
+     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
- #include "hw/riscv/virt.h"
+     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
- #include "hw/riscv/boot.h"
+     mc->numa_mem_supported = true;
- #include "hw/riscv/numa.h"
++    mc->default_ram_id = "riscv.spike.ram";
-+#include "hw/intc/sifive_clint.h"
+ }
- #include "chardev/char.h"
- #include "sysemu/arch_init.h"
+ static const TypeInfo spike_machine_typeinfo = {
  #include "sysemu/device_tree.h"
 diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/Kconfig
 +++ b/hw/intc/Kconfig
@@ -XXX,XX +XXX,XX @@ config RX_ICU
  config LOONGSON_LIOINTC
      bool
 +
 +config SIFIVE_CLINT
 +    bool
 diff --git a/hw/intc/meson.build b/hw/intc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/intc/meson.build
 +++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
  specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
  specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
  specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
 +specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
  specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
  specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
  specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/Kconfig
 +++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
      bool
      select HART
      select SIFIVE
 +    select SIFIVE_CLINT
      select SIFIVE_GPIO
      select SIFIVE_E_PRCI
      select UNIMP
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
      select CADENCE
      select HART
      select SIFIVE
 +    select SIFIVE_CLINT
      select SIFIVE_GPIO
      select SIFIVE_PDMA
      select SIFIVE_U_OTP
@@ -XXX,XX +XXX,XX @@ config SPIKE
      select HART
      select HTIF
      select SIFIVE
 +    select SIFIVE_CLINT
  config OPENTITAN
      bool
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
      select PCI_EXPRESS_GENERIC_BRIDGE
      select PFLASH_CFI01
      select SIFIVE
 +    select SIFIVE_CLINT
  config MICROCHIP_PFSOC
      bool
      select HART
      select SIFIVE
 +    select SIFIVE_CLINT
      select UNIMP
      select MCHP_PFSOC_MMUART
      select SIFIVE_PDMA
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/meson.build
 +++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
  riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
  riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
  riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
  riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 --
-.28.0
+.31.1

The following changes since commit 9435a8b3dd35f1f926f1b9127e8a906217a5518a:

Merge remote-tracking branch 'remotes/kraxel/tags/sirius/ipxe-20200908-pull-request' into staging (2020-09-08 21:21:13 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200910

for you to fetch changes up to 7595a65818ea9b49c36650a8c217a1ef9bd6e62a:

hw/riscv: Sort the Kconfig options in alphabetical order (2020-09-09 15:54:19 -0700)

----------------------------------------------------------------
This PR includes multiple fixes and features for RISC-V:
 - Fixes a bug in printing trap causes
 - Allows 16-bit writes to the SiFive test device. This fixes the
   failure to reboot the RISC-V virt machine
 - Support for the Microchip PolarFire SoC and Icicle Kit
 - A reafactor of RISC-V code out of hw/riscv

----------------------------------------------------------------
Bin Meng (28):
      target/riscv: cpu: Add a new 'resetvec' property
      hw/riscv: hart: Add a new 'resetvec' property
      target/riscv: cpu: Set reset vector based on the configured property value
      hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board
      hw/char: Add Microchip PolarFire SoC MMUART emulation
      hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
      hw/sd: Add Cadence SDHCI emulation
      hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card
      hw/dma: Add SiFive platform DMA controller emulation
      hw/riscv: microchip_pfsoc: Connect a DMA controller
      hw/net: cadence_gem: Add a new 'phy-addr' property
      hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
      hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
      hw/riscv: microchip_pfsoc: Hook GPIO controllers
      hw/riscv: clint: Avoid using hard-coded timebase frequency
      hw/riscv: sifive_u: Connect a DMA controller
      hw/riscv: Move sifive_e_prci model to hw/misc
      hw/riscv: Move sifive_u_prci model to hw/misc
      hw/riscv: Move sifive_u_otp model to hw/misc
      hw/riscv: Move sifive_gpio model to hw/gpio
      hw/riscv: Move sifive_clint model to hw/intc
      hw/riscv: Move sifive_plic model to hw/intc
      hw/riscv: Move riscv_htif model to hw/char
      hw/riscv: Move sifive_uart model to hw/char
      hw/riscv: Move sifive_test model to hw/misc
      hw/riscv: Always build riscv_hart.c
      hw/riscv: Drop CONFIG_SIFIVE
      hw/riscv: Sort the Kconfig options in alphabetical order

Nathan Chancellor (1):
      riscv: sifive_test: Allow 16-bit writes to memory region

Yifei Jiang (1):
      target/riscv: Fix bug in getting trap cause name for trace_riscv_trap

default-configs/riscv64-softmmu.mak         |   1 +
 {include/hw/riscv => hw/intc}/sifive_plic.h |   0
 hw/riscv/trace.h                            |   1 -
 include/hw/char/mchp_pfsoc_mmuart.h         |  61 ++++
 include/hw/{riscv => char}/riscv_htif.h     |   0
 include/hw/{riscv => char}/sifive_uart.h    |   0
 include/hw/dma/sifive_pdma.h                |  57 ++++
 include/hw/{riscv => gpio}/sifive_gpio.h    |   0
 include/hw/{riscv => intc}/sifive_clint.h   |   4 +-
 include/hw/{riscv => misc}/sifive_e_prci.h  |   0
 include/hw/{riscv => misc}/sifive_test.h    |   0
 include/hw/{riscv => misc}/sifive_u_otp.h   |   0
 include/hw/{riscv => misc}/sifive_u_prci.h  |   0
 include/hw/net/cadence_gem.h                |   2 +
 include/hw/riscv/microchip_pfsoc.h          | 133 +++++++++
 include/hw/riscv/riscv_hart.h               |   1 +
 include/hw/riscv/sifive_e.h                 |   2 +-
 include/hw/riscv/sifive_u.h                 |  17 +-
 include/hw/sd/cadence_sdhci.h               |  47 +++
 target/riscv/cpu.h                          |   8 +-
 hw/arm/xilinx_zynq.c                        |   1 +
 hw/arm/xlnx-versal.c                        |   1 +
 hw/arm/xlnx-zynqmp.c                        |   2 +
 hw/char/mchp_pfsoc_mmuart.c                 |  86 ++++++
 hw/{riscv => char}/riscv_htif.c             |   2 +-
 hw/{riscv => char}/sifive_uart.c            |   2 +-
 hw/dma/sifive_pdma.c                        | 313 ++++++++++++++++++++
 hw/{riscv => gpio}/sifive_gpio.c            |   2 +-
 hw/{riscv => intc}/sifive_clint.c           |  28 +-
 hw/{riscv => intc}/sifive_plic.c            |   2 +-
 hw/{riscv => misc}/sifive_e_prci.c          |   2 +-
 hw/{riscv => misc}/sifive_test.c            |   4 +-
 hw/{riscv => misc}/sifive_u_otp.c           |   2 +-
 hw/{riscv => misc}/sifive_u_prci.c          |   2 +-
 hw/net/cadence_gem.c                        |   7 +-
 hw/riscv/microchip_pfsoc.c                  | 437 ++++++++++++++++++++++++++++
 hw/riscv/opentitan.c                        |   1 +
 hw/riscv/riscv_hart.c                       |   3 +
 hw/riscv/sifive_e.c                         |  12 +-
 hw/riscv/sifive_u.c                         |  41 ++-
 hw/riscv/spike.c                            |   7 +-
 hw/riscv/virt.c                             |   9 +-
 hw/sd/cadence_sdhci.c                       | 193 ++++++++++++
 target/riscv/cpu.c                          |  19 +-
 target/riscv/cpu_helper.c                   |   8 +-
 target/riscv/csr.c                          |   4 +-
 MAINTAINERS                                 |   9 +
 hw/char/Kconfig                             |   9 +
 hw/char/meson.build                         |   3 +
 hw/dma/Kconfig                              |   3 +
 hw/dma/meson.build                          |   1 +
 hw/gpio/Kconfig                             |   3 +
 hw/gpio/meson.build                         |   1 +
 hw/gpio/trace-events                        |   6 +
 hw/intc/Kconfig                             |   6 +
 hw/intc/meson.build                         |   2 +
 hw/misc/Kconfig                             |  12 +
 hw/misc/meson.build                         |   6 +
 hw/riscv/Kconfig                            |  70 +++--
 hw/riscv/meson.build                        |  12 +-
 hw/riscv/trace-events                       |   7 -
 hw/sd/Kconfig                               |   4 +
 hw/sd/meson.build                           |   1 +
 meson.build                                 |   1 -
 64 files changed, 1575 insertions(+), 105 deletions(-)
 rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
 delete mode 100644 hw/riscv/trace.h
 create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
 rename include/hw/{riscv => char}/riscv_htif.h (100%)
 rename include/hw/{riscv => char}/sifive_uart.h (100%)
 create mode 100644 include/hw/dma/sifive_pdma.h
 rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
 rename include/hw/{riscv => intc}/sifive_clint.h (92%)
 rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
 rename include/hw/{riscv => misc}/sifive_test.h (100%)
 rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
 rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
 create mode 100644 include/hw/riscv/microchip_pfsoc.h
 create mode 100644 include/hw/sd/cadence_sdhci.h
 create mode 100644 hw/char/mchp_pfsoc_mmuart.c
 rename hw/{riscv => char}/riscv_htif.c (99%)
 rename hw/{riscv => char}/sifive_uart.c (99%)
 create mode 100644 hw/dma/sifive_pdma.c
 rename hw/{riscv => gpio}/sifive_gpio.c (99%)
 rename hw/{riscv => intc}/sifive_clint.c (90%)
 rename hw/{riscv => intc}/sifive_plic.c (99%)
 rename hw/{riscv => misc}/sifive_e_prci.c (99%)
 rename hw/{riscv => misc}/sifive_test.c (97%)
 rename hw/{riscv => misc}/sifive_u_otp.c (99%)
 rename hw/{riscv => misc}/sifive_u_prci.c (99%)
 create mode 100644 hw/riscv/microchip_pfsoc.c
 create mode 100644 hw/sd/cadence_sdhci.c
 delete mode 100644 hw/riscv/trace-events

From: Yifei Jiang <jiangyifei@huawei.com>

When the cause number is equal to or greater than 23, print "(unknown)" in
trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last
excpetion "guest_store_page_fault" can not be printed.

In addition, the current check of cause is invalid for riscv_intr_names. So
introduce riscv_cpu_get_trap_name to get the trap cause name.

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200814035819.1214-1-jiangyifei@huawei.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  1 +
 target/riscv/cpu.c        | 11 +++++++++++
 target/riscv/cpu_helper.c |  4 ++--
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ extern const char * const riscv_fpr_regnames[];
 extern const char * const riscv_excp_names[];
 extern const char * const riscv_intr_names[];
 
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
 void riscv_cpu_do_interrupt(CPUState *cpu);
 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char * const riscv_intr_names[] = {
     "reserved"
 };
 
+const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
+{
+    if (async) {
+        return (cause < ARRAY_SIZE(riscv_intr_names)) ?
+               riscv_intr_names[cause] : "(unknown)";
+    } else {
+        return (cause < ARRAY_SIZE(riscv_excp_names)) ?
+               riscv_excp_names[cause] : "(unknown)";
+    }
+}
+
 static void set_misa(CPURISCVState *env, target_ulong misa)
 {
     env->misa_mask = env->misa = misa;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         }
     }
 
-    trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ?
-        (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)");
+    trace_riscv_trap(env->mhartid, async, cause, env->pc, tval,
+        riscv_cpu_get_trap_name(cause, async));
 
     if (env->priv <= PRV_S &&
             cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {
-- 
2.28.0

From: Nathan Chancellor <natechancellor@gmail.com>

When shutting down the machine running a mainline Linux kernel, the
following error happens:

$ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \
    -display none -initrd rootfs.cpio -kernel Image -m 512m \
    -nodefaults -serial mon:stdio
...
Requesting system poweroff
[    4.999630] reboot: Power down
sbi_trap_error: hart0: trap handler failed (error -2)
sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000
sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822
sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78
sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0
sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040
sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024
sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024
sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555
sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158
sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000
sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000
sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000
sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000
sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008
sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000
sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000
sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000
sbi_trap_error: hart0: t6=0x0000000000000000

The kernel does a 16-bit write when powering off the machine, which
was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept
mismatching sizes in memory_region_access_valid""). Make min_access_size
match reality so that the machine can shut down properly now.

Cc: qemu-stable@nongnu.org
Fixes: 88a07990fa ("SiFive RISC-V Test Finisher")
Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200901055822.2721209-1-natechancellor@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_test_ops = {
     .write = sifive_test_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
     .valid = {
-        .min_access_size = 4,
+        .min_access_size = 2,
         .max_access_size = 4
     }
 };
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.

Normally reset vector address is a configurable parameter. Let's
create a 64-bit property to store the reset vector address which
covers both 32-bit and 64-bit CPUs.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h | 1 +
 target/riscv/cpu.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVCPU {
         uint16_t elen;
         bool mmu;
         bool pmp;
+        uint64_t resetvec;
     } cfg;
 } RISCVCPU;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+    DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/riscv_hart.h | 1 +
 hw/riscv/riscv_hart.c         | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -XXX,XX +XXX,XX @@ typedef struct RISCVHartArrayState {
     uint32_t num_harts;
     uint32_t hartid_base;
     char *cpu_type;
+    uint64_t resetvec;
     RISCVCPU *harts;
 } RISCVHartArrayState;
 
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -XXX,XX +XXX,XX @@ static Property riscv_harts_props[] = {
     DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
     DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
     DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
+    DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
+                       DEFAULT_RSTVEC),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
                                char *cpu_type, Error **errp)
 {
     object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
+    qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
     s->harts[idx].env.mhartid = s->hartid_base + idx;
     qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
     return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 1 +
 hw/riscv/sifive_e.c  | 1 +
 hw/riscv/sifive_u.c  | 2 ++
 target/riscv/cpu.c   | 7 ++-----
 4 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
 
     /* Boot ROM */
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_init(Object *obj)
     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
     object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
                             TYPE_SIFIVE_GPIO);
 }
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
     qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
+    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
 
     object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
     qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
     qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
+    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
 
     object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
     object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_11_0);
-    set_resetvec(env, DEFAULT_RSTVEC);
 }
 
 static void riscv_base_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void riscv_base_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
     set_misa(env, 0);
-    set_resetvec(env, DEFAULT_RSTVEC);
 }
 
 static void rvxx_sifive_u_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_u_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, 0x1004);
 }
 
 static void rvxx_sifive_e_cpu_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void rvxx_sifive_e_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, 0x1004);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
 
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
-    set_resetvec(env, 0x8090);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
 
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         set_feature(env, RISCV_FEATURE_PMP);
     }
 
+    set_resetvec(env, cpu->cfg.resetvec);
+
     /* If misa isn't set (rv32 and rv64 machines) set it here */
     if (!env->misa) {
         /* Do some ISA extension error checking */
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an initial support for Microchip PolarFire SoC Icicle Kit.
The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
E51 plus four U54 cores and many on-chip peripherals and an FPGA.

For more details about Microchip PolarFire Soc, please see:
https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga

Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
The following perepherals are created as an unimplemented device:

- Bus Error Uint 0/1/2/3/4
- L2 cache controller
- SYSREG
- MPUCFG
- IOSCBCFG

More devices will be added later.

The BIOS image used by this machine is hss.bin, aka Hart Software
Services, which can be built from:
https://github.com/polarfire-soc/hart-software-services

To launch this machine:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit

The memory is set to 1 GiB by default to match the hardware.
A sanity check on ram size is performed in the machine init routine
to prompt user to increase the RAM size to > 1 GiB when less than
1 GiB ram is detected.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 default-configs/riscv64-softmmu.mak |   1 +
 include/hw/riscv/microchip_pfsoc.h  |  88 ++++++++
 hw/riscv/microchip_pfsoc.c          | 312 ++++++++++++++++++++++++++++
 MAINTAINERS                         |   7 +
 hw/riscv/Kconfig                    |   6 +
 hw/riscv/meson.build                |   1 +
 6 files changed, 415 insertions(+)
 create mode 100644 include/hw/riscv/microchip_pfsoc.h
 create mode 100644 hw/riscv/microchip_pfsoc.c

diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_SPIKE=y
 CONFIG_SIFIVE_E=y
 CONFIG_SIFIVE_U=y
 CONFIG_RISCV_VIRT=y
+CONFIG_MICROCHIP_PFSOC=y
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC machine interface
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MICROCHIP_PFSOC_H
+#define HW_MICROCHIP_PFSOC_H
+
+typedef struct MicrochipPFSoCState {
+    /*< private >*/
+    DeviceState parent_obj;
+
+    /*< public >*/
+    CPUClusterState e_cluster;
+    CPUClusterState u_cluster;
+    RISCVHartArrayState e_cpus;
+    RISCVHartArrayState u_cpus;
+    DeviceState *plic;
+} MicrochipPFSoCState;
+
+#define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
+#define MICROCHIP_PFSOC(obj) \
+    OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC)
+
+typedef struct MicrochipIcicleKitState {
+    /*< private >*/
+    MachineState parent_obj;
+
+    /*< public >*/
+    MicrochipPFSoCState soc;
+} MicrochipIcicleKitState;
+
+#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \
+    MACHINE_TYPE_NAME("microchip-icicle-kit")
+#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \
+    OBJECT_CHECK(MicrochipIcicleKitState, (obj), \
+                 TYPE_MICROCHIP_ICICLE_KIT_MACHINE)
+
+enum {
+    MICROCHIP_PFSOC_DEBUG,
+    MICROCHIP_PFSOC_E51_DTIM,
+    MICROCHIP_PFSOC_BUSERR_UNIT0,
+    MICROCHIP_PFSOC_BUSERR_UNIT1,
+    MICROCHIP_PFSOC_BUSERR_UNIT2,
+    MICROCHIP_PFSOC_BUSERR_UNIT3,
+    MICROCHIP_PFSOC_BUSERR_UNIT4,
+    MICROCHIP_PFSOC_CLINT,
+    MICROCHIP_PFSOC_L2CC,
+    MICROCHIP_PFSOC_L2LIM,
+    MICROCHIP_PFSOC_PLIC,
+    MICROCHIP_PFSOC_SYSREG,
+    MICROCHIP_PFSOC_MPUCFG,
+    MICROCHIP_PFSOC_ENVM_CFG,
+    MICROCHIP_PFSOC_ENVM_DATA,
+    MICROCHIP_PFSOC_IOSCB_CFG,
+    MICROCHIP_PFSOC_DRAM,
+};
+
+#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
+#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
+
+#define MICROCHIP_PFSOC_PLIC_HART_CONFIG        "MS"
+#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES        185
+#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES     7
+#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE      0x04
+#define MICROCHIP_PFSOC_PLIC_PENDING_BASE       0x1000
+#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE        0x2000
+#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE      0x80
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE       0x200000
+#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE     0x1000
+
+#endif /* HW_MICROCHIP_PFSOC_H */
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
+ *
+ * 0) CLINT (Core Level Interruptor)
+ * 1) PLIC (Platform Level Interrupt Controller)
+ * 2) eNVM (Embedded Non-Volatile Memory)
+ *
+ * This board currently generates devicetree dynamically that indicates at least
+ * two harts and up to five harts.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qemu/units.h"
+#include "qemu/cutils.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/irq.h"
+#include "hw/loader.h"
+#include "hw/sysbus.h"
+#include "hw/cpu/cluster.h"
+#include "target/riscv/cpu.h"
+#include "hw/misc/unimp.h"
+#include "hw/riscv/boot.h"
+#include "hw/riscv/riscv_hart.h"
+#include "hw/riscv/sifive_clint.h"
+#include "hw/riscv/sifive_plic.h"
+#include "hw/riscv/microchip_pfsoc.h"
+
+/*
+ * The BIOS image used by this machine is called Hart Software Services (HSS).
+ * See https://github.com/polarfire-soc/hart-software-services
+ */
+#define BIOS_FILENAME   "hss.bin"
+#define RESET_VECTOR    0x20220000
+
+static const struct MemmapEntry {
+    hwaddr base;
+    hwaddr size;
+} microchip_pfsoc_memmap[] = {
+    [MICROCHIP_PFSOC_DEBUG] =           {        0x0,     0x1000 },
+    [MICROCHIP_PFSOC_E51_DTIM] =        {  0x1000000,     0x2000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT0] =    {  0x1700000,     0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT1] =    {  0x1701000,     0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT2] =    {  0x1702000,     0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT3] =    {  0x1703000,     0x1000 },
+    [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
+    [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
+    [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
+    [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
+    [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
+    [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
+    [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
+    [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
+    [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
+    [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
+    [MICROCHIP_PFSOC_DRAM] =            { 0x80000000,        0x0 },
+};
+
+static void microchip_pfsoc_soc_instance_init(Object *obj)
+{
+    MachineState *ms = MACHINE(qdev_get_machine());
+    MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
+
+    object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
+    qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
+
+    object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
+                            TYPE_RISCV_HART_ARRAY);
+    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
+    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
+    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
+                         TYPE_RISCV_CPU_SIFIVE_E51);
+    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
+
+    object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
+    qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
+
+    object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
+                            TYPE_RISCV_HART_ARRAY);
+    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
+    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
+    qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
+                         TYPE_RISCV_CPU_SIFIVE_U54);
+    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
+}
+
+static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
+{
+    MachineState *ms = MACHINE(qdev_get_machine());
+    MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
+    const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
+    MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
+    MemoryRegion *envm_data = g_new(MemoryRegion, 1);
+    char *plic_hart_config;
+    size_t plic_hart_config_len;
+    int i;
+
+    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
+    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
+    /*
+     * The cluster must be realized after the RISC-V hart array container,
+     * as the container's CPU object is only created on realize, and the
+     * CPU must exist and have been parented into the cluster before the
+     * cluster is realized.
+     */
+    qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
+    qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
+
+    /* E51 DTIM */
+    memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
+                           memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_E51_DTIM].base,
+                                e51_dtim_mem);
+
+    /* Bus Error Units */
+    create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
+    create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
+    create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
+    create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
+    create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
+        memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
+
+    /* CLINT */
+    sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
+        memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+
+    /* L2 cache controller */
+    create_unimplemented_device("microchip.pfsoc.l2cc",
+        memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
+
+    /*
+     * Add L2-LIM at reset size.
+     * This should be reduced in size as the L2 Cache Controller WayEnable
+     * register is incremented. Unfortunately I don't see a nice (or any) way
+     * to handle reducing or blocking out the L2 LIM while still allowing it
+     * be re returned to all enabled after a reset. For the time being, just
+     * leave it enabled all the time. This won't break anything, but will be
+     * too generous to misbehaving guests.
+     */
+    memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
+                           memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_L2LIM].base,
+                                l2lim_mem);
+
+    /* create PLIC hart topology configuration string */
+    plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) *
+                           ms->smp.cpus;
+    plic_hart_config = g_malloc0(plic_hart_config_len);
+    for (i = 0; i < ms->smp.cpus; i++) {
+        if (i != 0) {
+            strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG,
+                    plic_hart_config_len);
+        } else {
+            strncat(plic_hart_config, "M", plic_hart_config_len);
+        }
+        plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1);
+    }
+
+    /* PLIC */
+    s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
+        plic_hart_config, 0,
+        MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
+        MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
+        MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
+        MICROCHIP_PFSOC_PLIC_PENDING_BASE,
+        MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
+        MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
+        MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
+        MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
+        memmap[MICROCHIP_PFSOC_PLIC].size);
+    g_free(plic_hart_config);
+
+    /* SYSREG */
+    create_unimplemented_device("microchip.pfsoc.sysreg",
+        memmap[MICROCHIP_PFSOC_SYSREG].base,
+        memmap[MICROCHIP_PFSOC_SYSREG].size);
+
+    /* MPUCFG */
+    create_unimplemented_device("microchip.pfsoc.mpucfg",
+        memmap[MICROCHIP_PFSOC_MPUCFG].base,
+        memmap[MICROCHIP_PFSOC_MPUCFG].size);
+
+    /* eNVM */
+    memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
+                           memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
+                           &error_fatal);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
+                                envm_data);
+
+    /* IOSCBCFG */
+    create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
+        memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
+        memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
+}
+
+static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = microchip_pfsoc_soc_realize;
+    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
+    dc->user_creatable = false;
+}
+
+static const TypeInfo microchip_pfsoc_soc_type_info = {
+    .name = TYPE_MICROCHIP_PFSOC,
+    .parent = TYPE_DEVICE,
+    .instance_size = sizeof(MicrochipPFSoCState),
+    .instance_init = microchip_pfsoc_soc_instance_init,
+    .class_init = microchip_pfsoc_soc_class_init,
+};
+
+static void microchip_pfsoc_soc_register_types(void)
+{
+    type_register_static(&microchip_pfsoc_soc_type_info);
+}
+
+type_init(microchip_pfsoc_soc_register_types)
+
+static void microchip_icicle_kit_machine_init(MachineState *machine)
+{
+    MachineClass *mc = MACHINE_GET_CLASS(machine);
+    const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
+    MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+
+    /* Sanity check on RAM size */
+    if (machine->ram_size < mc->default_ram_size) {
+        char *sz = size_to_str(mc->default_ram_size);
+        error_report("Invalid RAM size, should be bigger than %s", sz);
+        g_free(sz);
+        exit(EXIT_FAILURE);
+    }
+
+    /* Initialize SoC */
+    object_initialize_child(OBJECT(machine), "soc", &s->soc,
+                            TYPE_MICROCHIP_PFSOC);
+    qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
+
+    /* Register RAM */
+    memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
+                           machine->ram_size, &error_fatal);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
+
+    /* Load the firmware */
+    riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
+}
+
+static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->desc = "Microchip PolarFire SoC Icicle Kit";
+    mc->init = microchip_icicle_kit_machine_init;
+    mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
+                   MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
+    mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
+    mc->default_cpus = mc->min_cpus;
+    mc->default_ram_size = 1 * GiB;
+}
+
+static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
+    .name       = MACHINE_TYPE_NAME("microchip-icicle-kit"),
+    .parent     = TYPE_MACHINE,
+    .class_init = microchip_icicle_kit_machine_class_init,
+    .instance_size = sizeof(MicrochipIcicleKitState),
+};
+
+static void microchip_icicle_kit_machine_init_register_types(void)
+{
+    type_register_static(&microchip_icicle_kit_machine_typeinfo);
+}
+
+type_init(microchip_icicle_kit_machine_init_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/riscv/opentitan.h
 F: include/hw/char/ibex_uart.h
 F: include/hw/intc/ibex_plic.h
 
+Microchip PolarFire SoC Icicle Kit
+M: Bin Meng <bin.meng@windriver.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: hw/riscv/microchip_pfsoc.c
+F: include/hw/riscv/microchip_pfsoc.h
+
 RX Machines
 -----------
 rx-gdbsim
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PFLASH_CFI01
     select SIFIVE
+
+config MICROCHIP_PFSOC
+    bool
+    select HART
+    select SIFIVE
+    select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
+riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 
 hw_arch += {'riscv': riscv_ss}
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC MMUART is ns16550 compatible, with some
additional registers. Create a simple MMUART model built on top
of the existing ns16550 model.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++++++++++++++++++
 hw/char/mchp_pfsoc_mmuart.c         | 86 +++++++++++++++++++++++++++++
 MAINTAINERS                         |  2 +
 hw/char/Kconfig                     |  3 +
 hw/char/meson.build                 |  1 +
 5 files changed, 153 insertions(+)
 create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h
 create mode 100644 hw/char/mchp_pfsoc_mmuart.c

diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfsoc_mmuart.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/char/mchp_pfsoc_mmuart.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC MMUART emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MCHP_PFSOC_MMUART_H
+#define HW_MCHP_PFSOC_MMUART_H
+
+#include "hw/char/serial.h"
+
+#define MCHP_PFSOC_MMUART_REG_SIZE  52
+
+typedef struct MchpPfSoCMMUartState {
+    MemoryRegion iomem;
+    hwaddr base;
+    qemu_irq irq;
+
+    SerialMM *serial;
+
+    uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)];
+} MchpPfSoCMMUartState;
+
+/**
+ * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
+ *
+ * This is a helper routine for board to create a MMUART device that is
+ * compatible with Microchip PolarFire SoC.
+ *
+ * @sysmem: system memory region to map
+ * @base: base address of the MMUART registers
+ * @irq: IRQ number of the MMUART device
+ * @chr: character device to associate to
+ *
+ * @return: a pointer to the device specific control structure
+ */
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+    hwaddr base, qemu_irq irq, Chardev *chr);
+
+#endif /* HW_MCHP_PFSOC_MMUART_H */
diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/char/mchp_pfsoc_mmuart.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Microchip PolarFire SoC MMUART emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "chardev/char.h"
+#include "exec/address-spaces.h"
+#include "hw/char/mchp_pfsoc_mmuart.h"
+
+static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
+{
+    MchpPfSoCMMUartState *s = opaque;
+
+    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
+                      __func__, addr);
+        return 0;
+    }
+
+    return s->reg[addr / sizeof(uint32_t)];
+}
+
+static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
+                                    uint64_t value, unsigned size)
+{
+    MchpPfSoCMMUartState *s = opaque;
+    uint32_t val32 = (uint32_t)value;
+
+    if (addr >= MCHP_PFSOC_MMUART_REG_SIZE) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
+                      " v=0x%x\n", __func__, addr, val32);
+        return;
+    }
+
+    s->reg[addr / sizeof(uint32_t)] = val32;
+}
+
+static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
+    .read = mchp_pfsoc_mmuart_read,
+    .write = mchp_pfsoc_mmuart_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
+    hwaddr base, qemu_irq irq, Chardev *chr)
+{
+    MchpPfSoCMMUartState *s;
+
+    s = g_new0(MchpPfSoCMMUartState, 1);
+
+    memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s,
+                          "mchp.pfsoc.mmuart", 0x1000);
+
+    s->base = base;
+    s->irq = irq;
+
+    s->serial = serial_mm_init(sysmem, base, 2, irq, 399193, chr,
+                               DEVICE_LITTLE_ENDIAN);
+
+    memory_region_add_subregion(sysmem, base + 0x20, &s->iomem);
+
+    return s;
+}
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Bin Meng <bin.meng@windriver.com>
 L: qemu-riscv@nongnu.org
 S: Supported
 F: hw/riscv/microchip_pfsoc.c
+F: hw/char/mchp_pfsoc_mmuart.c
 F: include/hw/riscv/microchip_pfsoc.h
+F: include/hw/char/mchp_pfsoc_mmuart.h
 
 RX Machines
 -----------
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -XXX,XX +XXX,XX @@ config RENESAS_SCI
 
 config AVR_USART
     bool
+
+config MCHP_PFSOC_MMUART
+    bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
 softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
 softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
 
 specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
 specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
wires 4 of them out. Let's connect all 5 MMUARTs.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++
 hw/riscv/microchip_pfsoc.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig                   |  1 +
 3 files changed, 51 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 #ifndef HW_MICROCHIP_PFSOC_H
 #define HW_MICROCHIP_PFSOC_H
 
+#include "hw/char/mchp_pfsoc_mmuart.h"
+
 typedef struct MicrochipPFSoCState {
     /*< private >*/
     DeviceState parent_obj;
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     RISCVHartArrayState e_cpus;
     RISCVHartArrayState u_cpus;
     DeviceState *plic;
+    MchpPfSoCMMUartState *serial0;
+    MchpPfSoCMMUartState *serial1;
+    MchpPfSoCMMUartState *serial2;
+    MchpPfSoCMMUartState *serial3;
+    MchpPfSoCMMUartState *serial4;
 } MicrochipPFSoCState;
 
 #define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_L2CC,
     MICROCHIP_PFSOC_L2LIM,
     MICROCHIP_PFSOC_PLIC,
+    MICROCHIP_PFSOC_MMUART0,
     MICROCHIP_PFSOC_SYSREG,
     MICROCHIP_PFSOC_MPUCFG,
+    MICROCHIP_PFSOC_MMUART1,
+    MICROCHIP_PFSOC_MMUART2,
+    MICROCHIP_PFSOC_MMUART3,
+    MICROCHIP_PFSOC_MMUART4,
     MICROCHIP_PFSOC_ENVM_CFG,
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_IOSCB_CFG,
     MICROCHIP_PFSOC_DRAM,
 };
 
+enum {
+    MICROCHIP_PFSOC_MMUART0_IRQ = 90,
+    MICROCHIP_PFSOC_MMUART1_IRQ = 91,
+    MICROCHIP_PFSOC_MMUART2_IRQ = 92,
+    MICROCHIP_PFSOC_MMUART3_IRQ = 93,
+    MICROCHIP_PFSOC_MMUART4_IRQ = 94,
+};
+
 #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT    1
 #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT       4
 
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  * 0) CLINT (Core Level Interruptor)
  * 1) PLIC (Platform Level Interrupt Controller)
  * 2) eNVM (Embedded Non-Volatile Memory)
+ * 3) MMUARTs (Multi-Mode UART)
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@
 #include "hw/irq.h"
 #include "hw/loader.h"
 #include "hw/sysbus.h"
+#include "chardev/char.h"
 #include "hw/cpu/cluster.h"
 #include "target/riscv/cpu.h"
 #include "hw/misc/unimp.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/microchip_pfsoc.h"
+#include "sysemu/sysemu.h"
 
 /*
  * The BIOS image used by this machine is called Hart Software Services (HSS).
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
     [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
     [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
+    [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
     [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
     [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
+    [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
+    [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
+    [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
+    [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
     [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         memmap[MICROCHIP_PFSOC_MPUCFG].base,
         memmap[MICROCHIP_PFSOC_MPUCFG].size);
 
+    /* MMUARTs */
+    s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
+        memmap[MICROCHIP_PFSOC_MMUART0].base,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
+        serial_hd(0));
+    s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
+        memmap[MICROCHIP_PFSOC_MMUART1].base,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
+        serial_hd(1));
+    s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
+        memmap[MICROCHIP_PFSOC_MMUART2].base,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
+        serial_hd(2));
+    s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
+        memmap[MICROCHIP_PFSOC_MMUART3].base,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
+        serial_hd(3));
+    s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
+        memmap[MICROCHIP_PFSOC_MMUART4].base,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
+        serial_hd(4));
+
     /* eNVM */
     memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
                            memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select HART
     select SIFIVE
     select UNIMP
+    select MCHP_PFSOC_MMUART
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible
controller. The SDHCI compatible registers start from offset 0x200,
which are called Slot Register Set (SRS) in its datasheet.

This creates a Cadence SDHCI model built on top of the existing
generic SDHCI model. Cadence specific Host Register Set (HRS) is
implemented to make guest software happy.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/sd/cadence_sdhci.h |  47 +++++++++
 hw/sd/cadence_sdhci.c         | 193 ++++++++++++++++++++++++++++++++++
 hw/sd/Kconfig                 |   4 +
 hw/sd/meson.build             |   1 +
 4 files changed, 245 insertions(+)
 create mode 100644 include/hw/sd/cadence_sdhci.h
 create mode 100644 hw/sd/cadence_sdhci.c

diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/sd/cadence_sdhci.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Cadence SDHCI emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef CADENCE_SDHCI_H
+#define CADENCE_SDHCI_H
+
+#include "hw/sd/sdhci.h"
+
+#define CADENCE_SDHCI_REG_SIZE  0x100
+#define CADENCE_SDHCI_NUM_REGS  (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t))
+
+typedef struct CadenceSDHCIState {
+    SysBusDevice parent;
+
+    MemoryRegion container;
+    MemoryRegion iomem;
+    BusState *bus;
+
+    uint32_t regs[CADENCE_SDHCI_NUM_REGS];
+
+    SDHCIState sdhci;
+} CadenceSDHCIState;
+
+#define TYPE_CADENCE_SDHCI  "cadence.sdhci"
+#define CADENCE_SDHCI(obj)  OBJECT_CHECK(CadenceSDHCIState, (obj), \
+                                         TYPE_CADENCE_SDHCI)
+
+#endif /* CADENCE_SDHCI_H */
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/sd/cadence_sdhci.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * Cadence SDHCI emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/error-report.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "migration/vmstate.h"
+#include "hw/irq.h"
+#include "hw/sd/cadence_sdhci.h"
+#include "sdhci-internal.h"
+
+/* HRS - Host Register Set (specific to Cadence) */
+
+#define CADENCE_SDHCI_HRS00             0x00    /* general information */
+#define CADENCE_SDHCI_HRS00_SWR             BIT(0)
+#define CADENCE_SDHCI_HRS00_POR_VAL         0x00010000
+
+#define CADENCE_SDHCI_HRS04             0x10    /* PHY access port */
+#define CADENCE_SDHCI_HRS04_WR              BIT(24)
+#define CADENCE_SDHCI_HRS04_RD              BIT(25)
+#define CADENCE_SDHCI_HRS04_ACK             BIT(26)
+
+#define CADENCE_SDHCI_HRS06             0x18    /* eMMC control */
+#define CADENCE_SDHCI_HRS06_TUNE_UP         BIT(15)
+
+/* SRS - Slot Register Set (SDHCI-compatible) */
+
+#define CADENCE_SDHCI_SRS_BASE          0x200
+
+#define TO_REG(addr)    ((addr) / sizeof(uint32_t))
+
+static void cadence_sdhci_instance_init(Object *obj)
+{
+    CadenceSDHCIState *s = CADENCE_SDHCI(obj);
+
+    object_initialize_child(OBJECT(s), "generic-sdhci",
+                            &s->sdhci, TYPE_SYSBUS_SDHCI);
+}
+
+static void cadence_sdhci_reset(DeviceState *dev)
+{
+    CadenceSDHCIState *s = CADENCE_SDHCI(dev);
+
+    memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE);
+    s->regs[TO_REG(CADENCE_SDHCI_HRS00)] = CADENCE_SDHCI_HRS00_POR_VAL;
+
+    device_cold_reset(DEVICE(&s->sdhci));
+}
+
+static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    CadenceSDHCIState *s = opaque;
+    uint32_t val;
+
+    val = s->regs[TO_REG(addr)];
+
+    return (uint64_t)val;
+}
+
+static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val,
+                                unsigned int size)
+{
+    CadenceSDHCIState *s = opaque;
+    uint32_t val32 = (uint32_t)val;
+
+    switch (addr) {
+    case CADENCE_SDHCI_HRS00:
+        /*
+         * The only writable bit is SWR (software reset) and it automatically
+         * clears to zero, so essentially this register remains unchanged.
+         */
+        if (val32 & CADENCE_SDHCI_HRS00_SWR) {
+            cadence_sdhci_reset(DEVICE(s));
+        }
+
+        break;
+    case CADENCE_SDHCI_HRS04:
+        /*
+         * Only emulate the ACK bit behavior when read or write transaction
+         * are requested.
+         */
+        if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) {
+            val32 |= CADENCE_SDHCI_HRS04_ACK;
+        } else {
+            val32 &= ~CADENCE_SDHCI_HRS04_ACK;
+        }
+
+        s->regs[TO_REG(addr)] = val32;
+        break;
+    case CADENCE_SDHCI_HRS06:
+        if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) {
+            val32 &= ~CADENCE_SDHCI_HRS06_TUNE_UP;
+        }
+
+        s->regs[TO_REG(addr)] = val32;
+        break;
+    default:
+        s->regs[TO_REG(addr)] = val32;
+        break;
+    }
+}
+
+static const MemoryRegionOps cadence_sdhci_ops = {
+    .read = cadence_sdhci_read,
+    .write = cadence_sdhci_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    }
+};
+
+static void cadence_sdhci_realize(DeviceState *dev, Error **errp)
+{
+    CadenceSDHCIState *s = CADENCE_SDHCI(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+    SysBusDevice *sbd_sdhci = SYS_BUS_DEVICE(&s->sdhci);
+
+    memory_region_init(&s->container, OBJECT(s),
+                       "cadence.sdhci-container", 0x1000);
+    sysbus_init_mmio(sbd, &s->container);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops,
+                          s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE);
+    memory_region_add_subregion(&s->container, 0, &s->iomem);
+
+    sysbus_realize(sbd_sdhci, errp);
+    memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE,
+                                sysbus_mmio_get_region(sbd_sdhci, 0));
+
+    /* propagate irq and "sd-bus" from generic-sdhci */
+    sysbus_pass_irq(sbd, sbd_sdhci);
+    s->bus = qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus");
+}
+
+static const VMStateDescription vmstate_cadence_sdhci = {
+    .name = TYPE_CADENCE_SDHCI,
+    .version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_REGS),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static void cadence_sdhci_class_init(ObjectClass *classp, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(classp);
+
+    dc->desc = "Cadence SD/SDIO/eMMC Host Controller (SD4HC)";
+    dc->realize = cadence_sdhci_realize;
+    dc->reset = cadence_sdhci_reset;
+    dc->vmsd = &vmstate_cadence_sdhci;
+}
+
+static TypeInfo cadence_sdhci_info = {
+    .name          = TYPE_CADENCE_SDHCI,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(CadenceSDHCIState),
+    .instance_init = cadence_sdhci_instance_init,
+    .class_init    = cadence_sdhci_class_init,
+};
+
+static void cadence_sdhci_register_types(void)
+{
+    type_register_static(&cadence_sdhci_info);
+}
+
+type_init(cadence_sdhci_register_types)
diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/Kconfig
+++ b/hw/sd/Kconfig
@@ -XXX,XX +XXX,XX @@ config SDHCI_PCI
     default y if PCI_DEVICES
     depends on PCI
     select SDHCI
+
+config CADENCE_SDHCI
+    bool
+    select SDHCI
diff --git a/hw/sd/meson.build b/hw/sd/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/meson.build
+++ b/hw/sd/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_mmci.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c'))
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))
 softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))
+softmmu_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC integrates one Cadence SDHCI controller.
On the Icicle Kit board, one eMMC chip and an external SD card
connect to this controller depending on different configuration.

As QEMU does not support eMMC yet, we just emulate the SD card
configuration. To test this, the Hart Software Services (HSS)
should choose the SD card configuration:

$ cp boards/icicle-kit-es/def_config.sdcard .config
$ make BOARD=icicle-kit-es

The SD card image can be built from the Yocto BSP at:
https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp

Note the generated SD card image should be resized before use:
$ qemu-img resize /path/to/sdcard.img 4G

Launch QEMU with the following command:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |  4 ++++
 hw/riscv/microchip_pfsoc.c         | 23 +++++++++++++++++++++++
 hw/riscv/Kconfig                   |  1 +
 3 files changed, 28 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 #define HW_MICROCHIP_PFSOC_H
 
 #include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/sd/cadence_sdhci.h"
 
 typedef struct MicrochipPFSoCState {
     /*< private >*/
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     MchpPfSoCMMUartState *serial2;
     MchpPfSoCMMUartState *serial3;
     MchpPfSoCMMUartState *serial4;
+    CadenceSDHCIState sdhci;
 } MicrochipPFSoCState;
 
 #define TYPE_MICROCHIP_PFSOC    "microchip.pfsoc"
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_MMUART0,
     MICROCHIP_PFSOC_SYSREG,
     MICROCHIP_PFSOC_MPUCFG,
+    MICROCHIP_PFSOC_EMMC_SD,
     MICROCHIP_PFSOC_MMUART1,
     MICROCHIP_PFSOC_MMUART2,
     MICROCHIP_PFSOC_MMUART3,
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 enum {
+    MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
     MICROCHIP_PFSOC_MMUART0_IRQ = 90,
     MICROCHIP_PFSOC_MMUART1_IRQ = 91,
     MICROCHIP_PFSOC_MMUART2_IRQ = 92,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  * 1) PLIC (Platform Level Interrupt Controller)
  * 2) eNVM (Embedded Non-Volatile Memory)
  * 3) MMUARTs (Multi-Mode UART)
+ * 4) Cadence eMMC/SDHC controller and an SD card connected to it
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
     [MICROCHIP_PFSOC_SYSREG] =          { 0x20002000,     0x2000 },
     [MICROCHIP_PFSOC_MPUCFG] =          { 0x20005000,     0x1000 },
+    [MICROCHIP_PFSOC_EMMC_SD] =         { 0x20008000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART1] =         { 0x20100000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
     qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
                          TYPE_RISCV_CPU_SIFIVE_U54);
     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
+
+    object_initialize_child(obj, "sd-controller", &s->sdhci,
+                            TYPE_CADENCE_SDHCI);
 }
 
 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         memmap[MICROCHIP_PFSOC_MPUCFG].base,
         memmap[MICROCHIP_PFSOC_MPUCFG].size);
 
+    /* SDHCI */
+    sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
+                    memmap[MICROCHIP_PFSOC_EMMC_SD].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
+
     /* MMUARTs */
     s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
         memmap[MICROCHIP_PFSOC_MMUART0].base,
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+    DriveInfo *dinfo = drive_get_next(IF_SD);
 
     /* Sanity check on RAM size */
     if (machine->ram_size < mc->default_ram_size) {
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
 
     /* Load the firmware */
     riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
+
+    /* Attach an SD card */
+    if (dinfo) {
+        CadenceSDHCIState *sdhci = &(s->soc.sdhci);
+        DeviceState *card = qdev_new(TYPE_SD_CARD);
+
+        qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
+                                &error_fatal);
+        qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
+    }
 }
 
 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select SIFIVE
     select UNIMP
     select MCHP_PFSOC_MMUART
+    select CADENCE_SDHCI
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC integrates a DMA engine that supports:
* Independent concurrent DMA transfers using 4 DMA channels
* Generation of interrupts on various conditions during execution
which is actually an IP reused from the SiFive FU540 chip.

This creates a model to support both polling and interrupt modes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/dma/sifive_pdma.h |  57 +++++++
 hw/dma/sifive_pdma.c         | 313 +++++++++++++++++++++++++++++++++++
 hw/dma/Kconfig               |   3 +
 hw/dma/meson.build           |   1 +
 4 files changed, 374 insertions(+)
 create mode 100644 include/hw/dma/sifive_pdma.h
 create mode 100644 hw/dma/sifive_pdma.c

diff --git a/include/hw/dma/sifive_pdma.h b/include/hw/dma/sifive_pdma.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/dma/sifive_pdma.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * SiFive Platform DMA emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SIFIVE_PDMA_H
+#define SIFIVE_PDMA_H
+
+struct sifive_pdma_chan {
+    uint32_t control;
+    uint32_t next_config;
+    uint64_t next_bytes;
+    uint64_t next_dst;
+    uint64_t next_src;
+    uint32_t exec_config;
+    uint64_t exec_bytes;
+    uint64_t exec_dst;
+    uint64_t exec_src;
+    int state;
+};
+
+#define SIFIVE_PDMA_CHANS           4
+#define SIFIVE_PDMA_IRQS            (SIFIVE_PDMA_CHANS * 2)
+#define SIFIVE_PDMA_REG_SIZE        0x100000
+#define SIFIVE_PDMA_CHAN_NO(reg)    ((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >> 12)
+
+typedef struct SiFivePDMAState {
+    SysBusDevice parent;
+    MemoryRegion iomem;
+    qemu_irq irq[SIFIVE_PDMA_IRQS];
+
+    struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS];
+} SiFivePDMAState;
+
+#define TYPE_SIFIVE_PDMA    "sifive.pdma"
+
+#define SIFIVE_PDMA(obj)    \
+    OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA)
+
+#endif /* SIFIVE_PDMA_H */
diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/dma/sifive_pdma.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * SiFive Platform DMA emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ *   Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "sysemu/dma.h"
+#include "hw/dma/sifive_pdma.h"
+
+#define DMA_CONTROL         0x000
+#define   CONTROL_CLAIM     BIT(0)
+#define   CONTROL_RUN       BIT(1)
+#define   CONTROL_DONE_IE   BIT(14)
+#define   CONTROL_ERR_IE    BIT(15)
+#define   CONTROL_DONE      BIT(30)
+#define   CONTROL_ERR       BIT(31)
+
+#define DMA_NEXT_CONFIG     0x004
+#define   CONFIG_REPEAT     BIT(2)
+#define   CONFIG_ORDER      BIT(3)
+#define   CONFIG_WRSZ_SHIFT 24
+#define   CONFIG_RDSZ_SHIFT 28
+#define   CONFIG_SZ_MASK    0xf
+
+#define DMA_NEXT_BYTES      0x008
+#define DMA_NEXT_DST        0x010
+#define DMA_NEXT_SRC        0x018
+#define DMA_EXEC_CONFIG     0x104
+#define DMA_EXEC_BYTES      0x108
+#define DMA_EXEC_DST        0x110
+#define DMA_EXEC_SRC        0x118
+
+enum dma_chan_state {
+    DMA_CHAN_STATE_IDLE,
+    DMA_CHAN_STATE_STARTED,
+    DMA_CHAN_STATE_ERROR,
+    DMA_CHAN_STATE_DONE
+};
+
+static void sifive_pdma_run(SiFivePDMAState *s, int ch)
+{
+    uint64_t bytes = s->chan[ch].next_bytes;
+    uint64_t dst = s->chan[ch].next_dst;
+    uint64_t src = s->chan[ch].next_src;
+    uint32_t config = s->chan[ch].next_config;
+    int wsize, rsize, size;
+    uint8_t buf[64];
+    int n;
+
+    /* do nothing if bytes to transfer is zero */
+    if (!bytes) {
+        goto error;
+    }
+
+    /*
+     * The manual does not describe how the hardware behaviors when
+     * config.wsize and config.rsize are given different values.
+     * A common case is memory to memory DMA, and in this case they
+     * are normally the same. Abort if this expectation fails.
+     */
+    wsize = (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK;
+    rsize = (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK;
+    if (wsize != rsize) {
+        goto error;
+    }
+
+    /*
+     * Calculate the transaction size
+     *
+     * size field is base 2 logarithm of DMA transaction size,
+     * but there is an upper limit of 64 bytes per transaction.
+     */
+    size = wsize;
+    if (size > 6) {
+        size = 6;
+    }
+    size = 1 << size;
+
+    /* the bytes to transfer should be multiple of transaction size */
+    if (bytes % size) {
+        goto error;
+    }
+
+    /* indicate a DMA transfer is started */
+    s->chan[ch].state = DMA_CHAN_STATE_STARTED;
+    s->chan[ch].control &= ~CONTROL_DONE;
+    s->chan[ch].control &= ~CONTROL_ERR;
+
+    /* load the next_ registers into their exec_ counterparts */
+    s->chan[ch].exec_config = config;
+    s->chan[ch].exec_bytes = bytes;
+    s->chan[ch].exec_dst = dst;
+    s->chan[ch].exec_src = src;
+
+    for (n = 0; n < bytes / size; n++) {
+        cpu_physical_memory_read(s->chan[ch].exec_src, buf, size);
+        cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size);
+        s->chan[ch].exec_src += size;
+        s->chan[ch].exec_dst += size;
+        s->chan[ch].exec_bytes -= size;
+    }
+
+    /* indicate a DMA transfer is done */
+    s->chan[ch].state = DMA_CHAN_STATE_DONE;
+    s->chan[ch].control &= ~CONTROL_RUN;
+    s->chan[ch].control |= CONTROL_DONE;
+
+    /* reload exec_ registers if repeat is required */
+    if (s->chan[ch].next_config & CONFIG_REPEAT) {
+        s->chan[ch].exec_bytes = bytes;
+        s->chan[ch].exec_dst = dst;
+        s->chan[ch].exec_src = src;
+    }
+
+    return;
+
+error:
+    s->chan[ch].state = DMA_CHAN_STATE_ERROR;
+    s->chan[ch].control |= CONTROL_ERR;
+    return;
+}
+
+static inline void sifive_pdma_update_irq(SiFivePDMAState *s, int ch)
+{
+    bool done_ie, err_ie;
+
+    done_ie = !!(s->chan[ch].control & CONTROL_DONE_IE);
+    err_ie = !!(s->chan[ch].control & CONTROL_ERR_IE);
+
+    if (done_ie && (s->chan[ch].control & CONTROL_DONE)) {
+        qemu_irq_raise(s->irq[ch * 2]);
+    } else {
+        qemu_irq_lower(s->irq[ch * 2]);
+    }
+
+    if (err_ie && (s->chan[ch].control & CONTROL_ERR)) {
+        qemu_irq_raise(s->irq[ch * 2 + 1]);
+    } else {
+        qemu_irq_lower(s->irq[ch * 2 + 1]);
+    }
+
+    s->chan[ch].state = DMA_CHAN_STATE_IDLE;
+}
+
+static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned size)
+{
+    SiFivePDMAState *s = opaque;
+    int ch = SIFIVE_PDMA_CHAN_NO(offset);
+    uint64_t val = 0;
+
+    if (ch >= SIFIVE_PDMA_CHANS) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
+                      __func__, ch);
+        return 0;
+    }
+
+    offset &= 0xfff;
+    switch (offset) {
+    case DMA_CONTROL:
+        val = s->chan[ch].control;
+        break;
+    case DMA_NEXT_CONFIG:
+        val = s->chan[ch].next_config;
+        break;
+    case DMA_NEXT_BYTES:
+        val = s->chan[ch].next_bytes;
+        break;
+    case DMA_NEXT_DST:
+        val = s->chan[ch].next_dst;
+        break;
+    case DMA_NEXT_SRC:
+        val = s->chan[ch].next_src;
+        break;
+    case DMA_EXEC_CONFIG:
+        val = s->chan[ch].exec_config;
+        break;
+    case DMA_EXEC_BYTES:
+        val = s->chan[ch].exec_bytes;
+        break;
+    case DMA_EXEC_DST:
+        val = s->chan[ch].exec_dst;
+        break;
+    case DMA_EXEC_SRC:
+        val = s->chan[ch].exec_src;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+                      __func__, offset);
+        break;
+    }
+
+    return val;
+}
+
+static void sifive_pdma_write(void *opaque, hwaddr offset,
+                              uint64_t value, unsigned size)
+{
+    SiFivePDMAState *s = opaque;
+    int ch = SIFIVE_PDMA_CHAN_NO(offset);
+
+    if (ch >= SIFIVE_PDMA_CHANS) {
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n",
+                      __func__, ch);
+        return;
+    }
+
+    offset &= 0xfff;
+    switch (offset) {
+    case DMA_CONTROL:
+        s->chan[ch].control = value;
+
+        if (value & CONTROL_RUN) {
+            sifive_pdma_run(s, ch);
+        }
+
+        sifive_pdma_update_irq(s, ch);
+        break;
+    case DMA_NEXT_CONFIG:
+        s->chan[ch].next_config = value;
+        break;
+    case DMA_NEXT_BYTES:
+        s->chan[ch].next_bytes = value;
+        break;
+    case DMA_NEXT_DST:
+        s->chan[ch].next_dst = value;
+        break;
+    case DMA_NEXT_SRC:
+        s->chan[ch].next_src = value;
+        break;
+    case DMA_EXEC_CONFIG:
+    case DMA_EXEC_BYTES:
+    case DMA_EXEC_DST:
+    case DMA_EXEC_SRC:
+        /* these are read-only registers */
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+                      __func__, offset);
+        break;
+    }
+}
+
+static const MemoryRegionOps sifive_pdma_ops = {
+    .read = sifive_pdma_read,
+    .write = sifive_pdma_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    /* there are 32-bit and 64-bit wide registers */
+    .impl = {
+        .min_access_size = 4,
+        .max_access_size = 8,
+    }
+};
+
+static void sifive_pdma_realize(DeviceState *dev, Error **errp)
+{
+    SiFivePDMAState *s = SIFIVE_PDMA(dev);
+    int i;
+
+    memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s,
+                          TYPE_SIFIVE_PDMA, SIFIVE_PDMA_REG_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
+
+    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+        sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
+    }
+}
+
+static void sifive_pdma_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->desc = "SiFive Platform DMA controller";
+    dc->realize = sifive_pdma_realize;
+}
+
+static const TypeInfo sifive_pdma_info = {
+    .name          = TYPE_SIFIVE_PDMA,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(SiFivePDMAState),
+    .class_init    = sifive_pdma_class_init,
+};
+
+static void sifive_pdma_register_types(void)
+{
+    type_register_static(&sifive_pdma_info);
+}
+
+type_init(sifive_pdma_register_types)
diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/Kconfig
+++ b/hw/dma/Kconfig
@@ -XXX,XX +XXX,XX @@ config ZYNQ_DEVCFG
 
 config STP2000
     bool
+
+config SIFIVE_PDMA
+    bool
diff --git a/hw/dma/meson.build b/hw/dma/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/dma/meson.build
+++ b/hw/dma/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zdma.c'))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.c'))
 softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
controller to move the 2nd stage bootloader in the system memory.
Let's connect a DMA controller to Microchip PolarFire SoC.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h | 11 +++++++++++
 hw/riscv/microchip_pfsoc.c         | 15 +++++++++++++++
 hw/riscv/Kconfig                   |  1 +
 3 files changed, 27 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 #define HW_MICROCHIP_PFSOC_H
 
 #include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/dma/sifive_pdma.h"
 #include "hw/sd/cadence_sdhci.h"
 
 typedef struct MicrochipPFSoCState {
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     MchpPfSoCMMUartState *serial2;
     MchpPfSoCMMUartState *serial3;
     MchpPfSoCMMUartState *serial4;
+    SiFivePDMAState dma;
     CadenceSDHCIState sdhci;
 } MicrochipPFSoCState;
 
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_BUSERR_UNIT4,
     MICROCHIP_PFSOC_CLINT,
     MICROCHIP_PFSOC_L2CC,
+    MICROCHIP_PFSOC_DMA,
     MICROCHIP_PFSOC_L2LIM,
     MICROCHIP_PFSOC_PLIC,
     MICROCHIP_PFSOC_MMUART0,
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 enum {
+    MICROCHIP_PFSOC_DMA_IRQ0 = 5,
+    MICROCHIP_PFSOC_DMA_IRQ1 = 6,
+    MICROCHIP_PFSOC_DMA_IRQ2 = 7,
+    MICROCHIP_PFSOC_DMA_IRQ3 = 8,
+    MICROCHIP_PFSOC_DMA_IRQ4 = 9,
+    MICROCHIP_PFSOC_DMA_IRQ5 = 10,
+    MICROCHIP_PFSOC_DMA_IRQ6 = 11,
+    MICROCHIP_PFSOC_DMA_IRQ7 = 12,
     MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
     MICROCHIP_PFSOC_MMUART0_IRQ = 90,
     MICROCHIP_PFSOC_MMUART1_IRQ = 91,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  * 2) eNVM (Embedded Non-Volatile Memory)
  * 3) MMUARTs (Multi-Mode UART)
  * 4) Cadence eMMC/SDHC controller and an SD card connected to it
+ * 5) SiFive Platform DMA (Direct Memory Access Controller)
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_BUSERR_UNIT4] =    {  0x1704000,     0x1000 },
     [MICROCHIP_PFSOC_CLINT] =           {  0x2000000,    0x10000 },
     [MICROCHIP_PFSOC_L2CC] =            {  0x2010000,     0x1000 },
+    [MICROCHIP_PFSOC_DMA] =             {  0x3000000,   0x100000 },
     [MICROCHIP_PFSOC_L2LIM] =           {  0x8000000,  0x2000000 },
     [MICROCHIP_PFSOC_PLIC] =            {  0xc000000,  0x4000000 },
     [MICROCHIP_PFSOC_MMUART0] =         { 0x20000000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
                          TYPE_RISCV_CPU_SIFIVE_U54);
     qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
 
+    object_initialize_child(obj, "dma-controller", &s->dma,
+                            TYPE_SIFIVE_PDMA);
+
     object_initialize_child(obj, "sd-controller", &s->sdhci,
                             TYPE_CADENCE_SDHCI);
 }
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         memmap[MICROCHIP_PFSOC_PLIC].size);
     g_free(plic_hart_config);
 
+    /* DMA */
+    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
+                    memmap[MICROCHIP_PFSOC_DMA].base);
+    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+                           qdev_get_gpio_in(DEVICE(s->plic),
+                                            MICROCHIP_PFSOC_DMA_IRQ0 + i));
+    }
+
     /* SYSREG */
     create_unimplemented_device("microchip.pfsoc.sysreg",
         memmap[MICROCHIP_PFSOC_SYSREG].base,
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select SIFIVE
     select UNIMP
     select MCHP_PFSOC_MMUART
+    select SIFIVE_PDMA
     select CADENCE_SDHCI
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

At present the PHY address of the PHY connected to GEM is hard-coded
to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
all boards. Add a new 'phy-addr' property so that board can specify
the PHY address for each GEM instance.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/net/cadence_gem.h | 2 ++
 hw/net/cadence_gem.c         | 5 +++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -XXX,XX +XXX,XX @@ typedef struct CadenceGEMState {
     /* Mask of register bits which are write 1 to clear */
     uint32_t regs_w1c[CADENCE_GEM_MAXREG];
 
+    /* PHY address */
+    uint8_t phy_addr;
     /* PHY registers backing store */
     uint16_t phy_regs[32];
 
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
             uint32_t phy_addr, reg_num;
 
             phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
-            if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+            if (phy_addr == s->phy_addr || phy_addr == 0) {
                 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                 retval &= 0xFFFF0000;
                 retval |= gem_phy_read(s, reg_num);
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
             uint32_t phy_addr, reg_num;
 
             phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
-            if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+            if (phy_addr == s->phy_addr || phy_addr == 0) {
                 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                 gem_phy_write(s, reg_num, val);
             }
@@ -XXX,XX +XXX,XX @@ static Property gem_properties[] = {
     DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
     DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
                        GEM_MODID_VALUE),
+    DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
     DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
                       num_priority_queues, 1),
     DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

When cadence_gem model was created for Xilinx boards, the PHY address
was hard-coded to 23 in the GEM model. Now that we have introduced a
property we can use that to tell GEM model what our PHY address is.
Change all boards' GEM 'phy-addr' property value to 23, and set the
PHY address default value to 0 in the GEM model.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/arm/xilinx_zynq.c | 1 +
 hw/arm/xlnx-versal.c | 1 +
 hw/arm/xlnx-zynqmp.c | 2 ++
 hw/net/cadence_gem.c | 6 +++---
 4 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
         qdev_set_nic_properties(dev, nd);
     }
+    object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
     s = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(s, &error_fatal);
     sysbus_mmio_map(s, 0, base);
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
             qemu_check_nic_model(nd, "cadence_gem");
             qdev_set_nic_properties(dev, nd);
         }
+        object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort);
         object_property_set_int(OBJECT(dev), "num-priority-queues", 2,
                                 &error_abort);
         object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps),
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
         }
         object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION,
                                 &error_abort);
+        object_property_set_int(OBJECT(&s->gem[i]), "phy-addr", 23,
+                                &error_abort);
         object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2,
                                 &error_abort);
         if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) {
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@
 #define GEM_PHYMNTNC_REG_SHIFT 18
 
 /* Marvell PHY definitions */
-#define BOARD_PHY_ADDRESS    23 /* PHY address we will emulate a device at */
+#define BOARD_PHY_ADDRESS    0 /* PHY address we will emulate a device at */
 
 #define PHY_REG_CONTROL      0
 #define PHY_REG_STATUS       1
@@ -XXX,XX +XXX,XX @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
             uint32_t phy_addr, reg_num;
 
             phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
-            if (phy_addr == s->phy_addr || phy_addr == 0) {
+            if (phy_addr == s->phy_addr) {
                 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                 retval &= 0xFFFF0000;
                 retval |= gem_phy_read(s, reg_num);
@@ -XXX,XX +XXX,XX @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
             uint32_t phy_addr, reg_num;
 
             phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
-            if (phy_addr == s->phy_addr || phy_addr == 0) {
+            if (phy_addr == s->phy_addr) {
                 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
                 gem_phy_write(s, reg_num, val);
             }
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC integrates 2 Candence GEMs to provide
IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface.

On the Icicle Kit board, GEM0 connects to a PHY at address 8 while
GEM1 connects to a PHY at address 9.

The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we
must specify 2 '-nic' options from the command line in order to get
a working ethernet.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-14-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |  7 ++++++
 hw/riscv/microchip_pfsoc.c         | 39 ++++++++++++++++++++++++++++++
 2 files changed, 46 insertions(+)

diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/char/mchp_pfsoc_mmuart.h"
 #include "hw/dma/sifive_pdma.h"
+#include "hw/net/cadence_gem.h"
 #include "hw/sd/cadence_sdhci.h"
 
 typedef struct MicrochipPFSoCState {
@@ -XXX,XX +XXX,XX @@ typedef struct MicrochipPFSoCState {
     MchpPfSoCMMUartState *serial3;
     MchpPfSoCMMUartState *serial4;
     SiFivePDMAState dma;
+    CadenceGEMState gem0;
+    CadenceGEMState gem1;
     CadenceSDHCIState sdhci;
 } MicrochipPFSoCState;
 
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_MMUART2,
     MICROCHIP_PFSOC_MMUART3,
     MICROCHIP_PFSOC_MMUART4,
+    MICROCHIP_PFSOC_GEM0,
+    MICROCHIP_PFSOC_GEM1,
     MICROCHIP_PFSOC_ENVM_CFG,
     MICROCHIP_PFSOC_ENVM_DATA,
     MICROCHIP_PFSOC_IOSCB_CFG,
@@ -XXX,XX +XXX,XX @@ enum {
     MICROCHIP_PFSOC_DMA_IRQ5 = 10,
     MICROCHIP_PFSOC_DMA_IRQ6 = 11,
     MICROCHIP_PFSOC_DMA_IRQ7 = 12,
+    MICROCHIP_PFSOC_GEM0_IRQ = 64,
+    MICROCHIP_PFSOC_GEM1_IRQ = 70,
     MICROCHIP_PFSOC_EMMC_SD_IRQ = 88,
     MICROCHIP_PFSOC_MMUART0_IRQ = 90,
     MICROCHIP_PFSOC_MMUART1_IRQ = 91,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
  * 3) MMUARTs (Multi-Mode UART)
  * 4) Cadence eMMC/SDHC controller and an SD card connected to it
  * 5) SiFive Platform DMA (Direct Memory Access Controller)
+ * 6) GEM (Gigabit Ethernet MAC Controller)
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@
 #define BIOS_FILENAME   "hss.bin"
 #define RESET_VECTOR    0x20220000
 
+/* GEM version */
+#define GEM_REVISION    0x0107010c
+
 static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [MICROCHIP_PFSOC_MMUART2] =         { 0x20102000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART3] =         { 0x20104000,     0x1000 },
     [MICROCHIP_PFSOC_MMUART4] =         { 0x20106000,     0x1000 },
+    [MICROCHIP_PFSOC_GEM0] =            { 0x20110000,     0x2000 },
+    [MICROCHIP_PFSOC_GEM1] =            { 0x20112000,     0x2000 },
     [MICROCHIP_PFSOC_ENVM_CFG] =        { 0x20200000,     0x1000 },
     [MICROCHIP_PFSOC_ENVM_DATA] =       { 0x20220000,    0x20000 },
     [MICROCHIP_PFSOC_IOSCB_CFG] =       { 0x37080000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
     object_initialize_child(obj, "dma-controller", &s->dma,
                             TYPE_SIFIVE_PDMA);
 
+    object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
+    object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
+
     object_initialize_child(obj, "sd-controller", &s->sdhci,
                             TYPE_CADENCE_SDHCI);
 }
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     MemoryRegion *envm_data = g_new(MemoryRegion, 1);
     char *plic_hart_config;
     size_t plic_hart_config_len;
+    NICInfo *nd;
     int i;
 
     sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
         qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
         serial_hd(4));
 
+    /* GEMs */
+
+    nd = &nd_table[0];
+    if (nd->used) {
+        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+        qdev_set_nic_properties(DEVICE(&s->gem0), nd);
+    }
+    nd = &nd_table[1];
+    if (nd->used) {
+        qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
+        qdev_set_nic_properties(DEVICE(&s->gem1), nd);
+    }
+
+    object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
+    object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
+    sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
+                    memmap[MICROCHIP_PFSOC_GEM0].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
+
+    object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
+    object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
+    sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
+                    memmap[MICROCHIP_PFSOC_GEM1].base);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
+        qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
+
     /* eNVM */
     memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
                            memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems
enough to create unimplemented devices to cover their register
spaces at this point.

With this commit, QEMU can boot to U-Boot (2nd stage bootloader)
all the way to the Linux shell login prompt, with a modified HSS
(1st stage bootloader).

For detailed instructions on how to create images for the Icicle
Kit board, please check QEMU RISC-V WiKi page at:
https://wiki.qemu.org/Documentation/Platforms/RISCV

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/microchip_pfsoc.h |  3 +++
 hw/riscv/microchip_pfsoc.c         | 14 ++++++++++++++
 2 files changed, 17 insertions(+)

From: Bin Meng <bin.meng@windriver.com>

At present the CLINT timestamp is using a hard-coded timebase
frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be
true for all boards.

Add a new 'timebase-freq' property to the CLINT device, and
update various functions to accept this as a parameter.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/sifive_clint.h |  4 +++-
 target/riscv/cpu.h              |  6 ++++--
 hw/riscv/microchip_pfsoc.c      |  6 +++++-
 hw/riscv/sifive_clint.c         | 26 +++++++++++++++-----------
 hw/riscv/sifive_e.c             |  3 ++-
 hw/riscv/sifive_u.c             |  3 ++-
 hw/riscv/spike.c                |  3 ++-
 hw/riscv/virt.c                 |  3 ++-
 target/riscv/cpu_helper.c       |  4 +++-
 target/riscv/csr.c              |  4 ++--
 10 files changed, 40 insertions(+), 22 deletions(-)

diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_clint.h
+++ b/include/hw/riscv/sifive_clint.h
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState {
     uint32_t timecmp_base;
     uint32_t time_base;
     uint32_t aperture_size;
+    uint32_t timebase_freq;
 } SiFiveCLINTState;
 
 DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
     uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
-    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
+    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
+    bool provide_rdtime);
 
 enum {
     SIFIVE_SIP_BASE     = 0x0,
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     pmp_table_t pmp_state;
 
     /* machine specific rdtime callback */
-    uint64_t (*rdtime_fn)(void);
+    uint64_t (*rdtime_fn)(uint32_t);
+    uint32_t rdtime_fn_arg;
 
     /* True if in debugger mode.  */
     bool debugger;
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+                             uint32_t arg);
 #endif
 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
 
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
 #define BIOS_FILENAME   "hss.bin"
 #define RESET_VECTOR    0x20220000
 
+/* CLINT timebase frequency */
+#define CLINT_TIMEBASE_FREQ 1000000
+
 /* GEM version */
 #define GEM_REVISION    0x0107010c
 
@@ -XXX,XX +XXX,XX @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
     /* CLINT */
     sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base,
         memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus,
-        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+        CLINT_TIMEBASE_FREQ, false);
 
     /* L2 cache controller */
     create_unimplemented_device("microchip.pfsoc.l2cc",
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/sifive_clint.h"
 #include "qemu/timer.h"
 
-static uint64_t cpu_riscv_read_rtc(void)
+static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
 {
     return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
-        SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND);
+        timebase_freq, NANOSECONDS_PER_SECOND);
 }
 
 /*
  * Called when timecmp is written to update the QEMU timer or immediately
  * trigger timer interrupt if mtimecmp <= current timer value.
  */
-static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
+static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
+                                       uint32_t timebase_freq)
 {
     uint64_t next;
     uint64_t diff;
 
-    uint64_t rtc_r = cpu_riscv_read_rtc();
+    uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq);
 
     cpu->env.timecmp = value;
     if (cpu->env.timecmp <= rtc_r) {
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value)
     diff = cpu->env.timecmp - rtc_r;
     /* back to ns (note args switched in muldiv64) */
     next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
-        muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ);
+        muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
     timer_mod(cpu->env.timer, next);
 }
 
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
         }
     } else if (addr == clint->time_base) {
         /* time_lo */
-        return cpu_riscv_read_rtc() & 0xFFFFFFFF;
+        return cpu_riscv_read_rtc(clint->timebase_freq) & 0xFFFFFFFF;
     } else if (addr == clint->time_base + 4) {
         /* time_hi */
-        return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF;
+        return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0xFFFFFFFF;
     }
 
     error_report("clint: invalid read: %08x", (uint32_t)addr);
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
             /* timecmp_lo */
             uint64_t timecmp_hi = env->timecmp >> 32;
             sifive_clint_write_timecmp(RISCV_CPU(cpu),
-                timecmp_hi << 32 | (value & 0xFFFFFFFF));
+                timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_freq);
             return;
         } else if ((addr & 0x7) == 4) {
             /* timecmp_hi */
             uint64_t timecmp_lo = env->timecmp;
             sifive_clint_write_timecmp(RISCV_CPU(cpu),
-                value << 32 | (timecmp_lo & 0xFFFFFFFF));
+                value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_freq);
         } else {
             error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);
         }
@@ -XXX,XX +XXX,XX @@ static Property sifive_clint_properties[] = {
     DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
     DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0),
     DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0),
+    DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -XXX,XX +XXX,XX @@ type_init(sifive_clint_register_types)
  */
 DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
     uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
-    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
+    uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
+    bool provide_rdtime)
 {
     int i;
     for (i = 0; i < num_harts; i++) {
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
             continue;
         }
         if (provide_rdtime) {
-            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc);
+            riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq);
         }
         env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                   &sifive_clint_timer_cb, cpu);
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
     qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
     qdev_prop_set_uint32(dev, "time-base", time_base);
     qdev_prop_set_uint32(dev, "aperture-size", size);
+    qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq);
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     return dev;
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
         memmap[SIFIVE_E_PLIC].size);
     sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
         memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
-        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+        SIFIVE_CLINT_TIMEBASE_FREQ, false);
     create_unimplemented_device("riscv.sifive.e.aon",
         memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
     sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
         memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
-        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+        SIFIVE_CLINT_TIMEBASE_FREQ, false);
 
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
         return;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
         sifive_clint_create(
             memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
             memmap[SPIKE_CLINT].size, base_hartid, hart_count,
-            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+            SIFIVE_CLINT_TIMEBASE_FREQ, false);
     }
 
     /* register system main memory (actual RAM) */
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         sifive_clint_create(
             memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
             memmap[VIRT_CLINT].size, base_hartid, hart_count,
-            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+            SIFIVE_CLINT_TIMEBASE_FREQ, true);
 
         /* Per-socket PLIC hart topology configuration string */
         plic_hart_config_len =
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
     return old;
 }
 
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+                             uint32_t arg)
 {
     env->rdtime_fn = fn;
+    env->rdtime_fn_arg = arg;
 }
 
 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
         return -RISCV_EXCP_ILLEGAL_INST;
     }
 
-    *val = env->rdtime_fn() + delta;
+    *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
         return -RISCV_EXCP_ILLEGAL_INST;
     }
 
-    *val = (env->rdtime_fn() + delta) >> 32;
+    *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
     return 0;
 }
 #endif
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/sifive_u.h | 11 +++++++++++
 hw/riscv/sifive_u.c         | 30 ++++++++++++++++++++++++++++++
 hw/riscv/Kconfig            |  1 +
 3 files changed, 42 insertions(+)

diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -XXX,XX +XXX,XX @@
 #ifndef HW_SIFIVE_U_H
 #define HW_SIFIVE_U_H
 
+#include "hw/dma/sifive_pdma.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveUSoCState {
     SiFiveUPRCIState prci;
     SIFIVEGPIOState gpio;
     SiFiveUOTPState otp;
+    SiFivePDMAState dma;
     CadenceGEMState gem;
 
     uint32_t serial;
@@ -XXX,XX +XXX,XX @@ enum {
     SIFIVE_U_MROM,
     SIFIVE_U_CLINT,
     SIFIVE_U_L2CC,
+    SIFIVE_U_PDMA,
     SIFIVE_U_L2LIM,
     SIFIVE_U_PLIC,
     SIFIVE_U_PRCI,
@@ -XXX,XX +XXX,XX @@ enum {
     SIFIVE_U_GPIO_IRQ13 = 20,
     SIFIVE_U_GPIO_IRQ14 = 21,
     SIFIVE_U_GPIO_IRQ15 = 22,
+    SIFIVE_U_PDMA_IRQ0 = 23,
+    SIFIVE_U_PDMA_IRQ1 = 24,
+    SIFIVE_U_PDMA_IRQ2 = 25,
+    SIFIVE_U_PDMA_IRQ3 = 26,
+    SIFIVE_U_PDMA_IRQ4 = 27,
+    SIFIVE_U_PDMA_IRQ5 = 28,
+    SIFIVE_U_PDMA_IRQ6 = 29,
+    SIFIVE_U_PDMA_IRQ7 = 30,
     SIFIVE_U_GEM_IRQ = 0x35
 };
 
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
  * 4) GPIO (General Purpose Input/Output Controller)
  * 5) OTP (One-Time Programmable) memory with stored serial number
  * 6) GEM (Gigabit Ethernet Controller) and management block
+ * 7) DMA (Direct Memory Access Controller)
  *
  * This board currently generates devicetree dynamically that indicates at least
  * two harts and up to five harts.
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [SIFIVE_U_MROM] =     {     0x1000,     0xf000 },
     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
     [SIFIVE_U_L2CC] =     {  0x2010000,     0x1000 },
+    [SIFIVE_U_PDMA] =     {  0x3000000,   0x100000 },
     [SIFIVE_U_L2LIM] =    {  0x8000000,  0x2000000 },
     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
     [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
     g_free(nodename);
 
+    nodename = g_strdup_printf("/soc/dma@%lx",
+        (long)memmap[SIFIVE_U_PDMA].base);
+    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
+    qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
+        SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
+        SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
+        SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
+    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+    qemu_fdt_setprop_cells(fdt, nodename, "reg",
+        0x0, memmap[SIFIVE_U_PDMA].base,
+        0x0, memmap[SIFIVE_U_PDMA].size);
+    qemu_fdt_setprop_string(fdt, nodename, "compatible",
+                            "sifive,fu540-c000-pdma");
+    g_free(nodename);
+
     nodename = g_strdup_printf("/soc/cache-controller@%lx",
         (long)memmap[SIFIVE_U_L2CC].base);
     qemu_fdt_add_subnode(fdt, nodename);
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_instance_init(Object *obj)
     object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
     object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
     object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
+    object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
 }
 
 static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
                                             SIFIVE_U_GPIO_IRQ0 + i));
     }
 
+    /* PDMA */
+    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
+
+    /* Connect PDMA interrupts to the PLIC */
+    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+                           qdev_get_gpio_in(DEVICE(s->plic),
+                                            SIFIVE_U_PDMA_IRQ0 + i));
+    }
+
     qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
         return;
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select CADENCE
     select HART
     select SIFIVE
+    select SIFIVE_PDMA
     select UNIMP
 
 config SPIKE
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_e_prci model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => misc}/sifive_e_prci.h | 0
 hw/{riscv => misc}/sifive_e_prci.c         | 2 +-
 hw/riscv/sifive_e.c                        | 2 +-
 hw/misc/Kconfig                            | 3 +++
 hw/misc/meson.build                        | 3 +++
 hw/riscv/Kconfig                           | 1 +
 hw/riscv/meson.build                       | 1 -
 7 files changed, 9 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
 rename hw/{riscv => misc}/sifive_e_prci.c (99%)

diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
similarity index 100%
rename from include/hw/riscv/sifive_e_prci.h
rename to include/hw/misc/sifive_e_prci.h
diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
similarity index 99%
rename from hw/riscv/sifive_e_prci.c
rename to hw/misc/sifive_e_prci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/misc/sifive_e_prci.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "hw/hw.h"
-#include "hw/riscv/sifive_e_prci.h"
+#include "hw/misc/sifive_e_prci.h"
 
 static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
-#include "hw/riscv/sifive_e_prci.h"
 #include "hw/riscv/boot.h"
+#include "hw/misc/sifive_e_prci.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
 config AVR_POWER
     bool
 
+config SIFIVE_E_PRCI
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
 # Mac devices
 softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
+# RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+
 # PKUnity SoC devices
 softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
 
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
     bool
     select HART
     select SIFIVE
+    select SIFIVE_E_PRCI
     select UNIMP
 
 config SIFIVE_U
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_prci model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => misc}/sifive_u_prci.h | 0
 include/hw/riscv/sifive_u.h                | 2 +-
 hw/{riscv => misc}/sifive_u_prci.c         | 2 +-
 hw/misc/Kconfig                            | 3 +++
 hw/misc/meson.build                        | 1 +
 hw/riscv/Kconfig                           | 1 +
 hw/riscv/meson.build                       | 1 -
 7 files changed, 7 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_u_prci.h (100%)
 rename hw/{riscv => misc}/sifive_u_prci.c (99%)

diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h
similarity index 100%
rename from include/hw/riscv/sifive_u_prci.h
rename to include/hw/misc/sifive_u_prci.h
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
 #include "hw/riscv/sifive_gpio.h"
-#include "hw/riscv/sifive_u_prci.h"
 #include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_prci.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
 #define RISCV_U_SOC(obj) \
diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c
similarity index 99%
rename from hw/riscv/sifive_u_prci.c
rename to hw/misc/sifive_u_prci.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u_prci.c
+++ b/hw/misc/sifive_u_prci.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
-#include "hw/riscv/sifive_u_prci.h"
+#include "hw/misc/sifive_u_prci.h"
 
 static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
 config SIFIVE_E_PRCI
     bool
 
+config SIFIVE_U_PRCI
+    bool
+
 source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
 
 # PKUnity SoC devices
 softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select HART
     select SIFIVE
     select SIFIVE_PDMA
+    select SIFIVE_U_PRCI
     select UNIMP
 
 config SPIKE
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => misc}/sifive_u_otp.h | 0
 include/hw/riscv/sifive_u.h               | 2 +-
 hw/{riscv => misc}/sifive_u_otp.c         | 2 +-
 hw/misc/Kconfig                           | 3 +++
 hw/misc/meson.build                       | 1 +
 hw/riscv/Kconfig                          | 1 +
 hw/riscv/meson.build                      | 1 -
 7 files changed, 7 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_u_otp.h (100%)
 rename hw/{riscv => misc}/sifive_u_otp.c (99%)

diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h
similarity index 100%
rename from include/hw/riscv/sifive_u_otp.h
rename to include/hw/misc/sifive_u_otp.h
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
 #include "hw/riscv/sifive_gpio.h"
-#include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_otp.h"
 #include "hw/misc/sifive_u_prci.h"
 
 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c
similarity index 99%
rename from hw/riscv/sifive_u_otp.c
rename to hw/misc/sifive_u_otp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u_otp.c
+++ b/hw/misc/sifive_u_otp.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
-#include "hw/riscv/sifive_u_otp.h"
+#include "hw/misc/sifive_u_otp.h"
 
 static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_POWER
 config SIFIVE_E_PRCI
     bool
 
+config SIFIVE_U_OTP
+    bool
+
 config SIFIVE_U_PRCI
     bool
 
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
 
 # PKUnity SoC devices
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select HART
     select SIFIVE
     select SIFIVE_PDMA
+    select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
     select UNIMP
 
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.

Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only supported trace target in that directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/trace.h                         | 1 -
 include/hw/{riscv => gpio}/sifive_gpio.h | 0
 include/hw/riscv/sifive_e.h              | 2 +-
 include/hw/riscv/sifive_u.h              | 2 +-
 hw/{riscv => gpio}/sifive_gpio.c         | 2 +-
 hw/gpio/Kconfig                          | 3 +++
 hw/gpio/meson.build                      | 1 +
 hw/gpio/trace-events                     | 6 ++++++
 hw/riscv/Kconfig                         | 2 ++
 hw/riscv/meson.build                     | 1 -
 hw/riscv/trace-events                    | 7 -------
 meson.build                              | 1 -
 12 files changed, 15 insertions(+), 13 deletions(-)
 delete mode 100644 hw/riscv/trace.h
 rename include/hw/{riscv => gpio}/sifive_gpio.h (100%)
 rename hw/{riscv => gpio}/sifive_gpio.c (99%)
 delete mode 100644 hw/riscv/trace-events

diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/hw/riscv/trace.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "trace/trace-hw_riscv.h"
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h
similarity index 100%
rename from include/hw/riscv/sifive_gpio.h
rename to include/hw/gpio/sifive_gpio.h
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 
 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
 #define RISCV_E_SOC(obj) \
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/net/cadence_gem.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_cpu.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 #include "hw/misc/sifive_u_otp.h"
 #include "hw/misc/sifive_u_prci.h"
 
diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c
similarity index 99%
rename from hw/riscv/sifive_gpio.c
rename to hw/gpio/sifive_gpio.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/gpio/sifive_gpio.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
-#include "hw/riscv/sifive_gpio.h"
+#include "hw/gpio/sifive_gpio.h"
 #include "migration/vmstate.h"
 #include "trace.h"
 
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -XXX,XX +XXX,XX @@ config PL061
 
 config GPIO_KEY
     bool
+
+config SIFIVE_GPIO
+    bool
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PR
 nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
 nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
+
+# sifive_gpio.c
+sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
+sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
+sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
+sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
     bool
     select HART
     select SIFIVE
+    select SIFIVE_GPIO
     select SIFIVE_E_PRCI
     select UNIMP
 
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select CADENCE
     select HART
     select SIFIVE
+    select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/hw/riscv/trace-events
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-# See docs/devel/tracing.txt for syntax documentation.
-
-# hw/gpio/sifive_gpio.c
-sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
-sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
-sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
diff --git a/meson.build b/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/meson.build
+++ b/meson.build
@@ -XXX,XX +XXX,XX @@ if have_system
     'hw/watchdog',
     'hw/xen',
     'hw/gpio',
-    'hw/riscv',
     'migration',
     'net',
     'ui',
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => intc}/sifive_clint.h | 0
 hw/{riscv => intc}/sifive_clint.c         | 2 +-
 hw/riscv/microchip_pfsoc.c                | 2 +-
 hw/riscv/sifive_e.c                       | 2 +-
 hw/riscv/sifive_u.c                       | 2 +-
 hw/riscv/spike.c                          | 2 +-
 hw/riscv/virt.c                           | 2 +-
 hw/intc/Kconfig                           | 3 +++
 hw/intc/meson.build                       | 1 +
 hw/riscv/Kconfig                          | 5 +++++
 hw/riscv/meson.build                      | 1 -
 11 files changed, 15 insertions(+), 7 deletions(-)
 rename include/hw/{riscv => intc}/sifive_clint.h (100%)
 rename hw/{riscv => intc}/sifive_clint.c (99%)

diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint.h
similarity index 100%
rename from include/hw/riscv/sifive_clint.h
rename to include/hw/intc/sifive_clint.h
diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c
similarity index 99%
rename from hw/riscv/sifive_clint.c
rename to hw/intc/sifive_clint.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/intc/sifive_clint.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "target/riscv/cpu.h"
 #include "hw/qdev-properties.h"
-#include "hw/riscv/sifive_clint.h"
+#include "hw/intc/sifive_clint.h"
 #include "qemu/timer.h"
 
 static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/microchip_pfsoc.h"
+#include "hw/intc/sifive_clint.h"
 #include "sysemu/sysemu.h"
 
 /*
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
 #include "hw/riscv/boot.h"
+#include "hw/intc/sifive_clint.h"
 #include "hw/misc/sifive_e_prci.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
+#include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "net/eth.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_htif.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/spike.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/sifive_plic.h"
-#include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -XXX,XX +XXX,XX @@ config RX_ICU
 
 config LOONGSON_LIOINTC
     bool
+
+config SIFIVE_CLINT
+    bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
 specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
 specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
 specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
+specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
 specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
 specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
 specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
     bool
     select HART
     select SIFIVE
+    select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_E_PRCI
     select UNIMP
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select CADENCE
     select HART
     select SIFIVE
+    select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_U_OTP
@@ -XXX,XX +XXX,XX @@ config SPIKE
     select HART
     select HTIF
     select SIFIVE
+    select SIFIVE_CLINT
 
 config OPENTITAN
     bool
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PFLASH_CFI01
     select SIFIVE
+    select SIFIVE_CLINT
 
 config MICROCHIP_PFSOC
     bool
     select HART
     select SIFIVE
+    select SIFIVE_CLINT
     select UNIMP
     select MCHP_PFSOC_MMUART
     select SIFIVE_PDMA
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 {include/hw/riscv => hw/intc}/sifive_plic.h | 0
 hw/{riscv => intc}/sifive_plic.c            | 2 +-
 hw/riscv/microchip_pfsoc.c                  | 2 +-
 hw/riscv/sifive_e.c                         | 2 +-
 hw/riscv/sifive_u.c                         | 2 +-
 hw/riscv/virt.c                             | 2 +-
 hw/intc/Kconfig                             | 3 +++
 hw/intc/meson.build                         | 1 +
 hw/riscv/Kconfig                            | 5 +++++
 hw/riscv/meson.build                        | 1 -
 10 files changed, 14 insertions(+), 6 deletions(-)
 rename {include/hw/riscv => hw/intc}/sifive_plic.h (100%)
 rename hw/{riscv => intc}/sifive_plic.c (99%)

diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h
similarity index 100%
rename from include/hw/riscv/sifive_plic.h
rename to hw/intc/sifive_plic.h
diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c
similarity index 99%
rename from hw/riscv/sifive_plic.c
rename to hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/pci/msi.h"
 #include "hw/boards.h"
 #include "hw/qdev-properties.h"
+#include "hw/intc/sifive_plic.h"
 #include "target/riscv/cpu.h"
 #include "sysemu/sysemu.h"
-#include "hw/riscv/sifive_plic.h"
 
 #define RISCV_DEBUG_PLIC 0
 
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/microchip_pfsoc.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "sysemu/sysemu.h"
 
 /*
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
 #include "hw/riscv/boot.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "hw/misc/sifive_e_prci.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "chardev/char.h"
 #include "net/eth.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/serial.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_plic.h"
 #include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
 #include "hw/intc/sifive_clint.h"
+#include "hw/intc/sifive_plic.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -XXX,XX +XXX,XX @@ config LOONGSON_LIOINTC
 
 config SIFIVE_CLINT
     bool
+
+config SIFIVE_PLIC
+    bool
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
 specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
 specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c'))
 specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
+specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
 specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
 specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c'))
 specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_GPIO
+    select SIFIVE_PLIC
     select SIFIVE_E_PRCI
     select UNIMP
 
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PDMA
+    select SIFIVE_PLIC
     select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
     select UNIMP
@@ -XXX,XX +XXX,XX @@ config SPIKE
     select HTIF
     select SIFIVE
     select SIFIVE_CLINT
+    select SIFIVE_PLIC
 
 config OPENTITAN
     bool
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select PFLASH_CFI01
     select SIFIVE
     select SIFIVE_CLINT
+    select SIFIVE_PLIC
 
 config MICROCHIP_PFSOC
     bool
@@ -XXX,XX +XXX,XX @@ config MICROCHIP_PFSOC
     select UNIMP
     select MCHP_PFSOC_MMUART
     select SIFIVE_PDMA
+    select SIFIVE_PLIC
     select CADENCE_SDHCI
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move riscv_htif model to hw/char directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => char}/riscv_htif.h | 0
 hw/{riscv => char}/riscv_htif.c         | 2 +-
 hw/riscv/spike.c                        | 2 +-
 hw/char/Kconfig                         | 3 +++
 hw/char/meson.build                     | 1 +
 hw/riscv/Kconfig                        | 3 ---
 hw/riscv/meson.build                    | 1 -
 7 files changed, 6 insertions(+), 6 deletions(-)
 rename include/hw/{riscv => char}/riscv_htif.h (100%)
 rename hw/{riscv => char}/riscv_htif.c (99%)

diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h
similarity index 100%
rename from include/hw/riscv/riscv_htif.h
rename to include/hw/char/riscv_htif.h
diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c
similarity index 99%
rename from hw/riscv/riscv_htif.c
rename to hw/char/riscv_htif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/riscv_htif.c
+++ b/hw/char/riscv_htif.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "qemu/log.h"
 #include "hw/sysbus.h"
+#include "hw/char/riscv_htif.h"
 #include "hw/char/serial.h"
 #include "chardev/char.h"
 #include "chardev/char-fe.h"
-#include "hw/riscv/riscv_htif.h"
 #include "qemu/timer.h"
 #include "qemu/error-report.h"
 
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/loader.h"
 #include "hw/sysbus.h"
 #include "target/riscv/cpu.h"
-#include "hw/riscv/riscv_htif.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/riscv/spike.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
+#include "hw/char/riscv_htif.h"
 #include "hw/intc/sifive_clint.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -XXX,XX +XXX,XX @@
 config ESCC
     bool
 
+config HTIF
+    bool
+
 config PARALLEL
     bool
     default y
diff --git a/hw/char/meson.build b/hw/char/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
 softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
 
+specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
 specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
 specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
 specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@
-config HTIF
-    bool
-
 config HART
     bool
 
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
-riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
 riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
 
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => char}/sifive_uart.h | 0
 hw/{riscv => char}/sifive_uart.c         | 2 +-
 hw/riscv/sifive_e.c                      | 2 +-
 hw/riscv/sifive_u.c                      | 2 +-
 hw/char/Kconfig                          | 3 +++
 hw/char/meson.build                      | 1 +
 hw/riscv/Kconfig                         | 2 ++
 hw/riscv/meson.build                     | 1 -
 8 files changed, 9 insertions(+), 4 deletions(-)
 rename include/hw/{riscv => char}/sifive_uart.h (100%)
 rename hw/{riscv => char}/sifive_uart.c (99%)

diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h
similarity index 100%
rename from include/hw/riscv/sifive_uart.h
rename to include/hw/char/sifive_uart.h
diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c
similarity index 99%
rename from hw/riscv/sifive_uart.c
rename to hw/char/sifive_uart.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -XXX,XX +XXX,XX @@
 #include "chardev/char-fe.h"
 #include "hw/hw.h"
 #include "hw/irq.h"
-#include "hw/riscv/sifive_uart.h"
+#include "hw/char/sifive_uart.h"
 
 /*
  * Not yet implemented:
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_e.h"
 #include "hw/riscv/boot.h"
+#include "hw/char/sifive_uart.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
 #include "hw/misc/sifive_e_prci.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/unimp.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_uart.h"
 #include "hw/riscv/sifive_u.h"
 #include "hw/riscv/boot.h"
+#include "hw/char/sifive_uart.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
 #include "chardev/char.h"
diff --git a/hw/char/Kconfig b/hw/char/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/Kconfig
+++ b/hw/char/Kconfig
@@ -XXX,XX +XXX,XX @@ config AVR_USART
 
 config MCHP_PFSOC_MMUART
     bool
+
+config SIFIVE_UART
+    bool
diff --git a/hw/char/meson.build b/hw/char/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_uart.c'))
 softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c'))
 softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c'))
+softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c'))
 softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
 softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
 softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
     select SIFIVE_CLINT
     select SIFIVE_GPIO
     select SIFIVE_PLIC
+    select SIFIVE_UART
     select SIFIVE_E_PRCI
     select UNIMP
 
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
     select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_PLIC
+    select SIFIVE_UART
     select SIFIVE_U_OTP
     select SIFIVE_U_PRCI
     select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/{riscv => misc}/sifive_test.h | 0
 hw/{riscv => misc}/sifive_test.c         | 2 +-
 hw/riscv/virt.c                          | 2 +-
 hw/misc/Kconfig                          | 3 +++
 hw/misc/meson.build                      | 1 +
 hw/riscv/Kconfig                         | 1 +
 hw/riscv/meson.build                     | 1 -
 7 files changed, 7 insertions(+), 3 deletions(-)
 rename include/hw/{riscv => misc}/sifive_test.h (100%)
 rename hw/{riscv => misc}/sifive_test.c (98%)

diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h
similarity index 100%
rename from include/hw/riscv/sifive_test.h
rename to include/hw/misc/sifive_test.h
diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c
similarity index 98%
rename from hw/riscv/sifive_test.c
rename to hw/misc/sifive_test.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/misc/sifive_test.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "sysemu/runstate.h"
 #include "hw/hw.h"
-#include "hw/riscv/sifive_test.h"
+#include "hw/misc/sifive_test.h"
 
 static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
 {
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/serial.h"
 #include "target/riscv/cpu.h"
 #include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
 #include "hw/intc/sifive_clint.h"
 #include "hw/intc/sifive_plic.h"
+#include "hw/misc/sifive_test.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -XXX,XX +XXX,XX @@ config MAC_VIA
 config AVR_POWER
     bool
 
+config SIFIVE_TEST
+    bool
+
 config SIFIVE_E_PRCI
     bool
 
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
 softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
 
 # RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_PLIC
+    select SIFIVE_TEST
 
 config MICROCHIP_PFSOC
     bool
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
 riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

Every RISC-V machine needs riscv_hart hence there is no need to
have a dedicated Kconfig option for it. Drop the Kconfig option
and always build riscv_hart.c.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/Kconfig     | 9 ---------
 hw/riscv/meson.build | 2 +-
 2 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@
-config HART
-    bool
-
 config IBEX
     bool
 
@@ -XXX,XX +XXX,XX @@ config SIFIVE
 
 config SIFIVE_E
     bool
-    select HART
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_GPIO
@@ -XXX,XX +XXX,XX @@ config SIFIVE_E
 config SIFIVE_U
     bool
     select CADENCE
-    select HART
     select SIFIVE
     select SIFIVE_CLINT
     select SIFIVE_GPIO
@@ -XXX,XX +XXX,XX @@ config SIFIVE_U
 
 config SPIKE
     bool
-    select HART
     select HTIF
     select SIFIVE
     select SIFIVE_CLINT
@@ -XXX,XX +XXX,XX @@ config SPIKE
 config OPENTITAN
     bool
     select IBEX
-    select HART
     select UNIMP
 
 config RISCV_VIRT
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     imply PCI_DEVICES
     imply TEST_DEVICES
     select PCI
-    select HART
     select SERIAL
     select GOLDFISH_RTC
     select VIRTIO_MMIO
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
 
 config MICROCHIP_PFSOC
     bool
-    select HART
     select SIFIVE
     select SIFIVE_CLINT
     select UNIMP
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@
 riscv_ss = ss.source_set()
 riscv_ss.add(files('boot.c'), fdt)
 riscv_ss.add(files('numa.c'))
-riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
+riscv_ss.add(files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
 riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-- 
2.28.0

From: Bin Meng <bin.meng@windriver.com>

The name SIFIVE is too vague to convey the required component of
MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in
each machine instead.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-12-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/Kconfig | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

From: Bin Meng <bin.meng@windriver.com>

At present the Kconfig file is in disorder. Let's sort the options.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-13-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/Kconfig | 58 ++++++++++++++++++++++++------------------------
 1 file changed, 29 insertions(+), 29 deletions(-)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -XXX,XX +XXX,XX @@
 config IBEX
     bool
 
-config SIFIVE_E
-    bool
-    select MSI_NONBROKEN
-    select SIFIVE_CLINT
-    select SIFIVE_GPIO
-    select SIFIVE_PLIC
-    select SIFIVE_UART
-    select SIFIVE_E_PRCI
-    select UNIMP
-
-config SIFIVE_U
+config MICROCHIP_PFSOC
     bool
-    select CADENCE
+    select CADENCE_SDHCI
+    select MCHP_PFSOC_MMUART
     select MSI_NONBROKEN
     select SIFIVE_CLINT
-    select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_PLIC
-    select SIFIVE_UART
-    select SIFIVE_U_OTP
-    select SIFIVE_U_PRCI
     select UNIMP
 
-config SPIKE
-    bool
-    select HTIF
-    select MSI_NONBROKEN
-    select SIFIVE_CLINT
-    select SIFIVE_PLIC
-
 config OPENTITAN
     bool
     select IBEX
@@ -XXX,XX +XXX,XX @@ config RISCV_VIRT
     bool
     imply PCI_DEVICES
     imply TEST_DEVICES
+    select GOLDFISH_RTC
     select MSI_NONBROKEN
     select PCI
-    select SERIAL
-    select GOLDFISH_RTC
-    select VIRTIO_MMIO
     select PCI_EXPRESS_GENERIC_BRIDGE
     select PFLASH_CFI01
+    select SERIAL
     select SIFIVE_CLINT
     select SIFIVE_PLIC
     select SIFIVE_TEST
+    select VIRTIO_MMIO
 
-config MICROCHIP_PFSOC
+config SIFIVE_E
     bool
     select MSI_NONBROKEN
     select SIFIVE_CLINT
+    select SIFIVE_GPIO
+    select SIFIVE_PLIC
+    select SIFIVE_UART
+    select SIFIVE_E_PRCI
     select UNIMP
-    select MCHP_PFSOC_MMUART
+
+config SIFIVE_U
+    bool
+    select CADENCE
+    select MSI_NONBROKEN
+    select SIFIVE_CLINT
+    select SIFIVE_GPIO
     select SIFIVE_PDMA
     select SIFIVE_PLIC
-    select CADENCE_SDHCI
+    select SIFIVE_UART
+    select SIFIVE_U_OTP
+    select SIFIVE_U_PRCI
+    select UNIMP
+
+config SPIKE
+    bool
+    select HTIF
+    select MSI_NONBROKEN
+    select SIFIVE_CLINT
+    select SIFIVE_PLIC
-- 
2.28.0

From: Alistair Francis <alistair.francis@wdc.com>

The following changes since commit 4c127fdbe81d66e7cafed90908d0fd1f6f2a6cd0:

Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211021' into staging (2021-10-21 09:53:27 -0700)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211022-2

for you to fetch changes up to 11ec06f9eaedc801ded34c79861367b76ab2b731:

hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id (2021-10-22 23:35:47 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for QEMU 6.2

- Vector extension bug fixes
 - Bit manipulation extension bug fix
 - Support vhost-user and numa mem options on all boards
 - Rationalise XLEN and operand lengths
 - Bump the OpenTitan FPGA support
 - Remove the Ibex PLIC
 - General code cleanup

----------------------------------------------------------------
Alistair Francis (7):
      target/riscv: Remove some unused macros
      target/riscv: Organise the CPU properties
      hw/riscv: opentitan: Update to the latest build
      hw/intc: Remove the Ibex PLIC
      hw/intc: sifive_plic: Move the properties
      hw/intc: sifive_plic: Cleanup the realize function
      hw/intc: sifive_plic: Cleanup the irq_request function

Bin Meng (6):
      hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
      hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
      hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id
      hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id
      hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id
      hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id

Frank Chang (2):
      target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
      target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh

Mingwang Li (1):
      hw/riscv: virt: Use machine->ram as the system memory

Philipp Tomsich (1):
      target/riscv: Fix orc.b implementation

Richard Henderson (15):
      target/riscv: Move cpu_get_tb_cpu_state out of line
      target/riscv: Create RISCVMXL enumeration
      target/riscv: Split misa.mxl and misa.ext
      target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
      target/riscv: Add MXL/SXL/UXL to TB_FLAGS
      target/riscv: Use REQUIRE_64BIT in amo_check64
      target/riscv: Properly check SEW in amo_op
      target/riscv: Replace is_32bit with get_xl/get_xlen
      target/riscv: Replace DisasContext.w with DisasContext.ol
      target/riscv: Use gen_arith_per_ol for RVM
      target/riscv: Adjust trans_rev8_32 for riscv64
      target/riscv: Use gen_unary_per_ol for RVB
      target/riscv: Use gen_shift*_per_ol for RVB, RVI
      target/riscv: Use riscv_csrrw_debug for cpu_dump
      target/riscv: Compute mstatus.sd on demand

Travis Geiselbrecht (1):
      target/riscv: line up all of the registers in the info register dump

From: Frank Chang <frank.chang@sifive.com>

oprsz and maxsz are passed with the same value in commit: eee2d61e202.
However, vmv.v.v was missed in that commit and should pass the same
value as well in its tcg_gen_gvec_2_ptr() call.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211007081803.1705656-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

From: Travis Geiselbrecht <travisg@gmail.com>

Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.

Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

From: Philipp Tomsich <philipp.tomsich@vrull.eu>

The earlier implementation fell into a corner case for bytes that were
0x01, giving a wrong result (but not affecting our application test
cases for strings, as an ASCII value 0x01 is rare in those...).

This changes the algorithm to:
 1. Mask out the high-bit of each bytes (so that each byte is <= 127).
 2. Add 127 to each byte (i.e. if the low 7 bits are not 0, this will overflow
    into the highest bit of each byte).
 3. Bitwise-or the original value back in (to cover those cases where the
    source byte was exactly 128) to saturate the high-bit.
 4. Shift-and-mask (implemented as a mask-and-shift) to extract the MSB of
    each byte into its LSB.
 5. Multiply with 0xff to fan out the LSB to all bits of each byte.

Fixes: d7a4fcb034 ("target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci")

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reported-by: Vincent Palatin <vpalatin@rivosinc.com>
Tested-by: Vincent Palatin <vpalatin@rivosinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211013184125.2010897-1-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
 static void gen_orc_b(TCGv ret, TCGv source1)
 {
     TCGv  tmp = tcg_temp_new();
-    TCGv  ones = tcg_constant_tl(dup_const_tl(MO_8, 0x01));
+    TCGv  low7 = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
 
-    /* Set lsb in each byte if the byte was zero. */
-    tcg_gen_sub_tl(tmp, source1, ones);
-    tcg_gen_andc_tl(tmp, tmp, source1);
+    /* Set msb in each byte if the byte was non-zero. */
+    tcg_gen_and_tl(tmp, source1, low7);
+    tcg_gen_add_tl(tmp, tmp, low7);
+    tcg_gen_or_tl(tmp, tmp, source1);
+
+    /* Extract the msb to the lsb in each byte */
+    tcg_gen_andc_tl(tmp, tmp, low7);
     tcg_gen_shri_tl(tmp, tmp, 7);
-    tcg_gen_andc_tl(tmp, ones, tmp);
 
     /* Replicate the lsb of each byte across the byte. */
     tcg_gen_muli_tl(ret, tmp, 0xff);
-- 
2.31.1

From: Mingwang Li <limingwang@huawei.com>

If default main_mem is used to be registered as the system memory,
other memory cannot be initialized. Therefore, the system memory
should be initialized to the machine->ram, which consists of the
default main_mem and other possible memory required by applications,
such as shared hugepage memory in DPDK.

Also, the mc->defaul_ram_id should be set to the default main_mem,
such as "riscv_virt_board.ram" for the virt machine.

Signed-off-by: Mingwang Li <limingwang@huawei.com>
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211016030908.40480-1-limingwang@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/virt.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     const MemMapEntry *memmap = virt_memmap;
     RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     char *plic_hart_config, *soc_name;
     target_ulong start_addr = memmap[VIRT_DRAM].base;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     }
 
     /* register system main memory (actual RAM) */
-    memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
-                           machine->ram_size, &error_fatal);
     memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
-        main_mem);
+        machine->ram);
 
     /* create device tree */
     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+    mc->default_ram_id = "riscv_virt_board.ram";
 
     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 
-- 
2.31.1

From: Frank Chang <frank.chang@sifive.com>

TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
rvv is enabled.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211015074627.3957162-2-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       | 14 +++++++-------
 target/riscv/translate.c |  2 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 
-#define TB_FLAGS_MMU_MASK   7
 #define TB_FLAGS_PRIV_MMU_MASK                3
 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
@@ -XXX,XX +XXX,XX @@ typedef CPURISCVState CPUArchState;
 typedef RISCVCPU ArchCPU;
 #include "exec/cpu-all.h"
 
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
-FIELD(TB_FLAGS, LMUL, 3, 2)
-FIELD(TB_FLAGS, SEW, 5, 3)
-FIELD(TB_FLAGS, VILL, 8, 1)
+FIELD(TB_FLAGS, MEM_IDX, 0, 3)
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
+FIELD(TB_FLAGS, LMUL, 4, 2)
+FIELD(TB_FLAGS, SEW, 6, 3)
+FIELD(TB_FLAGS, VILL, 9, 1)
 /* Is a Hypervisor instruction load/store allowed? */
-FIELD(TB_FLAGS, HLSX, 9, 1)
-FIELD(TB_FLAGS, MSTATUS_HS_FS, 10, 2)
+FIELD(TB_FLAGS, HLSX, 10, 1)
+FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
 
 bool riscv_cpu_is_32bit(CPURISCVState *env);
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     uint32_t tb_flags = ctx->base.tb->flags;
 
     ctx->pc_succ_insn = ctx->base.pc_first;
-    ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK;
+    ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
     ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
     ctx->priv_ver = env->priv_ver;
 #if !defined(CONFIG_USER_ONLY)
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Since commit 1a9540d1f1a
("target/riscv: Drop support for ISA spec version 1.09.1")
these definitions are unused, remove them.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: f4d8a7a035f39c0a35d44c1e371c5c99cc2fa15a.1634531504.git.alistair.francis@wdc.com
---
 target/riscv/cpu_bits.h | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define SATP64_ASID         0x0FFFF00000000000ULL
 #define SATP64_PPN          0x00000FFFFFFFFFFFULL
 
-/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
-#define VM_1_09_MBARE       0
-#define VM_1_09_MBB         1
-#define VM_1_09_MBBID       2
-#define VM_1_09_SV32        8
-#define VM_1_09_SV39        9
-#define VM_1_09_SV48        10
-
 /* VM modes (satp.mode) privileged ISA 1.10 */
 #define VM_1_10_MBARE       0
 #define VM_1_10_SV32        1
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Organise the CPU properties so that standard extensions come first
then followed by experimental extensions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com
---
 target/riscv/cpu.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_init(Object *obj)
 }
 
 static Property riscv_cpu_properties[] = {
+    /* Defaults for standard extensions */
     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
@@ -XXX,XX +XXX,XX @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
-    /* This is experimental so mark with 'x-' */
+    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
+    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
+    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+
+    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
+
+    /* These are experimental so mark with 'x-' */
     DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
     DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
-    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
-    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
-    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
-    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
-    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
-    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
     /* ePMP 0.9.3 */
     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
 
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the function to cpu_helper.c, as it is large and growing.

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
     return cpu->cfg.vlen >> (sew + 3 - lmul);
 }
 
-static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
-                                        target_ulong *cs_base, uint32_t *pflags)
-{
-    uint32_t flags = 0;
-
-    *pc = env->pc;
-    *cs_base = 0;
-
-    if (riscv_has_ext(env, RVV)) {
-        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
-        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
-                    FIELD_EX64(env->vtype, VTYPE, VILL));
-        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
-                    FIELD_EX64(env->vtype, VTYPE, VSEW));
-        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
-                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
-        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
-    } else {
-        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
-    }
-
-#ifdef CONFIG_USER_ONLY
-    flags |= TB_FLAGS_MSTATUS_FS;
-#else
-    flags |= cpu_mmu_index(env, 0);
-    if (riscv_cpu_fp_enabled(env)) {
-        flags |= env->mstatus & MSTATUS_FS;
-    }
-
-    if (riscv_has_ext(env, RVH)) {
-        if (env->priv == PRV_M ||
-            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
-            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
-                get_field(env->hstatus, HSTATUS_HU))) {
-            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
-        }
-
-        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
-                           get_field(env->mstatus_hs, MSTATUS_FS));
-    }
-#endif
-
-    *pflags = flags;
-}
+void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+                          target_ulong *cs_base, uint32_t *pflags);
 
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 #endif
 }
 
+void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
+                          target_ulong *cs_base, uint32_t *pflags)
+{
+    uint32_t flags = 0;
+
+    *pc = env->pc;
+    *cs_base = 0;
+
+    if (riscv_has_ext(env, RVV)) {
+        uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
+        bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+        flags = FIELD_DP32(flags, TB_FLAGS, VILL,
+                    FIELD_EX64(env->vtype, VTYPE, VILL));
+        flags = FIELD_DP32(flags, TB_FLAGS, SEW,
+                    FIELD_EX64(env->vtype, VTYPE, VSEW));
+        flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
+                    FIELD_EX64(env->vtype, VTYPE, VLMUL));
+        flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
+    } else {
+        flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
+    }
+
+#ifdef CONFIG_USER_ONLY
+    flags |= TB_FLAGS_MSTATUS_FS;
+#else
+    flags |= cpu_mmu_index(env, 0);
+    if (riscv_cpu_fp_enabled(env)) {
+        flags |= env->mstatus & MSTATUS_FS;
+    }
+
+    if (riscv_has_ext(env, RVH)) {
+        if (env->priv == PRV_M ||
+            (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+            (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+                get_field(env->hstatus, HSTATUS_HU))) {
+            flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
+        }
+
+        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,
+                           get_field(env->mstatus_hs, MSTATUS_FS));
+    }
+#endif
+
+    *pflags = flags;
+}
+
 #ifndef CONFIG_USER_ONLY
 static int riscv_cpu_local_irq_pending(CPURISCVState *env)
 {
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Move the MXL_RV* defines to enumerators.

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define MISA32_MXL          0xC0000000
 #define MISA64_MXL          0xC000000000000000ULL
 
-#define MXL_RV32            1
-#define MXL_RV64            2
-#define MXL_RV128           3
+typedef enum {
+    MXL_RV32  = 1,
+    MXL_RV64  = 2,
+    MXL_RV128 = 3,
+} RISCVMXL;
 
 /* sstatus CSR bits */
 #define SSTATUS_UIE         0x00000001
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

The hw representation of misa.mxl is at the high bits of the
misa csr.  Representing this in the same way inside QEMU
results in overly complex code trying to check that field.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-4-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h          | 15 +++----
 linux-user/elfload.c        |  2 +-
 linux-user/riscv/cpu_loop.c |  2 +-
 target/riscv/cpu.c          | 78 +++++++++++++++++++++----------------
 target/riscv/csr.c          | 44 ++++++++++++++-------
 target/riscv/gdbstub.c      |  8 ++--
 target/riscv/machine.c      | 10 +++--
 target/riscv/translate.c    | 10 +++--
 8 files changed, 100 insertions(+), 69 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu-defs.h"
 #include "fpu/softfloat-types.h"
 #include "qom/object.h"
+#include "cpu_bits.h"
 
 #define TCG_GUEST_DEFAULT_MO 0
 
@@ -XXX,XX +XXX,XX @@
 # define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
 #endif
 
-#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
-#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
-
 #define RV(x) ((target_ulong)1 << (x - 'A'))
 
 #define RVI RV('I')
@@ -XXX,XX +XXX,XX @@ struct CPURISCVState {
     target_ulong priv_ver;
     target_ulong bext_ver;
     target_ulong vext_ver;
-    target_ulong misa;
-    target_ulong misa_mask;
+
+    /* RISCVMXL, but uint32_t for vmstate migration */
+    uint32_t misa_mxl;      /* current mxl */
+    uint32_t misa_mxl_max;  /* max mxl for this cpu */
+    uint32_t misa_ext;      /* current extensions */
+    uint32_t misa_ext_mask; /* max ext for this cpu */
 
     uint32_t features;
 
@@ -XXX,XX +XXX,XX @@ struct RISCVCPU {
 
 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
 {
-    return (env->misa & ext) != 0;
+    return (env->misa_ext & ext) != 0;
 }
 
 static inline bool riscv_feature(CPURISCVState *env, int feature)
@@ -XXX,XX +XXX,XX @@ static inline bool riscv_feature(CPURISCVState *env, int feature)
 }
 
 #include "cpu_user.h"
-#include "cpu_bits.h"
 
 extern const char * const riscv_int_regnames[];
 extern const char * const riscv_fpr_regnames[];
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
     uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
                     | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
 
-    return cpu->env.misa & mask;
+    return cpu->env.misa_ext & mask;
 #undef MISA_BIT
 }
 
diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/riscv/cpu_loop.c
+++ b/linux-user/riscv/cpu_loop.c
@@ -XXX,XX +XXX,XX @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
     env->gpr[xSP] = regs->sp;
     env->elf_flags = info->elf_flags;
 
-    if ((env->misa & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
+    if ((env->misa_ext & RVE) && !(env->elf_flags & EF_RISCV_RVE)) {
         error_report("Incompatible ELF: RVE cpu requires RVE ABI binary");
         exit(EXIT_FAILURE);
     }
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
 
 bool riscv_cpu_is_32bit(CPURISCVState *env)
 {
-    if (env->misa & RV64) {
-        return false;
-    }
-
-    return true;
+    return env->misa_mxl == MXL_RV32;
 }
 
-static void set_misa(CPURISCVState *env, target_ulong misa)
+static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
 {
-    env->misa_mask = env->misa = misa;
+    env->misa_mxl_max = env->misa_mxl = mxl;
+    env->misa_ext_mask = env->misa_ext = ext;
 }
 
 static void set_priv_version(CPURISCVState *env, int priv_ver)
@@ -XXX,XX +XXX,XX @@ static void riscv_any_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
 #if defined(TARGET_RISCV32)
-    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #elif defined(TARGET_RISCV64)
-    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
 #endif
     set_priv_version(env, PRIV_VERSION_1_11_0);
 }
@@ -XXX,XX +XXX,XX @@ static void rv64_base_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
-    set_misa(env, RV64);
+    set_misa(env, MXL_RV64, 0);
 }
 
 static void rv64_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
 }
 
 static void rv64_sifive_e_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
+    set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
@@ -XXX,XX +XXX,XX @@ static void rv32_base_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
     /* We set this in the realise function */
-    set_misa(env, RV32);
+    set_misa(env, MXL_RV32, 0);
 }
 
 static void rv32_sifive_u_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
 }
 
 static void rv32_sifive_e_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
+    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
 }
@@ -XXX,XX +XXX,XX @@ static void rv32_sifive_e_cpu_init(Object *obj)
 static void rv32_ibex_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV32 | RVI | RVM | RVC | RVU);
+    set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
     qdev_prop_set_bit(DEVICE(obj), "x-epmp", true);
@@ -XXX,XX +XXX,XX @@ static void rv32_ibex_cpu_init(Object *obj)
 static void rv32_imafcu_nommu_cpu_init(Object *obj)
 {
     CPURISCVState *env = &RISCV_CPU(obj)->env;
-    set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
+    set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
     set_priv_version(env, PRIV_VERSION_1_10_0);
     set_resetvec(env, DEFAULT_RSTVEC);
     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
 
     mcc->parent_reset(dev);
 #ifndef CONFIG_USER_ONLY
+    env->misa_mxl = env->misa_mxl_max;
     env->priv = PRV_M;
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
     env->mcause = 0;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
     CPURISCVState *env = &cpu->env;
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
     int priv_version = 0;
-    target_ulong target_misa = env->misa;
     Error *local_err = NULL;
 
     cpu_exec_realizefn(cs, &local_err);
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 
     set_resetvec(env, cpu->cfg.resetvec);
 
-    /* If only XLEN is set for misa, then set misa from properties */
-    if (env->misa == RV32 || env->misa == RV64) {
+    /* Validate that MISA_MXL is set properly. */
+    switch (env->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+    case MXL_RV64:
+        break;
+#endif
+    case MXL_RV32:
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    assert(env->misa_mxl_max == env->misa_mxl);
+
+    /* If only MISA_EXT is unset for misa, then set it from properties */
+    if (env->misa_ext == 0) {
+        uint32_t ext = 0;
+
         /* Do some ISA extension error checking */
         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
             error_setg(errp,
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 
         /* Set the ISA extensions, checks should have happened above */
         if (cpu->cfg.ext_i) {
-            target_misa |= RVI;
+            ext |= RVI;
         }
         if (cpu->cfg.ext_e) {
-            target_misa |= RVE;
+            ext |= RVE;
         }
         if (cpu->cfg.ext_m) {
-            target_misa |= RVM;
+            ext |= RVM;
         }
         if (cpu->cfg.ext_a) {
-            target_misa |= RVA;
+            ext |= RVA;
         }
         if (cpu->cfg.ext_f) {
-            target_misa |= RVF;
+            ext |= RVF;
         }
         if (cpu->cfg.ext_d) {
-            target_misa |= RVD;
+            ext |= RVD;
         }
         if (cpu->cfg.ext_c) {
-            target_misa |= RVC;
+            ext |= RVC;
         }
         if (cpu->cfg.ext_s) {
-            target_misa |= RVS;
+            ext |= RVS;
         }
         if (cpu->cfg.ext_u) {
-            target_misa |= RVU;
+            ext |= RVU;
         }
         if (cpu->cfg.ext_h) {
-            target_misa |= RVH;
+            ext |= RVH;
         }
         if (cpu->cfg.ext_v) {
             int vext_version = VEXT_VERSION_0_07_1;
-            target_misa |= RVV;
+            ext |= RVV;
             if (!is_power_of_2(cpu->cfg.vlen)) {
                 error_setg(errp,
                         "Vector extension VLEN must be power of 2");
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             set_vext_version(env, vext_version);
         }
 
-        set_misa(env, target_misa);
+        set_misa(env, env->misa_mxl, ext);
     }
 
     riscv_cpu_register_gdb_regs_for_features(cs);
@@ -XXX,XX +XXX,XX @@ char *riscv_isa_string(RISCVCPU *cpu)
     char *isa_str = g_new(char, maxlen);
     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
     for (i = 0; i < sizeof(riscv_exts); i++) {
-        if (cpu->env.misa & RV(riscv_exts[i])) {
+        if (cpu->env.misa_ext & RV(riscv_exts[i])) {
             *p++ = qemu_tolower(riscv_exts[i]);
         }
     }
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 {
 #if !defined(CONFIG_USER_ONLY)
     /* loose check condition for fcsr in vector extension */
-    if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
+    if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) {
         return RISCV_EXCP_NONE;
     }
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (env->misa & RVV) {
+    if (env->misa_ext & RVV) {
         return RISCV_EXCP_NONE;
     }
     return RISCV_EXCP_ILLEGAL_INST;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
 static RISCVException read_misa(CPURISCVState *env, int csrno,
                                 target_ulong *val)
 {
-    *val = env->misa;
+    target_ulong misa;
+
+    switch (env->misa_mxl) {
+    case MXL_RV32:
+        misa = (target_ulong)MXL_RV32 << 30;
+        break;
+#ifdef TARGET_RISCV64
+    case MXL_RV64:
+        misa = (target_ulong)MXL_RV64 << 62;
+        break;
+#endif
+    default:
+        g_assert_not_reached();
+    }
+
+    *val = misa | env->misa_ext;
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
 
+    /*
+     * misa.MXL writes are not supported by QEMU.
+     * Drop writes to those bits.
+     */
+
     /* Mask extensions that are not supported by this hart */
-    val &= env->misa_mask;
+    val &= env->misa_ext_mask;
 
     /* Mask extensions that are not supported by QEMU */
     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
@@ -XXX,XX +XXX,XX @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
         val &= ~RVC;
     }
 
-    /* misa.MXL writes are not supported by QEMU */
-    if (riscv_cpu_is_32bit(env)) {
-        val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
-    } else {
-        val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
+    /* If nothing changed, do nothing. */
+    if (val == env->misa_ext) {
+        return RISCV_EXCP_NONE;
     }
 
     /* flush translation cache */
-    if (val != env->misa) {
-        tb_flush(env_cpu(env));
-    }
-
-    env->misa = val;
-
+    tb_flush(env_cpu(env));
+    env->misa_ext = val;
     return RISCV_EXCP_NONE;
 }
 
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
 {
     if (n < 32) {
-        if (env->misa & RVD) {
+        if (env->misa_ext & RVD) {
             return gdb_get_reg64(buf, env->fpr[n]);
         }
-        if (env->misa & RVF) {
+        if (env->misa_ext & RVF) {
             return gdb_get_reg32(buf, env->fpr[n]);
         }
     /* there is hole between ft11 and fflags in fpu.xml */
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    if (env->misa & RVD) {
+    if (env->misa_ext & RVD) {
         gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
                                  36, "riscv-64bit-fpu.xml", 0);
-    } else if (env->misa & RVF) {
+    } else if (env->misa_ext & RVF) {
         gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
                                  36, "riscv-32bit-fpu.xml", 0);
     }
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_hyper = {
 
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
-    .version_id = 2,
-    .minimum_version_id = 2,
+    .version_id = 3,
+    .minimum_version_id = 3,
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
         VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_riscv_cpu = {
         VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
         VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
         VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
-        VMSTATE_UINTTL(env.misa, RISCVCPU),
-        VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
+        VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
+        VMSTATE_UINT32(env.misa_ext, RISCVCPU),
+        VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
+        VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
         VMSTATE_UINT32(env.features, RISCVCPU),
         VMSTATE_UINTTL(env.priv, RISCVCPU),
         VMSTATE_UINTTL(env.virt, RISCVCPU),
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* pc_succ_insn points to the instruction following base.pc_next */
     target_ulong pc_succ_insn;
     target_ulong priv_ver;
-    target_ulong misa;
+    RISCVMXL xl;
+    uint32_t misa_ext;
     uint32_t opcode;
     uint32_t mstatus_fs;
     uint32_t mstatus_hs_fs;
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
 {
-    return ctx->misa & ext;
+    return ctx->misa_ext & ext;
 }
 
 #ifdef TARGET_RISCV32
@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
 #else
 static inline bool is_32bit(DisasContext *ctx)
 {
-    return (ctx->misa & RV32) == RV32;
+    return ctx->xl == MXL_RV32;
 }
 #endif
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 #else
     ctx->virt_enabled = false;
 #endif
-    ctx->misa = env->misa;
+    ctx->xl = env->misa_mxl;
+    ctx->misa_ext = env->misa_ext;
     ctx->frm = -1;  /* unknown rounding mode */
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
     ctx->vlen = cpu->cfg.vlen;
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.

Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h            |  9 ++++++++-
 hw/riscv/boot.c               |  2 +-
 semihosting/arm-compat-semi.c |  2 +-
 target/riscv/cpu.c            | 24 ++++++++++++++----------
 target/riscv/cpu_helper.c     | 12 ++++++------
 target/riscv/csr.c            | 24 ++++++++++++------------
 target/riscv/gdbstub.c        |  2 +-
 target/riscv/monitor.c        |  4 ++--
 8 files changed, 45 insertions(+), 34 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VILL, 9, 1)
 FIELD(TB_FLAGS, HLSX, 10, 1)
 FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
 
-bool riscv_cpu_is_32bit(CPURISCVState *env);
+#ifdef TARGET_RISCV32
+#define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
+#else
+static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
+{
+    return env->misa_mxl;
+}
+#endif
 
 /*
  * A simplification for VLMAX
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@
 
 bool riscv_is_32bit(RISCVHartArrayState *harts)
 {
-    return riscv_cpu_is_32bit(&harts->harts[0].env);
+    return harts->harts[0].env.misa_mxl_max == MXL_RV32;
 }
 
 target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index XXXXXXX..XXXXXXX 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -XXX,XX +XXX,XX @@ static inline bool is_64bit_semihosting(CPUArchState *env)
 #if defined(TARGET_ARM)
     return is_a64(env);
 #elif defined(TARGET_RISCV)
-    return !riscv_cpu_is_32bit(env);
+    return riscv_cpu_mxl(env) != MXL_RV32;
 #else
 #error un-handled architecture
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
     }
 }
 
-bool riscv_cpu_is_32bit(CPURISCVState *env)
-{
-    return env->misa_mxl == MXL_RV32;
-}
-
 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
 {
     env->misa_mxl_max = env->misa_mxl = mxl;
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #ifndef CONFIG_USER_ONLY
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
                      (target_ulong)(env->mstatus >> 32));
     }
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
 {
     RISCVCPU *cpu = RISCV_CPU(s);
-    if (riscv_cpu_is_32bit(&cpu->env)) {
+
+    switch (riscv_cpu_mxl(&cpu->env)) {
+    case MXL_RV32:
         info->print_insn = print_insn_riscv32;
-    } else {
+        break;
+    case MXL_RV64:
         info->print_insn = print_insn_riscv64;
+        break;
+    default:
+        g_assert_not_reached();
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static gchar *riscv_gdb_arch_name(CPUState *cs)
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
 
-    if (riscv_cpu_is_32bit(env)) {
+    switch (riscv_cpu_mxl(env)) {
+    case MXL_RV32:
         return g_strdup("riscv:rv32");
-    } else {
+    case MXL_RV64:
         return g_strdup("riscv:rv64");
+    default:
+        g_assert_not_reached();
     }
 }
 
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
 
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
 {
-    uint64_t sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
+    uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
     uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
                             MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
                             MSTATUS64_UXL | sd;
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
 
     if (first_stage == true) {
         if (use_background) {
-            if (riscv_cpu_is_32bit(env)) {
+            if (riscv_cpu_mxl(env) == MXL_RV32) {
                 base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
                 vm = get_field(env->vsatp, SATP32_MODE);
             } else {
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
                 vm = get_field(env->vsatp, SATP64_MODE);
             }
         } else {
-            if (riscv_cpu_is_32bit(env)) {
+            if (riscv_cpu_mxl(env) == MXL_RV32) {
                 base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
                 vm = get_field(env->satp, SATP32_MODE);
             } else {
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         }
         widened = 0;
     } else {
-        if (riscv_cpu_is_32bit(env)) {
+        if (riscv_cpu_mxl(env) == MXL_RV32) {
             base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
             vm = get_field(env->hgatp, SATP32_MODE);
         } else {
@@ -XXX,XX +XXX,XX @@ restart:
         }
 
         target_ulong pte;
-        if (riscv_cpu_is_32bit(env)) {
+        if (riscv_cpu_mxl(env) == MXL_RV32) {
             pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
         } else {
             pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
     int page_fault_exceptions, vm;
     uint64_t stap_mode;
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         stap_mode = SATP32_MODE;
     } else {
         stap_mode = SATP64_MODE;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
             }
             break;
         }
-        if (riscv_cpu_is_32bit(env)) {
+        if (riscv_cpu_mxl(env) == MXL_RV32) {
             switch (csrno) {
             case CSR_CYCLEH:
                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
@@ -XXX,XX +XXX,XX @@ static RISCVException ctr(CPURISCVState *env, int csrno)
 
 static RISCVException ctr32(CPURISCVState *env, int csrno)
 {
-    if (!riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException any(CPURISCVState *env, int csrno)
 
 static RISCVException any32(CPURISCVState *env, int csrno)
 {
-    if (!riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException hmode(CPURISCVState *env, int csrno)
 
 static RISCVException hmode32(CPURISCVState *env, int csrno)
 {
-    if (!riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
         if (riscv_cpu_virt_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
         } else {
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
 
 static int validate_vm(CPURISCVState *env, target_ulong vm)
 {
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         return valid_vm_1_10_32[vm & 0xf];
     } else {
         return valid_vm_1_10_64[vm & 0xf];
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
         MSTATUS_TW;
 
-    if (!riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
         /*
          * RV32: MPV and GVA are not in mstatus. The current plan is to
          * add them to mstatush. For now, we just don't support it.
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 
     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
     } else {
         mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
 {
     target_ulong mask = (sstatus_v1_10_mask);
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         mask |= SSTATUS32_SD;
     } else {
         mask |= SSTATUS64_SD;
@@ -XXX,XX +XXX,XX @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
         return RISCV_EXCP_NONE;
     }
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         vm = validate_vm(env, get_field(val, SATP32_MODE));
         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
         asid = (val ^ env->satp) & SATP32_ASID;
@@ -XXX,XX +XXX,XX @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
     *val = env->hstatus;
-    if (!riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) != MXL_RV32) {
         /* We only support 64-bit VSXL */
         *val = set_field(*val, HSTATUS_VSXL, 2);
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException write_hstatus(CPURISCVState *env, int csrno,
                                     target_ulong val)
 {
     env->hstatus = val;
-    if (!riscv_cpu_is_32bit(env) && get_field(val, HSTATUS_VSXL) != 2) {
+    if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
     }
     if (get_field(val, HSTATUS_VSBE) != 0) {
@@ -XXX,XX +XXX,XX @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
     } else {
         env->htimedelta = val;
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
     CPURISCVState *env = &cpu->env;
     GString *s = g_string_new(NULL);
     riscv_csr_predicate_fn predicate;
-    int bitsize = riscv_cpu_is_32bit(env) ? 32 : 64;
+    int bitsize = 16 << env->misa_mxl_max;
     int i;
 
     g_string_printf(s, "<?xml version=\"1.0\"?>");
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -XXX,XX +XXX,XX @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
     target_ulong last_size;
     int last_attr;
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
         vm = get_field(env->satp, SATP32_MODE);
     } else {
@@ -XXX,XX +XXX,XX @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
         return;
     }
 
-    if (riscv_cpu_is_32bit(env)) {
+    if (riscv_cpu_mxl(env) == MXL_RV32) {
         if (!(env->satp & SATP32_MODE)) {
             monitor_printf(mon, "No translation or protection\n");
             return;
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Begin adding support for switching XLEN at runtime.  Extract the
effective XLEN from MISA and MSTATUS and store for use during translation.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-6-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  2 ++
 target/riscv/cpu.c        |  8 ++++++++
 target/riscv/cpu_helper.c | 33 +++++++++++++++++++++++++++++++++
 target/riscv/csr.c        |  3 +++
 target/riscv/translate.c  |  2 +-
 5 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(TB_FLAGS, VILL, 9, 1)
 /* Is a Hypervisor instruction load/store allowed? */
 FIELD(TB_FLAGS, HLSX, 10, 1)
 FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
+/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
+FIELD(TB_FLAGS, XL, 13, 2)
 
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset(DeviceState *dev)
     env->misa_mxl = env->misa_mxl_max;
     env->priv = PRV_M;
     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
+    if (env->misa_mxl > MXL_RV32) {
+        /*
+         * The reset status of SXL/UXL is undefined, but mstatus is WARL
+         * and we must ensure that the value after init is valid for read.
+         */
+        env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
+        env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
+    }
     env->mcause = 0;
     env->pc = env->resetvec;
     env->two_stage_lookup = false;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
 #endif
 }
 
+static RISCVMXL cpu_get_xl(CPURISCVState *env)
+{
+#if defined(TARGET_RISCV32)
+    return MXL_RV32;
+#elif defined(CONFIG_USER_ONLY)
+    return MXL_RV64;
+#else
+    RISCVMXL xl = riscv_cpu_mxl(env);
+
+    /*
+     * When emulating a 32-bit-only cpu, use RV32.
+     * When emulating a 64-bit cpu, and MXL has been reduced to RV32,
+     * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened
+     * back to RV64 for lower privs.
+     */
+    if (xl != MXL_RV32) {
+        switch (env->priv) {
+        case PRV_M:
+            break;
+        case PRV_U:
+            xl = get_field(env->mstatus, MSTATUS64_UXL);
+            break;
+        default: /* PRV_S | PRV_H */
+            xl = get_field(env->mstatus, MSTATUS64_SXL);
+            break;
+        }
+    }
+    return xl;
+#endif
+}
+
 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags)
 {
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     }
 #endif
 
+    flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
+
     *pflags = flags;
 }
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
         mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
     } else {
         mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+        /* SXL and UXL fields are for now read only */
+        mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
+        mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
     }
     env->mstatus = mstatus;
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
 #else
     ctx->virt_enabled = false;
 #endif
-    ctx->xl = env->misa_mxl;
     ctx->misa_ext = env->misa_ext;
     ctx->frm = -1;  /* unknown rounding mode */
     ctx->ext_ifencei = cpu->cfg.ext_ifencei;
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
     ctx->mlen = 1 << (ctx->sew  + 3 - ctx->lmul);
     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
+    ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
     ctx->cs = cs;
     ctx->w = false;
     ctx->ntemp = 0;
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Use the same REQUIRE_64BIT check that we use elsewhere,
rather than open-coding the use of is_32bit.

From: Richard Henderson <richard.henderson@linaro.org>

We're currently assuming SEW <= 3, and the "else" from
the SEW == 3 must be less.  Use a switch and explicitly
bound both SEW and SEQ for all cases.

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
         gen_helper_exit_atomic(cpu_env);
         s->base.is_jmp = DISAS_NORETURN;
         return true;
-    } else {
-        if (s->sew == 3) {
-            if (!is_32bit(s)) {
-                fn = fnsd[seq];
-            } else {
-                /* Check done in amo_check(). */
-                g_assert_not_reached();
-            }
-        } else {
-            assert(seq < ARRAY_SIZE(fnsw));
-            fn = fnsw[seq];
-        }
+    }
+
+    switch (s->sew) {
+    case 0 ... 2:
+        assert(seq < ARRAY_SIZE(fnsw));
+        fn = fnsw[seq];
+        break;
+    case 3:
+        /* XLEN check done in amo_check(). */
+        assert(seq < ARRAY_SIZE(fnsd));
+        fn = fnsd[seq];
+        break;
+    default:
+        g_assert_not_reached();
     }
 
     data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for RV128, replace a simple predicate
with a more versatile test.

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
 }
 
 #ifdef TARGET_RISCV32
-# define is_32bit(ctx)  true
+#define get_xl(ctx)    MXL_RV32
 #elif defined(CONFIG_USER_ONLY)
-# define is_32bit(ctx)  false
+#define get_xl(ctx)    MXL_RV64
 #else
-static inline bool is_32bit(DisasContext *ctx)
+#define get_xl(ctx)    ((ctx)->xl)
+#endif
+
+/* The word size for this machine mode. */
+static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
 {
-    return ctx->xl == MXL_RV32;
+    return 16 << get_xl(ctx);
 }
-#endif
 
 /* The word size for this operation. */
 static inline int oper_len(DisasContext *ctx)
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 static void mark_fs_dirty(DisasContext *ctx)
 {
     TCGv tmp;
-    target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+    target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
 
     if (ctx->mstatus_fs != MSTATUS_FS) {
         /* Remember the state change for the rest of the TB. */
@@ -XXX,XX +XXX,XX @@ EX_SH(12)
     }                              \
 } while (0)
 
-#define REQUIRE_32BIT(ctx) do { \
-    if (!is_32bit(ctx)) {       \
-        return false;           \
-    }                           \
+#define REQUIRE_32BIT(ctx) do {    \
+    if (get_xl(ctx) != MXL_RV32) { \
+        return false;              \
+    }                              \
 } while (0)
 
-#define REQUIRE_64BIT(ctx) do { \
-    if (is_32bit(ctx)) {        \
-        return false;           \
-    }                           \
+#define REQUIRE_64BIT(ctx) do {    \
+    if (get_xl(ctx) < MXL_RV64) {  \
+        return false;              \
+    }                              \
 } while (0)
 
 static int ex_rvc_register(DisasContext *ctx, int reg)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

In preparation for RV128, consider more than just "w" for
operand size modification.  This will be used for the "d"
insns from RV128 as well.

Rename oper_len to get_olen to better match get_xlen.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-10-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 69 ++++++++++++++++---------
 target/riscv/insn_trans/trans_rvb.c.inc |  8 +--
 target/riscv/insn_trans/trans_rvi.c.inc | 18 +++----
 target/riscv/insn_trans/trans_rvm.c.inc | 10 ++--
 4 files changed, 62 insertions(+), 43 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
        to any system register, which includes CSR_FRM, so we do not have
        to reset this known value.  */
     int frm;
-    bool w;
+    RISCVMXL ol;
     bool virt_enabled;
     bool ext_ifencei;
     bool hlsx;
@@ -XXX,XX +XXX,XX @@ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
     return 16 << get_xl(ctx);
 }
 
-/* The word size for this operation. */
-static inline int oper_len(DisasContext *ctx)
+/* The operation length, as opposed to the xlen. */
+#ifdef TARGET_RISCV32
+#define get_ol(ctx)    MXL_RV32
+#else
+#define get_ol(ctx)    ((ctx)->ol)
+#endif
+
+static inline int get_olen(DisasContext *ctx)
 {
-    return ctx->w ? 32 : TARGET_LONG_BITS;
+    return 16 << get_ol(ctx);
 }
 
-
 /*
  * RISC-V requires NaN-boxing of narrower width floating point values.
  * This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -XXX,XX +XXX,XX @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
         return ctx->zero;
     }
 
-    switch (ctx->w ? ext : EXT_NONE) {
-    case EXT_NONE:
-        return cpu_gpr[reg_num];
-    case EXT_SIGN:
-        t = temp_new(ctx);
-        tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
-        return t;
-    case EXT_ZERO:
-        t = temp_new(ctx);
-        tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
-        return t;
+    switch (get_ol(ctx)) {
+    case MXL_RV32:
+        switch (ext) {
+        case EXT_NONE:
+            break;
+        case EXT_SIGN:
+            t = temp_new(ctx);
+            tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
+            return t;
+        case EXT_ZERO:
+            t = temp_new(ctx);
+            tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
+            return t;
+        default:
+            g_assert_not_reached();
+        }
+        break;
+    case MXL_RV64:
+        break;
+    default:
+        g_assert_not_reached();
     }
-    g_assert_not_reached();
+    return cpu_gpr[reg_num];
 }
 
 static TCGv dest_gpr(DisasContext *ctx, int reg_num)
 {
-    if (reg_num == 0 || ctx->w) {
+    if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
         return temp_new(ctx);
     }
     return cpu_gpr[reg_num];
@@ -XXX,XX +XXX,XX @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
 {
     if (reg_num != 0) {
-        if (ctx->w) {
+        switch (get_ol(ctx)) {
+        case MXL_RV32:
             tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
-        } else {
+            break;
+        case MXL_RV64:
             tcg_gen_mov_tl(cpu_gpr[reg_num], t);
+            break;
+        default:
+            g_assert_not_reached();
         }
     }
 }
@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                              void (*func)(TCGv, TCGv, target_long))
 {
     TCGv dest, src1;
-    int max_len = oper_len(ctx);
+    int max_len = get_olen(ctx);
 
     if (a->shamt >= max_len) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                              void (*func)(TCGv, TCGv, TCGv))
 {
     TCGv dest, src1, src2;
-    int max_len = oper_len(ctx);
+    int max_len = get_olen(ctx);
 
     if (a->shamt >= max_len) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
     TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
     TCGv ext2 = tcg_temp_new();
 
-    tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
+    tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);
     func(dest, src1, ext2);
 
     gen_set_gpr(ctx, a->rd, dest);
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
     ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
     ctx->cs = cs;
-    ctx->w = false;
     ctx->ntemp = 0;
     memset(ctx->temp, 0, sizeof(ctx->temp));
 
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     CPURISCVState *env = cpu->env_ptr;
     uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
 
+    ctx->ol = ctx->xl;
     decode_opc(env, ctx, opcode16);
     ctx->base.pc_next = ctx->pc_succ_insn;
-    ctx->w = false;
 
     for (int i = ctx->ntemp - 1; i >= 0; --i) {
         tcg_temp_free(ctx->temp[i]);
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_NONE, gen_rorw);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_NONE, gen_rolw);
 }
 
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_and(DisasContext *ctx, arg_and *a)
 static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
 }
 
 static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
 }
 
@@ -XXX,XX +XXX,XX @@ static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
 }
 
 static bool trans_addw(DisasContext *ctx, arg_addw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
 }
 
 static bool trans_subw(DisasContext *ctx, arg_subw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
 }
 
 static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
 }
 
 static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
 }
 
 static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
 {
     REQUIRE_64BIT(ctx);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
 }
 
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_SIGN, gen_div);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_ZERO, gen_divu);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_SIGN, gen_rem);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_EXT(ctx, RVM);
-    ctx->w = true;
+    ctx->ol = MXL_RV32;
     return gen_arith(ctx, a, EXT_ZERO, gen_remu);
 }
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

The multiply high-part instructions require a separate
implementation for RV32 when TARGET_LONG_BITS == 64.

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
     return true;
 }
 
+static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
+                             void (*f_tl)(TCGv, TCGv, TCGv),
+                             void (*f_32)(TCGv, TCGv, TCGv))
+{
+    int olen = get_olen(ctx);
+
+    if (olen != TARGET_LONG_BITS) {
+        if (olen == 32) {
+            f_tl = f_32;
+        } else {
+            g_assert_not_reached();
+        }
+    }
+    return gen_arith(ctx, a, ext, f_tl);
+}
+
 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                              void (*func)(TCGv, TCGv, target_long))
 {
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -XXX,XX +XXX,XX @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
     tcg_temp_free(discard);
 }
 
+static void gen_mulh_w(TCGv ret, TCGv s1, TCGv s2)
+{
+    tcg_gen_mul_tl(ret, s1, s2);
+    tcg_gen_sari_tl(ret, ret, 32);
+}
+
 static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, EXT_NONE, gen_mulh);
+    return gen_arith_per_ol(ctx, a, EXT_SIGN, gen_mulh, gen_mulh_w);
 }
 
 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
@@ -XXX,XX +XXX,XX @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
     tcg_temp_free(rh);
 }
 
+static void gen_mulhsu_w(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv t1 = tcg_temp_new();
+    TCGv t2 = tcg_temp_new();
+
+    tcg_gen_ext32s_tl(t1, arg1);
+    tcg_gen_ext32u_tl(t2, arg2);
+    tcg_gen_mul_tl(ret, t1, t2);
+    tcg_temp_free(t1);
+    tcg_temp_free(t2);
+    tcg_gen_sari_tl(ret, ret, 32);
+}
+
 static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
+    return gen_arith_per_ol(ctx, a, EXT_NONE, gen_mulhsu, gen_mulhsu_w);
 }
 
 static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
@@ -XXX,XX +XXX,XX @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
 static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
 {
     REQUIRE_EXT(ctx, RVM);
-    return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
+    /* gen_mulh_w works for either sign as input. */
+    return gen_arith_per_ol(ctx, a, EXT_ZERO, gen_mulhu, gen_mulh_w);
 }
 
 static void gen_div(TCGv ret, TCGv source1, TCGv source2)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-12-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

From: Richard Henderson <richard.henderson@linaro.org>

The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
     return true;
 }
 
+static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+                             void (*f_tl)(TCGv, TCGv),
+                             void (*f_32)(TCGv, TCGv))
+{
+    int olen = get_olen(ctx);
+
+    if (olen != TARGET_LONG_BITS) {
+        if (olen == 32) {
+            f_tl = f_32;
+        } else {
+            g_assert_not_reached();
+        }
+    }
+    return gen_unary(ctx, a, ext, f_tl);
+}
+
 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static void gen_clz(TCGv ret, TCGv arg1)
     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
 }
 
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+    TCGv t = tcg_temp_new();
+    tcg_gen_shli_tl(t, arg1, 32);
+    tcg_gen_clzi_tl(ret, t, 32);
+    tcg_temp_free(t);
+}
+
 static bool trans_clz(DisasContext *ctx, arg_clz *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
+    return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
 }
 
 static void gen_ctz(TCGv ret, TCGv arg1)
@@ -XXX,XX +XXX,XX @@ static void gen_ctz(TCGv ret, TCGv arg1)
     tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
 }
 
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ctzi_tl(ret, arg1, 32);
+}
+
 static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
+    return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
 }
 
 static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
     return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
 }
 
-static void gen_clzw(TCGv ret, TCGv arg1)
-{
-    TCGv t = tcg_temp_new();
-    tcg_gen_shli_tl(t, arg1, 32);
-    tcg_gen_clzi_tl(ret, t, 32);
-    tcg_temp_free(t);
-}
-
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
     return gen_unary(ctx, a, EXT_NONE, gen_clzw);
 }
 
-static void gen_ctzw(TCGv ret, TCGv arg1)
-{
-    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-    tcg_gen_ctzi_tl(ret, ret, 64);
-}
-
 static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
+    return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
 }
 
 static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Most shift instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-14-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c                | 31 +++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 92 ++++++++++++++-----------
 target/riscv/insn_trans/trans_rvi.c.inc | 26 +++----
 3 files changed, 97 insertions(+), 52 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
     return true;
 }
 
+static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a,
+                                    DisasExtend ext,
+                                    void (*f_tl)(TCGv, TCGv, target_long),
+                                    void (*f_32)(TCGv, TCGv, target_long))
+{
+    int olen = get_olen(ctx);
+    if (olen != TARGET_LONG_BITS) {
+        if (olen == 32) {
+            f_tl = f_32;
+        } else {
+            g_assert_not_reached();
+        }
+    }
+    return gen_shift_imm_fn(ctx, a, ext, f_tl);
+}
+
 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
                              void (*func)(TCGv, TCGv, TCGv))
 {
@@ -XXX,XX +XXX,XX @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
     return true;
 }
 
+static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
+                             void (*f_tl)(TCGv, TCGv, TCGv),
+                             void (*f_32)(TCGv, TCGv, TCGv))
+{
+    int olen = get_olen(ctx);
+    if (olen != TARGET_LONG_BITS) {
+        if (olen == 32) {
+            f_tl = f_32;
+        } else {
+            g_assert_not_reached();
+        }
+    }
+    return gen_shift(ctx, a, ext, f_tl);
+}
+
 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
                       void (*func)(TCGv, TCGv))
 {
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
 }
 
+static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv_i32 t1 = tcg_temp_new_i32();
+    TCGv_i32 t2 = tcg_temp_new_i32();
+
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_trunc_tl_i32(t2, arg2);
+
+    tcg_gen_rotr_i32(t1, t1, t2);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
+}
+
 static bool trans_ror(DisasContext *ctx, arg_ror *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
+    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw);
+}
+
+static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
+{
+    TCGv_i32 t1 = tcg_temp_new_i32();
+
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_rotri_i32(t1, t1, shamt);
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free_i32(t1);
 }
 
 static bool trans_rori(DisasContext *ctx, arg_rori *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
+    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
+                                   tcg_gen_rotri_tl, gen_roriw);
+}
+
+static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv_i32 t1 = tcg_temp_new_i32();
+    TCGv_i32 t2 = tcg_temp_new_i32();
+
+    /* truncate to 32-bits */
+    tcg_gen_trunc_tl_i32(t1, arg1);
+    tcg_gen_trunc_tl_i32(t2, arg2);
+
+    tcg_gen_rotl_i32(t1, t1, t2);
+
+    /* sign-extend 64-bits */
+    tcg_gen_ext_i32_tl(ret, t1);
+
+    tcg_temp_free_i32(t1);
+    tcg_temp_free_i32(t2);
 }
 
 static bool trans_rol(DisasContext *ctx, arg_rol *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
+    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw);
 }
 
 static void gen_rev8_32(TCGv ret, TCGv src1)
@@ -XXX,XX +XXX,XX @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
     return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
 }
 
-static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv_i32 t1 = tcg_temp_new_i32();
-    TCGv_i32 t2 = tcg_temp_new_i32();
-
-    /* truncate to 32-bits */
-    tcg_gen_trunc_tl_i32(t1, arg1);
-    tcg_gen_trunc_tl_i32(t2, arg2);
-
-    tcg_gen_rotr_i32(t1, t1, t2);
-
-    /* sign-extend 64-bits */
-    tcg_gen_ext_i32_tl(ret, t1);
-
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
-}
-
 static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
     ctx->ol = MXL_RV32;
-    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
-}
-
-static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
-{
-    TCGv_i32 t1 = tcg_temp_new_i32();
-    TCGv_i32 t2 = tcg_temp_new_i32();
-
-    /* truncate to 32-bits */
-    tcg_gen_trunc_tl_i32(t1, arg1);
-    tcg_gen_trunc_tl_i32(t2, arg2);
-
-    tcg_gen_rotl_i32(t1, t1, t2);
-
-    /* sign-extend 64-bits */
-    tcg_gen_ext_i32_tl(ret, t1);
-
-    tcg_temp_free_i32(t1);
-    tcg_temp_free_i32(t2);
+    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw);
 }
 
 static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_slli(DisasContext *ctx, arg_slli *a)
     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
 }
 
+static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
+{
+    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
+}
+
 static bool trans_srli(DisasContext *ctx, arg_srli *a)
 {
-    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
+    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
+                                   tcg_gen_shri_tl, gen_srliw);
+}
+
+static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
+{
+    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
 }
 
 static bool trans_srai(DisasContext *ctx, arg_srai *a)
 {
-    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
+    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
+                                   tcg_gen_sari_tl, gen_sraiw);
 }
 
 static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -XXX,XX +XXX,XX @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
     return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
 }
 
-static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
-{
-    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
-}
-
 static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -XXX,XX +XXX,XX @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
 }
 
-static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
-{
-    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
-}
-
 static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
 {
     REQUIRE_64BIT(ctx);
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

Use the official debug read interface to the csrs,
rather than referencing the env slots directly.
Put the list of csrs to dump into a table.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-15-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
 1 file changed, 45 insertions(+), 44 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 #endif
     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
 #ifndef CONFIG_USER_ONLY
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus);
-    if (riscv_cpu_mxl(env) == MXL_RV32) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ",
-                     (target_ulong)(env->mstatus >> 32));
-    }
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus",
-                     (target_ulong)env->vsstatus);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
-    }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval   ", env->mtval);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval   ", env->stval);
-    if (riscv_has_ext(env, RVH)) {
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval   ", env->htval);
-        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2  ", env->mtval2);
+    {
+        static const int dump_csrs[] = {
+            CSR_MHARTID,
+            CSR_MSTATUS,
+            CSR_MSTATUSH,
+            CSR_HSTATUS,
+            CSR_VSSTATUS,
+            CSR_MIP,
+            CSR_MIE,
+            CSR_MIDELEG,
+            CSR_HIDELEG,
+            CSR_MEDELEG,
+            CSR_HEDELEG,
+            CSR_MTVEC,
+            CSR_STVEC,
+            CSR_VSTVEC,
+            CSR_MEPC,
+            CSR_SEPC,
+            CSR_VSEPC,
+            CSR_MCAUSE,
+            CSR_SCAUSE,
+            CSR_VSCAUSE,
+            CSR_MTVAL,
+            CSR_STVAL,
+            CSR_HTVAL,
+            CSR_MTVAL2,
+            CSR_MSCRATCH,
+            CSR_SSCRATCH,
+            CSR_SATP,
+        };
+
+        for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
+            int csrno = dump_csrs[i];
+            target_ulong val = 0;
+            RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
+
+            /*
+             * Rely on the smode, hmode, etc, predicates within csr.c
+             * to do the filtering of the registers that are present.
+             */
+            if (res == RISCV_EXCP_NONE) {
+                qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+                             csr_ops[csrno].name, val);
+            }
+        }
     }
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch);
-    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp    ", env->satp);
 #endif
 
     for (i = 0; i < 32; i++) {
-- 
2.31.1

From: Richard Henderson <richard.henderson@linaro.org>

The position of this read-only field is dependent on the current xlen.
Rather than having to compute that difference in many places, compute
it only on read.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-16-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c |  3 +--
 target/riscv/csr.c        | 37 ++++++++++++++++++++++---------------
 target/riscv/translate.c  |  5 ++---
 3 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_fp_enabled(CPURISCVState *env)
 
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
 {
-    uint64_t sd = riscv_cpu_mxl(env) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
     uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
                             MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
-                            MSTATUS64_UXL | sd;
+                            MSTATUS64_UXL;
     bool current_virt = riscv_cpu_virt_enabled(env);
 
     g_assert(riscv_has_ext(env, RVH));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno,
 }
 
 /* Machine Trap Setup */
+
+/* We do not store SD explicitly, only compute it on demand. */
+static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
+{
+    if ((status & MSTATUS_FS) == MSTATUS_FS ||
+        (status & MSTATUS_XS) == MSTATUS_XS) {
+        switch (xl) {
+        case MXL_RV32:
+            return status | MSTATUS32_SD;
+        case MXL_RV64:
+            return status | MSTATUS64_SD;
+        default:
+            g_assert_not_reached();
+        }
+    }
+    return status;
+}
+
 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
-    *val = env->mstatus;
+    *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
     return RISCV_EXCP_NONE;
 }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 {
     uint64_t mstatus = env->mstatus;
     uint64_t mask = 0;
-    int dirty;
 
     /* flush tlb on mstatus fields that affect VM */
     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
@@ -XXX,XX +XXX,XX @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 
     mstatus = (mstatus & ~mask) | (val & mask);
 
-    dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
-            ((mstatus & MSTATUS_XS) == MSTATUS_XS);
-    if (riscv_cpu_mxl(env) == MXL_RV32) {
-        mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
-    } else {
-        mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+    if (riscv_cpu_mxl(env) == MXL_RV64) {
         /* SXL and UXL fields are for now read only */
         mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
         mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
@@ -XXX,XX +XXX,XX @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
 {
     target_ulong mask = (sstatus_v1_10_mask);
 
-    if (riscv_cpu_mxl(env) == MXL_RV32) {
-        mask |= SSTATUS32_SD;
-    } else {
-        mask |= SSTATUS64_SD;
-    }
-
-    *val = env->mstatus & mask;
+    /* TODO: Use SXL not MXL. */
+    *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
     return RISCV_EXCP_NONE;
 }
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
 static void mark_fs_dirty(DisasContext *ctx)
 {
     TCGv tmp;
-    target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
 
     if (ctx->mstatus_fs != MSTATUS_FS) {
         /* Remember the state change for the rest of the TB. */
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 
         tmp = tcg_temp_new();
         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
         tcg_temp_free(tmp);
     }
@@ -XXX,XX +XXX,XX @@ static void mark_fs_dirty(DisasContext *ctx)
 
         tmp = tcg_temp_new();
         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
+        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
         tcg_temp_free(tmp);
     }
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
---
 include/hw/riscv/opentitan.h |  6 +++---
 hw/riscv/opentitan.c         | 22 +++++++++++++++++-----
 2 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -XXX,XX +XXX,XX @@
 #define HW_OPENTITAN_H
 
 #include "hw/riscv/riscv_hart.h"
-#include "hw/intc/ibex_plic.h"
+#include "hw/intc/sifive_plic.h"
 #include "hw/char/ibex_uart.h"
 #include "hw/timer/ibex_timer.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct LowRISCIbexSoCState {
 
     /*< public >*/
     RISCVHartArrayState cpus;
-    IbexPlicState plic;
+    SiFivePLICState plic;
     IbexUartState uart;
     IbexTimerState timer;
 
@@ -XXX,XX +XXX,XX @@ enum {
 };
 
 enum {
-    IBEX_TIMER_TIMEREXPIRED0_0 = 125,
+    IBEX_TIMER_TIMEREXPIRED0_0 = 126,
     IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
     IBEX_UART0_RX_TIMEOUT_IRQ = 7,
     IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
     [IBEX_DEV_PINMUX] =         {  0x40460000,  0x1000  },
     [IBEX_DEV_PADCTRL] =        {  0x40470000,  0x1000  },
     [IBEX_DEV_FLASH_CTRL] =     {  0x41000000,  0x1000  },
-    [IBEX_DEV_PLIC] =           {  0x41010000,  0x1000  },
     [IBEX_DEV_AES] =            {  0x41100000,  0x1000  },
     [IBEX_DEV_HMAC] =           {  0x41110000,  0x1000  },
     [IBEX_DEV_KMAC] =           {  0x41120000,  0x1000  },
-    [IBEX_DEV_KEYMGR] =         {  0x41130000,  0x1000  },
+    [IBEX_DEV_OTBN] =           {  0x41130000,  0x10000 },
+    [IBEX_DEV_KEYMGR] =         {  0x41140000,  0x1000  },
     [IBEX_DEV_CSRNG] =          {  0x41150000,  0x1000  },
     [IBEX_DEV_ENTROPY] =        {  0x41160000,  0x1000  },
     [IBEX_DEV_EDNO] =           {  0x41170000,  0x1000  },
     [IBEX_DEV_EDN1] =           {  0x41180000,  0x1000  },
     [IBEX_DEV_ALERT_HANDLER] =  {  0x411b0000,  0x1000  },
     [IBEX_DEV_NMI_GEN] =        {  0x411c0000,  0x1000  },
-    [IBEX_DEV_OTBN] =           {  0x411d0000,  0x10000 },
     [IBEX_DEV_PERI] =           {  0x411f0000,  0x10000 },
+    [IBEX_DEV_PLIC] =           {  0x48000000,  0x4005000  },
     [IBEX_DEV_FLASH_VIRTUAL] =  {  0x80000000,  0x80000 },
 };
 
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_init(Object *obj)
 
     object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
 
-    object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
+    object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
 
     object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
 
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                                 &s->flash_alias);
 
     /* PLIC */
+    qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
+    qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 0x18);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200004);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 4);
+    qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
+
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
     for (i = 0; i < ms->smp.cpus; i++) {
         CPUState *cpu = qemu_get_cpu(i);
 
-        qdev_connect_gpio_out(DEVICE(&s->plic), i,
+        qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
                               qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
     }
 
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and
instead use the SiFive PLIC.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
---
 hw/intc/ibex_plic.c | 307 --------------------------------------------
 hw/intc/meson.build |   1 -
 2 files changed, 308 deletions(-)
 delete mode 100644 hw/intc/ibex_plic.c

diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
deleted file mode 100644
index XXXXXXX..XXXXXXX
--- a/hw/intc/ibex_plic.c
+++ /dev/null
@@ -XXX,XX +XXX,XX @@
-/*
- * QEMU RISC-V lowRISC Ibex PLIC
- *
- * Copyright (c) 2020 Western Digital
- *
- * Documentation avaliable: https://docs.opentitan.org/hw/ip/rv_plic/doc/
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "qemu/log.h"
-#include "hw/qdev-properties.h"
-#include "hw/core/cpu.h"
-#include "hw/boards.h"
-#include "hw/pci/msi.h"
-#include "target/riscv/cpu_bits.h"
-#include "target/riscv/cpu.h"
-#include "hw/intc/ibex_plic.h"
-#include "hw/irq.h"
-
-static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
-{
-    uint32_t end = base + (num * 0x04);
-
-    if (addr >= base && addr < end) {
-        return true;
-    }
-
-    return false;
-}
-
-static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
-{
-    int pending_num = irq / 32;
-
-    if (!level) {
-        /*
-         * If the level is low make sure we clear the hidden_pending.
-         */
-        s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
-    }
-
-    if (s->claimed[pending_num] & 1 << (irq % 32)) {
-        /*
-         * The interrupt has been claimed, but not completed.
-         * The pending bit can't be set.
-         * Save the pending level for after the interrupt is completed.
-         */
-        s->hidden_pending[pending_num] |= level << (irq % 32);
-    } else {
-        s->pending[pending_num] |= level << (irq % 32);
-    }
-}
-
-static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
-{
-    int i;
-    uint32_t max_irq = 0;
-    uint32_t max_prio = s->threshold;
-
-    for (i = 0; i < s->pending_num; i++) {
-        uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
-
-        if (!(s->pending[i] & s->enable[i])) {
-            /* No pending and enabled IRQ */
-            continue;
-        }
-
-        if (s->priority[irq_num] > max_prio) {
-            max_irq = irq_num;
-            max_prio = s->priority[irq_num];
-        }
-    }
-
-    if (max_irq) {
-        s->claim = max_irq;
-        return true;
-    }
-
-    return false;
-}
-
-static void ibex_plic_update(IbexPlicState *s)
-{
-    int i;
-
-    for (i = 0; i < s->num_cpus; i++) {
-        qemu_set_irq(s->external_irqs[i], ibex_plic_irqs_pending(s, 0));
-    }
-}
-
-static void ibex_plic_reset(DeviceState *dev)
-{
-    IbexPlicState *s = IBEX_PLIC(dev);
-
-    s->threshold = 0x00000000;
-    s->claim = 0x00000000;
-}
-
-static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
-                               unsigned int size)
-{
-    IbexPlicState *s = opaque;
-    int offset;
-    uint32_t ret = 0;
-
-    if (addr_between(addr, s->pending_base, s->pending_num)) {
-        offset = (addr - s->pending_base) / 4;
-        ret = s->pending[offset];
-    } else if (addr_between(addr, s->source_base, s->source_num)) {
-        qemu_log_mask(LOG_UNIMP,
-                      "%s: Interrupt source mode not supported\n", __func__);
-    } else if (addr_between(addr, s->priority_base, s->priority_num)) {
-        offset = (addr - s->priority_base) / 4;
-        ret = s->priority[offset];
-    } else if (addr_between(addr, s->enable_base, s->enable_num)) {
-        offset = (addr - s->enable_base) / 4;
-        ret = s->enable[offset];
-    } else if (addr_between(addr, s->threshold_base, 1)) {
-        ret = s->threshold;
-    } else if (addr_between(addr, s->claim_base, 1)) {
-        int pending_num = s->claim / 32;
-        s->pending[pending_num] &= ~(1 << (s->claim % 32));
-
-        /* Set the interrupt as claimed, but not completed */
-        s->claimed[pending_num] |= 1 << (s->claim % 32);
-
-        /* Return the current claimed interrupt */
-        ret = s->claim;
-
-        /* Clear the claimed interrupt */
-        s->claim = 0x00000000;
-
-        /* Update the interrupt status after the claim */
-        ibex_plic_update(s);
-    }
-
-    return ret;
-}
-
-static void ibex_plic_write(void *opaque, hwaddr addr,
-                            uint64_t value, unsigned int size)
-{
-    IbexPlicState *s = opaque;
-
-    if (addr_between(addr, s->pending_base, s->pending_num)) {
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: Pending registers are read only\n", __func__);
-    } else if (addr_between(addr, s->source_base, s->source_num)) {
-        qemu_log_mask(LOG_UNIMP,
-                      "%s: Interrupt source mode not supported\n", __func__);
-    } else if (addr_between(addr, s->priority_base, s->priority_num)) {
-        uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
-        s->priority[irq] = value & 7;
-        ibex_plic_update(s);
-    } else if (addr_between(addr, s->enable_base, s->enable_num)) {
-        uint32_t enable_reg = (addr - s->enable_base) / 4;
-
-        s->enable[enable_reg] = value;
-    } else if (addr_between(addr, s->threshold_base, 1)) {
-        s->threshold = value & 3;
-    } else if (addr_between(addr, s->claim_base, 1)) {
-        if (s->claim == value) {
-            /* Interrupt was completed */
-            s->claim = 0;
-        }
-        if (s->claimed[value / 32] & 1 << (value % 32)) {
-            int pending_num = value / 32;
-
-            /* This value was already claimed, clear it. */
-            s->claimed[pending_num] &= ~(1 << (value % 32));
-
-            if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
-                /*
-                 * If the bit in hidden_pending is set then that means we
-                 * received an interrupt between claiming and completing
-                 * the interrupt that hasn't since been de-asserted.
-                 * On hardware this would trigger an interrupt, so let's
-                 * trigger one here as well.
-                 */
-                s->pending[pending_num] |= 1 << (value % 32);
-            }
-        }
-    }
-
-    ibex_plic_update(s);
-}
-
-static const MemoryRegionOps ibex_plic_ops = {
-    .read = ibex_plic_read,
-    .write = ibex_plic_write,
-    .endianness = DEVICE_NATIVE_ENDIAN,
-    .valid = {
-        .min_access_size = 4,
-        .max_access_size = 4
-    }
-};
-
-static void ibex_plic_irq_request(void *opaque, int irq, int level)
-{
-    IbexPlicState *s = opaque;
-
-    ibex_plic_irqs_set_pending(s, irq, level > 0);
-    ibex_plic_update(s);
-}
-
-static Property ibex_plic_properties[] = {
-    DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
-    DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
-
-    DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
-    DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
-
-    DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
-    DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
-
-    DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
-    DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
-
-    DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
-    DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
-
-    DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
-
-    DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
-static void ibex_plic_init(Object *obj)
-{
-    IbexPlicState *s = IBEX_PLIC(obj);
-
-    memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
-                          TYPE_IBEX_PLIC, 0x400);
-    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
-}
-
-static void ibex_plic_realize(DeviceState *dev, Error **errp)
-{
-    IbexPlicState *s = IBEX_PLIC(dev);
-    int i;
-
-    s->pending = g_new0(uint32_t, s->pending_num);
-    s->hidden_pending = g_new0(uint32_t, s->pending_num);
-    s->claimed = g_new0(uint32_t, s->pending_num);
-    s->source = g_new0(uint32_t, s->source_num);
-    s->priority = g_new0(uint32_t, s->priority_num);
-    s->enable = g_new0(uint32_t, s->enable_num);
-
-    qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
-
-    s->external_irqs = g_malloc(sizeof(qemu_irq) * s->num_cpus);
-    qdev_init_gpio_out(dev, s->external_irqs, s->num_cpus);
-
-    /*
-     * We can't allow the supervisor to control SEIP as this would allow the
-     * supervisor to clear a pending external interrupt which will result in
-     * a lost interrupt in the case a PLIC is attached. The SEIP bit must be
-     * hardware controlled when a PLIC is attached.
-     */
-    MachineState *ms = MACHINE(qdev_get_machine());
-    unsigned int smp_cpus = ms->smp.cpus;
-    for (i = 0; i < smp_cpus; i++) {
-        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
-        if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
-            error_report("SEIP already claimed");
-            exit(1);
-        }
-    }
-
-    msi_nonbroken = true;
-}
-
-static void ibex_plic_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-
-    dc->reset = ibex_plic_reset;
-    device_class_set_props(dc, ibex_plic_properties);
-    dc->realize = ibex_plic_realize;
-}
-
-static const TypeInfo ibex_plic_info = {
-    .name          = TYPE_IBEX_PLIC,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(IbexPlicState),
-    .instance_init = ibex_plic_init,
-    .class_init    = ibex_plic_class_init,
-};
-
-static void ibex_plic_register_types(void)
-{
-    type_register_static(&ibex_plic_info);
-}
-
-type_init(ibex_plic_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -XXX,XX +XXX,XX @@ specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
 specific_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_vic.c'))
 specific_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210_gic.c', 'exynos4210_combiner.c'))
 specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))
-specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_plic.c'))
 specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))
 specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_liointc.c'))
 specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c'))
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alistair.francis@wdc.com
---
 hw/intc/sifive_plic.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_plic_ops = {
     }
 };
 
-static Property sifive_plic_properties[] = {
-    DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
-    DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
-    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
-    DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
-    DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
-    DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
-    DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
-    DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
-    DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
-    DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
-    DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
 /*
  * parse PLIC hart/mode address offset config
  *
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_sifive_plic = {
         }
 };
 
+static Property sifive_plic_properties[] = {
+    DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
+    DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
+    DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
+    DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
+    DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
+    DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
+    DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
+    DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
+    DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
+    DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
+    DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
 static void sifive_plic_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
---
 hw/intc/sifive_plic.c | 45 +++++++++++++++++++++++--------------------
 1 file changed, 24 insertions(+), 21 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
 
 static void sifive_plic_realize(DeviceState *dev, Error **errp)
 {
-    SiFivePLICState *plic = SIFIVE_PLIC(dev);
+    SiFivePLICState *s = SIFIVE_PLIC(dev);
     int i;
 
-    memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
-                          TYPE_SIFIVE_PLIC, plic->aperture_size);
-    parse_hart_config(plic);
-    plic->bitfield_words = (plic->num_sources + 31) >> 5;
-    plic->num_enables = plic->bitfield_words * plic->num_addrs;
-    plic->source_priority = g_new0(uint32_t, plic->num_sources);
-    plic->target_priority = g_new(uint32_t, plic->num_addrs);
-    plic->pending = g_new0(uint32_t, plic->bitfield_words);
-    plic->claimed = g_new0(uint32_t, plic->bitfield_words);
-    plic->enable = g_new0(uint32_t, plic->num_enables);
-    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
-    qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
-
-    plic->s_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
-    qdev_init_gpio_out(dev, plic->s_external_irqs, plic->num_harts);
-
-    plic->m_external_irqs = g_malloc(sizeof(qemu_irq) * plic->num_harts);
-    qdev_init_gpio_out(dev, plic->m_external_irqs, plic->num_harts);
+    memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s,
+                          TYPE_SIFIVE_PLIC, s->aperture_size);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+
+    parse_hart_config(s);
+
+    s->bitfield_words = (s->num_sources + 31) >> 5;
+    s->num_enables = s->bitfield_words * s->num_addrs;
+    s->source_priority = g_new0(uint32_t, s->num_sources);
+    s->target_priority = g_new(uint32_t, s->num_addrs);
+    s->pending = g_new0(uint32_t, s->bitfield_words);
+    s->claimed = g_new0(uint32_t, s->bitfield_words);
+    s->enable = g_new0(uint32_t, s->num_enables);
+
+    qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources);
+
+    s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
+    qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts);
+
+    s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
+    qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
 
     /* We can't allow the supervisor to control SEIP as this would allow the
      * supervisor to clear a pending external interrupt which will result in
      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
      * hardware controlled when a PLIC is attached.
      */
-    for (i = 0; i < plic->num_harts; i++) {
-        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
+    for (i = 0; i < s->num_harts; i++) {
+        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
             error_report("SEIP already claimed");
             exit(1);
-- 
2.31.1

From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.francis@wdc.com
---
 hw/intc/sifive_plic.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
 
 static void sifive_plic_irq_request(void *opaque, int irq, int level)
 {
-    SiFivePLICState *plic = opaque;
-    if (RISCV_DEBUG_PLIC) {
-        qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
-    }
-    sifive_plic_set_pending(plic, irq, level > 0);
-    sifive_plic_update(plic);
+    SiFivePLICState *s = opaque;
+
+    sifive_plic_set_pending(s, irq, level > 0);
+    sifive_plic_update(s);
 }
 
 static void sifive_plic_realize(DeviceState *dev, Error **errp)
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/microchip_pfsoc.c | 36 ++++++++++++++++++++----------------
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
     MemoryRegion *mem_high = g_new(MemoryRegion, 1);
     MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
-    uint64_t mem_high_size;
+    uint64_t mem_low_size, mem_high_size;
     hwaddr firmware_load_addr;
     const char *firmware_name;
     bool kernel_as_payload = false;
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
                             TYPE_MICROCHIP_PFSOC);
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
+    /* Split RAM into low and high regions using aliases to machine->ram */
+    mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
+    mem_high_size = machine->ram_size - mem_low_size;
+    memory_region_init_alias(mem_low, NULL,
+                             "microchip.icicle.kit.ram_low", machine->ram,
+                             0, mem_low_size);
+    memory_region_init_alias(mem_high, NULL,
+                             "microchip.icicle.kit.ram_high", machine->ram,
+                             mem_low_size, mem_high_size);
+
     /* Register RAM */
-    memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
-                           memmap[MICROCHIP_PFSOC_DRAM_LO].size,
-                           &error_fatal);
-    memory_region_init_alias(mem_low_alias, NULL,
-                             "microchip.icicle.kit.ram_low.alias",
-                             mem_low, 0,
-                             memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
     memory_region_add_subregion(system_memory,
                                 memmap[MICROCHIP_PFSOC_DRAM_LO].base,
                                 mem_low);
+    memory_region_add_subregion(system_memory,
+                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
+                                mem_high);
+
+    /* Create aliases for the low and high RAM regions */
+    memory_region_init_alias(mem_low_alias, NULL,
+                             "microchip.icicle.kit.ram_low.alias",
+                             mem_low, 0, mem_low_size);
     memory_region_add_subregion(system_memory,
                                 memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
                                 mem_low_alias);
-
-    mem_high_size = machine->ram_size - 1 * GiB;
-
-    memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
-                           mem_high_size, &error_fatal);
     memory_region_init_alias(mem_high_alias, NULL,
                              "microchip.icicle.kit.ram_high.alias",
                              mem_high, 0, mem_high_size);
-    memory_region_add_subregion(system_memory,
-                                memmap[MICROCHIP_PFSOC_DRAM_HI].base,
-                                mem_high);
     memory_region_add_subregion(system_memory,
                                 memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
                                 mem_high_alias);
@@ -XXX,XX +XXX,XX @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
                    MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
     mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
     mc->default_cpus = mc->min_cpus;
+    mc->default_ram_id = "microchip.icicle.kit.ram";
 
     /*
      * Map 513 MiB high memory, the mimimum required high memory size, because
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

While at it add check for user supplied RAM size and error out if it
mismatches board expected value.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/cutils.h"
 #include "hw/riscv/opentitan.h"
 #include "qapi/error.h"
 #include "hw/boards.h"
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry ibex_memmap[] = {
 
 static void opentitan_board_init(MachineState *machine)
 {
+    MachineClass *mc = MACHINE_GET_CLASS(machine);
     const MemMapEntry *memmap = ibex_memmap;
     OpenTitanState *s = g_new0(OpenTitanState, 1);
     MemoryRegion *sys_mem = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+
+    if (machine->ram_size != mc->default_ram_size) {
+        char *sz = size_to_str(mc->default_ram_size);
+        error_report("Invalid RAM size, should be %s", sz);
+        g_free(sz);
+        exit(EXIT_FAILURE);
+    }
 
     /* Initialize SoC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc,
                             TYPE_RISCV_IBEX_SOC);
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
-    memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
-        memmap[IBEX_DEV_RAM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
-        memmap[IBEX_DEV_RAM].base, main_mem);
+        memmap[IBEX_DEV_RAM].base, machine->ram);
 
     if (machine->firmware) {
         riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
@@ -XXX,XX +XXX,XX @@ static void opentitan_machine_init(MachineClass *mc)
     mc->init = opentitan_board_init;
     mc->max_cpus = 1;
     mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
+    mc->default_ram_id = "riscv.lowrisc.ibex.ram";
+    mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
 }
 
 DEFINE_MACHINE("opentitan", opentitan_machine_init)
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-4-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/shakti_c.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_state_init(MachineState *mstate)
 {
     ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 
     /* Allow only Shakti C CPU for this platform */
     if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_state_init(MachineState *mstate)
     qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
 
     /* register RAM */
-    memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
-                           mstate->ram_size, &error_fatal);
     memory_region_add_subregion(system_memory,
                                 shakti_c_memmap[SHAKTI_C_RAM].base,
-                                main_mem);
+                                mstate->ram);
 
     /* ROM reset vector */
     riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
@@ -XXX,XX +XXX,XX @@ static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
     mc->desc = "RISC-V Board compatible with Shakti SDK";
     mc->init = shakti_c_machine_state_init;
     mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
+    mc->default_ram_id = "riscv.shakti.c.ram";
 }
 
 static const TypeInfo shakti_c_machine_type_info = {
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

While at it add check for user supplied RAM size and error out if it
mismatches board expected value.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_e.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/cutils.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
 #include "hw/boards.h"
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry sifive_e_memmap[] = {
 
 static void sifive_e_machine_init(MachineState *machine)
 {
+    MachineClass *mc = MACHINE_GET_CLASS(machine);
     const MemMapEntry *memmap = sifive_e_memmap;
 
     SiFiveEState *s = RISCV_E_MACHINE(machine);
     MemoryRegion *sys_mem = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     int i;
 
+    if (machine->ram_size != mc->default_ram_size) {
+        char *sz = size_to_str(mc->default_ram_size);
+        error_report("Invalid RAM size, should be %s", sz);
+        g_free(sz);
+        exit(EXIT_FAILURE);
+    }
+
     /* Initialize SoC */
     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
     /* Data Tightly Integrated Memory */
-    memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
-        memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
-        memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
+        memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
 
     /* Mask ROM reset vector */
     uint32_t reset_vec[4];
@@ -XXX,XX +XXX,XX @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
     mc->init = sifive_e_machine_init;
     mc->max_cpus = 1;
     mc->default_cpu_type = SIFIVE_E_CPU;
+    mc->default_ram_id = "riscv.sifive.e.ram";
+    mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
 
     object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
                                    sifive_e_machine_set_revb);
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/sifive_u.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     const MemMapEntry *memmap = sifive_u_memmap;
     SiFiveUState *s = RISCV_U_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
     target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
     target_ulong firmware_end_addr, kernel_start_addr;
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_init(MachineState *machine)
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
     /* register RAM */
-    memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
-                           machine->ram_size, &error_fatal);
     memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
-                                main_mem);
+                                machine->ram);
 
     /* register QSPI0 Flash */
     memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
@@ -XXX,XX +XXX,XX @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
     mc->default_cpu_type = SIFIVE_U_CPU;
     mc->default_cpus = mc->min_cpus;
+    mc->default_ram_id = "riscv.sifive.u.ram";
 
     object_class_property_add_bool(oc, "start-in-flash",
                                    sifive_u_machine_get_start_in_flash,
-- 
2.31.1

From: Bin Meng <bmeng.cn@gmail.com>

Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.

Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/spike.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     const MemMapEntry *memmap = spike_memmap;
     SpikeState *s = SPIKE_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
-    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
     target_ulong firmware_end_addr, kernel_start_addr;
     uint32_t fdt_load_addr;
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
     }
 
     /* register system main memory (actual RAM) */
-    memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
-                           machine->ram_size, &error_fatal);
     memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
-        main_mem);
+        machine->ram);
 
     /* create device tree */
     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
@@ -XXX,XX +XXX,XX @@ static void spike_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+    mc->default_ram_id = "riscv.spike.ram";
 }
 
 static const TypeInfo spike_machine_typeinfo = {
-- 
2.31.1