misc: Some inclusive terminology changes

[PATCH 4/6] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink

Posted by Philippe Mathieu-Daudé 5 years, 5 months ago

In order to use inclusive terminology, rename 'slave stream'
as 'sink stream'.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 hw/net/xilinx_axienet.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 0c4ac727207..4e48535f373 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -46,11 +46,11 @@
      OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
 
 #define XILINX_AXI_ENET_DATA_STREAM(obj) \
-     OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
+     OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
      TYPE_XILINX_AXI_ENET_DATA_STREAM)
 
 #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
-     OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
+     OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
      TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
 
 /* Advertisement control register. */
@@ -310,10 +310,10 @@ struct TEMAC  {
     void *parent;
 };
 
-typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
+typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink;
 typedef struct XilinxAXIEnet XilinxAXIEnet;
 
-struct XilinxAXIEnetStreamSlave {
+struct XilinxAXIEnetStreamSink {
     Object parent;
 
     struct XilinxAXIEnet *enet;
@@ -325,8 +325,8 @@ struct XilinxAXIEnet {
     qemu_irq irq;
     StreamSink *tx_data_dev;
     StreamSink *tx_control_dev;
-    XilinxAXIEnetStreamSlave rx_data_dev;
-    XilinxAXIEnetStreamSlave rx_control_dev;
+    XilinxAXIEnetStreamSink rx_data_dev;
+    XilinxAXIEnetStreamSink rx_control_dev;
     NICState *nic;
     NICConf conf;
 
@@ -859,7 +859,7 @@ xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
                                    bool eop)
 {
     int i;
-    XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
+    XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
     XilinxAXIEnet *s = cs->enet;
 
     assert(eop);
@@ -880,7 +880,7 @@ static size_t
 xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
                                 bool eop)
 {
-    XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
+    XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
     XilinxAXIEnet *s = ds->enet;
 
     /* TX enable ?  */
@@ -954,8 +954,8 @@ static NetClientInfo net_xilinx_enet_info = {
 static void xilinx_enet_realize(DeviceState *dev, Error **errp)
 {
     XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
-    XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
-    XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
+    XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
+    XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(
                                                             &s->rx_control_dev);
 
     object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
@@ -1046,7 +1046,7 @@ static const TypeInfo xilinx_enet_info = {
 static const TypeInfo xilinx_enet_data_stream_info = {
     .name          = TYPE_XILINX_AXI_ENET_DATA_STREAM,
     .parent        = TYPE_OBJECT,
-    .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
+    .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
     .class_init    = xilinx_enet_data_stream_class_init,
     .interfaces = (InterfaceInfo[]) {
             { TYPE_STREAM_SINK },
@@ -1057,7 +1057,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
 static const TypeInfo xilinx_enet_control_stream_info = {
     .name          = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
     .parent        = TYPE_OBJECT,
-    .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
+    .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
     .class_init    = xilinx_enet_control_stream_class_init,
     .interfaces = (InterfaceInfo[]) {
             { TYPE_STREAM_SINK },
-- 
2.26.2

Re: [PATCH 4/6] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink

Posted by Paolo Bonzini 5 years, 5 months ago

On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename 'slave stream'
> as 'sink stream'.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
>  hw/net/xilinx_axienet.c | 24 ++++++++++++------------
>  1 file changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> index 0c4ac727207..4e48535f373 100644
> --- a/hw/net/xilinx_axienet.c
> +++ b/hw/net/xilinx_axienet.c
> @@ -46,11 +46,11 @@
>       OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
>  
>  #define XILINX_AXI_ENET_DATA_STREAM(obj) \
> -     OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
> +     OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
>       TYPE_XILINX_AXI_ENET_DATA_STREAM)
>  
>  #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
> -     OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
> +     OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
>       TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
>  
>  /* Advertisement control register. */
> @@ -310,10 +310,10 @@ struct TEMAC  {
>      void *parent;
>  };
>  
> -typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
> +typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink;
>  typedef struct XilinxAXIEnet XilinxAXIEnet;
>  
> -struct XilinxAXIEnetStreamSlave {
> +struct XilinxAXIEnetStreamSink {
>      Object parent;
>  
>      struct XilinxAXIEnet *enet;
> @@ -325,8 +325,8 @@ struct XilinxAXIEnet {
>      qemu_irq irq;
>      StreamSink *tx_data_dev;
>      StreamSink *tx_control_dev;
> -    XilinxAXIEnetStreamSlave rx_data_dev;
> -    XilinxAXIEnetStreamSlave rx_control_dev;
> +    XilinxAXIEnetStreamSink rx_data_dev;
> +    XilinxAXIEnetStreamSink rx_control_dev;
>      NICState *nic;
>      NICConf conf;
>  
> @@ -859,7 +859,7 @@ xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
>                                     bool eop)
>  {
>      int i;
> -    XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
> +    XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
>      XilinxAXIEnet *s = cs->enet;
>  
>      assert(eop);
> @@ -880,7 +880,7 @@ static size_t
>  xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
>                                  bool eop)
>  {
> -    XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
> +    XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
>      XilinxAXIEnet *s = ds->enet;
>  
>      /* TX enable ?  */
> @@ -954,8 +954,8 @@ static NetClientInfo net_xilinx_enet_info = {
>  static void xilinx_enet_realize(DeviceState *dev, Error **errp)
>  {
>      XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
> -    XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
> -    XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
> +    XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
> +    XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(
>                                                              &s->rx_control_dev);
>  
>      object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
> @@ -1046,7 +1046,7 @@ static const TypeInfo xilinx_enet_info = {
>  static const TypeInfo xilinx_enet_data_stream_info = {
>      .name          = TYPE_XILINX_AXI_ENET_DATA_STREAM,
>      .parent        = TYPE_OBJECT,
> -    .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> +    .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
>      .class_init    = xilinx_enet_data_stream_class_init,
>      .interfaces = (InterfaceInfo[]) {
>              { TYPE_STREAM_SINK },
> @@ -1057,7 +1057,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
>  static const TypeInfo xilinx_enet_control_stream_info = {
>      .name          = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
>      .parent        = TYPE_OBJECT,
> -    .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> +    .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
>      .class_init    = xilinx_enet_control_stream_class_init,
>      .interfaces = (InterfaceInfo[]) {
>              { TYPE_STREAM_SINK },
> 

Acked-by: Paolo Bonzini <pbonzini@redhat.com>

Re: [PATCH 4/6] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink

Posted by Edgar E. Iglesias 5 years, 5 months ago

On Fri, Sep 11, 2020 at 09:28:38AM +0200, Paolo Bonzini wrote:
> On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> > In order to use inclusive terminology, rename 'slave stream'
> > as 'sink stream'.
> > 
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > ---
> >  hw/net/xilinx_axienet.c | 24 ++++++++++++------------
> >  1 file changed, 12 insertions(+), 12 deletions(-)
> > 
> > diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> > index 0c4ac727207..4e48535f373 100644
> > --- a/hw/net/xilinx_axienet.c
> > +++ b/hw/net/xilinx_axienet.c
> > @@ -46,11 +46,11 @@
> >       OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
> >  
> >  #define XILINX_AXI_ENET_DATA_STREAM(obj) \
> > -     OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
> > +     OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
> >       TYPE_XILINX_AXI_ENET_DATA_STREAM)
> >  
> >  #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
> > -     OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
> > +     OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
> >       TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
> >  
> >  /* Advertisement control register. */
> > @@ -310,10 +310,10 @@ struct TEMAC  {
> >      void *parent;
> >  };
> >  
> > -typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
> > +typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink;
> >  typedef struct XilinxAXIEnet XilinxAXIEnet;
> >  
> > -struct XilinxAXIEnetStreamSlave {
> > +struct XilinxAXIEnetStreamSink {
> >      Object parent;
> >  
> >      struct XilinxAXIEnet *enet;
> > @@ -325,8 +325,8 @@ struct XilinxAXIEnet {
> >      qemu_irq irq;
> >      StreamSink *tx_data_dev;
> >      StreamSink *tx_control_dev;
> > -    XilinxAXIEnetStreamSlave rx_data_dev;
> > -    XilinxAXIEnetStreamSlave rx_control_dev;
> > +    XilinxAXIEnetStreamSink rx_data_dev;
> > +    XilinxAXIEnetStreamSink rx_control_dev;
> >      NICState *nic;
> >      NICConf conf;
> >  
> > @@ -859,7 +859,7 @@ xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
> >                                     bool eop)
> >  {
> >      int i;
> > -    XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
> > +    XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
> >      XilinxAXIEnet *s = cs->enet;
> >  
> >      assert(eop);
> > @@ -880,7 +880,7 @@ static size_t
> >  xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
> >                                  bool eop)
> >  {
> > -    XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
> > +    XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
> >      XilinxAXIEnet *s = ds->enet;
> >  
> >      /* TX enable ?  */
> > @@ -954,8 +954,8 @@ static NetClientInfo net_xilinx_enet_info = {
> >  static void xilinx_enet_realize(DeviceState *dev, Error **errp)
> >  {
> >      XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
> > -    XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
> > -    XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
> > +    XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
> > +    XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(
> >                                                              &s->rx_control_dev);
> >  
> >      object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
> > @@ -1046,7 +1046,7 @@ static const TypeInfo xilinx_enet_info = {
> >  static const TypeInfo xilinx_enet_data_stream_info = {
> >      .name          = TYPE_XILINX_AXI_ENET_DATA_STREAM,
> >      .parent        = TYPE_OBJECT,
> > -    .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> > +    .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
> >      .class_init    = xilinx_enet_data_stream_class_init,
> >      .interfaces = (InterfaceInfo[]) {
> >              { TYPE_STREAM_SINK },
> > @@ -1057,7 +1057,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
> >  static const TypeInfo xilinx_enet_control_stream_info = {
> >      .name          = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
> >      .parent        = TYPE_OBJECT,
> > -    .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> > +    .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
> >      .class_init    = xilinx_enet_control_stream_class_init,
> >      .interfaces = (InterfaceInfo[]) {
> >              { TYPE_STREAM_SINK },
> > 
> 
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>


Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

[PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices
[PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink
[PATCH 3/6] hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink
[PATCH 4/6] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink
[PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole'
[PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken()