Series comparison

-[PULL 00/18] riscv-to-apply queue
+[PULL 00/28] riscv-to-apply queue
-The following changes since commit 7774e403f2ac58b3e87bfe8d2f77676501ba893e:
+The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
-  Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200825-pull-request' into staging (2020-08-25 10:54:51 +0100)
+  Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)
 are available in the Git repository at:
-  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200825
+  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528
-for you to fetch changes up to e39a8320b088dd5efc9ebaafe387e52b3d962665:
+for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:
-  target/riscv: Support the Virtual Instruction fault (2020-08-25 09:11:36 -0700)
+  target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)
 ----------------------------------------------------------------
-This pull request first adds support for multi-socket NUMA RISC-V
+RISC-V PR for 9.1
 machines. The Spike and Virt machines both support NUMA sockets.
-This PR also updates the current experimental Hypervisor support to the
+* APLICs add child earlier than realize
-v0.6.1 spec.
+* Fix exposure of Zkr
 * Raise exceptions on wrs.nto
 * Implement SBI debug console (DBCN) calls for KVM
 * Support 64-bit addresses for initrd
 * Change RISCV_EXCP_SEMIHOST exception number to 63
 * Tolerate KVM disable ext errors
 * Set tval in breakpoints
 * Add support for Zve32x extension
 * Add support for Zve64x extension
 * Relax vector register check in RISCV gdbstub
 * Fix the element agnostic Vector function problem
 * Fix Zvkb extension config
 * Implement dynamic establishment of custom decoder
 * Add th.sxstatus CSR emulation
 * Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
 * Check single width operator for vector fp widen instructions
 * Check single width operator for vfncvt.rod.f.f.w
 * Remove redudant SEW checking for vector fp narrow/widen instructions
 * Prioritize pmp errors in raise_mmu_exception()
 * Do not set mtval2 for non guest-page faults
 * Remove experimental prefix from "B" extension
 * Fixup CBO extension register calculation
 * Fix the hart bit setting of AIA
 * Fix reg_width in ricsv_gen_dynamic_vector_feature()
 * Decode all of the pmpcfg and pmpaddr CSRs
 * Raise an exception when CSRRS/CSRRC writes a read-only CSR
 ----------------------------------------------------------------
-Alistair Francis (13):
+Alexei Filippov (1):
-      target/riscv: Allow setting a two-stage lookup in the virt status
+      target/riscv: do not set mtval2 for non guest-page faults
       target/riscv: Allow generating hlv/hlvx/hsv instructions
       target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
       target/riscv: Don't allow guest to write to htinst
       target/riscv: Convert MSTATUS MTL to GVA
       target/riscv: Fix the interrupt cause code
       target/riscv: Update the Hypervisor trap return/entry
       target/riscv: Update the CSRs to the v0.6 Hyp extension
       target/riscv: Only support a single VSXL length
       target/riscv: Only support little endian guests
       target/riscv: Support the v0.6 Hypervisor extension CRSs
       target/riscv: Return the exception from invalid CSR accesses
       target/riscv: Support the Virtual Instruction fault
-Anup Patel (5):
+Alistair Francis (2):
-      hw/riscv: Allow creating multiple instances of CLINT
+      target/riscv: rvzicbo: Fixup CBO extension register calculation
-      hw/riscv: Allow creating multiple instances of PLIC
+      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
       hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
       hw/riscv: spike: Allow creating multiple NUMA sockets
       hw/riscv: virt: Allow creating multiple NUMA sockets
- include/hw/riscv/numa.h                 | 113 +++++++
+Andrew Jones (2):
- include/hw/riscv/sifive_clint.h         |   7 +-
+      target/riscv/kvm: Fix exposure of Zkr
- include/hw/riscv/sifive_plic.h          |  12 +-
+      target/riscv: Raise exceptions on wrs.nto
  include/hw/riscv/spike.h                |  11 +-
  include/hw/riscv/virt.h                 |   9 +-
  target/riscv/cpu.h                      |   2 +
  target/riscv/cpu_bits.h                 |  25 +-
  target/riscv/helper.h                   |   4 +
  target/riscv/insn32-64.decode           |   5 +
  target/riscv/insn32.decode              |  11 +
  hw/riscv/numa.c                         | 242 +++++++++++++++
  hw/riscv/sifive_clint.c                 |  20 +-
  hw/riscv/sifive_e.c                     |   4 +-
  hw/riscv/sifive_plic.c                  |  24 +-
  hw/riscv/sifive_u.c                     |   4 +-
  hw/riscv/spike.c                        | 232 +++++++++-----
  hw/riscv/virt.c                         | 526 ++++++++++++++++++--------------
  target/riscv/cpu_helper.c               | 123 ++++----
  target/riscv/csr.c                      | 171 +++++++++--
  target/riscv/op_helper.c                | 176 ++++++++++-
  target/riscv/translate.c                |  10 -
  hw/riscv/meson.build                    |   1 +
  target/riscv/insn_trans/trans_rvh.c.inc | 342 ++++++++++++++++++++-
 files changed, 1630 insertions(+), 444 deletions(-)
  create mode 100644 include/hw/riscv/numa.h
  create mode 100644 hw/riscv/numa.c
+Cheng Yang (1):
+      hw/riscv/boot.c: Support 64-bit address for initrd
+Christoph Müllner (1):
+      riscv: thead: Add th.sxstatus CSR emulation
+Clément Léger (1):
+      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
+Daniel Henrique Barboza (6):
+      target/riscv/kvm: implement SBI debug console (DBCN) calls
+      target/riscv/kvm: tolerate KVM disable ext errors
+      target/riscv/debug: set tval=pc in breakpoint exceptions
+      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
+      target/riscv: prioritize pmp errors in raise_mmu_exception()
+      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
+Huang Tao (2):
+      target/riscv: Fix the element agnostic function problem
+      target/riscv: Implement dynamic establishment of custom decoder
+Jason Chien (3):
+      target/riscv: Add support for Zve32x extension
+      target/riscv: Add support for Zve64x extension
+      target/riscv: Relax vector register check in RISCV gdbstub
+Max Chou (4):
+      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
+      target/riscv: rvv: Check single width operator for vector fp widen instructions
+      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
+      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
+Rob Bradford (1):
+      target/riscv: Remove experimental prefix from "B" extension
+Yangyu Chen (1):
+      target/riscv/cpu.c: fix Zvkb extension config
+Yong-Xuan Wang (1):
+      target/riscv/kvm.c: Fix the hart bit setting of AIA
+Yu-Ming Chang (1):
+      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
+yang.zhang (1):
+      hw/intc/riscv_aplic: APLICs should add child earlier than realize
+ MAINTAINERS                                    |   1 +
+ target/riscv/cpu.h                             |  11 ++
+ target/riscv/cpu_bits.h                        |   2 +-
+ target/riscv/cpu_cfg.h                         |   2 +
+ target/riscv/helper.h                          |   1 +
+ target/riscv/sbi_ecall_interface.h             |  17 +++
+ target/riscv/tcg/tcg-cpu.h                     |  15 +++
+ disas/riscv.c                                  |  65 +++++++++-
+ hw/intc/riscv_aplic.c                          |   8 +-
+ hw/riscv/boot.c                                |   4 +-
+ target/riscv/cpu.c                             |  10 +-
+ target/riscv/cpu_helper.c                      |  37 +++---
+ target/riscv/csr.c                             |  71 +++++++++--
+ target/riscv/debug.c                           |   3 +
+ target/riscv/gdbstub.c                         |   8 +-
+ target/riscv/kvm/kvm-cpu.c                     | 157 ++++++++++++++++++++++++-
+ target/riscv/op_helper.c                       |  17 ++-
+ target/riscv/tcg/tcg-cpu.c                     |  50 +++++---
+ target/riscv/th_csr.c                          |  79 +++++++++++++
+ target/riscv/translate.c                       |  31 +++--
+ target/riscv/vector_internals.c                |  22 ++++
+ target/riscv/insn_trans/trans_privileged.c.inc |   2 +
+ target/riscv/insn_trans/trans_rvv.c.inc        |  46 +++++---
+ target/riscv/insn_trans/trans_rvzawrs.c.inc    |  29 +++--
+ target/riscv/insn_trans/trans_rvzicbo.c.inc    |  16 ++-
+ target/riscv/meson.build                       |   1 +
+files changed, 596 insertions(+), 109 deletions(-)
+ create mode 100644 target/riscv/th_csr.c

-New patch
+[PULL 01/28] hw/intc/riscv_aplic: APLICs should add child earlier than realize
+From: "yang.zhang" <yang.zhang@hexintek.com>
+Since only root APLICs can have hw IRQ lines, aplic->parent should
+be initialized first.
+Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/intc/riscv_aplic.c | 8 ++++----
+file changed, 4 insertions(+), 4 deletions(-)
+diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/riscv_aplic.c
++++ b/hw/intc/riscv_aplic.c
+@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
+     qdev_prop_set_bit(dev, "msimode", msimode);
+     qdev_prop_set_bit(dev, "mmode", mmode);
++    if (parent) {
++        riscv_aplic_add_child(parent, dev);
++    }
++
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+     if (!is_kvm_aia(msimode)) {
+         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+     }
+-    if (parent) {
+-        riscv_aplic_add_child(parent, dev);
+-    }
+-
+     if (!msimode) {
+         for (i = 0; i < num_harts; i++) {
+             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
+--
+.45.1

-[PULL 09/18] target/riscv: Don't allow guest to write to htinst
+[PULL 02/28] target/riscv/kvm: Fix exposure of Zkr
+From: Andrew Jones <ajones@ventanamicro.com>
+The Zkr extension may only be exposed to KVM guests if the VMM
+implements the SEED CSR. Use the same implementation as TCG.
+Without this patch, running with a KVM which does not forward the
+SEED CSR access to QEMU will result in an ILL exception being
+injected into the guest (this results in Linux guests crashing on
+boot). And, when running with a KVM which does forward the access,
+QEMU will crash, since QEMU doesn't know what to do with the exit.
+Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: ca5359fec6b2aff851eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com
-Message-Id: <ca5359fec6b2aff851eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 1 -
+ target/riscv/cpu.h         |  3 +++
-file changed, 1 deletion(-)
+ target/riscv/csr.c         | 18 ++++++++++++++----
  target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 files changed, 42 insertions(+), 4 deletions(-)
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.h
++++ b/target/riscv/cpu.h
+@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
+ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
++target_ulong riscv_new_csr_seed(target_ulong new_value,
++                                target_ulong write_mask);
++
+ uint8_t satp_mode_max_from_map(uint32_t map);
+ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
+@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
+ #endif
- static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
  /* Crypto Extension */
 -static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 -                               target_ulong *ret_value,
 -                               target_ulong new_value,
 -                               target_ulong write_mask)
 +target_ulong riscv_new_csr_seed(target_ulong new_value,
 +                                target_ulong write_mask)
  {
--    env->htinst = val;
+     uint16_t random_v;
-     return 0;
+     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
          rval = random_v | SEED_OPST_ES16;
      }
 +    return rval;
 +}
 +
 +static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 +                               target_ulong *ret_value,
 +                               target_ulong new_value,
 +                               target_ulong write_mask)
 +{
 +    target_ulong rval;
 +
 +    rval = riscv_new_csr_seed(new_value, write_mask);
 +
      if (ret_value) {
          *ret_value = rval;
      }
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/kvm/kvm-cpu.c
 +++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
      return ret;
  }
++static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
++{
++    target_ulong csr_num = run->riscv_csr.csr_num;
++    target_ulong new_value = run->riscv_csr.new_value;
++    target_ulong write_mask = run->riscv_csr.write_mask;
++    int ret = 0;
++
++    switch (csr_num) {
++    case CSR_SEED:
++        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
++        break;
++    default:
++        qemu_log_mask(LOG_UNIMP,
++                      "%s: un-handled CSR EXIT for CSR %lx\n",
++                      __func__, csr_num);
++        ret = -1;
++        break;
++    }
++
++    return ret;
++}
++
+ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+ {
+     int ret = 0;
+@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
+     case KVM_EXIT_RISCV_SBI:
+         ret = kvm_riscv_handle_sbi(cs, run);
+         break;
++    case KVM_EXIT_RISCV_CSR:
++        ret = kvm_riscv_handle_csr(cs, run);
++        break;
+     default:
+         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
+                       __func__, run->exit_reason);
 --
-.28.0
+.45.1

-[PULL 07/18] target/riscv: Allow generating hlv/hlvx/hsv instructions
+[PULL 03/28] target/riscv: Raise exceptions on wrs.nto
+From: Andrew Jones <ajones@ventanamicro.com>
+Implementing wrs.nto to always just return is consistent with the
+specification, as the instruction is permitted to terminate the
+stall for any reason, but it's not useful for virtualization, where
+we'd like the guest to trap to the hypervisor in order to allow
+scheduling of the lock holding VCPU. Change to always immediately
+raise exceptions when the appropriate conditions are present,
+otherwise continue to just return. Note, immediately raising
+exceptions is also consistent with the specification since the
+time limit that should expire prior to the exception is
+implementation-specific.
+Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com
-Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h                 |   1 +
+ target/riscv/helper.h                       |  1 +
- target/riscv/helper.h                   |   3 +
+ target/riscv/op_helper.c                    | 11 ++++++++
- target/riscv/insn32-64.decode           |   5 +
+ target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
- target/riscv/insn32.decode              |  11 +
+files changed, 32 insertions(+), 9 deletions(-)
  target/riscv/op_helper.c                | 114 ++++++++
  target/riscv/insn_trans/trans_rvh.c.inc | 340 ++++++++++++++++++++++++
 files changed, 474 insertions(+)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
-+++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@
- #define HSTATUS_SP2V         0x00000200
- #define HSTATUS_VTVM         0x00100000
- #define HSTATUS_VTSR         0x00400000
-+#define HSTATUS_HU           0x00000200
- #define HSTATUS32_WPRI       0xFF8FF87E
- #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/helper.h
 +++ b/target/riscv/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(tlb_flush, void, env)
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
- /* Hypervisor functions */
+ DEF_HELPER_1(sret, tl, env)
- #ifndef CONFIG_USER_ONLY
+ DEF_HELPER_1(mret, tl, env)
- DEF_HELPER_1(hyp_tlb_flush, void, env)
+ DEF_HELPER_1(wfi, void, env)
-+DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
++DEF_HELPER_1(wrs_nto, void, env)
-+DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
+ DEF_HELPER_1(tlb_flush, void, env)
-+DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
+ DEF_HELPER_1(tlb_flush_all, void, env)
- #endif
+ /* Native Debug */
  /* Vector functions */
 diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32-64.decode
 +++ b/target/riscv/insn32-64.decode
@@ -XXX,XX +XXX,XX @@ fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
  fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
  fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
  fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
 +
 +# *** RV32H Base Instruction Set ***
 +hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
 +hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
 +hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn32.decode
 +++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
  @r_vm_0  ...... . ..... ..... ... ..... .......    &rmrr vm=0 %rs2 %rs1 %rd
  @r_wdvm  ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
  @r2_zimm . zimm:11  ..... ... ..... ....... %rs1 %rd
 +@r2_s    .......   ..... ..... ... ..... ....... %rs2 %rs1
  @hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
  @hfence_vvma ....... ..... .....   ... ..... ....... %rs2 %rs1
@@ -XXX,XX +XXX,XX @@ fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
  fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
  # *** RV32H Base Instruction Set ***
 +hlv_b       0110000  00000  ..... 100 ..... 1110011 @r2
 +hlv_bu      0110000  00001  ..... 100 ..... 1110011 @r2
 +hlv_h       0110010  00000  ..... 100 ..... 1110011 @r2
 +hlv_hu      0110010  00001  ..... 100 ..... 1110011 @r2
 +hlvx_hu     0110010  00011  ..... 100 ..... 1110011 @r2
 +hlv_w       0110100  00000  ..... 100 ..... 1110011 @r2
 +hlvx_wu     0110100  00011  ..... 100 ..... 1110011 @r2
 +hsv_b       0110001  .....  ..... 100 00000 1110011 @r2_s
 +hsv_h       0110011  .....  ..... 100 00000 1110011 @r2_s
 +hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
  hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
  hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env)
+@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
-     riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+     }
  }
-+target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
++void helper_wrs_nto(CPURISCVState *env)
 +                             target_ulong attrs, target_ulong memop)
 +{
-+    if (env->priv == PRV_M ||
++    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
-+        (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
++        get_field(env->hstatus, HSTATUS_VTW) &&
-+        (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
++        !get_field(env->mstatus, MSTATUS_TW)) {
-+            get_field(env->hstatus, HSTATUS_HU))) {
++        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
-+        target_ulong pte;
++    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
-+
++        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +        riscv_cpu_set_two_stage_lookup(env, true);
 +
 +        switch (memop) {
 +        case MO_SB:
 +            pte = cpu_ldsb_data_ra(env, address, GETPC());
 +            break;
 +        case MO_UB:
 +            pte = cpu_ldub_data_ra(env, address, GETPC());
 +            break;
 +        case MO_TESW:
 +            pte = cpu_ldsw_data_ra(env, address, GETPC());
 +            break;
 +        case MO_TEUW:
 +            pte = cpu_lduw_data_ra(env, address, GETPC());
 +            break;
 +        case MO_TESL:
 +            pte = cpu_ldl_data_ra(env, address, GETPC());
 +            break;
 +        case MO_TEUL:
 +            pte = cpu_ldl_data_ra(env, address, GETPC());
 +            break;
 +        case MO_TEQ:
 +            pte = cpu_ldq_data_ra(env, address, GETPC());
 +            break;
 +        default:
 +            g_assert_not_reached();
 +        }
 +
 +        riscv_cpu_set_two_stage_lookup(env, false);
 +
 +        return pte;
 +    }
-+
-+    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
-+    return 0;
 +}
 +
-+void helper_hyp_store(CPURISCVState *env, target_ulong address,
+ void helper_tlb_flush(CPURISCVState *env)
-+                      target_ulong val, target_ulong attrs, target_ulong memop)
+ {
-+{
+     CPUState *cs = env_cpu(env);
-+    if (env->priv == PRV_M ||
+diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
 +        (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 +        (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
 +            get_field(env->hstatus, HSTATUS_HU))) {
 +        riscv_cpu_set_two_stage_lookup(env, true);
 +
 +        switch (memop) {
 +        case MO_SB:
 +        case MO_UB:
 +            cpu_stb_data_ra(env, address, val, GETPC());
 +            break;
 +        case MO_TESW:
 +        case MO_TEUW:
 +            cpu_stw_data_ra(env, address, val, GETPC());
 +            break;
 +        case MO_TESL:
 +        case MO_TEUL:
 +            cpu_stl_data_ra(env, address, val, GETPC());
 +            break;
 +        case MO_TEQ:
 +            cpu_stq_data_ra(env, address, val, GETPC());
 +            break;
 +        default:
 +            g_assert_not_reached();
 +        }
 +
 +        riscv_cpu_set_two_stage_lookup(env, false);
 +
 +        return;
 +    }
 +
 +    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +}
 +
 +target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
 +                               target_ulong attrs, target_ulong memop)
 +{
 +    if (env->priv == PRV_M ||
 +        (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 +        (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
 +            get_field(env->hstatus, HSTATUS_HU))) {
 +        target_ulong pte;
 +
 +        riscv_cpu_set_two_stage_lookup(env, true);
 +
 +        switch (memop) {
 +        case MO_TEUL:
 +            pte = cpu_ldub_data_ra(env, address, GETPC());
 +            break;
 +        case MO_TEUW:
 +            pte = cpu_lduw_data_ra(env, address, GETPC());
 +            break;
 +        default:
 +            g_assert_not_reached();
 +        }
 +
 +        riscv_cpu_set_two_stage_lookup(env, false);
 +
 +        return pte;
 +    }
 +
 +    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    return 0;
 +}
 +
  #endif /* !CONFIG_USER_ONLY */
 diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvh.c.inc
+--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
-+++ b/target/riscv/insn_trans/trans_rvh.c.inc
++++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
 @@ -XXX,XX +XXX,XX @@
   * this program.  If not, see <http://www.gnu.org/licenses/>.
   */
-+static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
+-static bool trans_wrs(DisasContext *ctx)
 +static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
  {
      if (!ctx->cfg_ptr->ext_zawrs) {
          return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
      return true;
  }
 -#define GEN_TRANS_WRS(insn)                                     \
 -static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
 -{                                                               \
 -    (void)a;                                                    \
 -    return trans_wrs(ctx);                                      \
 -}
 +static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
 +{
-+    REQUIRE_EXT(ctx, RVH);
++    if (!ctx->cfg_ptr->ext_zawrs) {
 +        return false;
 +    }
 -GEN_TRANS_WRS(wrs_nto)
 -GEN_TRANS_WRS(wrs_sto)
 +    /*
 +     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
 +     * should raise an exception when the implementation-specific bounded time
 +     * limit has expired. Our time limit is zero, so we either return
 +     * immediately, as does our implementation of wrs.sto, or raise an
 +     * exception, as handled by the wrs.nto helper.
 +     */
 +#ifndef CONFIG_USER_ONLY
-+    TCGv t0 = tcg_temp_new();
++    gen_helper_wrs_nto(tcg_env);
 +    TCGv t1 = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_SB);
 +
 +    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
 +    gen_set_gpr(a->rd, t1);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(t1);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv t1 = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_TESW);
 +
 +    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
 +    gen_set_gpr(a->rd, t1);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(t1);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv t1 = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_TESL);
 +
 +    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
 +    gen_set_gpr(a->rd, t1);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(t1);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv t1 = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_UB);
 +
 +    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
 +    gen_set_gpr(a->rd, t1);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(t1);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv t1 = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_TEUW);
 +
 +    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
 +    gen_set_gpr(a->rd, t1);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(t1);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv dat = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    gen_get_gpr(dat, a->rs2);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_SB);
 +
 +    gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(dat);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv dat = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    gen_get_gpr(dat, a->rs2);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_TESW);
 +
 +    gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(dat);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv dat = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    gen_get_gpr(dat, a->rs2);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_TESL);
 +
 +    gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(dat);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +#ifdef TARGET_RISCV64
 +static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv t1 = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_TEUL);
 +
 +    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
 +    gen_set_gpr(a->rd, t1);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(t1);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv t1 = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_TEQ);
 +
 +    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
 +    gen_set_gpr(a->rd, t1);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(t1);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +
 +static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
 +{
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv dat = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    gen_get_gpr(dat, a->rs2);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_TEQ);
 +
 +    gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(dat);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
 +#endif
 +
-+static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
++    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
-+{
++    return trans_wrs_sto(ctx, NULL);
 +    REQUIRE_EXT(ctx, RVH);
 +#ifndef CONFIG_USER_ONLY
 +    TCGv t0 = tcg_temp_new();
 +    TCGv t1 = tcg_temp_new();
 +    TCGv mem_idx = tcg_temp_new();
 +    TCGv memop = tcg_temp_new();
 +
 +    gen_get_gpr(t0, a->rs1);
 +    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
 +    tcg_gen_movi_tl(memop, MO_TEUW);
 +
 +    gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
 +    gen_set_gpr(a->rd, t1);
 +
 +    tcg_temp_free(t0);
 +    tcg_temp_free(t1);
 +    tcg_temp_free(mem_idx);
 +    tcg_temp_free(memop);
 +    return true;
 +#else
 +    return false;
 +#endif
 +}
-+
-+static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
-+{
-+    REQUIRE_EXT(ctx, RVH);
-+#ifndef CONFIG_USER_ONLY
-+    TCGv t0 = tcg_temp_new();
-+    TCGv t1 = tcg_temp_new();
-+    TCGv mem_idx = tcg_temp_new();
-+    TCGv memop = tcg_temp_new();
-+
-+    gen_get_gpr(t0, a->rs1);
-+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
-+    tcg_gen_movi_tl(memop, MO_TEUL);
-+
-+    gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
-+    gen_set_gpr(a->rd, t1);
-+
-+    tcg_temp_free(t0);
-+    tcg_temp_free(t1);
-+    tcg_temp_free(mem_idx);
-+    tcg_temp_free(memop);
-+    return true;
-+#else
-+    return false;
-+#endif
-+}
-+
- static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
- {
-     REQUIRE_EXT(ctx, RVH);
 --
-.28.0
+.45.1

-[PULL 16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs
+[PULL 04/28] target/riscv/kvm: implement SBI debug console (DBCN) calls
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+SBI defines a Debug Console extension "DBCN" that will, in time, replace
+the legacy console putchar and getchar SBI extensions.
+The appeal of the DBCN extension is that it allows multiple bytes to be
+read/written in the SBI console in a single SBI call.
+As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
+module to userspace. But this will only happens if the KVM module
+actually supports this SBI extension and we activate it.
+We'll check for DBCN support during init time, checking if get-reg-list
+is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
+kvm_set_one_reg() during kvm_arch_init_vcpu().
+Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
+SBI_EXT_DBCN, reading and writing as required.
+A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
+host, takes around 20 seconds to boot without using DBCN. With this
+patch we're taking around 14 seconds to boot due to the speed-up in the
+terminal output.  There's no change in boot time if the guest isn't
+using earlycon.
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com
-Message-Id: <644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h |  3 +++
+ target/riscv/sbi_ecall_interface.h |  17 +++++
- target/riscv/csr.c      | 40 ++++++++++++++++++++++++++++++++++++++++
+ target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
-files changed, 43 insertions(+)
+files changed, 128 insertions(+)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
+--- a/target/riscv/sbi_ecall_interface.h
-+++ b/target/riscv/cpu_bits.h
++++ b/target/riscv/sbi_ecall_interface.h
 @@ -XXX,XX +XXX,XX @@
- #define CSR_HIDELEG         0x603
- #define CSR_HIE             0x604
+ /* clang-format off */
- #define CSR_HCOUNTEREN      0x606
-+#define CSR_HGEIE           0x607
++#define SBI_SUCCESS                      0
- #define CSR_HTVAL           0x643
++#define SBI_ERR_FAILED                  -1
-+#define CSR_HVIP            0x645
++#define SBI_ERR_NOT_SUPPORTED           -2
- #define CSR_HIP             0x644
++#define SBI_ERR_INVALID_PARAM           -3
- #define CSR_HTINST          0x64A
++#define SBI_ERR_DENIED                  -4
-+#define CSR_HGEIP           0xE12
++#define SBI_ERR_INVALID_ADDRESS         -5
- #define CSR_HGATP           0x680
++#define SBI_ERR_ALREADY_AVAILABLE       -6
- #define CSR_HTIMEDELTA      0x605
++#define SBI_ERR_ALREADY_STARTED         -7
- #define CSR_HTIMEDELTAH     0x615
++#define SBI_ERR_ALREADY_STOPPED         -8
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
++#define SBI_ERR_NO_SHMEM                -9
 +
  /* SBI Extension IDs */
  #define SBI_EXT_0_1_SET_TIMER           0x0
  #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_IPI                     0x735049
  #define SBI_EXT_RFENCE                  0x52464E43
  #define SBI_EXT_HSM                     0x48534D
 +#define SBI_EXT_DBCN                    0x4442434E
  /* SBI function IDs for BASE extension */
  #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
  #define SBI_EXT_HSM_HART_STOP           0x1
  #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 +/* SBI function IDs for DBCN extension */
 +#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
 +#define SBI_EXT_DBCN_CONSOLE_READ       0x1
 +#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
 +
  #define SBI_HSM_HART_STATUS_STARTED     0x0
  #define SBI_HSM_HART_STATUS_STOPPED     0x1
  #define SBI_HSM_HART_STATUS_START_PENDING   0x2
 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/kvm/kvm-cpu.c
-+++ b/target/riscv/csr.c
++++ b/target/riscv/kvm/kvm-cpu.c
-@@ -XXX,XX +XXX,XX @@ static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                     KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
  };
 +static KVMCPUConfig kvm_sbi_dbcn = {
 +    .name = "sbi_dbcn",
 +    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
 +                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
 +};
 +
  static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
  {
      CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
      return 0;
  }
-+static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
++static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
-+                   target_ulong new_value, target_ulong write_mask)
++                                             KVMScratchCPU *kvmcpu,
 +                                             struct kvm_reg_list *reglist)
 +{
-+    int ret = rmw_mip(env, 0, ret_value, new_value,
++    struct kvm_reg_list *reg_search;
-+                      write_mask & hip_writable_mask);
++
-+
++    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
-+    *ret_value &= hip_writable_mask;
++                         sizeof(uint64_t), uint64_cmp);
 +
-+    return ret;
++    if (reg_search) {
 +        kvm_sbi_dbcn.supported = true;
 +    }
 +}
 +
- static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
-                    target_ulong new_value, target_ulong write_mask)
+                                  struct kvm_reg_list *reglist)
  {
-     int ret = rmw_mip(env, 0, ret_value, new_value,
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
-                       write_mask & hip_writable_mask);
+     if (riscv_has_ext(&cpu->env, RVV)) {
+         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
-+    *ret_value &= hip_writable_mask;
+     }
 +
 +    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
  }
  static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
      return ret;
  }
-@@ -XXX,XX +XXX,XX @@ static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
++static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
      return 0;
  }
 +static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
 +{
-+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
++    target_ulong reg = 1;
-+    return 0;
++
 +    if (!kvm_sbi_dbcn.supported) {
 +        return 0;
 +    }
 +
 +    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
 +}
 +
-+static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
+ int kvm_arch_init_vcpu(CPUState *cs)
  {
      int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
      kvm_riscv_update_cpu_misa_ext(cpu, cs);
      kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 +    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
 +
      return ret;
  }
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
      return true;
  }
 +static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
 +{
-+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
++    g_autofree uint8_t *buf = NULL;
-+    return 0;
++    RISCVCPU *cpu = RISCV_CPU(cs);
 +    target_ulong num_bytes;
 +    uint64_t addr;
 +    unsigned char ch;
 +    int ret;
 +
 +    switch (run->riscv_sbi.function_id) {
 +    case SBI_EXT_DBCN_CONSOLE_READ:
 +    case SBI_EXT_DBCN_CONSOLE_WRITE:
 +        num_bytes = run->riscv_sbi.args[0];
 +
 +        if (num_bytes == 0) {
 +            run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +            run->riscv_sbi.ret[1] = 0;
 +            break;
 +        }
 +
 +        addr = run->riscv_sbi.args[1];
 +
 +        /*
 +         * Handle the case where a 32 bit CPU is running in a
 +         * 64 bit addressing env.
 +         */
 +        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
 +            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
 +        }
 +
 +        buf = g_malloc0(num_bytes);
 +
 +        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
 +            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
 +                             "reading chardev");
 +                exit(1);
 +            }
 +
 +            cpu_physical_memory_write(addr, buf, ret);
 +        } else {
 +            cpu_physical_memory_read(addr, buf, num_bytes);
 +
 +            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
 +            if (ret < 0) {
 +                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
 +                             "writing chardev");
 +                exit(1);
 +            }
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = ret;
 +        break;
 +    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
 +        ch = run->riscv_sbi.args[0];
 +        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
 +
 +        if (ret < 0) {
 +            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
 +                         "writing chardev");
 +            exit(1);
 +        }
 +
 +        run->riscv_sbi.ret[0] = SBI_SUCCESS;
 +        run->riscv_sbi.ret[1] = 0;
 +        break;
 +    default:
 +        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
 +    }
 +}
 +
- static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
+ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
  {
-     *val = env->htval;
+     int ret = 0;
-@@ -XXX,XX +XXX,XX @@ static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
-     return 0;
+         }
- }
+         ret = 0;
+         break;
-+static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
++    case SBI_EXT_DBCN:
-+{
++        kvm_riscv_handle_sbi_dbcn(cs, run);
-+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
++        break;
-+    return 0;
+     default:
-+}
+         qemu_log_mask(LOG_UNIMP,
-+
+                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
 +static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
 +{
 +    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
 +    return 0;
 +}
 +
  static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
  {
      *val = env->hgatp;
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
      [CSR_HSTATUS] =             { hmode,   read_hstatus,     write_hstatus    },
      [CSR_HEDELEG] =             { hmode,   read_hedeleg,     write_hedeleg    },
      [CSR_HIDELEG] =             { hmode,   read_hideleg,     write_hideleg    },
 +    [CSR_HVIP] =                { hmode,   NULL,     NULL,     rmw_hvip       },
      [CSR_HIP] =                 { hmode,   NULL,     NULL,     rmw_hip        },
      [CSR_HIE] =                 { hmode,   read_hie,         write_hie        },
      [CSR_HCOUNTEREN] =          { hmode,   read_hcounteren,  write_hcounteren },
 +    [CSR_HGEIE] =               { hmode,   read_hgeie,       write_hgeie      },
      [CSR_HTVAL] =               { hmode,   read_htval,       write_htval      },
      [CSR_HTINST] =              { hmode,   read_htinst,      write_htinst     },
 +    [CSR_HGEIP] =               { hmode,   read_hgeip,       write_hgeip      },
      [CSR_HGATP] =               { hmode,   read_hgatp,       write_hgatp      },
      [CSR_HTIMEDELTA] =          { hmode,   read_htimedelta,  write_htimedelta },
  #if defined(TARGET_RISCV32)
 --
-.28.0
+.45.1

-New patch
+[PULL 05/28] hw/riscv/boot.c: Support 64-bit address for initrd
+From: Cheng Yang <yangcheng.work@foxmail.com>
+Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
+to set the address of initrd in FDT to support 64-bit address.
+Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ hw/riscv/boot.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/riscv/boot.c
++++ b/hw/riscv/boot.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
+     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
+     if (fdt) {
+         end = start + size;
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
+-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
++        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
+     }
+ }
+--
+.45.1

-[PULL 13/18] target/riscv: Update the CSRs to the v0.6 Hyp extension
+[PULL 06/28] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63
+From: Clément Léger <cleger@rivosinc.com>
+The current semihost exception number (16) is a reserved number (range
+[16-17]). The upcoming double trap specification uses that number for
+the double trap exception. Since the privileged spec (Table 22) defines
+ranges for custom uses change the semihosting exception number to 63
+which belongs to the range [48-63] in order to avoid any future
+collisions with reserved exception.
+Signed-off-by: Clément Léger <cleger@rivosinc.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com
-Message-Id: <4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h | 14 ++++++++------
+ target/riscv/cpu_bits.h | 2 +-
-file changed, 8 insertions(+), 6 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
 diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_bits.h
 +++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
- #endif
+     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
+     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
- /* hstatus CSR bits */
+     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
--#define HSTATUS_SPRV         0x00000001
+-    RISCV_EXCP_SEMIHOST = 0x10,
-+#define HSTATUS_VSBE         0x00000020
+     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
-+#define HSTATUS_GVA          0x00000040
+     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
- #define HSTATUS_SPV          0x00000080
+     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
--#define HSTATUS_SP2P         0x00000100
+     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
--#define HSTATUS_SP2V         0x00000200
++    RISCV_EXCP_SEMIHOST = 0x3f,
-+#define HSTATUS_SPVP         0x00000100
+ } RISCVException;
-+#define HSTATUS_HU           0x00000200
-+#define HSTATUS_VGEIN        0x0003F000
+ #define RISCV_EXCP_INT_FLAG                0x80000000
  #define HSTATUS_VTVM         0x00100000
  #define HSTATUS_VTSR         0x00400000
 -#define HSTATUS_HU           0x00000200
 -#define HSTATUS_GVA          0x00000040
 -#define HSTATUS_SPVP         0x00000100
 +#if defined(TARGET_RISCV64)
 +#define HSTATUS_VSXL        0x300000000
 +#endif
  #define HSTATUS32_WPRI       0xFF8FF87E
  #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
 --
-.28.0
+.45.1

-New patch
+[PULL 07/28] target/riscv/kvm: tolerate KVM disable ext errors
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
+enabled, will fail with a kernel oops SIGILL right at the start. The
+reason is that we can't expose zkr without implementing the SEED CSR.
+Disabling zkr in the guest would be a workaround, but if the KVM doesn't
+allow it we'll error out and never boot.
+In hindsight this is too strict. If we keep proceeding, despite not
+disabling the extension in the KVM vcpu, we'll not add the extension in
+the riscv,isa. The guest kernel will be unaware of the extension, i.e.
+it doesn't matter if the KVM vcpu has it enabled underneath or not. So
+it's ok to keep booting in this case.
+Change our current logic to not error out if we fail to disable an
+extension in kvm_set_one_reg(), but show a warning and keep booting. It
+is important to throw a warning because we must make the user aware that
+the extension is still available in the vcpu, meaning that an
+ill-behaved guest can ignore the riscv,isa settings and  use the
+extension.
+The case we're handling happens with an EINVAL error code. If we fail to
+disable the extension in KVM for any other reason, error out.
+We'll also keep erroring out when we fail to enable an extension in KVM,
+since adding the extension in riscv,isa at this point will cause a guest
+malfunction because the extension isn't enabled in the vcpu.
+Suggested-by: Andrew Jones <ajones@ventanamicro.com>
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
+file changed, 8 insertions(+), 4 deletions(-)
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm/kvm-cpu.c
++++ b/target/riscv/kvm/kvm-cpu.c
+@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
+         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
+         ret = kvm_set_one_reg(cs, id, &reg);
+         if (ret != 0) {
+-            error_report("Unable to %s extension %s in KVM, error %d",
+-                         reg ? "enable" : "disable",
+-                         multi_ext_cfg->name, ret);
+-            exit(EXIT_FAILURE);
++            if (!reg && ret == -EINVAL) {
++                warn_report("KVM cannot disable extension %s",
++                            multi_ext_cfg->name);
++            } else {
++                error_report("Unable to enable extension %s in KVM, error %d",
++                             multi_ext_cfg->name, ret);
++                exit(EXIT_FAILURE);
++            }
+         }
+     }
+ }
+--
+.45.1

-[PULL 11/18] target/riscv: Fix the interrupt cause code
+[PULL 08/28] target/riscv/debug: set tval=pc in breakpoint exceptions
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+We're not setting (s/m)tval when triggering breakpoints of type 2
+(mcontrol) and 6 (mcontrol6). According to the debug spec section
+.7.12, "Match Control Type 6":
+"The Privileged Spec says that breakpoint exceptions that occur on
+instruction fetches, loads, or stores update the tval CSR with either
+zero or the faulting virtual address. The faulting virtual address for
+an mcontrol6 trigger with action = 0 is the address being accessed and
+which caused that trigger to fire."
+A similar text is also found in the Debug spec section 5.7.11 w.r.t.
+mcontrol.
+Note that what we're doing ATM is not violating the spec, but it's
+simple enough to set mtval/stval and it makes life easier for any
+software that relies on this info.
+Given that we always use action = 0, save the faulting address for the
+mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
+used as as scratch area for traps with address information. 'tval' is
+then set during riscv_cpu_do_interrupt().
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com
-Message-Id: <85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 5 +++--
+ target/riscv/cpu_helper.c | 1 +
-file changed, 3 insertions(+), 2 deletions(-)
+ target/riscv/debug.c      | 3 +++
 files changed, 4 insertions(+)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
 @@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+             tval = env->bins;
-             if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
+             break;
-                 !force_hs_execp) {
+         case RISCV_EXCP_BREAKPOINT:
-+                /* Trap to VS mode */
++            tval = env->badaddr;
-                 /*
+             if (cs->watchpoint_hit) {
-                  * See if we need to adjust cause. Yes if its VS mode interrupt
+                 tval = cs->watchpoint_hit->hitaddr;
-                  * no if hypervisor has delegated one of hs mode's interrupt
+                 cs->watchpoint_hit = NULL;
-                  */
+diff --git a/target/riscv/debug.c b/target/riscv/debug.c
-                 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
+index XXXXXXX..XXXXXXX 100644
--                    cause == IRQ_VS_EXT)
+--- a/target/riscv/debug.c
-+                    cause == IRQ_VS_EXT) {
++++ b/target/riscv/debug.c
-                     cause = cause - 1;
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
--                /* Trap to VS mode */
+                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
-+                }
+                     /* check U/S/M bit against current privilege level */
-                 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
+                     if ((ctrl >> 3) & BIT(env->priv)) {
-             } else if (riscv_cpu_virt_enabled(env)) {
++                        env->badaddr = pc;
-                 /* Trap into HS mode, from virt */
+                         return true;
                      }
                  }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                      if (env->virt_enabled) {
                          /* check VU/VS bit against current privilege level */
                          if ((ctrl >> 23) & BIT(env->priv)) {
 +                            env->badaddr = pc;
                              return true;
                          }
                      } else {
                          /* check U/S/M bit against current privilege level */
                          if ((ctrl >> 3) & BIT(env->priv)) {
 +                            env->badaddr = pc;
                              return true;
                          }
                      }
 --
-.28.0
+.45.1

-New patch
+[PULL 09/28] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Privileged spec section 4.1.9 mentions:
+"When a trap is taken into S-mode, stval is written with
+exception-specific information to assist software in handling the trap.
+(...)
+If stval is written with a nonzero value when a breakpoint,
+address-misaligned, access-fault, or page-fault exception occurs on an
+instruction fetch, load, or store, then stval will contain the faulting
+virtual address."
+A similar text is found for mtval in section 3.1.16.
+Setting mtval/stval in this scenario is optional, but some softwares read
+these regs when handling ebreaks.
+Write 'badaddr' in all ebreak breakpoints to write the appropriate
+'tval' during riscv_do_cpu_interrrupt().
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
+file changed, 2 insertions(+)
+diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_privileged.c.inc
++++ b/target/riscv/insn_trans/trans_privileged.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
+         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
+     } else {
++        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
++                      offsetof(CPURISCVState, badaddr));
+         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+     }
+     return true;
+--
+.45.1

-[PULL 10/18] target/riscv: Convert MSTATUS MTL to GVA
+[PULL 10/28] target/riscv: Add support for Zve32x extension
+From: Jason Chien <jason.chien@sifive.com>
+Add support for Zve32x extension and replace some checks for Zve32f with
+Zve32x, since Zve32f depends on Zve32x.
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com
-Message-Id: <9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h   |  5 +++--
+ target/riscv/cpu_cfg.h                  |  1 +
- target/riscv/cpu_helper.c | 24 ++++++++++++++++++++----
+ target/riscv/cpu.c                      |  2 ++
- target/riscv/csr.c        |  6 +++---
+ target/riscv/cpu_helper.c               |  2 +-
-files changed, 26 insertions(+), 9 deletions(-)
+ target/riscv/csr.c                      |  2 +-
  target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
  target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 files changed, 15 insertions(+), 12 deletions(-)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
- #define MSTATUS_TW          0x20000000 /* since: priv-1.10 */
+     bool ext_zhinx;
- #define MSTATUS_TSR         0x40000000 /* since: priv-1.10 */
+     bool ext_zhinxmin;
- #if defined(TARGET_RISCV64)
+     bool ext_zve32f;
--#define MSTATUS_MTL         0x4000000000ULL
++    bool ext_zve32x;
-+#define MSTATUS_GVA         0x4000000000ULL
+     bool ext_zve64f;
- #define MSTATUS_MPV         0x8000000000ULL
+     bool ext_zve64d;
- #elif defined(TARGET_RISCV32)
+     bool ext_zvbb;
--#define MSTATUS_MTL         0x00000040
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
-+#define MSTATUS_GVA         0x00000040
+index XXXXXXX..XXXXXXX 100644
- #define MSTATUS_MPV         0x00000080
+--- a/target/riscv/cpu.c
- #endif
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
-@@ -XXX,XX +XXX,XX @@
+     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
- #define HSTATUS_VTVM         0x00100000
+     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
- #define HSTATUS_VTSR         0x00400000
+     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
- #define HSTATUS_HU           0x00000200
++    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
-+#define HSTATUS_GVA          0x00000040
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
- #define HSTATUS32_WPRI       0xFF8FF87E
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
- #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
      MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
      MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
 +    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
      MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
-         if (riscv_has_ext(env, RVH)) {
+     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
-             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
+     *cs_base = 0;
-+            if ((riscv_cpu_virt_enabled(env) ||
+-    if (cpu->cfg.ext_zve32f) {
-+                 riscv_cpu_two_stage_lookup(env)) && tval) {
++    if (cpu->cfg.ext_zve32x) {
-+                /*
+         /*
-+                 * If we are writing a guest virtual address to stval, set
+          * If env->vl equals to VLMAX, we can use generic vector operation
-+                 * this to 1. If we are trapping to VS we will set this to 0
+          * expanders (GVEC) to accerlate the vector operations.
 +                 * later.
 +                 */
 +                env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1);
 +            } else {
 +                /* For other HS-mode traps, we set this to 0. */
 +                env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
 +            }
 +
              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
                  !force_hs_execp) {
                  /*
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                      cause == IRQ_VS_EXT)
                      cause = cause - 1;
                  /* Trap to VS mode */
 +                env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
              } else if (riscv_cpu_virt_enabled(env)) {
                  /* Trap into HS mode, from virt */
                  riscv_cpu_swap_hypervisor_regs(env);
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
  #ifdef TARGET_RISCV32
              env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
                                         riscv_cpu_virt_enabled(env));
 -            env->mstatush = set_field(env->mstatush, MSTATUS_MTL,
 -                                       riscv_cpu_force_hs_excep_enabled(env));
 +            if (riscv_cpu_virt_enabled(env) && tval) {
 +                env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1);
 +            }
  #else
              env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
                                        riscv_cpu_virt_enabled(env));
 -            env->mstatus = set_field(env->mstatus, MSTATUS_MTL,
 -                                      riscv_cpu_force_hs_excep_enabled(env));
 +            if (riscv_cpu_virt_enabled(env) && tval) {
 +                env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
 +            }
  #endif
              mtval2 = env->guest_phys_fault_addr;
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/csr.c
 +++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
-         MSTATUS_TW;
- #if defined(TARGET_RISCV64)
+ static RISCVException vs(CPURISCVState *env, int csrno)
-     /*
+ {
--     * RV32: MPV and MTL are not in mstatus. The current plan is to
+-    if (riscv_cpu_cfg(env)->ext_zve32f) {
-+     * RV32: MPV and GVA are not in mstatus. The current plan is to
++    if (riscv_cpu_cfg(env)->ext_zve32x) {
-      * add them to mstatush. For now, we just don't support it.
+ #if !defined(CONFIG_USER_ONLY)
-      */
+         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
--    mask |= MSTATUS_MTL | MSTATUS_MPV;
+             return RISCV_EXCP_ILLEGAL_INST;
-+    mask |= MSTATUS_MPV | MSTATUS_GVA;
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
- #endif
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.c
-     mstatus = (mstatus & ~mask) | (val & mask);
++++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-         tlb_flush(env_cpu(env));
+         return;
      }
--    val &= MSTATUS_MPV | MSTATUS_MTL;
+-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-+    val &= MSTATUS_MPV | MSTATUS_GVA;
+-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+-        return;
-     env->mstatush = val;
++    /* The Zve32f extension depends on the Zve32x extension */
 +    if (cpu->cfg.ext_zve32f) {
 +        if (!riscv_has_ext(env, RVF)) {
 +            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
 +            return;
 +        }
 +        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
      }
      if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
      }
 -    /*
 -     * In principle Zve*x would also suffice here, were they supported
 -     * in qemu
 -     */
      if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
           cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
 -         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
 +         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
          error_setg(errp,
                     "Vector crypto extensions require V or Zve* extensions");
          return;
 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/insn_trans/trans_rvv.c.inc
 +++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
  {
      TCGv s1, dst;
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
  {
      TCGv dst;
 -    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
 +    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
          return false;
      }
 --
-.28.0
+.45.1

-[PULL 18/18] target/riscv: Support the Virtual Instruction fault
+[PULL 11/28] target/riscv: Add support for Zve64x extension
+From: Jason Chien <jason.chien@sifive.com>
+Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
+enabling Zve64x enables Zve32x according to their dependency.
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com
-Message-Id: <4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h                 |  6 +++
+ target/riscv/cpu_cfg.h     |  1 +
- target/riscv/helper.h                   |  1 +
+ target/riscv/cpu.c         |  2 ++
- target/riscv/csr.c                      | 64 ++++++++++++++++++++++++-
+ target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
- target/riscv/op_helper.c                | 42 ++++++++++++++--
+files changed, 14 insertions(+), 6 deletions(-)
  target/riscv/insn_trans/trans_rvh.c.inc |  2 +-
 files changed, 109 insertions(+), 6 deletions(-)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
+--- a/target/riscv/cpu_cfg.h
-+++ b/target/riscv/cpu_bits.h
++++ b/target/riscv/cpu_cfg.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
- #define HSTATUS_WPRI HSTATUS64_WPRI
+     bool ext_zve32x;
- #endif
+     bool ext_zve64f;
+     bool ext_zve64d;
-+#define HCOUNTEREN_CY        (1 << 0)
++    bool ext_zve64x;
-+#define HCOUNTEREN_TM        (1 << 1)
+     bool ext_zvbb;
-+#define HCOUNTEREN_IR        (1 << 2)
+     bool ext_zvbc;
-+#define HCOUNTEREN_HPM3      (1 << 3)
+     bool ext_zvkb;
-+
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
  /* Privilege modes */
  #define PRV_U 0
  #define PRV_S 1
@@ -XXX,XX +XXX,XX @@
  #define RISCV_EXCP_STORE_PAGE_FAULT              0xf /* since: priv-1.10.0 */
  #define RISCV_EXCP_INST_GUEST_PAGE_FAULT         0x14
  #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT       0x15
 +#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT        0x16
  #define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT  0x17
  #define RISCV_EXCP_INT_FLAG                0x80000000
 diff --git a/target/riscv/helper.h b/target/riscv/helper.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/helper.h
+--- a/target/riscv/cpu.c
-+++ b/target/riscv/helper.h
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(tlb_flush, void, env)
+@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
- /* Hypervisor functions */
+     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
- #ifndef CONFIG_USER_ONLY
+     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
- DEF_HELPER_1(hyp_tlb_flush, void, env)
+     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
-+DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)
++    ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
- DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
+     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
- DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
+     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
- DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
+     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
      MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
      MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
      MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
 +    MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
      MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
      MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
      MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/tcg/tcg-cpu.c
-+++ b/target/riscv/csr.c
++++ b/target/riscv/tcg/tcg-cpu.c
-@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
-         /* The Counters extensions is not enabled */
-         return -RISCV_EXCP_ILLEGAL_INST;
+     /* The Zve64d extension depends on the Zve64f extension */
      if (cpu->cfg.ext_zve64d) {
 +        if (!riscv_has_ext(env, RVD)) {
 +            error_setg(errp, "Zve64d/V extensions require D extension");
 +            return;
 +        }
          cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
      }
-+
-+    if (riscv_cpu_virt_enabled(env)) {
+-    /* The Zve64f extension depends on the Zve32f extension */
-+        switch (csrno) {
++    /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
-+        case CSR_CYCLE:
+     if (cpu->cfg.ext_zve64f) {
-+            if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
-+                get_field(env->mcounteren, HCOUNTEREN_CY)) {
+         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
 +                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +            }
 +            break;
 +        case CSR_TIME:
 +            if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
 +                get_field(env->mcounteren, HCOUNTEREN_TM)) {
 +                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +            }
 +            break;
 +        case CSR_INSTRET:
 +            if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
 +                get_field(env->mcounteren, HCOUNTEREN_IR)) {
 +                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +            }
 +            break;
 +        case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
 +            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
 +                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
 +                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +            }
 +            break;
 +#if defined(TARGET_RISCV32)
 +        case CSR_CYCLEH:
 +            if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
 +                get_field(env->mcounteren, HCOUNTEREN_CY)) {
 +                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +            }
 +            break;
 +        case CSR_TIMEH:
 +            if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
 +                get_field(env->mcounteren, HCOUNTEREN_TM)) {
 +                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +            }
 +            break;
 +        case CSR_INSTRETH:
 +            if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
 +                get_field(env->mcounteren, HCOUNTEREN_IR)) {
 +                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +            }
 +            break;
 +        case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
 +            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
 +                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
 +                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 +            }
 +            break;
 +#endif
 +        }
 +    }
  #endif
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ static int hmode(CPURISCVState *env, int csrno)
          if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
              env->priv == PRV_M) {
              return 0;
 +        } else {
 +            return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
          }
      }
-@@ -XXX,XX +XXX,XX @@ static const target_ulong delegable_excps =
+-    if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
-     (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
+-        error_setg(errp, "Zve64d/V extensions require D extension");
-     (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
+-        return;
-     (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
++    /* The Zve64x extension depends on the Zve32x extension */
-+    (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
++    if (cpu->cfg.ext_zve64x) {
-     (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
++        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
  static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
      SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
      }
-     /* check predicate */
+     /* The Zve32f extension depends on the Zve32x extension */
--    if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
 +    if (!csr_ops[csrno].predicate) {
          return -RISCV_EXCP_ILLEGAL_INST;
      }
 +    ret = csr_ops[csrno].predicate(env, csrno);
 +    if (ret < 0) {
 +        return ret;
 +    }
      /* execute combined read/write operation if it exists */
      if (csr_ops[csrno].op) {
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
          riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
      }
 +    if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
 +        get_field(env->hstatus, HSTATUS_VTSR)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
 +    }
 +
      mstatus = env->mstatus;
      if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
      if ((env->priv == PRV_S &&
          get_field(env->mstatus, MSTATUS_TW)) ||
          riscv_cpu_virt_enabled(env)) {
 -        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
      } else {
          cs->halted = 1;
          cs->exception_index = EXCP_HLT;
@@ -XXX,XX +XXX,XX @@ void helper_tlb_flush(CPURISCVState *env)
          (env->priv == PRV_S &&
           get_field(env->mstatus, MSTATUS_TVM))) {
          riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
 +               get_field(env->hstatus, HSTATUS_VTVM)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
      } else {
          tlb_flush(cs);
      }
@@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env)
  {
      CPUState *cs = env_cpu(env);
 +    if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
 +    }
 +
      if (env->priv == PRV_M ||
          (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
          tlb_flush(cs);
@@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env)
      riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
  }
 +void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
 +{
 +    if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
 +        get_field(env->mstatus, MSTATUS_TVM)) {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
 +
 +    helper_hyp_tlb_flush(env);
 +}
 +
  target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
                               target_ulong attrs, target_ulong memop)
  {
@@ -XXX,XX +XXX,XX @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
          return pte;
      }
 -    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    if (riscv_cpu_virt_enabled(env)) {
 +        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
 +    } else {
 +        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    }
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ void helper_hyp_store(CPURISCVState *env, target_ulong address,
          return;
      }
--    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+-    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f) {
-+    if (riscv_cpu_virt_enabled(env)) {
++    if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) {
-+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+         error_setg(
-+    } else {
+             errp,
-+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+-            "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions");
-+    }
++            "Zvbc and Zvknhb extensions require V or Zve64x extensions");
- }
+         return;
  target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
@@ -XXX,XX +XXX,XX @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
          return pte;
      }
--    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
-+    if (riscv_cpu_virt_enabled(env)) {
-+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
-+    } else {
-+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
-+    }
-     return 0;
- }
-diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/insn_trans/trans_rvh.c.inc
-+++ b/target/riscv/insn_trans/trans_rvh.c.inc
-@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
- {
-     REQUIRE_EXT(ctx, RVH);
- #ifndef CONFIG_USER_ONLY
--    gen_helper_hyp_tlb_flush(cpu_env);
-+    gen_helper_hyp_gvma_tlb_flush(cpu_env);
-     return true;
- #endif
-     return false;
 --
-.28.0
+.45.1

-New patch
+[PULL 12/28] target/riscv: Relax vector register check in RISCV gdbstub
+From: Jason Chien <jason.chien@sifive.com>
+In current implementation, the gdbstub allows reading vector registers
+only if V extension is supported. However, all vector extensions and
+vector crypto extensions have the vector registers and they all depend
+on Zve32x. The gdbstub should check for Zve32x instead.
+Signed-off-by: Jason Chien <jason.chien@sifive.com>
+Reviewed-by: Frank Chang <frank.chang@sifive.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
+Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/gdbstub.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/gdbstub.c
++++ b/target/riscv/gdbstub.c
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
+                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
+);
+     }
+-    if (env->misa_ext & RVV) {
++    if (cpu->cfg.ext_zve32x) {
+         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
+                                  riscv_gdb_set_vector,
+                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
+--
+.45.1

-New patch
+[PULL 13/28] target/riscv: Fix the element agnostic function problem
+From: Huang Tao <eric.huang@linux.alibaba.com>
+In RVV and vcrypto instructions, the masked and tail elements are set to 1s
+using vext_set_elems_1s function if the vma/vta bit is set. It is the element
+agnostic policy.
+However, this function can't deal the big endian situation. This patch fixes
+the problem by adding handling of such case.
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
+Suggested-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
+file changed, 22 insertions(+)
+diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/vector_internals.c
++++ b/target/riscv/vector_internals.c
+@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
+     if (tot - cnt == 0) {
+         return ;
+     }
++
++    if (HOST_BIG_ENDIAN) {
++        /*
++         * Deal the situation when the elements are insdie
++         * only one uint64 block including setting the
++         * masked-off element.
++         */
++        if (((tot - 1) ^ cnt) < 8) {
++            memset(base + H1(tot - 1), -1, tot - cnt);
++            return;
++        }
++        /*
++         * Otherwise, at least cross two uint64_t blocks.
++         * Set first unaligned block.
++         */
++        if (cnt % 8 != 0) {
++            uint32_t j = ROUND_UP(cnt, 8);
++            memset(base + H1(j - 1), -1, j - cnt);
++            cnt = j;
++        }
++        /* Set other 64bit aligend blocks */
++    }
+     memset(base + cnt, -1, tot - cnt);
+ }
+--
+.45.1

-[PULL 02/18] hw/riscv: Allow creating multiple instances of PLIC
+[PULL 14/28] target/riscv/cpu.c: fix Zvkb extension config
-From: Anup Patel <anup.patel@wdc.com>
+From: Yangyu Chen <cyy@cyyself.name>
-We extend PLIC emulation to allow multiple instances of PLIC in
+This code has a typo that writes zvkb to zvkg, causing users can't
-a QEMU RISC-V machine. To achieve this, we remove first HART id
+enable zvkb through the config. This patch gets this fixed.
 zero assumption from PLIC emulation.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Signed-off-by: Yangyu Chen <cyy@cyyself.name>
-Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
+Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Message-Id: <20200616032229.766089-3-anup.patel@wdc.com>
+Reviewed-by: Max Chou <max.chou@sifive.com>
 Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
 Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/sifive_plic.h | 12 +++++++-----
+ target/riscv/cpu.c | 2 +-
- hw/riscv/sifive_e.c            |  2 +-
+file changed, 1 insertion(+), 1 deletion(-)
  hw/riscv/sifive_plic.c         | 24 +++++++++++++-----------
  hw/riscv/sifive_u.c            |  2 +-
  hw/riscv/virt.c                |  2 +-
 files changed, 23 insertions(+), 19 deletions(-)
-diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_plic.h
+--- a/target/riscv/cpu.c
-+++ b/include/hw/riscv/sifive_plic.h
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@ typedef struct SiFivePLICState {
+@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
-     /*< public >*/
+     /* Vector cryptography extensions */
-     MemoryRegion mmio;
+     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
-     uint32_t num_addrs;
+     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-+    uint32_t num_harts;
+-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
-     uint32_t bitfield_words;
++    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
-     PLICAddr *addr_config;
+     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
-     uint32_t *source_priority;
+     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
-@@ -XXX,XX +XXX,XX @@ typedef struct SiFivePLICState {
+     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
      /* config */
      char *hart_config;
 +    uint32_t hartid_base;
      uint32_t num_sources;
      uint32_t num_priorities;
      uint32_t priority_base;
@@ -XXX,XX +XXX,XX @@ typedef struct SiFivePLICState {
  } SiFivePLICState;
  DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
 -    uint32_t num_sources, uint32_t num_priorities,
 -    uint32_t priority_base, uint32_t pending_base,
 -    uint32_t enable_base, uint32_t enable_stride,
 -    uint32_t context_base, uint32_t context_stride,
 -    uint32_t aperture_size);
 +    uint32_t hartid_base, uint32_t num_sources,
 +    uint32_t num_priorities, uint32_t priority_base,
 +    uint32_t pending_base, uint32_t enable_base,
 +    uint32_t enable_stride, uint32_t context_base,
 +    uint32_t context_stride, uint32_t aperture_size);
  #endif
 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_e.c
 +++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
      /* MMIO */
      s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
 -        (char *)SIFIVE_E_PLIC_HART_CONFIG,
 +        (char *)SIFIVE_E_PLIC_HART_CONFIG, 0,
          SIFIVE_E_PLIC_NUM_SOURCES,
          SIFIVE_E_PLIC_NUM_PRIORITIES,
          SIFIVE_E_PLIC_PRIORITY_BASE,
 diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_plic.c
 +++ b/hw/riscv/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_plic_ops = {
  static Property sifive_plic_properties[] = {
      DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
 +    DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
      DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
      DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
      DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
      }
      hartid++;
 -    /* store hart/mode combinations */
      plic->num_addrs = addrid;
 +    plic->num_harts = hartid;
 +
 +    /* store hart/mode combinations */
      plic->addr_config = g_new(PLICAddr, plic->num_addrs);
 -    addrid = 0, hartid = 0;
 +    addrid = 0, hartid = plic->hartid_base;
      p = plic->hart_config;
      while ((c = *p++)) {
          if (c == ',') {
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
  static void sifive_plic_realize(DeviceState *dev, Error **errp)
  {
 -    MachineState *ms = MACHINE(qdev_get_machine());
 -    unsigned int smp_cpus = ms->smp.cpus;
      SiFivePLICState *plic = SIFIVE_PLIC(dev);
      int i;
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
       * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
       * hardware controlled when a PLIC is attached.
       */
 -    for (i = 0; i < smp_cpus; i++) {
 -        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
 +    for (i = 0; i < plic->num_harts; i++) {
 +        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
          if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
              error_report("SEIP already claimed");
              exit(1);
@@ -XXX,XX +XXX,XX @@ type_init(sifive_plic_register_types)
   * Create PLIC device.
   */
  DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
 -    uint32_t num_sources, uint32_t num_priorities,
 -    uint32_t priority_base, uint32_t pending_base,
 -    uint32_t enable_base, uint32_t enable_stride,
 -    uint32_t context_base, uint32_t context_stride,
 -    uint32_t aperture_size)
 +    uint32_t hartid_base, uint32_t num_sources,
 +    uint32_t num_priorities, uint32_t priority_base,
 +    uint32_t pending_base, uint32_t enable_base,
 +    uint32_t enable_stride, uint32_t context_base,
 +    uint32_t context_stride, uint32_t aperture_size)
  {
      DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
      assert(enable_stride == (enable_stride & -enable_stride));
      assert(context_stride == (context_stride & -context_stride));
      qdev_prop_set_string(dev, "hart-config", hart_config);
 +    qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
      qdev_prop_set_uint32(dev, "num-sources", num_sources);
      qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
      qdev_prop_set_uint32(dev, "priority-base", priority_base);
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
      /* MMIO */
      s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
 -        plic_hart_config,
 +        plic_hart_config, 0,
          SIFIVE_U_PLIC_NUM_SOURCES,
          SIFIVE_U_PLIC_NUM_PRIORITIES,
          SIFIVE_U_PLIC_PRIORITY_BASE,
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      /* MMIO */
      s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
 -        plic_hart_config,
 +        plic_hart_config, 0,
          VIRT_PLIC_NUM_SOURCES,
          VIRT_PLIC_NUM_PRIORITIES,
          VIRT_PLIC_PRIORITY_BASE,
 --
-.28.0
+.45.1

-[PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets
+[PULL 15/28] target/riscv: Implement dynamic establishment of custom decoder
-From: Anup Patel <anup.patel@wdc.com>
+From: Huang Tao <eric.huang@linux.alibaba.com>
-We extend RISC-V spike machine to allow creating a multi-socket
+In this patch, we modify the decoder to be a freely composable data
-machine. Each RISC-V spike machine socket is a NUMA node having
+structure instead of a hardcoded one. It can be dynamically builded up
-a set of HARTs, a memory instance, and a CLINT instance. Other
+according to the extensions.
-devices are shared between all sockets. We also update the
+This approach has several benefits:
-generated device tree accordingly.
+. Provides support for heterogeneous cpu architectures. As we add decoder in
    RISCVCPU, each cpu can have their own decoder, and the decoders can be
    different due to cpu's features.
 . Improve the decoding efficiency. We run the guard_func to see if the decoder
    can be added to the dynamic_decoder when building up the decoder. Therefore,
    there is no need to run the guard_func when decoding each instruction. It can
    improve the decoding efficiency
 . For vendor or dynamic cpus, it allows them to customize their own decoder
    functions to improve decoding efficiency, especially when vendor-defined
    instruction sets increase. Because of dynamic building up, it can skip the other
    decoder guard functions when decoding.
 . Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
    overhead for users that don't need this particular vendor decoder.
-By default, NUMA multi-socket support is disabled for RISC-V spike
+Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
-machine. To enable it, users can use "-numa" command-line options
+Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
-of QEMU.
+Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Example1: For two NUMA nodes with 2 CPUs each, append following
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-to command-line options: "-smp 4 -numa node -numa node"
+Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
 Example2: For two NUMA nodes with 1 and 3 CPUs, append following
 to command-line options:
 "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
 -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
 -numa cpu,node-id=1,core-id=3"
 The maximum number of sockets in a RISC-V spike machine is 8
 but this limit can be changed in future.
 Signed-off-by: Anup Patel <anup.patel@wdc.com>
 Reviewed-by: Atish Patra <atish.patra@wdc.com>
 Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/spike.h |  11 +-
+ target/riscv/cpu.h         |  1 +
- hw/riscv/spike.c         | 232 ++++++++++++++++++++++++++-------------
+ target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
-files changed, 167 insertions(+), 76 deletions(-)
+ target/riscv/cpu.c         |  1 +
  target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
  target/riscv/translate.c   | 31 +++++++++++++++----------------
 files changed, 47 insertions(+), 16 deletions(-)
-diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
+diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/spike.h
+--- a/target/riscv/cpu.h
-+++ b/include/hw/riscv/spike.h
++++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
- #include "hw/riscv/riscv_hart.h"
+     uint32_t pmu_avail_ctrs;
- #include "hw/sysbus.h"
+     /* Mapping of events to counters */
+     GHashTable *pmu_event_ctr_map;
-+#define SPIKE_CPUS_MAX 8
++    const GPtrArray *decoders;
-+#define SPIKE_SOCKETS_MAX 8
+ };
  /**
 diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/tcg/tcg-cpu.h
 +++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
  void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
  bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 +struct DisasContext;
 +struct RISCVCPUConfig;
 +typedef struct RISCVDecoder {
 +    bool (*guard_func)(const struct RISCVCPUConfig *);
 +    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +} RISCVDecoder;
 +
-+#define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike")
++typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
 +#define SPIKE_MACHINE(obj) \
 +    OBJECT_CHECK(SpikeState, (obj), TYPE_SPIKE_MACHINE)
 +
- typedef struct {
++extern const size_t decoder_table_size;
-     /*< private >*/
++
--    SysBusDevice parent_obj;
++extern const RISCVDecoder decoder_table[];
-+    MachineState parent;
++
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
-     /*< public >*/
++
--    RISCVHartArrayState soc;
+ #endif
-+    RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
      void *fdt;
      int fdt_size;
  } SpikeState;
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/spike.c
+--- a/target/riscv/cpu.c
-+++ b/hw/riscv/spike.c
++++ b/target/riscv/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
- #include "hw/riscv/sifive_clint.h"
+             error_propagate(errp, local_err);
- #include "hw/riscv/spike.h"
+             return;
- #include "hw/riscv/boot.h"
+         }
-+#include "hw/riscv/numa.h"
++        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
- #include "chardev/char.h"
+     } else if (kvm_enabled()) {
- #include "sysemu/arch_init.h"
+         riscv_kvm_cpu_finalize_features(cpu, &local_err);
- #include "sysemu/device_tree.h"
+         if (local_err != NULL) {
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
-     uint64_t mem_size, const char *cmdline)
+index XXXXXXX..XXXXXXX 100644
- {
+--- a/target/riscv/tcg/tcg-cpu.c
-     void *fdt;
++++ b/target/riscv/tcg/tcg-cpu.c
--    int cpu;
+@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
--    uint32_t *cells;
+     }
--    char *nodename;
+ }
-+    uint64_t addr, size;
-+    unsigned long clint_addr;
++void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
-+    int cpu, socket;
++{
-+    MachineState *mc = MACHINE(s);
++    GPtrArray *dynamic_decoders;
-+    uint32_t *clint_cells;
++    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
-+    uint32_t cpu_phandle, intc_phandle, phandle = 1;
++    for (size_t i = 0; i < decoder_table_size; ++i) {
-+    char *name, *mem_name, *clint_name, *clust_name;
++        if (decoder_table[i].guard_func &&
-+    char *core_name, *cpu_name, *intc_name;
++            decoder_table[i].guard_func(&cpu->cfg)) {
++            g_ptr_array_add(dynamic_decoders,
-     fdt = s->fdt = create_device_tree(&s->fdt_size);
++                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
      if (!fdt) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
      qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
      qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 -    nodename = g_strdup_printf("/memory@%lx",
 -        (long)memmap[SPIKE_DRAM].base);
 -    qemu_fdt_add_subnode(fdt, nodename);
 -    qemu_fdt_setprop_cells(fdt, nodename, "reg",
 -        memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
 -        mem_size >> 32, mem_size);
 -    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 -    g_free(nodename);
 -
      qemu_fdt_add_subnode(fdt, "/cpus");
      qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
          SIFIVE_CLINT_TIMEBASE_FREQ);
      qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
      qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 +    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
 +
 +    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
 +        clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
 +        qemu_fdt_add_subnode(fdt, clust_name);
 +
 +        clint_cells =  g_new0(uint32_t, s->soc[socket].num_harts * 4);
 -    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 -        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 -        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 -        char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 -        qemu_fdt_add_subnode(fdt, nodename);
 +        for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
 +            cpu_phandle = phandle++;
 +
 +            cpu_name = g_strdup_printf("/cpus/cpu@%d",
 +                s->soc[socket].hartid_base + cpu);
 +            qemu_fdt_add_subnode(fdt, cpu_name);
  #if defined(TARGET_RISCV32)
 -        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
 +            qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
  #else
 -        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 +            qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
  #endif
 -        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 -        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 -        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 -        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 -        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 -        qemu_fdt_add_subnode(fdt, intc);
 -        qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
 -        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 -        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 -        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 -        g_free(isa);
 -        g_free(intc);
 -        g_free(nodename);
 -    }
 +            name = riscv_isa_string(&s->soc[socket].harts[cpu]);
 +            qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
 +            g_free(name);
 +            qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
 +            qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
 +            qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
 +                s->soc[socket].hartid_base + cpu);
 +            qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
 +            riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
 +            qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
 -    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 -    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 -        nodename =
 -            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 -        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 -        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 -        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 -        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 -        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 -        g_free(nodename);
 +            intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
 +            qemu_fdt_add_subnode(fdt, intc_name);
 +            intc_phandle = phandle++;
 +            qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
 +            qemu_fdt_setprop_string(fdt, intc_name, "compatible",
 +                "riscv,cpu-intc");
 +            qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
 +            qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
 +
 +            clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 +            clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 +            clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 +            clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 +
 +            core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
 +            qemu_fdt_add_subnode(fdt, core_name);
 +            qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
 +
 +            g_free(core_name);
 +            g_free(intc_name);
 +            g_free(cpu_name);
 +        }
-+
-+        addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
-+        size = riscv_socket_mem_size(mc, socket);
-+        mem_name = g_strdup_printf("/memory@%lx", (long)addr);
-+        qemu_fdt_add_subnode(fdt, mem_name);
-+        qemu_fdt_setprop_cells(fdt, mem_name, "reg",
-+            addr >> 32, addr, size >> 32, size);
-+        qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
-+        riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
-+        g_free(mem_name);
-+
-+        clint_addr = memmap[SPIKE_CLINT].base +
-+            (memmap[SPIKE_CLINT].size * socket);
-+        clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
-+        qemu_fdt_add_subnode(fdt, clint_name);
-+        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
-+        qemu_fdt_setprop_cells(fdt, clint_name, "reg",
-+            0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
-+        qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
-+            clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
-+        riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
-+
-+        g_free(clint_name);
-+        g_free(clint_cells);
-+        g_free(clust_name);
-     }
--    nodename = g_strdup_printf("/soc/clint@%lx",
--        (long)memmap[SPIKE_CLINT].base);
--    qemu_fdt_add_subnode(fdt, nodename);
--    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
--    qemu_fdt_setprop_cells(fdt, nodename, "reg",
--        0x0, memmap[SPIKE_CLINT].base,
--        0x0, memmap[SPIKE_CLINT].size);
--    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
--        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
--    g_free(cells);
--    g_free(nodename);
-+
-+    riscv_socket_fdt_write_distance_matrix(mc, fdt);
-     if (cmdline) {
-         qemu_fdt_add_subnode(fdt, "/chosen");
-@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
- static void spike_board_init(MachineState *machine)
- {
-     const struct MemmapEntry *memmap = spike_memmap;
--
--    SpikeState *s = g_new0(SpikeState, 1);
-+    SpikeState *s = SPIKE_MACHINE(machine);
-     MemoryRegion *system_memory = get_system_memory();
-     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
-     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
--    unsigned int smp_cpus = machine->smp.cpus;
-     uint32_t fdt_load_addr;
-     uint64_t kernel_entry;
-+    char *soc_name;
-+    int i, base_hartid, hart_count;
--    /* Initialize SOC */
--    object_initialize_child(OBJECT(machine), "soc", &s->soc,
--                            TYPE_RISCV_HART_ARRAY);
--    object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
--                            &error_abort);
--    object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
--                            &error_abort);
--    sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
-+    /* Check socket count limit */
-+    if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
-+        error_report("number of sockets/nodes should be less than %d",
-+            SPIKE_SOCKETS_MAX);
-+        exit(1);
 +    }
 +
-+    /* Initialize sockets */
++    cpu->decoders = dynamic_decoders;
 +    for (i = 0; i < riscv_socket_count(machine); i++) {
 +        if (!riscv_socket_check_hartids(machine, i)) {
 +            error_report("discontinuous hartids in socket%d", i);
 +            exit(1);
 +        }
 +
 +        base_hartid = riscv_socket_first_hartid(machine, i);
 +        if (base_hartid < 0) {
 +            error_report("can't find hartid base for socket%d", i);
 +            exit(1);
 +        }
 +
 +        hart_count = riscv_socket_hart_count(machine, i);
 +        if (hart_count < 0) {
 +            error_report("can't find hart count for socket%d", i);
 +            exit(1);
 +        }
 +
 +        soc_name = g_strdup_printf("soc%d", i);
 +        object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
 +                                TYPE_RISCV_HART_ARRAY);
 +        g_free(soc_name);
 +        object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
 +                                machine->cpu_type, &error_abort);
 +        object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
 +                                base_hartid, &error_abort);
 +        object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
 +                                hart_count, &error_abort);
 +        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
 +
 +        /* Core Local Interruptor (timer and IPI) for each socket */
 +        sifive_clint_create(
 +            memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
 +            memmap[SPIKE_CLINT].size, base_hartid, hart_count,
 +            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
 +    }
      /* register system main memory (actual RAM) */
      memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                                fdt_load_addr, s->fdt);
      /* initialize HTIF using symbols found in load_kernel */
 -    htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
 +    htif_mm_init(system_memory, mask_rom,
 +                 &s->soc[0].harts[0].env, serial_hd(0));
 +}
 -    /* Core Local Interruptor (timer and IPI) */
 -    sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
 -        0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 -        false);
 +static void spike_machine_instance_init(Object *obj)
 +{
  }
 -static void spike_machine_init(MachineClass *mc)
 +static void spike_machine_class_init(ObjectClass *oc, void *data)
  {
 -    mc->desc = "RISC-V Spike Board";
 +    MachineClass *mc = MACHINE_CLASS(oc);
 +
 +    mc->desc = "RISC-V Spike board";
      mc->init = spike_board_init;
 -    mc->max_cpus = 8;
 +    mc->max_cpus = SPIKE_CPUS_MAX;
      mc->is_default = true;
      mc->default_cpu_type = SPIKE_V1_10_0_CPU;
 +    mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
 +    mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
 +    mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
 +    mc->numa_mem_supported = true;
 +}
 +
-+static const TypeInfo spike_machine_typeinfo = {
+ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
-+    .name       = MACHINE_TYPE_NAME("spike"),
+ {
-+    .parent     = TYPE_MACHINE,
+     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
-+    .class_init = spike_machine_class_init,
+diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-+    .instance_init = spike_machine_instance_init,
+index XXXXXXX..XXXXXXX 100644
-+    .instance_size = sizeof(SpikeState),
+--- a/target/riscv/translate.c
 +++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/helper-info.c.inc"
  #undef  HELPER_H
 +#include "tcg/tcg-cpu.h"
 +
  /* global register indices */
  static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
  static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      /* FRM is known to contain a valid value. */
      bool frm_valid;
      bool insn_start_updated;
 +    const GPtrArray *decoders;
  } DisasContext;
  static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
      return (first_word & 3) == 3 ? 4 : 2;
  }
 +const RISCVDecoder decoder_table[] = {
 +    { always_true_p, decode_insn32 },
 +    { has_xthead_p, decode_xthead},
 +    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
 +};
 +
-+static void spike_machine_init_register_types(void)
++const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
-+{
++
-+    type_register_static(&spike_machine_typeinfo);
+ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
  {
 -    /*
 -     * A table with predicate (i.e., guard) functions and decoder functions
 -     * that are tested in-order until a decoder matches onto the opcode.
 -     */
 -    static const struct {
 -        bool (*guard_func)(const RISCVCPUConfig *);
 -        bool (*decode_func)(DisasContext *, uint32_t);
 -    } decoders[] = {
 -        { always_true_p,  decode_insn32 },
 -        { has_xthead_p, decode_xthead },
 -        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
 -    };
 -
      ctx->virt_inst_excp = false;
      ctx->cur_insn_len = insn_len(opcode);
      /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                               ctx->base.pc_next + 2));
          ctx->opcode = opcode32;
 -        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
 -            if (decoders[i].guard_func(ctx->cfg_ptr) &&
 -                decoders[i].decode_func(ctx, opcode32)) {
 +        for (guint i = 0; i < ctx->decoders->len; ++i) {
 +            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
 +            if (func(ctx, opcode32)) {
                  return;
              }
          }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
      ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
      ctx->zero = tcg_constant_tl(0);
      ctx->virt_inst_excp = false;
 +    ctx->decoders = cpu->decoders;
  }
--DEFINE_MACHINE("spike", spike_machine_init)
+ static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 +type_init(spike_machine_init_register_types)
 --
-.28.0
+.45.1

-[PULL 03/18] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
+[PULL 16/28] riscv: thead: Add th.sxstatus CSR emulation
-From: Anup Patel <anup.patel@wdc.com>
+From: Christoph Müllner <christoph.muellner@vrull.eu>
-We add common helper routines which can be shared by RISC-V
+The th.sxstatus CSR can be used to identify available custom extension
-multi-socket NUMA machines.
+on T-Head CPUs. The CSR is documented here:
   https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc
-We have two types of helpers:
+An important property of this patch is, that the th.sxstatus MAEE field
-. riscv_socket_xyz() - These helper assist managing multiple
+is not set (indicating that XTheadMae is not available).
-   sockets irrespective whether QEMU NUMA is enabled/disabled
+XTheadMae is a memory attribute extension (similar to Svpbmt) which is
-. riscv_numa_xyz() - These helpers assist in providing
+implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
-   necessary QEMU machine callbacks for QEMU NUMA emulation
+in PTEs that are marked as reserved. QEMU maintainers prefer to not
 implement XTheadMae, so we need give kernels a mechanism to identify
 if XTheadMae is available in a system or not. And this patch introduces
 this mechanism in QEMU in a way that's compatible with real HW
 (i.e., probing the th.sxstatus.MAEE bit).
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Further context can be found on the list:
-Reviewed-by: Atish Patra <atish.patra@wdc.com>
+https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html
-Message-Id: <20200616032229.766089-4-anup.patel@wdc.com>
 Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
 Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/numa.h | 113 +++++++++++++++++++
+ MAINTAINERS              |  1 +
- hw/riscv/numa.c         | 242 ++++++++++++++++++++++++++++++++++++++++
+ target/riscv/cpu.h       |  3 ++
- hw/riscv/meson.build    |   1 +
+ target/riscv/cpu.c       |  1 +
-files changed, 356 insertions(+)
+ target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
- create mode 100644 include/hw/riscv/numa.h
+ target/riscv/meson.build |  1 +
- create mode 100644 hw/riscv/numa.c
+files changed, 85 insertions(+)
  create mode 100644 target/riscv/th_csr.c
-diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h
+diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
  S: Supported
  F: target/riscv/insn_trans/trans_xthead.c.inc
  F: target/riscv/xthead*.decode
 +F: target/riscv/th_*
  F: disas/riscv-xthead*
  RISC-V XVentanaCondOps extension
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
  uint8_t satp_mode_max_from_map(uint32_t map);
  const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 +/* Implemented in th_csr.c */
 +void th_register_custom_csrs(RISCVCPU *cpu);
 +
  #endif /* RISCV_CPU_H */
 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.c
 +++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
      cpu->cfg.mvendorid = THEAD_VENDOR_ID;
  #ifndef CONFIG_USER_ONLY
      set_satp_mode_max_supported(cpu, VM_1_10_SV39);
 +    th_register_custom_csrs(cpu);
  #endif
      /* inherited from parent obj via riscv_cpu_init() */
 diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/riscv/numa.h
++++ b/target/riscv/th_csr.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * QEMU RISC-V NUMA Helper
++ * T-Head-specific CSRs.
 + *
-+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
++ * Copyright (c) 2024 VRULL GmbH
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#ifndef RISCV_NUMA_H
 +#define RISCV_NUMA_H
 +
 +#include "hw/sysbus.h"
 +#include "sysemu/numa.h"
 +
 +/**
 + * riscv_socket_count:
 + * @ms: pointer to machine state
 + *
 + * Returns: number of sockets for a numa system and 1 for a non-numa system
 + */
 +int riscv_socket_count(const MachineState *ms);
 +
 +/**
 + * riscv_socket_first_hartid:
 + * @ms: pointer to machine state
 + * @socket_id: socket index
 + *
 + * Returns: first hartid for a valid socket and -1 for an invalid socket
 + */
 +int riscv_socket_first_hartid(const MachineState *ms, int socket_id);
 +
 +/**
 + * riscv_socket_last_hartid:
 + * @ms: pointer to machine state
 + * @socket_id: socket index
 + *
 + * Returns: last hartid for a valid socket and -1 for an invalid socket
 + */
 +int riscv_socket_last_hartid(const MachineState *ms, int socket_id);
 +
 +/**
 + * riscv_socket_hart_count:
 + * @ms: pointer to machine state
 + * @socket_id: socket index
 + *
 + * Returns: number of harts for a valid socket and -1 for an invalid socket
 + */
 +int riscv_socket_hart_count(const MachineState *ms, int socket_id);
 +
 +/**
 + * riscv_socket_mem_offset:
 + * @ms: pointer to machine state
 + * @socket_id: socket index
 + *
 + * Returns: offset of ram belonging to given socket
 + */
 +uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id);
 +
 +/**
 + * riscv_socket_mem_size:
 + * @ms: pointer to machine state
 + * @socket_id: socket index
 + *
 + * Returns: size of ram belonging to given socket
 + */
 +uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id);
 +
 +/**
 + * riscv_socket_check_hartids:
 + * @ms: pointer to machine state
 + * @socket_id: socket index
 + *
 + * Returns: true if hardids belonging to given socket are contiguous else false
 + */
 +bool riscv_socket_check_hartids(const MachineState *ms, int socket_id);
 +
 +/**
 + * riscv_socket_fdt_write_id:
 + * @ms: pointer to machine state
 + * @socket_id: socket index
 + *
 + * Write NUMA node-id FDT property for given FDT node
 + */
 +void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
 +                               const char *node_name, int socket_id);
 +
 +/**
 + * riscv_socket_fdt_write_distance_matrix:
 + * @ms: pointer to machine state
 + * @socket_id: socket index
 + *
 + * Write NUMA distance matrix in FDT for given machine
 + */
 +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt);
 +
 +CpuInstanceProperties
 +riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index);
 +
 +int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx);
 +
 +const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms);
 +
 +#endif /* RISCV_NUMA_H */
 diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/riscv/numa.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * QEMU RISC-V NUMA Helper
 + *
 + * Copyright (c) 2020 Western Digital Corporation or its affiliates.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2 or later, as published by the Free Software Foundation.
 + *
 ...
 + * You should have received a copy of the GNU General Public License along with
 + * this program.  If not, see <http://www.gnu.org/licenses/>.
 + */
 +
 +#include "qemu/osdep.h"
-+#include "qemu/units.h"
++#include "cpu.h"
-+#include "qemu/log.h"
++#include "cpu_vendorid.h"
 +#include "qemu/error-report.h"
 +#include "qapi/error.h"
 +#include "hw/boards.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/riscv/numa.h"
 +#include "sysemu/device_tree.h"
 +
-+static bool numa_enabled(const MachineState *ms)
++#define CSR_TH_SXSTATUS 0x5c0
 +
 +/* TH_SXSTATUS bits */
 +#define TH_SXSTATUS_UCME        BIT(16)
 +#define TH_SXSTATUS_MAEE        BIT(21)
 +#define TH_SXSTATUS_THEADISAEE  BIT(22)
 +
 +typedef struct {
 +    int csrno;
 +    int (*insertion_test)(RISCVCPU *cpu);
 +    riscv_csr_operations csr_ops;
 +} riscv_csr;
 +
 +static RISCVException smode(CPURISCVState *env, int csrno)
 +{
-+    return (ms->numa_state && ms->numa_state->num_nodes) ? true : false;
++    if (riscv_has_ext(env, RVS)) {
 +        return RISCV_EXCP_NONE;
 +    }
 +
 +    return RISCV_EXCP_ILLEGAL_INST;
 +}
 +
-+int riscv_socket_count(const MachineState *ms)
++static int test_thead_mvendorid(RISCVCPU *cpu)
 +{
-+    return (numa_enabled(ms)) ? ms->numa_state->num_nodes : 1;
++    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
 +}
 +
 +int riscv_socket_first_hartid(const MachineState *ms, int socket_id)
 +{
 +    int i, first_hartid = ms->smp.cpus;
 +
 +    if (!numa_enabled(ms)) {
 +        return (!socket_id) ? 0 : -1;
 +    }
 +
 +    for (i = 0; i < ms->smp.cpus; i++) {
 +        if (ms->possible_cpus->cpus[i].props.node_id != socket_id) {
 +            continue;
 +        }
 +        if (i < first_hartid) {
 +            first_hartid = i;
 +        }
 +    }
 +
 +    return (first_hartid < ms->smp.cpus) ? first_hartid : -1;
 +}
 +
 +int riscv_socket_last_hartid(const MachineState *ms, int socket_id)
 +{
 +    int i, last_hartid = -1;
 +
 +    if (!numa_enabled(ms)) {
 +        return (!socket_id) ? ms->smp.cpus - 1 : -1;
 +    }
 +
 +    for (i = 0; i < ms->smp.cpus; i++) {
 +        if (ms->possible_cpus->cpus[i].props.node_id != socket_id) {
 +            continue;
 +        }
 +        if (i > last_hartid) {
 +            last_hartid = i;
 +        }
 +    }
 +
 +    return (last_hartid < ms->smp.cpus) ? last_hartid : -1;
 +}
 +
 +int riscv_socket_hart_count(const MachineState *ms, int socket_id)
 +{
 +    int first_hartid, last_hartid;
 +
 +    if (!numa_enabled(ms)) {
 +        return (!socket_id) ? ms->smp.cpus : -1;
 +    }
 +
 +    first_hartid = riscv_socket_first_hartid(ms, socket_id);
 +    if (first_hartid < 0) {
 +        return -1;
 +    }
 +
-+    last_hartid = riscv_socket_last_hartid(ms, socket_id);
++    return 0;
 +    if (last_hartid < 0) {
 +        return -1;
 +    }
 +
 +    if (first_hartid > last_hartid) {
 +        return -1;
 +    }
 +
 +    return last_hartid - first_hartid + 1;
 +}
 +
-+bool riscv_socket_check_hartids(const MachineState *ms, int socket_id)
++static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
 +                                       target_ulong *val)
 +{
-+    int i, first_hartid, last_hartid;
++    /* We don't set MAEE here, because QEMU does not implement MAEE. */
 +    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
 +    return RISCV_EXCP_NONE;
 +}
 +
-+    if (!numa_enabled(ms)) {
++static riscv_csr th_csr_list[] = {
-+        return (!socket_id) ? true : false;
++    {
 +        .csrno = CSR_TH_SXSTATUS,
 +        .insertion_test = test_thead_mvendorid,
 +        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
 +    }
++};
 +
-+    first_hartid = riscv_socket_first_hartid(ms, socket_id);
++void th_register_custom_csrs(RISCVCPU *cpu)
-+    if (first_hartid < 0) {
++{
-+        return false;
++    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
-+    }
++        int csrno = th_csr_list[i].csrno;
-+
++        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
-+    last_hartid = riscv_socket_last_hartid(ms, socket_id);
++        if (!th_csr_list[i].insertion_test(cpu)) {
-+    if (last_hartid < 0) {
++            riscv_set_csr_ops(csrno, csr_ops);
 +        return false;
 +    }
 +
 +    for (i = first_hartid; i <= last_hartid; i++) {
 +        if (ms->possible_cpus->cpus[i].props.node_id != socket_id) {
 +            return false;
 +        }
 +    }
-+
-+    return true;
 +}
-+
+diff --git a/target/riscv/meson.build b/target/riscv/meson.build
 +uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id)
 +{
 +    int i;
 +    uint64_t mem_offset = 0;
 +
 +    if (!numa_enabled(ms)) {
 +        return 0;
 +    }
 +
 +    for (i = 0; i < ms->numa_state->num_nodes; i++) {
 +        if (i == socket_id) {
 +            break;
 +        }
 +        mem_offset += ms->numa_state->nodes[i].node_mem;
 +    }
 +
 +    return (i == socket_id) ? mem_offset : 0;
 +}
 +
 +uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id)
 +{
 +    if (!numa_enabled(ms)) {
 +        return (!socket_id) ? ms->ram_size : 0;
 +    }
 +
 +    return (socket_id < ms->numa_state->num_nodes) ?
 +            ms->numa_state->nodes[socket_id].node_mem : 0;
 +}
 +
 +void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
 +                               const char *node_name, int socket_id)
 +{
 +    if (numa_enabled(ms)) {
 +        qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id);
 +    }
 +}
 +
 +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt)
 +{
 +    int i, j, idx;
 +    uint32_t *dist_matrix, dist_matrix_size;
 +
 +    if (numa_enabled(ms) && ms->numa_state->have_numa_distance) {
 +        dist_matrix_size = riscv_socket_count(ms) * riscv_socket_count(ms);
 +        dist_matrix_size *= (3 * sizeof(uint32_t));
 +        dist_matrix = g_malloc0(dist_matrix_size);
 +
 +        for (i = 0; i < riscv_socket_count(ms); i++) {
 +            for (j = 0; j < riscv_socket_count(ms); j++) {
 +                idx = (i * riscv_socket_count(ms) + j) * 3;
 +                dist_matrix[idx + 0] = cpu_to_be32(i);
 +                dist_matrix[idx + 1] = cpu_to_be32(j);
 +                dist_matrix[idx + 2] =
 +                    cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
 +            }
 +        }
 +
 +        qemu_fdt_add_subnode(fdt, "/distance-map");
 +        qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
 +                                "numa-distance-map-v1");
 +        qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
 +                         dist_matrix, dist_matrix_size);
 +        g_free(dist_matrix);
 +    }
 +}
 +
 +CpuInstanceProperties
 +riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
 +{
 +    MachineClass *mc = MACHINE_GET_CLASS(ms);
 +    const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
 +
 +    assert(cpu_index < possible_cpus->len);
 +    return possible_cpus->cpus[cpu_index].props;
 +}
 +
 +int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx)
 +{
 +    int64_t nidx = 0;
 +
 +    if (ms->numa_state->num_nodes) {
 +        nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
 +        if (ms->numa_state->num_nodes <= nidx) {
 +            nidx = ms->numa_state->num_nodes - 1;
 +        }
 +    }
 +
 +    return nidx;
 +}
 +
 +const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms)
 +{
 +    int n;
 +    unsigned int max_cpus = ms->smp.max_cpus;
 +
 +    if (ms->possible_cpus) {
 +        assert(ms->possible_cpus->len == max_cpus);
 +        return ms->possible_cpus;
 +    }
 +
 +    ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
 +                                  sizeof(CPUArchId) * max_cpus);
 +    ms->possible_cpus->len = max_cpus;
 +    for (n = 0; n < ms->possible_cpus->len; n++) {
 +        ms->possible_cpus->cpus[n].type = ms->cpu_type;
 +        ms->possible_cpus->cpus[n].arch_id = n;
 +        ms->possible_cpus->cpus[n].props.has_core_id = true;
 +        ms->possible_cpus->cpus[n].props.core_id = n;
 +    }
 +
 +    return ms->possible_cpus;
 +}
 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
 index XXXXXXX..XXXXXXX 100644
---- a/hw/riscv/meson.build
+--- a/target/riscv/meson.build
-+++ b/hw/riscv/meson.build
++++ b/target/riscv/meson.build
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
- riscv_ss = ss.source_set()
+   'monitor.c',
- riscv_ss.add(files('boot.c'))
+   'machine.c',
-+riscv_ss.add(files('numa.c'))
+   'pmu.c',
- riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
++  'th_csr.c',
- riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
+   'time_helper.c',
- riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
+   'riscv-qmp-cmds.c',
  ))
 --
-.28.0
+.45.1

-[PULL 05/18] hw/riscv: virt: Allow creating multiple NUMA sockets
+[PULL 17/28] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
-From: Anup Patel <anup.patel@wdc.com>
+From: Max Chou <max.chou@sifive.com>
-We extend RISC-V virt machine to allow creating a multi-socket
+According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
-machine. Each RISC-V virt machine socket is a NUMA node having
+instructions will be affected by Zvfhmin extension.
-a set of HARTs, a memory instance, a CLINT instance, and a PLIC
+And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
-instance. Other devices are shared between all sockets. We also
+conversions of
 update the generated device tree accordingly.
-By default, NUMA multi-socket support is disabled for RISC-V virt
+* From 1*SEW(16/32) to 2*SEW(32/64)
-machine. To enable it, users can use "-numa" command-line options
+* From 2*SEW(32/64) to 1*SEW(16/32)
 of QEMU.
-Example1: For two NUMA nodes with 2 CPUs each, append following
+Signed-off-by: Max Chou <max.chou@sifive.com>
-to command-line options: "-smp 4 -numa node -numa node"
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Example2: For two NUMA nodes with 1 and 3 CPUs, append following
+Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
 to command-line options:
 "-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
 -numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
 -numa cpu,node-id=1,core-id=3"
 The maximum number of sockets in a RISC-V virt machine is 8
 but this limit can be changed in future.
 Signed-off-by: Anup Patel <anup.patel@wdc.com>
 Reviewed-by: Atish Patra <atish.patra@wdc.com>
 Message-Id: <20200616032229.766089-6-anup.patel@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/virt.h |   9 +-
+ target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
- hw/riscv/virt.c         | 526 +++++++++++++++++++++++-----------------
+file changed, 18 insertions(+), 2 deletions(-)
 files changed, 306 insertions(+), 229 deletions(-)
-diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/virt.h
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/include/hw/riscv/virt.h
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static bool require_rvf(DisasContext *s)
  #include "hw/sysbus.h"
  #include "hw/block/flash.h"
 +#define VIRT_CPUS_MAX 8
 +#define VIRT_SOCKETS_MAX 8
 +
  #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
  #define RISCV_VIRT_MACHINE(obj) \
      OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE)
@@ -XXX,XX +XXX,XX @@ typedef struct {
      MachineState parent;
      /*< public >*/
 -    RISCVHartArrayState soc;
 -    DeviceState *plic;
 +    RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
 +    DeviceState *plic[VIRT_SOCKETS_MAX];
      PFlashCFI01 *flash[2];
      void *fdt;
@@ -XXX,XX +XXX,XX @@ enum {
  #define VIRT_PLIC_ENABLE_STRIDE 0x80
  #define VIRT_PLIC_CONTEXT_BASE 0x200000
  #define VIRT_PLIC_CONTEXT_STRIDE 0x1000
 +#define VIRT_PLIC_SIZE(__num_context) \
 +    (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
  #define FDT_PCI_ADDR_CELLS    3
  #define FDT_PCI_INT_CELLS     1
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/riscv/sifive_test.h"
  #include "hw/riscv/virt.h"
  #include "hw/riscv/boot.h"
 +#include "hw/riscv/numa.h"
  #include "chardev/char.h"
  #include "sysemu/arch_init.h"
  #include "sysemu/device_tree.h"
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
      [VIRT_RTC] =         {   0x101000,        0x1000 },
      [VIRT_CLINT] =       {  0x2000000,       0x10000 },
      [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
 -    [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
 +    [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
      [VIRT_UART0] =       { 0x10000000,         0x100 },
      [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
      [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
      uint64_t mem_size, const char *cmdline)
  {
      void *fdt;
 -    int cpu, i;
 -    uint32_t *cells;
 -    char *nodename;
 -    uint32_t plic_phandle, test_phandle, phandle = 1;
 +    int i, cpu, socket;
 +    MachineState *mc = MACHINE(s);
 +    uint64_t addr, size;
 +    uint32_t *clint_cells, *plic_cells;
 +    unsigned long clint_addr, plic_addr;
 +    uint32_t plic_phandle[MAX_NODES];
 +    uint32_t cpu_phandle, intc_phandle, test_phandle;
 +    uint32_t phandle = 1, plic_mmio_phandle = 1;
 +    uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
 +    char *mem_name, *cpu_name, *core_name, *intc_name;
 +    char *name, *clint_name, *plic_name, *clust_name;
      hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
      hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
      qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
      qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 -    nodename = g_strdup_printf("/memory@%lx",
 -        (long)memmap[VIRT_DRAM].base);
 -    qemu_fdt_add_subnode(fdt, nodename);
 -    qemu_fdt_setprop_cells(fdt, nodename, "reg",
 -        memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
 -        mem_size >> 32, mem_size);
 -    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 -    g_free(nodename);
 -
      qemu_fdt_add_subnode(fdt, "/cpus");
      qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
                            SIFIVE_CLINT_TIMEBASE_FREQ);
      qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
      qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 +    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
 +
 +    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
 +        clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
 +        qemu_fdt_add_subnode(fdt, clust_name);
 +
 +        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
 +        clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
 +
 +        for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
 +            cpu_phandle = phandle++;
 -    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 -        int cpu_phandle = phandle++;
 -        int intc_phandle;
 -        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 -        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 -        char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 -        qemu_fdt_add_subnode(fdt, nodename);
 +            cpu_name = g_strdup_printf("/cpus/cpu@%d",
 +                s->soc[socket].hartid_base + cpu);
 +            qemu_fdt_add_subnode(fdt, cpu_name);
  #if defined(TARGET_RISCV32)
 -        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
 +            qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
  #else
 -        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 +            qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
  #endif
 -        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 -        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 -        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 -        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 -        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 -        qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
 -        intc_phandle = phandle++;
 -        qemu_fdt_add_subnode(fdt, intc);
 -        qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
 -        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 -        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 -        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 -        g_free(isa);
 -        g_free(intc);
 -        g_free(nodename);
 -    }
 +            name = riscv_isa_string(&s->soc[socket].harts[cpu]);
 +            qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
 +            g_free(name);
 +            qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
 +            qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
 +            qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
 +                s->soc[socket].hartid_base + cpu);
 +            qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
 +            riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
 +            qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
 +
 +            intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
 +            qemu_fdt_add_subnode(fdt, intc_name);
 +            intc_phandle = phandle++;
 +            qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
 +            qemu_fdt_setprop_string(fdt, intc_name, "compatible",
 +                "riscv,cpu-intc");
 +            qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
 +            qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
 +
 +            clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 +            clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 +            clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 +            clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 +
 +            plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 +            plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 +            plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 +            plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 +
 +            core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
 +            qemu_fdt_add_subnode(fdt, core_name);
 +            qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
 +
 +            g_free(core_name);
 +            g_free(intc_name);
 +            g_free(cpu_name);
 +        }
 -    /* Add cpu-topology node */
 -    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
 -    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
 -    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 -        char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
 -                                              cpu);
 -        char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 -        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
 -        qemu_fdt_add_subnode(fdt, core_nodename);
 -        qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
 -        g_free(core_nodename);
 -        g_free(cpu_nodename);
 +        addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
 +        size = riscv_socket_mem_size(mc, socket);
 +        mem_name = g_strdup_printf("/memory@%lx", (long)addr);
 +        qemu_fdt_add_subnode(fdt, mem_name);
 +        qemu_fdt_setprop_cells(fdt, mem_name, "reg",
 +            addr >> 32, addr, size >> 32, size);
 +        qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
 +        riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
 +        g_free(mem_name);
 +
 +        clint_addr = memmap[VIRT_CLINT].base +
 +            (memmap[VIRT_CLINT].size * socket);
 +        clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
 +        qemu_fdt_add_subnode(fdt, clint_name);
 +        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
 +        qemu_fdt_setprop_cells(fdt, clint_name, "reg",
 +            0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
 +        qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
 +            clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
 +        riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
 +        g_free(clint_name);
 +
 +        plic_phandle[socket] = phandle++;
 +        plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
 +        plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
 +        qemu_fdt_add_subnode(fdt, plic_name);
 +        qemu_fdt_setprop_cell(fdt, plic_name,
 +            "#address-cells", FDT_PLIC_ADDR_CELLS);
 +        qemu_fdt_setprop_cell(fdt, plic_name,
 +            "#interrupt-cells", FDT_PLIC_INT_CELLS);
 +        qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
 +        qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
 +        qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
 +            plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
 +        qemu_fdt_setprop_cells(fdt, plic_name, "reg",
 +            0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
 +        qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
 +        riscv_socket_fdt_write_id(mc, fdt, plic_name, socket);
 +        qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]);
 +        g_free(plic_name);
 +
 +        g_free(clint_cells);
 +        g_free(plic_cells);
 +        g_free(clust_name);
      }
--    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
--    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
--        nodename =
--            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
--        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
--        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
--        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
--        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
--        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
--        g_free(nodename);
--    }
--    nodename = g_strdup_printf("/soc/clint@%lx",
--        (long)memmap[VIRT_CLINT].base);
--    qemu_fdt_add_subnode(fdt, nodename);
--    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
--    qemu_fdt_setprop_cells(fdt, nodename, "reg",
--        0x0, memmap[VIRT_CLINT].base,
--        0x0, memmap[VIRT_CLINT].size);
--    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
--        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
--    g_free(cells);
--    g_free(nodename);
--
--    plic_phandle = phandle++;
--    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
--    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
--        nodename =
--            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
--        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
--        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
--        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
--        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
--        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
--        g_free(nodename);
-+    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
-+        if (socket == 0) {
-+            plic_mmio_phandle = plic_phandle[socket];
-+            plic_virtio_phandle = plic_phandle[socket];
-+            plic_pcie_phandle = plic_phandle[socket];
-+        }
-+        if (socket == 1) {
-+            plic_virtio_phandle = plic_phandle[socket];
-+            plic_pcie_phandle = plic_phandle[socket];
-+        }
-+        if (socket == 2) {
-+            plic_pcie_phandle = plic_phandle[socket];
-+        }
-     }
--    nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
--        (long)memmap[VIRT_PLIC].base);
--    qemu_fdt_add_subnode(fdt, nodename);
--    qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
--                          FDT_PLIC_ADDR_CELLS);
--    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
--                          FDT_PLIC_INT_CELLS);
--    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
--    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
--    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
--        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
--    qemu_fdt_setprop_cells(fdt, nodename, "reg",
--        0x0, memmap[VIRT_PLIC].base,
--        0x0, memmap[VIRT_PLIC].size);
--    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
--    qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
--    plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
--    g_free(cells);
--    g_free(nodename);
-+
-+    riscv_socket_fdt_write_distance_matrix(mc, fdt);
-     for (i = 0; i < VIRTIO_COUNT; i++) {
--        nodename = g_strdup_printf("/virtio_mmio@%lx",
-+        name = g_strdup_printf("/soc/virtio_mmio@%lx",
-             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
--        qemu_fdt_add_subnode(fdt, nodename);
--        qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
--        qemu_fdt_setprop_cells(fdt, nodename, "reg",
-+        qemu_fdt_add_subnode(fdt, name);
-+        qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
-+        qemu_fdt_setprop_cells(fdt, name, "reg",
-x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
-x0, memmap[VIRT_VIRTIO].size);
--        qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
--        qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
--        g_free(nodename);
-+        qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
-+            plic_virtio_phandle);
-+        qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
-+        g_free(name);
-     }
--    nodename = g_strdup_printf("/soc/pci@%lx",
-+    name = g_strdup_printf("/soc/pci@%lx",
-         (long) memmap[VIRT_PCIE_ECAM].base);
--    qemu_fdt_add_subnode(fdt, nodename);
--    qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
--                          FDT_PCI_ADDR_CELLS);
--    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
--                          FDT_PCI_INT_CELLS);
--    qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
--    qemu_fdt_setprop_string(fdt, nodename, "compatible",
--                            "pci-host-ecam-generic");
--    qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
--    qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
--    qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
--                           memmap[VIRT_PCIE_ECAM].size /
--                               PCIE_MMCFG_SIZE_MIN - 1);
--    qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
--    qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
--                           0, memmap[VIRT_PCIE_ECAM].size);
--    qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
-+    qemu_fdt_add_subnode(fdt, name);
-+    qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
-+    qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
-+    qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
-+    qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
-+    qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
-+    qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
-+    qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
-+        memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
-+    qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
-+    qemu_fdt_setprop_cells(fdt, name, "reg", 0,
-+        memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
-+    qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
-, FDT_PCI_RANGE_IOPORT, 2, 0,
-, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
-, FDT_PCI_RANGE_MMIO,
-, memmap[VIRT_PCIE_MMIO].base,
-, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
--    create_pcie_irq_map(fdt, nodename, plic_phandle);
--    g_free(nodename);
-+    create_pcie_irq_map(fdt, name, plic_pcie_phandle);
-+    g_free(name);
-     test_phandle = phandle++;
--    nodename = g_strdup_printf("/test@%lx",
-+    name = g_strdup_printf("/soc/test@%lx",
-         (long)memmap[VIRT_TEST].base);
--    qemu_fdt_add_subnode(fdt, nodename);
-+    qemu_fdt_add_subnode(fdt, name);
-     {
-         const char compat[] = "sifive,test1\0sifive,test0\0syscon";
--        qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compat));
-+        qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat));
-     }
--    qemu_fdt_setprop_cells(fdt, nodename, "reg",
-+    qemu_fdt_setprop_cells(fdt, name, "reg",
-x0, memmap[VIRT_TEST].base,
-x0, memmap[VIRT_TEST].size);
--    qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle);
--    test_phandle = qemu_fdt_get_phandle(fdt, nodename);
--    g_free(nodename);
--
--    nodename = g_strdup_printf("/reboot");
--    qemu_fdt_add_subnode(fdt, nodename);
--    qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
--    qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
--    qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
--    qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
--    g_free(nodename);
--
--    nodename = g_strdup_printf("/poweroff");
--    qemu_fdt_add_subnode(fdt, nodename);
--    qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
--    qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
--    qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
--    qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
--    g_free(nodename);
--
--    nodename = g_strdup_printf("/uart@%lx",
--        (long)memmap[VIRT_UART0].base);
--    qemu_fdt_add_subnode(fdt, nodename);
--    qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
--    qemu_fdt_setprop_cells(fdt, nodename, "reg",
-+    qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
-+    test_phandle = qemu_fdt_get_phandle(fdt, name);
-+    g_free(name);
-+
-+    name = g_strdup_printf("/soc/reboot");
-+    qemu_fdt_add_subnode(fdt, name);
-+    qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
-+    qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
-+    qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
-+    qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
-+    g_free(name);
-+
-+    name = g_strdup_printf("/soc/poweroff");
-+    qemu_fdt_add_subnode(fdt, name);
-+    qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
-+    qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
-+    qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
-+    qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
-+    g_free(name);
-+
-+    name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
-+    qemu_fdt_add_subnode(fdt, name);
-+    qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
-+    qemu_fdt_setprop_cells(fdt, name, "reg",
-x0, memmap[VIRT_UART0].base,
-x0, memmap[VIRT_UART0].size);
--    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
--    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
--    qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
-+    qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
-+    qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
-+    qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ);
-     qemu_fdt_add_subnode(fdt, "/chosen");
--    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
-+    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
-     if (cmdline) {
-         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
-     }
--    g_free(nodename);
--
--    nodename = g_strdup_printf("/rtc@%lx",
--        (long)memmap[VIRT_RTC].base);
--    qemu_fdt_add_subnode(fdt, nodename);
--    qemu_fdt_setprop_string(fdt, nodename, "compatible",
--        "google,goldfish-rtc");
--    qemu_fdt_setprop_cells(fdt, nodename, "reg",
-+    g_free(name);
-+
-+    name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
-+    qemu_fdt_add_subnode(fdt, name);
-+    qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
-+    qemu_fdt_setprop_cells(fdt, name, "reg",
-x0, memmap[VIRT_RTC].base,
-x0, memmap[VIRT_RTC].size);
--    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
--    qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ);
--    g_free(nodename);
--
--    nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
--    qemu_fdt_add_subnode(s->fdt, nodename);
--    qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash");
--    qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
-+    qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
-+    qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
-+    g_free(name);
-+
-+    name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
-+    qemu_fdt_add_subnode(s->fdt, name);
-+    qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash");
-+    qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
-, flashbase, 2, flashsize,
-, flashbase + flashsize, 2, flashsize);
--    qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4);
--    g_free(nodename);
-+    qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4);
-+    g_free(name);
  }
--
++static bool require_rvfmin(DisasContext *s)
- static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
++{
-                                           hwaddr ecam_base, hwaddr ecam_size,
++    if (s->mstatus_fs == EXT_STATUS_DISABLED) {
-                                           hwaddr mmio_base, hwaddr mmio_size,
++        return false;
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
      MemoryRegion *system_memory = get_system_memory();
      MemoryRegion *main_mem = g_new(MemoryRegion, 1);
      MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
 -    char *plic_hart_config;
 +    char *plic_hart_config, *soc_name;
      size_t plic_hart_config_len;
      target_ulong start_addr = memmap[VIRT_DRAM].base;
      uint32_t fdt_load_addr;
      uint64_t kernel_entry;
 -    int i;
 -    unsigned int smp_cpus = machine->smp.cpus;
 +    DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
 +    int i, j, base_hartid, hart_count;
 -    /* Initialize SOC */
 -    object_initialize_child(OBJECT(machine), "soc", &s->soc,
 -                            TYPE_RISCV_HART_ARRAY);
 -    object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
 -                            &error_abort);
 -    object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
 -                            &error_abort);
 -    sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
 +    /* Check socket count limit */
 +    if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
 +        error_report("number of sockets/nodes should be less than %d",
 +            VIRT_SOCKETS_MAX);
 +        exit(1);
 +    }
 +
-+    /* Initialize sockets */
++    switch (s->sew) {
-+    mmio_plic = virtio_plic = pcie_plic = NULL;
++    case MO_16:
-+    for (i = 0; i < riscv_socket_count(machine); i++) {
++        return s->cfg_ptr->ext_zvfhmin;
-+        if (!riscv_socket_check_hartids(machine, i)) {
++    case MO_32:
-+            error_report("discontinuous hartids in socket%d", i);
++        return s->cfg_ptr->ext_zve32f;
-+            exit(1);
++    default:
-+        }
++        return false;
 +    }
 +}
 +
-+        base_hartid = riscv_socket_first_hartid(machine, i);
+ static bool require_scale_rvf(DisasContext *s)
-+        if (base_hartid < 0) {
+ {
-+            error_report("can't find hartid base for socket%d", i);
+     if (s->mstatus_fs == EXT_STATUS_DISABLED) {
-+            exit(1);
+@@ -XXX,XX +XXX,XX @@ static bool require_scale_rvfmin(DisasContext *s)
 +        }
 +
 +        hart_count = riscv_socket_hart_count(machine, i);
 +        if (hart_count < 0) {
 +            error_report("can't find hart count for socket%d", i);
 +            exit(1);
 +        }
 +
 +        soc_name = g_strdup_printf("soc%d", i);
 +        object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
 +                                TYPE_RISCV_HART_ARRAY);
 +        g_free(soc_name);
 +        object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
 +                                machine->cpu_type, &error_abort);
 +        object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
 +                                base_hartid, &error_abort);
 +        object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
 +                                hart_count, &error_abort);
 +        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
 +
 +        /* Per-socket CLINT */
 +        sifive_clint_create(
 +            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
 +            memmap[VIRT_CLINT].size, base_hartid, hart_count,
 +            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
 +
 +        /* Per-socket PLIC hart topology configuration string */
 +        plic_hart_config_len =
 +            (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
 +        plic_hart_config = g_malloc0(plic_hart_config_len);
 +        for (j = 0; j < hart_count; j++) {
 +            if (j != 0) {
 +                strncat(plic_hart_config, ",", plic_hart_config_len);
 +            }
 +            strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
 +                plic_hart_config_len);
 +            plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
 +        }
 +
 +        /* Per-socket PLIC */
 +        s->plic[i] = sifive_plic_create(
 +            memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
 +            plic_hart_config, base_hartid,
 +            VIRT_PLIC_NUM_SOURCES,
 +            VIRT_PLIC_NUM_PRIORITIES,
 +            VIRT_PLIC_PRIORITY_BASE,
 +            VIRT_PLIC_PENDING_BASE,
 +            VIRT_PLIC_ENABLE_BASE,
 +            VIRT_PLIC_ENABLE_STRIDE,
 +            VIRT_PLIC_CONTEXT_BASE,
 +            VIRT_PLIC_CONTEXT_STRIDE,
 +            memmap[VIRT_PLIC].size);
 +        g_free(plic_hart_config);
 +
 +        /* Try to use different PLIC instance based device type */
 +        if (i == 0) {
 +            mmio_plic = s->plic[i];
 +            virtio_plic = s->plic[i];
 +            pcie_plic = s->plic[i];
 +        }
 +        if (i == 1) {
 +            virtio_plic = s->plic[i];
 +            pcie_plic = s->plic[i];
 +        }
 +        if (i == 2) {
 +            pcie_plic = s->plic[i];
 +        }
 +    }
      /* register system main memory (actual RAM) */
      memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                virt_memmap[VIRT_MROM].size, kernel_entry,
                                fdt_load_addr, s->fdt);
 -    /* create PLIC hart topology configuration string */
 -    plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
 -    plic_hart_config = g_malloc0(plic_hart_config_len);
 -    for (i = 0; i < smp_cpus; i++) {
 -        if (i != 0) {
 -            strncat(plic_hart_config, ",", plic_hart_config_len);
 -        }
 -        strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
 -        plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
 -    }
 -
 -    /* MMIO */
 -    s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
 -        plic_hart_config, 0,
 -        VIRT_PLIC_NUM_SOURCES,
 -        VIRT_PLIC_NUM_PRIORITIES,
 -        VIRT_PLIC_PRIORITY_BASE,
 -        VIRT_PLIC_PENDING_BASE,
 -        VIRT_PLIC_ENABLE_BASE,
 -        VIRT_PLIC_ENABLE_STRIDE,
 -        VIRT_PLIC_CONTEXT_BASE,
 -        VIRT_PLIC_CONTEXT_STRIDE,
 -        memmap[VIRT_PLIC].size);
 -    sifive_clint_create(memmap[VIRT_CLINT].base,
 -        memmap[VIRT_CLINT].size, 0, smp_cpus,
 -        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
 +    /* SiFive Test MMIO device */
      sifive_test_create(memmap[VIRT_TEST].base);
 +    /* VirtIO MMIO devices */
      for (i = 0; i < VIRTIO_COUNT; i++) {
          sysbus_create_simple("virtio-mmio",
              memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
 -            qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
 +            qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
      }
-     gpex_pcie_init(system_memory,
+     switch (s->sew) {
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
+-    case MO_8:
-                          memmap[VIRT_PCIE_MMIO].base,
+-        return s->cfg_ptr->ext_zvfhmin;
-                          memmap[VIRT_PCIE_MMIO].size,
+     case MO_16:
-                          memmap[VIRT_PCIE_PIO].base,
+         return s->cfg_ptr->ext_zve32f;
--                         DEVICE(s->plic), true);
+     case MO_32:
-+                         DEVICE(pcie_plic), true);
+@@ -XXX,XX +XXX,XX @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
+ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
-     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
+ {
--        0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
+     return opfv_widen_check(s, a) &&
-+        0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
++           require_rvfmin(s) &&
-         serial_hd(0), DEVICE_LITTLE_ENDIAN);
+            require_scale_rvfmin(s) &&
+            (s->sew != MO_8);
      sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
 -        qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ));
 +        qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
      virt_flash_create(s);
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                    drive_get(IF_PFLASH, 0, i));
      }
      virt_flash_map(s, system_memory);
 -
 -    g_free(plic_hart_config);
  }
+@@ -XXX,XX +XXX,XX @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
- static void virt_machine_instance_init(Object *obj)
+ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
-@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
+ {
+     return opfv_narrow_check(s, a) &&
-     mc->desc = "RISC-V VirtIO board";
++           require_rvfmin(s) &&
-     mc->init = virt_machine_init;
+            require_scale_rvfmin(s) &&
--    mc->max_cpus = 8;
+            (s->sew != MO_8);
 +    mc->max_cpus = VIRT_CPUS_MAX;
      mc->default_cpu_type = VIRT_CPU;
      mc->pci_allow_0_address = true;
 +    mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
 +    mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
 +    mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
 +    mc->numa_mem_supported = true;
  }
- static const TypeInfo virt_machine_typeinfo = {
 --
-.28.0
+.45.1

-[PULL 15/18] target/riscv: Only support little endian guests
+[PULL 18/28] target/riscv: rvv: Check single width operator for vector fp widen instructions
+From: Max Chou <max.chou@sifive.com>
+The require_scale_rvf function only checks the double width operator for
+the vector floating point widen instructions, so most of the widen
+checking functions need to add require_rvf for single width operator.
+The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
+integer to double width float, so the opfxv_widen_check function doesn’t
+need require_rvf for the single width operator(integer).
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com
-Message-Id: <93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 5 +++++
+ target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 file changed, 5 insertions(+)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/csr.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
+@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
-     /* We only support 64-bit VSXL */
+ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
-     *val = set_field(*val, HSTATUS_VSXL, 2);
+ {
- #endif
+     return require_rvv(s) &&
-+    /* We only support little endian */
++           require_rvf(s) &&
-+    *val = set_field(*val, HSTATUS_VSBE, 0);
+            require_scale_rvf(s) &&
-     return 0;
+            (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check)
  static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf)
  static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv)
  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return require_rvv(s) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
@@ -XXX,XX +XXX,XX @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check)
  static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
  {
      return reduction_widen_check(s, a) &&
 +           require_rvf(s) &&
             require_scale_rvf(s) &&
             (s->sew != MO_8);
  }
-@@ -XXX,XX +XXX,XX @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
-         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
-     }
- #endif
-+    if (get_field(val, HSTATUS_VSBE) != 0) {
-+        qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
-+    }
-     return 0;
- }
 --
-.28.0
+.45.1

-New patch
+[PULL 19/28] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
+From: Max Chou <max.chou@sifive.com>
+The opfv_narrow_check needs to check the single width float operator by
+require_rvf.
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240322092600.1198921-4-max.chou@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/insn_trans/trans_rvv.c.inc | 1 +
+file changed, 1 insertion(+)
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
+@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_narrow_check(s, a) &&
++           require_rvf(s) &&
+            require_scale_rvf(s) &&
+            (s->sew != MO_8);
+ }
+--
+.45.1

-[PULL 14/18] target/riscv: Only support a single VSXL length
+[PULL 20/28] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions
+From: Max Chou <max.chou@sifive.com>
+If the checking functions check both the single and double width
+operators at the same time, then the single width operator checking
+functions (require_rvf[min]) will check whether the SEW is 8.
+Signed-off-by: Max Chou <max.chou@sifive.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com
-Message-Id: <f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/csr.c | 9 +++++++++
+ target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
-file changed, 9 insertions(+)
+file changed, 4 insertions(+), 12 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/insn_trans/trans_rvv.c.inc
-+++ b/target/riscv/csr.c
++++ b/target/riscv/insn_trans/trans_rvv.c.inc
-@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
+@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
- static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
+     return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_ds(s, a->rd, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
      return require_rvv(s) &&
             require_rvf(s) &&
             require_scale_rvf(s) &&
 -           (s->sew != MO_8) &&
             vext_check_isa_ill(s) &&
             vext_check_dd(s, a->rd, a->rs2, a->vm);
  }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
  {
-     *val = env->hstatus;
+     return opfv_widen_check(s, a) &&
-+#ifdef TARGET_RISCV64
+            require_rvfmin(s) &&
-+    /* We only support 64-bit VSXL */
+-           require_scale_rvfmin(s) &&
-+    *val = set_field(*val, HSTATUS_VSXL, 2);
+-           (s->sew != MO_8);
-+#endif
++           require_scale_rvfmin(s);
      return 0;
  }
- static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
+ #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
  {
-     env->hstatus = val;
+     return opfv_narrow_check(s, a) &&
-+#ifdef TARGET_RISCV64
+            require_rvfmin(s) &&
-+    if (get_field(val, HSTATUS_VSXL) != 2) {
+-           require_scale_rvfmin(s) &&
-+        qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
+-           (s->sew != MO_8);
-+    }
++           require_scale_rvfmin(s);
 +#endif
      return 0;
  }
+ static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
+ {
+     return opfv_narrow_check(s, a) &&
+            require_rvf(s) &&
+-           require_scale_rvf(s) &&
+-           (s->sew != MO_8);
++           require_scale_rvf(s);
+ }
+ #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
+@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
+ {
+     return reduction_widen_check(s, a) &&
+            require_rvf(s) &&
+-           require_scale_rvf(s) &&
+-           (s->sew != MO_8);
++           require_scale_rvf(s);
+ }
+ GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
 --
-.28.0
+.45.1

-[PULL 08/18] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
+[PULL 21/28] target/riscv: prioritize pmp errors in raise_mmu_exception()
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+raise_mmu_exception(), as is today, is prioritizing guest page faults by
+checking first if virt_enabled && !first_stage, and then considering the
+regular inst/load/store faults.
+There's no mention in the spec about guest page fault being a higher
+priority that PMP faults. In fact, privileged spec section 3.7.1 says:
+"Attempting to fetch an instruction from a PMP region that does not have
+execute permissions raises an instruction access-fault exception.
+Attempting to execute a load or load-reserved instruction which accesses
+a physical address within a PMP region without read permissions raises a
+load access-fault exception. Attempting to execute a store,
+store-conditional, or AMO instruction which accesses a physical address
+within a PMP region without write permissions raises a store
+access-fault exception."
+So, in fact, we're doing it wrong - PMP faults should always be thrown,
+regardless of also being a first or second stage fault.
+The way riscv_cpu_tlb_fill() and get_physical_address() work is
+adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
+reflected in the 'pmp_violation' flag. What we need is to change
+raise_mmu_exception() to prioritize it.
+Reported-by: Joseph Chan <jchan@ventanamicro.com>
+Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
+Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com
-Message-Id: <024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/cpu_helper.c | 60 ++++++++++++++++-----------------------
+ target/riscv/cpu_helper.c | 22 ++++++++++++----------
-file changed, 25 insertions(+), 35 deletions(-)
+file changed, 12 insertions(+), 10 deletions(-)
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
-      * was called. Background registers will be used if the guest has
-      * forced a two stage translation to be on (in HS or M mode).
-      */
-+    if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) {
-+        use_background = true;
-+    }
-+
-     if (mode == PRV_M && access_type != MMU_INST_FETCH) {
-         if (get_field(env->mstatus, MSTATUS_MPRV)) {
-             mode = get_field(env->mstatus, MSTATUS_MPP);
--
--            if (riscv_has_ext(env, RVH) &&
--                MSTATUS_MPV_ISSET(env)) {
--                use_background = true;
--            }
--        }
--    }
--
--    if (mode == PRV_S && access_type != MMU_INST_FETCH &&
--        riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
--        if (get_field(env->hstatus, HSTATUS_SPRV)) {
--            mode = get_field(env->mstatus, SSTATUS_SPP);
--            use_background = true;
-         }
-     }
 @@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+     switch (access_type) {
+     case MMU_INST_FETCH:
+-        if (env->virt_enabled && !first_stage) {
++        if (pmp_violation) {
++            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
++        } else if (env->virt_enabled && !first_stage) {
+             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
+         } else {
+-            cs->exception_index = pmp_violation ?
+-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
++            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
          }
          break;
      case MMU_DATA_LOAD:
--        if (riscv_cpu_virt_enabled(env) && !first_stage) {
+-        if (two_stage && !first_stage) {
-+        if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
++        if (pmp_violation) {
-+            !first_stage) {
++            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
 +        } else if (two_stage && !first_stage) {
              cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
          } else {
-             cs->exception_index = page_fault_exceptions ?
+-            cs->exception_index = pmp_violation ?
-@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
+-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
 +            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
          }
          break;
      case MMU_DATA_STORE:
--        if (riscv_cpu_virt_enabled(env) && !first_stage) {
+-        if (two_stage && !first_stage) {
-+        if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
++        if (pmp_violation) {
-+            !first_stage) {
++            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
 +        } else if (two_stage && !first_stage) {
              cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
          } else {
-             cs->exception_index = page_fault_exceptions ?
+-            cs->exception_index = pmp_violation ?
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-     hwaddr pa = 0;
+-                RISCV_EXCP_STORE_PAGE_FAULT;
-     int prot, prot2;
++            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
      bool pmp_violation = false;
 -    bool m_mode_two_stage = false;
 -    bool hs_mode_two_stage = false;
      bool first_stage_error = true;
      int ret = TRANSLATE_FAIL;
      int mode = mmu_idx;
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
      qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                    __func__, address, access_type, mmu_idx);
 -    /*
 -     * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
 -     * set and we want to access a virtulisation address.
 -     */
 -    if (riscv_has_ext(env, RVH)) {
 -        m_mode_two_stage = env->priv == PRV_M &&
 -                           access_type != MMU_INST_FETCH &&
 -                           get_field(env->mstatus, MSTATUS_MPRV) &&
 -                           MSTATUS_MPV_ISSET(env);
 -
 -        hs_mode_two_stage = env->priv == PRV_S &&
 -                            !riscv_cpu_virt_enabled(env) &&
 -                            access_type != MMU_INST_FETCH &&
 -                            get_field(env->hstatus, HSTATUS_SPRV) &&
 -                            get_field(env->hstatus, HSTATUS_SPV);
 -    }
 -
      if (mode == PRV_M && access_type != MMU_INST_FETCH) {
          if (get_field(env->mstatus, MSTATUS_MPRV)) {
              mode = get_field(env->mstatus, MSTATUS_MPP);
          }
-     }
+         break;
+     default:
 -    if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
 +    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
 +        access_type != MMU_INST_FETCH &&
 +        get_field(env->mstatus, MSTATUS_MPRV) &&
 +        MSTATUS_MPV_ISSET(env)) {
 +        riscv_cpu_set_two_stage_lookup(env, true);
 +    }
 +
 +    if (riscv_cpu_virt_enabled(env) ||
 +        (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) {
          /* Two stage lookup */
          ret = get_physical_address(env, &pa, &prot, address, access_type,
                                     mmu_idx, true, true);
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                        __func__, address, ret, pa, prot);
      }
 +    /* We did the two stage lookup based on MPRV, unset the lookup */
 +    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
 +        access_type != MMU_INST_FETCH &&
 +        get_field(env->mstatus, MSTATUS_MPRV) &&
 +        MSTATUS_MPV_ISSET(env)) {
 +        riscv_cpu_set_two_stage_lookup(env, false);
 +    }
 +
      if (riscv_feature(env, RISCV_FEATURE_PMP) &&
          (ret == TRANSLATE_SUCCESS) &&
          !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
 --
-.28.0
+.45.1

-[PULL 12/18] target/riscv: Update the Hypervisor trap return/entry
+[PULL 22/28] target/riscv: do not set mtval2 for non guest-page faults
+From: Alexei Filippov <alexei.filippov@syntacore.com>
+Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
+setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
+translation part, mtval2 will be set in case of successes 2 stage translation but
+failed pmp check.
+In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
+riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
+should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
+page-fault is taken into M-mode, mtval2 is written with either zero or guest
+physical address that faulted, shifted by 2 bits. *For other traps, mtval2
+is set to zero...*
+Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com
-Message-Id: <e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/cpu_bits.h   |  1 +
+ target/riscv/cpu_helper.c | 12 ++++++------
- target/riscv/cpu_helper.c | 16 ++++++----------
+file changed, 6 insertions(+), 6 deletions(-)
  target/riscv/op_helper.c  |  8 ++------
  target/riscv/translate.c  | 10 ----------
 files changed, 9 insertions(+), 26 deletions(-)
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
-+++ b/target/riscv/cpu_bits.h
-@@ -XXX,XX +XXX,XX @@
- #define HSTATUS_VTSR         0x00400000
- #define HSTATUS_HU           0x00000200
- #define HSTATUS_GVA          0x00000040
-+#define HSTATUS_SPVP         0x00000100
- #define HSTATUS32_WPRI       0xFF8FF87E
- #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu_helper.c
 +++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-             } else if (riscv_cpu_virt_enabled(env)) {
+                               __func__, pa, ret, prot_pmp, tlb_size);
-                 /* Trap into HS mode, from virt */
-                 riscv_cpu_swap_hypervisor_regs(env);
+                 prot &= prot_pmp;
--                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
+-            }
 -                                         get_field(env->hstatus, HSTATUS_SPV));
 -                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
 +                env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
                                           get_field(env->mstatus, SSTATUS_SPP));
                  env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
                                           riscv_cpu_virt_enabled(env));
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                  riscv_cpu_set_force_hs_excep(env, 0);
              } else {
                  /* Trap into HS mode */
 -                env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
 -                                         get_field(env->hstatus, HSTATUS_SPV));
 -                env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
 -                                         get_field(env->mstatus, SSTATUS_SPP));
 -                env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
 -                                         riscv_cpu_virt_enabled(env));
 -
-+                if (!riscv_cpu_two_stage_lookup(env)) {
+-            if (ret != TRANSLATE_SUCCESS) {
-+                    env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
++            } else {
-+                                             riscv_cpu_virt_enabled(env));
+                 /*
                   * Guest physical address translation failed, this is a HS
                   * level exception
                   */
                  first_stage_error = false;
 -                env->guest_phys_fault_addr = (im_address |
 -                                              (address &
 -                                               (TARGET_PAGE_SIZE - 1))) >> 2;
 +                if (ret != TRANSLATE_PMP_FAIL) {
 +                    env->guest_phys_fault_addr = (im_address |
 +                                                  (address &
 +                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
 +                }
-+                riscv_cpu_set_two_stage_lookup(env, false);
-                 htval = env->guest_phys_fault_addr;
              }
          }
-diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/op_helper.c
-+++ b/target/riscv/op_helper.c
-@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
-         prev_priv = get_field(mstatus, MSTATUS_SPP);
-         prev_virt = get_field(hstatus, HSTATUS_SPV);
--        hstatus = set_field(hstatus, HSTATUS_SPV,
--                                 get_field(hstatus, HSTATUS_SP2V));
--        mstatus = set_field(mstatus, MSTATUS_SPP,
--                            get_field(hstatus, HSTATUS_SP2P));
--        hstatus = set_field(hstatus, HSTATUS_SP2V, 0);
--        hstatus = set_field(hstatus, HSTATUS_SP2P, 0);
-+        hstatus = set_field(hstatus, HSTATUS_SPV, 0);
-+        mstatus = set_field(mstatus, MSTATUS_SPP, 0);
-         mstatus = set_field(mstatus, SSTATUS_SIE,
-                             get_field(mstatus, SSTATUS_SPIE));
-         mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
-diff --git a/target/riscv/translate.c b/target/riscv/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/translate.c
-+++ b/target/riscv/translate.c
-@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
- #if !defined(CONFIG_USER_ONLY)
-     if (riscv_has_ext(env, RVH)) {
-         ctx->virt_enabled = riscv_cpu_virt_enabled(env);
--        if (env->priv_ver == PRV_M &&
--            get_field(env->mstatus, MSTATUS_MPRV) &&
--            MSTATUS_MPV_ISSET(env)) {
--            ctx->virt_enabled = true;
--        } else if (env->priv == PRV_S &&
--                   !riscv_cpu_virt_enabled(env) &&
--                   get_field(env->hstatus, HSTATUS_SPRV) &&
--                   get_field(env->hstatus, HSTATUS_SPV)) {
--            ctx->virt_enabled = true;
--        }
      } else {
-         ctx->virt_enabled = false;
-     }
 --
-.28.0
+.45.1

-New patch
+[PULL 23/28] target/riscv: Remove experimental prefix from "B" extension
+From: Rob Bradford <rbradford@rivosinc.com>
+This extension has now been ratified:
+https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
+removed.
+Since this is now a ratified extension add it to the list of extensions
+included in the "max" CPU variant.
+Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
+Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/cpu.c         | 2 +-
+ target/riscv/tcg/tcg-cpu.c | 2 +-
+files changed, 2 insertions(+), 2 deletions(-)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
+     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
+     MISA_EXT_INFO(RVV, "v", "Vector operations"),
+     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
+-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
++    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
+ };
+ static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
+diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/tcg/tcg-cpu.c
++++ b/target/riscv/tcg/tcg-cpu.c
+@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
+     const RISCVCPUMultiExtConfig *prop;
+     /* Enable RVG, RVJ and RVV that are disabled by default */
+-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
++    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
+     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
+         isa_ext_update_enabled(cpu, prop->offset, true);
+--
+.45.1

-[PULL 17/18] target/riscv: Return the exception from invalid CSR accesses
+[PULL 24/28] target/riscv: rvzicbo: Fixup CBO extension register calculation
-When performing a CSR access let's return a negative exception value on
+From: Alistair Francis <alistair23@gmail.com>
-an error instead of -1. This will allow us to specify the exception in
-future patches.
+When running the instruction
 ```
     cbo.flush 0(x0)
 ```
 QEMU would segfault.
 The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
 allocated.
 In order to fix this let's use the existing get_address()
 helper. This also has the benefit of performing pointer mask
 calculations on the address specified in rs1.
 The pointer masking specificiation specifically states:
 """
 Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
 """
 So this is the correct behaviour and we previously have been incorrectly
 not masking the address.
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com
+Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
-Message-Id: <a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com>
+Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Cc: qemu-stable <qemu-stable@nongnu.org>
 Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- target/riscv/csr.c       | 46 ++++++++++++++++++++--------------------
+ target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
- target/riscv/op_helper.c | 18 ++++++++++------
+file changed, 12 insertions(+), 4 deletions(-)
 files changed, 35 insertions(+), 29 deletions(-)
-diff --git a/target/riscv/csr.c b/target/riscv/csr.c
+diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/csr.c
+--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
-+++ b/target/riscv/csr.c
++++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
-@@ -XXX,XX +XXX,XX @@ static int fs(CPURISCVState *env, int csrno)
+@@ -XXX,XX +XXX,XX @@
-         return 0;
+ static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
-     }
+ {
-     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+     REQUIRE_ZICBOM(ctx);
--        return -1;
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
-+        return -RISCV_EXCP_ILLEGAL_INST;
++    TCGv src = get_address(ctx, a->rs1, 0);
-     }
++
- #endif
++    gen_helper_cbo_clean_flush(tcg_env, src);
-     return 0;
+     return true;
@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
      if (!cpu->cfg.ext_counters) {
          /* The Counters extensions is not enabled */
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
  #endif
      return 0;
@@ -XXX,XX +XXX,XX @@ static int hmode(CPURISCVState *env, int csrno)
          }
      }
 -    return -1;
 +    return -RISCV_EXCP_ILLEGAL_INST;
  }
- static int pmp(CPURISCVState *env, int csrno)
+ static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
@@ -XXX,XX +XXX,XX @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
  {
- #if !defined(CONFIG_USER_ONLY)
+     REQUIRE_ZICBOM(ctx);
-     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
--        return -1;
++    TCGv src = get_address(ctx, a->rs1, 0);
-+        return -RISCV_EXCP_ILLEGAL_INST;
++
-     }
++    gen_helper_cbo_clean_flush(tcg_env, src);
- #endif
+     return true;
-     *val = riscv_cpu_get_fflags(env);
+ }
-@@ -XXX,XX +XXX,XX @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
  static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
  {
- #if !defined(CONFIG_USER_ONLY)
+     REQUIRE_ZICBOM(ctx);
-     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
--        return -1;
++    TCGv src = get_address(ctx, a->rs1, 0);
-+        return -RISCV_EXCP_ILLEGAL_INST;
++
-     }
++    gen_helper_cbo_inval(tcg_env, src);
-     env->mstatus |= MSTATUS_FS;
+     return true;
- #endif
+ }
-@@ -XXX,XX +XXX,XX @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
  static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
  {
- #if !defined(CONFIG_USER_ONLY)
+     REQUIRE_ZICBOZ(ctx);
-     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
--        return -1;
++    TCGv src = get_address(ctx, a->rs1, 0);
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
  #endif
      *val = env->frm;
@@ -XXX,XX +XXX,XX @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
  {
  #if !defined(CONFIG_USER_ONLY)
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      env->mstatus |= MSTATUS_FS;
  #endif
@@ -XXX,XX +XXX,XX @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
  {
  #if !defined(CONFIG_USER_ONLY)
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
  #endif
      *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
@@ -XXX,XX +XXX,XX @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
  {
  #if !defined(CONFIG_USER_ONLY)
      if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      env->mstatus |= MSTATUS_FS;
  #endif
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
      uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
      if (!env->rdtime_fn) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      *val = env->rdtime_fn() + delta;
@@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
      uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
      if (!env->rdtime_fn) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      *val = (env->rdtime_fn() + delta) >> 32;
@@ -XXX,XX +XXX,XX @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
  static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
  {
      if (env->priv_ver < PRIV_VERSION_1_11_0) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      *val = env->mcounteren;
      return 0;
@@ -XXX,XX +XXX,XX @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
  static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
  {
      if (env->priv_ver < PRIV_VERSION_1_11_0) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      env->mcounteren = val;
      return 0;
@@ -XXX,XX +XXX,XX @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
      }
      if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      } else {
          *val = env->satp;
      }
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
          ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
      {
          if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
 -            return -1;
 +            return -RISCV_EXCP_ILLEGAL_INST;
          } else {
              if((val ^ env->satp) & SATP_ASID) {
                  tlb_flush(env_cpu(env));
@@ -XXX,XX +XXX,XX @@ static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
  static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
  {
      if (!env->rdtime_fn) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
  #if defined(TARGET_RISCV32)
@@ -XXX,XX +XXX,XX @@ static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
  static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
  {
      if (!env->rdtime_fn) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
  #if defined(TARGET_RISCV32)
@@ -XXX,XX +XXX,XX @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
  static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
  {
      if (!env->rdtime_fn) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      *val = env->htimedelta >> 32;
@@ -XXX,XX +XXX,XX @@ static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
  static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
  {
      if (!env->rdtime_fn) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
      if ((write_mask && read_only) ||
          (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
  #endif
      /* ensure the CSR extension is enabled. */
      if (!cpu->cfg.ext_icsr) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      /* check predicate */
      if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      /* execute combined read/write operation if it exists */
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
      /* if no accessor exists then return failure */
      if (!csr_ops[csrno].read) {
 -        return -1;
 +        return -RISCV_EXCP_ILLEGAL_INST;
      }
      /* read old value */
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
          target_ulong csr)
  {
      target_ulong val = 0;
 -    if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
 -        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    int ret = riscv_csrrw(env, csr, &val, src, -1);
 +
-+    if (ret < 0) {
++    gen_helper_cbo_zero(tcg_env, src);
-+        riscv_raise_exception(env, -ret, GETPC());
+     return true;
      }
      return val;
  }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
          target_ulong csr, target_ulong rs1_pass)
  {
      target_ulong val = 0;
 -    if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
 -        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
 +
 +    if (ret < 0) {
 +        riscv_raise_exception(env, -ret, GETPC());
      }
      return val;
  }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
          target_ulong csr, target_ulong rs1_pass)
  {
      target_ulong val = 0;
 -    if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
 -        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 +    int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
 +
 +    if (ret < 0) {
 +        riscv_raise_exception(env, -ret, GETPC());
      }
      return val;
  }
 --
-.28.0
+.45.1

-New patch
+[PULL 25/28] target/riscv/kvm.c: Fix the hart bit setting of AIA
+From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
+In AIA spec, each hart (or each hart within a group) has a unique hart
+number to locate the memory pages of interrupt files in the address
+space. The number of bits required to represent any hart number is equal
+to ceil(log2(hmax + 1)), where hmax is the largest hart number among
+groups.
+However, if the largest hart number among groups is a power of 2, QEMU
+will pass an inaccurate hart-index-bit setting to Linux. For example, when
+the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
+to represent 4 harts, but we passes 3 to Linux. The code needs to be
+updated to ensure accurate hart-index-bit settings.
+Additionally, a Linux patch[1] is necessary to correctly recover the hart
+index when the guest OS has only 1 hart, where the hart-index-bit is 0.
+[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/
+Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
+Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
+file changed, 8 insertions(+), 1 deletion(-)
+diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/riscv/kvm/kvm-cpu.c
++++ b/target/riscv/kvm/kvm-cpu.c
+@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
+         }
+     }
+-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
++
++    if (max_hart_per_socket > 1) {
++        max_hart_per_socket--;
++        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
++    } else {
++        hart_bits = 0;
++    }
++
+     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
+                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
+                             &hart_bits, true, NULL);
+--
+.45.1

-[PULL 01/18] hw/riscv: Allow creating multiple instances of CLINT
+[PULL 26/28] riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()
-From: Anup Patel <anup.patel@wdc.com>
+From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
-We extend CLINT emulation to allow multiple instances of CLINT in
+Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
-a QEMU RISC-V machine. To achieve this, we remove first HART id
+in bytes, when in this context we want 'reg_width' as the length in
-zero assumption from CLINT emulation.
+bits.
-Signed-off-by: Anup Patel <anup.patel@wdc.com>
+Fix 'reg_width' back to the value in bits like 7cb59921c05a
 ("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
 beforehand.
 While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
 clarity about what the variable represents. 'bitsize' is also used in
 riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
 gdb_feature_builder_append_reg().
 Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
 Cc: Alex Bennée <alex.bennee@linaro.org>
 Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
 Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
 Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
 Acked-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
-Message-Id: <20200616032229.766089-2-anup.patel@wdc.com>
+Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 ---
- include/hw/riscv/sifive_clint.h |  7 ++++---
+ target/riscv/gdbstub.c | 6 +++---
- hw/riscv/sifive_clint.c         | 20 ++++++++++++--------
+file changed, 3 insertions(+), 3 deletions(-)
  hw/riscv/sifive_e.c             |  2 +-
  hw/riscv/sifive_u.c             |  2 +-
  hw/riscv/spike.c                |  2 +-
  hw/riscv/virt.c                 |  2 +-
 files changed, 20 insertions(+), 15 deletions(-)
-diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
+diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/riscv/sifive_clint.h
+--- a/target/riscv/gdbstub.c
-+++ b/include/hw/riscv/sifive_clint.h
++++ b/target/riscv/gdbstub.c
-@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState {
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
+ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
      /*< public >*/
      MemoryRegion mmio;
 +    uint32_t hartid_base;
      uint32_t num_harts;
      uint32_t sip_base;
      uint32_t timecmp_base;
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState {
      uint32_t aperture_size;
  } SiFiveCLINTState;
 -DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
 -    uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base,
 -    bool provide_rdtime);
 +DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
 +    uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
 +    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
  enum {
      SIFIVE_SIP_BASE     = 0x0,
 diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_clint.c
 +++ b/hw/riscv/sifive_clint.c
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
      SiFiveCLINTState *clint = opaque;
      if (addr >= clint->sip_base &&
          addr < clint->sip_base + (clint->num_harts << 2)) {
 -        size_t hartid = (addr - clint->sip_base) >> 2;
 +        size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2);
          CPUState *cpu = qemu_get_cpu(hartid);
          CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
          if (!env) {
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
          }
      } else if (addr >= clint->timecmp_base &&
          addr < clint->timecmp_base + (clint->num_harts << 3)) {
 -        size_t hartid = (addr - clint->timecmp_base) >> 3;
 +        size_t hartid = clint->hartid_base +
 +            ((addr - clint->timecmp_base) >> 3);
          CPUState *cpu = qemu_get_cpu(hartid);
          CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
          if (!env) {
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
      if (addr >= clint->sip_base &&
          addr < clint->sip_base + (clint->num_harts << 2)) {
 -        size_t hartid = (addr - clint->sip_base) >> 2;
 +        size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2);
          CPUState *cpu = qemu_get_cpu(hartid);
          CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
          if (!env) {
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
          return;
      } else if (addr >= clint->timecmp_base &&
          addr < clint->timecmp_base + (clint->num_harts << 3)) {
 -        size_t hartid = (addr - clint->timecmp_base) >> 3;
 +        size_t hartid = clint->hartid_base +
 +            ((addr - clint->timecmp_base) >> 3);
          CPUState *cpu = qemu_get_cpu(hartid);
          CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
          if (!env) {
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_clint_ops = {
  };
  static Property sifive_clint_properties[] = {
 +    DEFINE_PROP_UINT32("hartid-base", SiFiveCLINTState, hartid_base, 0),
      DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
      DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
      DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
@@ -XXX,XX +XXX,XX @@ type_init(sifive_clint_register_types)
  /*
   * Create CLINT device.
   */
 -DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
 -    uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base,
 -    bool provide_rdtime)
 +DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
 +    uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
 +    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
  {
+     RISCVCPU *cpu = RISCV_CPU(cs);
+-    int reg_width = cpu->cfg.vlenb;
++    int bitsize = cpu->cfg.vlenb << 3;
+     GDBFeatureBuilder builder;
      int i;
-     for (i = 0; i < num_harts; i++) {
--        CPUState *cpu = qemu_get_cpu(i);
+@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
-+        CPUState *cpu = qemu_get_cpu(hartid_base + i);
-         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
+     /* First define types and totals in a whole VL */
-         if (!env) {
+     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-             continue;
+-        int count = reg_width / vec_lanes[i].size;
-@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
++        int count = bitsize / vec_lanes[i].size;
          gdb_feature_builder_append_tag(
              &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
              vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
      /* Define vector registers */
      for (i = 0; i < 32; i++) {
          gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
 -                                       reg_width, i, "riscv_vector", "vector");
 +                                       bitsize, i, "riscv_vector", "vector");
      }
-     DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT);
+     gdb_feature_builder_end(&builder);
 +    qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
      qdev_prop_set_uint32(dev, "num-harts", num_harts);
      qdev_prop_set_uint32(dev, "sip-base", sip_base);
      qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_e.c
 +++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
          SIFIVE_E_PLIC_CONTEXT_STRIDE,
          memmap[SIFIVE_E_PLIC].size);
      sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
 -        memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
 +        memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
          SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
      create_unimplemented_device("riscv.sifive.e.aon",
          memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/sifive_u.c
 +++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
      sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
          serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
      sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
 -        memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
 +        memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
          SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
      if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/spike.c
 +++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
      /* Core Local Interruptor (timer and IPI) */
      sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
 -        smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
 +        0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
          false);
  }
 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/riscv/virt.c
 +++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
          VIRT_PLIC_CONTEXT_STRIDE,
          memmap[VIRT_PLIC].size);
      sifive_clint_create(memmap[VIRT_CLINT].base,
 -        memmap[VIRT_CLINT].size, smp_cpus,
 +        memmap[VIRT_CLINT].size, 0, smp_cpus,
          SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
      sifive_test_create(memmap[VIRT_TEST].base);
 --
-.28.0
+.45.1

-New patch
+[PULL 27/28] disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs
+From: Alistair Francis <alistair23@gmail.com>
+Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
+CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
+CSRs are part of the disassembly.
+Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Fixes: ea10325917 ("RISC-V Disassembler")
+Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
+Cc: qemu-stable <qemu-stable@nongnu.org>
+Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+---
+ disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
+file changed, 64 insertions(+), 1 deletion(-)
+diff --git a/disas/riscv.c b/disas/riscv.c
+index XXXXXXX..XXXXXXX 100644
+--- a/disas/riscv.c
++++ b/disas/riscv.c
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
+     case 0x0383: return "mibound";
+     case 0x0384: return "mdbase";
+     case 0x0385: return "mdbound";
+-    case 0x03a0: return "pmpcfg3";
++    case 0x03a0: return "pmpcfg0";
++    case 0x03a1: return "pmpcfg1";
++    case 0x03a2: return "pmpcfg2";
++    case 0x03a3: return "pmpcfg3";
++    case 0x03a4: return "pmpcfg4";
++    case 0x03a5: return "pmpcfg5";
++    case 0x03a6: return "pmpcfg6";
++    case 0x03a7: return "pmpcfg7";
++    case 0x03a8: return "pmpcfg8";
++    case 0x03a9: return "pmpcfg9";
++    case 0x03aa: return "pmpcfg10";
++    case 0x03ab: return "pmpcfg11";
++    case 0x03ac: return "pmpcfg12";
++    case 0x03ad: return "pmpcfg13";
++    case 0x03ae: return "pmpcfg14";
++    case 0x03af: return "pmpcfg15";
+     case 0x03b0: return "pmpaddr0";
+     case 0x03b1: return "pmpaddr1";
+     case 0x03b2: return "pmpaddr2";
+@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
+     case 0x03bd: return "pmpaddr13";
+     case 0x03be: return "pmpaddr14";
+     case 0x03bf: return "pmpaddr15";
++    case 0x03c0: return "pmpaddr16";
++    case 0x03c1: return "pmpaddr17";
++    case 0x03c2: return "pmpaddr18";
++    case 0x03c3: return "pmpaddr19";
++    case 0x03c4: return "pmpaddr20";
++    case 0x03c5: return "pmpaddr21";
++    case 0x03c6: return "pmpaddr22";
++    case 0x03c7: return "pmpaddr23";
++    case 0x03c8: return "pmpaddr24";
++    case 0x03c9: return "pmpaddr25";
++    case 0x03ca: return "pmpaddr26";
++    case 0x03cb: return "pmpaddr27";
++    case 0x03cc: return "pmpaddr28";
++    case 0x03cd: return "pmpaddr29";
++    case 0x03ce: return "pmpaddr30";
++    case 0x03cf: return "pmpaddr31";
++    case 0x03d0: return "pmpaddr32";
++    case 0x03d1: return "pmpaddr33";
++    case 0x03d2: return "pmpaddr34";
++    case 0x03d3: return "pmpaddr35";
++    case 0x03d4: return "pmpaddr36";
++    case 0x03d5: return "pmpaddr37";
++    case 0x03d6: return "pmpaddr38";
++    case 0x03d7: return "pmpaddr39";
++    case 0x03d8: return "pmpaddr40";
++    case 0x03d9: return "pmpaddr41";
++    case 0x03da: return "pmpaddr42";
++    case 0x03db: return "pmpaddr43";
++    case 0x03dc: return "pmpaddr44";
++    case 0x03dd: return "pmpaddr45";
++    case 0x03de: return "pmpaddr46";
++    case 0x03df: return "pmpaddr47";
++    case 0x03e0: return "pmpaddr48";
++    case 0x03e1: return "pmpaddr49";
++    case 0x03e2: return "pmpaddr50";
++    case 0x03e3: return "pmpaddr51";
++    case 0x03e4: return "pmpaddr52";
++    case 0x03e5: return "pmpaddr53";
++    case 0x03e6: return "pmpaddr54";
++    case 0x03e7: return "pmpaddr55";
++    case 0x03e8: return "pmpaddr56";
++    case 0x03e9: return "pmpaddr57";
++    case 0x03ea: return "pmpaddr58";
++    case 0x03eb: return "pmpaddr59";
++    case 0x03ec: return "pmpaddr60";
++    case 0x03ed: return "pmpaddr61";
++    case 0x03ee: return "pmpaddr62";
++    case 0x03ef: return "pmpaddr63";
+     case 0x0780: return "mtohost";
+     case 0x0781: return "mfromhost";
+     case 0x0782: return "mreset";
+--
+.45.1

-[PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt status
+[PULL 28/28] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR
+From: Yu-Ming Chang <yumin686@andestech.com>
+Both CSRRS and CSRRC always read the addressed CSR and cause any read side
+effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
+holding a zero value other than x0, the instruction will still attempt to write
+the unmodified value back to the CSR and will cause any attendant side effects.
+So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
+a register holding a zero value, an illegal instruction exception should be
+raised.
+Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-Message-id: 08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com
-Message-Id: <08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com>
 ---
- target/riscv/cpu.h        |  2 ++
+ target/riscv/cpu.h       |  4 ++++
- target/riscv/cpu_bits.h   |  1 +
+ target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
- target/riscv/cpu_helper.c | 18 ++++++++++++++++++
+ target/riscv/op_helper.c |  6 ++---
-files changed, 21 insertions(+)
+files changed, 53 insertions(+), 8 deletions(-)
 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/cpu.h
 +++ b/target/riscv/cpu.h
-@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
+@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
- void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
+ void riscv_cpu_update_mask(CPURISCVState *env);
- bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
+ bool riscv_cpu_is_32bit(RISCVCPU *cpu);
- void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
-+bool riscv_cpu_two_stage_lookup(CPURISCVState *env);
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
-+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);
++                          target_ulong *ret_value);
- int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
- hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+                            target_ulong *ret_value,
- void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
+                            target_ulong new_value, target_ulong write_mask);
-diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
+@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                            target_ulong new_value,
                                            target_ulong write_mask);
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value);
  RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                  Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask);
 diff --git a/target/riscv/csr.c b/target/riscv/csr.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/riscv/cpu_bits.h
+--- a/target/riscv/csr.c
-+++ b/target/riscv/cpu_bits.h
++++ b/target/riscv/csr.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-  * page table fault.
-  */
+ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
- #define FORCE_HS_EXCEP      2
+                                                int csrno,
-+#define HS_TWO_STAGE        4
+-                                               bool write_mask)
++                                               bool write)
- /* RV32 satp CSR field masks */
+ {
- #define SATP32_MODE         0x80000000
+     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
-diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
+     bool read_only = get_field(csrno, 0xC00) == 3;
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
---- a/target/riscv/cpu_helper.c
+     }
-+++ b/target/riscv/cpu_helper.c
-@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
+     /* read / write check */
-     env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
+-    if (write_mask && read_only) {
 +    if (write && read_only) {
          return RISCV_EXCP_ILLEGAL_INST;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
-+bool riscv_cpu_two_stage_lookup(CPURISCVState *env)
++RISCVException riscv_csrr(CPURISCVState *env, int csrno,
 +                           target_ulong *ret_value)
 +{
-+    if (!riscv_has_ext(env, RVH)) {
++    RISCVException ret = riscv_csrrw_check(env, csrno, false);
-+        return false;
++    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
-+    return get_field(env->virt, HS_TWO_STAGE);
++    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
 +}
 +
-+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable)
+ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                             target_ulong *ret_value,
                             target_ulong new_value, target_ulong write_mask)
  {
 -    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
 +    RISCVException ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
      return RISCV_EXCP_NONE;
  }
 +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
 +                               Int128 *ret_value)
 +{
-+    if (!riscv_has_ext(env, RVH)) {
++    RISCVException ret;
-+        return;
++
 +    ret = riscv_csrrw_check(env, csrno, false);
 +    if (ret != RISCV_EXCP_NONE) {
 +        return ret;
 +    }
 +
-+    env->virt = set_field(env->virt, HS_TWO_STAGE, enable);
++    if (csr_ops[csrno].read128) {
 +        return riscv_csrrw_do128(env, csrno, ret_value,
 +                                 int128_zero(), int128_zero());
 +    }
 +
 +    /*
 +     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
 +     * at all defined.
 +     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
 +     * significant), for those, this fallback is correctly handling the
 +     * accesses
 +     */
 +    target_ulong old_value;
 +    ret = riscv_csrrw_do64(env, csrno, &old_value,
 +                           (target_ulong)0,
 +                           (target_ulong)0);
 +    if (ret == RISCV_EXCP_NONE && ret_value) {
 +        *ret_value = int128_make64(old_value);
 +    }
 +    return ret;
 +}
 +
- int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
+ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                  Int128 *ret_value,
                                  Int128 new_value, Int128 write_mask)
  {
-     CPURISCVState *env = &cpu->env;
+     RISCVException ret;
 -    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
 +    ret = riscv_csrrw_check(env, csrno, true);
      if (ret != RISCV_EXCP_NONE) {
          return ret;
      }
 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/riscv/op_helper.c
 +++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
      }
      target_ulong val = 0;
 -    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
 +    RISCVException ret = riscv_csrr(env, csr, &val);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
  target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
  {
      Int128 rv = int128_zero();
 -    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
 -                                          int128_zero(),
 -                                          int128_zero());
 +    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
      if (ret != RISCV_EXCP_NONE) {
          riscv_raise_exception(env, ret, GETPC());
 --
-.28.0
+.45.1

The following changes since commit 7774e403f2ac58b3e87bfe8d2f77676501ba893e:

Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200825-pull-request' into staging (2020-08-25 10:54:51 +0100)

are available in the Git repository at:

git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200825

for you to fetch changes up to e39a8320b088dd5efc9ebaafe387e52b3d962665:

target/riscv: Support the Virtual Instruction fault (2020-08-25 09:11:36 -0700)

----------------------------------------------------------------
This pull request first adds support for multi-socket NUMA RISC-V
machines. The Spike and Virt machines both support NUMA sockets.

This PR also updates the current experimental Hypervisor support to the
v0.6.1 spec.

----------------------------------------------------------------
Alistair Francis (13):
      target/riscv: Allow setting a two-stage lookup in the virt status
      target/riscv: Allow generating hlv/hlvx/hsv instructions
      target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
      target/riscv: Don't allow guest to write to htinst
      target/riscv: Convert MSTATUS MTL to GVA
      target/riscv: Fix the interrupt cause code
      target/riscv: Update the Hypervisor trap return/entry
      target/riscv: Update the CSRs to the v0.6 Hyp extension
      target/riscv: Only support a single VSXL length
      target/riscv: Only support little endian guests
      target/riscv: Support the v0.6 Hypervisor extension CRSs
      target/riscv: Return the exception from invalid CSR accesses
      target/riscv: Support the Virtual Instruction fault

Anup Patel (5):
      hw/riscv: Allow creating multiple instances of CLINT
      hw/riscv: Allow creating multiple instances of PLIC
      hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
      hw/riscv: spike: Allow creating multiple NUMA sockets
      hw/riscv: virt: Allow creating multiple NUMA sockets

From: Anup Patel <anup.patel@wdc.com>

We extend CLINT emulation to allow multiple instances of CLINT in
a QEMU RISC-V machine. To achieve this, we remove first HART id
zero assumption from CLINT emulation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-Id: <20200616032229.766089-2-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/sifive_clint.h |  7 ++++---
 hw/riscv/sifive_clint.c         | 20 ++++++++++++--------
 hw/riscv/sifive_e.c             |  2 +-
 hw/riscv/sifive_u.c             |  2 +-
 hw/riscv/spike.c                |  2 +-
 hw/riscv/virt.c                 |  2 +-
 6 files changed, 20 insertions(+), 15 deletions(-)

diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_clint.h
+++ b/include/hw/riscv/sifive_clint.h
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState {
 
     /*< public >*/
     MemoryRegion mmio;
+    uint32_t hartid_base;
     uint32_t num_harts;
     uint32_t sip_base;
     uint32_t timecmp_base;
@@ -XXX,XX +XXX,XX @@ typedef struct SiFiveCLINTState {
     uint32_t aperture_size;
 } SiFiveCLINTState;
 
-DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
-    uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base,
-    bool provide_rdtime);
+DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
+    uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
+    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
 
 enum {
     SIFIVE_SIP_BASE     = 0x0,
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
     SiFiveCLINTState *clint = opaque;
     if (addr >= clint->sip_base &&
         addr < clint->sip_base + (clint->num_harts << 2)) {
-        size_t hartid = (addr - clint->sip_base) >> 2;
+        size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2);
         CPUState *cpu = qemu_get_cpu(hartid);
         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
         if (!env) {
@@ -XXX,XX +XXX,XX @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
         }
     } else if (addr >= clint->timecmp_base &&
         addr < clint->timecmp_base + (clint->num_harts << 3)) {
-        size_t hartid = (addr - clint->timecmp_base) >> 3;
+        size_t hartid = clint->hartid_base +
+            ((addr - clint->timecmp_base) >> 3);
         CPUState *cpu = qemu_get_cpu(hartid);
         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
         if (!env) {
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
 
     if (addr >= clint->sip_base &&
         addr < clint->sip_base + (clint->num_harts << 2)) {
-        size_t hartid = (addr - clint->sip_base) >> 2;
+        size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2);
         CPUState *cpu = qemu_get_cpu(hartid);
         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
         if (!env) {
@@ -XXX,XX +XXX,XX @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
         return;
     } else if (addr >= clint->timecmp_base &&
         addr < clint->timecmp_base + (clint->num_harts << 3)) {
-        size_t hartid = (addr - clint->timecmp_base) >> 3;
+        size_t hartid = clint->hartid_base +
+            ((addr - clint->timecmp_base) >> 3);
         CPUState *cpu = qemu_get_cpu(hartid);
         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
         if (!env) {
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_clint_ops = {
 };
 
 static Property sifive_clint_properties[] = {
+    DEFINE_PROP_UINT32("hartid-base", SiFiveCLINTState, hartid_base, 0),
     DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
     DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
     DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
@@ -XXX,XX +XXX,XX @@ type_init(sifive_clint_register_types)
 /*
  * Create CLINT device.
  */
-DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
-    uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base,
-    bool provide_rdtime)
+DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
+    uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
+    uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
 {
     int i;
     for (i = 0; i < num_harts; i++) {
-        CPUState *cpu = qemu_get_cpu(i);
+        CPUState *cpu = qemu_get_cpu(hartid_base + i);
         CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
         if (!env) {
             continue;
@@ -XXX,XX +XXX,XX @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
     }
 
     DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT);
+    qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
     qdev_prop_set_uint32(dev, "num-harts", num_harts);
     qdev_prop_set_uint32(dev, "sip-base", sip_base);
     qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_E_PLIC_CONTEXT_STRIDE,
         memmap[SIFIVE_E_PLIC].size);
     sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
-        memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
+        memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
     create_unimplemented_device("riscv.sifive.e.aon",
         memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
     sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
-        memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
+        memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
 
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
 
     /* Core Local Interruptor (timer and IPI) */
     sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
-        smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+        0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
         false);
 }
 
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
         VIRT_PLIC_CONTEXT_STRIDE,
         memmap[VIRT_PLIC].size);
     sifive_clint_create(memmap[VIRT_CLINT].base,
-        memmap[VIRT_CLINT].size, smp_cpus,
+        memmap[VIRT_CLINT].size, 0, smp_cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
     sifive_test_create(memmap[VIRT_TEST].base);
 
-- 
2.28.0

From: Anup Patel <anup.patel@wdc.com>

We extend PLIC emulation to allow multiple instances of PLIC in
a QEMU RISC-V machine. To achieve this, we remove first HART id
zero assumption from PLIC emulation.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200616032229.766089-3-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/sifive_plic.h | 12 +++++++-----
 hw/riscv/sifive_e.c            |  2 +-
 hw/riscv/sifive_plic.c         | 24 +++++++++++++-----------
 hw/riscv/sifive_u.c            |  2 +-
 hw/riscv/virt.c                |  2 +-
 5 files changed, 23 insertions(+), 19 deletions(-)

diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/sifive_plic.h
+++ b/include/hw/riscv/sifive_plic.h
@@ -XXX,XX +XXX,XX @@ typedef struct SiFivePLICState {
     /*< public >*/
     MemoryRegion mmio;
     uint32_t num_addrs;
+    uint32_t num_harts;
     uint32_t bitfield_words;
     PLICAddr *addr_config;
     uint32_t *source_priority;
@@ -XXX,XX +XXX,XX @@ typedef struct SiFivePLICState {
 
     /* config */
     char *hart_config;
+    uint32_t hartid_base;
     uint32_t num_sources;
     uint32_t num_priorities;
     uint32_t priority_base;
@@ -XXX,XX +XXX,XX @@ typedef struct SiFivePLICState {
 } SiFivePLICState;
 
 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
-    uint32_t num_sources, uint32_t num_priorities,
-    uint32_t priority_base, uint32_t pending_base,
-    uint32_t enable_base, uint32_t enable_stride,
-    uint32_t context_base, uint32_t context_stride,
-    uint32_t aperture_size);
+    uint32_t hartid_base, uint32_t num_sources,
+    uint32_t num_priorities, uint32_t priority_base,
+    uint32_t pending_base, uint32_t enable_base,
+    uint32_t enable_stride, uint32_t context_base,
+    uint32_t context_stride, uint32_t aperture_size);
 
 #endif
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -XXX,XX +XXX,XX @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
 
     /* MMIO */
     s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
-        (char *)SIFIVE_E_PLIC_HART_CONFIG,
+        (char *)SIFIVE_E_PLIC_HART_CONFIG, 0,
         SIFIVE_E_PLIC_NUM_SOURCES,
         SIFIVE_E_PLIC_NUM_PRIORITIES,
         SIFIVE_E_PLIC_PRIORITY_BASE,
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps sifive_plic_ops = {
 
 static Property sifive_plic_properties[] = {
     DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
+    DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
     DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
     DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
     DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
@@ -XXX,XX +XXX,XX @@ static void parse_hart_config(SiFivePLICState *plic)
     }
     hartid++;
 
-    /* store hart/mode combinations */
     plic->num_addrs = addrid;
+    plic->num_harts = hartid;
+
+    /* store hart/mode combinations */
     plic->addr_config = g_new(PLICAddr, plic->num_addrs);
-    addrid = 0, hartid = 0;
+    addrid = 0, hartid = plic->hartid_base;
     p = plic->hart_config;
     while ((c = *p++)) {
         if (c == ',') {
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
 
 static void sifive_plic_realize(DeviceState *dev, Error **errp)
 {
-    MachineState *ms = MACHINE(qdev_get_machine());
-    unsigned int smp_cpus = ms->smp.cpus;
     SiFivePLICState *plic = SIFIVE_PLIC(dev);
     int i;
 
@@ -XXX,XX +XXX,XX @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
      * hardware controlled when a PLIC is attached.
      */
-    for (i = 0; i < smp_cpus; i++) {
-        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
+    for (i = 0; i < plic->num_harts; i++) {
+        RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
             error_report("SEIP already claimed");
             exit(1);
@@ -XXX,XX +XXX,XX @@ type_init(sifive_plic_register_types)
  * Create PLIC device.
  */
 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
-    uint32_t num_sources, uint32_t num_priorities,
-    uint32_t priority_base, uint32_t pending_base,
-    uint32_t enable_base, uint32_t enable_stride,
-    uint32_t context_base, uint32_t context_stride,
-    uint32_t aperture_size)
+    uint32_t hartid_base, uint32_t num_sources,
+    uint32_t num_priorities, uint32_t priority_base,
+    uint32_t pending_base, uint32_t enable_base,
+    uint32_t enable_stride, uint32_t context_base,
+    uint32_t context_stride, uint32_t aperture_size)
 {
     DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
     assert(enable_stride == (enable_stride & -enable_stride));
     assert(context_stride == (context_stride & -context_stride));
     qdev_prop_set_string(dev, "hart-config", hart_config);
+    qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
     qdev_prop_set_uint32(dev, "num-sources", num_sources);
     qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
     qdev_prop_set_uint32(dev, "priority-base", priority_base);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -XXX,XX +XXX,XX @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
 
     /* MMIO */
     s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
-        plic_hart_config,
+        plic_hart_config, 0,
         SIFIVE_U_PLIC_NUM_SOURCES,
         SIFIVE_U_PLIC_NUM_PRIORITIES,
         SIFIVE_U_PLIC_PRIORITY_BASE,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
 
     /* MMIO */
     s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
-        plic_hart_config,
+        plic_hart_config, 0,
         VIRT_PLIC_NUM_SOURCES,
         VIRT_PLIC_NUM_PRIORITIES,
         VIRT_PLIC_PRIORITY_BASE,
-- 
2.28.0

From: Anup Patel <anup.patel@wdc.com>

We add common helper routines which can be shared by RISC-V
multi-socket NUMA machines.

We have two types of helpers:
1. riscv_socket_xyz() - These helper assist managing multiple
   sockets irrespective whether QEMU NUMA is enabled/disabled
2. riscv_numa_xyz() - These helpers assist in providing
   necessary QEMU machine callbacks for QEMU NUMA emulation

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-4-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/numa.h | 113 +++++++++++++++++++
 hw/riscv/numa.c         | 242 ++++++++++++++++++++++++++++++++++++++++
 hw/riscv/meson.build    |   1 +
 3 files changed, 356 insertions(+)
 create mode 100644 include/hw/riscv/numa.h
 create mode 100644 hw/riscv/numa.c

diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/riscv/numa.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU RISC-V NUMA Helper
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef RISCV_NUMA_H
+#define RISCV_NUMA_H
+
+#include "hw/sysbus.h"
+#include "sysemu/numa.h"
+
+/**
+ * riscv_socket_count:
+ * @ms: pointer to machine state
+ *
+ * Returns: number of sockets for a numa system and 1 for a non-numa system
+ */
+int riscv_socket_count(const MachineState *ms);
+
+/**
+ * riscv_socket_first_hartid:
+ * @ms: pointer to machine state
+ * @socket_id: socket index
+ *
+ * Returns: first hartid for a valid socket and -1 for an invalid socket
+ */
+int riscv_socket_first_hartid(const MachineState *ms, int socket_id);
+
+/**
+ * riscv_socket_last_hartid:
+ * @ms: pointer to machine state
+ * @socket_id: socket index
+ *
+ * Returns: last hartid for a valid socket and -1 for an invalid socket
+ */
+int riscv_socket_last_hartid(const MachineState *ms, int socket_id);
+
+/**
+ * riscv_socket_hart_count:
+ * @ms: pointer to machine state
+ * @socket_id: socket index
+ *
+ * Returns: number of harts for a valid socket and -1 for an invalid socket
+ */
+int riscv_socket_hart_count(const MachineState *ms, int socket_id);
+
+/**
+ * riscv_socket_mem_offset:
+ * @ms: pointer to machine state
+ * @socket_id: socket index
+ *
+ * Returns: offset of ram belonging to given socket
+ */
+uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id);
+
+/**
+ * riscv_socket_mem_size:
+ * @ms: pointer to machine state
+ * @socket_id: socket index
+ *
+ * Returns: size of ram belonging to given socket
+ */
+uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id);
+
+/**
+ * riscv_socket_check_hartids:
+ * @ms: pointer to machine state
+ * @socket_id: socket index
+ *
+ * Returns: true if hardids belonging to given socket are contiguous else false
+ */
+bool riscv_socket_check_hartids(const MachineState *ms, int socket_id);
+
+/**
+ * riscv_socket_fdt_write_id:
+ * @ms: pointer to machine state
+ * @socket_id: socket index
+ *
+ * Write NUMA node-id FDT property for given FDT node
+ */
+void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
+                               const char *node_name, int socket_id);
+
+/**
+ * riscv_socket_fdt_write_distance_matrix:
+ * @ms: pointer to machine state
+ * @socket_id: socket index
+ *
+ * Write NUMA distance matrix in FDT for given machine
+ */
+void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt);
+
+CpuInstanceProperties
+riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index);
+
+int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx);
+
+const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms);
+
+#endif /* RISCV_NUMA_H */
diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/riscv/numa.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU RISC-V NUMA Helper
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/riscv/numa.h"
+#include "sysemu/device_tree.h"
+
+static bool numa_enabled(const MachineState *ms)
+{
+    return (ms->numa_state && ms->numa_state->num_nodes) ? true : false;
+}
+
+int riscv_socket_count(const MachineState *ms)
+{
+    return (numa_enabled(ms)) ? ms->numa_state->num_nodes : 1;
+}
+
+int riscv_socket_first_hartid(const MachineState *ms, int socket_id)
+{
+    int i, first_hartid = ms->smp.cpus;
+
+    if (!numa_enabled(ms)) {
+        return (!socket_id) ? 0 : -1;
+    }
+
+    for (i = 0; i < ms->smp.cpus; i++) {
+        if (ms->possible_cpus->cpus[i].props.node_id != socket_id) {
+            continue;
+        }
+        if (i < first_hartid) {
+            first_hartid = i;
+        }
+    }
+
+    return (first_hartid < ms->smp.cpus) ? first_hartid : -1;
+}
+
+int riscv_socket_last_hartid(const MachineState *ms, int socket_id)
+{
+    int i, last_hartid = -1;
+
+    if (!numa_enabled(ms)) {
+        return (!socket_id) ? ms->smp.cpus - 1 : -1;
+    }
+
+    for (i = 0; i < ms->smp.cpus; i++) {
+        if (ms->possible_cpus->cpus[i].props.node_id != socket_id) {
+            continue;
+        }
+        if (i > last_hartid) {
+            last_hartid = i;
+        }
+    }
+
+    return (last_hartid < ms->smp.cpus) ? last_hartid : -1;
+}
+
+int riscv_socket_hart_count(const MachineState *ms, int socket_id)
+{
+    int first_hartid, last_hartid;
+
+    if (!numa_enabled(ms)) {
+        return (!socket_id) ? ms->smp.cpus : -1;
+    }
+
+    first_hartid = riscv_socket_first_hartid(ms, socket_id);
+    if (first_hartid < 0) {
+        return -1;
+    }
+
+    last_hartid = riscv_socket_last_hartid(ms, socket_id);
+    if (last_hartid < 0) {
+        return -1;
+    }
+
+    if (first_hartid > last_hartid) {
+        return -1;
+    }
+
+    return last_hartid - first_hartid + 1;
+}
+
+bool riscv_socket_check_hartids(const MachineState *ms, int socket_id)
+{
+    int i, first_hartid, last_hartid;
+
+    if (!numa_enabled(ms)) {
+        return (!socket_id) ? true : false;
+    }
+
+    first_hartid = riscv_socket_first_hartid(ms, socket_id);
+    if (first_hartid < 0) {
+        return false;
+    }
+
+    last_hartid = riscv_socket_last_hartid(ms, socket_id);
+    if (last_hartid < 0) {
+        return false;
+    }
+
+    for (i = first_hartid; i <= last_hartid; i++) {
+        if (ms->possible_cpus->cpus[i].props.node_id != socket_id) {
+            return false;
+        }
+    }
+
+    return true;
+}
+
+uint64_t riscv_socket_mem_offset(const MachineState *ms, int socket_id)
+{
+    int i;
+    uint64_t mem_offset = 0;
+
+    if (!numa_enabled(ms)) {
+        return 0;
+    }
+
+    for (i = 0; i < ms->numa_state->num_nodes; i++) {
+        if (i == socket_id) {
+            break;
+        }
+        mem_offset += ms->numa_state->nodes[i].node_mem;
+    }
+
+    return (i == socket_id) ? mem_offset : 0;
+}
+
+uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id)
+{
+    if (!numa_enabled(ms)) {
+        return (!socket_id) ? ms->ram_size : 0;
+    }
+
+    return (socket_id < ms->numa_state->num_nodes) ?
+            ms->numa_state->nodes[socket_id].node_mem : 0;
+}
+
+void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt,
+                               const char *node_name, int socket_id)
+{
+    if (numa_enabled(ms)) {
+        qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id);
+    }
+}
+
+void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt)
+{
+    int i, j, idx;
+    uint32_t *dist_matrix, dist_matrix_size;
+
+    if (numa_enabled(ms) && ms->numa_state->have_numa_distance) {
+        dist_matrix_size = riscv_socket_count(ms) * riscv_socket_count(ms);
+        dist_matrix_size *= (3 * sizeof(uint32_t));
+        dist_matrix = g_malloc0(dist_matrix_size);
+
+        for (i = 0; i < riscv_socket_count(ms); i++) {
+            for (j = 0; j < riscv_socket_count(ms); j++) {
+                idx = (i * riscv_socket_count(ms) + j) * 3;
+                dist_matrix[idx + 0] = cpu_to_be32(i);
+                dist_matrix[idx + 1] = cpu_to_be32(j);
+                dist_matrix[idx + 2] =
+                    cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
+            }
+        }
+
+        qemu_fdt_add_subnode(fdt, "/distance-map");
+        qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
+                                "numa-distance-map-v1");
+        qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
+                         dist_matrix, dist_matrix_size);
+        g_free(dist_matrix);
+    }
+}
+
+CpuInstanceProperties
+riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
+{
+    MachineClass *mc = MACHINE_GET_CLASS(ms);
+    const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
+
+    assert(cpu_index < possible_cpus->len);
+    return possible_cpus->cpus[cpu_index].props;
+}
+
+int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx)
+{
+    int64_t nidx = 0;
+
+    if (ms->numa_state->num_nodes) {
+        nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes);
+        if (ms->numa_state->num_nodes <= nidx) {
+            nidx = ms->numa_state->num_nodes - 1;
+        }
+    }
+
+    return nidx;
+}
+
+const CPUArchIdList *riscv_numa_possible_cpu_arch_ids(MachineState *ms)
+{
+    int n;
+    unsigned int max_cpus = ms->smp.max_cpus;
+
+    if (ms->possible_cpus) {
+        assert(ms->possible_cpus->len == max_cpus);
+        return ms->possible_cpus;
+    }
+
+    ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
+                                  sizeof(CPUArchId) * max_cpus);
+    ms->possible_cpus->len = max_cpus;
+    for (n = 0; n < ms->possible_cpus->len; n++) {
+        ms->possible_cpus->cpus[n].type = ms->cpu_type;
+        ms->possible_cpus->cpus[n].arch_id = n;
+        ms->possible_cpus->cpus[n].props.has_core_id = true;
+        ms->possible_cpus->cpus[n].props.core_id = n;
+    }
+
+    return ms->possible_cpus;
+}
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -XXX,XX +XXX,XX @@
 riscv_ss = ss.source_set()
 riscv_ss.add(files('boot.c'))
+riscv_ss.add(files('numa.c'))
 riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c'))
 riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
 riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
-- 
2.28.0

From: Anup Patel <anup.patel@wdc.com>

We extend RISC-V spike machine to allow creating a multi-socket
machine. Each RISC-V spike machine socket is a NUMA node having
a set of HARTs, a memory instance, and a CLINT instance. Other
devices are shared between all sockets. We also update the
generated device tree accordingly.

By default, NUMA multi-socket support is disabled for RISC-V spike
machine. To enable it, users can use "-numa" command-line options
of QEMU.

Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"

Example2: For two NUMA nodes with 1 and 3 CPUs, append following
to command-line options:
"-smp 4 -numa node -numa node -numa cpu,node-id=0,core-id=0 \
-numa cpu,node-id=1,core-id=1 -numa cpu,node-id=1,core-id=2 \
-numa cpu,node-id=1,core-id=3"

The maximum number of sockets in a RISC-V spike machine is 8
but this limit can be changed in future.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-5-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/spike.h |  11 +-
 hw/riscv/spike.c         | 232 ++++++++++++++++++++++++++-------------
 2 files changed, 167 insertions(+), 76 deletions(-)

diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/sysbus.h"
 
+#define SPIKE_CPUS_MAX 8
+#define SPIKE_SOCKETS_MAX 8
+
+#define TYPE_SPIKE_MACHINE MACHINE_TYPE_NAME("spike")
+#define SPIKE_MACHINE(obj) \
+    OBJECT_CHECK(SpikeState, (obj), TYPE_SPIKE_MACHINE)
+
 typedef struct {
     /*< private >*/
-    SysBusDevice parent_obj;
+    MachineState parent;
 
     /*< public >*/
-    RISCVHartArrayState soc;
+    RISCVHartArrayState soc[SPIKE_SOCKETS_MAX];
     void *fdt;
     int fdt_size;
 } SpikeState;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/sifive_clint.h"
 #include "hw/riscv/spike.h"
 #include "hw/riscv/boot.h"
+#include "hw/riscv/numa.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
     uint64_t mem_size, const char *cmdline)
 {
     void *fdt;
-    int cpu;
-    uint32_t *cells;
-    char *nodename;
+    uint64_t addr, size;
+    unsigned long clint_addr;
+    int cpu, socket;
+    MachineState *mc = MACHINE(s);
+    uint32_t *clint_cells;
+    uint32_t cpu_phandle, intc_phandle, phandle = 1;
+    char *name, *mem_name, *clint_name, *clust_name;
+    char *core_name, *cpu_name, *intc_name;
 
     fdt = s->fdt = create_device_tree(&s->fdt_size);
     if (!fdt) {
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 
-    nodename = g_strdup_printf("/memory@%lx",
-        (long)memmap[SPIKE_DRAM].base);
-    qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base,
-        mem_size >> 32, mem_size);
-    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
-    g_free(nodename);
-
     qemu_fdt_add_subnode(fdt, "/cpus");
     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
         SIFIVE_CLINT_TIMEBASE_FREQ);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
+    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
+
+    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+        clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
+        qemu_fdt_add_subnode(fdt, clust_name);
+
+        clint_cells =  g_new0(uint32_t, s->soc[socket].num_harts * 4);
 
-    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
-        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
-        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
-        char *isa = riscv_isa_string(&s->soc.harts[cpu]);
-        qemu_fdt_add_subnode(fdt, nodename);
+        for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
+            cpu_phandle = phandle++;
+
+            cpu_name = g_strdup_printf("/cpus/cpu@%d",
+                s->soc[socket].hartid_base + cpu);
+            qemu_fdt_add_subnode(fdt, cpu_name);
 #if defined(TARGET_RISCV32)
-        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
+            qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
 #else
-        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
+            qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
 #endif
-        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
-        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
-        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
-        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
-        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
-        qemu_fdt_add_subnode(fdt, intc);
-        qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
-        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
-        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
-        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
-        g_free(isa);
-        g_free(intc);
-        g_free(nodename);
-    }
+            name = riscv_isa_string(&s->soc[socket].harts[cpu]);
+            qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
+            g_free(name);
+            qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
+            qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
+            qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
+                s->soc[socket].hartid_base + cpu);
+            qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
+            riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
+            qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
 
-    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
-    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
-        nodename =
-            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
-        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
-        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
-        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
-        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
-        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
-        g_free(nodename);
+            intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
+            qemu_fdt_add_subnode(fdt, intc_name);
+            intc_phandle = phandle++;
+            qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
+            qemu_fdt_setprop_string(fdt, intc_name, "compatible",
+                "riscv,cpu-intc");
+            qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
+            qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
+
+            clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
+            clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
+            clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
+            clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
+
+            core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
+            qemu_fdt_add_subnode(fdt, core_name);
+            qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
+
+            g_free(core_name);
+            g_free(intc_name);
+            g_free(cpu_name);
+        }
+
+        addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket);
+        size = riscv_socket_mem_size(mc, socket);
+        mem_name = g_strdup_printf("/memory@%lx", (long)addr);
+        qemu_fdt_add_subnode(fdt, mem_name);
+        qemu_fdt_setprop_cells(fdt, mem_name, "reg",
+            addr >> 32, addr, size >> 32, size);
+        qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
+        riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
+        g_free(mem_name);
+
+        clint_addr = memmap[SPIKE_CLINT].base +
+            (memmap[SPIKE_CLINT].size * socket);
+        clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
+        qemu_fdt_add_subnode(fdt, clint_name);
+        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
+        qemu_fdt_setprop_cells(fdt, clint_name, "reg",
+            0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size);
+        qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
+            clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+        riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
+
+        g_free(clint_name);
+        g_free(clint_cells);
+        g_free(clust_name);
     }
-    nodename = g_strdup_printf("/soc/clint@%lx",
-        (long)memmap[SPIKE_CLINT].base);
-    qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
-    qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        0x0, memmap[SPIKE_CLINT].base,
-        0x0, memmap[SPIKE_CLINT].size);
-    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
-        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
-    g_free(cells);
-    g_free(nodename);
+
+    riscv_socket_fdt_write_distance_matrix(mc, fdt);
 
     if (cmdline) {
         qemu_fdt_add_subnode(fdt, "/chosen");
@@ -XXX,XX +XXX,XX @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
 static void spike_board_init(MachineState *machine)
 {
     const struct MemmapEntry *memmap = spike_memmap;
-
-    SpikeState *s = g_new0(SpikeState, 1);
+    SpikeState *s = SPIKE_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
-    unsigned int smp_cpus = machine->smp.cpus;
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
+    char *soc_name;
+    int i, base_hartid, hart_count;
 
-    /* Initialize SOC */
-    object_initialize_child(OBJECT(machine), "soc", &s->soc,
-                            TYPE_RISCV_HART_ARRAY);
-    object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
-                            &error_abort);
-    object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
-                            &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
+    /* Check socket count limit */
+    if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) {
+        error_report("number of sockets/nodes should be less than %d",
+            SPIKE_SOCKETS_MAX);
+        exit(1);
+    }
+
+    /* Initialize sockets */
+    for (i = 0; i < riscv_socket_count(machine); i++) {
+        if (!riscv_socket_check_hartids(machine, i)) {
+            error_report("discontinuous hartids in socket%d", i);
+            exit(1);
+        }
+
+        base_hartid = riscv_socket_first_hartid(machine, i);
+        if (base_hartid < 0) {
+            error_report("can't find hartid base for socket%d", i);
+            exit(1);
+        }
+
+        hart_count = riscv_socket_hart_count(machine, i);
+        if (hart_count < 0) {
+            error_report("can't find hart count for socket%d", i);
+            exit(1);
+        }
+
+        soc_name = g_strdup_printf("soc%d", i);
+        object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
+                                TYPE_RISCV_HART_ARRAY);
+        g_free(soc_name);
+        object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
+                                machine->cpu_type, &error_abort);
+        object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
+                                base_hartid, &error_abort);
+        object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
+                                hart_count, &error_abort);
+        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
+
+        /* Core Local Interruptor (timer and IPI) for each socket */
+        sifive_clint_create(
+            memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size,
+            memmap[SPIKE_CLINT].size, base_hartid, hart_count,
+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
+    }
 
     /* register system main memory (actual RAM) */
     memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
@@ -XXX,XX +XXX,XX @@ static void spike_board_init(MachineState *machine)
                               fdt_load_addr, s->fdt);
 
     /* initialize HTIF using symbols found in load_kernel */
-    htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
+    htif_mm_init(system_memory, mask_rom,
+                 &s->soc[0].harts[0].env, serial_hd(0));
+}
 
-    /* Core Local Interruptor (timer and IPI) */
-    sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
-        0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
-        false);
+static void spike_machine_instance_init(Object *obj)
+{
 }
 
-static void spike_machine_init(MachineClass *mc)
+static void spike_machine_class_init(ObjectClass *oc, void *data)
 {
-    mc->desc = "RISC-V Spike Board";
+    MachineClass *mc = MACHINE_CLASS(oc);
+
+    mc->desc = "RISC-V Spike board";
     mc->init = spike_board_init;
-    mc->max_cpus = 8;
+    mc->max_cpus = SPIKE_CPUS_MAX;
     mc->is_default = true;
     mc->default_cpu_type = SPIKE_V1_10_0_CPU;
+    mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
+    mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
+    mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
+    mc->numa_mem_supported = true;
+}
+
+static const TypeInfo spike_machine_typeinfo = {
+    .name       = MACHINE_TYPE_NAME("spike"),
+    .parent     = TYPE_MACHINE,
+    .class_init = spike_machine_class_init,
+    .instance_init = spike_machine_instance_init,
+    .instance_size = sizeof(SpikeState),
+};
+
+static void spike_machine_init_register_types(void)
+{
+    type_register_static(&spike_machine_typeinfo);
 }
 
-DEFINE_MACHINE("spike", spike_machine_init)
+type_init(spike_machine_init_register_types)
-- 
2.28.0

From: Anup Patel <anup.patel@wdc.com>

We extend RISC-V virt machine to allow creating a multi-socket
machine. Each RISC-V virt machine socket is a NUMA node having
a set of HARTs, a memory instance, a CLINT instance, and a PLIC
instance. Other devices are shared between all sockets. We also
update the generated device tree accordingly.

By default, NUMA multi-socket support is disabled for RISC-V virt
machine. To enable it, users can use "-numa" command-line options
of QEMU.

Example1: For two NUMA nodes with 2 CPUs each, append following
to command-line options: "-smp 4 -numa node -numa node"

The maximum number of sockets in a RISC-V virt machine is 8
but this limit can be changed in future.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Message-Id: <20200616032229.766089-6-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |   9 +-
 hw/riscv/virt.c         | 526 +++++++++++++++++++++++-----------------
 2 files changed, 306 insertions(+), 229 deletions(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/block/flash.h"
 
+#define VIRT_CPUS_MAX 8
+#define VIRT_SOCKETS_MAX 8
+
 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
 #define RISCV_VIRT_MACHINE(obj) \
     OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE)
@@ -XXX,XX +XXX,XX @@ typedef struct {
     MachineState parent;
 
     /*< public >*/
-    RISCVHartArrayState soc;
-    DeviceState *plic;
+    RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
+    DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
 
     void *fdt;
@@ -XXX,XX +XXX,XX @@ enum {
 #define VIRT_PLIC_ENABLE_STRIDE 0x80
 #define VIRT_PLIC_CONTEXT_BASE 0x200000
 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000
+#define VIRT_PLIC_SIZE(__num_context) \
+    (VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
 
 #define FDT_PCI_ADDR_CELLS    3
 #define FDT_PCI_INT_CELLS     1
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/riscv/sifive_test.h"
 #include "hw/riscv/virt.h"
 #include "hw/riscv/boot.h"
+#include "hw/riscv/numa.h"
 #include "chardev/char.h"
 #include "sysemu/arch_init.h"
 #include "sysemu/device_tree.h"
@@ -XXX,XX +XXX,XX @@ static const struct MemmapEntry {
     [VIRT_RTC] =         {   0x101000,        0x1000 },
     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
     [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
-    [VIRT_PLIC] =        {  0xc000000,     0x4000000 },
+    [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
     uint64_t mem_size, const char *cmdline)
 {
     void *fdt;
-    int cpu, i;
-    uint32_t *cells;
-    char *nodename;
-    uint32_t plic_phandle, test_phandle, phandle = 1;
+    int i, cpu, socket;
+    MachineState *mc = MACHINE(s);
+    uint64_t addr, size;
+    uint32_t *clint_cells, *plic_cells;
+    unsigned long clint_addr, plic_addr;
+    uint32_t plic_phandle[MAX_NODES];
+    uint32_t cpu_phandle, intc_phandle, test_phandle;
+    uint32_t phandle = 1, plic_mmio_phandle = 1;
+    uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
+    char *mem_name, *cpu_name, *core_name, *intc_name;
+    char *name, *clint_name, *plic_name, *clust_name;
     hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
     hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
 
@@ -XXX,XX +XXX,XX @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 
-    nodename = g_strdup_printf("/memory@%lx",
-        (long)memmap[VIRT_DRAM].base);
-    qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
-        mem_size >> 32, mem_size);
-    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
-    g_free(nodename);
-
     qemu_fdt_add_subnode(fdt, "/cpus");
     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
                           SIFIVE_CLINT_TIMEBASE_FREQ);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
+    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
+
+    for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
+        clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
+        qemu_fdt_add_subnode(fdt, clust_name);
+
+        plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+        clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
+
+        for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
+            cpu_phandle = phandle++;
 
-    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
-        int cpu_phandle = phandle++;
-        int intc_phandle;
-        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
-        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
-        char *isa = riscv_isa_string(&s->soc.harts[cpu]);
-        qemu_fdt_add_subnode(fdt, nodename);
+            cpu_name = g_strdup_printf("/cpus/cpu@%d",
+                s->soc[socket].hartid_base + cpu);
+            qemu_fdt_add_subnode(fdt, cpu_name);
 #if defined(TARGET_RISCV32)
-        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
+            qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
 #else
-        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
+            qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
 #endif
-        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
-        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
-        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
-        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
-        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
-        qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
-        intc_phandle = phandle++;
-        qemu_fdt_add_subnode(fdt, intc);
-        qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
-        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
-        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
-        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
-        g_free(isa);
-        g_free(intc);
-        g_free(nodename);
-    }
+            name = riscv_isa_string(&s->soc[socket].harts[cpu]);
+            qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
+            g_free(name);
+            qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
+            qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
+            qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
+                s->soc[socket].hartid_base + cpu);
+            qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
+            riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
+            qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
+
+            intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
+            qemu_fdt_add_subnode(fdt, intc_name);
+            intc_phandle = phandle++;
+            qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
+            qemu_fdt_setprop_string(fdt, intc_name, "compatible",
+                "riscv,cpu-intc");
+            qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
+            qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
+
+            clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
+            clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
+            clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
+            clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
+
+            plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
+            plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
+            plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
+            plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
+
+            core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
+            qemu_fdt_add_subnode(fdt, core_name);
+            qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
+
+            g_free(core_name);
+            g_free(intc_name);
+            g_free(cpu_name);
+        }
 
-    /* Add cpu-topology node */
-    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
-    qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
-    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
-        char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
-                                              cpu);
-        char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
-        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
-        qemu_fdt_add_subnode(fdt, core_nodename);
-        qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
-        g_free(core_nodename);
-        g_free(cpu_nodename);
+        addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
+        size = riscv_socket_mem_size(mc, socket);
+        mem_name = g_strdup_printf("/memory@%lx", (long)addr);
+        qemu_fdt_add_subnode(fdt, mem_name);
+        qemu_fdt_setprop_cells(fdt, mem_name, "reg",
+            addr >> 32, addr, size >> 32, size);
+        qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
+        riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
+        g_free(mem_name);
+
+        clint_addr = memmap[VIRT_CLINT].base +
+            (memmap[VIRT_CLINT].size * socket);
+        clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
+        qemu_fdt_add_subnode(fdt, clint_name);
+        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
+        qemu_fdt_setprop_cells(fdt, clint_name, "reg",
+            0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
+        qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
+            clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+        riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
+        g_free(clint_name);
+
+        plic_phandle[socket] = phandle++;
+        plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
+        plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
+        qemu_fdt_add_subnode(fdt, plic_name);
+        qemu_fdt_setprop_cell(fdt, plic_name,
+            "#address-cells", FDT_PLIC_ADDR_CELLS);
+        qemu_fdt_setprop_cell(fdt, plic_name,
+            "#interrupt-cells", FDT_PLIC_INT_CELLS);
+        qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
+        qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
+        qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
+            plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+        qemu_fdt_setprop_cells(fdt, plic_name, "reg",
+            0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
+        qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
+        riscv_socket_fdt_write_id(mc, fdt, plic_name, socket);
+        qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]);
+        g_free(plic_name);
+
+        g_free(clint_cells);
+        g_free(plic_cells);
+        g_free(clust_name);
     }
 
-    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
-    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
-        nodename =
-            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
-        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
-        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
-        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
-        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
-        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
-        g_free(nodename);
-    }
-    nodename = g_strdup_printf("/soc/clint@%lx",
-        (long)memmap[VIRT_CLINT].base);
-    qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
-    qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        0x0, memmap[VIRT_CLINT].base,
-        0x0, memmap[VIRT_CLINT].size);
-    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
-        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
-    g_free(cells);
-    g_free(nodename);
-
-    plic_phandle = phandle++;
-    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
-    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
-        nodename =
-            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
-        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
-        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
-        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
-        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
-        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
-        g_free(nodename);
+    for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+        if (socket == 0) {
+            plic_mmio_phandle = plic_phandle[socket];
+            plic_virtio_phandle = plic_phandle[socket];
+            plic_pcie_phandle = plic_phandle[socket];
+        }
+        if (socket == 1) {
+            plic_virtio_phandle = plic_phandle[socket];
+            plic_pcie_phandle = plic_phandle[socket];
+        }
+        if (socket == 2) {
+            plic_pcie_phandle = plic_phandle[socket];
+        }
     }
-    nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
-        (long)memmap[VIRT_PLIC].base);
-    qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
-                          FDT_PLIC_ADDR_CELLS);
-    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
-                          FDT_PLIC_INT_CELLS);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
-    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
-    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
-        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
-    qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        0x0, memmap[VIRT_PLIC].base,
-        0x0, memmap[VIRT_PLIC].size);
-    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
-    qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
-    plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
-    g_free(cells);
-    g_free(nodename);
+
+    riscv_socket_fdt_write_distance_matrix(mc, fdt);
 
     for (i = 0; i < VIRTIO_COUNT; i++) {
-        nodename = g_strdup_printf("/virtio_mmio@%lx",
+        name = g_strdup_printf("/soc/virtio_mmio@%lx",
             (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
-        qemu_fdt_add_subnode(fdt, nodename);
-        qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
-        qemu_fdt_setprop_cells(fdt, nodename, "reg",
+        qemu_fdt_add_subnode(fdt, name);
+        qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
+        qemu_fdt_setprop_cells(fdt, name, "reg",
             0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
             0x0, memmap[VIRT_VIRTIO].size);
-        qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
-        qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
-        g_free(nodename);
+        qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
+            plic_virtio_phandle);
+        qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
+        g_free(name);
     }
 
-    nodename = g_strdup_printf("/soc/pci@%lx",
+    name = g_strdup_printf("/soc/pci@%lx",
         (long) memmap[VIRT_PCIE_ECAM].base);
-    qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_cell(fdt, nodename, "#address-cells",
-                          FDT_PCI_ADDR_CELLS);
-    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells",
-                          FDT_PCI_INT_CELLS);
-    qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible",
-                            "pci-host-ecam-generic");
-    qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
-    qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
-    qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
-                           memmap[VIRT_PCIE_ECAM].size /
-                               PCIE_MMCFG_SIZE_MIN - 1);
-    qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
-    qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base,
-                           0, memmap[VIRT_PCIE_ECAM].size);
-    qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges",
+    qemu_fdt_add_subnode(fdt, name);
+    qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
+    qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
+    qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
+    qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
+    qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
+    qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
+    qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
+        memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
+    qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
+    qemu_fdt_setprop_cells(fdt, name, "reg", 0,
+        memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
+    qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
         1, FDT_PCI_RANGE_IOPORT, 2, 0,
         2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
         1, FDT_PCI_RANGE_MMIO,
         2, memmap[VIRT_PCIE_MMIO].base,
         2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size);
-    create_pcie_irq_map(fdt, nodename, plic_phandle);
-    g_free(nodename);
+    create_pcie_irq_map(fdt, name, plic_pcie_phandle);
+    g_free(name);
 
     test_phandle = phandle++;
-    nodename = g_strdup_printf("/test@%lx",
+    name = g_strdup_printf("/soc/test@%lx",
         (long)memmap[VIRT_TEST].base);
-    qemu_fdt_add_subnode(fdt, nodename);
+    qemu_fdt_add_subnode(fdt, name);
     {
         const char compat[] = "sifive,test1\0sifive,test0\0syscon";
-        qemu_fdt_setprop(fdt, nodename, "compatible", compat, sizeof(compat));
+        qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat));
     }
-    qemu_fdt_setprop_cells(fdt, nodename, "reg",
+    qemu_fdt_setprop_cells(fdt, name, "reg",
         0x0, memmap[VIRT_TEST].base,
         0x0, memmap[VIRT_TEST].size);
-    qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_phandle);
-    test_phandle = qemu_fdt_get_phandle(fdt, nodename);
-    g_free(nodename);
-
-    nodename = g_strdup_printf("/reboot");
-    qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
-    qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
-    qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
-    qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
-    g_free(nodename);
-
-    nodename = g_strdup_printf("/poweroff");
-    qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
-    qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_phandle);
-    qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
-    qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
-    g_free(nodename);
-
-    nodename = g_strdup_printf("/uart@%lx",
-        (long)memmap[VIRT_UART0].base);
-    qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
-    qemu_fdt_setprop_cells(fdt, nodename, "reg",
+    qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
+    test_phandle = qemu_fdt_get_phandle(fdt, name);
+    g_free(name);
+
+    name = g_strdup_printf("/soc/reboot");
+    qemu_fdt_add_subnode(fdt, name);
+    qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
+    qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
+    qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
+    qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
+    g_free(name);
+
+    name = g_strdup_printf("/soc/poweroff");
+    qemu_fdt_add_subnode(fdt, name);
+    qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
+    qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
+    qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
+    qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
+    g_free(name);
+
+    name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
+    qemu_fdt_add_subnode(fdt, name);
+    qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
+    qemu_fdt_setprop_cells(fdt, name, "reg",
         0x0, memmap[VIRT_UART0].base,
         0x0, memmap[VIRT_UART0].size);
-    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
-    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
-    qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ);
+    qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
+    qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
+    qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ);
 
     qemu_fdt_add_subnode(fdt, "/chosen");
-    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
+    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
     if (cmdline) {
         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
     }
-    g_free(nodename);
-
-    nodename = g_strdup_printf("/rtc@%lx",
-        (long)memmap[VIRT_RTC].base);
-    qemu_fdt_add_subnode(fdt, nodename);
-    qemu_fdt_setprop_string(fdt, nodename, "compatible",
-        "google,goldfish-rtc");
-    qemu_fdt_setprop_cells(fdt, nodename, "reg",
+    g_free(name);
+
+    name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
+    qemu_fdt_add_subnode(fdt, name);
+    qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
+    qemu_fdt_setprop_cells(fdt, name, "reg",
         0x0, memmap[VIRT_RTC].base,
         0x0, memmap[VIRT_RTC].size);
-    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
-    qemu_fdt_setprop_cell(fdt, nodename, "interrupts", RTC_IRQ);
-    g_free(nodename);
-
-    nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
-    qemu_fdt_add_subnode(s->fdt, nodename);
-    qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash");
-    qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
+    qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
+    qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
+    g_free(name);
+
+    name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
+    qemu_fdt_add_subnode(s->fdt, name);
+    qemu_fdt_setprop_string(s->fdt, name, "compatible", "cfi-flash");
+    qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
                                  2, flashbase, 2, flashsize,
                                  2, flashbase + flashsize, 2, flashsize);
-    qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4);
-    g_free(nodename);
+    qemu_fdt_setprop_cell(s->fdt, name, "bank-width", 4);
+    g_free(name);
 }
 
-
 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
                                           hwaddr ecam_base, hwaddr ecam_size,
                                           hwaddr mmio_base, hwaddr mmio_size,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
-    char *plic_hart_config;
+    char *plic_hart_config, *soc_name;
     size_t plic_hart_config_len;
     target_ulong start_addr = memmap[VIRT_DRAM].base;
     uint32_t fdt_load_addr;
     uint64_t kernel_entry;
-    int i;
-    unsigned int smp_cpus = machine->smp.cpus;
+    DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
+    int i, j, base_hartid, hart_count;
 
-    /* Initialize SOC */
-    object_initialize_child(OBJECT(machine), "soc", &s->soc,
-                            TYPE_RISCV_HART_ARRAY);
-    object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
-                            &error_abort);
-    object_property_set_int(OBJECT(&s->soc), "num-harts", smp_cpus,
-                            &error_abort);
-    sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_abort);
+    /* Check socket count limit */
+    if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
+        error_report("number of sockets/nodes should be less than %d",
+            VIRT_SOCKETS_MAX);
+        exit(1);
+    }
+
+    /* Initialize sockets */
+    mmio_plic = virtio_plic = pcie_plic = NULL;
+    for (i = 0; i < riscv_socket_count(machine); i++) {
+        if (!riscv_socket_check_hartids(machine, i)) {
+            error_report("discontinuous hartids in socket%d", i);
+            exit(1);
+        }
+
+        base_hartid = riscv_socket_first_hartid(machine, i);
+        if (base_hartid < 0) {
+            error_report("can't find hartid base for socket%d", i);
+            exit(1);
+        }
+
+        hart_count = riscv_socket_hart_count(machine, i);
+        if (hart_count < 0) {
+            error_report("can't find hart count for socket%d", i);
+            exit(1);
+        }
+
+        soc_name = g_strdup_printf("soc%d", i);
+        object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
+                                TYPE_RISCV_HART_ARRAY);
+        g_free(soc_name);
+        object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
+                                machine->cpu_type, &error_abort);
+        object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
+                                base_hartid, &error_abort);
+        object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
+                                hart_count, &error_abort);
+        sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
+
+        /* Per-socket CLINT */
+        sifive_clint_create(
+            memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
+            memmap[VIRT_CLINT].size, base_hartid, hart_count,
+            SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
+
+        /* Per-socket PLIC hart topology configuration string */
+        plic_hart_config_len =
+            (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
+        plic_hart_config = g_malloc0(plic_hart_config_len);
+        for (j = 0; j < hart_count; j++) {
+            if (j != 0) {
+                strncat(plic_hart_config, ",", plic_hart_config_len);
+            }
+            strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
+                plic_hart_config_len);
+            plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
+        }
+
+        /* Per-socket PLIC */
+        s->plic[i] = sifive_plic_create(
+            memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
+            plic_hart_config, base_hartid,
+            VIRT_PLIC_NUM_SOURCES,
+            VIRT_PLIC_NUM_PRIORITIES,
+            VIRT_PLIC_PRIORITY_BASE,
+            VIRT_PLIC_PENDING_BASE,
+            VIRT_PLIC_ENABLE_BASE,
+            VIRT_PLIC_ENABLE_STRIDE,
+            VIRT_PLIC_CONTEXT_BASE,
+            VIRT_PLIC_CONTEXT_STRIDE,
+            memmap[VIRT_PLIC].size);
+        g_free(plic_hart_config);
+
+        /* Try to use different PLIC instance based device type */
+        if (i == 0) {
+            mmio_plic = s->plic[i];
+            virtio_plic = s->plic[i];
+            pcie_plic = s->plic[i];
+        }
+        if (i == 1) {
+            virtio_plic = s->plic[i];
+            pcie_plic = s->plic[i];
+        }
+        if (i == 2) {
+            pcie_plic = s->plic[i];
+        }
+    }
 
     /* register system main memory (actual RAM) */
     memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                               virt_memmap[VIRT_MROM].size, kernel_entry,
                               fdt_load_addr, s->fdt);
 
-    /* create PLIC hart topology configuration string */
-    plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
-    plic_hart_config = g_malloc0(plic_hart_config_len);
-    for (i = 0; i < smp_cpus; i++) {
-        if (i != 0) {
-            strncat(plic_hart_config, ",", plic_hart_config_len);
-        }
-        strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
-        plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
-    }
-
-    /* MMIO */
-    s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
-        plic_hart_config, 0,
-        VIRT_PLIC_NUM_SOURCES,
-        VIRT_PLIC_NUM_PRIORITIES,
-        VIRT_PLIC_PRIORITY_BASE,
-        VIRT_PLIC_PENDING_BASE,
-        VIRT_PLIC_ENABLE_BASE,
-        VIRT_PLIC_ENABLE_STRIDE,
-        VIRT_PLIC_CONTEXT_BASE,
-        VIRT_PLIC_CONTEXT_STRIDE,
-        memmap[VIRT_PLIC].size);
-    sifive_clint_create(memmap[VIRT_CLINT].base,
-        memmap[VIRT_CLINT].size, 0, smp_cpus,
-        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
+    /* SiFive Test MMIO device */
     sifive_test_create(memmap[VIRT_TEST].base);
 
+    /* VirtIO MMIO devices */
     for (i = 0; i < VIRTIO_COUNT; i++) {
         sysbus_create_simple("virtio-mmio",
             memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
-            qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
+            qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
     }
 
     gpex_pcie_init(system_memory,
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                          memmap[VIRT_PCIE_MMIO].base,
                          memmap[VIRT_PCIE_MMIO].size,
                          memmap[VIRT_PCIE_PIO].base,
-                         DEVICE(s->plic), true);
+                         DEVICE(pcie_plic), true);
 
     serial_mm_init(system_memory, memmap[VIRT_UART0].base,
-        0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
+        0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
         serial_hd(0), DEVICE_LITTLE_ENDIAN);
 
     sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
-        qdev_get_gpio_in(DEVICE(s->plic), RTC_IRQ));
+        qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
 
     virt_flash_create(s);
 
@@ -XXX,XX +XXX,XX @@ static void virt_machine_init(MachineState *machine)
                                   drive_get(IF_PFLASH, 0, i));
     }
     virt_flash_map(s, system_memory);
-
-    g_free(plic_hart_config);
 }
 
 static void virt_machine_instance_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
 
     mc->desc = "RISC-V VirtIO board";
     mc->init = virt_machine_init;
-    mc->max_cpus = 8;
+    mc->max_cpus = VIRT_CPUS_MAX;
     mc->default_cpu_type = VIRT_CPU;
     mc->pci_allow_0_address = true;
+    mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
+    mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
+    mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
+    mc->numa_mem_supported = true;
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.28.0

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com
Message-Id: <08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/cpu.h        |  2 ++
 target/riscv/cpu_bits.h   |  1 +
 target/riscv/cpu_helper.c | 18 ++++++++++++++++++
 3 files changed, 21 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
+bool riscv_cpu_two_stage_lookup(CPURISCVState *env);
+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);
 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
  * page table fault.
  */
 #define FORCE_HS_EXCEP      2
+#define HS_TWO_STAGE        4
 
 /* RV32 satp CSR field masks */
 #define SATP32_MODE         0x80000000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
     env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
 }
 
+bool riscv_cpu_two_stage_lookup(CPURISCVState *env)
+{
+    if (!riscv_has_ext(env, RVH)) {
+        return false;
+    }
+
+    return get_field(env->virt, HS_TWO_STAGE);
+}
+
+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable)
+{
+    if (!riscv_has_ext(env, RVH)) {
+        return;
+    }
+
+    env->virt = set_field(env->virt, HS_TWO_STAGE, enable);
+}
+
 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
 {
     CPURISCVState *env = &cpu->env;
-- 
2.28.0

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com
Message-Id: <477c864312280ea55a98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h                 |   1 +
 target/riscv/helper.h                   |   3 +
 target/riscv/insn32-64.decode           |   5 +
 target/riscv/insn32.decode              |  11 +
 target/riscv/op_helper.c                | 114 ++++++++
 target/riscv/insn_trans/trans_rvh.c.inc | 340 ++++++++++++++++++++++++
 6 files changed, 474 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define HSTATUS_SP2V         0x00000200
 #define HSTATUS_VTVM         0x00100000
 #define HSTATUS_VTSR         0x00400000
+#define HSTATUS_HU           0x00000200
 
 #define HSTATUS32_WPRI       0xFF8FF87E
 #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(tlb_flush, void, env)
 /* Hypervisor functions */
 #ifndef CONFIG_USER_ONLY
 DEF_HELPER_1(hyp_tlb_flush, void, env)
+DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
+DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
+DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
 #endif
 
 /* Vector functions */
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -XXX,XX +XXX,XX @@ fmv_x_d    1110001  00000 ..... 000 ..... 1010011 @r2
 fcvt_d_l   1101001  00010 ..... ... ..... 1010011 @r2_rm
 fcvt_d_lu  1101001  00011 ..... ... ..... 1010011 @r2_rm
 fmv_d_x    1111001  00000 ..... 000 ..... 1010011 @r2
+
+# *** RV32H Base Instruction Set ***
+hlv_wu    0110100  00001   ..... 100 ..... 1110011 @r2
+hlv_d     0110110  00000   ..... 100 ..... 1110011 @r2
+hsv_d     0110111  .....   ..... 100 00000 1110011 @r2_s
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -XXX,XX +XXX,XX @@
 @r_vm_0  ...... . ..... ..... ... ..... .......    &rmrr vm=0 %rs2 %rs1 %rd
 @r_wdvm  ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
 @r2_zimm . zimm:11  ..... ... ..... ....... %rs1 %rd
+@r2_s    .......   ..... ..... ... ..... ....... %rs2 %rs1
 
 @hfence_gvma ....... ..... .....   ... ..... ....... %rs2 %rs1
 @hfence_vvma ....... ..... .....   ... ..... ....... %rs2 %rs1
@@ -XXX,XX +XXX,XX @@ fcvt_d_w   1101001  00000 ..... ... ..... 1010011 @r2_rm
 fcvt_d_wu  1101001  00001 ..... ... ..... 1010011 @r2_rm
 
 # *** RV32H Base Instruction Set ***
+hlv_b       0110000  00000  ..... 100 ..... 1110011 @r2
+hlv_bu      0110000  00001  ..... 100 ..... 1110011 @r2
+hlv_h       0110010  00000  ..... 100 ..... 1110011 @r2
+hlv_hu      0110010  00001  ..... 100 ..... 1110011 @r2
+hlvx_hu     0110010  00011  ..... 100 ..... 1110011 @r2
+hlv_w       0110100  00000  ..... 100 ..... 1110011 @r2
+hlvx_wu     0110100  00011  ..... 100 ..... 1110011 @r2
+hsv_b       0110001  .....  ..... 100 00000 1110011 @r2_s
+hsv_h       0110011  .....  ..... 100 00000 1110011 @r2_s
+hsv_w       0110101  .....  ..... 100 00000 1110011 @r2_s
 hfence_gvma 0110001  .....  ..... 000 00000 1110011 @hfence_gvma
 hfence_vvma 0010001  .....  ..... 000 00000 1110011 @hfence_vvma
 
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env)
     riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 }
 
+target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
+                             target_ulong attrs, target_ulong memop)
+{
+    if (env->priv == PRV_M ||
+        (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+        (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+            get_field(env->hstatus, HSTATUS_HU))) {
+        target_ulong pte;
+
+        riscv_cpu_set_two_stage_lookup(env, true);
+
+        switch (memop) {
+        case MO_SB:
+            pte = cpu_ldsb_data_ra(env, address, GETPC());
+            break;
+        case MO_UB:
+            pte = cpu_ldub_data_ra(env, address, GETPC());
+            break;
+        case MO_TESW:
+            pte = cpu_ldsw_data_ra(env, address, GETPC());
+            break;
+        case MO_TEUW:
+            pte = cpu_lduw_data_ra(env, address, GETPC());
+            break;
+        case MO_TESL:
+            pte = cpu_ldl_data_ra(env, address, GETPC());
+            break;
+        case MO_TEUL:
+            pte = cpu_ldl_data_ra(env, address, GETPC());
+            break;
+        case MO_TEQ:
+            pte = cpu_ldq_data_ra(env, address, GETPC());
+            break;
+        default:
+            g_assert_not_reached();
+        }
+
+        riscv_cpu_set_two_stage_lookup(env, false);
+
+        return pte;
+    }
+
+    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    return 0;
+}
+
+void helper_hyp_store(CPURISCVState *env, target_ulong address,
+                      target_ulong val, target_ulong attrs, target_ulong memop)
+{
+    if (env->priv == PRV_M ||
+        (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+        (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+            get_field(env->hstatus, HSTATUS_HU))) {
+        riscv_cpu_set_two_stage_lookup(env, true);
+
+        switch (memop) {
+        case MO_SB:
+        case MO_UB:
+            cpu_stb_data_ra(env, address, val, GETPC());
+            break;
+        case MO_TESW:
+        case MO_TEUW:
+            cpu_stw_data_ra(env, address, val, GETPC());
+            break;
+        case MO_TESL:
+        case MO_TEUL:
+            cpu_stl_data_ra(env, address, val, GETPC());
+            break;
+        case MO_TEQ:
+            cpu_stq_data_ra(env, address, val, GETPC());
+            break;
+        default:
+            g_assert_not_reached();
+        }
+
+        riscv_cpu_set_two_stage_lookup(env, false);
+
+        return;
+    }
+
+    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+}
+
+target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
+                               target_ulong attrs, target_ulong memop)
+{
+    if (env->priv == PRV_M ||
+        (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+        (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+            get_field(env->hstatus, HSTATUS_HU))) {
+        target_ulong pte;
+
+        riscv_cpu_set_two_stage_lookup(env, true);
+
+        switch (memop) {
+        case MO_TEUL:
+            pte = cpu_ldub_data_ra(env, address, GETPC());
+            break;
+        case MO_TEUW:
+            pte = cpu_lduw_data_ra(env, address, GETPC());
+            break;
+        default:
+            g_assert_not_reached();
+        }
+
+        riscv_cpu_set_two_stage_lookup(env, false);
+
+        return pte;
+    }
+
+    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    return 0;
+}
+
 #endif /* !CONFIG_USER_ONLY */
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_SB);
+
+    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+    gen_set_gpr(a->rd, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_TESW);
+
+    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+    gen_set_gpr(a->rd, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_TESL);
+
+    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+    gen_set_gpr(a->rd, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_UB);
+
+    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+    gen_set_gpr(a->rd, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_TEUW);
+
+    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+    gen_set_gpr(a->rd, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv dat = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(dat, a->rs2);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_SB);
+
+    gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(dat);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv dat = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(dat, a->rs2);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_TESW);
+
+    gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(dat);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv dat = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(dat, a->rs2);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_TESL);
+
+    gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(dat);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_TEUL);
+
+    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+    gen_set_gpr(a->rd, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_TEQ);
+
+    gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+    gen_set_gpr(a->rd, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv dat = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    gen_get_gpr(dat, a->rs2);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_TEQ);
+
+    gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(dat);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+#endif
+
+static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_TEUW);
+
+    gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
+    gen_set_gpr(a->rd, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
+{
+    REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+    TCGv t0 = tcg_temp_new();
+    TCGv t1 = tcg_temp_new();
+    TCGv mem_idx = tcg_temp_new();
+    TCGv memop = tcg_temp_new();
+
+    gen_get_gpr(t0, a->rs1);
+    tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+    tcg_gen_movi_tl(memop, MO_TEUL);
+
+    gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
+    gen_set_gpr(a->rd, t1);
+
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
+    tcg_temp_free(mem_idx);
+    tcg_temp_free(memop);
+    return true;
+#else
+    return false;
+#endif
+}
+
 static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
 {
     REQUIRE_EXT(ctx, RVH);
-- 
2.28.0

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com
Message-Id: <024ad8a594fb2feaf0950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 60 ++++++++++++++++-----------------------
 1 file changed, 25 insertions(+), 35 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
      * was called. Background registers will be used if the guest has
      * forced a two stage translation to be on (in HS or M mode).
      */
+    if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) {
+        use_background = true;
+    }
+
     if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
-
-            if (riscv_has_ext(env, RVH) &&
-                MSTATUS_MPV_ISSET(env)) {
-                use_background = true;
-            }
-        }
-    }
-
-    if (mode == PRV_S && access_type != MMU_INST_FETCH &&
-        riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
-        if (get_field(env->hstatus, HSTATUS_SPRV)) {
-            mode = get_field(env->mstatus, SSTATUS_SPP);
-            use_background = true;
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
         }
         break;
     case MMU_DATA_LOAD:
-        if (riscv_cpu_virt_enabled(env) && !first_stage) {
+        if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
+            !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
             cs->exception_index = page_fault_exceptions ?
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
         }
         break;
     case MMU_DATA_STORE:
-        if (riscv_cpu_virt_enabled(env) && !first_stage) {
+        if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
+            !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
             cs->exception_index = page_fault_exceptions ?
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     hwaddr pa = 0;
     int prot, prot2;
     bool pmp_violation = false;
-    bool m_mode_two_stage = false;
-    bool hs_mode_two_stage = false;
     bool first_stage_error = true;
     int ret = TRANSLATE_FAIL;
     int mode = mmu_idx;
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
                   __func__, address, access_type, mmu_idx);
 
-    /*
-     * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
-     * set and we want to access a virtulisation address.
-     */
-    if (riscv_has_ext(env, RVH)) {
-        m_mode_two_stage = env->priv == PRV_M &&
-                           access_type != MMU_INST_FETCH &&
-                           get_field(env->mstatus, MSTATUS_MPRV) &&
-                           MSTATUS_MPV_ISSET(env);
-
-        hs_mode_two_stage = env->priv == PRV_S &&
-                            !riscv_cpu_virt_enabled(env) &&
-                            access_type != MMU_INST_FETCH &&
-                            get_field(env->hstatus, HSTATUS_SPRV) &&
-                            get_field(env->hstatus, HSTATUS_SPV);
-    }
-
     if (mode == PRV_M && access_type != MMU_INST_FETCH) {
         if (get_field(env->mstatus, MSTATUS_MPRV)) {
             mode = get_field(env->mstatus, MSTATUS_MPP);
         }
     }
 
-    if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
+    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+        access_type != MMU_INST_FETCH &&
+        get_field(env->mstatus, MSTATUS_MPRV) &&
+        MSTATUS_MPV_ISSET(env)) {
+        riscv_cpu_set_two_stage_lookup(env, true);
+    }
+
+    if (riscv_cpu_virt_enabled(env) ||
+        (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) {
         /* Two stage lookup */
         ret = get_physical_address(env, &pa, &prot, address, access_type,
                                    mmu_idx, true, true);
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       __func__, address, ret, pa, prot);
     }
 
+    /* We did the two stage lookup based on MPRV, unset the lookup */
+    if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+        access_type != MMU_INST_FETCH &&
+        get_field(env->mstatus, MSTATUS_MPRV) &&
+        MSTATUS_MPV_ISSET(env)) {
+        riscv_cpu_set_two_stage_lookup(env, false);
+    }
+
     if (riscv_feature(env, RISCV_FEATURE_PMP) &&
         (ret == TRANSLATE_SUCCESS) &&
         !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
-- 
2.28.0

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com
Message-Id: <9308432988946de550a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h   |  5 +++--
 target/riscv/cpu_helper.c | 24 ++++++++++++++++++++----
 target/riscv/csr.c        |  6 +++---
 3 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define MSTATUS_TW          0x20000000 /* since: priv-1.10 */
 #define MSTATUS_TSR         0x40000000 /* since: priv-1.10 */
 #if defined(TARGET_RISCV64)
-#define MSTATUS_MTL         0x4000000000ULL
+#define MSTATUS_GVA         0x4000000000ULL
 #define MSTATUS_MPV         0x8000000000ULL
 #elif defined(TARGET_RISCV32)
-#define MSTATUS_MTL         0x00000040
+#define MSTATUS_GVA         0x00000040
 #define MSTATUS_MPV         0x00000080
 #endif
 
@@ -XXX,XX +XXX,XX @@
 #define HSTATUS_VTVM         0x00100000
 #define HSTATUS_VTSR         0x00400000
 #define HSTATUS_HU           0x00000200
+#define HSTATUS_GVA          0x00000040
 
 #define HSTATUS32_WPRI       0xFF8FF87E
 #define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
         if (riscv_has_ext(env, RVH)) {
             target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
 
+            if ((riscv_cpu_virt_enabled(env) ||
+                 riscv_cpu_two_stage_lookup(env)) && tval) {
+                /*
+                 * If we are writing a guest virtual address to stval, set
+                 * this to 1. If we are trapping to VS we will set this to 0
+                 * later.
+                 */
+                env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1);
+            } else {
+                /* For other HS-mode traps, we set this to 0. */
+                env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
+            }
+
             if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
                 !force_hs_execp) {
                 /*
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
                     cause == IRQ_VS_EXT)
                     cause = cause - 1;
                 /* Trap to VS mode */
+                env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
             } else if (riscv_cpu_virt_enabled(env)) {
                 /* Trap into HS mode, from virt */
                 riscv_cpu_swap_hypervisor_regs(env);
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
 #ifdef TARGET_RISCV32
             env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
                                        riscv_cpu_virt_enabled(env));
-            env->mstatush = set_field(env->mstatush, MSTATUS_MTL,
-                                       riscv_cpu_force_hs_excep_enabled(env));
+            if (riscv_cpu_virt_enabled(env) && tval) {
+                env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1);
+            }
 #else
             env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
                                       riscv_cpu_virt_enabled(env));
-            env->mstatus = set_field(env->mstatus, MSTATUS_MTL,
-                                      riscv_cpu_force_hs_excep_enabled(env));
+            if (riscv_cpu_virt_enabled(env) && tval) {
+                env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
+            }
 #endif
 
             mtval2 = env->guest_phys_fault_addr;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
         MSTATUS_TW;
 #if defined(TARGET_RISCV64)
     /*
-     * RV32: MPV and MTL are not in mstatus. The current plan is to
+     * RV32: MPV and GVA are not in mstatus. The current plan is to
      * add them to mstatush. For now, we just don't support it.
      */
-    mask |= MSTATUS_MTL | MSTATUS_MPV;
+    mask |= MSTATUS_MPV | MSTATUS_GVA;
 #endif
 
     mstatus = (mstatus & ~mask) | (val & mask);
@@ -XXX,XX +XXX,XX @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
         tlb_flush(env_cpu(env));
     }
 
-    val &= MSTATUS_MPV | MSTATUS_MTL;
+    val &= MSTATUS_MPV | MSTATUS_GVA;
 
     env->mstatush = val;
 
-- 
2.28.0

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com
Message-Id: <85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
 
             if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
                 !force_hs_execp) {
+                /* Trap to VS mode */
                 /*
                  * See if we need to adjust cause. Yes if its VS mode interrupt
                  * no if hypervisor has delegated one of hs mode's interrupt
                  */
                 if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
-                    cause == IRQ_VS_EXT)
+                    cause == IRQ_VS_EXT) {
                     cause = cause - 1;
-                /* Trap to VS mode */
+                }
                 env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
             } else if (riscv_cpu_virt_enabled(env)) {
                 /* Trap into HS mode, from virt */
-- 
2.28.0

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com
Message-Id: <e7e4e801234f2934306e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h   |  1 +
 target/riscv/cpu_helper.c | 16 ++++++----------
 target/riscv/op_helper.c  |  8 ++------
 target/riscv/translate.c  | 10 ----------
 4 files changed, 9 insertions(+), 26 deletions(-)

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com
Message-Id: <4f227b30cb1816795296c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com
Message-Id: <f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/csr.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->hstatus;
+#ifdef TARGET_RISCV64
+    /* We only support 64-bit VSXL */
+    *val = set_field(*val, HSTATUS_VSXL, 2);
+#endif
     return 0;
 }
 
 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
 {
     env->hstatus = val;
+#ifdef TARGET_RISCV64
+    if (get_field(val, HSTATUS_VSXL) != 2) {
+        qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
+    }
+#endif
     return 0;
 }
 
-- 
2.28.0

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com
Message-Id: <93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/csr.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
     /* We only support 64-bit VSXL */
     *val = set_field(*val, HSTATUS_VSXL, 2);
 #endif
+    /* We only support little endian */
+    *val = set_field(*val, HSTATUS_VSBE, 0);
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
     }
 #endif
+    if (get_field(val, HSTATUS_VSBE) != 0) {
+        qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
+    }
     return 0;
 }
 
-- 
2.28.0

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com
Message-Id: <644b6c114b1a81adbee0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h |  3 +++
 target/riscv/csr.c      | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define CSR_HIDELEG         0x603
 #define CSR_HIE             0x604
 #define CSR_HCOUNTEREN      0x606
+#define CSR_HGEIE           0x607
 #define CSR_HTVAL           0x643
+#define CSR_HVIP            0x645
 #define CSR_HIP             0x644
 #define CSR_HTINST          0x64A
+#define CSR_HGEIP           0xE12
 #define CSR_HGATP           0x680
 #define CSR_HTIMEDELTA      0x605
 #define CSR_HTIMEDELTAH     0x615
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+                   target_ulong new_value, target_ulong write_mask)
+{
+    int ret = rmw_mip(env, 0, ret_value, new_value,
+                      write_mask & hip_writable_mask);
+
+    *ret_value &= hip_writable_mask;
+
+    return ret;
+}
+
 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
                    target_ulong new_value, target_ulong write_mask)
 {
     int ret = rmw_mip(env, 0, ret_value, new_value,
                       write_mask & hip_writable_mask);
 
+    *ret_value &= hip_writable_mask;
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
+static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->htval;
@@ -XXX,XX +XXX,XX @@ static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
     return 0;
 }
 
+static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
+static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
+{
+    qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+    return 0;
+}
+
 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
 {
     *val = env->hgatp;
@@ -XXX,XX +XXX,XX @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_HSTATUS] =             { hmode,   read_hstatus,     write_hstatus    },
     [CSR_HEDELEG] =             { hmode,   read_hedeleg,     write_hedeleg    },
     [CSR_HIDELEG] =             { hmode,   read_hideleg,     write_hideleg    },
+    [CSR_HVIP] =                { hmode,   NULL,     NULL,     rmw_hvip       },
     [CSR_HIP] =                 { hmode,   NULL,     NULL,     rmw_hip        },
     [CSR_HIE] =                 { hmode,   read_hie,         write_hie        },
     [CSR_HCOUNTEREN] =          { hmode,   read_hcounteren,  write_hcounteren },
+    [CSR_HGEIE] =               { hmode,   read_hgeie,       write_hgeie      },
     [CSR_HTVAL] =               { hmode,   read_htval,       write_htval      },
     [CSR_HTINST] =              { hmode,   read_htinst,      write_htinst     },
+    [CSR_HGEIP] =               { hmode,   read_hgeip,       write_hgeip      },
     [CSR_HGATP] =               { hmode,   read_hgatp,       write_hgatp      },
     [CSR_HTIMEDELTA] =          { hmode,   read_htimedelta,  write_htimedelta },
 #if defined(TARGET_RISCV32)
-- 
2.28.0

When performing a CSR access let's return a negative exception value on
an error instead of -1. This will allow us to specify the exception in
future patches.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com
Message-Id: <a487dad60c9b8fe7a2b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/csr.c       | 46 ++++++++++++++++++++--------------------
 target/riscv/op_helper.c | 18 ++++++++++------
 2 files changed, 35 insertions(+), 29 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int fs(CPURISCVState *env, int csrno)
         return 0;
     }
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     return 0;
@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
 
     if (!cpu->cfg.ext_counters) {
         /* The Counters extensions is not enabled */
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     return 0;
@@ -XXX,XX +XXX,XX @@ static int hmode(CPURISCVState *env, int csrno)
         }
     }
 
-    return -1;
+    return -RISCV_EXCP_ILLEGAL_INST;
 }
 
 static int pmp(CPURISCVState *env, int csrno)
@@ -XXX,XX +XXX,XX @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     *val = riscv_cpu_get_fflags(env);
@@ -XXX,XX +XXX,XX @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
     env->mstatus |= MSTATUS_FS;
 #endif
@@ -XXX,XX +XXX,XX @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     *val = env->frm;
@@ -XXX,XX +XXX,XX @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
     env->mstatus |= MSTATUS_FS;
 #endif
@@ -XXX,XX +XXX,XX @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
@@ -XXX,XX +XXX,XX @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
     env->mstatus |= MSTATUS_FS;
 #endif
@@ -XXX,XX +XXX,XX @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 
     if (!env->rdtime_fn) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = env->rdtime_fn() + delta;
@@ -XXX,XX +XXX,XX @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 
     if (!env->rdtime_fn) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = (env->rdtime_fn() + delta) >> 32;
@@ -XXX,XX +XXX,XX @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (env->priv_ver < PRIV_VERSION_1_11_0) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
     *val = env->mcounteren;
     return 0;
@@ -XXX,XX +XXX,XX @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
 {
     if (env->priv_ver < PRIV_VERSION_1_11_0) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
     env->mcounteren = val;
     return 0;
@@ -XXX,XX +XXX,XX @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
     }
 
     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     } else {
         *val = env->satp;
     }
@@ -XXX,XX +XXX,XX @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
         ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
     {
         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
-            return -1;
+            return -RISCV_EXCP_ILLEGAL_INST;
         } else {
             if((val ^ env->satp) & SATP_ASID) {
                 tlb_flush(env_cpu(env));
@@ -XXX,XX +XXX,XX @@ static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
 static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (!env->rdtime_fn) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 
 #if defined(TARGET_RISCV32)
@@ -XXX,XX +XXX,XX @@ static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
 static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
 {
     if (!env->rdtime_fn) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 
 #if defined(TARGET_RISCV32)
@@ -XXX,XX +XXX,XX @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
 static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
 {
     if (!env->rdtime_fn) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 
     *val = env->htimedelta >> 32;
@@ -XXX,XX +XXX,XX @@ static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
 static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
 {
     if (!env->rdtime_fn) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 
     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 
     if ((write_mask && read_only) ||
         (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 #endif
 
     /* ensure the CSR extension is enabled. */
     if (!cpu->cfg.ext_icsr) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 
     /* check predicate */
     if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 
     /* execute combined read/write operation if it exists */
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
 
     /* if no accessor exists then return failure */
     if (!csr_ops[csrno].read) {
-        return -1;
+        return -RISCV_EXCP_ILLEGAL_INST;
     }
 
     /* read old value */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
         target_ulong csr)
 {
     target_ulong val = 0;
-    if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
-        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    int ret = riscv_csrrw(env, csr, &val, src, -1);
+
+    if (ret < 0) {
+        riscv_raise_exception(env, -ret, GETPC());
     }
     return val;
 }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
         target_ulong csr, target_ulong rs1_pass)
 {
     target_ulong val = 0;
-    if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
-        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+
+    if (ret < 0) {
+        riscv_raise_exception(env, -ret, GETPC());
     }
     return val;
 }
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
         target_ulong csr, target_ulong rs1_pass)
 {
     target_ulong val = 0;
-    if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
-        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
+
+    if (ret < 0) {
+        riscv_raise_exception(env, -ret, GETPC());
     }
     return val;
 }
-- 
2.28.0

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com
Message-Id: <4c744dce9b0b057cbb5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h                 |  6 +++
 target/riscv/helper.h                   |  1 +
 target/riscv/csr.c                      | 64 ++++++++++++++++++++++++-
 target/riscv/op_helper.c                | 42 ++++++++++++++--
 target/riscv/insn_trans/trans_rvh.c.inc |  2 +-
 5 files changed, 109 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@
 #define HSTATUS_WPRI HSTATUS64_WPRI
 #endif
 
+#define HCOUNTEREN_CY        (1 << 0)
+#define HCOUNTEREN_TM        (1 << 1)
+#define HCOUNTEREN_IR        (1 << 2)
+#define HCOUNTEREN_HPM3      (1 << 3)
+
 /* Privilege modes */
 #define PRV_U 0
 #define PRV_S 1
@@ -XXX,XX +XXX,XX @@
 #define RISCV_EXCP_STORE_PAGE_FAULT              0xf /* since: priv-1.10.0 */
 #define RISCV_EXCP_INST_GUEST_PAGE_FAULT         0x14
 #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT       0x15
+#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT        0x16
 #define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT  0x17
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(tlb_flush, void, env)
 /* Hypervisor functions */
 #ifndef CONFIG_USER_ONLY
 DEF_HELPER_1(hyp_tlb_flush, void, env)
+DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)
 DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
 DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
 DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static int ctr(CPURISCVState *env, int csrno)
         /* The Counters extensions is not enabled */
         return -RISCV_EXCP_ILLEGAL_INST;
     }
+
+    if (riscv_cpu_virt_enabled(env)) {
+        switch (csrno) {
+        case CSR_CYCLE:
+            if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
+                get_field(env->mcounteren, HCOUNTEREN_CY)) {
+                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+            }
+            break;
+        case CSR_TIME:
+            if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
+                get_field(env->mcounteren, HCOUNTEREN_TM)) {
+                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+            }
+            break;
+        case CSR_INSTRET:
+            if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
+                get_field(env->mcounteren, HCOUNTEREN_IR)) {
+                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+            }
+            break;
+        case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
+                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+            }
+            break;
+#if defined(TARGET_RISCV32)
+        case CSR_CYCLEH:
+            if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
+                get_field(env->mcounteren, HCOUNTEREN_CY)) {
+                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+            }
+            break;
+        case CSR_TIMEH:
+            if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
+                get_field(env->mcounteren, HCOUNTEREN_TM)) {
+                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+            }
+            break;
+        case CSR_INSTRETH:
+            if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
+                get_field(env->mcounteren, HCOUNTEREN_IR)) {
+                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+            }
+            break;
+        case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
+                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+                return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+            }
+            break;
+#endif
+        }
+    }
 #endif
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ static int hmode(CPURISCVState *env, int csrno)
         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
             env->priv == PRV_M) {
             return 0;
+        } else {
+            return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
         }
     }
 
@@ -XXX,XX +XXX,XX @@ static const target_ulong delegable_excps =
     (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
     (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
     (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
+    (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
     (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
@@ -XXX,XX +XXX,XX @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
     }
 
     /* check predicate */
-    if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
+    if (!csr_ops[csrno].predicate) {
         return -RISCV_EXCP_ILLEGAL_INST;
     }
+    ret = csr_ops[csrno].predicate(env, csrno);
+    if (ret < 0) {
+        return ret;
+    }
 
     /* execute combined read/write operation if it exists */
     if (csr_ops[csrno].op) {
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
     }
 
+    if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
+        get_field(env->hstatus, HSTATUS_VTSR)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    }
+
     mstatus = env->mstatus;
 
     if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     if ((env->priv == PRV_S &&
         get_field(env->mstatus, MSTATUS_TW)) ||
         riscv_cpu_virt_enabled(env)) {
-        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
     } else {
         cs->halted = 1;
         cs->exception_index = EXCP_HLT;
@@ -XXX,XX +XXX,XX @@ void helper_tlb_flush(CPURISCVState *env)
         (env->priv == PRV_S &&
          get_field(env->mstatus, MSTATUS_TVM))) {
         riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
+               get_field(env->hstatus, HSTATUS_VTVM)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
     } else {
         tlb_flush(cs);
     }
@@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
 
+    if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    }
+
     if (env->priv == PRV_M ||
         (env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
         tlb_flush(cs);
@@ -XXX,XX +XXX,XX @@ void helper_hyp_tlb_flush(CPURISCVState *env)
     riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
 }
 
+void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
+{
+    if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
+        get_field(env->mstatus, MSTATUS_TVM)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+
+    helper_hyp_tlb_flush(env);
+}
+
 target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
                              target_ulong attrs, target_ulong memop)
 {
@@ -XXX,XX +XXX,XX @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
         return pte;
     }
 
-    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    if (riscv_cpu_virt_enabled(env)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ void helper_hyp_store(CPURISCVState *env, target_ulong address,
         return;
     }
 
-    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    if (riscv_cpu_virt_enabled(env)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
 }
 
 target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
@@ -XXX,XX +XXX,XX @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
         return pte;
     }
 
-    riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    if (riscv_cpu_virt_enabled(env)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
     return 0;
 }
 
diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvh.c.inc
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
 {
     REQUIRE_EXT(ctx, RVH);
 #ifndef CONFIG_USER_ONLY
-    gen_helper_hyp_tlb_flush(cpu_env);
+    gen_helper_hyp_gvma_tlb_flush(cpu_env);
     return true;
 #endif
     return false;
-- 
2.28.0

The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:

Merge tag 'pull-error-2024-05-27' of https://repo.or.cz/qemu/armbru into staging (2024-05-27 06:40:42 -0700)

are available in the Git repository at:

https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240528

for you to fetch changes up to 1806da76cb81088ea026ca3441551782b850e393:

target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR (2024-05-28 12:20:27 +1000)

----------------------------------------------------------------
RISC-V PR for 9.1

* APLICs add child earlier than realize
* Fix exposure of Zkr
* Raise exceptions on wrs.nto
* Implement SBI debug console (DBCN) calls for KVM
* Support 64-bit addresses for initrd
* Change RISCV_EXCP_SEMIHOST exception number to 63
* Tolerate KVM disable ext errors
* Set tval in breakpoints
* Add support for Zve32x extension
* Add support for Zve64x extension
* Relax vector register check in RISCV gdbstub
* Fix the element agnostic Vector function problem
* Fix Zvkb extension config
* Implement dynamic establishment of custom decoder
* Add th.sxstatus CSR emulation
* Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
* Check single width operator for vector fp widen instructions
* Check single width operator for vfncvt.rod.f.f.w
* Remove redudant SEW checking for vector fp narrow/widen instructions
* Prioritize pmp errors in raise_mmu_exception()
* Do not set mtval2 for non guest-page faults
* Remove experimental prefix from "B" extension
* Fixup CBO extension register calculation
* Fix the hart bit setting of AIA
* Fix reg_width in ricsv_gen_dynamic_vector_feature()
* Decode all of the pmpcfg and pmpaddr CSRs
* Raise an exception when CSRRS/CSRRC writes a read-only CSR

----------------------------------------------------------------
Alexei Filippov (1):
      target/riscv: do not set mtval2 for non guest-page faults

Alistair Francis (2):
      target/riscv: rvzicbo: Fixup CBO extension register calculation
      disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs

Andrew Jones (2):
      target/riscv/kvm: Fix exposure of Zkr
      target/riscv: Raise exceptions on wrs.nto

Cheng Yang (1):
      hw/riscv/boot.c: Support 64-bit address for initrd

Christoph Müllner (1):
      riscv: thead: Add th.sxstatus CSR emulation

Clément Léger (1):
      target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

Daniel Henrique Barboza (6):
      target/riscv/kvm: implement SBI debug console (DBCN) calls
      target/riscv/kvm: tolerate KVM disable ext errors
      target/riscv/debug: set tval=pc in breakpoint exceptions
      trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint
      target/riscv: prioritize pmp errors in raise_mmu_exception()
      riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()

Huang Tao (2):
      target/riscv: Fix the element agnostic function problem
      target/riscv: Implement dynamic establishment of custom decoder

Jason Chien (3):
      target/riscv: Add support for Zve32x extension
      target/riscv: Add support for Zve64x extension
      target/riscv: Relax vector register check in RISCV gdbstub

Max Chou (4):
      target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions
      target/riscv: rvv: Check single width operator for vector fp widen instructions
      target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
      target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions

Rob Bradford (1):
      target/riscv: Remove experimental prefix from "B" extension

Yangyu Chen (1):
      target/riscv/cpu.c: fix Zvkb extension config

Yong-Xuan Wang (1):
      target/riscv/kvm.c: Fix the hart bit setting of AIA

Yu-Ming Chang (1):
      target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

yang.zhang (1):
      hw/intc/riscv_aplic: APLICs should add child earlier than realize

From: "yang.zhang" <yang.zhang@hexintek.com>

Since only root APLICs can have hw IRQ lines, aplic->parent should
be initialized first.

Fixes: e8f79343cf ("hw/intc: Add RISC-V AIA APLIC device emulation")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: yang.zhang <yang.zhang@hexintek.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240409014445.278-1-gaoshanliukou@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/riscv_aplic.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -XXX,XX +XXX,XX @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
     qdev_prop_set_bit(dev, "msimode", msimode);
     qdev_prop_set_bit(dev, "mmode", mmode);
 
+    if (parent) {
+        riscv_aplic_add_child(parent, dev);
+    }
+
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 
     if (!is_kvm_aia(msimode)) {
         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
     }
 
-    if (parent) {
-        riscv_aplic_add_child(parent, dev);
-    }
-
     if (!msimode) {
         for (i = 0; i < num_harts; i++) {
             CPUState *cpu = cpu_by_arch_id(hartid_base + i);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

The Zkr extension may only be exposed to KVM guests if the VMM
implements the SEED CSR. Use the same implementation as TCG.

Without this patch, running with a KVM which does not forward the
SEED CSR access to QEMU will result in an ILL exception being
injected into the guest (this results in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.

Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422134605.534207-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  3 +++
 target/riscv/csr.c         | 18 ++++++++++++++----
 target/riscv/kvm/kvm-cpu.c | 25 +++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
 
 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
 
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask);
+
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno,
 #endif
 
 /* Crypto Extension */
-static RISCVException rmw_seed(CPURISCVState *env, int csrno,
-                               target_ulong *ret_value,
-                               target_ulong new_value,
-                               target_ulong write_mask)
+target_ulong riscv_new_csr_seed(target_ulong new_value,
+                                target_ulong write_mask)
 {
     uint16_t random_v;
     Error *random_e = NULL;
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
         rval = random_v | SEED_OPST_ES16;
     }
 
+    return rval;
+}
+
+static RISCVException rmw_seed(CPURISCVState *env, int csrno,
+                               target_ulong *ret_value,
+                               target_ulong new_value,
+                               target_ulong write_mask)
+{
+    target_ulong rval;
+
+    rval = riscv_new_csr_seed(new_value, write_mask);
+
     if (ret_value) {
         *ret_value = rval;
     }
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
     return ret;
 }
 
+static int kvm_riscv_handle_csr(CPUState *cs, struct kvm_run *run)
+{
+    target_ulong csr_num = run->riscv_csr.csr_num;
+    target_ulong new_value = run->riscv_csr.new_value;
+    target_ulong write_mask = run->riscv_csr.write_mask;
+    int ret = 0;
+
+    switch (csr_num) {
+    case CSR_SEED:
+        run->riscv_csr.ret_value = riscv_new_csr_seed(new_value, write_mask);
+        break;
+    default:
+        qemu_log_mask(LOG_UNIMP,
+                      "%s: un-handled CSR EXIT for CSR %lx\n",
+                      __func__, csr_num);
+        ret = -1;
+        break;
+    }
+
+    return ret;
+}
+
 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
     case KVM_EXIT_RISCV_SBI:
         ret = kvm_riscv_handle_sbi(cs, run);
         break;
+    case KVM_EXIT_RISCV_CSR:
+        ret = kvm_riscv_handle_csr(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
                       __func__, run->exit_reason);
-- 
2.45.1

From: Andrew Jones <ajones@ventanamicro.com>

Implementing wrs.nto to always just return is consistent with the
specification, as the instruction is permitted to terminate the
stall for any reason, but it's not useful for virtualization, where
we'd like the guest to trap to the hypervisor in order to allow
scheduling of the lock holding VCPU. Change to always immediately
raise exceptions when the appropriate conditions are present,
otherwise continue to just return. Note, immediately raising
exceptions is also consistent with the specification since the
time limit that should expire prior to the exception is
implementation-specific.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240424142808.62936-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                       |  1 +
 target/riscv/op_helper.c                    | 11 ++++++++
 target/riscv/insn_trans/trans_rvzawrs.c.inc | 29 ++++++++++++++-------
 3 files changed, 32 insertions(+), 9 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
 DEF_HELPER_1(sret, tl, env)
 DEF_HELPER_1(mret, tl, env)
 DEF_HELPER_1(wfi, void, env)
+DEF_HELPER_1(wrs_nto, void, env)
 DEF_HELPER_1(tlb_flush, void, env)
 DEF_HELPER_1(tlb_flush_all, void, env)
 /* Native Debug */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ void helper_wfi(CPURISCVState *env)
     }
 }
 
+void helper_wrs_nto(CPURISCVState *env)
+{
+    if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) &&
+        get_field(env->hstatus, HSTATUS_VTW) &&
+        !get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+    } else if (env->priv != PRV_M && get_field(env->mstatus, MSTATUS_TW)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+}
+
 void helper_tlb_flush(CPURISCVState *env)
 {
     CPUState *cs = env_cpu(env);
diff --git a/target/riscv/insn_trans/trans_rvzawrs.c.inc b/target/riscv/insn_trans/trans_rvzawrs.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzawrs.c.inc
+++ b/target/riscv/insn_trans/trans_rvzawrs.c.inc
@@ -XXX,XX +XXX,XX @@
  * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-static bool trans_wrs(DisasContext *ctx)
+static bool trans_wrs_sto(DisasContext *ctx, arg_wrs_sto *a)
 {
     if (!ctx->cfg_ptr->ext_zawrs) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_wrs(DisasContext *ctx)
     return true;
 }
 
-#define GEN_TRANS_WRS(insn)                                     \
-static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn *a)  \
-{                                                               \
-    (void)a;                                                    \
-    return trans_wrs(ctx);                                      \
-}
+static bool trans_wrs_nto(DisasContext *ctx, arg_wrs_nto *a)
+{
+    if (!ctx->cfg_ptr->ext_zawrs) {
+        return false;
+    }
 
-GEN_TRANS_WRS(wrs_nto)
-GEN_TRANS_WRS(wrs_sto)
+    /*
+     * Depending on the mode of execution, mstatus.TW and hstatus.VTW, wrs.nto
+     * should raise an exception when the implementation-specific bounded time
+     * limit has expired. Our time limit is zero, so we either return
+     * immediately, as does our implementation of wrs.sto, or raise an
+     * exception, as handled by the wrs.nto helper.
+     */
+#ifndef CONFIG_USER_ONLY
+    gen_helper_wrs_nto(tcg_env);
+#endif
+
+    /* We only get here when helper_wrs_nto() doesn't raise an exception. */
+    return trans_wrs_sto(ctx, NULL);
+}
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

SBI defines a Debug Console extension "DBCN" that will, in time, replace
the legacy console putchar and getchar SBI extensions.

The appeal of the DBCN extension is that it allows multiple bytes to be
read/written in the SBI console in a single SBI call.

As far as KVM goes, the DBCN calls are forwarded by an in-kernel KVM
module to userspace. But this will only happens if the KVM module
actually supports this SBI extension and we activate it.

We'll check for DBCN support during init time, checking if get-reg-list
is advertising KVM_RISCV_SBI_EXT_DBCN. In that case, we'll enable it via
kvm_set_one_reg() during kvm_arch_init_vcpu().

Finally, change kvm_riscv_handle_sbi() to handle the incoming calls for
SBI_EXT_DBCN, reading and writing as required.

A simple KVM guest with 'earlycon=sbi', running in an emulated RISC-V
host, takes around 20 seconds to boot without using DBCN. With this
patch we're taking around 14 seconds to boot due to the speed-up in the
terminal output.  There's no change in boot time if the guest isn't
using earlycon.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240425155012.581366-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/sbi_ecall_interface.h |  17 +++++
 target/riscv/kvm/kvm-cpu.c         | 111 +++++++++++++++++++++++++++++
 2 files changed, 128 insertions(+)

diff --git a/target/riscv/sbi_ecall_interface.h b/target/riscv/sbi_ecall_interface.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/sbi_ecall_interface.h
+++ b/target/riscv/sbi_ecall_interface.h
@@ -XXX,XX +XXX,XX @@
 
 /* clang-format off */
 
+#define SBI_SUCCESS                      0
+#define SBI_ERR_FAILED                  -1
+#define SBI_ERR_NOT_SUPPORTED           -2
+#define SBI_ERR_INVALID_PARAM           -3
+#define SBI_ERR_DENIED                  -4
+#define SBI_ERR_INVALID_ADDRESS         -5
+#define SBI_ERR_ALREADY_AVAILABLE       -6
+#define SBI_ERR_ALREADY_STARTED         -7
+#define SBI_ERR_ALREADY_STOPPED         -8
+#define SBI_ERR_NO_SHMEM                -9
+
 /* SBI Extension IDs */
 #define SBI_EXT_0_1_SET_TIMER           0x0
 #define SBI_EXT_0_1_CONSOLE_PUTCHAR     0x1
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_IPI                     0x735049
 #define SBI_EXT_RFENCE                  0x52464E43
 #define SBI_EXT_HSM                     0x48534D
+#define SBI_EXT_DBCN                    0x4442434E
 
 /* SBI function IDs for BASE extension */
 #define SBI_EXT_BASE_GET_SPEC_VERSION   0x0
@@ -XXX,XX +XXX,XX @@
 #define SBI_EXT_HSM_HART_STOP           0x1
 #define SBI_EXT_HSM_HART_GET_STATUS     0x2
 
+/* SBI function IDs for DBCN extension */
+#define SBI_EXT_DBCN_CONSOLE_WRITE      0x0
+#define SBI_EXT_DBCN_CONSOLE_READ       0x1
+#define SBI_EXT_DBCN_CONSOLE_WRITE_BYTE 0x2
+
 #define SBI_HSM_HART_STATUS_STARTED     0x0
 #define SBI_HSM_HART_STATUS_STOPPED     0x1
 #define SBI_HSM_HART_STATUS_START_PENDING   0x2
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static KVMCPUConfig kvm_v_vlenb = {
                    KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)
 };
 
+static KVMCPUConfig kvm_sbi_dbcn = {
+    .name = "sbi_dbcn",
+    .kvm_reg_id = KVM_REG_RISCV | KVM_REG_SIZE_U64 |
+                  KVM_REG_RISCV_SBI_EXT | KVM_RISCV_SBI_EXT_DBCN
+};
+
 static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
 {
     CPURISCVState *env = &cpu->env;
@@ -XXX,XX +XXX,XX @@ static int uint64_cmp(const void *a, const void *b)
     return 0;
 }
 
+static void kvm_riscv_check_sbi_dbcn_support(RISCVCPU *cpu,
+                                             KVMScratchCPU *kvmcpu,
+                                             struct kvm_reg_list *reglist)
+{
+    struct kvm_reg_list *reg_search;
+
+    reg_search = bsearch(&kvm_sbi_dbcn.kvm_reg_id, reglist->reg, reglist->n,
+                         sizeof(uint64_t), uint64_cmp);
+
+    if (reg_search) {
+        kvm_sbi_dbcn.supported = true;
+    }
+}
+
 static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
                                  struct kvm_reg_list *reglist)
 {
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
     if (riscv_has_ext(&cpu->env, RVV)) {
         kvm_riscv_read_vlenb(cpu, kvmcpu, reglist);
     }
+
+    kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
 }
 
 static void riscv_init_kvm_registers(Object *cpu_obj)
@@ -XXX,XX +XXX,XX @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs)
     return ret;
 }
 
+static int kvm_vcpu_enable_sbi_dbcn(RISCVCPU *cpu, CPUState *cs)
+{
+    target_ulong reg = 1;
+
+    if (!kvm_sbi_dbcn.supported) {
+        return 0;
+    }
+
+    return kvm_set_one_reg(cs, kvm_sbi_dbcn.kvm_reg_id, &reg);
+}
+
 int kvm_arch_init_vcpu(CPUState *cs)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs)
     kvm_riscv_update_cpu_misa_ext(cpu, cs);
     kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
 
+    ret = kvm_vcpu_enable_sbi_dbcn(cpu, cs);
+
     return ret;
 }
 
@@ -XXX,XX +XXX,XX @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
     return true;
 }
 
+static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
+{
+    g_autofree uint8_t *buf = NULL;
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    target_ulong num_bytes;
+    uint64_t addr;
+    unsigned char ch;
+    int ret;
+
+    switch (run->riscv_sbi.function_id) {
+    case SBI_EXT_DBCN_CONSOLE_READ:
+    case SBI_EXT_DBCN_CONSOLE_WRITE:
+        num_bytes = run->riscv_sbi.args[0];
+
+        if (num_bytes == 0) {
+            run->riscv_sbi.ret[0] = SBI_SUCCESS;
+            run->riscv_sbi.ret[1] = 0;
+            break;
+        }
+
+        addr = run->riscv_sbi.args[1];
+
+        /*
+         * Handle the case where a 32 bit CPU is running in a
+         * 64 bit addressing env.
+         */
+        if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) {
+            addr |= (uint64_t)run->riscv_sbi.args[2] << 32;
+        }
+
+        buf = g_malloc0(num_bytes);
+
+        if (run->riscv_sbi.function_id == SBI_EXT_DBCN_CONSOLE_READ) {
+            ret = qemu_chr_fe_read_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_READ: error when "
+                             "reading chardev");
+                exit(1);
+            }
+
+            cpu_physical_memory_write(addr, buf, ret);
+        } else {
+            cpu_physical_memory_read(addr, buf, num_bytes);
+
+            ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
+            if (ret < 0) {
+                error_report("SBI_EXT_DBCN_CONSOLE_WRITE: error when "
+                             "writing chardev");
+                exit(1);
+            }
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = ret;
+        break;
+    case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
+        ch = run->riscv_sbi.args[0];
+        ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
+
+        if (ret < 0) {
+            error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
+                         "writing chardev");
+            exit(1);
+        }
+
+        run->riscv_sbi.ret[0] = SBI_SUCCESS;
+        run->riscv_sbi.ret[1] = 0;
+        break;
+    default:
+        run->riscv_sbi.ret[0] = SBI_ERR_NOT_SUPPORTED;
+    }
+}
+
 static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
 {
     int ret = 0;
@@ -XXX,XX +XXX,XX @@ static int kvm_riscv_handle_sbi(CPUState *cs, struct kvm_run *run)
         }
         ret = 0;
         break;
+    case SBI_EXT_DBCN:
+        kvm_riscv_handle_sbi_dbcn(cs, run);
+        break;
     default:
         qemu_log_mask(LOG_UNIMP,
                       "%s: un-handled SBI EXIT, specific reasons is %lu\n",
-- 
2.45.1

From: Cheng Yang <yangcheng.work@foxmail.com>

Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.

Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_A4482251DD0890F312758FA6B33F60815609@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -XXX,XX +XXX,XX @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
     /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
     if (fdt) {
         end = start + size;
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start);
-        qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
+        qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
     }
 }
 
-- 
2.45.1

From: Clément Léger <cleger@rivosinc.com>

The current semihost exception number (16) is a reserved number (range
[16-17]). The upcoming double trap specification uses that number for
the double trap exception. Since the privileged spec (Table 22) defines
ranges for custom uses change the semihosting exception number to 63
which belongs to the range [48-63] in order to avoid any future
collisions with reserved exception.

Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240422135840.1959967-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_bits.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -XXX,XX +XXX,XX @@ typedef enum RISCVException {
     RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
     RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
     RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
-    RISCV_EXCP_SEMIHOST = 0x10,
     RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
     RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
     RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
     RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
+    RISCV_EXCP_SEMIHOST = 0x3f,
 } RISCVException;
 
 #define RISCV_EXCP_INT_FLAG                0x80000000
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
enabled, will fail with a kernel oops SIGILL right at the start. The
reason is that we can't expose zkr without implementing the SEED CSR.
Disabling zkr in the guest would be a workaround, but if the KVM doesn't
allow it we'll error out and never boot.

In hindsight this is too strict. If we keep proceeding, despite not
disabling the extension in the KVM vcpu, we'll not add the extension in
the riscv,isa. The guest kernel will be unaware of the extension, i.e.
it doesn't matter if the KVM vcpu has it enabled underneath or not. So
it's ok to keep booting in this case.

Change our current logic to not error out if we fail to disable an
extension in kvm_set_one_reg(), but show a warning and keep booting. It
is important to throw a warning because we must make the user aware that
the extension is still available in the vcpu, meaning that an
ill-behaved guest can ignore the riscv,isa settings and  use the
extension.

The case we're handling happens with an EINVAL error code. If we fail to
disable the extension in KVM for any other reason, error out.

We'll also keep erroring out when we fail to enable an extension in KVM,
since adding the extension in riscv,isa at this point will cause a guest
malfunction because the extension isn't enabled in the vcpu.

Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240422171425.333037-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
         reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
         ret = kvm_set_one_reg(cs, id, &reg);
         if (ret != 0) {
-            error_report("Unable to %s extension %s in KVM, error %d",
-                         reg ? "enable" : "disable",
-                         multi_ext_cfg->name, ret);
-            exit(EXIT_FAILURE);
+            if (!reg && ret == -EINVAL) {
+                warn_report("KVM cannot disable extension %s",
+                            multi_ext_cfg->name);
+            } else {
+                error_report("Unable to enable extension %s in KVM, error %d",
+                             multi_ext_cfg->name, ret);
+                exit(EXIT_FAILURE);
+            }
         }
     }
 }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

We're not setting (s/m)tval when triggering breakpoints of type 2
(mcontrol) and 6 (mcontrol6). According to the debug spec section
5.7.12, "Match Control Type 6":

"The Privileged Spec says that breakpoint exceptions that occur on
instruction fetches, loads, or stores update the tval CSR with either
zero or the faulting virtual address. The faulting virtual address for
an mcontrol6 trigger with action = 0 is the address being accessed and
which caused that trigger to fire."

A similar text is also found in the Debug spec section 5.7.11 w.r.t.
mcontrol.

Note that what we're doing ATM is not violating the spec, but it's
simple enough to set mtval/stval and it makes life easier for any
software that relies on this info.

Given that we always use action = 0, save the faulting address for the
mcontrol and mcontrol6 trigger breakpoints into env->badaddr, which is
used as as scratch area for traps with address information. 'tval' is
then set during riscv_cpu_do_interrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240416230437.1869024-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 1 +
 target/riscv/debug.c      | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_do_interrupt(CPUState *cs)
             tval = env->bins;
             break;
         case RISCV_EXCP_BREAKPOINT:
+            tval = env->badaddr;
             if (cs->watchpoint_hit) {
                 tval = cs->watchpoint_hit->hitaddr;
                 cs->watchpoint_hit = NULL;
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
                     /* check U/S/M bit against current privilege level */
                     if ((ctrl >> 3) & BIT(env->priv)) {
+                        env->badaddr = pc;
                         return true;
                     }
                 }
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                     if (env->virt_enabled) {
                         /* check VU/VS bit against current privilege level */
                         if ((ctrl >> 23) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     } else {
                         /* check U/S/M bit against current privilege level */
                         if ((ctrl >> 3) & BIT(env->priv)) {
+                            env->badaddr = pc;
                             return true;
                         }
                     }
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Privileged spec section 4.1.9 mentions:

"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)

If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."

A similar text is found for mtval in section 3.1.16.

Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.

Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240416230437.1869024-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
     if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
         generate_exception(ctx, RISCV_EXCP_SEMIHOST);
     } else {
+        tcg_gen_st_tl(tcg_constant_tl(ebreak_addr), tcg_env,
+                      offsetof(CPURISCVState, badaddr));
         generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
     }
     return true;
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve32x extension and replace some checks for Zve32f with
Zve32x, since Zve32f depends on Zve32x.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-2-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h                  |  1 +
 target/riscv/cpu.c                      |  2 ++
 target/riscv/cpu_helper.c               |  2 +-
 target/riscv/csr.c                      |  2 +-
 target/riscv/tcg/tcg-cpu.c              | 16 ++++++++--------
 target/riscv/insn_trans/trans_rvv.c.inc |  4 ++--
 6 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -XXX,XX +XXX,XX @@ struct RISCVCPUConfig {
     bool ext_zhinx;
     bool ext_zhinxmin;
     bool ext_zve32f;
+    bool ext_zve32x;
     bool ext_zve64f;
     bool ext_zve64d;
     bool ext_zvbb;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVIsaExtData isa_edata_arr[] = {
     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
+    ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
+    MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
     *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
     *cs_base = 0;
 
-    if (cpu->cfg.ext_zve32f) {
+    if (cpu->cfg.ext_zve32x) {
         /*
          * If env->vl equals to VLMAX, we can use generic vector operation
          * expanders (GVEC) to accerlate the vector operations.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    if (riscv_cpu_cfg(env)->ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
-        error_setg(errp, "Zve32f/Zve64f extensions require F extension");
-        return;
+    /* The Zve32f extension depends on the Zve32x extension */
+    if (cpu->cfg.ext_zve32f) {
+        if (!riscv_has_ext(env, RVF)) {
+            error_setg(errp, "Zve32f/Zve64f extensions require F extension");
+            return;
+        }
+        cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
     }
 
     if (cpu->cfg.ext_zvfh) {
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
     }
 
-    /*
-     * In principle Zve*x would also suffice here, were they supported
-     * in qemu
-     */
     if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
          cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
-         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) {
+         cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
         error_setg(errp,
                    "Vector crypto extensions require V or Zve* extensions");
         return;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
 {
     TCGv s1, dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
@@ -XXX,XX +XXX,XX @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
 {
     TCGv dst;
 
-    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
+    if (!require_rvv(s) || !s->cfg_ptr->ext_zve32x) {
         return false;
     }
 
-- 
2.45.1

From: Jason Chien <jason.chien@sifive.com>

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu.c         |  2 ++
 target/riscv/tcg/tcg-cpu.c | 17 +++++++++++------
 3 files changed, 14 insertions(+), 6 deletions(-)

From: Jason Chien <jason.chien@sifive.com>

In current implementation, the gdbstub allows reading vector registers
only if V extension is supported. However, all vector extensions and
vector crypto extensions have the vector registers and they all depend
on Zve32x. The gdbstub should check for Zve32x instead.

Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Message-ID: <20240328022343.6871-4-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
                                  gdb_find_static_feature("riscv-32bit-fpu.xml"),
                                  0);
     }
-    if (env->misa_ext & RVV) {
+    if (cpu->cfg.ext_zve32x) {
         gdb_register_coprocessor(cs, riscv_gdb_get_vector,
                                  riscv_gdb_set_vector,
                                  ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.

However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240325021654.6594-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/vector_internals.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/vector_internals.c
+++ b/target/riscv/vector_internals.c
@@ -XXX,XX +XXX,XX @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt,
     if (tot - cnt == 0) {
         return ;
     }
+
+    if (HOST_BIG_ENDIAN) {
+        /*
+         * Deal the situation when the elements are insdie
+         * only one uint64 block including setting the
+         * masked-off element.
+         */
+        if (((tot - 1) ^ cnt) < 8) {
+            memset(base + H1(tot - 1), -1, tot - cnt);
+            return;
+        }
+        /*
+         * Otherwise, at least cross two uint64_t blocks.
+         * Set first unaligned block.
+         */
+        if (cnt % 8 != 0) {
+            uint32_t j = ROUND_UP(cnt, 8);
+            memset(base + H1(j - 1), -1, j - cnt);
+            cnt = j;
+        }
+        /* Set other 64bit aligend blocks */
+    }
     memset(base + cnt, -1, tot - cnt);
 }
 
-- 
2.45.1

From: Yangyu Chen <cyy@cyyself.name>

This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to riscv_cpu_extensions")
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by:  Weiwei Li <liwei1518@gmail.com>
Message-ID: <tencent_7E34EEF0F90B9A68BF38BEE09EC6D4877C0A@qq.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
     /* Vector cryptography extensions */
     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
-    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkg, false),
+    MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
-- 
2.45.1

From: Huang Tao <eric.huang@linux.alibaba.com>

In this patch, we modify the decoder to be a freely composable data
structure instead of a hardcoded one. It can be dynamically builded up
according to the extensions.
This approach has several benefits:
1. Provides support for heterogeneous cpu architectures. As we add decoder in
   RISCVCPU, each cpu can have their own decoder, and the decoders can be
   different due to cpu's features.
2. Improve the decoding efficiency. We run the guard_func to see if the decoder
   can be added to the dynamic_decoder when building up the decoder. Therefore,
   there is no need to run the guard_func when decoding each instruction. It can
   improve the decoding efficiency
3. For vendor or dynamic cpus, it allows them to customize their own decoder
   functions to improve decoding efficiency, especially when vendor-defined
   instruction sets increase. Because of dynamic building up, it can skip the other
   decoder guard functions when decoding.
4. Pre patch for allowing adding a vendor decoder before decode_insn32() with minimal
   overhead for users that don't need this particular vendor decoder.

Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
Suggested-by: Christoph Muellner <christoph.muellner@vrull.eu>
Co-authored-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240506023607.29544-1-eric.huang@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h         |  1 +
 target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++
 target/riscv/cpu.c         |  1 +
 target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++
 target/riscv/translate.c   | 31 +++++++++++++++----------------
 5 files changed, 47 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
     uint32_t pmu_avail_ctrs;
     /* Mapping of events to counters */
     GHashTable *pmu_event_ctr_map;
+    const GPtrArray *decoders;
 };
 
 /**
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
 
+struct DisasContext;
+struct RISCVCPUConfig;
+typedef struct RISCVDecoder {
+    bool (*guard_func)(const struct RISCVCPUConfig *);
+    bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+} RISCVDecoder;
+
+typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t);
+
+extern const size_t decoder_table_size;
+
+extern const RISCVDecoder decoder_table[];
+
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu);
+
 #endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
             error_propagate(errp, local_err);
             return;
         }
+        riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
     } else if (kvm_enabled()) {
         riscv_kvm_cpu_finalize_features(cpu, &local_err);
         if (local_err != NULL) {
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
     }
 }
 
+void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
+{
+    GPtrArray *dynamic_decoders;
+    dynamic_decoders = g_ptr_array_sized_new(decoder_table_size);
+    for (size_t i = 0; i < decoder_table_size; ++i) {
+        if (decoder_table[i].guard_func &&
+            decoder_table[i].guard_func(&cpu->cfg)) {
+            g_ptr_array_add(dynamic_decoders,
+                            (gpointer)decoder_table[i].riscv_cpu_decode_fn);
+        }
+    }
+
+    cpu->decoders = dynamic_decoders;
+}
+
 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu)
 {
     return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/helper-info.c.inc"
 #undef  HELPER_H
 
+#include "tcg/tcg-cpu.h"
+
 /* global register indices */
 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     /* FRM is known to contain a valid value. */
     bool frm_valid;
     bool insn_start_updated;
+    const GPtrArray *decoders;
 } DisasContext;
 
 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
@@ -XXX,XX +XXX,XX @@ static inline int insn_len(uint16_t first_word)
     return (first_word & 3) == 3 ? 4 : 2;
 }
 
+const RISCVDecoder decoder_table[] = {
+    { always_true_p, decode_insn32 },
+    { has_xthead_p, decode_xthead},
+    { has_XVentanaCondOps_p, decode_XVentanaCodeOps},
+};
+
+const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
+
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
-    /*
-     * A table with predicate (i.e., guard) functions and decoder functions
-     * that are tested in-order until a decoder matches onto the opcode.
-     */
-    static const struct {
-        bool (*guard_func)(const RISCVCPUConfig *);
-        bool (*decode_func)(DisasContext *, uint32_t);
-    } decoders[] = {
-        { always_true_p,  decode_insn32 },
-        { has_xthead_p, decode_xthead },
-        { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
-    };
-
     ctx->virt_inst_excp = false;
     ctx->cur_insn_len = insn_len(opcode);
     /* Check for compressed insn */
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                                              ctx->base.pc_next + 2));
         ctx->opcode = opcode32;
 
-        for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
-            if (decoders[i].guard_func(ctx->cfg_ptr) &&
-                decoders[i].decode_func(ctx, opcode32)) {
+        for (guint i = 0; i < ctx->decoders->len; ++i) {
+            riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
+            if (func(ctx, opcode32)) {
                 return;
             }
         }
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
     ctx->zero = tcg_constant_tl(0);
     ctx->virt_inst_excp = false;
+    ctx->decoders = cpu->decoders;
 }
 
 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
-- 
2.45.1

From: Christoph Müllner <christoph.muellner@vrull.eu>

The th.sxstatus CSR can be used to identify available custom extension
on T-Head CPUs. The CSR is documented here:
  https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc

An important property of this patch is, that the th.sxstatus MAEE field
is not set (indicating that XTheadMae is not available).
XTheadMae is a memory attribute extension (similar to Svpbmt) which is
implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits
in PTEs that are marked as reserved. QEMU maintainers prefer to not
implement XTheadMae, so we need give kernels a mechanism to identify
if XTheadMae is available in a system or not. And this patch introduces
this mechanism in QEMU in a way that's compatible with real HW
(i.e., probing the th.sxstatus.MAEE bit).

Further context can be found on the list:
https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html

Reviewed-by: LIU Zhiwei <zhiwe_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-ID: <20240429073656.2486732-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 MAINTAINERS              |  1 +
 target/riscv/cpu.h       |  3 ++
 target/riscv/cpu.c       |  1 +
 target/riscv/th_csr.c    | 79 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  1 +
 5 files changed, 85 insertions(+)
 create mode 100644 target/riscv/th_csr.c

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ target_ulong riscv_new_csr_seed(target_ulong new_value,
 uint8_t satp_mode_max_from_map(uint32_t map);
 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit);
 
+/* Implemented in th_csr.c */
+void th_register_custom_csrs(RISCVCPU *cpu);
+
 #endif /* RISCV_CPU_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static void rv64_thead_c906_cpu_init(Object *obj)
     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
 #ifndef CONFIG_USER_ONLY
     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+    th_register_custom_csrs(cpu);
 #endif
 
     /* inherited from parent obj via riscv_cpu_init() */
diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/riscv/th_csr.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * T-Head-specific CSRs.
+ *
+ * Copyright (c) 2024 VRULL GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "cpu_vendorid.h"
+
+#define CSR_TH_SXSTATUS 0x5c0
+
+/* TH_SXSTATUS bits */
+#define TH_SXSTATUS_UCME        BIT(16)
+#define TH_SXSTATUS_MAEE        BIT(21)
+#define TH_SXSTATUS_THEADISAEE  BIT(22)
+
+typedef struct {
+    int csrno;
+    int (*insertion_test)(RISCVCPU *cpu);
+    riscv_csr_operations csr_ops;
+} riscv_csr;
+
+static RISCVException smode(CPURISCVState *env, int csrno)
+{
+    if (riscv_has_ext(env, RVS)) {
+        return RISCV_EXCP_NONE;
+    }
+
+    return RISCV_EXCP_ILLEGAL_INST;
+}
+
+static int test_thead_mvendorid(RISCVCPU *cpu)
+{
+    if (cpu->cfg.mvendorid != THEAD_VENDOR_ID) {
+        return -1;
+    }
+
+    return 0;
+}
+
+static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno,
+                                       target_ulong *val)
+{
+    /* We don't set MAEE here, because QEMU does not implement MAEE. */
+    *val = TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE;
+    return RISCV_EXCP_NONE;
+}
+
+static riscv_csr th_csr_list[] = {
+    {
+        .csrno = CSR_TH_SXSTATUS,
+        .insertion_test = test_thead_mvendorid,
+        .csr_ops = { "th.sxstatus", smode, read_th_sxstatus }
+    }
+};
+
+void th_register_custom_csrs(RISCVCPU *cpu)
+{
+    for (size_t i = 0; i < ARRAY_SIZE(th_csr_list); i++) {
+        int csrno = th_csr_list[i].csrno;
+        riscv_csr_operations *csr_ops = &th_csr_list[i].csr_ops;
+        if (!th_csr_list[i].insertion_test(cpu)) {
+            riscv_set_csr_ops(csrno, csr_ops);
+        }
+    }
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -XXX,XX +XXX,XX @@ riscv_system_ss.add(files(
   'monitor.c',
   'machine.c',
   'pmu.c',
+  'th_csr.c',
   'time_helper.c',
   'riscv-qmp-cmds.c',
 ))
-- 
2.45.1

From: Max Chou <max.chou@sifive.com>

According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of

* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-2-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

From: Max Chou <max.chou@sifive.com>

The require_scale_rvf function only checks the double width operator for
the vector floating point widen instructions, so most of the widen
checking functions need to add require_rvf for single width operator.

The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width
integer to double width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
 1 file changed, 5 insertions(+)

From: Max Chou <max.chou@sifive.com>

If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240322092600.1198921-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -XXX,XX +XXX,XX @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
     return require_rvv(s) &&
            require_rvf(s) &&
            require_scale_rvf(s) &&
-           (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm);
 }
@@ -XXX,XX +XXX,XX @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM)             \
@@ -XXX,XX +XXX,XX @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvfmin(s) &&
-           require_scale_rvfmin(s) &&
-           (s->sew != MO_8);
+           require_scale_rvfmin(s);
 }
 
 static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM)            \
@@ -XXX,XX +XXX,XX @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a)
 {
     return reduction_widen_check(s, a) &&
            require_rvf(s) &&
-           require_scale_rvf(s) &&
-           (s->sew != MO_8);
+           require_scale_rvf(s);
 }
 
 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

raise_mmu_exception(), as is today, is prioritizing guest page faults by
checking first if virt_enabled && !first_stage, and then considering the
regular inst/load/store faults.

There's no mention in the spec about guest page fault being a higher
priority that PMP faults. In fact, privileged spec section 3.7.1 says:

"Attempting to fetch an instruction from a PMP region that does not have
execute permissions raises an instruction access-fault exception.
Attempting to execute a load or load-reserved instruction which accesses
a physical address within a PMP region without read permissions raises a
load access-fault exception. Attempting to execute a store,
store-conditional, or AMO instruction which accesses a physical address
within a PMP region without write permissions raises a store
access-fault exception."

So, in fact, we're doing it wrong - PMP faults should always be thrown,
regardless of also being a first or second stage fault.

The way riscv_cpu_tlb_fill() and get_physical_address() work is
adequate: a TRANSLATE_PMP_FAIL error is immediately reported and
reflected in the 'pmp_violation' flag. What we need is to change
raise_mmu_exception() to prioritize it.

Reported-by: Joseph Chan <jchan@ventanamicro.com>
Fixes: 82d53adfbb ("target/riscv/cpu_helper.c: Invalid exception on MMU translation stage")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240413105929.7030-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
 
     switch (access_type) {
     case MMU_INST_FETCH:
-        if (env->virt_enabled && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT;
+        } else if (env->virt_enabled && !first_stage) {
             cs->exception_index = RISCV_EXCP_INST_GUEST_PAGE_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_INST_ACCESS_FAULT : RISCV_EXCP_INST_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT;
         }
         break;
     case MMU_DATA_LOAD:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_LOAD_ACCESS_FAULT : RISCV_EXCP_LOAD_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT;
         }
         break;
     case MMU_DATA_STORE:
-        if (two_stage && !first_stage) {
+        if (pmp_violation) {
+            cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+        } else if (two_stage && !first_stage) {
             cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
         } else {
-            cs->exception_index = pmp_violation ?
-                RISCV_EXCP_STORE_AMO_ACCESS_FAULT :
-                RISCV_EXCP_STORE_PAGE_FAULT;
+            cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT;
         }
         break;
     default:
-- 
2.45.1

From: Alexei Filippov <alexei.filippov@syntacore.com>

Previous patch fixed the PMP priority in raise_mmu_exception() but we're still
setting mtval2 incorrectly. In riscv_cpu_tlb_fill(), after pmp check in 2 stage
translation part, mtval2 will be set in case of successes 2 stage translation but
failed pmp check.

In this case we gonna set mtval2 via env->guest_phys_fault_addr in context of
riscv_cpu_tlb_fill(), as this was a guest-page-fault, but it didn't and mtval2
should be zero, according to RISCV privileged spec sect. 9.4.4: When a guest
page-fault is taken into M-mode, mtval2 is written with either zero or guest
physical address that faulted, shifted by 2 bits. *For other traps, mtval2
is set to zero...*

Signed-off-by: Alexei Filippov <alexei.filippov@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240503103052.6819-1-alexei.filippov@syntacore.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -XXX,XX +XXX,XX @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                               __func__, pa, ret, prot_pmp, tlb_size);
 
                 prot &= prot_pmp;
-            }
-
-            if (ret != TRANSLATE_SUCCESS) {
+            } else {
                 /*
                  * Guest physical address translation failed, this is a HS
                  * level exception
                  */
                 first_stage_error = false;
-                env->guest_phys_fault_addr = (im_address |
-                                              (address &
-                                               (TARGET_PAGE_SIZE - 1))) >> 2;
+                if (ret != TRANSLATE_PMP_FAIL) {
+                    env->guest_phys_fault_addr = (im_address |
+                                                  (address &
+                                                   (TARGET_PAGE_SIZE - 1))) >> 2;
+                }
             }
         }
     } else {
-- 
2.45.1

From: Rob Bradford <rbradford@rivosinc.com>

This extension has now been ratified:
https://jira.riscv.org/browse/RVS-2006 so the "x-" prefix can be
removed.

Since this is now a ratified extension add it to the list of extensions
included in the "max" CPU variant.

Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20240514110217.22516-1-rbradford@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c         | 2 +-
 target/riscv/tcg/tcg-cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -XXX,XX +XXX,XX @@ static const MISAExtInfo misa_ext_info_arr[] = {
     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
     MISA_EXT_INFO(RVV, "v", "Vector operations"),
     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
-    MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)")
+    MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
 };
 
 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -XXX,XX +XXX,XX @@ static void riscv_init_max_cpu_extensions(Object *obj)
     const RISCVCPUMultiExtConfig *prop;
 
     /* Enable RVG, RVJ and RVV that are disabled by default */
-    riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
+    riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVJ | RVV);
 
     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
         isa_ext_update_enabled(cpu, prop->offset, true);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

When running the instruction

```
    cbo.flush 0(x0)
```

QEMU would segfault.

The issue was in cpu_gpr[a->rs1] as QEMU does not have cpu_gpr[0]
allocated.

In order to fix this let's use the existing get_address()
helper. This also has the benefit of performing pointer mask
calculations on the address specified in rs1.

The pointer masking specificiation specifically states:

"""
Cache Management Operations: All instructions in Zicbom, Zicbop and Zicboz
"""

So this is the correct behaviour and we previously have been incorrectly
not masking the address.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reported-by: Fabian Thomas <fabian.thomas@cispa.de>
Fixes: e05da09b7cfd ("target/riscv: implement Zicbom extension")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514023910.301766-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvzicbo.c.inc | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/insn_trans/trans_rvzicbo.c.inc
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/insn_trans/trans_rvzicbo.c.inc
+++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc
@@ -XXX,XX +XXX,XX @@
 static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_clean_flush(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
 {
     REQUIRE_ZICBOM(ctx);
-    gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_inval(tcg_env, src);
     return true;
 }
 
 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
 {
     REQUIRE_ZICBOZ(ctx);
-    gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]);
+    TCGv src = get_address(ctx, a->rs1, 0);
+
+    gen_helper_cbo_zero(tcg_env, src);
     return true;
 }
-- 
2.45.1

From: Yong-Xuan Wang <yongxuan.wang@sifive.com>

In AIA spec, each hart (or each hart within a group) has a unique hart
number to locate the memory pages of interrupt files in the address
space. The number of bits required to represent any hart number is equal
to ceil(log2(hmax + 1)), where hmax is the largest hart number among
groups.

However, if the largest hart number among groups is a power of 2, QEMU
will pass an inaccurate hart-index-bit setting to Linux. For example, when
the guest OS has 4 harts, only ceil(log2(3 + 1)) = 2 bits are sufficient
to represent 4 harts, but we passes 3 to Linux. The code needs to be
updated to ensure accurate hart-index-bit settings.

Additionally, a Linux patch[1] is necessary to correctly recover the hart
index when the guest OS has only 1 hart, where the hart-index-bit is 0.

[1] https://lore.kernel.org/lkml/20240415064905.25184-1-yongxuan.wang@sifive.com/t/

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240515091129.28116-1-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/kvm/kvm-cpu.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -XXX,XX +XXX,XX @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
         }
     }
 
-    hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+
+    if (max_hart_per_socket > 1) {
+        max_hart_per_socket--;
+        hart_bits = find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1;
+    } else {
+        hart_bits = 0;
+    }
+
     ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
                             KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
                             &hart_bits, true, NULL);
-- 
2.45.1

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Commit 33a24910ae changed 'reg_width' to use 'vlenb', i.e. vector length
in bytes, when in this context we want 'reg_width' as the length in
bits.

Fix 'reg_width' back to the value in bits like 7cb59921c05a
("target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'") set
beforehand.

While we're at it, rename 'reg_width' to 'bitsize' to provide a bit more
clarity about what the variable represents. 'bitsize' is also used in
riscv_gen_dynamic_csr_feature() with the same purpose, i.e. as an input to
gdb_feature_builder_append_reg().

Cc: Akihiko Odaki <akihiko.odaki@daynix.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Reported-by: Robin Dapp <rdapp.gcc@gmail.com>
Fixes: 33a24910ae ("target/riscv: Use GDBFeature for dynamic XML")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240517203054.880861-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/gdbstub.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -XXX,XX +XXX,XX @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
 static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
-    int reg_width = cpu->cfg.vlenb;
+    int bitsize = cpu->cfg.vlenb << 3;
     GDBFeatureBuilder builder;
     int i;
 
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
 
     /* First define types and totals in a whole VL */
     for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
-        int count = reg_width / vec_lanes[i].size;
+        int count = bitsize / vec_lanes[i].size;
         gdb_feature_builder_append_tag(
             &builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
             vec_lanes[i].id, vec_lanes[i].gdb_type, count);
@@ -XXX,XX +XXX,XX @@ static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
     /* Define vector registers */
     for (i = 0; i < 32; i++) {
         gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
-                                       reg_width, i, "riscv_vector", "vector");
+                                       bitsize, i, "riscv_vector", "vector");
     }
 
     gdb_feature_builder_end(&builder);
-- 
2.45.1

From: Alistair Francis <alistair23@gmail.com>

Previously we only listed a single pmpcfg CSR and the first 16 pmpaddr
CSRs. This patch fixes this to list all 16 pmpcfg and all 64 pmpaddr
CSRs are part of the disassembly.

Reported-by: Eric DeVolder <eric_devolder@yahoo.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Fixes: ea10325917 ("RISC-V Disassembler")
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-stable <qemu-stable@nongnu.org>
Message-ID: <20240514051615.330979-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 disas/riscv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index XXXXXXX..XXXXXXX 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x0383: return "mibound";
     case 0x0384: return "mdbase";
     case 0x0385: return "mdbound";
-    case 0x03a0: return "pmpcfg3";
+    case 0x03a0: return "pmpcfg0";
+    case 0x03a1: return "pmpcfg1";
+    case 0x03a2: return "pmpcfg2";
+    case 0x03a3: return "pmpcfg3";
+    case 0x03a4: return "pmpcfg4";
+    case 0x03a5: return "pmpcfg5";
+    case 0x03a6: return "pmpcfg6";
+    case 0x03a7: return "pmpcfg7";
+    case 0x03a8: return "pmpcfg8";
+    case 0x03a9: return "pmpcfg9";
+    case 0x03aa: return "pmpcfg10";
+    case 0x03ab: return "pmpcfg11";
+    case 0x03ac: return "pmpcfg12";
+    case 0x03ad: return "pmpcfg13";
+    case 0x03ae: return "pmpcfg14";
+    case 0x03af: return "pmpcfg15";
     case 0x03b0: return "pmpaddr0";
     case 0x03b1: return "pmpaddr1";
     case 0x03b2: return "pmpaddr2";
@@ -XXX,XX +XXX,XX @@ static const char *csr_name(int csrno)
     case 0x03bd: return "pmpaddr13";
     case 0x03be: return "pmpaddr14";
     case 0x03bf: return "pmpaddr15";
+    case 0x03c0: return "pmpaddr16";
+    case 0x03c1: return "pmpaddr17";
+    case 0x03c2: return "pmpaddr18";
+    case 0x03c3: return "pmpaddr19";
+    case 0x03c4: return "pmpaddr20";
+    case 0x03c5: return "pmpaddr21";
+    case 0x03c6: return "pmpaddr22";
+    case 0x03c7: return "pmpaddr23";
+    case 0x03c8: return "pmpaddr24";
+    case 0x03c9: return "pmpaddr25";
+    case 0x03ca: return "pmpaddr26";
+    case 0x03cb: return "pmpaddr27";
+    case 0x03cc: return "pmpaddr28";
+    case 0x03cd: return "pmpaddr29";
+    case 0x03ce: return "pmpaddr30";
+    case 0x03cf: return "pmpaddr31";
+    case 0x03d0: return "pmpaddr32";
+    case 0x03d1: return "pmpaddr33";
+    case 0x03d2: return "pmpaddr34";
+    case 0x03d3: return "pmpaddr35";
+    case 0x03d4: return "pmpaddr36";
+    case 0x03d5: return "pmpaddr37";
+    case 0x03d6: return "pmpaddr38";
+    case 0x03d7: return "pmpaddr39";
+    case 0x03d8: return "pmpaddr40";
+    case 0x03d9: return "pmpaddr41";
+    case 0x03da: return "pmpaddr42";
+    case 0x03db: return "pmpaddr43";
+    case 0x03dc: return "pmpaddr44";
+    case 0x03dd: return "pmpaddr45";
+    case 0x03de: return "pmpaddr46";
+    case 0x03df: return "pmpaddr47";
+    case 0x03e0: return "pmpaddr48";
+    case 0x03e1: return "pmpaddr49";
+    case 0x03e2: return "pmpaddr50";
+    case 0x03e3: return "pmpaddr51";
+    case 0x03e4: return "pmpaddr52";
+    case 0x03e5: return "pmpaddr53";
+    case 0x03e6: return "pmpaddr54";
+    case 0x03e7: return "pmpaddr55";
+    case 0x03e8: return "pmpaddr56";
+    case 0x03e9: return "pmpaddr57";
+    case 0x03ea: return "pmpaddr58";
+    case 0x03eb: return "pmpaddr59";
+    case 0x03ec: return "pmpaddr60";
+    case 0x03ed: return "pmpaddr61";
+    case 0x03ee: return "pmpaddr62";
+    case 0x03ef: return "pmpaddr63";
     case 0x0780: return "mtohost";
     case 0x0781: return "mfromhost";
     case 0x0782: return "mreset";
-- 
2.45.1

From: Yu-Ming Chang <yumin686@andestech.com>

Both CSRRS and CSRRC always read the addressed CSR and cause any read side
effects regardless of rs1 and rd fields. Note that if rs1 specifies a register
holding a zero value other than x0, the instruction will still attempt to write
the unmodified value back to the CSR and will cause any attendant side effects.

So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specifies
a register holding a zero value, an illegal instruction exception should be
raised.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240403070823.80897-1-yumin686@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h       |  4 ++++
 target/riscv/csr.c       | 51 ++++++++++++++++++++++++++++++++++++----
 target/riscv/op_helper.c |  6 ++---
 3 files changed, 53 insertions(+), 8 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
 void riscv_cpu_update_mask(CPURISCVState *env);
 bool riscv_cpu_is_32bit(RISCVCPU *cpu);
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                          target_ulong *ret_value);
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask);
@@ -XXX,XX +XXX,XX @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
                                           target_ulong new_value,
                                           target_ulong write_mask);
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value);
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -XXX,XX +XXX,XX @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
 
 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
                                                int csrno,
-                                               bool write_mask)
+                                               bool write)
 {
     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
     bool read_only = get_field(csrno, 0xC00) == 3;
@@ -XXX,XX +XXX,XX @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
     }
 
     /* read / write check */
-    if (write_mask && read_only) {
+    if (write && read_only) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr(CPURISCVState *env, int csrno,
+                           target_ulong *ret_value)
+{
+    RISCVException ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
+}
+
 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
                            target_ulong *ret_value,
                            target_ulong new_value, target_ulong write_mask)
 {
-    RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
+    RISCVException ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
@@ -XXX,XX +XXX,XX @@ static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
+                               Int128 *ret_value)
+{
+    RISCVException ret;
+
+    ret = riscv_csrrw_check(env, csrno, false);
+    if (ret != RISCV_EXCP_NONE) {
+        return ret;
+    }
+
+    if (csr_ops[csrno].read128) {
+        return riscv_csrrw_do128(env, csrno, ret_value,
+                                 int128_zero(), int128_zero());
+    }
+
+    /*
+     * Fall back to 64-bit version for now, if the 128-bit alternative isn't
+     * at all defined.
+     * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
+     * significant), for those, this fallback is correctly handling the
+     * accesses
+     */
+    target_ulong old_value;
+    ret = riscv_csrrw_do64(env, csrno, &old_value,
+                           (target_ulong)0,
+                           (target_ulong)0);
+    if (ret == RISCV_EXCP_NONE && ret_value) {
+        *ret_value = int128_make64(old_value);
+    }
+    return ret;
+}
+
 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
                                 Int128 *ret_value,
                                 Int128 new_value, Int128 write_mask)
 {
     RISCVException ret;
 
-    ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
+    ret = riscv_csrrw_check(env, csrno, true);
     if (ret != RISCV_EXCP_NONE) {
         return ret;
     }
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
     }
 
     target_ulong val = 0;
-    RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0);
+    RISCVException ret = riscv_csrr(env, csr, &val);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
@@ -XXX,XX +XXX,XX @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
 target_ulong helper_csrr_i128(CPURISCVState *env, int csr)
 {
     Int128 rv = int128_zero();
-    RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
-                                          int128_zero(),
-                                          int128_zero());
+    RISCVException ret = riscv_csrr_i128(env, csr, &rv);
 
     if (ret != RISCV_EXCP_NONE) {
         riscv_raise_exception(env, ret, GETPC());
-- 
2.45.1