[v1] riscv-to-apply queue

[PULL 0/5] riscv-to-apply queue

Alistair Francis posted 5 patches 5 years, 5 months ago

Diff against v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v1 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v2 v3 v3 v3 v3
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git fetch https://github.com/patchew-project/qemu tags/patchew/20200722164838.1591305-1-alistair.francis@wdc.com

Maintainers: Sagar Karandikar <sagark@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup.patel@wdc.com>

There is a newer version of this series

include/hw/rtc/goldfish_rtc.h           |  1 +
hw/riscv/sifive_e.c                     |  2 +-
hw/rtc/goldfish_rtc.c                   | 17 ++++++++++++++---
target/riscv/csr.c                      |  2 +-
target/riscv/insn_trans/trans_rvv.inc.c | 11 ++++++++++-
5 files changed, 27 insertions(+), 6 deletions(-)

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[PULL 0/5] riscv-to-apply queue

Posted by Alistair Francis 5 years, 5 months ago

The following changes since commit 3cbc8970f55c87cb58699b6dc8fe42998bc79dc0:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2020-07-21' into staging (2020-07-22 09:13:46 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200722-1

for you to fetch changes up to 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d:

  target/riscv: Fix the range of pmpcfg of CSR funcion table (2020-07-22 09:41:36 -0700)

----------------------------------------------------------------
This PR contains a few RISC-V fixes.

The main fix is the correction of the goldfish RTC time. On top of that
some small fixes to the recently added vector extensions have been added
(including an assert that fixed a coverity report). There is a change in
the SiFive E debug memory size to match hardware. Finally there is a fix
for PMP accesses.

----------------------------------------------------------------
Bin Meng (1):
      hw/riscv: sifive_e: Correct debug block size

Jessica Clarke (1):
      goldfish_rtc: Fix non-atomic read behaviour of TIME_LOW/TIME_HIGH

LIU Zhiwei (2):
      target/riscv: Quiet Coverity complains about vamo*
      target/riscv: fix vector index load/store constraints

Zong Li (1):
      target/riscv: Fix the range of pmpcfg of CSR funcion table

 include/hw/rtc/goldfish_rtc.h           |  1 +
 hw/riscv/sifive_e.c                     |  2 +-
 hw/rtc/goldfish_rtc.c                   | 17 ++++++++++++++---
 target/riscv/csr.c                      |  2 +-
 target/riscv/insn_trans/trans_rvv.inc.c | 11 ++++++++++-
 5 files changed, 27 insertions(+), 6 deletions(-)

Re: [PULL 0/5] riscv-to-apply queue

Posted by Peter Maydell 5 years, 4 months ago

On Wed, 22 Jul 2020 at 18:00, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 3cbc8970f55c87cb58699b6dc8fe42998bc79dc0:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2020-07-21' into staging (2020-07-22 09:13:46 +0100)
>
> are available in the Git repository at:
>
>   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200722-1
>
> for you to fetch changes up to 8ba26b0b2b00dd5849a6c0981e358dc7a7cc315d:
>
>   target/riscv: Fix the range of pmpcfg of CSR funcion table (2020-07-22 09:41:36 -0700)
>
> ----------------------------------------------------------------
> This PR contains a few RISC-V fixes.
>
> The main fix is the correction of the goldfish RTC time. On top of that
> some small fixes to the recently added vector extensions have been added
> (including an assert that fixed a coverity report). There is a change in
> the SiFive E debug memory size to match hardware. Finally there is a fix
> for PMP accesses.


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.

-- PMM