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charset="utf-8" From: Jessica Clarke The specification says: 0x00 TIME_LOW R: Get current time, then return low-order 32-bits. 0x04 TIME_HIGH R: Return high 32-bits from previous TIME_LOW read. ... To read the value, the kernel must perform an IO_READ(TIME_LOW), which returns an unsigned 32-bit value, before an IO_READ(TIME_HIGH), which returns a signed 32-bit value, corresponding to the higher half of the full value. However, we were just returning the current time for both. If the guest is unlucky enough to read TIME_LOW and TIME_HIGH either side of an overflow of the lower half, it will see time be in the future, before jumping backwards on the next read, and Linux currently relies on the atomicity guaranteed by the spec so is affected by this. Fix this violation of the spec by caching the correct value for TIME_HIGH whenever TIME_LOW is read, and returning that value for any TIME_HIGH read. Signed-off-by: Jessica Clarke Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20200718004934.83174-1-jrtc27@jrtc27.com> Signed-off-by: Alistair Francis --- include/hw/rtc/goldfish_rtc.h | 1 + hw/rtc/goldfish_rtc.c | 17 ++++++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h index 16f9f9e29d..9bd8924f5f 100644 --- a/include/hw/rtc/goldfish_rtc.h +++ b/include/hw/rtc/goldfish_rtc.h @@ -41,6 +41,7 @@ typedef struct GoldfishRTCState { uint32_t alarm_running; uint32_t irq_pending; uint32_t irq_enabled; + uint32_t time_high; } GoldfishRTCState; =20 #endif diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c index 01e9d2b083..6ddd45cce0 100644 --- a/hw/rtc/goldfish_rtc.c +++ b/hw/rtc/goldfish_rtc.c @@ -94,12 +94,22 @@ static uint64_t goldfish_rtc_read(void *opaque, hwaddr = offset, GoldfishRTCState *s =3D opaque; uint64_t r =3D 0; =20 + /* + * From the documentation linked at the top of the file: + * + * To read the value, the kernel must perform an IO_READ(TIME_LOW), = which + * returns an unsigned 32-bit value, before an IO_READ(TIME_HIGH), w= hich + * returns a signed 32-bit value, corresponding to the higher half o= f the + * full value. + */ switch (offset) { case RTC_TIME_LOW: - r =3D goldfish_rtc_get_count(s) & 0xffffffff; + r =3D goldfish_rtc_get_count(s); + s->time_high =3D r >> 32; + r &=3D 0xffffffff; break; case RTC_TIME_HIGH: - r =3D goldfish_rtc_get_count(s) >> 32; + r =3D s->time_high; break; case RTC_ALARM_LOW: r =3D s->alarm_next & 0xffffffff; @@ -216,7 +226,7 @@ static const MemoryRegionOps goldfish_rtc_ops =3D { =20 static const VMStateDescription goldfish_rtc_vmstate =3D { .name =3D TYPE_GOLDFISH_RTC, - .version_id =3D 1, + .version_id =3D 2, .pre_save =3D goldfish_rtc_pre_save, .post_load =3D goldfish_rtc_post_load, .fields =3D (VMStateField[]) { @@ -225,6 +235,7 @@ static const VMStateDescription goldfish_rtc_vmstate = =3D { VMSTATE_UINT32(alarm_running, GoldfishRTCState), VMSTATE_UINT32(irq_pending, GoldfishRTCState), VMSTATE_UINT32(irq_enabled, GoldfishRTCState), + VMSTATE_UINT32(time_high, GoldfishRTCState), VMSTATE_END_OF_LIST() } }; --=20 2.27.0 From nobody Fri Dec 19 22:05:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; 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charset="utf-8" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20200721133742.2298-1-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.inc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index c0b7375927..7b4752b911 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -733,6 +733,7 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8= _t seq) g_assert_not_reached(); #endif } else { + assert(seq < ARRAY_SIZE(fnsw)); fn =3D fnsw[seq]; } } --=20 2.27.0 From nobody Fri Dec 19 22:05:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; 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d="scan'208";a="252418636" IronPort-SDR: hTMyhXynS3PWceY5QtaEPQla3z9HDNWfZFMCFb8WQXVxwDAwntC/DhwKTop+FuAlp4Dj/XAPcq x4PCbRP7Gci4+blhW4RsbfXIfY8OwtU78= IronPort-SDR: 4KkGJrx4Q5uTgYlouEphm1GTAmo3xFA9w4OtSEzxFdjHM5yA5crYWvbS9IX8GzpQe/9otaDn4E QCQvV2CkzCCw== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL 3/5] target/riscv: fix vector index load/store constraints Date: Wed, 22 Jul 2020 09:48:36 -0700 Message-Id: <20200722164838.1591305-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200722164838.1591305-1-alistair.francis@wdc.com> References: <20200722164838.1591305-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=465c3c755=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/22 12:58:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.inc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 7b4752b911..887c6b8883 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -513,13 +513,21 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a= , uint8_t seq) return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); } =20 +/* + * For vector indexed segment loads, the destination vector register + * groups cannot overlap the source vector register group (specified by + * `vs2`), else an illegal instruction exception is raised. + */ static bool ld_index_check(DisasContext *s, arg_rnfvm* a) { return (vext_check_isa_ill(s) && vext_check_overlap_mask(s, a->rd, a->vm, false) && vext_check_reg(s, a->rd, false) && vext_check_reg(s, a->rs2, false) && - vext_check_nf(s, a->nf)); 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charset="utf-8" From: Bin Meng Currently the debug region size is set to 0x100, but according to FE310-G000 and FE310-G002 manuals: FE310-G000: 0x100 - 0xFFF FE310-G002: 0x0 - 0xFFF Change the size to 0x1000 that applies to both. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- hw/riscv/sifive_e.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 7bb97b463d..c8b060486a 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -54,7 +54,7 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } sifive_e_memmap[] =3D { - [SIFIVE_E_DEBUG] =3D { 0x0, 0x100 }, + [SIFIVE_E_DEBUG] =3D { 0x0, 0x1000 }, [SIFIVE_E_MROM] =3D { 0x1000, 0x2000 }, [SIFIVE_E_OTP] =3D { 0x20000, 0x2000 }, [SIFIVE_E_CLINT] =3D { 0x2000000, 0x10000 }, --=20 2.27.0 From nobody Fri Dec 19 22:05:23 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; 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d="scan'208";a="252418638" IronPort-SDR: Ufn2PwBWqxXIaQpjg+7WN8QUCuUKAup0S5wLuGnYhRabQtH6R3S7n0YOJkGzD1Eja/XKayScsg r+c87DnRiTczg4kmn6jyHM4/yQbVs822c= IronPort-SDR: E3uBad/5vTPgNF75YGMPh4naLr9RsLM5MGVgtHKEue1EV7yNHVM2W6UcGoymQypMT9Tk4m4OkX s2Ql/PnPmLkQ== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org Subject: [PULL 5/5] target/riscv: Fix the range of pmpcfg of CSR funcion table Date: Wed, 22 Jul 2020 09:48:38 -0700 Message-Id: <20200722164838.1591305-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200722164838.1591305-1-alistair.francis@wdc.com> References: <20200722164838.1591305-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=465c3c755=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/22 12:58:21 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis , Zong Li Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Zong Li The range of Physical Memory Protection should be from CSR_PMPCFG0 to CSR_PMPCFG3, not to CSR_PMPADDR9. Signed-off-by: Zong Li Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-Id: Signed-off-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ac01c835e1..6a96a01b1c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1353,7 +1353,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_MTINST] =3D { hmode, read_mtinst, write_mtins= t }, =20 /* Physical Memory Protection */ - [CSR_PMPCFG0 ... CSR_PMPADDR9] =3D { pmp, read_pmpcfg, write_pmpc= fg }, + [CSR_PMPCFG0 ... CSR_PMPCFG3] =3D { pmp, read_pmpcfg, write_pmpc= fg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] =3D { pmp, read_pmpaddr, write_pmpa= ddr }, =20 /* Performance Counters */ --=20 2.27.0