Series comparison

-[PULL 00/12] target-arm queue
+[PULL 00/24] target-arm queue
-Not much here, mostly documentation, but a few bug fixes.
+Hi; here's the latest round of arm patches. I have included also
 my patchset for the RTC devices to avoid keeping time_t and
 time_t diffs in 32-bit variables.
 thanks
 -- PMM
-The following changes since commit 873ec69aeb12e24eec7fb317fd0cd8494e8489dd:
+The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:
-  Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging (2020-07-20 11:03:09 +0100)
+  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200720
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831
-for you to fetch changes up to 6a0b7505f1fd6769c3f1558fda76464d51e4118a:
+for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:
-  docs/system: Document the arm virt board (2020-07-20 11:35:17 +0100)
+  hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * virt: Don't enable MTE emulation by default
+ * Some of the preliminary patches for Cortex-A710 support
- * virt: Diagnose attempts to use MTE with memory-hotplug or KVM
+ * i.MX7 and i.MX6UL refactoring
-   (rather than silently not working correctly)
+ * Implement SRC device for i.MX7
- * util: Implement qemu_get_thread_id() for OpenBSD
+ * Catch illegal-exception-return from EL3 with bad NSE/NS
- * qdev: Add doc comments for qdev_unrealize and GPIO functions,
+ * Use 64-bit offsets for holding time_t differences in RTC devices
-   and standardize on doc-comments-in-header-file
+ * Model correct number of MPU regions for an505, an521, an524 boards
  * hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
  * docs/system: Document canon-a1100, collie, gumstix, virt boards
 ----------------------------------------------------------------
-David CARLIER (1):
+Alex Bennée (1):
-      util: Implement qemu_get_thread_id() for OpenBSD
+      target/arm: properly document FEAT_CRC32
 Jean-Christophe Dubois (6):
       Remove i.MX7 IOMUX GPR device from i.MX6UL
       Refactor i.MX6UL processor code
       Add i.MX6UL missing devices.
       Refactor i.MX7 processor code
       Add i.MX7 missing TZ devices and memory regions
       Add i.MX7 SRC device implementation
 Peter Maydell (8):
-      qdev: Move doc comments from qdev.c to qdev-core.h
+      target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
-      qdev: Document qdev_unrealize()
+      hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
-      qdev: Document GPIO related functions
+      hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
-      hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
+      hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
-      docs/system: Briefly document canon-a1100 board
+      rtc: Use time_t for passing and returning time offsets
-      docs/system: Briefly document collie board
+      target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
-      docs/system: Briefly document gumstix boards
+      hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
-      docs/system: Document the arm virt board
+      hw/arm: Set number of MPU regions correctly for an505, an521, an524
-Richard Henderson (3):
+Richard Henderson (9):
-      hw/arm/virt: Enable MTE via a machine property
+      target/arm: Reduce dcz_blocksize to uint8_t
-      hw/arm/virt: Error for MTE enabled with KVM
+      target/arm: Allow cpu to configure GM blocksize
-      hw/arm/virt: Disable memory hotplug when MTE is enabled
+      target/arm: Support more GM blocksizes
       target/arm: When tag memory is not present, set MTE=1
       target/arm: Introduce make_ccsidr64
       target/arm: Apply access checks to neoverse-n1 special registers
       target/arm: Apply access checks to neoverse-v1 special registers
       target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
       target/arm: Implement FEAT_HPDS2 as a no-op
- docs/system/arm/collie.rst   |  16 +++
+ docs/system/arm/emulation.rst  |   2 +
- docs/system/arm/digic.rst    |  11 ++
+ include/hw/arm/armsse.h        |   5 +
- docs/system/arm/gumstix.rst  |  21 ++++
+ include/hw/arm/armv7m.h        |   8 +
- docs/system/arm/virt.rst     | 161 ++++++++++++++++++++++++++
+ include/hw/arm/fsl-imx6ul.h    | 158 ++++++++++++++++---
- docs/system/target-arm.rst   |   4 +
+ include/hw/arm/fsl-imx7.h      | 338 ++++++++++++++++++++++++++++++-----------
- include/hw/arm/virt.h        |   1 +
+ include/hw/misc/imx7_src.h     |  66 ++++++++
- include/hw/qdev-core.h       | 267 ++++++++++++++++++++++++++++++++++++++++++-
+ include/hw/rtc/aspeed_rtc.h    |   2 +-
- include/hw/qdev-properties.h |  13 +++
+ include/sysemu/rtc.h           |   4 +-
- hw/arm/armsse.c              |   2 +
+ target/arm/cpregs.h            |   2 +
- hw/arm/virt.c                |  50 +++++++-
+ target/arm/cpu.h               |   5 +-
- hw/core/qdev.c               |  33 ------
+ target/arm/internals.h         |   6 -
- target/arm/cpu.c             |  19 +--
+ target/arm/tcg/translate.h     |   2 +
- target/arm/cpu64.c           |   5 +-
+ hw/arm/armsse.c                |  16 ++
- util/oslib-posix.c           |   2 +
+ hw/arm/armv7m.c                |  21 +++
- MAINTAINERS                  |   4 +
+ hw/arm/fsl-imx6ul.c            | 174 +++++++++++++--------
-files changed, 559 insertions(+), 50 deletions(-)
+ hw/arm/fsl-imx7.c              | 201 +++++++++++++++++++-----
- create mode 100644 docs/system/arm/collie.rst
+ hw/arm/mps2-tz.c               |  29 ++++
- create mode 100644 docs/system/arm/digic.rst
+ hw/misc/imx7_src.c             | 276 +++++++++++++++++++++++++++++++++
- create mode 100644 docs/system/arm/gumstix.rst
+ hw/rtc/aspeed_rtc.c            |   5 +-
- create mode 100644 docs/system/arm/virt.rst
+ hw/rtc/m48t59.c                |   2 +-
  hw/rtc/twl92230.c              |   4 +-
  softmmu/rtc.c                  |   4 +-
  target/arm/cpu.c               | 207 ++++++++++++++-----------
  target/arm/helper.c            |  15 +-
  target/arm/tcg/cpu32.c         |   2 +-
  target/arm/tcg/cpu64.c         | 102 +++++++++----
  target/arm/tcg/helper-a64.c    |   9 ++
  target/arm/tcg/mte_helper.c    |  90 ++++++++---
  target/arm/tcg/translate-a64.c |   5 +-
  hw/misc/meson.build            |   1 +
  hw/misc/trace-events           |   4 +
 files changed, 1393 insertions(+), 372 deletions(-)
  create mode 100644 include/hw/misc/imx7_src.h
  create mode 100644 hw/misc/imx7_src.c

-[PULL 02/12] hw/arm/virt: Error for MTE enabled with KVM
+[PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t
 From: Richard Henderson <richard.henderson@linaro.org>
-While we expect KVM to support MTE at some future point,
+This value is only 4 bits wide.
 it certainly won't be ready in time for qemu 5.1.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200713213341.590275-3-richard.henderson@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 6 ++++++
+ target/arm/cpu.h | 3 ++-
-file changed, 6 insertions(+)
+file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/target/arm/cpu.h
-+++ b/hw/arm/virt.c
++++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-         exit(1);
+     bool prop_lpa2;
-     }
+     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
-+    if (vms->mte && kvm_enabled()) {
+-    uint32_t dcz_blocksize;
-+        error_report("mach-virt: KVM does not support providing "
++    uint8_t dcz_blocksize;
 +                     "MTE to the guest CPU");
 +        exit(1);
 +    }
 +
-     create_fdt(vms);
+     uint64_t rvbar_prop; /* Property/input signals.  */
-     possible_cpus = mc->possible_cpu_arch_ids(machine);
+     /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
 --
-.20.1
+.34.1

-[PULL 05/12] qdev: Move doc comments from qdev.c to qdev-core.h
+[PULL 02/24] target/arm: Allow cpu to configure GM blocksize
-The doc-comments which document the qdev API are split between the
+From: Richard Henderson <richard.henderson@linaro.org>
-header file and the C source files, because as a project we haven't
-been consistent about where we put them.
+Previously we hard-coded the blocksize with GMID_EL1_BS.
+But the value we choose for -cpu max does not match the
-Move all the doc-comments in qdev.c to the header files, so that
+value that cortex-a710 uses.
-users of the APIs don't have to look at the implementation files for
-this information.
+Mirror the way we handle dcz_blocksize.
-In the process, unify them into our doc-comment format and expand on
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-them in some cases to clarify expected use cases.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200711142425.16283-2-peter.maydell@linaro.org
 ---
- include/hw/qdev-core.h       | 57 ++++++++++++++++++++++++++++++++++++
+ target/arm/cpu.h               |  2 ++
- include/hw/qdev-properties.h | 13 ++++++++
+ target/arm/internals.h         |  6 -----
- hw/core/qdev.c               | 33 ---------------------
+ target/arm/tcg/translate.h     |  2 ++
-files changed, 70 insertions(+), 33 deletions(-)
+ target/arm/helper.c            | 11 +++++---
+ target/arm/tcg/cpu64.c         |  1 +
-diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
+ target/arm/tcg/mte_helper.c    | 46 ++++++++++++++++++++++------------
-index XXXXXXX..XXXXXXX 100644
+ target/arm/tcg/translate-a64.c |  5 ++--
---- a/include/hw/qdev-core.h
+files changed, 45 insertions(+), 28 deletions(-)
-+++ b/include/hw/qdev-core.h
-@@ -XXX,XX +XXX,XX @@ compat_props_add(GPtrArray *arr,
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
- /*** Board API.  This should go away once we have a machine config file.  ***/
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
-+/**
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-+ * qdev_new: Create a device on the heap
-+ * @name: device type to create (we assert() that this type exists)
+     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
-+ *
+     uint8_t dcz_blocksize;
-+ * This only allocates the memory and initializes the device state
++    /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
-+ * structure, ready for the caller to set properties if they wish.
++    uint8_t gm_blocksize;
-+ * The device still needs to be realized.
-+ * The returned object has a reference count of 1.
+     uint64_t rvbar_prop; /* Property/input signals.  */
-+ */
- DeviceState *qdev_new(const char *name);
+diff --git a/target/arm/internals.h b/target/arm/internals.h
-+/**
+index XXXXXXX..XXXXXXX 100644
-+ * qdev_try_new: Try to create a device on the heap
+--- a/target/arm/internals.h
-+ * @name: device type to create
++++ b/target/arm/internals.h
-+ *
+@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
-+ * This is like qdev_new(), except it returns %NULL when type @name
-+ * does not exist, rather than asserting.
+ #endif /* !CONFIG_USER_ONLY */
-+ */
- DeviceState *qdev_try_new(const char *name);
+-/*
-+/**
+- * The log2 of the words in the tag block, for GMID_EL1.BS.
-+ * qdev_realize: Realize @dev.
+- * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
-+ * @dev: device to realize
+- */
-+ * @bus: bus to plug it into (may be NULL)
+-#define GMID_EL1_BS  6
-+ * @errp: pointer to error object
+-
-+ *
+ /*
-+ * "Realize" the device, i.e. perform the second phase of device
+  * SVE predicates are 1/8 the size of SVE vectors, and cannot use
-+ * initialization.
+  * the same simd_desc() encoding due to restrictions on size.
-+ * @dev must not be plugged into a bus already.
+diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
-+ * If @bus, plug @dev into @bus.  This takes a reference to @dev.
+index XXXXXXX..XXXXXXX 100644
-+ * If @dev has no QOM parent, make one up, taking another reference.
+--- a/target/arm/tcg/translate.h
-+ * On success, return true.
++++ b/target/arm/tcg/translate.h
-+ * On failure, store an error through @errp and return false.
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
-+ *
+     int8_t btype;
-+ * If you created @dev using qdev_new(), you probably want to use
+     /* A copy of cpu->dcz_blocksize. */
-+ * qdev_realize_and_unref() instead.
+     uint8_t dcz_blocksize;
-+ */
++    /* A copy of cpu->gm_blocksize. */
- bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
++    uint8_t gm_blocksize;
-+/**
+     /* True if this page is guarded.  */
-+ * qdev_realize_and_unref: Realize @dev and drop a reference
+     bool guarded_page;
-+ * @dev: device to realize
+     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
-+ * @bus: bus to plug it into (may be NULL)
+diff --git a/target/arm/helper.c b/target/arm/helper.c
-+ * @errp: pointer to error object
+index XXXXXXX..XXXXXXX 100644
-+ *
+--- a/target/arm/helper.c
-+ * Realize @dev and drop a reference.
++++ b/target/arm/helper.c
-+ * This is like qdev_realize(), except the caller must hold a
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
-+ * (private) reference, which is dropped on return regardless of
+       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
-+ * success or failure.  Intended use::
+       .access = PL1_RW, .accessfn = access_mte,
-+ *
+       .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
-+ *     dev = qdev_new();
+-    { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
-+ *     [...]
+-      .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
-+ *     qdev_realize_and_unref(dev, bus, errp);
+-      .access = PL1_R, .accessfn = access_aa64_tid5,
-+ *
+-      .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
-+ * Now @dev can go away without further ado.
+     { .name = "TCO", .state = ARM_CP_STATE_AA64,
-+ *
+       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
-+ * If you are embedding the device into some other QOM device and
+       .type = ARM_CP_NO_RAW,
-+ * initialized it via some variant on object_initialize_child() then
+@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
-+ * do not use this function, because that family of functions arrange
+      * then define only a RAZ/WI version of PSTATE.TCO.
-+ * for the only reference to the child device to be held by the parent
+      */
-+ * via the child<> property, and so the reference-count-drop done here
+     if (cpu_isar_feature(aa64_mte, cpu)) {
-+ * would be incorrect. For that use case you want qdev_realize().
++        ARMCPRegInfo gmid_reginfo = {
-+ */
++            .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
- bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
++            .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
- void qdev_unrealize(DeviceState *dev);
++            .access = PL1_R, .accessfn = access_aa64_tid5,
- void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
++            .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
-diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
++        };
-index XXXXXXX..XXXXXXX 100644
++        define_one_arm_cp_reg(cpu, &gmid_reginfo);
---- a/include/hw/qdev-properties.h
+         define_arm_cp_regs(cpu, mte_reginfo);
-+++ b/include/hw/qdev-properties.h
+         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
-@@ -XXX,XX +XXX,XX @@ void error_set_from_qdev_prop_error(Error **errp, int ret, DeviceState *dev,
+     } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
-  */
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
- void qdev_property_add_static(DeviceState *dev, Property *prop);
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
-+/**
++++ b/target/arm/tcg/cpu64.c
-+ * qdev_alias_all_properties: Create aliases on source for all target properties
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
-+ * @target: Device which has properties to be aliased
+     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
-+ * @source: Object to add alias properties to
+     cpu->dcz_blocksize = 7; /*  512 bytes */
-+ *
+ #endif
-+ * Add alias properties to the @source object for all qdev properties on
++    cpu->gm_blocksize = 6;  /*  256 bytes */
-+ * the @target DeviceState.
-+ *
+     cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
-+ * This is useful when @target is an internal implementation object
+     cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
-+ * owned by @source, and you want to expose all the properties of that
+diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
-+ * implementation object as properties on the @source object so that users
+index XXXXXXX..XXXXXXX 100644
-+ * of @source can set them.
+--- a/target/arm/tcg/mte_helper.c
-+ */
++++ b/target/arm/tcg/mte_helper.c
- void qdev_alias_all_properties(DeviceState *target, Object *source);
+@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
  /**
 diff --git a/hw/core/qdev.c b/hw/core/qdev.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/qdev.c
 +++ b/hw/core/qdev.c
@@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
      }
  }
--/*
+-#define LDGM_STGM_SIZE  (4 << GMID_EL1_BS)
-- * Create a device on the heap.
+-
-- * A type @name must exist.
+ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 - * This only initializes the device state structure and allows
 - * properties to be set.  The device still needs to be realized.  See
 - * qdev-core.h.
 - */
  DeviceState *qdev_new(const char *name)
  {
-     if (!object_class_by_name(name)) {
+     int mmu_idx = cpu_mmu_index(env, false);
-@@ -XXX,XX +XXX,XX @@ DeviceState *qdev_new(const char *name)
+     uintptr_t ra = GETPC();
-     return DEVICE(object_new(name));
++    int gm_bs = env_archcpu(env)->gm_blocksize;
 +    int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 -    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
 +    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
      /* Trap if accessing an invalid page.  */
      tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
 +                                 gm_bs_bytes, MMU_DATA_LOAD,
 +                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
      /* The tag is squashed to zero if the page does not support tags.  */
      if (!tag_mem) {
          return 0;
      }
 -    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
      /*
 -     * We are loading 64-bits worth of tags.  The ordering of elements
 -     * within the word corresponds to a 64-bit little-endian operation.
 +     * The ordering of elements within the word corresponds to
 +     * a little-endian operation.
       */
 -    return ldq_le_p(tag_mem);
 +    switch (gm_bs) {
 +    case 6:
 +        /* 256 bytes -> 16 tags -> 64 result bits */
 +        return ldq_le_p(tag_mem);
 +    default:
 +        /* cpu configured with unsupported gm blocksize. */
 +        g_assert_not_reached();
 +    }
  }
--/*
+ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
 - * Try to create a device on the heap.
 - * This is like qdev_new(), except it returns %NULL when type @name
 - * does not exist.
 - */
  DeviceState *qdev_try_new(const char *name)
  {
-     if (!module_object_class_by_name(name)) {
+     int mmu_idx = cpu_mmu_index(env, false);
-@@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
+     uintptr_t ra = GETPC();
-     qdev_unrealize(dev);
++    int gm_bs = env_archcpu(env)->gm_blocksize;
 +    int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 -    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
 +    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
      /* Trap if accessing an invalid page.  */
      tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
 -                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
 +                                 gm_bs_bytes, MMU_DATA_LOAD,
 +                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
      /*
       * Tag store only happens if the page support tags,
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
          return;
      }
 -    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
      /*
 -     * We are storing 64-bits worth of tags.  The ordering of elements
 -     * within the word corresponds to a 64-bit little-endian operation.
 +     * The ordering of elements within the word corresponds to
 +     * a little-endian operation.
       */
 -    stq_le_p(tag_mem, val);
 +    switch (gm_bs) {
 +    case 6:
 +        stq_le_p(tag_mem, val);
 +        break;
 +    default:
 +        /* cpu configured with unsupported gm blocksize. */
 +        g_assert_not_reached();
 +    }
  }
--/*
+ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
-- * Realize @dev.
+diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
-- * @dev must not be plugged into a bus.
+index XXXXXXX..XXXXXXX 100644
-- * If @bus, plug @dev into @bus.  This takes a reference to @dev.
+--- a/target/arm/tcg/translate-a64.c
-- * If @dev has no QOM parent, make one up, taking another reference.
++++ b/target/arm/tcg/translate-a64.c
-- * On success, return true.
+@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
-- * On failure, store an error through @errp and return false.
+         gen_helper_stgm(cpu_env, addr, tcg_rt);
-- */
+     } else {
- bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
+         MMUAccessType acc = MMU_DATA_STORE;
- {
+-        int size = 4 << GMID_EL1_BS;
-     assert(!dev->realized && !dev->parent_bus);
++        int size = 4 << s->gm_blocksize;
-@@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
-     return object_property_set_bool(OBJECT(dev), "realized", true, errp);
+         clean_addr = clean_data_tbi(s, addr);
- }
+         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
--/*
+         gen_helper_ldgm(tcg_rt, cpu_env, addr);
-- * Realize @dev and drop a reference.
+     } else {
-- * This is like qdev_realize(), except the caller must hold a
+         MMUAccessType acc = MMU_DATA_LOAD;
-- * (private) reference, which is dropped on return regardless of
+-        int size = 4 << GMID_EL1_BS;
-- * success or failure.  Intended use:
++        int size = 4 << s->gm_blocksize;
-- *     dev = qdev_new();
-- *     [...]
+         clean_addr = clean_data_tbi(s, addr);
-- *     qdev_realize_and_unref(dev, bus, errp);
+         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
-- * Now @dev can go away without further ado.
+@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
-- */
+     dc->cp_regs = arm_cpu->cp_regs;
- bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp)
+     dc->features = env->features;
- {
+     dc->dcz_blocksize = arm_cpu->dcz_blocksize;
-     bool ret;
++    dc->gm_blocksize = arm_cpu->gm_blocksize;
-@@ -XXX,XX +XXX,XX @@ static void qdev_class_add_property(DeviceClass *klass, Property *prop)
-                                           prop->info->description);
+ #ifdef CONFIG_USER_ONLY
- }
+     /* In sve_probe_page, we assume TBI is enabled. */
 -/* @qdev_alias_all_properties - Add alias properties to the source object for
 - * all qdev properties on the target DeviceState.
 - */
  void qdev_alias_all_properties(DeviceState *target, Object *source)
  {
      ObjectClass *class;
 --
-.20.1
+.34.1

-[PULL 03/12] hw/arm/virt: Disable memory hotplug when MTE is enabled
+[PULL 03/24] target/arm: Support more GM blocksizes
 From: Richard Henderson <richard.henderson@linaro.org>
-When MTE is enabled, tag memory must exist for all RAM.
+Support all of the easy GM block sizes.
 Use direct memory operations, since the pointers are aligned.
-It might be possible to simultaneously hot plug tag memory
+While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
-alongside the corresponding normal memory, but for now just
+an atomic store of one nibble.  This is not difficult, but there
-disable hotplug.
+is also no point in supporting it until required.
 Note that cortex-a710 sets GM blocksize to match its cacheline
 size of 64 bytes.  I expect many implementations will also
 match the cacheline, which makes 16 bytes very unlikely.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200713213341.590275-4-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/virt.c | 5 +++++
+ target/arm/cpu.c            | 18 +++++++++---
-file changed, 5 insertions(+)
+ target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
 files changed, 62 insertions(+), 12 deletions(-)
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
+--- a/target/arm/cpu.c
-+++ b/hw/arm/virt.c
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
                                         ID_PFR1, VIRTUALIZATION, 0);
      }
 +    if (cpu_isar_feature(aa64_mte, cpu)) {
 +        /*
 +         * The architectural range of GM blocksize is 2-6, however qemu
 +         * doesn't support blocksize of 2 (see HELPER(ldgm)).
 +         */
 +        if (tcg_enabled()) {
 +            assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
 +        }
 +
  #ifndef CONFIG_USER_ONLY
 -    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
          /*
           * Disable the MTE feature bits if we do not have tag-memory
           * provided by the machine.
           */
 -        cpu->isar.id_aa64pfr1 =
 -            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
 -    }
 +        if (cpu->tag_memory == NULL) {
 +            cpu->isar.id_aa64pfr1 =
 +                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
 +        }
  #endif
 +    }
      if (tcg_enabled()) {
          /*
 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/mte_helper.c
 +++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
      int gm_bs = env_archcpu(env)->gm_blocksize;
      int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 +    uint64_t ret;
 +    int shift;
      ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
      /*
       * The ordering of elements within the word corresponds to
 -     * a little-endian operation.
 +     * a little-endian operation.  Computation of shift comes from
 +     *
 +     *     index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
 +     *     data<index*4+3:index*4> = tag
 +     *
 +     * Because of the alignment of ptr above, BS=6 has shift=0.
 +     * All memory operations are aligned.  Defer support for BS=2,
 +     * requiring insertion or extraction of a nibble, until we
 +     * support a cpu that requires it.
       */
      switch (gm_bs) {
 +    case 3:
 +        /* 32 bytes -> 2 tags -> 8 result bits */
 +        ret = *(uint8_t *)tag_mem;
 +        break;
 +    case 4:
 +        /* 64 bytes -> 4 tags -> 16 result bits */
 +        ret = cpu_to_le16(*(uint16_t *)tag_mem);
 +        break;
 +    case 5:
 +        /* 128 bytes -> 8 tags -> 32 result bits */
 +        ret = cpu_to_le32(*(uint32_t *)tag_mem);
 +        break;
      case 6:
          /* 256 bytes -> 16 tags -> 64 result bits */
 -        return ldq_le_p(tag_mem);
 +        return cpu_to_le64(*(uint64_t *)tag_mem);
      default:
 -        /* cpu configured with unsupported gm blocksize. */
 +        /*
 +         * CPU configured with unsupported/invalid gm blocksize.
 +         * This is detected early in arm_cpu_realizefn.
 +         */
          g_assert_not_reached();
      }
 +    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
 +    return ret << shift;
  }
  void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
      int gm_bs = env_archcpu(env)->gm_blocksize;
      int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 +    int shift;
      ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
          return;
      }
-+    if (vms->mte) {
+-    /*
-+        error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
+-     * The ordering of elements within the word corresponds to
-+        return;
+-     * a little-endian operation.
-+    }
+-     */
-+
++    /* See LDGM for comments on BS and on shift.  */
-     if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
++    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
-         error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
++    val >>= shift;
-         return;
+     switch (gm_bs) {
 +    case 3:
 +        /* 32 bytes -> 2 tags -> 8 result bits */
 +        *(uint8_t *)tag_mem = val;
 +        break;
 +    case 4:
 +        /* 64 bytes -> 4 tags -> 16 result bits */
 +        *(uint16_t *)tag_mem = cpu_to_le16(val);
 +        break;
 +    case 5:
 +        /* 128 bytes -> 8 tags -> 32 result bits */
 +        *(uint32_t *)tag_mem = cpu_to_le32(val);
 +        break;
      case 6:
 -        stq_le_p(tag_mem, val);
 +        /* 256 bytes -> 16 tags -> 64 result bits */
 +        *(uint64_t *)tag_mem = cpu_to_le64(val);
          break;
      default:
          /* cpu configured with unsupported gm blocksize. */
 --
-.20.1
+.34.1

-New patch
+[PULL 04/24] target/arm: When tag memory is not present, set MTE=1
+From: Richard Henderson <richard.henderson@linaro.org>
+When the cpu support MTE, but the system does not, reduce cpu
+support to user instructions at EL0 instead of completely
+disabling MTE.  If we encounter a cpu implementation which does
+something else, we can revisit this setting.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.c | 7 ++++---
+file changed, 4 insertions(+), 3 deletions(-)
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+ #ifndef CONFIG_USER_ONLY
+         /*
+-         * Disable the MTE feature bits if we do not have tag-memory
+-         * provided by the machine.
++         * If we do not have tag-memory provided by the machine,
++         * reduce MTE support to instructions enabled at EL0.
++         * This matches Cortex-A710 BROADCASTMTE input being LOW.
+          */
+         if (cpu->tag_memory == NULL) {
+             cpu->isar.id_aa64pfr1 =
+-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
++                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
+         }
+ #endif
+     }
+--
+.34.1

-New patch
+[PULL 05/24] target/arm: Introduce make_ccsidr64
+From: Richard Henderson <richard.henderson@linaro.org>
+Do not hard-code the constants for Neoverse V1.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
+file changed, 32 insertions(+), 16 deletions(-)
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/module.h"
+ #include "qapi/visitor.h"
+ #include "hw/qdev-properties.h"
++#include "qemu/units.h"
+ #include "internals.h"
+ #include "cpregs.h"
++static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
++                              unsigned cachesize)
++{
++    unsigned lg_linesize = ctz32(linesize);
++    unsigned sets;
++
++    /*
++     * The 64-bit CCSIDR_EL1 format is:
++     *   [55:32] number of sets - 1
++     *   [23:3]  associativity - 1
++     *   [2:0]   log2(linesize) - 4
++     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
++     */
++    assert(assoc != 0);
++    assert(is_power_of_2(linesize));
++    assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
++
++    /* sets * associativity * linesize == cachesize. */
++    sets = cachesize / (assoc * linesize);
++    assert(cachesize % (assoc * linesize) == 0);
++
++    return ((uint64_t)(sets - 1) << 32)
++         | ((assoc - 1) << 3)
++         | (lg_linesize - 4);
++}
++
+ static void aarch64_a35_initfn(Object *obj)
+ {
+     ARMCPU *cpu = ARM_CPU(obj);
+@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
+      * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
+      * but also says it implements CCIDX, which means they should be
+      * 64-bit format. So we here use values which are based on the textual
+-     * information in chapter 2 of the TRM (and on the fact that
+-     * sets * associativity * linesize == cachesize).
+-     *
+-     * The 64-bit CCSIDR_EL1 format is:
+-     *   [55:32] number of sets - 1
+-     *   [23:3]  associativity - 1
+-     *   [2:0]   log2(linesize) - 4
+-     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
+-     *
+-     * L1: 4-way set associative 64-byte line size, total size 64K,
+-     * so sets is 256.
++     * information in chapter 2 of the TRM:
+      *
++     * L1: 4-way set associative 64-byte line size, total size 64K.
+      * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
+-     * We pick 1MB, so this has 2048 sets.
+-     *
+      * L3: No L3 (this matches the CLIDR_EL1 value).
+      */
+-    cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
+-    cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
+-    cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
++    cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
++    cpu->ccsidr[1] = cpu->ccsidr[0];                 /* L1 icache */
++    cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB);  /* L2 cache */
+     /* From 3.2.115 SCTLR_EL3 */
+     cpu->reset_sctlr = 0x30c50838;
+--
+.34.1

-New patch
+[PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers
+From: Richard Henderson <richard.henderson@linaro.org>
+Access to many of the special registers is enabled or disabled
+by ACTLR_EL[23], which we implement as constant 0, which means
+that all writes outside EL3 should trap.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpregs.h    |  2 ++
+ target/arm/helper.c    |  4 ++--
+ target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
+files changed, 41 insertions(+), 11 deletions(-)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+ #endif
++CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
++
+ #endif /* TARGET_ARM_CPREGS_H */
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
+ }
+ /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM.  */
+-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
+-                                      bool isread)
++CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
++                               bool isread)
+ {
+     if (arm_current_el(env) == 1) {
+         uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
+     /* TODO:  Add A64FX specific HPC extension registers */
+ }
++static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
++                                     bool read)
++{
++    if (!read) {
++        int el = arm_current_el(env);
++
++        /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
++        if (el < 2 && arm_is_el2_enabled(env)) {
++            return CP_ACCESS_TRAP_EL2;
++        }
++        /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
++        if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
++            return CP_ACCESS_TRAP_EL3;
++        }
++    }
++    return CP_ACCESS_OK;
++}
++
+ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+     { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      /* Traps and enables are the same as for TCR_EL1. */
++      .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
+     { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
+       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     /*
+      * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
+      * (and in particular its system registers).
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
+     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
++      .accessfn = access_actlr_w },
+     { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
+       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+ };
+ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
+--
+.34.1

-New patch
+[PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers
+From: Richard Henderson <richard.henderson@linaro.org>
+There is only one additional EL1 register modeled, which
+also needs to use access_actlr_w.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/tcg/cpu64.c | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
+ static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
+     { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
+       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+--
+.34.1

-[PULL 01/12] hw/arm/virt: Enable MTE via a machine property
+[PULL 08/24] target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
 From: Richard Henderson <richard.henderson@linaro.org>
-Control this cpu feature via a machine property, much as we do
+Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
-with secure=on, since both require specialized support in the
+external to the cpu, which is out of scope for QEMU.
 machine setup to be functional.
 Default MTE to off, since this feature implies extra overhead.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200713213341.590275-2-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/virt.h |  1 +
+ target/arm/cpu.c | 3 +++
- hw/arm/virt.c         | 39 ++++++++++++++++++++++++++++++++++-----
+file changed, 3 insertions(+)
  target/arm/cpu.c      | 19 +++++++++++--------
  target/arm/cpu64.c    |  5 +++--
 files changed, 49 insertions(+), 15 deletions(-)
-diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/virt.h
-+++ b/include/hw/arm/virt.h
-@@ -XXX,XX +XXX,XX @@ typedef struct {
-     bool its;
-     bool virt;
-     bool ras;
-+    bool mte;
-     OnOffAuto acpi;
-     VirtGICType gic_version;
-     VirtIOMMUType iommu;
-diff --git a/hw/arm/virt.c b/hw/arm/virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/virt.c
-+++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
-                                      OBJECT(secure_sysmem), &error_abort);
-         }
--        /*
--         * The cpu adds the property if and only if MemTag is supported.
--         * If it is, we must allocate the ram to back that up.
--         */
--        if (object_property_find(cpuobj, "tag-memory", NULL)) {
-+        if (vms->mte) {
-+            /* Create the memory region only once, but link to all cpus. */
-             if (!tag_sysmem) {
-+                /*
-+                 * The property exists only if MemTag is supported.
-+                 * If it is, we must allocate the ram to back that up.
-+                 */
-+                if (!object_property_find(cpuobj, "tag-memory", NULL)) {
-+                    error_report("MTE requested, but not supported "
-+                                 "by the guest CPU");
-+                    exit(1);
-+                }
-+
-                 tag_sysmem = g_new(MemoryRegion, 1);
-                 memory_region_init(tag_sysmem, OBJECT(machine),
-                                    "tag-memory", UINT64_MAX / 32);
-@@ -XXX,XX +XXX,XX @@ static void virt_set_ras(Object *obj, bool value, Error **errp)
-     vms->ras = value;
- }
-+static bool virt_get_mte(Object *obj, Error **errp)
-+{
-+    VirtMachineState *vms = VIRT_MACHINE(obj);
-+
-+    return vms->mte;
-+}
-+
-+static void virt_set_mte(Object *obj, bool value, Error **errp)
-+{
-+    VirtMachineState *vms = VIRT_MACHINE(obj);
-+
-+    vms->mte = value;
-+}
-+
- static char *virt_get_gic_version(Object *obj, Error **errp)
- {
-     VirtMachineState *vms = VIRT_MACHINE(obj);
-@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
-                                     "Set on/off to enable/disable reporting host memory errors "
-                                     "to a KVM guest using ACPI and guest external abort exceptions");
-+    /* MTE is disabled by default.  */
-+    vms->mte = false;
-+    object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte);
-+    object_property_set_description(obj, "mte",
-+                                    "Set on/off to enable/disable emulating a "
-+                                    "guest CPU which implements the ARM "
-+                                    "Memory Tagging Extension");
-+
-     vms->irqmap = a15irqmap;
-     virt_flash_create(vms);
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
 @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-         cpu->id_pfr1 &= ~0xf000;
+         /* FEAT_SPE (Statistical Profiling Extension) */
-     }
+         cpu->isar.id_aa64dfr0 =
+             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
-+#ifndef CONFIG_USER_ONLY
++        /* FEAT_TRBE (Trace Buffer Extension) */
-+    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
++        cpu->isar.id_aa64dfr0 =
-+        /*
++            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
-+         * Disable the MTE feature bits if we do not have tag-memory
+         /* FEAT_TRF (Self-hosted Trace Extension) */
-+         * provided by the machine.
+         cpu->isar.id_aa64dfr0 =
-+         */
+             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
 +        cpu->isar.id_aa64pfr1 =
 +            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
 +    }
 +#endif
 +
      /* MPU can be configured out of a PMSA CPU either by setting has-mpu
       * to false or by setting pmsav7-dregion to 0.
       */
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
              cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
                                     cpu->secure_tag_memory);
          }
 -    } else if (cpu_isar_feature(aa64_mte, cpu)) {
 -        /*
 -         * Since there is no tag memory, we can't meaningfully support MTE
 -         * to its fullest.  To avoid problems later, when we would come to
 -         * use the tag memory, downgrade support to insns only.
 -         */
 -        cpu->isar.id_aa64pfr1 =
 -            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
      }
      cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
          t = cpu->isar.id_aa64pfr1;
          t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
          /*
 -         * Begin with full support for MTE; will be downgraded to MTE=1
 -         * during realize if the board provides no tag memory.
 +         * Begin with full support for MTE. This will be downgraded to MTE=0
 +         * during realize if the board provides no tag memory, much like
 +         * we do for EL2 with the virtualization=on property.
           */
          t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
          cpu->isar.id_aa64pfr1 = t;
 --
-.20.1
+.34.1

-New patch
+[PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op
+From: Richard Henderson <richard.henderson@linaro.org>
+This feature allows the operating system to set TCR_ELx.HWU*
+to allow the implementation to use the PBHA bits from the
+block and page descriptors for for IMPLEMENTATION DEFINED
+purposes.  Since QEMU has no need to use these bits, we may
+simply ignore them.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ docs/system/arm/emulation.rst | 1 +
+ target/arm/tcg/cpu32.c        | 2 +-
+ target/arm/tcg/cpu64.c        | 2 +-
+files changed, 3 insertions(+), 2 deletions(-)
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/emulation.rst
++++ b/docs/system/arm/emulation.rst
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+ - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
+ - FEAT_HCX (Support for the HCRX_EL2 register)
+ - FEAT_HPDS (Hierarchical permission disables)
++- FEAT_HPDS2 (Translation table page-based hardware attributes)
+ - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
+ - FEAT_IDST (ID space trap handling)
+ - FEAT_IESB (Implicit error synchronization event)
+diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu32.c
++++ b/target/arm/tcg/cpu32.c
+@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
+     cpu->isar.id_mmfr3 = t;
+     t = cpu->isar.id_mmfr4;
+-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
++    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
+     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
+     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
+     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
+     t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
+     t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
+-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
++    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2);     /* FEAT_HPDS2 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
+     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
+--
+.34.1

-[PULL 12/12] docs/system: Document the arm virt board
+[PULL 10/24] target/arm: properly document FEAT_CRC32
-Document the arm 'virt' board, which has been undocumented
+From: Alex Bennée <alex.bennee@linaro.org>
 for far too long given that it is the main recommended board
 type for arm guests.
+This is a mandatory feature for Armv8.1 architectures but we don't
+state the feature clearly in our emulation list. Also include
+FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
+Cc: qemu-stable@nongnu.org
+Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
+[PMM: pluralize 'instructions' in docs]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20200713175746.5936-5-peter.maydell@linaro.org
 ---
- docs/system/arm/virt.rst   | 161 +++++++++++++++++++++++++++++++++++++
+ docs/system/arm/emulation.rst | 1 +
- docs/system/target-arm.rst |   1 +
+ target/arm/tcg/cpu64.c        | 2 +-
- MAINTAINERS                |   1 +
+files changed, 2 insertions(+), 1 deletion(-)
 files changed, 163 insertions(+)
  create mode 100644 docs/system/arm/virt.rst
-diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@
 +'virt' generic virtual platform (``virt``)
 +==========================================
 +
 +The `virt` board is a platform which does not correspond to any
 +real hardware; it is designed for use in virtual machines.
 +It is the recommended board type if you simply want to run
 +a guest such as Linux and do not care about reproducing the
 +idiosyncrasies and limitations of a particular bit of real-world
 +hardware.
 +
 +This is a "versioned" board model, so as well as the ``virt`` machine
 +type itself (which may have improvements, bugfixes and other minor
 +changes between QEMU versions) a version is provided that guarantees
 +to have the same behaviour as that of previous QEMU releases, so
 +that VM migration will work between QEMU versions. For instance the
 +``virt-5.0`` machine type will behave like the ``virt`` machine from
 +the QEMU 5.0 release, and migration should work between ``virt-5.0``
 +of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
 +is not guaranteed to work between different QEMU releases for
 +the non-versioned ``virt`` machine type.
 +
 +Supported devices
 +"""""""""""""""""
 +
 +The virt board supports:
 +
 +- PCI/PCIe devices
 +- Flash memory
 +- One PL011 UART
 +- An RTC
 +- The fw_cfg device that allows a guest to obtain data from QEMU
 +- A PL061 GPIO controller
 +- An optional SMMUv3 IOMMU
 +- hotpluggable DIMMs
 +- hotpluggable NVDIMMs
 +- An MSI controller (GICv2M or ITS). GICv2M is selected by default along
 +  with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note
 +  that ITS is not modeled in TCG mode.
 +- 32 virtio-mmio transport devices
 +- running guests using the KVM accelerator on aarch64 hardware
 +- large amounts of RAM (at least 255GB, and more if using highmem)
 +- many CPUs (up to 512 if using a GICv3 and highmem)
 +- Secure-World-only devices if the CPU has TrustZone:
 +
 +  - A second PL011 UART
 +  - A secure flash memory
 +  - 16MB of secure RAM
 +
 +Supported guest CPU types:
 +
 +- ``cortex-a7`` (32-bit)
 +- ``cortex-a15`` (32-bit; the default)
 +- ``cortex-a53`` (64-bit)
 +- ``cortex-a57`` (64-bit)
 +- ``cortex-a72`` (64-bit)
 +- ``host`` (with KVM only)
 +- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
 +
 +Note that the default is ``cortex-a15``, so for an AArch64 guest you must
 +specify a CPU type.
 +
 +Graphics output is available, but unlike the x86 PC machine types
 +there is no default display device enabled: you should select one from
 +the Display devices section of "-device help". The recommended option
 +is ``virtio-gpu-pci``; this is the only one which will work correctly
 +with KVM. You may also need to ensure your guest kernel is configured
 +with support for this; see below.
 +
 +Machine-specific options
 +""""""""""""""""""""""""
 +
 +The following machine-specific options are supported:
 +
 +secure
 +  Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
 +  Arm Security Extensions (TrustZone). The default is ``off``.
 +
 +virtualization
 +  Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
 +  Arm Virtualization Extensions. The default is ``off``.
 +
 +highmem
 +  Set ``on``/``off`` to enable/disable placing devices and RAM in physical
 +  address space above 32 bits. The default is ``on`` for machine types
 +  later than ``virt-2.12``.
 +
 +gic-version
 +  Specify the version of the Generic Interrupt Controller (GIC) to provide.
 +  Valid values are:
 +
 +  ``2``
 +    GICv2
 +  ``3``
 +    GICv3
 +  ``host``
 +    Use the same GIC version the host provides, when using KVM
 +  ``max``
 +    Use the best GIC version possible (same as host when using KVM;
 +    currently same as ``3``` for TCG, but this may change in future)
 +
 +its
 +  Set ``on``/``off`` to enable/disable ITS instantiation. The default is ``on``
 +  for machine types later than ``virt-2.7``.
 +
 +iommu
 +  Set the IOMMU type to create for the guest. Valid values are:
 +
 +  ``none``
 +    Don't create an IOMMU (the default)
 +  ``smmuv3``
 +    Create an SMMUv3
 +
 +ras
 +  Set ``on``/``off`` to enable/disable reporting host memory errors to a guest
 +  using ACPI and guest external abort exceptions. The default is off.
 +
 +Linux guest kernel configuration
 +""""""""""""""""""""""""""""""""
 +
 +The 'defconfig' for Linux arm and arm64 kernels should include the
 +right device drivers for virtio and the PCI controller; however some older
 +kernel versions, especially for 32-bit Arm, did not have everything
 +enabled by default. If you're not seeing PCI devices that you expect,
 +then check that your guest config has::
 +
 +  CONFIG_PCI=y
 +  CONFIG_VIRTIO_PCI=y
 +  CONFIG_PCI_HOST_GENERIC=y
 +
 +If you want to use the ``virtio-gpu-pci`` graphics device you will also
 +need::
 +
 +  CONFIG_DRM=y
 +  CONFIG_DRM_VIRTIO_GPU=y
 +
 +Hardware configuration information for bare-metal programming
 +"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 +
 +The ``virt`` board automatically generates a device tree blob ("dtb")
 +which it passes to the guest. This provides information about the
 +addresses, interrupt lines and other configuration of the various devices
 +in the system. Guest code can rely on and hard-code the following
 +addresses:
 +
 +- Flash memory starts at address 0x0000_0000
 +
 +- RAM starts at 0x4000_0000
 +
 +All other information about device locations may change between
 +QEMU versions, so guest code must look in the DTB.
 +
 +QEMU supports two types of guest image boot for ``virt``, and
 +the way for the guest code to locate the dtb binary differs:
 +
 +- For guests using the Linux kernel boot protocol (this means any
 +  non-ELF file passed to the QEMU ``-kernel`` option) the address
 +  of the DTB is passed in a register (``r2`` for 32-bit guests,
 +  or ``x0`` for 64-bit guests)
 +
 +- For guests booting as "bare-metal" (any other kind of boot),
 +  the DTB is at the start of RAM (0x4000_0000)
 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-arm.rst
+--- a/docs/system/arm/emulation.rst
-+++ b/docs/system/target-arm.rst
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-    arm/collie
+ - FEAT_BBM at level 2 (Translation table break-before-make levels)
-    arm/sx1
+ - FEAT_BF16 (AArch64 BFloat16 instructions)
-    arm/stellaris
+ - FEAT_BTI (Branch Target Identification)
-+   arm/virt
++- FEAT_CRC32 (CRC32 instructions)
+ - FEAT_CSV2 (Cache speculation variant 2)
- Arm CPU features
+ - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
- ================
+ - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
-diff --git a/MAINTAINERS b/MAINTAINERS
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/target/arm/tcg/cpu64.c
-+++ b/MAINTAINERS
++++ b/target/arm/tcg/cpu64.c
-@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
- S: Maintained
+     t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
- F: hw/arm/virt*
+     t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
- F: include/hw/arm/virt.h
+     t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
-+F: docs/system/arm/virt.rst
+-    t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
++    t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);    /* FEAT_CRC32 */
- Xilinx Zynq
+     t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
- M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+     t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
      t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
 --
-.20.1
+.34.1

-New patch
+[PULL 11/24] Remove i.MX7 IOMUX GPR device from i.MX6UL
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
+In particular, register 22 is not present on i.MX6UL and this is actualy
+The only register that is really emulated in the i.MX7 IOMUX GPR device.
+Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
+as an unimplemented device at the same bus adress and the 2 instantiations
+were actualy colliding. So we go back to the unimplemented device for now.
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx6ul.h |  2 --
+ hw/arm/fsl-imx6ul.c         | 11 -----------
+files changed, 13 deletions(-)
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/misc/imx6ul_ccm.h"
+ #include "hw/misc/imx6_src.h"
+ #include "hw/misc/imx7_snvs.h"
+-#include "hw/misc/imx7_gpr.h"
+ #include "hw/intc/imx_gpcv2.h"
+ #include "hw/watchdog/wdt_imx2.h"
+ #include "hw/gpio/imx_gpio.h"
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
+     IMX6SRCState       src;
+     IMX7SNVSState      snvs;
+     IMXGPCv2State      gpcv2;
+-    IMX7GPRState       gpr;
+     IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
+     IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
+     IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx6ul.c
++++ b/hw/arm/fsl-imx6ul.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+      */
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
+-    /*
+-     * GPR
+-     */
+-    object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
+-
+     /*
+      * GPIOs 1 to 5
+      */
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX6UL_WDOGn_IRQ[i]));
+     }
+-    /*
+-     * GPR
+-     */
+-    sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
+-
+     /*
+      * SDMA
+      */
+--
+.34.1

-New patch
+[PULL 12/24] Refactor i.MX6UL processor code
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
+* Use those newly defined named constants whenever possible.
+* Standardize the way we init a familly of unimplemented devices
+  - SAI
+  - PWM
+  - CAN
+* Add/rework few comments
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
+ hw/arm/fsl-imx6ul.c         | 147 ++++++++++++++++++++++-----------
+files changed, 232 insertions(+), 71 deletions(-)
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/memory.h"
+ #include "cpu.h"
+ #include "qom/object.h"
++#include "qemu/units.h"
+ #define TYPE_FSL_IMX6UL "fsl-imx6ul"
+ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
+     FSL_IMX6UL_NUM_ADCS         = 2,
+     FSL_IMX6UL_NUM_USB_PHYS     = 2,
+     FSL_IMX6UL_NUM_USBS         = 2,
++    FSL_IMX6UL_NUM_SAIS         = 3,
++    FSL_IMX6UL_NUM_CANS         = 2,
++    FSL_IMX6UL_NUM_PWMS         = 4,
+ };
+ struct FslIMX6ULState {
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
+ enum FslIMX6ULMemoryMap {
+     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
+-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
++    FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
+     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
+-    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
+-    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
+-    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
+-    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
++    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
+-    /* AIPS-2 */
++    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
++    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
++
++    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
++    FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
++
++    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
++    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
++
++    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
++    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
++
++    /* AIPS-2 Begin */
+     FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
++
+     FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
++
+     FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
+     FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
+     FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
+     FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
++
+     FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
++
+     FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
++    FSL_IMX6UL_QSPI_SIZE            = 0x500,
++
+     FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
++    FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
++
+     FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
++    FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
++
+     FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
++    FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
++
+     FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
++    FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
++
+     FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
++    FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
++    FSL_IMX6UL_LCDIF_SIZE           = 0x100,
++
+     FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
++    FSL_IMX6UL_CSI_SIZE             = 0x100,
++
+     FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
++    FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
++    FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
++
+     FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
++    FSL_IMX6UL_EIM_SIZE             = 0x100,
++
+     FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
++
+     FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
++    FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
++
+     FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
++    FSL_IMX6UL_ROMCP_SIZE           = 0x300,
++
+     FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
+     FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
+     FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
++
+     FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
+     FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
++    FSL_IMX6UL_ADCn_SIZE            = 0x100,
++
+     FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
+     FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
+-    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
+-    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
+-    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
+-    FSL_IMX6UL_USBO2_USB_ADDR       = 0x02184000,
+-    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
+-    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
+-    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
+-    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
+-    /* AIPS-1 */
++    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
++    FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
++
++    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
++
++    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
++    FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
++    FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
++
++    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
++    FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
++
++    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
++    FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
++
++    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
++    FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
++
++    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
++    FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
++    /* AIPS-2 End */
++
++    /* AIPS-1 Begin */
+     FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
+     FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
+     FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
+     FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
++
+     FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
++    FSL_IMX6UL_SDMA_SIZE            = 0x300,
++
+     FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
++
+     FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
++    FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
++
+     FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
++    FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
++
+     FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
++
+     FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
++
+     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
+     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
++
+     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
++
+     FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
+-    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
+     FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
+-    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
++
+     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
++    FSL_IMX6UL_ANALOG_SIZE          = 0x300,
++
+     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
++
+     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
+     FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
++
+     FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
++    FSL_IMX6UL_KPP_SIZE             = 0x10,
++
+     FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
++
+     FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
++    FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
++
+     FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
+     FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
+     FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
+     FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
+     FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
++
+     FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
++
+     FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
+     FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
++    FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
++
+     FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
+     FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
+     FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
+     FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
++    FSL_IMX6UL_PWMn_SIZE            = 0x20,
++
+     FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
++    FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
++
+     FSL_IMX6UL_BEE_ADDR             = 0x02044000,
++    FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
++    FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
++
+     FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
++    FSL_IMX6UL_SPBA_SIZE            = 0x100,
++
+     FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
++    FSL_IMX6UL_ASRC_SIZE            = 0x100,
++
+     FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
+     FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
+     FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
++    FSL_IMX6UL_SAIn_SIZE            = 0x200,
++
+     FSL_IMX6UL_UART8_ADDR           = 0x02024000,
+     FSL_IMX6UL_UART1_ADDR           = 0x02020000,
+     FSL_IMX6UL_UART7_ADDR           = 0x02018000,
++
+     FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
+     FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
+     FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
+     FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
++
+     FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
++    FSL_IMX6UL_SPDIF_SIZE           = 0x100,
++    /* AIPS-1 End */
++
++    FSL_IMX6UL_BCH_ADDR             = 0x01808000,
++    FSL_IMX6UL_BCH_SIZE             = 0x200,
++
++    FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
++    FSL_IMX6UL_GPMI_SIZE            = 0x200,
+     FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
+-    FSL_IMX6UL_APBH_DMA_SIZE        = (32 * 1024),
++    FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
+     FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
+     FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
+-    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = 0x00060000,
++    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
++
+     FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
+-    FSL_IMX6UL_OCRAM_MEM_SIZE       = 0x00020000,
++    FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
++
+     FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
+-    FSL_IMX6UL_CAAM_MEM_SIZE        = 0x00008000,
++    FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
++
+     FSL_IMX6UL_ROM_ADDR             = 0x00000000,
+-    FSL_IMX6UL_ROM_SIZE             = 0x00018000,
++    FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
+ };
+ enum FslIMX6ULIRQs {
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx6ul.c
++++ b/hw/arm/fsl-imx6ul.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
+     /*
+-     * GPIOs 1 to 5
++     * GPIOs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
+         snprintf(name, NAME_SIZE, "gpio%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * GPT 1, 2
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
+         snprintf(name, NAME_SIZE, "gpt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * EPIT 1, 2
++     * EPITs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
+         snprintf(name, NAME_SIZE, "epit%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * eCSPI
++     * eCSPIs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
+         snprintf(name, NAME_SIZE, "spi%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * I2C
++     * I2Cs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
+         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
+         snprintf(name, NAME_SIZE, "uart%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
+         snprintf(name, NAME_SIZE, "eth%d", i);
+         object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
+     }
+-    /* USB */
++    /*
++     * USB PHYs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+         snprintf(name, NAME_SIZE, "usbphy%d", i);
+         object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
+     }
++
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+         snprintf(name, NAME_SIZE, "usb%d", i);
+         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
+     }
+     /*
+-     * SDHCI
++     * SDHCIs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+         snprintf(name, NAME_SIZE, "usdhc%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
+         snprintf(name, NAME_SIZE, "wdt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+      * A7MPCORE DAP
+      */
+     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
+-                                0x100000);
++                                FSL_IMX6UL_A7MPCORE_DAP_SIZE);
+     /*
+-     * GPT 1, 2
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
+         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * EPIT 1, 2
++     * EPITs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
+         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * GPIO
++     * GPIOs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
+         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * IOMUXC and IOMUXC_GPR
++     * IOMUXC
+      */
+-    for (i = 0; i < 1; i++) {
+-        static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
+-            FSL_IMX6UL_IOMUXC_ADDR,
+-            FSL_IMX6UL_IOMUXC_GPR_ADDR,
+-        };
+-
+-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
+-        create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
+-    }
++    create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
++                                FSL_IMX6UL_IOMUXC_SIZE);
++    create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
++                                FSL_IMX6UL_IOMUXC_GPR_SIZE);
+     /*
+      * CCM
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
+-    /* Initialize all ECSPI */
++    /*
++     * ECSPIs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
+         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
+             FSL_IMX6UL_ECSPI1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * I2C
++     * I2Cs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
+         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
+         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      *
+      * We must use two loops since phy_connected affects the other interface
+      * and we have to set all properties before calling sysbus_realize().
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
+     }
+-    /* USB */
++    /*
++     * USB PHYs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
++        static const hwaddr
++                     FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
++            FSL_IMX6UL_USBPHY1_ADDR,
++            FSL_IMX6UL_USBPHY2_ADDR,
++        };
++
+         sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
+         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+-                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
++                        FSL_IMX6UL_USB_PHYn_ADDR[i]);
+     }
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
++        static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
++            FSL_IMX6UL_USBO2_USB1_ADDR,
++            FSL_IMX6UL_USBO2_USB2_ADDR,
++        };
++
+         static const int FSL_IMX6UL_USBn_IRQ[] = {
+             FSL_IMX6UL_USB1_IRQ,
+             FSL_IMX6UL_USB2_IRQ,
+         };
++
+         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
+         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+-                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
++                        FSL_IMX6UL_USB02_USBn_ADDR[i]);
+         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                                             FSL_IMX6UL_USBn_IRQ[i]));
+     }
+     /*
+-     * USDHC
++     * USDHCs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
+         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+             FSL_IMX6UL_WDOG2_ADDR,
+             FSL_IMX6UL_WDOG3_ADDR,
+         };
++
+         static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
+             FSL_IMX6UL_WDOG1_IRQ,
+             FSL_IMX6UL_WDOG2_IRQ,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     /*
+      * SDMA
+      */
+-    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
++    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
++                                FSL_IMX6UL_SDMA_SIZE);
+     /*
+-     * SAI (Audio SSI (Synchronous Serial Interface))
++     * SAIs (Audio SSI (Synchronous Serial Interface))
+      */
+-    create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
+-    create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
+-    create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
++        static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
++            FSL_IMX6UL_SAI1_ADDR,
++            FSL_IMX6UL_SAI2_ADDR,
++            FSL_IMX6UL_SAI3_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "sai%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
++                                    FSL_IMX6UL_SAIn_SIZE);
++    }
+     /*
+-     * PWM
++     * PWMs
+      */
+-    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
+-    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
+-    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
+-    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
++        static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
++            FSL_IMX6UL_PWM1_ADDR,
++            FSL_IMX6UL_PWM2_ADDR,
++            FSL_IMX6UL_PWM3_ADDR,
++            FSL_IMX6UL_PWM4_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "pwm%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
++                                    FSL_IMX6UL_PWMn_SIZE);
++    }
+     /*
+      * Audio ASRC (asynchronous sample rate converter)
+      */
+-    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
++    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
++                                FSL_IMX6UL_ASRC_SIZE);
+     /*
+-     * CAN
++     * CANs
+      */
+-    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
+-    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
++        static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
++            FSL_IMX6UL_CAN1_ADDR,
++            FSL_IMX6UL_CAN2_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "can%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
++                                    FSL_IMX6UL_CANn_SIZE);
++    }
+     /*
+      * APHB_DMA
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+         };
+         snprintf(name, NAME_SIZE, "adc%d", i);
+-        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
++        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
++                                    FSL_IMX6UL_ADCn_SIZE);
+     }
+     /*
+      * LCD
+      */
+-    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
++    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
++                                FSL_IMX6UL_LCDIF_SIZE);
+     /*
+      * ROM memory
+--
+.34.1

-New patch
+[PULL 13/24] Add i.MX6UL missing devices.
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+* Add TZASC as unimplemented device.
+  - Allow bare metal application to access this (unimplemented) device
+* Add CSU as unimplemented device.
+  - Allow bare metal application to access this (unimplemented) device
+* Add 4 missing PWM devices
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx6ul.h |  2 +-
+ hw/arm/fsl-imx6ul.c         | 16 ++++++++++++++++
+files changed, 17 insertions(+), 1 deletion(-)
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
+     FSL_IMX6UL_NUM_USBS         = 2,
+     FSL_IMX6UL_NUM_SAIS         = 3,
+     FSL_IMX6UL_NUM_CANS         = 2,
+-    FSL_IMX6UL_NUM_PWMS         = 4,
++    FSL_IMX6UL_NUM_PWMS         = 8,
+ };
+ struct FslIMX6ULState {
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx6ul.c
++++ b/hw/arm/fsl-imx6ul.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+             FSL_IMX6UL_PWM2_ADDR,
+             FSL_IMX6UL_PWM3_ADDR,
+             FSL_IMX6UL_PWM4_ADDR,
++            FSL_IMX6UL_PWM5_ADDR,
++            FSL_IMX6UL_PWM6_ADDR,
++            FSL_IMX6UL_PWM7_ADDR,
++            FSL_IMX6UL_PWM8_ADDR,
+         };
+         snprintf(name, NAME_SIZE, "pwm%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
+                                 FSL_IMX6UL_LCDIF_SIZE);
++    /*
++     * CSU
++     */
++    create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
++                                FSL_IMX6UL_CSU_SIZE);
++
++    /*
++     * TZASC
++     */
++    create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
++                                FSL_IMX6UL_TZASC_SIZE);
++
+     /*
+      * ROM memory
+      */
+--
+.34.1

-New patch
+[PULL 14/24] Refactor i.MX7 processor code
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
+* Use those newly defined named constants whenever possible.
+* Standardize the way we init a familly of unimplemented devices
+  - SAI
+  - PWM
+  - CAN
+* Add/rework few comments
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
+ hw/arm/fsl-imx7.c         | 130 ++++++++++-----
+files changed, 335 insertions(+), 125 deletions(-)
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx7.h
++++ b/include/hw/arm/fsl-imx7.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/misc/imx7_ccm.h"
+ #include "hw/misc/imx7_snvs.h"
+ #include "hw/misc/imx7_gpr.h"
+-#include "hw/misc/imx6_src.h"
+ #include "hw/watchdog/wdt_imx2.h"
+ #include "hw/gpio/imx_gpio.h"
+ #include "hw/char/imx_serial.h"
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/usb/chipidea.h"
+ #include "cpu.h"
+ #include "qom/object.h"
++#include "qemu/units.h"
+ #define TYPE_FSL_IMX7 "fsl-imx7"
+ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
+@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
+     FSL_IMX7_NUM_ECSPIS       = 4,
+     FSL_IMX7_NUM_USBS         = 3,
+     FSL_IMX7_NUM_ADCS         = 2,
++    FSL_IMX7_NUM_SAIS         = 3,
++    FSL_IMX7_NUM_CANS         = 2,
++    FSL_IMX7_NUM_PWMS         = 4,
+ };
+ struct FslIMX7State {
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
+ enum FslIMX7MemoryMap {
+     FSL_IMX7_MMDC_ADDR            = 0x80000000,
+-    FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
++    FSL_IMX7_MMDC_SIZE            = (2 * GiB),
+-    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
+-    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
+-    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
+-    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
+-    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
+-    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
+-    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
++    FSL_IMX7_QSPI1_MEM_ADDR       = 0x60000000,
++    FSL_IMX7_QSPI1_MEM_SIZE       = (256 * MiB),
+-    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
++    FSL_IMX7_PCIE1_MEM_ADDR       = 0x40000000,
++    FSL_IMX7_PCIE1_MEM_SIZE       = (256 * MiB),
+-    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
+-    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
+-    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
+-    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
++    FSL_IMX7_QSPI1_RX_BUF_ADDR    = 0x34000000,
++    FSL_IMX7_QSPI1_RX_BUF_SIZE    = (32 * MiB),
+-    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
++    /* PCIe Peripherals */
++    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
+-    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
+-    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
+-    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
+-    FSL_IMX7_GPT4_ADDR            = 0x30300000,
++    /* MMAP Peripherals */
++    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
++    FSL_IMX7_DMA_APBH_SIZE        = 0x8000,
+-    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
+-    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
+-    FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
++    /* GPV configuration */
++    FSL_IMX7_GPV6_ADDR            = 0x32600000,
++    FSL_IMX7_GPV5_ADDR            = 0x32500000,
++    FSL_IMX7_GPV4_ADDR            = 0x32400000,
++    FSL_IMX7_GPV3_ADDR            = 0x32300000,
++    FSL_IMX7_GPV2_ADDR            = 0x32200000,
++    FSL_IMX7_GPV1_ADDR            = 0x32100000,
++    FSL_IMX7_GPV0_ADDR            = 0x32000000,
++    FSL_IMX7_GPVn_SIZE            = (1 * MiB),
+-    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
+-    FSL_IMX7_OCOTP_SIZE           = 0x10000,
++    /* Arm Peripherals */
++    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
+-    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
+-    FSL_IMX7_SNVS_ADDR            = 0x30370000,
+-    FSL_IMX7_CCM_ADDR             = 0x30380000,
++    /* AIPS-3 Begin */
+-    FSL_IMX7_SRC_ADDR             = 0x30390000,
+-    FSL_IMX7_SRC_SIZE             = 0x1000,
++    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
++    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
+-    FSL_IMX7_ADC1_ADDR            = 0x30610000,
+-    FSL_IMX7_ADC2_ADDR            = 0x30620000,
+-    FSL_IMX7_ADCn_SIZE            = 0x1000,
++    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
++    FSL_IMX7_SDMA_SIZE            = (4 * KiB),
+-    FSL_IMX7_PWM1_ADDR            = 0x30660000,
+-    FSL_IMX7_PWM2_ADDR            = 0x30670000,
+-    FSL_IMX7_PWM3_ADDR            = 0x30680000,
+-    FSL_IMX7_PWM4_ADDR            = 0x30690000,
+-    FSL_IMX7_PWMn_SIZE            = 0x10000,
++    FSL_IMX7_EIM_ADDR             = 0x30BC0000,
++    FSL_IMX7_EIM_SIZE             = (4 * KiB),
+-    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
+-    FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
++    FSL_IMX7_QSPI_ADDR            = 0x30BB0000,
++    FSL_IMX7_QSPI_SIZE            = 0x8000,
+-    FSL_IMX7_GPC_ADDR             = 0x303A0000,
++    FSL_IMX7_SIM2_ADDR            = 0x30BA0000,
++    FSL_IMX7_SIM1_ADDR            = 0x30B90000,
++    FSL_IMX7_SIMn_SIZE            = (4 * KiB),
++
++    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
++    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
++    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
++
++    FSL_IMX7_USB3_ADDR            = 0x30B30000,
++    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
++    FSL_IMX7_USB2_ADDR            = 0x30B20000,
++    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
++    FSL_IMX7_USB1_ADDR            = 0x30B10000,
++    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
++    FSL_IMX7_USBMISCn_SIZE        = 0x200,
++
++    FSL_IMX7_USB_PL301_ADDR       = 0x30AD0000,
++    FSL_IMX7_USB_PL301_SIZE       = (64 * KiB),
++
++    FSL_IMX7_SEMAPHORE_HS_ADDR    = 0x30AC0000,
++    FSL_IMX7_SEMAPHORE_HS_SIZE    = (64 * KiB),
++
++    FSL_IMX7_MUB_ADDR             = 0x30AB0000,
++    FSL_IMX7_MUA_ADDR             = 0x30AA0000,
++    FSL_IMX7_MUn_SIZE             = (KiB),
++
++    FSL_IMX7_UART7_ADDR           = 0x30A90000,
++    FSL_IMX7_UART6_ADDR           = 0x30A80000,
++    FSL_IMX7_UART5_ADDR           = 0x30A70000,
++    FSL_IMX7_UART4_ADDR           = 0x30A60000,
++
++    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
++    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
++    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
++    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
++
++    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
++    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
++    FSL_IMX7_CANn_SIZE            = (4 * KiB),
++
++    FSL_IMX7_AIPS3_CONF_ADDR      = 0x309F0000,
++    FSL_IMX7_AIPS3_CONF_SIZE      = (64 * KiB),
+     FSL_IMX7_CAAM_ADDR            = 0x30900000,
+-    FSL_IMX7_CAAM_SIZE            = 0x40000,
++    FSL_IMX7_CAAM_SIZE            = (256 * KiB),
+-    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
+-    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
+-    FSL_IMX7_CANn_SIZE            = 0x10000,
++    FSL_IMX7_SPBA_ADDR            = 0x308F0000,
++    FSL_IMX7_SPBA_SIZE            = (4 * KiB),
+-    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
+-    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
+-    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
+-    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
++    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
++    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
++    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
++    FSL_IMX7_SAIn_SIZE            = (4 * KiB),
+-    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
+-    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
+-    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
+-    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
+-
+-    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
+-    FSL_IMX7_LCDIF_SIZE           = 0x1000,
+-
+-    FSL_IMX7_UART1_ADDR           = 0x30860000,
++    FSL_IMX7_UART3_ADDR           = 0x30880000,
+     /*
+      * Some versions of the reference manual claim that UART2 is @
+      * 0x30870000, but experiments with HW + DT files in upstream
+@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
+      * actually located @ 0x30890000
+      */
+     FSL_IMX7_UART2_ADDR           = 0x30890000,
+-    FSL_IMX7_UART3_ADDR           = 0x30880000,
+-    FSL_IMX7_UART4_ADDR           = 0x30A60000,
+-    FSL_IMX7_UART5_ADDR           = 0x30A70000,
+-    FSL_IMX7_UART6_ADDR           = 0x30A80000,
+-    FSL_IMX7_UART7_ADDR           = 0x30A90000,
++    FSL_IMX7_UART1_ADDR           = 0x30860000,
+-    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
+-    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
+-    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
+-    FSL_IMX7_SAIn_SIZE            = 0x10000,
++    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
++    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
++    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
++    FSL_IMX7_ECSPIn_SIZE          = (4 * KiB),
+-    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
+-    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
++    /* AIPS-3 End */
+-    FSL_IMX7_USB1_ADDR            = 0x30B10000,
+-    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
+-    FSL_IMX7_USB2_ADDR            = 0x30B20000,
+-    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
+-    FSL_IMX7_USB3_ADDR            = 0x30B30000,
+-    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
+-    FSL_IMX7_USBMISCn_SIZE        = 0x200,
++    /* AIPS-2 Begin */
+-    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
+-    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
+-    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
++    FSL_IMX7_AXI_DEBUG_MON_ADDR   = 0x307E0000,
++    FSL_IMX7_AXI_DEBUG_MON_SIZE   = (64 * KiB),
+-    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
+-    FSL_IMX7_SDMA_SIZE            = 0x1000,
++    FSL_IMX7_PERFMON2_ADDR        = 0x307D0000,
++    FSL_IMX7_PERFMON1_ADDR        = 0x307C0000,
++    FSL_IMX7_PERFMONn_SIZE        = (64 * KiB),
++
++    FSL_IMX7_DDRC_ADDR            = 0x307A0000,
++    FSL_IMX7_DDRC_SIZE            = (4 * KiB),
++
++    FSL_IMX7_DDRC_PHY_ADDR        = 0x30790000,
++    FSL_IMX7_DDRC_PHY_SIZE        = (4 * KiB),
++
++    FSL_IMX7_TZASC_ADDR           = 0x30780000,
++    FSL_IMX7_TZASC_SIZE           = (64 * KiB),
++
++    FSL_IMX7_MIPI_DSI_ADDR        = 0x30760000,
++    FSL_IMX7_MIPI_DSI_SIZE        = (4 * KiB),
++
++    FSL_IMX7_MIPI_CSI_ADDR        = 0x30750000,
++    FSL_IMX7_MIPI_CSI_SIZE        = 0x4000,
++
++    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
++    FSL_IMX7_LCDIF_SIZE           = 0x8000,
++
++    FSL_IMX7_CSI_ADDR             = 0x30710000,
++    FSL_IMX7_CSI_SIZE             = (4 * KiB),
++
++    FSL_IMX7_PXP_ADDR             = 0x30700000,
++    FSL_IMX7_PXP_SIZE             = 0x4000,
++
++    FSL_IMX7_EPDC_ADDR            = 0x306F0000,
++    FSL_IMX7_EPDC_SIZE            = (4 * KiB),
++
++    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
++    FSL_IMX7_PCIE_PHY_SIZE        = (4 * KiB),
++
++    FSL_IMX7_SYSCNT_CTRL_ADDR     = 0x306C0000,
++    FSL_IMX7_SYSCNT_CMP_ADDR      = 0x306B0000,
++    FSL_IMX7_SYSCNT_RD_ADDR       = 0x306A0000,
++
++    FSL_IMX7_PWM4_ADDR            = 0x30690000,
++    FSL_IMX7_PWM3_ADDR            = 0x30680000,
++    FSL_IMX7_PWM2_ADDR            = 0x30670000,
++    FSL_IMX7_PWM1_ADDR            = 0x30660000,
++    FSL_IMX7_PWMn_SIZE            = (4 * KiB),
++
++    FSL_IMX7_FlEXTIMER2_ADDR      = 0x30650000,
++    FSL_IMX7_FlEXTIMER1_ADDR      = 0x30640000,
++    FSL_IMX7_FLEXTIMERn_SIZE      = (4 * KiB),
++
++    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
++
++    FSL_IMX7_ADC2_ADDR            = 0x30620000,
++    FSL_IMX7_ADC1_ADDR            = 0x30610000,
++    FSL_IMX7_ADCn_SIZE            = (4 * KiB),
++
++    FSL_IMX7_AIPS2_CONF_ADDR      = 0x305F0000,
++    FSL_IMX7_AIPS2_CONF_SIZE      = (64 * KiB),
++
++    /* AIPS-2 End */
++
++    /* AIPS-1 Begin */
++
++    FSL_IMX7_CSU_ADDR             = 0x303E0000,
++    FSL_IMX7_CSU_SIZE             = (64 * KiB),
++
++    FSL_IMX7_RDC_ADDR             = 0x303D0000,
++    FSL_IMX7_RDC_SIZE             = (4 * KiB),
++
++    FSL_IMX7_SEMAPHORE2_ADDR      = 0x303C0000,
++    FSL_IMX7_SEMAPHORE1_ADDR      = 0x303B0000,
++    FSL_IMX7_SEMAPHOREn_SIZE      = (4 * KiB),
++
++    FSL_IMX7_GPC_ADDR             = 0x303A0000,
++
++    FSL_IMX7_SRC_ADDR             = 0x30390000,
++    FSL_IMX7_SRC_SIZE             = (4 * KiB),
++
++    FSL_IMX7_CCM_ADDR             = 0x30380000,
++
++    FSL_IMX7_SNVS_HP_ADDR         = 0x30370000,
++
++    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
++
++    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
++    FSL_IMX7_OCOTP_SIZE           = 0x10000,
++
++    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
++    FSL_IMX7_IOMUXC_GPR_SIZE      = (4 * KiB),
++
++    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
++    FSL_IMX7_IOMUXC_SIZE          = (4 * KiB),
++
++    FSL_IMX7_KPP_ADDR             = 0x30320000,
++    FSL_IMX7_KPP_SIZE             = (4 * KiB),
++
++    FSL_IMX7_ROMCP_ADDR           = 0x30310000,
++    FSL_IMX7_ROMCP_SIZE           = (4 * KiB),
++
++    FSL_IMX7_GPT4_ADDR            = 0x30300000,
++    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
++    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
++    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
++
++    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
++    FSL_IMX7_IOMUXC_LPSR_SIZE     = (4 * KiB),
++
++    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
++    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
++    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
++    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
++
++    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
++
++    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
++    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
++    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
++    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
++    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
++    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
++    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
++
++    FSL_IMX7_AIPS1_CONF_ADDR      = 0x301F0000,
++    FSL_IMX7_AIPS1_CONF_SIZE      = (64 * KiB),
+-    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
+     FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
++    FSL_IMX7_A7MPCORE_DAP_SIZE    = (1 * MiB),
+-    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
+-    FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
++    /* AIPS-1 End */
+-    FSL_IMX7_GPR_ADDR             = 0x30340000,
++    FSL_IMX7_EIM_CS0_ADDR         = 0x28000000,
++    FSL_IMX7_EIM_CS0_SIZE         = (128 * MiB),
+-    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
+-    FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
++    FSL_IMX7_OCRAM_PXP_ADDR       = 0x00940000,
++    FSL_IMX7_OCRAM_PXP_SIZE       = (32 * KiB),
++
++    FSL_IMX7_OCRAM_EPDC_ADDR      = 0x00920000,
++    FSL_IMX7_OCRAM_EPDC_SIZE      = (128 * KiB),
++
++    FSL_IMX7_OCRAM_MEM_ADDR       = 0x00900000,
++    FSL_IMX7_OCRAM_MEM_SIZE       = (128 * KiB),
++
++    FSL_IMX7_TCMU_ADDR            = 0x00800000,
++    FSL_IMX7_TCMU_SIZE            = (32 * KiB),
++
++    FSL_IMX7_TCML_ADDR            = 0x007F8000,
++    FSL_IMX7_TCML_SIZE            = (32 * KiB),
++
++    FSL_IMX7_OCRAM_S_ADDR         = 0x00180000,
++    FSL_IMX7_OCRAM_S_SIZE         = (32 * KiB),
++
++    FSL_IMX7_CAAM_MEM_ADDR        = 0x00100000,
++    FSL_IMX7_CAAM_MEM_SIZE        = (32 * KiB),
++
++    FSL_IMX7_ROM_ADDR             = 0x00000000,
++    FSL_IMX7_ROM_SIZE             = (96 * KiB),
+ };
+ enum FslIMX7IRQs {
+diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx7.c
++++ b/hw/arm/fsl-imx7.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+     char name[NAME_SIZE];
+     int i;
++    /*
++     * CPUs
++     */
+     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
+         snprintf(name, NAME_SIZE, "cpu%d", i);
+         object_initialize_child(obj, name, &s->cpu[i],
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+                             TYPE_A15MPCORE_PRIV);
+     /*
+-     * GPIOs 1 to 7
++     * GPIOs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
+         snprintf(name, NAME_SIZE, "gpio%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+     }
+     /*
+-     * GPT1, 2, 3, 4
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
+         snprintf(name, NAME_SIZE, "gpt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+      */
+     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
++    /*
++     * ECSPIs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
+         snprintf(name, NAME_SIZE, "spi%d", i + 1);
+         object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
+     }
+-
++    /*
++     * I2Cs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
+         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
+         object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
+             snprintf(name, NAME_SIZE, "uart%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      */
+     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
+             snprintf(name, NAME_SIZE, "eth%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+     }
+     /*
+-     * SDHCI
++     * SDHCIs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
+             snprintf(name, NAME_SIZE, "usdhc%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
+             snprintf(name, NAME_SIZE, "wdt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+      */
+     object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
++    /*
++     * PCIE
++     */
+     object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
+         snprintf(name, NAME_SIZE, "usb%d", i);
+         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+         return;
+     }
++    /*
++     * CPUs
++     */
+     for (i = 0; i < smp_cpus; i++) {
+         o = OBJECT(&s->cpu[i]);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+      * A7MPCORE DAP
+      */
+     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
+-                                0x100000);
++                                FSL_IMX7_A7MPCORE_DAP_SIZE);
+     /*
+-     * GPT1, 2, 3, 4
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
+         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX7_GPTn_IRQ[i]));
+     }
++    /*
++     * GPIOs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
+         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
+             FSL_IMX7_GPIO1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     /*
+      * IOMUXC and IOMUXC_LPSR
+      */
+-    for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
+-        static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
+-            FSL_IMX7_IOMUXC_ADDR,
+-            FSL_IMX7_IOMUXC_LPSR_ADDR,
+-        };
+-
+-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
+-        create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
+-                                    FSL_IMX7_IOMUXCn_SIZE);
+-    }
++    create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
++                                FSL_IMX7_IOMUXC_SIZE);
++    create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
++                                FSL_IMX7_IOMUXC_LPSR_SIZE);
+     /*
+      * CCM
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
+-    /* Initialize all ECSPI */
++    /*
++     * ECSPIs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
+         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
+             FSL_IMX7_ECSPI1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX7_SPIn_IRQ[i]));
+     }
++    /*
++     * I2Cs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
+         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
+             FSL_IMX7_I2C1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
+         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      *
+      * We must use two loops since phy_connected affects the other interface
+      * and we have to set all properties before calling sysbus_realize().
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * USDHC
++     * USDHCs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
+         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+      * SNVS
+      */
+     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
+     /*
+      * SRC
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
+         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
+     /*
+-     * PWM
++     * PWMs
+      */
+-    create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
+-    create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
+-    create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
+-    create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
++    for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
++        static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
++            FSL_IMX7_PWM1_ADDR,
++            FSL_IMX7_PWM2_ADDR,
++            FSL_IMX7_PWM3_ADDR,
++            FSL_IMX7_PWM4_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "pwm%d", i);
++        create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
++                                    FSL_IMX7_PWMn_SIZE);
++    }
+     /*
+-     * CAN
++     * CANs
+      */
+-    create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
+-    create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
++    for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
++        static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
++            FSL_IMX7_CAN1_ADDR,
++            FSL_IMX7_CAN2_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "can%d", i);
++        create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
++                                    FSL_IMX7_CANn_SIZE);
++    }
+     /*
+-     * SAI (Audio SSI (Synchronous Serial Interface))
++     * SAIs (Audio SSI (Synchronous Serial Interface))
+      */
+-    create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
+-    create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
+-    create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
++    for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
++        static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
++            FSL_IMX7_SAI1_ADDR,
++            FSL_IMX7_SAI2_ADDR,
++            FSL_IMX7_SAI3_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "sai%d", i);
++        create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
++                                    FSL_IMX7_SAIn_SIZE);
++    }
+     /*
+      * OCOTP
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
+                                 FSL_IMX7_OCOTP_SIZE);
++    /*
++     * GPR
++     */
+     sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
++    /*
++     * PCIE
++     */
+     sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
+-
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
+         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
+             FSL_IMX7_USBMISC1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+      */
+     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
+                                 FSL_IMX7_PCIE_PHY_SIZE);
++
+ }
+ static Property fsl_imx7_properties[] = {
+--
+.34.1

-[PULL 04/12] util: Implement qemu_get_thread_id() for OpenBSD
+[PULL 15/24] Add i.MX7 missing TZ devices and memory regions
-From: David CARLIER <devnexen@gmail.com>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-Implement qemu_get_thread_id() for OpenBSD hosts, using
+* Add TZASC as unimplemented device.
-getthrid().
+  - Allow bare metal application to access this (unimplemented) device
 * Add CSU as unimplemented device.
   - Allow bare metal application to access this (unimplemented) device
 * Add various memory segments
   - OCRAM
   - OCRAM EPDC
   - OCRAM PXP
   - OCRAM S
   - ROM
   - CAAM
-Signed-off-by: David Carlier <devnexen@gmail.com>
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-Reviewed-by: Brad Smith <brad@comstyle.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: CA+XhMqxD6gQDBaj8tX0CMEj3si7qYKsM8u1km47e_-U7MC37Pg@mail.gmail.com
+Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 [PMM: tidied up commit message]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- util/oslib-posix.c | 2 ++
+ include/hw/arm/fsl-imx7.h |  7 +++++
-file changed, 2 insertions(+)
+ hw/arm/fsl-imx7.c         | 63 +++++++++++++++++++++++++++++++++++++++
 files changed, 70 insertions(+)
-diff --git a/util/oslib-posix.c b/util/oslib-posix.c
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/util/oslib-posix.c
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/util/oslib-posix.c
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@ int qemu_get_thread_id(void)
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
-     return (int)tid;
+     IMX7GPRState       gpr;
- #elif defined(__NetBSD__)
+     ChipideaState      usb[FSL_IMX7_NUM_USBS];
-     return _lwp_self();
+     DesignwarePCIEHost pcie;
-+#elif defined(__OpenBSD__)
++    MemoryRegion       rom;
-+    return getthrid();
++    MemoryRegion       caam;
- #else
++    MemoryRegion       ocram;
-     return getpid();
++    MemoryRegion       ocram_epdc;
- #endif
++    MemoryRegion       ocram_pxp;
 +    MemoryRegion       ocram_s;
 +
      uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
      bool               phy_connected[FSL_IMX7_NUM_ETHS];
  };
 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx7.c
 +++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                  FSL_IMX7_PCIE_PHY_SIZE);
 +    /*
 +     * CSU
 +     */
 +    create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
 +                                FSL_IMX7_CSU_SIZE);
 +
 +    /*
 +     * TZASC
 +     */
 +    create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
 +                                FSL_IMX7_TZASC_SIZE);
 +
 +    /*
 +     * OCRAM memory
 +     */
 +    memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
 +                           FSL_IMX7_OCRAM_MEM_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
 +                                &s->ocram);
 +
 +    /*
 +     * OCRAM EPDC memory
 +     */
 +    memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
 +                           FSL_IMX7_OCRAM_EPDC_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
 +                                &s->ocram_epdc);
 +
 +    /*
 +     * OCRAM PXP memory
 +     */
 +    memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
 +                           FSL_IMX7_OCRAM_PXP_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
 +                                &s->ocram_pxp);
 +
 +    /*
 +     * OCRAM_S memory
 +     */
 +    memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
 +                           FSL_IMX7_OCRAM_S_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
 +                                &s->ocram_s);
 +
 +    /*
 +     * ROM memory
 +     */
 +    memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
 +                           FSL_IMX7_ROM_SIZE, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
 +                                &s->rom);
 +
 +    /*
 +     * CAAM memory
 +     */
 +    memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
 +                           FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
 +                                &s->caam);
  }
  static Property fsl_imx7_properties[] = {
 --
-.20.1
+.34.1

-New patch
+[PULL 16/24] Add i.MX7 SRC device implementation
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
 The SRC device is normally used to start the secondary CPU.
 When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
 is installing at boot time and therefore the fact that the SRC device is
 unimplemented is hidden as Qemu respond directly to PSCI requets without
 using the SRC device.
 But if you try to run a more bare metal application (maybe uboot itself),
 then it is not possible to start the secondary CPU as the SRC is an
 unimplemented device.
 This patch adds the ability to start the secondary CPU through the SRC
 device so that you can use this feature in bare metal applications.
 Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/fsl-imx7.h  |   3 +-
  include/hw/misc/imx7_src.h |  66 +++++++++
  hw/arm/fsl-imx7.c          |   8 +-
  hw/misc/imx7_src.c         | 276 +++++++++++++++++++++++++++++++++++++
  hw/misc/meson.build        |   1 +
  hw/misc/trace-events       |   4 +
 files changed, 356 insertions(+), 2 deletions(-)
  create mode 100644 include/hw/misc/imx7_src.h
  create mode 100644 hw/misc/imx7_src.c
 diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/fsl-imx7.h
 +++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/misc/imx7_ccm.h"
  #include "hw/misc/imx7_snvs.h"
  #include "hw/misc/imx7_gpr.h"
 +#include "hw/misc/imx7_src.h"
  #include "hw/watchdog/wdt_imx2.h"
  #include "hw/gpio/imx_gpio.h"
  #include "hw/char/imx_serial.h"
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
      IMX7CCMState       ccm;
      IMX7AnalogState    analog;
      IMX7SNVSState      snvs;
 +    IMX7SRCState       src;
      IMXGPCv2State      gpcv2;
      IMXSPIState        spi[FSL_IMX7_NUM_ECSPIS];
      IMXI2CState        i2c[FSL_IMX7_NUM_I2CS];
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
      FSL_IMX7_GPC_ADDR             = 0x303A0000,
      FSL_IMX7_SRC_ADDR             = 0x30390000,
 -    FSL_IMX7_SRC_SIZE             = (4 * KiB),
      FSL_IMX7_CCM_ADDR             = 0x30380000,
 diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/imx7_src.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * IMX7 System Reset Controller
 + *
 + * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
 +#ifndef IMX7_SRC_H
 +#define IMX7_SRC_H
 +
 +#include "hw/sysbus.h"
 +#include "qemu/bitops.h"
 +#include "qom/object.h"
 +
 +#define SRC_SCR 0
 +#define SRC_A7RCR0 1
 +#define SRC_A7RCR1 2
 +#define SRC_M4RCR 3
 +#define SRC_ERCR 5
 +#define SRC_HSICPHY_RCR 7
 +#define SRC_USBOPHY1_RCR 8
 +#define SRC_USBOPHY2_RCR 9
 +#define SRC_MPIPHY_RCR 10
 +#define SRC_PCIEPHY_RCR 11
 +#define SRC_SBMR1 22
 +#define SRC_SRSR 23
 +#define SRC_SISR 26
 +#define SRC_SIMR 27
 +#define SRC_SBMR2 28
 +#define SRC_GPR1 29
 +#define SRC_GPR2 30
 +#define SRC_GPR3 31
 +#define SRC_GPR4 32
 +#define SRC_GPR5 33
 +#define SRC_GPR6 34
 +#define SRC_GPR7 35
 +#define SRC_GPR8 36
 +#define SRC_GPR9 37
 +#define SRC_GPR10 38
 +#define SRC_MAX 39
 +
 +/* SRC_A7SCR1 */
 +#define R_CORE1_ENABLE_SHIFT     1
 +#define R_CORE1_ENABLE_LENGTH    1
 +/* SRC_A7SCR0 */
 +#define R_CORE1_RST_SHIFT        5
 +#define R_CORE1_RST_LENGTH       1
 +#define R_CORE0_RST_SHIFT        4
 +#define R_CORE0_RST_LENGTH       1
 +
 +#define TYPE_IMX7_SRC "imx7.src"
 +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC)
 +
 +struct IMX7SRCState {
 +    /* <private> */
 +    SysBusDevice parent_obj;
 +
 +    /* <public> */
 +    MemoryRegion iomem;
 +
 +    uint32_t regs[SRC_MAX];
 +};
 +
 +#endif /* IMX7_SRC_H */
 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx7.c
 +++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
       */
      object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 +    /*
 +     * SRC
 +     */
 +    object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC);
 +
      /*
       * ECSPIs
       */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      /*
       * SRC
       */
 -    create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
      /*
       * Watchdogs
 diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/imx7_src.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * IMX7 System Reset Controller
 + *
 + * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + *
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/misc/imx7_src.h"
 +#include "migration/vmstate.h"
 +#include "qemu/bitops.h"
 +#include "qemu/log.h"
 +#include "qemu/main-loop.h"
 +#include "qemu/module.h"
 +#include "target/arm/arm-powerctl.h"
 +#include "hw/core/cpu.h"
 +#include "hw/registerfields.h"
 +
 +#include "trace.h"
 +
 +static const char *imx7_src_reg_name(uint32_t reg)
 +{
 +    static char unknown[20];
 +
 +    switch (reg) {
 +    case SRC_SCR:
 +        return "SRC_SCR";
 +    case SRC_A7RCR0:
 +        return "SRC_A7RCR0";
 +    case SRC_A7RCR1:
 +        return "SRC_A7RCR1";
 +    case SRC_M4RCR:
 +        return "SRC_M4RCR";
 +    case SRC_ERCR:
 +        return "SRC_ERCR";
 +    case SRC_HSICPHY_RCR:
 +        return "SRC_HSICPHY_RCR";
 +    case SRC_USBOPHY1_RCR:
 +        return "SRC_USBOPHY1_RCR";
 +    case SRC_USBOPHY2_RCR:
 +        return "SRC_USBOPHY2_RCR";
 +    case SRC_PCIEPHY_RCR:
 +        return "SRC_PCIEPHY_RCR";
 +    case SRC_SBMR1:
 +        return "SRC_SBMR1";
 +    case SRC_SRSR:
 +        return "SRC_SRSR";
 +    case SRC_SISR:
 +        return "SRC_SISR";
 +    case SRC_SIMR:
 +        return "SRC_SIMR";
 +    case SRC_SBMR2:
 +        return "SRC_SBMR2";
 +    case SRC_GPR1:
 +        return "SRC_GPR1";
 +    case SRC_GPR2:
 +        return "SRC_GPR2";
 +    case SRC_GPR3:
 +        return "SRC_GPR3";
 +    case SRC_GPR4:
 +        return "SRC_GPR4";
 +    case SRC_GPR5:
 +        return "SRC_GPR5";
 +    case SRC_GPR6:
 +        return "SRC_GPR6";
 +    case SRC_GPR7:
 +        return "SRC_GPR7";
 +    case SRC_GPR8:
 +        return "SRC_GPR8";
 +    case SRC_GPR9:
 +        return "SRC_GPR9";
 +    case SRC_GPR10:
 +        return "SRC_GPR10";
 +    default:
 +        sprintf(unknown, "%u ?", reg);
 +        return unknown;
 +    }
 +}
 +
 +static const VMStateDescription vmstate_imx7_src = {
 +    .name = TYPE_IMX7_SRC,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +static void imx7_src_reset(DeviceState *dev)
 +{
 +    IMX7SRCState *s = IMX7_SRC(dev);
 +
 +    memset(s->regs, 0, sizeof(s->regs));
 +
 +    /* Set reset values */
 +    s->regs[SRC_SCR] = 0xA0;
 +    s->regs[SRC_SRSR] = 0x1;
 +    s->regs[SRC_SIMR] = 0x1F;
 +}
 +
 +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    uint32_t value = 0;
 +    IMX7SRCState *s = (IMX7SRCState *)opaque;
 +    uint32_t index = offset >> 2;
 +
 +    if (index < SRC_MAX) {
 +        value = s->regs[index];
 +    } else {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
 +    }
 +
 +    trace_imx7_src_read(imx7_src_reg_name(index), value);
 +
 +    return value;
 +}
 +
 +
 +/*
 + * The reset is asynchronous so we need to defer clearing the reset
 + * bit until the work is completed.
 + */
 +
 +struct SRCSCRResetInfo {
 +    IMX7SRCState *s;
 +    uint32_t reset_bit;
 +};
 +
 +static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
 +{
 +    struct SRCSCRResetInfo *ri = data.host_ptr;
 +    IMX7SRCState *s = ri->s;
 +
 +    assert(qemu_mutex_iothread_locked());
 +
 +    s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0);
 +
 +    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
 +
 +    g_free(ri);
 +}
 +
 +static void imx7_defer_clear_reset_bit(uint32_t cpuid,
 +                                       IMX7SRCState *s,
 +                                       uint32_t reset_shift)
 +{
 +    struct SRCSCRResetInfo *ri;
 +    CPUState *cpu = arm_get_cpu_by_id(cpuid);
 +
 +    if (!cpu) {
 +        return;
 +    }
 +
 +    ri = g_new(struct SRCSCRResetInfo, 1);
 +    ri->s = s;
 +    ri->reset_bit = reset_shift;
 +
 +    async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri));
 +}
 +
 +
 +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value,
 +                           unsigned size)
 +{
 +    IMX7SRCState *s = (IMX7SRCState *)opaque;
 +    uint32_t index = offset >> 2;
 +    long unsigned int change_mask;
 +    uint32_t current_value = value;
 +
 +    if (index >= SRC_MAX) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
 +        return;
 +    }
 +
 +    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
 +
 +    change_mask = s->regs[index] ^ (uint32_t)current_value;
 +
 +    switch (index) {
 +    case SRC_A7RCR0:
 +        if (FIELD_EX32(change_mask, CORE0, RST)) {
 +            arm_reset_cpu(0);
 +            imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT);
 +        }
 +        if (FIELD_EX32(change_mask, CORE1, RST)) {
 +            arm_reset_cpu(1);
 +            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
 +        }
 +        s->regs[index] = current_value;
 +        break;
 +    case SRC_A7RCR1:
 +        /*
 +         * On real hardware when the system reset controller starts a
 +         * secondary CPU it runs through some boot ROM code which reads
 +         * the SRC_GPRX registers controlling the start address and branches
 +         * to it.
 +         * Here we are taking a short cut and branching directly to the
 +         * requested address (we don't want to run the boot ROM code inside
 +         * QEMU)
 +         */
 +        if (FIELD_EX32(change_mask, CORE1, ENABLE)) {
 +            if (FIELD_EX32(current_value, CORE1, ENABLE)) {
 +                /* CORE 1 is brought up */
 +                arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
 +                               3, false);
 +            } else {
 +                /* CORE 1 is shut down */
 +                arm_set_cpu_off(1);
 +            }
 +            /* We clear the reset bits as the processor changed state */
 +            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
 +            clear_bit(R_CORE1_RST_SHIFT, &change_mask);
 +        }
 +        s->regs[index] = current_value;
 +        break;
 +    default:
 +        s->regs[index] = current_value;
 +        break;
 +    }
 +}
 +
 +static const struct MemoryRegionOps imx7_src_ops = {
 +    .read = imx7_src_read,
 +    .write = imx7_src_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .valid = {
 +        /*
 +         * Our device would not work correctly if the guest was doing
 +         * unaligned access. This might not be a limitation on the real
 +         * device but in practice there is no reason for a guest to access
 +         * this device unaligned.
 +         */
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +        .unaligned = false,
 +    },
 +};
 +
 +static void imx7_src_realize(DeviceState *dev, Error **errp)
 +{
 +    IMX7SRCState *s = IMX7_SRC(dev);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s,
 +                          TYPE_IMX7_SRC, 0x1000);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 +}
 +
 +static void imx7_src_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = imx7_src_realize;
 +    dc->reset = imx7_src_reset;
 +    dc->vmsd = &vmstate_imx7_src;
 +    dc->desc = "i.MX6 System Reset Controller";
 +}
 +
 +static const TypeInfo imx7_src_info = {
 +    .name          = TYPE_IMX7_SRC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(IMX7SRCState),
 +    .class_init    = imx7_src_class_init,
 +};
 +
 +static void imx7_src_register_types(void)
 +{
 +    type_register_static(&imx7_src_info);
 +}
 +
 +type_init(imx7_src_register_types)
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files(
    'imx6_src.c',
    'imx6ul_ccm.c',
    'imx7_ccm.c',
 +  'imx7_src.c',
    'imx7_gpr.c',
    'imx7_snvs.c',
    'imx_ccm.c',
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d"
  ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
  ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
 +# imx7_src.c
 +imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
 +imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
 +
  # iotkit-sysinfo.c
  iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
  iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 --
 .34.1

-New patch
+[PULL 17/24] target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
+The architecture requires (R_TYTWB) that an attempt to return from EL3
+when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
+enforces that the CPU can't ever be executing below EL3 with the
+NSE,NS bits indicating an invalid security state.)
+We were missing this check; add it.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
+---
+ target/arm/tcg/helper-a64.c | 9 +++++++++
+file changed, 9 insertions(+)
+diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/helper-a64.c
++++ b/target/arm/tcg/helper-a64.c
+@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
+         spsr &= ~PSTATE_SS;
+     }
++    /*
++     * FEAT_RME forbids return from EL3 with an invalid security state.
++     * We don't need an explicit check for FEAT_RME here because we enforce
++     * in scr_write() that you can't set the NSE bit without it.
++     */
++    if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
++        goto illegal_return;
++    }
++
+     new_el = el_from_spsr(spsr);
+     if (new_el == -1) {
+         goto illegal_return;
+--
+.34.1

-[PULL 11/12] docs/system: Briefly document gumstix boards
+[PULL 18/24] hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
-Add skeletal documentation of the gumstix boards
+In the m48t59 device we almost always use 64-bit arithmetic when
-('connex' and 'verdex').
+dealing with time_t deltas.  The one exception is in set_alarm(),
 which currently uses a plain 'int' to hold the difference between two
 time_t values.  Switch to int64_t instead to avoid any possible
 overflow issues.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20200713175746.5936-4-peter.maydell@linaro.org
 ---
- docs/system/arm/gumstix.rst | 21 +++++++++++++++++++++
+ hw/rtc/m48t59.c | 2 +-
- docs/system/target-arm.rst  |  1 +
+file changed, 1 insertion(+), 1 deletion(-)
  MAINTAINERS                 |  1 +
 files changed, 23 insertions(+)
  create mode 100644 docs/system/arm/gumstix.rst
-diff --git a/docs/system/arm/gumstix.rst b/docs/system/arm/gumstix.rst
+diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/arm/gumstix.rst
@@ -XXX,XX +XXX,XX @@
 +Gumstix Connex and Verdex (``connex``, ``verdex``)
 +==================================================
 +
 +These machines model the Gumstix Connex and Verdex boards.
 +The Connex has a PXA255 CPU and the Verdex has a PXA270.
 +
 +Implemented devices:
 +
 + * NOR flash
 + * SMC91C111 ethernet
 + * Interrupt controller
 + * DMA
 + * Timer
 + * GPIO
 + * MMC/SD card
 + * Fast infra-red communications port (FIR)
 + * LCD controller
 + * Synchronous serial ports (SPI)
 + * PCMCIA interface
 + * I2C
 + * I2S
 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-arm.rst
+--- a/hw/rtc/m48t59.c
-+++ b/docs/system/target-arm.rst
++++ b/hw/rtc/m48t59.c
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque)
-    arm/aspeed
-    arm/digic
+ static void set_alarm(M48t59State *NVRAM)
-    arm/musicpal
+ {
-+   arm/gumstix
+-    int diff;
-    arm/nseries
++    int64_t diff;
-    arm/orangepi
+     if (NVRAM->alrm_timer != NULL) {
-    arm/palm
+         timer_del(NVRAM->alrm_timer);
-diff --git a/MAINTAINERS b/MAINTAINERS
+         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ R: Philippe Mathieu-Daudé <f4bug@amsat.org>
  L: qemu-arm@nongnu.org
  S: Odd Fixes
  F: hw/arm/gumstix.c
 +F: docs/system/arm/gumstix.rst
  i.MX25 PDK
  M: Peter Maydell <peter.maydell@linaro.org>
 --
-.20.1
+.34.1

-[PULL 10/12] docs/system: Briefly document collie board
+[PULL 19/24] hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
-Add skeletal documentation of the collie board.
+In the twl92230 device, use int64_t for the two state fields
 sec_offset and alm_sec, because we set these to values that
 are either time_t or differences between two time_t values.
 These fields aren't saved in vmstate anywhere, so we can
 safely widen them.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20200713175746.5936-3-peter.maydell@linaro.org
 ---
- docs/system/arm/collie.rst | 16 ++++++++++++++++
+ hw/rtc/twl92230.c | 4 ++--
- docs/system/target-arm.rst |  1 +
+file changed, 2 insertions(+), 2 deletions(-)
  MAINTAINERS                |  1 +
 files changed, 18 insertions(+)
  create mode 100644 docs/system/arm/collie.rst
-diff --git a/docs/system/arm/collie.rst b/docs/system/arm/collie.rst
+diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/arm/collie.rst
@@ -XXX,XX +XXX,XX @@
 +Sharp Zaurus SL-5500 (``collie``)
 +=================================
 +
 +This machine is a model of the Sharp Zaurus SL-5500, which was
 +a 1990s PDA based on the StrongARM SA1110.
 +
 +Implemented devices:
 +
 + * NOR flash
 + * Interrupt controller
 + * Timer
 + * RTC
 + * GPIO
 + * Peripheral Pin Controller (PPC)
 + * UARTs
 + * Synchronous Serial Ports (SSP)
 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-arm.rst
+--- a/hw/rtc/twl92230.c
-+++ b/docs/system/target-arm.rst
++++ b/hw/rtc/twl92230.c
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ struct MenelausState {
-    arm/orangepi
+         struct tm tm;
-    arm/palm
+         struct tm new;
-    arm/xscale
+         struct tm alm;
-+   arm/collie
+-        int sec_offset;
-    arm/sx1
+-        int alm_sec;
-    arm/stellaris
++        int64_t sec_offset;
++        int64_t alm_sec;
-diff --git a/MAINTAINERS b/MAINTAINERS
+         int next_comp;
-index XXXXXXX..XXXXXXX 100644
+     } rtc;
---- a/MAINTAINERS
+     uint16_t rtc_next_vmstate;
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
  S: Odd Fixes
  F: hw/arm/collie.c
  F: hw/arm/strongarm*
 +F: docs/system/arm/collie.rst
  Stellaris
  M: Peter Maydell <peter.maydell@linaro.org>
 --
-.20.1
+.34.1

-[PULL 09/12] docs/system: Briefly document canon-a1100 board
+[PULL 20/24] hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
-Add skeletal documentation of the canon-a1100 board.
+In the aspeed_rtc device we store a difference between two time_t
 values in an 'int'. This is not really correct when time_t could
 be 64 bits. Enlarge the field to 'int64_t'.
 This is a migration compatibility break for the aspeed boards.
 While we are changing the vmstate, remove the accidental
 duplicate of the offset field.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20200713175746.5936-2-peter.maydell@linaro.org
 ---
- docs/system/arm/digic.rst  | 11 +++++++++++
+ include/hw/rtc/aspeed_rtc.h | 2 +-
- docs/system/target-arm.rst |  1 +
+ hw/rtc/aspeed_rtc.c         | 5 ++---
- MAINTAINERS                |  1 +
+files changed, 3 insertions(+), 4 deletions(-)
 files changed, 13 insertions(+)
  create mode 100644 docs/system/arm/digic.rst
-diff --git a/docs/system/arm/digic.rst b/docs/system/arm/digic.rst
+diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/arm/digic.rst
@@ -XXX,XX +XXX,XX @@
 +Canon A1100 (``canon-a1100``)
 +=============================
 +
 +This machine is a model of the Canon PowerShot A1100 camera, which
 +uses the DIGIC SoC. This model is based on reverse engineering efforts
 +by the contributors to the `CHDK <http://chdk.wikia.com/>`_ and
 +`Magic Lantern <http://www.magiclantern.fm/>`_ projects.
 +
 +The emulation is incomplete. In particular it can't be used
 +to run the original camera firmware, but it can successfully run
 +an experimental version of the `barebox bootloader <http://www.barebox.org/>`_.
 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
 index XXXXXXX..XXXXXXX 100644
---- a/docs/system/target-arm.rst
+--- a/include/hw/rtc/aspeed_rtc.h
-+++ b/docs/system/target-arm.rst
++++ b/include/hw/rtc/aspeed_rtc.h
-@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
+@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
-    arm/versatile
+     qemu_irq irq;
-    arm/vexpress
-    arm/aspeed
+     uint32_t reg[0x18];
-+   arm/digic
+-    int offset;
-    arm/musicpal
++    int64_t offset;
-    arm/nseries
-    arm/orangepi
+ };
-diff --git a/MAINTAINERS b/MAINTAINERS
 diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/hw/rtc/aspeed_rtc.c
-+++ b/MAINTAINERS
++++ b/hw/rtc/aspeed_rtc.c
-@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/digic.h
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
- F: hw/*/digic*
- F: include/hw/*/digic*
+ static const VMStateDescription vmstate_aspeed_rtc = {
- F: tests/acceptance/machine_arm_canona1100.py
+     .name = TYPE_ASPEED_RTC,
-+F: docs/system/arm/digic.rst
+-    .version_id = 1,
++    .version_id = 2,
- Goldfish RTC
+     .fields = (VMStateField[]) {
- M: Anup Patel <anup.patel@wdc.com>
+         VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
 -        VMSTATE_INT32(offset, AspeedRtcState),
 -        VMSTATE_INT32(offset, AspeedRtcState),
 +        VMSTATE_INT64(offset, AspeedRtcState),
          VMSTATE_END_OF_LIST()
      }
  };
 --
-.20.1
+.34.1

-[PULL 07/12] qdev: Document GPIO related functions
+[PULL 21/24] rtc: Use time_t for passing and returning time offsets
-Add documentation comments for the various qdev functions
+The functions qemu_get_timedate() and qemu_timedate_diff() take
-related to creating and connecting GPIO lines.
+and return a time offset as an integer. Coverity points out that
 means that when an RTC device implementation holds an offset
 as a time_t, as the m48t59 does, the time_t will get truncated.
 (CID 1507157, 1517772).
 The functions work with time_t internally, so make them use that type
 in their APIs.
 Note that this won't help any Y2038 issues where either the device
 model itself is keeping the offset in a 32-bit integer, or where the
 hardware under emulation has Y2038 or other rollover problems.  If we
 missed any cases of the former then hopefully Coverity will warn us
 about them since after this patch we'd be truncating a time_t in
 assignments from qemu_timedate_diff().)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20200711142425.16283-4-peter.maydell@linaro.org
 ---
- include/hw/qdev-core.h | 191 ++++++++++++++++++++++++++++++++++++++++-
+ include/sysemu/rtc.h | 4 ++--
-file changed, 189 insertions(+), 2 deletions(-)
+ softmmu/rtc.c        | 4 ++--
 files changed, 4 insertions(+), 4 deletions(-)
-diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
+diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/qdev-core.h
+--- a/include/sysemu/rtc.h
-+++ b/include/hw/qdev-core.h
++++ b/include/sysemu/rtc.h
-@@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
+@@ -XXX,XX +XXX,XX @@
- void qdev_machine_creation_done(void);
+  * The behaviour of the clock whose value this function returns will
- bool qdev_machine_modified(void);
+  * depend on the -rtc command line option passed by the user.
+  */
-+/**
+-void qemu_get_timedate(struct tm *tm, int offset);
-+ * qdev_get_gpio_in: Get one of a device's anonymous input GPIO lines
++void qemu_get_timedate(struct tm *tm, time_t offset);
-+ * @dev: Device whose GPIO we want
 + * @n: Number of the anonymous GPIO line (which must be in range)
 + *
 + * Returns the qemu_irq corresponding to an anonymous input GPIO line
 + * (which the device has set up with qdev_init_gpio_in()). The index
 + * @n of the GPIO line must be valid (i.e. be at least 0 and less than
 + * the total number of anonymous input GPIOs the device has); this
 + * function will assert() if passed an invalid index.
 + *
 + * This function is intended to be used by board code or SoC "container"
 + * device models to wire up the GPIO lines; usually the return value
 + * will be passed to qdev_connect_gpio_out() or a similar function to
 + * connect another device's output GPIO line to this input.
 + *
 + * For named input GPIO lines, use qdev_get_gpio_in_named().
 + */
  qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);
 +/**
 + * qdev_get_gpio_in_named: Get one of a device's named input GPIO lines
 + * @dev: Device whose GPIO we want
 + * @name: Name of the input GPIO array
 + * @n: Number of the GPIO line in that array (which must be in range)
 + *
 + * Returns the qemu_irq corresponding to a named input GPIO line
 + * (which the device has set up with qdev_init_gpio_in_named()).
 + * The @name string must correspond to an input GPIO array which exists on
 + * the device, and the index @n of the GPIO line must be valid (i.e.
 + * be at least 0 and less than the total number of input GPIOs in that
 + * array); this function will assert() if passed an invalid name or index.
 + *
 + * For anonymous input GPIO lines, use qdev_get_gpio_in().
 + */
  qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n);
 +/**
 + * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
 + * @dev: Device whose GPIO to connect
 + * @n: Number of the anonymous output GPIO line (which must be in range)
 + * @pin: qemu_irq to connect the output line to
 + *
 + * This function connects an anonymous output GPIO line on a device
 + * up to an arbitrary qemu_irq, so that when the device asserts that
 + * output GPIO line, the qemu_irq's callback is invoked.
 + * The index @n of the GPIO line must be valid (i.e. be at least 0 and
 + * less than the total number of anonymous output GPIOs the device has
 + * created with qdev_init_gpio_out()); otherwise this function will assert().
 + *
 + * Outbound GPIO lines can be connected to any qemu_irq, but the common
 + * case is connecting them to another device's inbound GPIO line, using
 + * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named().
 + *
 + * It is not valid to try to connect one outbound GPIO to multiple
 + * qemu_irqs at once, or to connect multiple outbound GPIOs to the
 + * same qemu_irq. (Warning: there is no assertion or other guard to
 + * catch this error: the model will just not do the right thing.)
 + * Instead, for fan-out you can use the TYPE_IRQ_SPLIT device: connect
 + * a device's outbound GPIO to the splitter's input, and connect each
 + * of the splitter's outputs to a different device.  For fan-in you
 + * can use the TYPE_OR_IRQ device, which is a model of a logical OR
 + * gate with multiple inputs and one output.
 + *
 + * For named output GPIO lines, use qdev_connect_gpio_out_named().
 + */
  void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin);
 +/**
 + * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
 + * @dev: Device whose GPIO to connect
 + * @name: Name of the output GPIO array
 + * @n: Number of the anonymous output GPIO line (which must be in range)
 + * @pin: qemu_irq to connect the output line to
 + *
 + * This function connects an anonymous output GPIO line on a device
 + * up to an arbitrary qemu_irq, so that when the device asserts that
 + * output GPIO line, the qemu_irq's callback is invoked.
 + * The @name string must correspond to an output GPIO array which exists on
 + * the device, and the index @n of the GPIO line must be valid (i.e.
 + * be at least 0 and less than the total number of input GPIOs in that
 + * array); this function will assert() if passed an invalid name or index.
 + *
 + * Outbound GPIO lines can be connected to any qemu_irq, but the common
 + * case is connecting them to another device's inbound GPIO line, using
 + * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named().
 + *
 + * It is not valid to try to connect one outbound GPIO to multiple
 + * qemu_irqs at once, or to connect multiple outbound GPIOs to the
 + * same qemu_irq; see qdev_connect_gpio_out() for details.
 + *
 + * For named output GPIO lines, use qdev_connect_gpio_out_named().
 + */
  void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
                                   qemu_irq pin);
 +/**
 + * qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO
 + * @dev: Device whose output GPIO we are interested in
 + * @name: Name of the output GPIO array
 + * @n: Number of the output GPIO line within that array
 + *
 + * Returns whatever qemu_irq is currently connected to the specified
 + * output GPIO line of @dev. This will be NULL if the output GPIO line
 + * has never been wired up to the anything.  Note that the qemu_irq
 + * returned does not belong to @dev -- it will be the input GPIO or
 + * IRQ of whichever device the board code has connected up to @dev's
 + * output GPIO.
 + *
 + * You probably don't need to use this function -- it is used only
 + * by the platform-bus subsystem.
 + */
  qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n);
 +/**
 + * qdev_intercept_gpio_out: Intercept an existing GPIO connection
 + * @dev: Device to intercept the outbound GPIO line from
 + * @icpt: New qemu_irq to connect instead
 + * @name: Name of the output GPIO array
 + * @n: Number of the GPIO line in the array
 + *
 + * This function is provided only for use by the qtest testing framework
 + * and is not suitable for use in non-testing parts of QEMU.
 + *
 + * This function breaks an existing connection of an outbound GPIO
 + * line from @dev, and replaces it with the new qemu_irq @icpt, as if
 + * ``qdev_connect_gpio_out_named(dev, icpt, name, n)`` had been called.
 + * The previously connected qemu_irq is returned, so it can be restored
 + * by a second call to qdev_intercept_gpio_out() if desired.
 + */
  qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt,
                                   const char *name, int n);
@@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name);
  /*** Device API.  ***/
 -/* Register device properties.  */
 -/* GPIO inputs also double as IRQ sinks.  */
 +/**
 + * qdev_init_gpio_in: create an array of anonymous input GPIO lines
 + * @dev: Device to create input GPIOs for
 + * @handler: Function to call when GPIO line value is set
 + * @n: Number of GPIO lines to create
 + *
 + * Devices should use functions in the qdev_init_gpio_in* family in
 + * their instance_init or realize methods to create any input GPIO
 + * lines they need. There is no functional difference between
 + * anonymous and named GPIO lines. Stylistically, named GPIOs are
 + * preferable (easier to understand at callsites) unless a device
 + * has exactly one uniform kind of GPIO input whose purpose is obvious.
 + * Note that input GPIO lines can serve as 'sinks' for IRQ lines.
 + *
 + * See qdev_get_gpio_in() for how code that uses such a device can get
 + * hold of an input GPIO line to manipulate it.
 + */
  void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n);
 +/**
 + * qdev_init_gpio_out: create an array of anonymous output GPIO lines
 + * @dev: Device to create output GPIOs for
 + * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines
 + * @n: Number of GPIO lines to create
 + *
 + * Devices should use functions in the qdev_init_gpio_out* family
 + * in their instance_init or realize methods to create any output
 + * GPIO lines they need. There is no functional difference between
 + * anonymous and named GPIO lines. Stylistically, named GPIOs are
 + * preferable (easier to understand at callsites) unless a device
 + * has exactly one uniform kind of GPIO output whose purpose is obvious.
 + *
 + * The @pins argument should be a pointer to either a "qemu_irq"
 + * (if @n == 1) or a "qemu_irq []" array (if @n > 1) in the device's
 + * state structure. The device implementation can then raise and
 + * lower the GPIO line by calling qemu_set_irq(). (If anything is
 + * connected to the other end of the GPIO this will cause the handler
 + * function for that input GPIO to be called.)
 + *
 + * See qdev_connect_gpio_out() for how code that uses such a device
 + * can connect to one of its output GPIO lines.
 + */
  void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n);
 +/**
 + * qdev_init_gpio_out: create an array of named output GPIO lines
 + * @dev: Device to create output GPIOs for
 + * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines
 + * @name: Name to give this array of GPIO lines
 + * @n: Number of GPIO lines to create
 + *
 + * Like qdev_init_gpio_out(), but creates an array of GPIO output lines
 + * with a name. Code using the device can then connect these GPIO lines
 + * using qdev_connect_gpio_out_named().
 + */
  void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins,
                                const char *name, int n);
  /**
-@@ -XXX,XX +XXX,XX @@ static inline void qdev_init_gpio_in_named(DeviceState *dev,
+  * qemu_timedate_diff: Return difference between a struct tm and the RTC
-     qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n);
+@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
   * a timestamp one hour further ahead than the current RTC time
   * then this function will return 3600.
   */
 -int qemu_timedate_diff(struct tm *tm);
 +time_t qemu_timedate_diff(struct tm *tm);
  #endif
 diff --git a/softmmu/rtc.c b/softmmu/rtc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/softmmu/rtc.c
 +++ b/softmmu/rtc.c
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
      return value;
  }
-+/**
+-void qemu_get_timedate(struct tm *tm, int offset)
-+ * qdev_pass_gpios: create GPIO lines on container which pass through to device
++void qemu_get_timedate(struct tm *tm, time_t offset)
-+ * @dev: Device which has GPIO lines
+ {
-+ * @container: Container device which needs to expose them
+     time_t ti = qemu_ref_timedate(rtc_clock);
-+ * @name: Name of GPIO array to pass through (NULL for the anonymous GPIO array)
-+ *
+@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
-+ * In QEMU, complicated devices like SoCs are often modelled with a
+     }
-+ * "container" QOM device which itself contains other QOM devices and
+ }
-+ * which wires them up appropriately. This function allows the container
-+ * to create GPIO arrays on itself which simply pass through to a GPIO
+-int qemu_timedate_diff(struct tm *tm)
-+ * array of one of its internal devices.
++time_t qemu_timedate_diff(struct tm *tm)
-+ *
+ {
-+ * If @dev has both input and output GPIOs named @name then both will
+     time_t seconds;
 + * be passed through. It is not possible to pass a subset of the array
 + * with this function.
 + *
 + * To users of the container device, the GPIO array created on @container
 + * behaves exactly like any other.
 + */
  void qdev_pass_gpios(DeviceState *dev, DeviceState *container,
                       const char *name);
 --
-.20.1
+.34.1

-New patch
+[PULL 22/24] target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
+Where architecturally one ARM_FEATURE_X flag implies another
 ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
 set Y for it.  Currently we do this in two places -- we set a few
 flags in arm_cpu_post_init() because we need them to decide which
 properties to create on the CPU object, and then we do the rest in
 arm_cpu_realizefn().  However, this is fragile, because it's easy to
 add a new property and not notice that this means that an X-implies-Y
 check now has to move from realize to post-init.
 As a specific example, the pmsav7-dregion property is conditional
 on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
 on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
 rely on V8-implies-V7, which doesn't happen until the realizefn.
 Move all of these X-implies-Y checks into a new function, which
 we call at the top of arm_cpu_post_init(), so the feature bits
 are available at that point.
 This does now give us the reverse issue, that if there's a feature
 bit which is enabled or disabled by the setting of a property then
 then X-implies-Y features that are dependent on that property need to
 be in realize, not in this new function.  But the only one of those
 is the "EL3 implies VBAR" which is already in the right place, so
 putting things this way round seems better to me.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
 ---
  target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
 file changed, 97 insertions(+), 82 deletions(-)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
        NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
  }
 +static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
 +{
 +    CPUARMState *env = &cpu->env;
 +    bool no_aa32 = false;
 +
 +    /*
 +     * Some features automatically imply others: set the feature
 +     * bits explicitly for these cases.
 +     */
 +
 +    if (arm_feature(env, ARM_FEATURE_M)) {
 +        set_feature(env, ARM_FEATURE_PMSA);
 +    }
 +
 +    if (arm_feature(env, ARM_FEATURE_V8)) {
 +        if (arm_feature(env, ARM_FEATURE_M)) {
 +            set_feature(env, ARM_FEATURE_V7);
 +        } else {
 +            set_feature(env, ARM_FEATURE_V7VE);
 +        }
 +    }
 +
 +    /*
 +     * There exist AArch64 cpus without AArch32 support.  When KVM
 +     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
 +     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
 +     * As a general principle, we also do not make ID register
 +     * consistency checks anywhere unless using TCG, because only
 +     * for TCG would a consistency-check failure be a QEMU bug.
 +     */
 +    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 +    }
 +
 +    if (arm_feature(env, ARM_FEATURE_V7VE)) {
 +        /*
 +         * v7 Virtualization Extensions. In real hardware this implies
 +         * EL2 and also the presence of the Security Extensions.
 +         * For QEMU, for backwards-compatibility we implement some
 +         * CPUs or CPU configs which have no actual EL2 or EL3 but do
 +         * include the various other features that V7VE implies.
 +         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 +         * Security Extensions is ARM_FEATURE_EL3.
 +         */
 +        assert(!tcg_enabled() || no_aa32 ||
 +               cpu_isar_feature(aa32_arm_div, cpu));
 +        set_feature(env, ARM_FEATURE_LPAE);
 +        set_feature(env, ARM_FEATURE_V7);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V7)) {
 +        set_feature(env, ARM_FEATURE_VAPA);
 +        set_feature(env, ARM_FEATURE_THUMB2);
 +        set_feature(env, ARM_FEATURE_MPIDR);
 +        if (!arm_feature(env, ARM_FEATURE_M)) {
 +            set_feature(env, ARM_FEATURE_V6K);
 +        } else {
 +            set_feature(env, ARM_FEATURE_V6);
 +        }
 +
 +        /*
 +         * Always define VBAR for V7 CPUs even if it doesn't exist in
 +         * non-EL3 configs. This is needed by some legacy boards.
 +         */
 +        set_feature(env, ARM_FEATURE_VBAR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V6K)) {
 +        set_feature(env, ARM_FEATURE_V6);
 +        set_feature(env, ARM_FEATURE_MVFR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V6)) {
 +        set_feature(env, ARM_FEATURE_V5);
 +        if (!arm_feature(env, ARM_FEATURE_M)) {
 +            assert(!tcg_enabled() || no_aa32 ||
 +                   cpu_isar_feature(aa32_jazelle, cpu));
 +            set_feature(env, ARM_FEATURE_AUXCR);
 +        }
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V5)) {
 +        set_feature(env, ARM_FEATURE_V4T);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_LPAE)) {
 +        set_feature(env, ARM_FEATURE_V7MP);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 +        set_feature(env, ARM_FEATURE_CBAR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 +        !arm_feature(env, ARM_FEATURE_M)) {
 +        set_feature(env, ARM_FEATURE_THUMB_DSP);
 +    }
 +}
 +
  void arm_cpu_post_init(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
 -    /* M profile implies PMSA. We have to do this here rather than
 -     * in realize with the other feature-implication checks because
 -     * we look at the PMSA bit to see if we should add some properties.
 +    /*
 +     * Some features imply others. Figure this out now, because we
 +     * are going to look at the feature bits in deciding which
 +     * properties to add.
       */
 -    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
 -        set_feature(&cpu->env, ARM_FEATURE_PMSA);
 -    }
 +    arm_cpu_propagate_feature_implications(cpu);
      if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
          arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
      CPUARMState *env = &cpu->env;
      int pagebits;
      Error *local_err = NULL;
 -    bool no_aa32 = false;
      /* Use pc-relative instructions in system-mode */
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          cpu->isar.id_isar3 = u;
      }
 -    /* Some features automatically imply others: */
 -    if (arm_feature(env, ARM_FEATURE_V8)) {
 -        if (arm_feature(env, ARM_FEATURE_M)) {
 -            set_feature(env, ARM_FEATURE_V7);
 -        } else {
 -            set_feature(env, ARM_FEATURE_V7VE);
 -        }
 -    }
 -
 -    /*
 -     * There exist AArch64 cpus without AArch32 support.  When KVM
 -     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
 -     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
 -     * As a general principle, we also do not make ID register
 -     * consistency checks anywhere unless using TCG, because only
 -     * for TCG would a consistency-check failure be a QEMU bug.
 -     */
 -    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 -        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 -    }
 -
 -    if (arm_feature(env, ARM_FEATURE_V7VE)) {
 -        /* v7 Virtualization Extensions. In real hardware this implies
 -         * EL2 and also the presence of the Security Extensions.
 -         * For QEMU, for backwards-compatibility we implement some
 -         * CPUs or CPU configs which have no actual EL2 or EL3 but do
 -         * include the various other features that V7VE implies.
 -         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 -         * Security Extensions is ARM_FEATURE_EL3.
 -         */
 -        assert(!tcg_enabled() || no_aa32 ||
 -               cpu_isar_feature(aa32_arm_div, cpu));
 -        set_feature(env, ARM_FEATURE_LPAE);
 -        set_feature(env, ARM_FEATURE_V7);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V7)) {
 -        set_feature(env, ARM_FEATURE_VAPA);
 -        set_feature(env, ARM_FEATURE_THUMB2);
 -        set_feature(env, ARM_FEATURE_MPIDR);
 -        if (!arm_feature(env, ARM_FEATURE_M)) {
 -            set_feature(env, ARM_FEATURE_V6K);
 -        } else {
 -            set_feature(env, ARM_FEATURE_V6);
 -        }
 -
 -        /* Always define VBAR for V7 CPUs even if it doesn't exist in
 -         * non-EL3 configs. This is needed by some legacy boards.
 -         */
 -        set_feature(env, ARM_FEATURE_VBAR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V6K)) {
 -        set_feature(env, ARM_FEATURE_V6);
 -        set_feature(env, ARM_FEATURE_MVFR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V6)) {
 -        set_feature(env, ARM_FEATURE_V5);
 -        if (!arm_feature(env, ARM_FEATURE_M)) {
 -            assert(!tcg_enabled() || no_aa32 ||
 -                   cpu_isar_feature(aa32_jazelle, cpu));
 -            set_feature(env, ARM_FEATURE_AUXCR);
 -        }
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V5)) {
 -        set_feature(env, ARM_FEATURE_V4T);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_LPAE)) {
 -        set_feature(env, ARM_FEATURE_V7MP);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 -        set_feature(env, ARM_FEATURE_CBAR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 -        !arm_feature(env, ARM_FEATURE_M)) {
 -        set_feature(env, ARM_FEATURE_THUMB_DSP);
 -    }
      /*
       * We rely on no XScale CPU having VFP so we can use the same bits in the
 --
 .34.1

-[PULL 06/12] qdev: Document qdev_unrealize()
+[PULL 23/24] hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
-Add a doc comment for qdev_unrealize(), to go with the new
+M-profile CPUs generally allow configuration of the number of MPU
-documentation for the realize part of the qdev lifecycle.
+regions that they have.  We don't currently model this, so our
 implementations of some of the board models provide CPUs with the
 wrong number of regions.  RTOSes like Zephyr that hardcode the
 expected number of regions may therefore not run on the model if they
 are set up to run on real hardware.
 Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
 matching the ability of hardware to configure the number of Secure
 and NonSecure regions separately.  Our actual CPU implementation
 doesn't currently support that, and it happens that none of the MPS
 boards we model set the number of regions differently for Secure vs
 NonSecure, so we provide an interface to the boards and SoCs that
 won't need to change if we ever do add that functionality in future,
 but make it an error to configure the two properties to different
 values.
 (The property name on the CPU is the somewhat misnamed-for-M-profile
 "pmsav7-dregion", so we don't follow that naming convention for
 the properties here. The TRM doesn't say what the CPU configuration
 variable names are, so we pick something, and follow the lowercase
 convention we already have for properties here.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20200711142425.16283-3-peter.maydell@linaro.org
+Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
 ---
- include/hw/qdev-core.h | 19 +++++++++++++++++++
+ include/hw/arm/armv7m.h |  8 ++++++++
-file changed, 19 insertions(+)
+ hw/arm/armv7m.c         | 21 +++++++++++++++++++++
 files changed, 29 insertions(+)
-diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
+diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/qdev-core.h
+--- a/include/hw/arm/armv7m.h
-+++ b/include/hw/qdev-core.h
++++ b/include/hw/arm/armv7m.h
-@@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
-  * would be incorrect. For that use case you want qdev_realize().
+  * + Property "vfp": enable VFP (forwarded to CPU object)
   * + Property "dsp": enable DSP (forwarded to CPU object)
   * + Property "enable-bitband": expose bitbanded IO
 + * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
 + *   to CPU object pmsav7-dregion property; default is whatever the default
 + *   for the CPU is)
 + * + Property "mpu-s-regions": number of Secure MPU regions (default is
 + *   whatever the default for the CPU is; must currently be set to the same
 + *   value as mpu-ns-regions if the CPU implements the Security Extension)
   * + Clock input "refclk" is the external reference clock for the systick timers
   * + Clock input "cpuclk" is the main CPU clock
   */
- bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
+@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
-+/**
+     Object *idau;
-+ * qdev_unrealize: Unrealize a device
+     uint32_t init_svtor;
-+ * @dev: device to unrealize
+     uint32_t init_nsvtor;
-+ *
++    uint32_t mpu_ns_regions;
-+ * This function will "unrealize" a device, which is the first phase
++    uint32_t mpu_s_regions;
-+ * of correctly destroying a device that has been realized. It will:
+     bool enable_bitband;
-+ *
+     bool start_powered_off;
-+ *  - unrealize any child buses by calling qbus_unrealize()
+     bool vfp;
-+ *    (this will recursively unrealize any devices on those buses)
+diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
-+ *  - call the the unrealize method of @dev
+index XXXXXXX..XXXXXXX 100644
-+ *
+--- a/hw/arm/armv7m.c
-+ * The device can then be freed by causing its reference count to go
++++ b/hw/arm/armv7m.c
-+ * to zero.
+@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
-+ *
+         }
-+ * Warning: most devices in QEMU do not expect to be unrealized.  Only
+     }
-+ * devices which are hot-unpluggable should be unrealized (as part of
-+ * the unplugging process); all other devices are expected to last for
++    /*
-+ * the life of the simulation and should not be unrealized and freed.
++     * Real M-profile hardware can be configured with a different number of
-+ */
++     * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
- void qdev_unrealize(DeviceState *dev);
++     * support that yet, so catch attempts to select that.
- void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
++     */
-                                  int required_for_version);
++    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
 +        s->mpu_ns_regions != s->mpu_s_regions) {
 +        error_setg(errp,
 +                   "mpu-ns-regions and mpu-s-regions properties must have the same value");
 +        return;
 +    }
 +    if (s->mpu_ns_regions != UINT_MAX &&
 +        object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
 +        if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
 +                                      s->mpu_ns_regions, errp)) {
 +            return;
 +        }
 +    }
 +
      /*
       * Tell the CPU where the NVIC is; it will fail realize if it doesn't
       * have one. Similarly, tell the NVIC where its CPU is.
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
                       false),
      DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
      DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
 +    DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
 +    DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
      DEFINE_PROP_END_OF_LIST(),
  };
 --
-.20.1
+.34.1

-[PULL 08/12] hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
+[PULL 24/24] hw/arm: Set number of MPU regions correctly for an505, an521, an524
-In armsse_realize() we have a loop over [0, info->num_cpus), which
+The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
-indexes into various fixed-size arrays in the ARMSSE struct.  This
+MPS2/MPS3 FPGA images don't override these except in the case of
-confuses Coverity, which warns that we might overrun those arrays
+AN547, which uses 16 MPU regions.
-(CID 1430326, 1430337, 1430371, 1430414, 1430430).  This can't
-actually happen, because the info struct is always one of the entries
+Define properties on the ARMSSE object for the MPU regions (using the
-in the armsse_variants[] array and num_cpus is either 1 or 2; we also
+same names as the documented RTL configuration settings, and
-already assert in armsse_init() that num_cpus is not too large.
+following the pattern we already have for this device of using
-However, adding an assert to armsse_realize() like the one in
+all-caps names as the RTL does), and set them in the board code.
-armsse_init() should help Coverity figure out that these code paths
-aren't possible.
+We don't actually need to override the default except on AN547,
+but it's simpler code to have the board code set them always
 rather than tracking which board subtypes want to set them to
 a non-default value separately from what that value is.
 Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
 we now correctly use 8 MPU regions, while mps3-an547 stays at its
 current 16 regions.
 It's possible some guest code wrongly depended on the previous
 incorrectly modeled number of memory regions. (Such guest code
 should ideally check the number of regions via the MPU_TYPE
 register.) The old behaviour can be obtained with additional
 -global arguments to QEMU:
 For mps2-an521 and mps2-an524:
  -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16
 For mps2-an505:
  -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16
 NB that the way the implementation allows this use of -global
 is slightly fragile: if the board code explicitly sets the
 properties on the sse-200 object, this overrides the -global
 command line option. So we rely on:
  - the boards that need fixing all happen to use the SSE defaults
  - we can write the board code to only set the property if it
    is different from the default, rather than having all boards
    explicitly set the property
  - the board that does need to use a non-default value happens
    to need to set it to the same value (16) we previously used
 This works, but there are some kinds of refactoring of the
 mps2-tz.c code that would break the support for -global here.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200713143716.9881-1-peter.maydell@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
 ---
- hw/arm/armsse.c | 2 ++
+ include/hw/arm/armsse.h |  5 +++++
-file changed, 2 insertions(+)
+ hw/arm/armsse.c         | 16 ++++++++++++++++
+ hw/arm/mps2-tz.c        | 29 +++++++++++++++++++++++++++++
 files changed, 50 insertions(+)
 diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/armsse.h
 +++ b/include/hw/arm/armsse.h
@@ -XXX,XX +XXX,XX @@
   *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
   *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
   *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
 + *  + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
 + *    which set the number of MPU regions on the CPUs. If there is only one
 + *    CPU the CPU1 properties are not present.
   *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
   *    which are wired to its NVIC lines 32 .. n+32
   *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
      uint32_t exp_numirq;
      uint32_t sram_addr_width;
      uint32_t init_svtor;
 +    uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
 +    uint32_t cpu_mpu_s[SSE_MAX_CPUS];
      bool cpu_fpu[SSE_MAX_CPUS];
      bool cpu_dsp[SSE_MAX_CPUS];
  };
 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/armsse.c
 +++ b/hw/arm/armsse.c
+@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
+     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
+     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
+     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
++    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
++    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
+     DEFINE_PROP_END_OF_LIST()
+ };
+@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
+     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
+     DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
+     DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
++    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
++    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
++    DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
++    DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
+     DEFINE_PROP_END_OF_LIST()
+ };
+@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
+     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
+     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
+     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
++    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
++    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
+     DEFINE_PROP_END_OF_LIST()
+ };
 @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
-         return;
+                 return;
-     }
+             }
+         }
-+    assert(info->num_cpus <= SSE_MAX_CPUS);
++        if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
 +                                      s->cpu_mpu_ns[i], errp)) {
 +            return;
 +        }
 +        if (!object_property_set_uint(cpuobj, "mpu-s-regions",
 +                                      s->cpu_mpu_s[i], errp)) {
 +            return;
 +        }
          if (i > 0) {
              memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/mps2-tz.c
 +++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
      int uart_overflow_irq; /* number of the combined UART overflow IRQ */
      uint32_t init_svtor; /* init-svtor setting for SSE */
      uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
 +    uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
 +    uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
 +    uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
 +    uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
      const RAMInfo *raminfo;
      const char *armsse_type;
      uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
  #define MPS3_DDR_SIZE (2 * GiB)
  #endif
 +/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
 +#define MPU_REGION_DEFAULT UINT32_MAX
 +
-     /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
+ static const uint32_t an505_oscclk[] = {
-     assert(is_power_of_2(info->sram_banks));
+     40000000,
-     addr_width_max = 24 - ctz32(info->sram_banks);
+     24580000,
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                               OBJECT(system_memory), &error_abort);
      qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
      qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
 +    if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
 +        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
 +    }
 +    if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
 +        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
 +    }
 +    if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
 +        if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
 +            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
 +        }
 +        if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
 +            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
 +        }
 +    }
      qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
      qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
      qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
      IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
 +    MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
      mc->init = mps2tz_common_init;
      mc->reset = mps2_machine_reset;
      iic->check = mps2_tz_idau_check;
 +
 +    /* Most machines leave these at the SSE defaults */
 +    mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
 +    mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
 +    mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
 +    mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
  }
  static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
      mmc->numirq = 96;
      mmc->uart_overflow_irq = 48;
      mmc->init_svtor = 0x00000000;
 +    mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
      mmc->sram_addr_width = 21;
      mmc->raminfo = an547_raminfo;
      mmc->armsse_type = TYPE_SSE300;
 --
-.20.1
+.34.1

Not much here, mostly documentation, but a few bug fixes.

thanks
-- PMM

The following changes since commit 873ec69aeb12e24eec7fb317fd0cd8494e8489dd:

Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging (2020-07-20 11:03:09 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200720

for you to fetch changes up to 6a0b7505f1fd6769c3f1558fda76464d51e4118a:

docs/system: Document the arm virt board (2020-07-20 11:35:17 +0100)

----------------------------------------------------------------
target-arm queue:
 * virt: Don't enable MTE emulation by default
 * virt: Diagnose attempts to use MTE with memory-hotplug or KVM
   (rather than silently not working correctly)
 * util: Implement qemu_get_thread_id() for OpenBSD
 * qdev: Add doc comments for qdev_unrealize and GPIO functions,
   and standardize on doc-comments-in-header-file
 * hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
 * docs/system: Document canon-a1100, collie, gumstix, virt boards

----------------------------------------------------------------
David CARLIER (1):
      util: Implement qemu_get_thread_id() for OpenBSD

Peter Maydell (8):
      qdev: Move doc comments from qdev.c to qdev-core.h
      qdev: Document qdev_unrealize()
      qdev: Document GPIO related functions
      hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
      docs/system: Briefly document canon-a1100 board
      docs/system: Briefly document collie board
      docs/system: Briefly document gumstix boards
      docs/system: Document the arm virt board

Richard Henderson (3):
      hw/arm/virt: Enable MTE via a machine property
      hw/arm/virt: Error for MTE enabled with KVM
      hw/arm/virt: Disable memory hotplug when MTE is enabled

docs/system/arm/collie.rst   |  16 +++
 docs/system/arm/digic.rst    |  11 ++
 docs/system/arm/gumstix.rst  |  21 ++++
 docs/system/arm/virt.rst     | 161 ++++++++++++++++++++++++++
 docs/system/target-arm.rst   |   4 +
 include/hw/arm/virt.h        |   1 +
 include/hw/qdev-core.h       | 267 ++++++++++++++++++++++++++++++++++++++++++-
 include/hw/qdev-properties.h |  13 +++
 hw/arm/armsse.c              |   2 +
 hw/arm/virt.c                |  50 +++++++-
 hw/core/qdev.c               |  33 ------
 target/arm/cpu.c             |  19 +--
 target/arm/cpu64.c           |   5 +-
 util/oslib-posix.c           |   2 +
 MAINTAINERS                  |   4 +
 15 files changed, 559 insertions(+), 50 deletions(-)
 create mode 100644 docs/system/arm/collie.rst
 create mode 100644 docs/system/arm/digic.rst
 create mode 100644 docs/system/arm/gumstix.rst
 create mode 100644 docs/system/arm/virt.rst

From: Richard Henderson <richard.henderson@linaro.org>

Control this cpu feature via a machine property, much as we do
with secure=on, since both require specialized support in the
machine setup to be functional.

Default MTE to off, since this feature implies extra overhead.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200713213341.590275-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/virt.h |  1 +
 hw/arm/virt.c         | 39 ++++++++++++++++++++++++++++++++++-----
 target/arm/cpu.c      | 19 +++++++++++--------
 target/arm/cpu64.c    |  5 +++--
 4 files changed, 49 insertions(+), 15 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
     bool its;
     bool virt;
     bool ras;
+    bool mte;
     OnOffAuto acpi;
     VirtGICType gic_version;
     VirtIOMMUType iommu;
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
                                      OBJECT(secure_sysmem), &error_abort);
         }
 
-        /*
-         * The cpu adds the property if and only if MemTag is supported.
-         * If it is, we must allocate the ram to back that up.
-         */
-        if (object_property_find(cpuobj, "tag-memory", NULL)) {
+        if (vms->mte) {
+            /* Create the memory region only once, but link to all cpus. */
             if (!tag_sysmem) {
+                /*
+                 * The property exists only if MemTag is supported.
+                 * If it is, we must allocate the ram to back that up.
+                 */
+                if (!object_property_find(cpuobj, "tag-memory", NULL)) {
+                    error_report("MTE requested, but not supported "
+                                 "by the guest CPU");
+                    exit(1);
+                }
+
                 tag_sysmem = g_new(MemoryRegion, 1);
                 memory_region_init(tag_sysmem, OBJECT(machine),
                                    "tag-memory", UINT64_MAX / 32);
@@ -XXX,XX +XXX,XX @@ static void virt_set_ras(Object *obj, bool value, Error **errp)
     vms->ras = value;
 }
 
+static bool virt_get_mte(Object *obj, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    return vms->mte;
+}
+
+static void virt_set_mte(Object *obj, bool value, Error **errp)
+{
+    VirtMachineState *vms = VIRT_MACHINE(obj);
+
+    vms->mte = value;
+}
+
 static char *virt_get_gic_version(Object *obj, Error **errp)
 {
     VirtMachineState *vms = VIRT_MACHINE(obj);
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
                                     "Set on/off to enable/disable reporting host memory errors "
                                     "to a KVM guest using ACPI and guest external abort exceptions");
 
+    /* MTE is disabled by default.  */
+    vms->mte = false;
+    object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte);
+    object_property_set_description(obj, "mte",
+                                    "Set on/off to enable/disable emulating a "
+                                    "guest CPU which implements the ARM "
+                                    "Memory Tagging Extension");
+
     vms->irqmap = a15irqmap;
 
     virt_flash_create(vms);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         cpu->id_pfr1 &= ~0xf000;
     }
 
+#ifndef CONFIG_USER_ONLY
+    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
+        /*
+         * Disable the MTE feature bits if we do not have tag-memory
+         * provided by the machine.
+         */
+        cpu->isar.id_aa64pfr1 =
+            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+    }
+#endif
+
     /* MPU can be configured out of a PMSA CPU either by setting has-mpu
      * to false or by setting pmsav7-dregion to 0.
      */
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
             cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
                                    cpu->secure_tag_memory);
         }
-    } else if (cpu_isar_feature(aa64_mte, cpu)) {
-        /*
-         * Since there is no tag memory, we can't meaningfully support MTE
-         * to its fullest.  To avoid problems later, when we would come to
-         * use the tag memory, downgrade support to insns only.
-         */
-        cpu->isar.id_aa64pfr1 =
-            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
     }
 
     cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         t = cpu->isar.id_aa64pfr1;
         t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
         /*
-         * Begin with full support for MTE; will be downgraded to MTE=1
-         * during realize if the board provides no tag memory.
+         * Begin with full support for MTE. This will be downgraded to MTE=0
+         * during realize if the board provides no tag memory, much like
+         * we do for EL2 with the virtualization=on property.
          */
         t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
         cpu->isar.id_aa64pfr1 = t;
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

When MTE is enabled, tag memory must exist for all RAM.

It might be possible to simultaneously hot plug tag memory
alongside the corresponding normal memory, but for now just
disable hotplug.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200713213341.590275-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
         return;
     }
 
+    if (vms->mte) {
+        error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
+        return;
+    }
+
     if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
         error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
         return;
-- 
2.20.1

The doc-comments which document the qdev API are split between the
header file and the C source files, because as a project we haven't
been consistent about where we put them.

Move all the doc-comments in qdev.c to the header files, so that
users of the APIs don't have to look at the implementation files for
this information.

In the process, unify them into our doc-comment format and expand on
them in some cases to clarify expected use cases.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200711142425.16283-2-peter.maydell@linaro.org
---
 include/hw/qdev-core.h       | 57 ++++++++++++++++++++++++++++++++++++
 include/hw/qdev-properties.h | 13 ++++++++
 hw/core/qdev.c               | 33 ---------------------
 3 files changed, 70 insertions(+), 33 deletions(-)

diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -XXX,XX +XXX,XX @@ compat_props_add(GPtrArray *arr,
 
 /*** Board API.  This should go away once we have a machine config file.  ***/
 
+/**
+ * qdev_new: Create a device on the heap
+ * @name: device type to create (we assert() that this type exists)
+ *
+ * This only allocates the memory and initializes the device state
+ * structure, ready for the caller to set properties if they wish.
+ * The device still needs to be realized.
+ * The returned object has a reference count of 1.
+ */
 DeviceState *qdev_new(const char *name);
+/**
+ * qdev_try_new: Try to create a device on the heap
+ * @name: device type to create
+ *
+ * This is like qdev_new(), except it returns %NULL when type @name
+ * does not exist, rather than asserting.
+ */
 DeviceState *qdev_try_new(const char *name);
+/**
+ * qdev_realize: Realize @dev.
+ * @dev: device to realize
+ * @bus: bus to plug it into (may be NULL)
+ * @errp: pointer to error object
+ *
+ * "Realize" the device, i.e. perform the second phase of device
+ * initialization.
+ * @dev must not be plugged into a bus already.
+ * If @bus, plug @dev into @bus.  This takes a reference to @dev.
+ * If @dev has no QOM parent, make one up, taking another reference.
+ * On success, return true.
+ * On failure, store an error through @errp and return false.
+ *
+ * If you created @dev using qdev_new(), you probably want to use
+ * qdev_realize_and_unref() instead.
+ */
 bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
+/**
+ * qdev_realize_and_unref: Realize @dev and drop a reference
+ * @dev: device to realize
+ * @bus: bus to plug it into (may be NULL)
+ * @errp: pointer to error object
+ *
+ * Realize @dev and drop a reference.
+ * This is like qdev_realize(), except the caller must hold a
+ * (private) reference, which is dropped on return regardless of
+ * success or failure.  Intended use::
+ *
+ *     dev = qdev_new();
+ *     [...]
+ *     qdev_realize_and_unref(dev, bus, errp);
+ *
+ * Now @dev can go away without further ado.
+ *
+ * If you are embedding the device into some other QOM device and
+ * initialized it via some variant on object_initialize_child() then
+ * do not use this function, because that family of functions arrange
+ * for the only reference to the child device to be held by the parent
+ * via the child<> property, and so the reference-count-drop done here
+ * would be incorrect. For that use case you want qdev_realize().
+ */
 bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
 void qdev_unrealize(DeviceState *dev);
 void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -XXX,XX +XXX,XX @@ void error_set_from_qdev_prop_error(Error **errp, int ret, DeviceState *dev,
  */
 void qdev_property_add_static(DeviceState *dev, Property *prop);
 
+/**
+ * qdev_alias_all_properties: Create aliases on source for all target properties
+ * @target: Device which has properties to be aliased
+ * @source: Object to add alias properties to
+ *
+ * Add alias properties to the @source object for all qdev properties on
+ * the @target DeviceState.
+ *
+ * This is useful when @target is an internal implementation object
+ * owned by @source, and you want to expose all the properties of that
+ * implementation object as properties on the @source object so that users
+ * of @source can set them.
+ */
 void qdev_alias_all_properties(DeviceState *target, Object *source);
 
 /**
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/qdev.c
+++ b/hw/core/qdev.c
@@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
     }
 }
 
-/*
- * Create a device on the heap.
- * A type @name must exist.
- * This only initializes the device state structure and allows
- * properties to be set.  The device still needs to be realized.  See
- * qdev-core.h.
- */
 DeviceState *qdev_new(const char *name)
 {
     if (!object_class_by_name(name)) {
@@ -XXX,XX +XXX,XX @@ DeviceState *qdev_new(const char *name)
     return DEVICE(object_new(name));
 }
 
-/*
- * Try to create a device on the heap.
- * This is like qdev_new(), except it returns %NULL when type @name
- * does not exist.
- */
 DeviceState *qdev_try_new(const char *name)
 {
     if (!module_object_class_by_name(name)) {
@@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
     qdev_unrealize(dev);
 }
 
-/*
- * Realize @dev.
- * @dev must not be plugged into a bus.
- * If @bus, plug @dev into @bus.  This takes a reference to @dev.
- * If @dev has no QOM parent, make one up, taking another reference.
- * On success, return true.
- * On failure, store an error through @errp and return false.
- */
 bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
 {
     assert(!dev->realized && !dev->parent_bus);
@@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
     return object_property_set_bool(OBJECT(dev), "realized", true, errp);
 }
 
-/*
- * Realize @dev and drop a reference.
- * This is like qdev_realize(), except the caller must hold a
- * (private) reference, which is dropped on return regardless of
- * success or failure.  Intended use:
- *     dev = qdev_new();
- *     [...]
- *     qdev_realize_and_unref(dev, bus, errp);
- * Now @dev can go away without further ado.
- */
 bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp)
 {
     bool ret;
@@ -XXX,XX +XXX,XX @@ static void qdev_class_add_property(DeviceClass *klass, Property *prop)
                                           prop->info->description);
 }
 
-/* @qdev_alias_all_properties - Add alias properties to the source object for
- * all qdev properties on the target DeviceState.
- */
 void qdev_alias_all_properties(DeviceState *target, Object *source)
 {
     ObjectClass *class;
-- 
2.20.1

Add a doc comment for qdev_unrealize(), to go with the new
documentation for the realize part of the qdev lifecycle.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200711142425.16283-3-peter.maydell@linaro.org
---
 include/hw/qdev-core.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
  * would be incorrect. For that use case you want qdev_realize().
  */
 bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
+/**
+ * qdev_unrealize: Unrealize a device
+ * @dev: device to unrealize
+ *
+ * This function will "unrealize" a device, which is the first phase
+ * of correctly destroying a device that has been realized. It will:
+ *
+ *  - unrealize any child buses by calling qbus_unrealize()
+ *    (this will recursively unrealize any devices on those buses)
+ *  - call the the unrealize method of @dev
+ *
+ * The device can then be freed by causing its reference count to go
+ * to zero.
+ *
+ * Warning: most devices in QEMU do not expect to be unrealized.  Only
+ * devices which are hot-unpluggable should be unrealized (as part of
+ * the unplugging process); all other devices are expected to last for
+ * the life of the simulation and should not be unrealized and freed.
+ */
 void qdev_unrealize(DeviceState *dev);
 void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
                                  int required_for_version);
-- 
2.20.1

Add documentation comments for the various qdev functions
related to creating and connecting GPIO lines.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200711142425.16283-4-peter.maydell@linaro.org
---
 include/hw/qdev-core.h | 191 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 189 insertions(+), 2 deletions(-)

diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/qdev-core.h
+++ b/include/hw/qdev-core.h
@@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
 void qdev_machine_creation_done(void);
 bool qdev_machine_modified(void);
 
+/**
+ * qdev_get_gpio_in: Get one of a device's anonymous input GPIO lines
+ * @dev: Device whose GPIO we want
+ * @n: Number of the anonymous GPIO line (which must be in range)
+ *
+ * Returns the qemu_irq corresponding to an anonymous input GPIO line
+ * (which the device has set up with qdev_init_gpio_in()). The index
+ * @n of the GPIO line must be valid (i.e. be at least 0 and less than
+ * the total number of anonymous input GPIOs the device has); this
+ * function will assert() if passed an invalid index.
+ *
+ * This function is intended to be used by board code or SoC "container"
+ * device models to wire up the GPIO lines; usually the return value
+ * will be passed to qdev_connect_gpio_out() or a similar function to
+ * connect another device's output GPIO line to this input.
+ *
+ * For named input GPIO lines, use qdev_get_gpio_in_named().
+ */
 qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);
+/**
+ * qdev_get_gpio_in_named: Get one of a device's named input GPIO lines
+ * @dev: Device whose GPIO we want
+ * @name: Name of the input GPIO array
+ * @n: Number of the GPIO line in that array (which must be in range)
+ *
+ * Returns the qemu_irq corresponding to a named input GPIO line
+ * (which the device has set up with qdev_init_gpio_in_named()).
+ * The @name string must correspond to an input GPIO array which exists on
+ * the device, and the index @n of the GPIO line must be valid (i.e.
+ * be at least 0 and less than the total number of input GPIOs in that
+ * array); this function will assert() if passed an invalid name or index.
+ *
+ * For anonymous input GPIO lines, use qdev_get_gpio_in().
+ */
 qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n);
 
+/**
+ * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
+ * @dev: Device whose GPIO to connect
+ * @n: Number of the anonymous output GPIO line (which must be in range)
+ * @pin: qemu_irq to connect the output line to
+ *
+ * This function connects an anonymous output GPIO line on a device
+ * up to an arbitrary qemu_irq, so that when the device asserts that
+ * output GPIO line, the qemu_irq's callback is invoked.
+ * The index @n of the GPIO line must be valid (i.e. be at least 0 and
+ * less than the total number of anonymous output GPIOs the device has
+ * created with qdev_init_gpio_out()); otherwise this function will assert().
+ *
+ * Outbound GPIO lines can be connected to any qemu_irq, but the common
+ * case is connecting them to another device's inbound GPIO line, using
+ * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named().
+ *
+ * It is not valid to try to connect one outbound GPIO to multiple
+ * qemu_irqs at once, or to connect multiple outbound GPIOs to the
+ * same qemu_irq. (Warning: there is no assertion or other guard to
+ * catch this error: the model will just not do the right thing.)
+ * Instead, for fan-out you can use the TYPE_IRQ_SPLIT device: connect
+ * a device's outbound GPIO to the splitter's input, and connect each
+ * of the splitter's outputs to a different device.  For fan-in you
+ * can use the TYPE_OR_IRQ device, which is a model of a logical OR
+ * gate with multiple inputs and one output.
+ *
+ * For named output GPIO lines, use qdev_connect_gpio_out_named().
+ */
 void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin);
+/**
+ * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
+ * @dev: Device whose GPIO to connect
+ * @name: Name of the output GPIO array
+ * @n: Number of the anonymous output GPIO line (which must be in range)
+ * @pin: qemu_irq to connect the output line to
+ *
+ * This function connects an anonymous output GPIO line on a device
+ * up to an arbitrary qemu_irq, so that when the device asserts that
+ * output GPIO line, the qemu_irq's callback is invoked.
+ * The @name string must correspond to an output GPIO array which exists on
+ * the device, and the index @n of the GPIO line must be valid (i.e.
+ * be at least 0 and less than the total number of input GPIOs in that
+ * array); this function will assert() if passed an invalid name or index.
+ *
+ * Outbound GPIO lines can be connected to any qemu_irq, but the common
+ * case is connecting them to another device's inbound GPIO line, using
+ * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named().
+ *
+ * It is not valid to try to connect one outbound GPIO to multiple
+ * qemu_irqs at once, or to connect multiple outbound GPIOs to the
+ * same qemu_irq; see qdev_connect_gpio_out() for details.
+ *
+ * For named output GPIO lines, use qdev_connect_gpio_out_named().
+ */
 void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
                                  qemu_irq pin);
+/**
+ * qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO
+ * @dev: Device whose output GPIO we are interested in
+ * @name: Name of the output GPIO array
+ * @n: Number of the output GPIO line within that array
+ *
+ * Returns whatever qemu_irq is currently connected to the specified
+ * output GPIO line of @dev. This will be NULL if the output GPIO line
+ * has never been wired up to the anything.  Note that the qemu_irq
+ * returned does not belong to @dev -- it will be the input GPIO or
+ * IRQ of whichever device the board code has connected up to @dev's
+ * output GPIO.
+ *
+ * You probably don't need to use this function -- it is used only
+ * by the platform-bus subsystem.
+ */
 qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n);
+/**
+ * qdev_intercept_gpio_out: Intercept an existing GPIO connection
+ * @dev: Device to intercept the outbound GPIO line from
+ * @icpt: New qemu_irq to connect instead
+ * @name: Name of the output GPIO array
+ * @n: Number of the GPIO line in the array
+ *
+ * This function is provided only for use by the qtest testing framework
+ * and is not suitable for use in non-testing parts of QEMU.
+ *
+ * This function breaks an existing connection of an outbound GPIO
+ * line from @dev, and replaces it with the new qemu_irq @icpt, as if
+ * ``qdev_connect_gpio_out_named(dev, icpt, name, n)`` had been called.
+ * The previously connected qemu_irq is returned, so it can be restored
+ * by a second call to qdev_intercept_gpio_out() if desired.
+ */
 qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt,
                                  const char *name, int n);
 
@@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name);
 
 /*** Device API.  ***/
 
-/* Register device properties.  */
-/* GPIO inputs also double as IRQ sinks.  */
+/**
+ * qdev_init_gpio_in: create an array of anonymous input GPIO lines
+ * @dev: Device to create input GPIOs for
+ * @handler: Function to call when GPIO line value is set
+ * @n: Number of GPIO lines to create
+ *
+ * Devices should use functions in the qdev_init_gpio_in* family in
+ * their instance_init or realize methods to create any input GPIO
+ * lines they need. There is no functional difference between
+ * anonymous and named GPIO lines. Stylistically, named GPIOs are
+ * preferable (easier to understand at callsites) unless a device
+ * has exactly one uniform kind of GPIO input whose purpose is obvious.
+ * Note that input GPIO lines can serve as 'sinks' for IRQ lines.
+ *
+ * See qdev_get_gpio_in() for how code that uses such a device can get
+ * hold of an input GPIO line to manipulate it.
+ */
 void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n);
+/**
+ * qdev_init_gpio_out: create an array of anonymous output GPIO lines
+ * @dev: Device to create output GPIOs for
+ * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines
+ * @n: Number of GPIO lines to create
+ *
+ * Devices should use functions in the qdev_init_gpio_out* family
+ * in their instance_init or realize methods to create any output
+ * GPIO lines they need. There is no functional difference between
+ * anonymous and named GPIO lines. Stylistically, named GPIOs are
+ * preferable (easier to understand at callsites) unless a device
+ * has exactly one uniform kind of GPIO output whose purpose is obvious.
+ *
+ * The @pins argument should be a pointer to either a "qemu_irq"
+ * (if @n == 1) or a "qemu_irq []" array (if @n > 1) in the device's
+ * state structure. The device implementation can then raise and
+ * lower the GPIO line by calling qemu_set_irq(). (If anything is
+ * connected to the other end of the GPIO this will cause the handler
+ * function for that input GPIO to be called.)
+ *
+ * See qdev_connect_gpio_out() for how code that uses such a device
+ * can connect to one of its output GPIO lines.
+ */
 void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n);
+/**
+ * qdev_init_gpio_out: create an array of named output GPIO lines
+ * @dev: Device to create output GPIOs for
+ * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines
+ * @name: Name to give this array of GPIO lines
+ * @n: Number of GPIO lines to create
+ *
+ * Like qdev_init_gpio_out(), but creates an array of GPIO output lines
+ * with a name. Code using the device can then connect these GPIO lines
+ * using qdev_connect_gpio_out_named().
+ */
 void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins,
                               const char *name, int n);
 /**
@@ -XXX,XX +XXX,XX @@ static inline void qdev_init_gpio_in_named(DeviceState *dev,
     qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n);
 }
 
+/**
+ * qdev_pass_gpios: create GPIO lines on container which pass through to device
+ * @dev: Device which has GPIO lines
+ * @container: Container device which needs to expose them
+ * @name: Name of GPIO array to pass through (NULL for the anonymous GPIO array)
+ *
+ * In QEMU, complicated devices like SoCs are often modelled with a
+ * "container" QOM device which itself contains other QOM devices and
+ * which wires them up appropriately. This function allows the container
+ * to create GPIO arrays on itself which simply pass through to a GPIO
+ * array of one of its internal devices.
+ *
+ * If @dev has both input and output GPIOs named @name then both will
+ * be passed through. It is not possible to pass a subset of the array
+ * with this function.
+ *
+ * To users of the container device, the GPIO array created on @container
+ * behaves exactly like any other.
+ */
 void qdev_pass_gpios(DeviceState *dev, DeviceState *container,
                      const char *name);
 
-- 
2.20.1

In armsse_realize() we have a loop over [0, info->num_cpus), which
indexes into various fixed-size arrays in the ARMSSE struct.  This
confuses Coverity, which warns that we might overrun those arrays
(CID 1430326, 1430337, 1430371, 1430414, 1430430).  This can't
actually happen, because the info struct is always one of the entries
in the armsse_variants[] array and num_cpus is either 1 or 2; we also
already assert in armsse_init() that num_cpus is not too large.
However, adding an assert to armsse_realize() like the one in
armsse_init() should help Coverity figure out that these code paths
aren't possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200713143716.9881-1-peter.maydell@linaro.org
---
 hw/arm/armsse.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    assert(info->num_cpus <= SSE_MAX_CPUS);
+
     /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
     assert(is_power_of_2(info->sram_banks));
     addr_width_max = 24 - ctz32(info->sram_banks);
-- 
2.20.1

Add skeletal documentation of the canon-a1100 board.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200713175746.5936-2-peter.maydell@linaro.org
---
 docs/system/arm/digic.rst  | 11 +++++++++++
 docs/system/target-arm.rst |  1 +
 MAINTAINERS                |  1 +
 3 files changed, 13 insertions(+)
 create mode 100644 docs/system/arm/digic.rst

diff --git a/docs/system/arm/digic.rst b/docs/system/arm/digic.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/arm/digic.rst
@@ -XXX,XX +XXX,XX @@
+Canon A1100 (``canon-a1100``)
+=============================
+
+This machine is a model of the Canon PowerShot A1100 camera, which
+uses the DIGIC SoC. This model is based on reverse engineering efforts
+by the contributors to the `CHDK <http://chdk.wikia.com/>`_ and
+`Magic Lantern <http://www.magiclantern.fm/>`_ projects.
+
+The emulation is incomplete. In particular it can't be used
+to run the original camera firmware, but it can successfully run
+an experimental version of the `barebox bootloader <http://www.barebox.org/>`_.
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    arm/versatile
    arm/vexpress
    arm/aspeed
+   arm/digic
    arm/musicpal
    arm/nseries
    arm/orangepi
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/digic.h
 F: hw/*/digic*
 F: include/hw/*/digic*
 F: tests/acceptance/machine_arm_canona1100.py
+F: docs/system/arm/digic.rst
 
 Goldfish RTC
 M: Anup Patel <anup.patel@wdc.com>
-- 
2.20.1

Add skeletal documentation of the collie board.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200713175746.5936-3-peter.maydell@linaro.org
---
 docs/system/arm/collie.rst | 16 ++++++++++++++++
 docs/system/target-arm.rst |  1 +
 MAINTAINERS                |  1 +
 3 files changed, 18 insertions(+)
 create mode 100644 docs/system/arm/collie.rst

diff --git a/docs/system/arm/collie.rst b/docs/system/arm/collie.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/arm/collie.rst
@@ -XXX,XX +XXX,XX @@
+Sharp Zaurus SL-5500 (``collie``)
+=================================
+
+This machine is a model of the Sharp Zaurus SL-5500, which was
+a 1990s PDA based on the StrongARM SA1110.
+
+Implemented devices:
+
+ * NOR flash
+ * Interrupt controller
+ * Timer
+ * RTC
+ * GPIO
+ * Peripheral Pin Controller (PPC)
+ * UARTs
+ * Synchronous Serial Ports (SSP)
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    arm/orangepi
    arm/palm
    arm/xscale
+   arm/collie
    arm/sx1
    arm/stellaris
 
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Odd Fixes
 F: hw/arm/collie.c
 F: hw/arm/strongarm*
+F: docs/system/arm/collie.rst
 
 Stellaris
 M: Peter Maydell <peter.maydell@linaro.org>
-- 
2.20.1

Add skeletal documentation of the gumstix boards
('connex' and 'verdex').

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200713175746.5936-4-peter.maydell@linaro.org
---
 docs/system/arm/gumstix.rst | 21 +++++++++++++++++++++
 docs/system/target-arm.rst  |  1 +
 MAINTAINERS                 |  1 +
 3 files changed, 23 insertions(+)
 create mode 100644 docs/system/arm/gumstix.rst

diff --git a/docs/system/arm/gumstix.rst b/docs/system/arm/gumstix.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/arm/gumstix.rst
@@ -XXX,XX +XXX,XX @@
+Gumstix Connex and Verdex (``connex``, ``verdex``)
+==================================================
+
+These machines model the Gumstix Connex and Verdex boards.
+The Connex has a PXA255 CPU and the Verdex has a PXA270.
+
+Implemented devices:
+
+ * NOR flash
+ * SMC91C111 ethernet
+ * Interrupt controller
+ * DMA
+ * Timer
+ * GPIO
+ * MMC/SD card
+ * Fast infra-red communications port (FIR)
+ * LCD controller
+ * Synchronous serial ports (SPI)
+ * PCMCIA interface
+ * I2C
+ * I2S
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    arm/aspeed
    arm/digic
    arm/musicpal
+   arm/gumstix
    arm/nseries
    arm/orangepi
    arm/palm
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ R: Philippe Mathieu-Daudé <f4bug@amsat.org>
 L: qemu-arm@nongnu.org
 S: Odd Fixes
 F: hw/arm/gumstix.c
+F: docs/system/arm/gumstix.rst
 
 i.MX25 PDK
 M: Peter Maydell <peter.maydell@linaro.org>
-- 
2.20.1

Document the arm 'virt' board, which has been undocumented
for far too long given that it is the main recommended board
type for arm guests.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200713175746.5936-5-peter.maydell@linaro.org
---
 docs/system/arm/virt.rst   | 161 +++++++++++++++++++++++++++++++++++++
 docs/system/target-arm.rst |   1 +
 MAINTAINERS                |   1 +
 3 files changed, 163 insertions(+)
 create mode 100644 docs/system/arm/virt.rst

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/arm/virt.rst
@@ -XXX,XX +XXX,XX @@
+'virt' generic virtual platform (``virt``)
+==========================================
+
+The `virt` board is a platform which does not correspond to any
+real hardware; it is designed for use in virtual machines.
+It is the recommended board type if you simply want to run
+a guest such as Linux and do not care about reproducing the
+idiosyncrasies and limitations of a particular bit of real-world
+hardware.
+
+This is a "versioned" board model, so as well as the ``virt`` machine
+type itself (which may have improvements, bugfixes and other minor
+changes between QEMU versions) a version is provided that guarantees
+to have the same behaviour as that of previous QEMU releases, so
+that VM migration will work between QEMU versions. For instance the
+``virt-5.0`` machine type will behave like the ``virt`` machine from
+the QEMU 5.0 release, and migration should work between ``virt-5.0``
+of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
+is not guaranteed to work between different QEMU releases for
+the non-versioned ``virt`` machine type.
+
+Supported devices
+"""""""""""""""""
+
+The virt board supports:
+
+- PCI/PCIe devices
+- Flash memory
+- One PL011 UART
+- An RTC
+- The fw_cfg device that allows a guest to obtain data from QEMU
+- A PL061 GPIO controller
+- An optional SMMUv3 IOMMU
+- hotpluggable DIMMs
+- hotpluggable NVDIMMs
+- An MSI controller (GICv2M or ITS). GICv2M is selected by default along
+  with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note
+  that ITS is not modeled in TCG mode.
+- 32 virtio-mmio transport devices
+- running guests using the KVM accelerator on aarch64 hardware
+- large amounts of RAM (at least 255GB, and more if using highmem)
+- many CPUs (up to 512 if using a GICv3 and highmem)
+- Secure-World-only devices if the CPU has TrustZone:
+
+  - A second PL011 UART
+  - A secure flash memory
+  - 16MB of secure RAM
+
+Supported guest CPU types:
+
+- ``cortex-a7`` (32-bit)
+- ``cortex-a15`` (32-bit; the default)
+- ``cortex-a53`` (64-bit)
+- ``cortex-a57`` (64-bit)
+- ``cortex-a72`` (64-bit)
+- ``host`` (with KVM only)
+- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
+
+Note that the default is ``cortex-a15``, so for an AArch64 guest you must
+specify a CPU type.
+
+Graphics output is available, but unlike the x86 PC machine types
+there is no default display device enabled: you should select one from
+the Display devices section of "-device help". The recommended option
+is ``virtio-gpu-pci``; this is the only one which will work correctly
+with KVM. You may also need to ensure your guest kernel is configured
+with support for this; see below.
+
+Machine-specific options
+""""""""""""""""""""""""
+
+The following machine-specific options are supported:
+
+secure
+  Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
+  Arm Security Extensions (TrustZone). The default is ``off``.
+
+virtualization
+  Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
+  Arm Virtualization Extensions. The default is ``off``.
+
+highmem
+  Set ``on``/``off`` to enable/disable placing devices and RAM in physical
+  address space above 32 bits. The default is ``on`` for machine types
+  later than ``virt-2.12``.
+
+gic-version
+  Specify the version of the Generic Interrupt Controller (GIC) to provide.
+  Valid values are:
+
+  ``2``
+    GICv2
+  ``3``
+    GICv3
+  ``host``
+    Use the same GIC version the host provides, when using KVM
+  ``max``
+    Use the best GIC version possible (same as host when using KVM;
+    currently same as ``3``` for TCG, but this may change in future)
+
+its
+  Set ``on``/``off`` to enable/disable ITS instantiation. The default is ``on``
+  for machine types later than ``virt-2.7``.
+
+iommu
+  Set the IOMMU type to create for the guest. Valid values are:
+
+  ``none``
+    Don't create an IOMMU (the default)
+  ``smmuv3``
+    Create an SMMUv3
+
+ras
+  Set ``on``/``off`` to enable/disable reporting host memory errors to a guest
+  using ACPI and guest external abort exceptions. The default is off.
+
+Linux guest kernel configuration
+""""""""""""""""""""""""""""""""
+
+The 'defconfig' for Linux arm and arm64 kernels should include the
+right device drivers for virtio and the PCI controller; however some older
+kernel versions, especially for 32-bit Arm, did not have everything
+enabled by default. If you're not seeing PCI devices that you expect,
+then check that your guest config has::
+
+  CONFIG_PCI=y
+  CONFIG_VIRTIO_PCI=y
+  CONFIG_PCI_HOST_GENERIC=y
+
+If you want to use the ``virtio-gpu-pci`` graphics device you will also
+need::
+
+  CONFIG_DRM=y
+  CONFIG_DRM_VIRTIO_GPU=y
+
+Hardware configuration information for bare-metal programming
+"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+
+The ``virt`` board automatically generates a device tree blob ("dtb")
+which it passes to the guest. This provides information about the
+addresses, interrupt lines and other configuration of the various devices
+in the system. Guest code can rely on and hard-code the following
+addresses:
+
+- Flash memory starts at address 0x0000_0000
+
+- RAM starts at 0x4000_0000
+
+All other information about device locations may change between
+QEMU versions, so guest code must look in the DTB.
+
+QEMU supports two types of guest image boot for ``virt``, and
+the way for the guest code to locate the dtb binary differs:
+
+- For guests using the Linux kernel boot protocol (this means any
+  non-ELF file passed to the QEMU ``-kernel`` option) the address
+  of the DTB is passed in a register (``r2`` for 32-bit guests,
+  or ``x0`` for 64-bit guests)
+
+- For guests booting as "bare-metal" (any other kind of boot),
+  the DTB is at the start of RAM (0x4000_0000)
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    arm/collie
    arm/sx1
    arm/stellaris
+   arm/virt
 
 Arm CPU features
 ================
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/virt*
 F: include/hw/arm/virt.h
+F: docs/system/arm/virt.rst
 
 Xilinx Zynq
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-- 
2.20.1

Hi; here's the latest round of arm patches. I have included also
my patchset for the RTC devices to avoid keeping time_t and
time_t diffs in 32-bit variables.

thanks
-- PMM

The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:

Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831

for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:

hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)

----------------------------------------------------------------
target-arm queue:
 * Some of the preliminary patches for Cortex-A710 support
 * i.MX7 and i.MX6UL refactoring
 * Implement SRC device for i.MX7
 * Catch illegal-exception-return from EL3 with bad NSE/NS
 * Use 64-bit offsets for holding time_t differences in RTC devices
 * Model correct number of MPU regions for an505, an521, an524 boards

----------------------------------------------------------------
Alex Bennée (1):
      target/arm: properly document FEAT_CRC32

Jean-Christophe Dubois (6):
      Remove i.MX7 IOMUX GPR device from i.MX6UL
      Refactor i.MX6UL processor code
      Add i.MX6UL missing devices.
      Refactor i.MX7 processor code
      Add i.MX7 missing TZ devices and memory regions
      Add i.MX7 SRC device implementation

Peter Maydell (8):
      target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
      hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
      hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
      hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
      rtc: Use time_t for passing and returning time offsets
      target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
      hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
      hw/arm: Set number of MPU regions correctly for an505, an521, an524

Richard Henderson (9):
      target/arm: Reduce dcz_blocksize to uint8_t
      target/arm: Allow cpu to configure GM blocksize
      target/arm: Support more GM blocksizes
      target/arm: When tag memory is not present, set MTE=1
      target/arm: Introduce make_ccsidr64
      target/arm: Apply access checks to neoverse-n1 special registers
      target/arm: Apply access checks to neoverse-v1 special registers
      target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
      target/arm: Implement FEAT_HPDS2 as a no-op

From: Richard Henderson <richard.henderson@linaro.org>

Previously we hard-coded the blocksize with GMID_EL1_BS.
But the value we choose for -cpu max does not match the
value that cortex-a710 uses.

Mirror the way we handle dcz_blocksize.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h               |  2 ++
 target/arm/internals.h         |  6 -----
 target/arm/tcg/translate.h     |  2 ++
 target/arm/helper.c            | 11 +++++---
 target/arm/tcg/cpu64.c         |  1 +
 target/arm/tcg/mte_helper.c    | 46 ++++++++++++++++++++++------------
 target/arm/tcg/translate-a64.c |  5 ++--
 7 files changed, 45 insertions(+), 28 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
 
     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
     uint8_t dcz_blocksize;
+    /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
+    uint8_t gm_blocksize;
 
     uint64_t rvbar_prop; /* Property/input signals.  */
 
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
 
 #endif /* !CONFIG_USER_ONLY */
 
-/*
- * The log2 of the words in the tag block, for GMID_EL1.BS.
- * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
- */
-#define GMID_EL1_BS  6
-
 /*
  * SVE predicates are 1/8 the size of SVE vectors, and cannot use
  * the same simd_desc() encoding due to restrictions on size.
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     int8_t btype;
     /* A copy of cpu->dcz_blocksize. */
     uint8_t dcz_blocksize;
+    /* A copy of cpu->gm_blocksize. */
+    uint8_t gm_blocksize;
     /* True if this page is guarded.  */
     bool guarded_page;
     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
       .access = PL1_RW, .accessfn = access_mte,
       .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
-    { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
-      .access = PL1_R, .accessfn = access_aa64_tid5,
-      .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
     { .name = "TCO", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
       .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      * then define only a RAZ/WI version of PSTATE.TCO.
      */
     if (cpu_isar_feature(aa64_mte, cpu)) {
+        ARMCPRegInfo gmid_reginfo = {
+            .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
+            .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
+            .access = PL1_R, .accessfn = access_aa64_tid5,
+            .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
+        };
+        define_one_arm_cp_reg(cpu, &gmid_reginfo);
         define_arm_cp_regs(cpu, mte_reginfo);
         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
     } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
     cpu->dcz_blocksize = 7; /*  512 bytes */
 #endif
+    cpu->gm_blocksize = 6;  /*  256 bytes */
 
     cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
     cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
     }
 }
 
-#define LDGM_STGM_SIZE  (4 << GMID_EL1_BS)
-
 uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 {
     int mmu_idx = cpu_mmu_index(env, false);
     uintptr_t ra = GETPC();
+    int gm_bs = env_archcpu(env)->gm_blocksize;
+    int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
 
-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
+    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
     /* Trap if accessing an invalid page.  */
     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
+                                 gm_bs_bytes, MMU_DATA_LOAD,
+                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
 
     /* The tag is squashed to zero if the page does not support tags.  */
     if (!tag_mem) {
         return 0;
     }
 
-    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
     /*
-     * We are loading 64-bits worth of tags.  The ordering of elements
-     * within the word corresponds to a 64-bit little-endian operation.
+     * The ordering of elements within the word corresponds to
+     * a little-endian operation.
      */
-    return ldq_le_p(tag_mem);
+    switch (gm_bs) {
+    case 6:
+        /* 256 bytes -> 16 tags -> 64 result bits */
+        return ldq_le_p(tag_mem);
+    default:
+        /* cpu configured with unsupported gm blocksize. */
+        g_assert_not_reached();
+    }
 }
 
 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
 {
     int mmu_idx = cpu_mmu_index(env, false);
     uintptr_t ra = GETPC();
+    int gm_bs = env_archcpu(env)->gm_blocksize;
+    int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
 
-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
+    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
     /* Trap if accessing an invalid page.  */
     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
+                                 gm_bs_bytes, MMU_DATA_LOAD,
+                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
 
     /*
      * Tag store only happens if the page support tags,
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
         return;
     }
 
-    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
     /*
-     * We are storing 64-bits worth of tags.  The ordering of elements
-     * within the word corresponds to a 64-bit little-endian operation.
+     * The ordering of elements within the word corresponds to
+     * a little-endian operation.
      */
-    stq_le_p(tag_mem, val);
+    switch (gm_bs) {
+    case 6:
+        stq_le_p(tag_mem, val);
+        break;
+    default:
+        /* cpu configured with unsupported gm blocksize. */
+        g_assert_not_reached();
+    }
 }
 
 void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
         gen_helper_stgm(cpu_env, addr, tcg_rt);
     } else {
         MMUAccessType acc = MMU_DATA_STORE;
-        int size = 4 << GMID_EL1_BS;
+        int size = 4 << s->gm_blocksize;
 
         clean_addr = clean_data_tbi(s, addr);
         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
         gen_helper_ldgm(tcg_rt, cpu_env, addr);
     } else {
         MMUAccessType acc = MMU_DATA_LOAD;
-        int size = 4 << GMID_EL1_BS;
+        int size = 4 << s->gm_blocksize;
 
         clean_addr = clean_data_tbi(s, addr);
         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->cp_regs = arm_cpu->cp_regs;
     dc->features = env->features;
     dc->dcz_blocksize = arm_cpu->dcz_blocksize;
+    dc->gm_blocksize = arm_cpu->gm_blocksize;
 
 #ifdef CONFIG_USER_ONLY
     /* In sve_probe_page, we assume TBI is enabled. */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Support all of the easy GM block sizes.
Use direct memory operations, since the pointers are aligned.

While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
an atomic store of one nibble.  This is not difficult, but there
is also no point in supporting it until required.

Note that cortex-a710 sets GM blocksize to match its cacheline
size of 64 bytes.  I expect many implementations will also
match the cacheline, which makes 16 bytes very unlikely.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c            | 18 +++++++++---
 target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
 2 files changed, 62 insertions(+), 12 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
                                        ID_PFR1, VIRTUALIZATION, 0);
     }
 
+    if (cpu_isar_feature(aa64_mte, cpu)) {
+        /*
+         * The architectural range of GM blocksize is 2-6, however qemu
+         * doesn't support blocksize of 2 (see HELPER(ldgm)).
+         */
+        if (tcg_enabled()) {
+            assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
+        }
+
 #ifndef CONFIG_USER_ONLY
-    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
         /*
          * Disable the MTE feature bits if we do not have tag-memory
          * provided by the machine.
          */
-        cpu->isar.id_aa64pfr1 =
-            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
-    }
+        if (cpu->tag_memory == NULL) {
+            cpu->isar.id_aa64pfr1 =
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+        }
 #endif
+    }
 
     if (tcg_enabled()) {
         /*
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
     int gm_bs = env_archcpu(env)->gm_blocksize;
     int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
+    uint64_t ret;
+    int shift;
 
     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 
     /*
      * The ordering of elements within the word corresponds to
-     * a little-endian operation.
+     * a little-endian operation.  Computation of shift comes from
+     *
+     *     index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
+     *     data<index*4+3:index*4> = tag
+     *
+     * Because of the alignment of ptr above, BS=6 has shift=0.
+     * All memory operations are aligned.  Defer support for BS=2,
+     * requiring insertion or extraction of a nibble, until we
+     * support a cpu that requires it.
      */
     switch (gm_bs) {
+    case 3:
+        /* 32 bytes -> 2 tags -> 8 result bits */
+        ret = *(uint8_t *)tag_mem;
+        break;
+    case 4:
+        /* 64 bytes -> 4 tags -> 16 result bits */
+        ret = cpu_to_le16(*(uint16_t *)tag_mem);
+        break;
+    case 5:
+        /* 128 bytes -> 8 tags -> 32 result bits */
+        ret = cpu_to_le32(*(uint32_t *)tag_mem);
+        break;
     case 6:
         /* 256 bytes -> 16 tags -> 64 result bits */
-        return ldq_le_p(tag_mem);
+        return cpu_to_le64(*(uint64_t *)tag_mem);
     default:
-        /* cpu configured with unsupported gm blocksize. */
+        /*
+         * CPU configured with unsupported/invalid gm blocksize.
+         * This is detected early in arm_cpu_realizefn.
+         */
         g_assert_not_reached();
     }
+    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
+    return ret << shift;
 }
 
 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
     int gm_bs = env_archcpu(env)->gm_blocksize;
     int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
+    int shift;
 
     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
         return;
     }
 
-    /*
-     * The ordering of elements within the word corresponds to
-     * a little-endian operation.
-     */
+    /* See LDGM for comments on BS and on shift.  */
+    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
+    val >>= shift;
     switch (gm_bs) {
+    case 3:
+        /* 32 bytes -> 2 tags -> 8 result bits */
+        *(uint8_t *)tag_mem = val;
+        break;
+    case 4:
+        /* 64 bytes -> 4 tags -> 16 result bits */
+        *(uint16_t *)tag_mem = cpu_to_le16(val);
+        break;
+    case 5:
+        /* 128 bytes -> 8 tags -> 32 result bits */
+        *(uint32_t *)tag_mem = cpu_to_le32(val);
+        break;
     case 6:
-        stq_le_p(tag_mem, val);
+        /* 256 bytes -> 16 tags -> 64 result bits */
+        *(uint64_t *)tag_mem = cpu_to_le64(val);
         break;
     default:
         /* cpu configured with unsupported gm blocksize. */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

When the cpu support MTE, but the system does not, reduce cpu
support to user instructions at EL0 instead of completely
disabling MTE.  If we encounter a cpu implementation which does
something else, we can revisit this setting.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
 #ifndef CONFIG_USER_ONLY
         /*
-         * Disable the MTE feature bits if we do not have tag-memory
-         * provided by the machine.
+         * If we do not have tag-memory provided by the machine,
+         * reduce MTE support to instructions enabled at EL0.
+         * This matches Cortex-A710 BROADCASTMTE input being LOW.
          */
         if (cpu->tag_memory == NULL) {
             cpu->isar.id_aa64pfr1 =
-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
         }
 #endif
     }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Do not hard-code the constants for Neoverse V1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
 1 file changed, 32 insertions(+), 16 deletions(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
+#include "qemu/units.h"
 #include "internals.h"
 #include "cpregs.h"
 
+static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
+                              unsigned cachesize)
+{
+    unsigned lg_linesize = ctz32(linesize);
+    unsigned sets;
+
+    /*
+     * The 64-bit CCSIDR_EL1 format is:
+     *   [55:32] number of sets - 1
+     *   [23:3]  associativity - 1
+     *   [2:0]   log2(linesize) - 4
+     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
+     */
+    assert(assoc != 0);
+    assert(is_power_of_2(linesize));
+    assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
+
+    /* sets * associativity * linesize == cachesize. */
+    sets = cachesize / (assoc * linesize);
+    assert(cachesize % (assoc * linesize) == 0);
+
+    return ((uint64_t)(sets - 1) << 32)
+         | ((assoc - 1) << 3)
+         | (lg_linesize - 4);
+}
+
 static void aarch64_a35_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
      * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
      * but also says it implements CCIDX, which means they should be
      * 64-bit format. So we here use values which are based on the textual
-     * information in chapter 2 of the TRM (and on the fact that
-     * sets * associativity * linesize == cachesize).
-     *
-     * The 64-bit CCSIDR_EL1 format is:
-     *   [55:32] number of sets - 1
-     *   [23:3]  associativity - 1
-     *   [2:0]   log2(linesize) - 4
-     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
-     *
-     * L1: 4-way set associative 64-byte line size, total size 64K,
-     * so sets is 256.
+     * information in chapter 2 of the TRM:
      *
+     * L1: 4-way set associative 64-byte line size, total size 64K.
      * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
-     * We pick 1MB, so this has 2048 sets.
-     *
      * L3: No L3 (this matches the CLIDR_EL1 value).
      */
-    cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
+    cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
+    cpu->ccsidr[1] = cpu->ccsidr[0];                 /* L1 icache */
+    cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB);  /* L2 cache */
 
     /* From 3.2.115 SCTLR_EL3 */
     cpu->reset_sctlr = 0x30c50838;
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Access to many of the special registers is enabled or disabled
by ACTLR_EL[23], which we implement as constant 0, which means
that all writes outside EL3 should trap.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h    |  2 ++
 target/arm/helper.c    |  4 ++--
 target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
 3 files changed, 41 insertions(+), 11 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 #endif
 
+CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
+
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
 }
 
 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM.  */
-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
-                                      bool isread)
+CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
+                               bool isread)
 {
     if (arm_current_el(env) == 1) {
         uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
     /* TODO:  Add A64FX specific HPC extension registers */
 }
 
+static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
+                                     bool read)
+{
+    if (!read) {
+        int el = arm_current_el(env);
+
+        /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
+        if (el < 2 && arm_is_el2_enabled(env)) {
+            return CP_ACCESS_TRAP_EL2;
+        }
+        /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
+        if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
+            return CP_ACCESS_TRAP_EL3;
+        }
+    }
+    return CP_ACCESS_OK;
+}
+
 static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
     { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      /* Traps and enables are the same as for TCR_EL1. */
+      .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
     { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     /*
      * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
      * (and in particular its system registers).
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
+      .accessfn = access_actlr_w },
     { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
 };
 
 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

There is only one additional EL1 register modeled, which
also needs to use access_actlr_w.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
 static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
     { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
external to the cpu, which is out of scope for QEMU.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         /* FEAT_SPE (Statistical Profiling Extension) */
         cpu->isar.id_aa64dfr0 =
             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
+        /* FEAT_TRBE (Trace Buffer Extension) */
+        cpu->isar.id_aa64dfr0 =
+            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
         /* FEAT_TRF (Self-hosted Trace Extension) */
         cpu->isar.id_aa64dfr0 =
             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This feature allows the operating system to set TCR_ELx.HWU*
to allow the implementation to use the PBHA bits from the
block and page descriptors for for IMPLEMENTATION DEFINED
purposes.  Since QEMU has no need to use these bits, we may
simply ignore them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu32.c        | 2 +-
 target/arm/tcg/cpu64.c        | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
 - FEAT_HCX (Support for the HCRX_EL2 register)
 - FEAT_HPDS (Hierarchical permission disables)
+- FEAT_HPDS2 (Translation table page-based hardware attributes)
 - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
 - FEAT_IDST (ID space trap handling)
 - FEAT_IESB (Implicit error synchronization event)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
     cpu->isar.id_mmfr3 = t;
 
     t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
     t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
+    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2);     /* FEAT_HPDS2 */
     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

This is a mandatory feature for Armv8.1 architectures but we don't
state the feature clearly in our emulation list. Also include
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
Cc: qemu-stable@nongnu.org
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
[PMM: pluralize 'instructions' in docs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu64.c        | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

From: Jean-Christophe Dubois <jcd@tribudubois.net>

i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
In particular, register 22 is not present on i.MX6UL and this is actualy
The only register that is really emulated in the i.MX7 IOMUX GPR device.

Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
as an unimplemented device at the same bus adress and the 2 instantiations
were actualy colliding. So we go back to the unimplemented device for now.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 --
 hw/arm/fsl-imx6ul.c         | 11 -----------
 2 files changed, 13 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx6ul_ccm.h"
 #include "hw/misc/imx6_src.h"
 #include "hw/misc/imx7_snvs.h"
-#include "hw/misc/imx7_gpr.h"
 #include "hw/intc/imx_gpcv2.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "hw/gpio/imx_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
     IMX6SRCState       src;
     IMX7SNVSState      snvs;
     IMXGPCv2State      gpcv2;
-    IMX7GPRState       gpr;
     IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
     IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
     IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      */
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
-    /*
-     * GPR
-     */
-    object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
-
     /*
      * GPIOs 1 to 5
      */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_WDOGn_IRQ[i]));
     }
 
-    /*
-     * GPR
-     */
-    sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
-
     /*
      * SDMA
      */
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
 hw/arm/fsl-imx6ul.c         | 147 ++++++++++++++++++++++-----------
 2 files changed, 232 insertions(+), 71 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/memory.h"
 #include "cpu.h"
 #include "qom/object.h"
+#include "qemu/units.h"
 
 #define TYPE_FSL_IMX6UL "fsl-imx6ul"
 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_ADCS         = 2,
     FSL_IMX6UL_NUM_USB_PHYS     = 2,
     FSL_IMX6UL_NUM_USBS         = 2,
+    FSL_IMX6UL_NUM_SAIS         = 3,
+    FSL_IMX6UL_NUM_CANS         = 2,
+    FSL_IMX6UL_NUM_PWMS         = 4,
 };
 
 struct FslIMX6ULState {
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
 
 enum FslIMX6ULMemoryMap {
     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
 
     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
-    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
-    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
-    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
-    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
 
-    /* AIPS-2 */
+    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
+    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
+
+    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
+    FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
+
+    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
+    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
+
+    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
+
+    /* AIPS-2 Begin */
     FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
+
     FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
+
     FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
     FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
     FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
     FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
+
     FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
+
     FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
+    FSL_IMX6UL_QSPI_SIZE            = 0x500,
+
     FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
+    FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
+
     FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
+    FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
+
     FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
+    FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
+
     FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
+    FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
+
     FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
+    FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
+    FSL_IMX6UL_LCDIF_SIZE           = 0x100,
+
     FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
+    FSL_IMX6UL_CSI_SIZE             = 0x100,
+
     FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
+    FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
+    FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
+
     FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
+    FSL_IMX6UL_EIM_SIZE             = 0x100,
+
     FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
+
     FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
+    FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
+
     FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
+    FSL_IMX6UL_ROMCP_SIZE           = 0x300,
+
     FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
     FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
     FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
+
     FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
     FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
+    FSL_IMX6UL_ADCn_SIZE            = 0x100,
+
     FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
     FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
-    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
-    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
-    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
-    FSL_IMX6UL_USBO2_USB_ADDR       = 0x02184000,
-    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
-    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
-    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
-    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
 
-    /* AIPS-1 */
+    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
+    FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
+
+    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
+
+    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
+    FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
+    FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
+
+    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
+    FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
+
+    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
+    FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
+
+    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
+    FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
+
+    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
+    FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
+    /* AIPS-2 End */
+
+    /* AIPS-1 Begin */
     FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
     FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
     FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
     FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
+
     FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
+    FSL_IMX6UL_SDMA_SIZE            = 0x300,
+
     FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
+
     FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
+    FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
+
     FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
+    FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
+
     FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
+
     FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
+
     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
+
     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
+
     FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
-    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
     FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
-    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
+
     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
+    FSL_IMX6UL_ANALOG_SIZE          = 0x300,
+
     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
+
     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
     FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
+
     FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
+    FSL_IMX6UL_KPP_SIZE             = 0x10,
+
     FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
+
     FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
+    FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
+
     FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
     FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
     FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
     FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
     FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
+
     FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
+
     FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
     FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
+    FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
+
     FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
     FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
     FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
     FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
+    FSL_IMX6UL_PWMn_SIZE            = 0x20,
+
     FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
+    FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
+
     FSL_IMX6UL_BEE_ADDR             = 0x02044000,
+    FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
+    FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
+
     FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
+    FSL_IMX6UL_SPBA_SIZE            = 0x100,
+
     FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
+    FSL_IMX6UL_ASRC_SIZE            = 0x100,
+
     FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
     FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
     FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
+    FSL_IMX6UL_SAIn_SIZE            = 0x200,
+
     FSL_IMX6UL_UART8_ADDR           = 0x02024000,
     FSL_IMX6UL_UART1_ADDR           = 0x02020000,
     FSL_IMX6UL_UART7_ADDR           = 0x02018000,
+
     FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
     FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
     FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
     FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
+
     FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
+    FSL_IMX6UL_SPDIF_SIZE           = 0x100,
+    /* AIPS-1 End */
+
+    FSL_IMX6UL_BCH_ADDR             = 0x01808000,
+    FSL_IMX6UL_BCH_SIZE             = 0x200,
+
+    FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
+    FSL_IMX6UL_GPMI_SIZE            = 0x200,
 
     FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
-    FSL_IMX6UL_APBH_DMA_SIZE        = (32 * 1024),
+    FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
 
     FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
 
     FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
-    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = 0x00060000,
+    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
+
     FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
-    FSL_IMX6UL_OCRAM_MEM_SIZE       = 0x00020000,
+    FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
+
     FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
-    FSL_IMX6UL_CAAM_MEM_SIZE        = 0x00008000,
+    FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
+
     FSL_IMX6UL_ROM_ADDR             = 0x00000000,
-    FSL_IMX6UL_ROM_SIZE             = 0x00018000,
+    FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
 };
 
 enum FslIMX6ULIRQs {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
     /*
-     * GPIOs 1 to 5
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * GPT 1, 2
+     * GPTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * EPIT 1, 2
+     * EPITs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
         snprintf(name, NAME_SIZE, "epit%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * eCSPI
+     * eCSPIs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * I2C
+     * I2Cs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
         snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      */
     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
         snprintf(name, NAME_SIZE, "eth%d", i);
         object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
     }
 
-    /* USB */
+    /*
+     * USB PHYs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
         snprintf(name, NAME_SIZE, "usbphy%d", i);
         object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
     }
+
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
         snprintf(name, NAME_SIZE, "usb%d", i);
         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
     }
 
     /*
-     * SDHCI
+     * SDHCIs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
         snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
         snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      * A7MPCORE DAP
      */
     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
-                                0x100000);
+                                FSL_IMX6UL_A7MPCORE_DAP_SIZE);
 
     /*
-     * GPT 1, 2
+     * GPTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * EPIT 1, 2
+     * EPITs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * GPIO
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * IOMUXC and IOMUXC_GPR
+     * IOMUXC
      */
-    for (i = 0; i < 1; i++) {
-        static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
-            FSL_IMX6UL_IOMUXC_ADDR,
-            FSL_IMX6UL_IOMUXC_GPR_ADDR,
-        };
-
-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
-        create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
-    }
+    create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
+                                FSL_IMX6UL_IOMUXC_SIZE);
+    create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
+                                FSL_IMX6UL_IOMUXC_GPR_SIZE);
 
     /*
      * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
 
-    /* Initialize all ECSPI */
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
             FSL_IMX6UL_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * I2C
+     * I2Cs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      *
      * We must use two loops since phy_connected affects the other interface
      * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
     }
 
-    /* USB */
+    /*
+     * USB PHYs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+        static const hwaddr
+                     FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
+            FSL_IMX6UL_USBPHY1_ADDR,
+            FSL_IMX6UL_USBPHY2_ADDR,
+        };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
-                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
+                        FSL_IMX6UL_USB_PHYn_ADDR[i]);
     }
 
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+        static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
+            FSL_IMX6UL_USBO2_USB1_ADDR,
+            FSL_IMX6UL_USBO2_USB2_ADDR,
+        };
+
         static const int FSL_IMX6UL_USBn_IRQ[] = {
             FSL_IMX6UL_USB1_IRQ,
             FSL_IMX6UL_USB2_IRQ,
         };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
-                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
+                        FSL_IMX6UL_USB02_USBn_ADDR[i]);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
                                             FSL_IMX6UL_USBn_IRQ[i]));
     }
 
     /*
-     * USDHC
+     * USDHCs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_WDOG2_ADDR,
             FSL_IMX6UL_WDOG3_ADDR,
         };
+
         static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
             FSL_IMX6UL_WDOG1_IRQ,
             FSL_IMX6UL_WDOG2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     /*
      * SDMA
      */
-    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
+    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
+                                FSL_IMX6UL_SDMA_SIZE);
 
     /*
-     * SAI (Audio SSI (Synchronous Serial Interface))
+     * SAIs (Audio SSI (Synchronous Serial Interface))
      */
-    create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
-    create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
-    create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
+        static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
+            FSL_IMX6UL_SAI1_ADDR,
+            FSL_IMX6UL_SAI2_ADDR,
+            FSL_IMX6UL_SAI3_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "sai%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
+                                    FSL_IMX6UL_SAIn_SIZE);
+    }
 
     /*
-     * PWM
+     * PWMs
      */
-    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
-    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
-    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
-    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
+        static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
+            FSL_IMX6UL_PWM1_ADDR,
+            FSL_IMX6UL_PWM2_ADDR,
+            FSL_IMX6UL_PWM3_ADDR,
+            FSL_IMX6UL_PWM4_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "pwm%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
+                                    FSL_IMX6UL_PWMn_SIZE);
+    }
 
     /*
      * Audio ASRC (asynchronous sample rate converter)
      */
-    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
+    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
+                                FSL_IMX6UL_ASRC_SIZE);
 
     /*
-     * CAN
+     * CANs
      */
-    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
-    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
+        static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
+            FSL_IMX6UL_CAN1_ADDR,
+            FSL_IMX6UL_CAN2_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "can%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
+                                    FSL_IMX6UL_CANn_SIZE);
+    }
 
     /*
      * APHB_DMA
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
         };
 
         snprintf(name, NAME_SIZE, "adc%d", i);
-        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
+        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
+                                    FSL_IMX6UL_ADCn_SIZE);
     }
 
     /*
      * LCD
      */
-    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
+    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
+                                FSL_IMX6UL_LCDIF_SIZE);
 
     /*
      * ROM memory
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add TZASC as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add 4 missing PWM devices

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 +-
 hw/arm/fsl-imx6ul.c         | 16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_USBS         = 2,
     FSL_IMX6UL_NUM_SAIS         = 3,
     FSL_IMX6UL_NUM_CANS         = 2,
-    FSL_IMX6UL_NUM_PWMS         = 4,
+    FSL_IMX6UL_NUM_PWMS         = 8,
 };
 
 struct FslIMX6ULState {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_PWM2_ADDR,
             FSL_IMX6UL_PWM3_ADDR,
             FSL_IMX6UL_PWM4_ADDR,
+            FSL_IMX6UL_PWM5_ADDR,
+            FSL_IMX6UL_PWM6_ADDR,
+            FSL_IMX6UL_PWM7_ADDR,
+            FSL_IMX6UL_PWM8_ADDR,
         };
 
         snprintf(name, NAME_SIZE, "pwm%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
                                 FSL_IMX6UL_LCDIF_SIZE);
 
+    /*
+     * CSU
+     */
+    create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
+                                FSL_IMX6UL_CSU_SIZE);
+
+    /*
+     * TZASC
+     */
+    create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
+                                FSL_IMX6UL_TZASC_SIZE);
+
     /*
      * ROM memory
      */
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
 hw/arm/fsl-imx7.c         | 130 ++++++++++-----
 2 files changed, 335 insertions(+), 125 deletions(-)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx7_ccm.h"
 #include "hw/misc/imx7_snvs.h"
 #include "hw/misc/imx7_gpr.h"
-#include "hw/misc/imx6_src.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "hw/gpio/imx_gpio.h"
 #include "hw/char/imx_serial.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/usb/chipidea.h"
 #include "cpu.h"
 #include "qom/object.h"
+#include "qemu/units.h"
 
 #define TYPE_FSL_IMX7 "fsl-imx7"
 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
     FSL_IMX7_NUM_ECSPIS       = 4,
     FSL_IMX7_NUM_USBS         = 3,
     FSL_IMX7_NUM_ADCS         = 2,
+    FSL_IMX7_NUM_SAIS         = 3,
+    FSL_IMX7_NUM_CANS         = 2,
+    FSL_IMX7_NUM_PWMS         = 4,
 };
 
 struct FslIMX7State {
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
 
 enum FslIMX7MemoryMap {
     FSL_IMX7_MMDC_ADDR            = 0x80000000,
-    FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX7_MMDC_SIZE            = (2 * GiB),
 
-    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
-    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
-    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
-    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
-    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
-    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
-    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
+    FSL_IMX7_QSPI1_MEM_ADDR       = 0x60000000,
+    FSL_IMX7_QSPI1_MEM_SIZE       = (256 * MiB),
 
-    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+    FSL_IMX7_PCIE1_MEM_ADDR       = 0x40000000,
+    FSL_IMX7_PCIE1_MEM_SIZE       = (256 * MiB),
 
-    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
-    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
-    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
-    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
+    FSL_IMX7_QSPI1_RX_BUF_ADDR    = 0x34000000,
+    FSL_IMX7_QSPI1_RX_BUF_SIZE    = (32 * MiB),
 
-    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
+    /* PCIe Peripherals */
+    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 
-    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
-    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
-    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
-    FSL_IMX7_GPT4_ADDR            = 0x30300000,
+    /* MMAP Peripherals */
+    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
+    FSL_IMX7_DMA_APBH_SIZE        = 0x8000,
 
-    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
-    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
-    FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
+    /* GPV configuration */
+    FSL_IMX7_GPV6_ADDR            = 0x32600000,
+    FSL_IMX7_GPV5_ADDR            = 0x32500000,
+    FSL_IMX7_GPV4_ADDR            = 0x32400000,
+    FSL_IMX7_GPV3_ADDR            = 0x32300000,
+    FSL_IMX7_GPV2_ADDR            = 0x32200000,
+    FSL_IMX7_GPV1_ADDR            = 0x32100000,
+    FSL_IMX7_GPV0_ADDR            = 0x32000000,
+    FSL_IMX7_GPVn_SIZE            = (1 * MiB),
 
-    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
-    FSL_IMX7_OCOTP_SIZE           = 0x10000,
+    /* Arm Peripherals */
+    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
 
-    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
-    FSL_IMX7_SNVS_ADDR            = 0x30370000,
-    FSL_IMX7_CCM_ADDR             = 0x30380000,
+    /* AIPS-3 Begin */
 
-    FSL_IMX7_SRC_ADDR             = 0x30390000,
-    FSL_IMX7_SRC_SIZE             = 0x1000,
+    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
+    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 
-    FSL_IMX7_ADC1_ADDR            = 0x30610000,
-    FSL_IMX7_ADC2_ADDR            = 0x30620000,
-    FSL_IMX7_ADCn_SIZE            = 0x1000,
+    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
+    FSL_IMX7_SDMA_SIZE            = (4 * KiB),
 
-    FSL_IMX7_PWM1_ADDR            = 0x30660000,
-    FSL_IMX7_PWM2_ADDR            = 0x30670000,
-    FSL_IMX7_PWM3_ADDR            = 0x30680000,
-    FSL_IMX7_PWM4_ADDR            = 0x30690000,
-    FSL_IMX7_PWMn_SIZE            = 0x10000,
+    FSL_IMX7_EIM_ADDR             = 0x30BC0000,
+    FSL_IMX7_EIM_SIZE             = (4 * KiB),
 
-    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
-    FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
+    FSL_IMX7_QSPI_ADDR            = 0x30BB0000,
+    FSL_IMX7_QSPI_SIZE            = 0x8000,
 
-    FSL_IMX7_GPC_ADDR             = 0x303A0000,
+    FSL_IMX7_SIM2_ADDR            = 0x30BA0000,
+    FSL_IMX7_SIM1_ADDR            = 0x30B90000,
+    FSL_IMX7_SIMn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
+    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
+    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
+
+    FSL_IMX7_USB3_ADDR            = 0x30B30000,
+    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
+    FSL_IMX7_USB2_ADDR            = 0x30B20000,
+    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
+    FSL_IMX7_USB1_ADDR            = 0x30B10000,
+    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
+    FSL_IMX7_USBMISCn_SIZE        = 0x200,
+
+    FSL_IMX7_USB_PL301_ADDR       = 0x30AD0000,
+    FSL_IMX7_USB_PL301_SIZE       = (64 * KiB),
+
+    FSL_IMX7_SEMAPHORE_HS_ADDR    = 0x30AC0000,
+    FSL_IMX7_SEMAPHORE_HS_SIZE    = (64 * KiB),
+
+    FSL_IMX7_MUB_ADDR             = 0x30AB0000,
+    FSL_IMX7_MUA_ADDR             = 0x30AA0000,
+    FSL_IMX7_MUn_SIZE             = (KiB),
+
+    FSL_IMX7_UART7_ADDR           = 0x30A90000,
+    FSL_IMX7_UART6_ADDR           = 0x30A80000,
+    FSL_IMX7_UART5_ADDR           = 0x30A70000,
+    FSL_IMX7_UART4_ADDR           = 0x30A60000,
+
+    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
+    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
+    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
+    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
+
+    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
+    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
+    FSL_IMX7_CANn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_AIPS3_CONF_ADDR      = 0x309F0000,
+    FSL_IMX7_AIPS3_CONF_SIZE      = (64 * KiB),
 
     FSL_IMX7_CAAM_ADDR            = 0x30900000,
-    FSL_IMX7_CAAM_SIZE            = 0x40000,
+    FSL_IMX7_CAAM_SIZE            = (256 * KiB),
 
-    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
-    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
-    FSL_IMX7_CANn_SIZE            = 0x10000,
+    FSL_IMX7_SPBA_ADDR            = 0x308F0000,
+    FSL_IMX7_SPBA_SIZE            = (4 * KiB),
 
-    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
-    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
-    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
-    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
+    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
+    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
+    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
+    FSL_IMX7_SAIn_SIZE            = (4 * KiB),
 
-    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
-    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
-    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
-    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
-
-    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
-    FSL_IMX7_LCDIF_SIZE           = 0x1000,
-
-    FSL_IMX7_UART1_ADDR           = 0x30860000,
+    FSL_IMX7_UART3_ADDR           = 0x30880000,
     /*
      * Some versions of the reference manual claim that UART2 is @
      * 0x30870000, but experiments with HW + DT files in upstream
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
      * actually located @ 0x30890000
      */
     FSL_IMX7_UART2_ADDR           = 0x30890000,
-    FSL_IMX7_UART3_ADDR           = 0x30880000,
-    FSL_IMX7_UART4_ADDR           = 0x30A60000,
-    FSL_IMX7_UART5_ADDR           = 0x30A70000,
-    FSL_IMX7_UART6_ADDR           = 0x30A80000,
-    FSL_IMX7_UART7_ADDR           = 0x30A90000,
+    FSL_IMX7_UART1_ADDR           = 0x30860000,
 
-    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
-    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
-    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
-    FSL_IMX7_SAIn_SIZE            = 0x10000,
+    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
+    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
+    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
+    FSL_IMX7_ECSPIn_SIZE          = (4 * KiB),
 
-    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
-    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
+    /* AIPS-3 End */
 
-    FSL_IMX7_USB1_ADDR            = 0x30B10000,
-    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
-    FSL_IMX7_USB2_ADDR            = 0x30B20000,
-    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
-    FSL_IMX7_USB3_ADDR            = 0x30B30000,
-    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
-    FSL_IMX7_USBMISCn_SIZE        = 0x200,
+    /* AIPS-2 Begin */
 
-    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
-    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
-    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
+    FSL_IMX7_AXI_DEBUG_MON_ADDR   = 0x307E0000,
+    FSL_IMX7_AXI_DEBUG_MON_SIZE   = (64 * KiB),
 
-    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
-    FSL_IMX7_SDMA_SIZE            = 0x1000,
+    FSL_IMX7_PERFMON2_ADDR        = 0x307D0000,
+    FSL_IMX7_PERFMON1_ADDR        = 0x307C0000,
+    FSL_IMX7_PERFMONn_SIZE        = (64 * KiB),
+
+    FSL_IMX7_DDRC_ADDR            = 0x307A0000,
+    FSL_IMX7_DDRC_SIZE            = (4 * KiB),
+
+    FSL_IMX7_DDRC_PHY_ADDR        = 0x30790000,
+    FSL_IMX7_DDRC_PHY_SIZE        = (4 * KiB),
+
+    FSL_IMX7_TZASC_ADDR           = 0x30780000,
+    FSL_IMX7_TZASC_SIZE           = (64 * KiB),
+
+    FSL_IMX7_MIPI_DSI_ADDR        = 0x30760000,
+    FSL_IMX7_MIPI_DSI_SIZE        = (4 * KiB),
+
+    FSL_IMX7_MIPI_CSI_ADDR        = 0x30750000,
+    FSL_IMX7_MIPI_CSI_SIZE        = 0x4000,
+
+    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
+    FSL_IMX7_LCDIF_SIZE           = 0x8000,
+
+    FSL_IMX7_CSI_ADDR             = 0x30710000,
+    FSL_IMX7_CSI_SIZE             = (4 * KiB),
+
+    FSL_IMX7_PXP_ADDR             = 0x30700000,
+    FSL_IMX7_PXP_SIZE             = 0x4000,
+
+    FSL_IMX7_EPDC_ADDR            = 0x306F0000,
+    FSL_IMX7_EPDC_SIZE            = (4 * KiB),
+
+    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
+    FSL_IMX7_PCIE_PHY_SIZE        = (4 * KiB),
+
+    FSL_IMX7_SYSCNT_CTRL_ADDR     = 0x306C0000,
+    FSL_IMX7_SYSCNT_CMP_ADDR      = 0x306B0000,
+    FSL_IMX7_SYSCNT_RD_ADDR       = 0x306A0000,
+
+    FSL_IMX7_PWM4_ADDR            = 0x30690000,
+    FSL_IMX7_PWM3_ADDR            = 0x30680000,
+    FSL_IMX7_PWM2_ADDR            = 0x30670000,
+    FSL_IMX7_PWM1_ADDR            = 0x30660000,
+    FSL_IMX7_PWMn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_FlEXTIMER2_ADDR      = 0x30650000,
+    FSL_IMX7_FlEXTIMER1_ADDR      = 0x30640000,
+    FSL_IMX7_FLEXTIMERn_SIZE      = (4 * KiB),
+
+    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
+
+    FSL_IMX7_ADC2_ADDR            = 0x30620000,
+    FSL_IMX7_ADC1_ADDR            = 0x30610000,
+    FSL_IMX7_ADCn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_AIPS2_CONF_ADDR      = 0x305F0000,
+    FSL_IMX7_AIPS2_CONF_SIZE      = (64 * KiB),
+
+    /* AIPS-2 End */
+
+    /* AIPS-1 Begin */
+
+    FSL_IMX7_CSU_ADDR             = 0x303E0000,
+    FSL_IMX7_CSU_SIZE             = (64 * KiB),
+
+    FSL_IMX7_RDC_ADDR             = 0x303D0000,
+    FSL_IMX7_RDC_SIZE             = (4 * KiB),
+
+    FSL_IMX7_SEMAPHORE2_ADDR      = 0x303C0000,
+    FSL_IMX7_SEMAPHORE1_ADDR      = 0x303B0000,
+    FSL_IMX7_SEMAPHOREn_SIZE      = (4 * KiB),
+
+    FSL_IMX7_GPC_ADDR             = 0x303A0000,
+
+    FSL_IMX7_SRC_ADDR             = 0x30390000,
+    FSL_IMX7_SRC_SIZE             = (4 * KiB),
+
+    FSL_IMX7_CCM_ADDR             = 0x30380000,
+
+    FSL_IMX7_SNVS_HP_ADDR         = 0x30370000,
+
+    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
+
+    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
+    FSL_IMX7_OCOTP_SIZE           = 0x10000,
+
+    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
+    FSL_IMX7_IOMUXC_GPR_SIZE      = (4 * KiB),
+
+    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
+    FSL_IMX7_IOMUXC_SIZE          = (4 * KiB),
+
+    FSL_IMX7_KPP_ADDR             = 0x30320000,
+    FSL_IMX7_KPP_SIZE             = (4 * KiB),
+
+    FSL_IMX7_ROMCP_ADDR           = 0x30310000,
+    FSL_IMX7_ROMCP_SIZE           = (4 * KiB),
+
+    FSL_IMX7_GPT4_ADDR            = 0x30300000,
+    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
+    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
+    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
+
+    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
+    FSL_IMX7_IOMUXC_LPSR_SIZE     = (4 * KiB),
+
+    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
+    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
+    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
+    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
+
+    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+
+    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
+    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
+    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
+    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
+    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
+    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
+    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
+
+    FSL_IMX7_AIPS1_CONF_ADDR      = 0x301F0000,
+    FSL_IMX7_AIPS1_CONF_SIZE      = (64 * KiB),
 
-    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
     FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
+    FSL_IMX7_A7MPCORE_DAP_SIZE    = (1 * MiB),
 
-    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
-    FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
+    /* AIPS-1 End */
 
-    FSL_IMX7_GPR_ADDR             = 0x30340000,
+    FSL_IMX7_EIM_CS0_ADDR         = 0x28000000,
+    FSL_IMX7_EIM_CS0_SIZE         = (128 * MiB),
 
-    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
-    FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
+    FSL_IMX7_OCRAM_PXP_ADDR       = 0x00940000,
+    FSL_IMX7_OCRAM_PXP_SIZE       = (32 * KiB),
+
+    FSL_IMX7_OCRAM_EPDC_ADDR      = 0x00920000,
+    FSL_IMX7_OCRAM_EPDC_SIZE      = (128 * KiB),
+
+    FSL_IMX7_OCRAM_MEM_ADDR       = 0x00900000,
+    FSL_IMX7_OCRAM_MEM_SIZE       = (128 * KiB),
+
+    FSL_IMX7_TCMU_ADDR            = 0x00800000,
+    FSL_IMX7_TCMU_SIZE            = (32 * KiB),
+
+    FSL_IMX7_TCML_ADDR            = 0x007F8000,
+    FSL_IMX7_TCML_SIZE            = (32 * KiB),
+
+    FSL_IMX7_OCRAM_S_ADDR         = 0x00180000,
+    FSL_IMX7_OCRAM_S_SIZE         = (32 * KiB),
+
+    FSL_IMX7_CAAM_MEM_ADDR        = 0x00100000,
+    FSL_IMX7_CAAM_MEM_SIZE        = (32 * KiB),
+
+    FSL_IMX7_ROM_ADDR             = 0x00000000,
+    FSL_IMX7_ROM_SIZE             = (96 * KiB),
 };
 
 enum FslIMX7IRQs {
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     char name[NAME_SIZE];
     int i;
 
+    /*
+     * CPUs
+     */
     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
         snprintf(name, NAME_SIZE, "cpu%d", i);
         object_initialize_child(obj, name, &s->cpu[i],
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
                             TYPE_A15MPCORE_PRIV);
 
     /*
-     * GPIOs 1 to 7
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * GPT1, 2, 3, 4
+     * GPTs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      */
     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
         object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
     }
 
-
+    /*
+     * I2Cs
+     */
     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
         object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
             snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      */
     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
             snprintf(name, NAME_SIZE, "eth%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * SDHCI
+     * SDHCIs
      */
     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
             snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
             snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      */
     object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
 
+    /*
+     * PCIE
+     */
     object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
         snprintf(name, NAME_SIZE, "usb%d", i);
         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    /*
+     * CPUs
+     */
     for (i = 0; i < smp_cpus; i++) {
         o = OBJECT(&s->cpu[i]);
 
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      * A7MPCORE DAP
      */
     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
-                                0x100000);
+                                FSL_IMX7_A7MPCORE_DAP_SIZE);
 
     /*
-     * GPT1, 2, 3, 4
+     * GPTs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX7_GPTn_IRQ[i]));
     }
 
+    /*
+     * GPIOs
+     */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
             FSL_IMX7_GPIO1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     /*
      * IOMUXC and IOMUXC_LPSR
      */
-    for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
-        static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
-            FSL_IMX7_IOMUXC_ADDR,
-            FSL_IMX7_IOMUXC_LPSR_ADDR,
-        };
-
-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
-        create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
-                                    FSL_IMX7_IOMUXCn_SIZE);
-    }
+    create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
+                                FSL_IMX7_IOMUXC_SIZE);
+    create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
+                                FSL_IMX7_IOMUXC_LPSR_SIZE);
 
     /*
      * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
 
-    /* Initialize all ECSPI */
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
             FSL_IMX7_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX7_SPIn_IRQ[i]));
     }
 
+    /*
+     * I2Cs
+     */
     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
             FSL_IMX7_I2C1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      *
      * We must use two loops since phy_connected affects the other interface
      * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * USDHC
+     * USDHCs
      */
     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      * SNVS
      */
     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
 
     /*
      * SRC
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
 
     /*
-     * PWM
+     * PWMs
      */
-    create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
+        static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
+            FSL_IMX7_PWM1_ADDR,
+            FSL_IMX7_PWM2_ADDR,
+            FSL_IMX7_PWM3_ADDR,
+            FSL_IMX7_PWM4_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "pwm%d", i);
+        create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
+                                    FSL_IMX7_PWMn_SIZE);
+    }
 
     /*
-     * CAN
+     * CANs
      */
-    create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
-    create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
+        static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
+            FSL_IMX7_CAN1_ADDR,
+            FSL_IMX7_CAN2_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "can%d", i);
+        create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
+                                    FSL_IMX7_CANn_SIZE);
+    }
 
     /*
-     * SAI (Audio SSI (Synchronous Serial Interface))
+     * SAIs (Audio SSI (Synchronous Serial Interface))
      */
-    create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
-    create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
-    create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
+        static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
+            FSL_IMX7_SAI1_ADDR,
+            FSL_IMX7_SAI2_ADDR,
+            FSL_IMX7_SAI3_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "sai%d", i);
+        create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
+                                    FSL_IMX7_SAIn_SIZE);
+    }
 
     /*
      * OCOTP
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
                                 FSL_IMX7_OCOTP_SIZE);
 
+    /*
+     * GPR
+     */
     sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
 
+    /*
+     * PCIE
+     */
     sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
 
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
 
-
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
             FSL_IMX7_USBMISC1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      */
     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                 FSL_IMX7_PCIE_PHY_SIZE);
+
 }
 
 static Property fsl_imx7_properties[] = {
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h |  7 +++++
 hw/arm/fsl-imx7.c         | 63 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
     IMX7GPRState       gpr;
     ChipideaState      usb[FSL_IMX7_NUM_USBS];
     DesignwarePCIEHost pcie;
+    MemoryRegion       rom;
+    MemoryRegion       caam;
+    MemoryRegion       ocram;
+    MemoryRegion       ocram_epdc;
+    MemoryRegion       ocram_pxp;
+    MemoryRegion       ocram_s;
+
     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
     bool               phy_connected[FSL_IMX7_NUM_ETHS];
 };
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                 FSL_IMX7_PCIE_PHY_SIZE);
 
+    /*
+     * CSU
+     */
+    create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
+                                FSL_IMX7_CSU_SIZE);
+
+    /*
+     * TZASC
+     */
+    create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
+                                FSL_IMX7_TZASC_SIZE);
+
+    /*
+     * OCRAM memory
+     */
+    memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
+                           FSL_IMX7_OCRAM_MEM_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
+                                &s->ocram);
+
+    /*
+     * OCRAM EPDC memory
+     */
+    memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
+                           FSL_IMX7_OCRAM_EPDC_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
+                                &s->ocram_epdc);
+
+    /*
+     * OCRAM PXP memory
+     */
+    memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
+                           FSL_IMX7_OCRAM_PXP_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
+                                &s->ocram_pxp);
+
+    /*
+     * OCRAM_S memory
+     */
+    memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
+                           FSL_IMX7_OCRAM_S_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
+                                &s->ocram_s);
+
+    /*
+     * ROM memory
+     */
+    memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
+                           FSL_IMX7_ROM_SIZE, &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
+                                &s->rom);
+
+    /*
+     * CAAM memory
+     */
+    memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
+                           FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
+                                &s->caam);
 }
 
 static Property fsl_imx7_properties[] = {
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

The SRC device is normally used to start the secondary CPU.

When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
is installing at boot time and therefore the fact that the SRC device is
unimplemented is hidden as Qemu respond directly to PSCI requets without
using the SRC device.

But if you try to run a more bare metal application (maybe uboot itself),
then it is not possible to start the secondary CPU as the SRC is an
unimplemented device.

This patch adds the ability to start the secondary CPU through the SRC
device so that you can use this feature in bare metal applications.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h  |   3 +-
 include/hw/misc/imx7_src.h |  66 +++++++++
 hw/arm/fsl-imx7.c          |   8 +-
 hw/misc/imx7_src.c         | 276 +++++++++++++++++++++++++++++++++++++
 hw/misc/meson.build        |   1 +
 hw/misc/trace-events       |   4 +
 6 files changed, 356 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/imx7_src.h
 create mode 100644 hw/misc/imx7_src.c

The architecture requires (R_TYTWB) that an attempt to return from EL3
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
enforces that the CPU can't ever be executing below EL3 with the
NSE,NS bits indicating an invalid security state.)

We were missing this check; add it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
---
 target/arm/tcg/helper-a64.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
         spsr &= ~PSTATE_SS;
     }
 
+    /*
+     * FEAT_RME forbids return from EL3 with an invalid security state.
+     * We don't need an explicit check for FEAT_RME here because we enforce
+     * in scr_write() that you can't set the NSE bit without it.
+     */
+    if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
+        goto illegal_return;
+    }
+
     new_el = el_from_spsr(spsr);
     if (new_el == -1) {
         goto illegal_return;
-- 
2.34.1

In the aspeed_rtc device we store a difference between two time_t
values in an 'int'. This is not really correct when time_t could
be 64 bits. Enlarge the field to 'int64_t'.

This is a migration compatibility break for the aspeed boards.
While we are changing the vmstate, remove the accidental
duplicate of the offset field.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/rtc/aspeed_rtc.h | 2 +-
 hw/rtc/aspeed_rtc.c         | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/rtc/aspeed_rtc.h
+++ b/include/hw/rtc/aspeed_rtc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
     qemu_irq irq;
 
     uint32_t reg[0x18];
-    int offset;
+    int64_t offset;
 
 };
 
diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/rtc/aspeed_rtc.c
+++ b/hw/rtc/aspeed_rtc.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
 
 static const VMStateDescription vmstate_aspeed_rtc = {
     .name = TYPE_ASPEED_RTC,
-    .version_id = 1,
+    .version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
-        VMSTATE_INT32(offset, AspeedRtcState),
-        VMSTATE_INT32(offset, AspeedRtcState),
+        VMSTATE_INT64(offset, AspeedRtcState),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
2.34.1

The functions qemu_get_timedate() and qemu_timedate_diff() take
and return a time offset as an integer. Coverity points out that
means that when an RTC device implementation holds an offset
as a time_t, as the m48t59 does, the time_t will get truncated.
(CID 1507157, 1517772).

The functions work with time_t internally, so make them use that type
in their APIs.

Note that this won't help any Y2038 issues where either the device
model itself is keeping the offset in a 32-bit integer, or where the
hardware under emulation has Y2038 or other rollover problems.  If we
missed any cases of the former then hopefully Coverity will warn us
about them since after this patch we'd be truncating a time_t in
assignments from qemu_timedate_diff().)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/sysemu/rtc.h | 4 ++--
 softmmu/rtc.c        | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/rtc.h
+++ b/include/sysemu/rtc.h
@@ -XXX,XX +XXX,XX @@
  * The behaviour of the clock whose value this function returns will
  * depend on the -rtc command line option passed by the user.
  */
-void qemu_get_timedate(struct tm *tm, int offset);
+void qemu_get_timedate(struct tm *tm, time_t offset);
 
 /**
  * qemu_timedate_diff: Return difference between a struct tm and the RTC
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
  * a timestamp one hour further ahead than the current RTC time
  * then this function will return 3600.
  */
-int qemu_timedate_diff(struct tm *tm);
+time_t qemu_timedate_diff(struct tm *tm);
 
 #endif
diff --git a/softmmu/rtc.c b/softmmu/rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/softmmu/rtc.c
+++ b/softmmu/rtc.c
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
     return value;
 }
 
-void qemu_get_timedate(struct tm *tm, int offset)
+void qemu_get_timedate(struct tm *tm, time_t offset)
 {
     time_t ti = qemu_ref_timedate(rtc_clock);
 
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
     }
 }
 
-int qemu_timedate_diff(struct tm *tm)
+time_t qemu_timedate_diff(struct tm *tm)
 {
     time_t seconds;
 
-- 
2.34.1

Where architecturally one ARM_FEATURE_X flag implies another
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
set Y for it.  Currently we do this in two places -- we set a few
flags in arm_cpu_post_init() because we need them to decide which
properties to create on the CPU object, and then we do the rest in
arm_cpu_realizefn().  However, this is fragile, because it's easy to
add a new property and not notice that this means that an X-implies-Y
check now has to move from realize to post-init.

As a specific example, the pmsav7-dregion property is conditional
on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
rely on V8-implies-V7, which doesn't happen until the realizefn.

Move all of these X-implies-Y checks into a new function, which
we call at the top of arm_cpu_post_init(), so the feature bits
are available at that point.

This does now give us the reverse issue, that if there's a feature
bit which is enabled or disabled by the setting of a property then
then X-implies-Y features that are dependent on that property need to
be in realize, not in this new function.  But the only one of those
is the "EL3 implies VBAR" which is already in the right place, so
putting things this way round seems better to me.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
---
 target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
 1 file changed, 97 insertions(+), 82 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
       NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
 }
 
+static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
+{
+    CPUARMState *env = &cpu->env;
+    bool no_aa32 = false;
+
+    /*
+     * Some features automatically imply others: set the feature
+     * bits explicitly for these cases.
+     */
+
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_PMSA);
+    }
+
+    if (arm_feature(env, ARM_FEATURE_V8)) {
+        if (arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V7);
+        } else {
+            set_feature(env, ARM_FEATURE_V7VE);
+        }
+    }
+
+    /*
+     * There exist AArch64 cpus without AArch32 support.  When KVM
+     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
+     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
+     * As a general principle, we also do not make ID register
+     * consistency checks anywhere unless using TCG, because only
+     * for TCG would a consistency-check failure be a QEMU bug.
+     */
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
+    }
+
+    if (arm_feature(env, ARM_FEATURE_V7VE)) {
+        /*
+         * v7 Virtualization Extensions. In real hardware this implies
+         * EL2 and also the presence of the Security Extensions.
+         * For QEMU, for backwards-compatibility we implement some
+         * CPUs or CPU configs which have no actual EL2 or EL3 but do
+         * include the various other features that V7VE implies.
+         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
+         * Security Extensions is ARM_FEATURE_EL3.
+         */
+        assert(!tcg_enabled() || no_aa32 ||
+               cpu_isar_feature(aa32_arm_div, cpu));
+        set_feature(env, ARM_FEATURE_LPAE);
+        set_feature(env, ARM_FEATURE_V7);
+    }
+    if (arm_feature(env, ARM_FEATURE_V7)) {
+        set_feature(env, ARM_FEATURE_VAPA);
+        set_feature(env, ARM_FEATURE_THUMB2);
+        set_feature(env, ARM_FEATURE_MPIDR);
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V6K);
+        } else {
+            set_feature(env, ARM_FEATURE_V6);
+        }
+
+        /*
+         * Always define VBAR for V7 CPUs even if it doesn't exist in
+         * non-EL3 configs. This is needed by some legacy boards.
+         */
+        set_feature(env, ARM_FEATURE_VBAR);
+    }
+    if (arm_feature(env, ARM_FEATURE_V6K)) {
+        set_feature(env, ARM_FEATURE_V6);
+        set_feature(env, ARM_FEATURE_MVFR);
+    }
+    if (arm_feature(env, ARM_FEATURE_V6)) {
+        set_feature(env, ARM_FEATURE_V5);
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            assert(!tcg_enabled() || no_aa32 ||
+                   cpu_isar_feature(aa32_jazelle, cpu));
+            set_feature(env, ARM_FEATURE_AUXCR);
+        }
+    }
+    if (arm_feature(env, ARM_FEATURE_V5)) {
+        set_feature(env, ARM_FEATURE_V4T);
+    }
+    if (arm_feature(env, ARM_FEATURE_LPAE)) {
+        set_feature(env, ARM_FEATURE_V7MP);
+    }
+    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
+        set_feature(env, ARM_FEATURE_CBAR);
+    }
+    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
+        !arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_THUMB_DSP);
+    }
+}
+
 void arm_cpu_post_init(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
-    /* M profile implies PMSA. We have to do this here rather than
-     * in realize with the other feature-implication checks because
-     * we look at the PMSA bit to see if we should add some properties.
+    /*
+     * Some features imply others. Figure this out now, because we
+     * are going to look at the feature bits in deciding which
+     * properties to add.
      */
-    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
-        set_feature(&cpu->env, ARM_FEATURE_PMSA);
-    }
+    arm_cpu_propagate_feature_implications(cpu);
 
     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     CPUARMState *env = &cpu->env;
     int pagebits;
     Error *local_err = NULL;
-    bool no_aa32 = false;
 
     /* Use pc-relative instructions in system-mode */
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         cpu->isar.id_isar3 = u;
     }
 
-    /* Some features automatically imply others: */
-    if (arm_feature(env, ARM_FEATURE_V8)) {
-        if (arm_feature(env, ARM_FEATURE_M)) {
-            set_feature(env, ARM_FEATURE_V7);
-        } else {
-            set_feature(env, ARM_FEATURE_V7VE);
-        }
-    }
-
-    /*
-     * There exist AArch64 cpus without AArch32 support.  When KVM
-     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
-     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
-     * As a general principle, we also do not make ID register
-     * consistency checks anywhere unless using TCG, because only
-     * for TCG would a consistency-check failure be a QEMU bug.
-     */
-    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
-        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
-    }
-
-    if (arm_feature(env, ARM_FEATURE_V7VE)) {
-        /* v7 Virtualization Extensions. In real hardware this implies
-         * EL2 and also the presence of the Security Extensions.
-         * For QEMU, for backwards-compatibility we implement some
-         * CPUs or CPU configs which have no actual EL2 or EL3 but do
-         * include the various other features that V7VE implies.
-         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
-         * Security Extensions is ARM_FEATURE_EL3.
-         */
-        assert(!tcg_enabled() || no_aa32 ||
-               cpu_isar_feature(aa32_arm_div, cpu));
-        set_feature(env, ARM_FEATURE_LPAE);
-        set_feature(env, ARM_FEATURE_V7);
-    }
-    if (arm_feature(env, ARM_FEATURE_V7)) {
-        set_feature(env, ARM_FEATURE_VAPA);
-        set_feature(env, ARM_FEATURE_THUMB2);
-        set_feature(env, ARM_FEATURE_MPIDR);
-        if (!arm_feature(env, ARM_FEATURE_M)) {
-            set_feature(env, ARM_FEATURE_V6K);
-        } else {
-            set_feature(env, ARM_FEATURE_V6);
-        }
-
-        /* Always define VBAR for V7 CPUs even if it doesn't exist in
-         * non-EL3 configs. This is needed by some legacy boards.
-         */
-        set_feature(env, ARM_FEATURE_VBAR);
-    }
-    if (arm_feature(env, ARM_FEATURE_V6K)) {
-        set_feature(env, ARM_FEATURE_V6);
-        set_feature(env, ARM_FEATURE_MVFR);
-    }
-    if (arm_feature(env, ARM_FEATURE_V6)) {
-        set_feature(env, ARM_FEATURE_V5);
-        if (!arm_feature(env, ARM_FEATURE_M)) {
-            assert(!tcg_enabled() || no_aa32 ||
-                   cpu_isar_feature(aa32_jazelle, cpu));
-            set_feature(env, ARM_FEATURE_AUXCR);
-        }
-    }
-    if (arm_feature(env, ARM_FEATURE_V5)) {
-        set_feature(env, ARM_FEATURE_V4T);
-    }
-    if (arm_feature(env, ARM_FEATURE_LPAE)) {
-        set_feature(env, ARM_FEATURE_V7MP);
-    }
-    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
-        set_feature(env, ARM_FEATURE_CBAR);
-    }
-    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
-        !arm_feature(env, ARM_FEATURE_M)) {
-        set_feature(env, ARM_FEATURE_THUMB_DSP);
-    }
 
     /*
      * We rely on no XScale CPU having VFP so we can use the same bits in the
-- 
2.34.1

M-profile CPUs generally allow configuration of the number of MPU
regions that they have.  We don't currently model this, so our
implementations of some of the board models provide CPUs with the
wrong number of regions.  RTOSes like Zephyr that hardcode the
expected number of regions may therefore not run on the model if they
are set up to run on real hardware.

Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
matching the ability of hardware to configure the number of Secure
and NonSecure regions separately.  Our actual CPU implementation
doesn't currently support that, and it happens that none of the MPS
boards we model set the number of regions differently for Secure vs
NonSecure, so we provide an interface to the boards and SoCs that
won't need to change if we ever do add that functionality in future,
but make it an error to configure the two properties to different
values.

(The property name on the CPU is the somewhat misnamed-for-M-profile
"pmsav7-dregion", so we don't follow that naming convention for
the properties here. The TRM doesn't say what the CPU configuration
variable names are, so we pick something, and follow the lowercase
convention we already have for properties here.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
---
 include/hw/arm/armv7m.h |  8 ++++++++
 hw/arm/armv7m.c         | 21 +++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
  * + Property "vfp": enable VFP (forwarded to CPU object)
  * + Property "dsp": enable DSP (forwarded to CPU object)
  * + Property "enable-bitband": expose bitbanded IO
+ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
+ *   to CPU object pmsav7-dregion property; default is whatever the default
+ *   for the CPU is)
+ * + Property "mpu-s-regions": number of Secure MPU regions (default is
+ *   whatever the default for the CPU is; must currently be set to the same
+ *   value as mpu-ns-regions if the CPU implements the Security Extension)
  * + Clock input "refclk" is the external reference clock for the systick timers
  * + Clock input "cpuclk" is the main CPU clock
  */
@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
     Object *idau;
     uint32_t init_svtor;
     uint32_t init_nsvtor;
+    uint32_t mpu_ns_regions;
+    uint32_t mpu_s_regions;
     bool enable_bitband;
     bool start_powered_off;
     bool vfp;
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
         }
     }
 
+    /*
+     * Real M-profile hardware can be configured with a different number of
+     * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
+     * support that yet, so catch attempts to select that.
+     */
+    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
+        s->mpu_ns_regions != s->mpu_s_regions) {
+        error_setg(errp,
+                   "mpu-ns-regions and mpu-s-regions properties must have the same value");
+        return;
+    }
+    if (s->mpu_ns_regions != UINT_MAX &&
+        object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
+        if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
+                                      s->mpu_ns_regions, errp)) {
+            return;
+        }
+    }
+
     /*
      * Tell the CPU where the NVIC is; it will fail realize if it doesn't
      * have one. Similarly, tell the NVIC where its CPU is.
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
                      false),
     DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
     DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
+    DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
+    DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.34.1

The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
MPS2/MPS3 FPGA images don't override these except in the case of
AN547, which uses 16 MPU regions.

Define properties on the ARMSSE object for the MPU regions (using the
same names as the documented RTL configuration settings, and
following the pattern we already have for this device of using
all-caps names as the RTL does), and set them in the board code.

We don't actually need to override the default except on AN547,
but it's simpler code to have the board code set them always
rather than tracking which board subtypes want to set them to
a non-default value separately from what that value is.

Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
we now correctly use 8 MPU regions, while mps3-an547 stays at its
current 16 regions.

It's possible some guest code wrongly depended on the previous
incorrectly modeled number of memory regions. (Such guest code
should ideally check the number of regions via the MPU_TYPE
register.) The old behaviour can be obtained with additional
-global arguments to QEMU:

For mps2-an521 and mps2-an524:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16

For mps2-an505:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16

NB that the way the implementation allows this use of -global
is slightly fragile: if the board code explicitly sets the
properties on the sse-200 object, this overrides the -global
command line option. So we rely on:
 - the boards that need fixing all happen to use the SSE defaults
 - we can write the board code to only set the property if it
   is different from the default, rather than having all boards
   explicitly set the property
 - the board that does need to use a non-default value happens
   to need to set it to the same value (16) we previously used
This works, but there are some kinds of refactoring of the
mps2-tz.c code that would break the support for -global here.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
---
 include/hw/arm/armsse.h |  5 +++++
 hw/arm/armsse.c         | 16 ++++++++++++++++
 hw/arm/mps2-tz.c        | 29 +++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -XXX,XX +XXX,XX @@
  *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
  *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
  *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
+ *  + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
+ *    which set the number of MPU regions on the CPUs. If there is only one
+ *    CPU the CPU1 properties are not present.
  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
  *    which are wired to its NVIC lines 32 .. n+32
  *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
     uint32_t exp_numirq;
     uint32_t sram_addr_width;
     uint32_t init_svtor;
+    uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
+    uint32_t cpu_mpu_s[SSE_MAX_CPUS];
     bool cpu_fpu[SSE_MAX_CPUS];
     bool cpu_dsp[SSE_MAX_CPUS];
 };
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
     DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
     DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
+    DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
+    DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                 return;
             }
         }
+        if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
+                                      s->cpu_mpu_ns[i], errp)) {
+            return;
+        }
+        if (!object_property_set_uint(cpuobj, "mpu-s-regions",
+                                      s->cpu_mpu_s[i], errp)) {
+            return;
+        }
 
         if (i > 0) {
             memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
     int uart_overflow_irq; /* number of the combined UART overflow IRQ */
     uint32_t init_svtor; /* init-svtor setting for SSE */
     uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
+    uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
+    uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
+    uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
+    uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
     const RAMInfo *raminfo;
     const char *armsse_type;
     uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
 #define MPS3_DDR_SIZE (2 * GiB)
 #endif
 
+/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
+#define MPU_REGION_DEFAULT UINT32_MAX
+
 static const uint32_t an505_oscclk[] = {
     40000000,
     24580000,
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                              OBJECT(system_memory), &error_abort);
     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
     qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
+    if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
+        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
+    }
+    if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
+        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
+    }
+    if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
+        if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
+            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
+        }
+        if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
+            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
+        }
+    }
     qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
     qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
     qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
+    MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 
     mc->init = mps2tz_common_init;
     mc->reset = mps2_machine_reset;
     iic->check = mps2_tz_idau_check;
+
+    /* Most machines leave these at the SSE defaults */
+    mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
+    mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
+    mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
+    mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
 }
 
 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
     mmc->numirq = 96;
     mmc->uart_overflow_irq = 48;
     mmc->init_svtor = 0x00000000;
+    mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
     mmc->sram_addr_width = 21;
     mmc->raminfo = an547_raminfo;
     mmc->armsse_type = TYPE_SSE300;
-- 
2.34.1