1 | The following changes since commit 61fee7f45955cd0bf9b79be9fa9c7ebabb5e6a85: | 1 | Hi; here's the latest round of arm patches. I have included also |
---|---|---|---|
2 | my patchset for the RTC devices to avoid keeping time_t and | ||
3 | time_t diffs in 32-bit variables. | ||
2 | 4 | ||
3 | Merge remote-tracking branch 'remotes/philmd-gitlab/tags/acceptance-testing-20200622' into staging (2020-06-22 20:50:10 +0100) | 5 | thanks |
6 | -- PMM | ||
7 | |||
8 | The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c: | ||
9 | |||
10 | Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400) | ||
4 | 11 | ||
5 | are available in the Git repository at: | 12 | are available in the Git repository at: |
6 | 13 | ||
7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200623 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831 |
8 | 15 | ||
9 | for you to fetch changes up to 539533b85fbd269f777bed931de8ccae1dd837e9: | 16 | for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb: |
10 | 17 | ||
11 | arm/virt: Add memory hot remove support (2020-06-23 11:39:48 +0100) | 18 | hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100) |
12 | 19 | ||
13 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
14 | target-arm queue: | 21 | target-arm queue: |
15 | * util/oslib-posix : qemu_init_exec_dir implementation for Mac | 22 | * Some of the preliminary patches for Cortex-A710 support |
16 | * target/arm: Last parts of neon decodetree conversion | 23 | * i.MX7 and i.MX6UL refactoring |
17 | * hw/arm/virt: Add 5.0 HW compat props | 24 | * Implement SRC device for i.MX7 |
18 | * hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status | 25 | * Catch illegal-exception-return from EL3 with bad NSE/NS |
19 | * mps2: Add CMSDK APB watchdog, FPGAIO block, S2I devices and I2C devices | 26 | * Use 64-bit offsets for holding time_t differences in RTC devices |
20 | * mps2: Add some unimplemented-device stubs for audio and GPIO | 27 | * Model correct number of MPU regions for an505, an521, an524 boards |
21 | * mps2-tz: Use the ARM SBCon two-wire serial bus interface | ||
22 | * target/arm: Check supported KVM features globally (not per vCPU) | ||
23 | * tests/qtest/arm-cpu-features: Add feature setting tests | ||
24 | * arm/virt: Add memory hot remove support | ||
25 | 28 | ||
26 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
27 | Andrew Jones (2): | 30 | Alex Bennée (1): |
28 | hw/arm/virt: Add 5.0 HW compat props | 31 | target/arm: properly document FEAT_CRC32 |
29 | tests/qtest/arm-cpu-features: Add feature setting tests | ||
30 | 32 | ||
31 | David CARLIER (1): | 33 | Jean-Christophe Dubois (6): |
32 | util/oslib-posix : qemu_init_exec_dir implementation for Mac | 34 | Remove i.MX7 IOMUX GPR device from i.MX6UL |
35 | Refactor i.MX6UL processor code | ||
36 | Add i.MX6UL missing devices. | ||
37 | Refactor i.MX7 processor code | ||
38 | Add i.MX7 missing TZ devices and memory regions | ||
39 | Add i.MX7 SRC device implementation | ||
33 | 40 | ||
34 | Peter Maydell (23): | 41 | Peter Maydell (8): |
35 | target/arm: Convert Neon 2-reg-misc VREV64 to decodetree | 42 | target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS |
36 | target/arm: Convert Neon 2-reg-misc pairwise ops to decodetree | 43 | hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm() |
37 | target/arm: Convert VZIP, VUZP to decodetree | 44 | hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec |
38 | target/arm: Convert Neon narrowing moves to decodetree | 45 | hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference |
39 | target/arm: Convert Neon 2-reg-misc VSHLL to decodetree | 46 | rtc: Use time_t for passing and returning time offsets |
40 | target/arm: Convert Neon VCVT f16/f32 insns to decodetree | 47 | target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init |
41 | target/arm: Convert vectorised 2-reg-misc Neon ops to decodetree | 48 | hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties |
42 | target/arm: Convert Neon 2-reg-misc crypto operations to decodetree | 49 | hw/arm: Set number of MPU regions correctly for an505, an521, an524 |
43 | target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFn | ||
44 | target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefs | ||
45 | target/arm: Make gen_swap_half() take separate src and dest | ||
46 | target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree | ||
47 | target/arm: Convert remaining simple 2-reg-misc Neon ops | ||
48 | target/arm: Convert Neon VQABS, VQNEG to decodetree | ||
49 | target/arm: Convert simple fp Neon 2-reg-misc insns | ||
50 | target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree | ||
51 | target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree | ||
52 | target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree | ||
53 | target/arm: Convert Neon VSWP to decodetree | ||
54 | target/arm: Convert Neon VTRN to decodetree | ||
55 | target/arm: Move some functions used only in translate-neon.inc.c to that file | ||
56 | target/arm: Remove unnecessary gen_io_end() calls | ||
57 | target/arm: Remove dead code relating to SABA and UABA | ||
58 | 50 | ||
59 | Philippe Mathieu-Daudé (15): | 51 | Richard Henderson (9): |
60 | hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status | 52 | target/arm: Reduce dcz_blocksize to uint8_t |
61 | hw/i2c/versatile_i2c: Add definitions for register addresses | 53 | target/arm: Allow cpu to configure GM blocksize |
62 | hw/i2c/versatile_i2c: Add SCL/SDA definitions | 54 | target/arm: Support more GM blocksizes |
63 | hw/i2c: Add header for ARM SBCon two-wire serial bus interface | 55 | target/arm: When tag memory is not present, set MTE=1 |
64 | hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string | 56 | target/arm: Introduce make_ccsidr64 |
65 | hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections | 57 | target/arm: Apply access checks to neoverse-n1 special registers |
66 | hw/arm/mps2: Rename CMSDK AHB peripheral region | 58 | target/arm: Apply access checks to neoverse-v1 special registers |
67 | hw/arm/mps2: Add CMSDK APB watchdog device | 59 | target/arm: Suppress FEAT_TRBE (Trace Buffer Extension) |
68 | hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices | 60 | target/arm: Implement FEAT_HPDS2 as a no-op |
69 | hw/arm/mps2: Map the FPGA I/O block | ||
70 | hw/arm/mps2: Add SPI devices | ||
71 | hw/arm/mps2: Add I2C devices | ||
72 | hw/arm/mps2: Add audio I2S interface as unimplemented device | ||
73 | hw/arm/mps2-tz: Use the ARM SBCon two-wire serial bus interface | ||
74 | target/arm: Check supported KVM features globally (not per vCPU) | ||
75 | 61 | ||
76 | Shameer Kolothum (1): | 62 | docs/system/arm/emulation.rst | 2 + |
77 | arm/virt: Add memory hot remove support | 63 | include/hw/arm/armsse.h | 5 + |
64 | include/hw/arm/armv7m.h | 8 + | ||
65 | include/hw/arm/fsl-imx6ul.h | 158 ++++++++++++++++--- | ||
66 | include/hw/arm/fsl-imx7.h | 338 ++++++++++++++++++++++++++++++----------- | ||
67 | include/hw/misc/imx7_src.h | 66 ++++++++ | ||
68 | include/hw/rtc/aspeed_rtc.h | 2 +- | ||
69 | include/sysemu/rtc.h | 4 +- | ||
70 | target/arm/cpregs.h | 2 + | ||
71 | target/arm/cpu.h | 5 +- | ||
72 | target/arm/internals.h | 6 - | ||
73 | target/arm/tcg/translate.h | 2 + | ||
74 | hw/arm/armsse.c | 16 ++ | ||
75 | hw/arm/armv7m.c | 21 +++ | ||
76 | hw/arm/fsl-imx6ul.c | 174 +++++++++++++-------- | ||
77 | hw/arm/fsl-imx7.c | 201 +++++++++++++++++++----- | ||
78 | hw/arm/mps2-tz.c | 29 ++++ | ||
79 | hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++ | ||
80 | hw/rtc/aspeed_rtc.c | 5 +- | ||
81 | hw/rtc/m48t59.c | 2 +- | ||
82 | hw/rtc/twl92230.c | 4 +- | ||
83 | softmmu/rtc.c | 4 +- | ||
84 | target/arm/cpu.c | 207 ++++++++++++++----------- | ||
85 | target/arm/helper.c | 15 +- | ||
86 | target/arm/tcg/cpu32.c | 2 +- | ||
87 | target/arm/tcg/cpu64.c | 102 +++++++++---- | ||
88 | target/arm/tcg/helper-a64.c | 9 ++ | ||
89 | target/arm/tcg/mte_helper.c | 90 ++++++++--- | ||
90 | target/arm/tcg/translate-a64.c | 5 +- | ||
91 | hw/misc/meson.build | 1 + | ||
92 | hw/misc/trace-events | 4 + | ||
93 | 31 files changed, 1393 insertions(+), 372 deletions(-) | ||
94 | create mode 100644 include/hw/misc/imx7_src.h | ||
95 | create mode 100644 hw/misc/imx7_src.c | ||
78 | 96 | ||
79 | include/hw/i2c/arm_sbcon_i2c.h | 35 ++ | ||
80 | target/arm/cpu.h | 2 +- | ||
81 | target/arm/kvm_arm.h | 21 +- | ||
82 | target/arm/translate.h | 8 +- | ||
83 | target/arm/neon-dp.decode | 106 ++++ | ||
84 | hw/acpi/generic_event_device.c | 29 + | ||
85 | hw/arm/mps2-tz.c | 23 +- | ||
86 | hw/arm/mps2.c | 65 ++- | ||
87 | hw/arm/realview.c | 3 +- | ||
88 | hw/arm/versatilepb.c | 3 +- | ||
89 | hw/arm/vexpress.c | 3 +- | ||
90 | hw/arm/virt.c | 63 +- | ||
91 | hw/i2c/versatile_i2c.c | 38 +- | ||
92 | hw/watchdog/cmsdk-apb-watchdog.c | 1 + | ||
93 | target/arm/cpu.c | 2 +- | ||
94 | target/arm/cpu64.c | 10 +- | ||
95 | target/arm/kvm.c | 4 +- | ||
96 | target/arm/kvm64.c | 14 +- | ||
97 | target/arm/translate-a64.c | 20 +- | ||
98 | target/arm/translate-neon.inc.c | 1191 +++++++++++++++++++++++++++++++++++++- | ||
99 | target/arm/translate-vfp.inc.c | 7 +- | ||
100 | target/arm/translate.c | 1064 +--------------------------------- | ||
101 | tests/qtest/arm-cpu-features.c | 38 +- | ||
102 | util/oslib-posix.c | 15 + | ||
103 | MAINTAINERS | 1 + | ||
104 | hw/arm/Kconfig | 8 +- | ||
105 | hw/watchdog/trace-events | 1 + | ||
106 | 27 files changed, 1624 insertions(+), 1151 deletions(-) | ||
107 | create mode 100644 include/hw/i2c/arm_sbcon_i2c.h | ||
108 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
2 | 1 | ||
3 | Cc: Cornelia Huck <cohuck@redhat.com> | ||
4 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
5 | Reviewed-by: Cornelia Huck <cohuck@redhat.com> | ||
6 | Message-id: 20200616140803.25515-1-drjones@redhat.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | --- | ||
9 | hw/arm/virt.c | 1 + | ||
10 | 1 file changed, 1 insertion(+) | ||
11 | |||
12 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/hw/arm/virt.c | ||
15 | +++ b/hw/arm/virt.c | ||
16 | @@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1) | ||
17 | static void virt_machine_5_0_options(MachineClass *mc) | ||
18 | { | ||
19 | virt_machine_5_1_options(mc); | ||
20 | + compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); | ||
21 | } | ||
22 | DEFINE_VIRT_MACHINE(5, 0) | ||
23 | |||
24 | -- | ||
25 | 2.20.1 | ||
26 | |||
27 | diff view generated by jsdifflib |
1 | Since commit ba3e7926691ed3 it has been unnecessary for target code | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | to call gen_io_end() after an IO instruction in icount mode; it is | ||
3 | sufficient to call gen_io_start() before it and to force the end of | ||
4 | the TB. | ||
5 | 2 | ||
6 | Many now-unnecessary calls to gen_io_end() were removed in commit | 3 | This value is only 4 bits wide. |
7 | 9e9b10c6491153b, but some were missed or accidentally added later. | ||
8 | Remove unneeded calls from the arm target: | ||
9 | 4 | ||
10 | * the call in the handling of exception-return-via-LDM is | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | unnecessary, and the code is already forcing end-of-TB | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
12 | * the call in the VFP access check code is more complicated: | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
13 | we weren't ending the TB, so we need to add the code to | 8 | Message-id: 20230811214031.171020-2-richard.henderson@linaro.org |
14 | force that by setting DISAS_UPDATE | ||
15 | * the doc comment for ARM_CP_IO doesn't need to mention | ||
16 | gen_io_end() any more | ||
17 | |||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> | ||
22 | Message-id: 20200619170324.12093-1-peter.maydell@linaro.org | ||
23 | --- | 10 | --- |
24 | target/arm/cpu.h | 2 +- | 11 | target/arm/cpu.h | 3 ++- |
25 | target/arm/translate-vfp.inc.c | 7 +++---- | 12 | 1 file changed, 2 insertions(+), 1 deletion(-) |
26 | target/arm/translate.c | 3 --- | ||
27 | 3 files changed, 4 insertions(+), 8 deletions(-) | ||
28 | 13 | ||
29 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
30 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
31 | --- a/target/arm/cpu.h | 16 | --- a/target/arm/cpu.h |
32 | +++ b/target/arm/cpu.h | 17 | +++ b/target/arm/cpu.h |
33 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) | 18 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
34 | * migration or KVM state synchronization. (Typically this is for "registers" | 19 | bool prop_lpa2; |
35 | * which are actually used as instructions for cache maintenance and so on.) | 20 | |
36 | * IO indicates that this register does I/O and therefore its accesses | 21 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ |
37 | - * need to be surrounded by gen_io_start()/gen_io_end(). In particular, | 22 | - uint32_t dcz_blocksize; |
38 | + * need to be marked with gen_io_start() and also end the TB. In particular, | 23 | + uint8_t dcz_blocksize; |
39 | * registers which implement clocks or timers require this. | 24 | + |
40 | * RAISES_EXC is for when the read or write hook might raise an exception; | 25 | uint64_t rvbar_prop; /* Property/input signals. */ |
41 | * the generated code will synchronize the CPU state before calling the hook | 26 | |
42 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c | 27 | /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ |
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/translate-vfp.inc.c | ||
45 | +++ b/target/arm/translate-vfp.inc.c | ||
46 | @@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) | ||
47 | if (s->v7m_lspact) { | ||
48 | /* | ||
49 | * Lazy state saving affects external memory and also the NVIC, | ||
50 | - * so we must mark it as an IO operation for icount. | ||
51 | + * so we must mark it as an IO operation for icount (and cause | ||
52 | + * this to be the last insn in the TB). | ||
53 | */ | ||
54 | if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | ||
55 | + s->base.is_jmp = DISAS_UPDATE; | ||
56 | gen_io_start(); | ||
57 | } | ||
58 | gen_helper_v7m_preserve_fp_state(cpu_env); | ||
59 | - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | ||
60 | - gen_io_end(); | ||
61 | - } | ||
62 | /* | ||
63 | * If the preserve_fp_state helper doesn't throw an exception | ||
64 | * then it will clear LSPACT; we don't need to repeat this for | ||
65 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/target/arm/translate.c | ||
68 | +++ b/target/arm/translate.c | ||
69 | @@ -XXX,XX +XXX,XX @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) | ||
70 | gen_io_start(); | ||
71 | } | ||
72 | gen_helper_cpsr_write_eret(cpu_env, tmp); | ||
73 | - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | ||
74 | - gen_io_end(); | ||
75 | - } | ||
76 | tcg_temp_free_i32(tmp); | ||
77 | /* Must exit loop to check un-masked IRQs */ | ||
78 | s->base.is_jmp = DISAS_EXIT; | ||
79 | -- | 28 | -- |
80 | 2.20.1 | 29 | 2.34.1 |
81 | 30 | ||
82 | 31 | diff view generated by jsdifflib |
1 | From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This adds support for memory(pc-dimm) hot remove on arm/virt that | 3 | Previously we hard-coded the blocksize with GMID_EL1_BS. |
4 | uses acpi ged device. | 4 | But the value we choose for -cpu max does not match the |
5 | 5 | value that cortex-a710 uses. | |
6 | NVDIMM hot removal is not yet supported. | 6 | |
7 | 7 | Mirror the way we handle dcz_blocksize. | |
8 | Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> | 8 | |
9 | Message-id: 20200622124157.20360-1-shameerali.kolothum.thodi@huawei.com | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Tested-by: Eric Auger <eric.auger@redhat.com> | 11 | Message-id: 20230811214031.171020-3-richard.henderson@linaro.org |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 13 | --- |
14 | hw/acpi/generic_event_device.c | 29 ++++++++++++++++ | 14 | target/arm/cpu.h | 2 ++ |
15 | hw/arm/virt.c | 62 ++++++++++++++++++++++++++++++++-- | 15 | target/arm/internals.h | 6 ----- |
16 | 2 files changed, 89 insertions(+), 2 deletions(-) | 16 | target/arm/tcg/translate.h | 2 ++ |
17 | 17 | target/arm/helper.c | 11 +++++--- | |
18 | diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c | 18 | target/arm/tcg/cpu64.c | 1 + |
19 | index XXXXXXX..XXXXXXX 100644 | 19 | target/arm/tcg/mte_helper.c | 46 ++++++++++++++++++++++------------ |
20 | --- a/hw/acpi/generic_event_device.c | 20 | target/arm/tcg/translate-a64.c | 5 ++-- |
21 | +++ b/hw/acpi/generic_event_device.c | 21 | 7 files changed, 45 insertions(+), 28 deletions(-) |
22 | @@ -XXX,XX +XXX,XX @@ static void acpi_ged_device_plug_cb(HotplugHandler *hotplug_dev, | 22 | |
23 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
24 | index XXXXXXX..XXXXXXX 100644 | ||
25 | --- a/target/arm/cpu.h | ||
26 | +++ b/target/arm/cpu.h | ||
27 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { | ||
28 | |||
29 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ | ||
30 | uint8_t dcz_blocksize; | ||
31 | + /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ | ||
32 | + uint8_t gm_blocksize; | ||
33 | |||
34 | uint64_t rvbar_prop; /* Property/input signals. */ | ||
35 | |||
36 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/internals.h | ||
39 | +++ b/target/arm/internals.h | ||
40 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs); | ||
41 | |||
42 | #endif /* !CONFIG_USER_ONLY */ | ||
43 | |||
44 | -/* | ||
45 | - * The log2 of the words in the tag block, for GMID_EL1.BS. | ||
46 | - * The is the maximum, 256 bytes, which manipulates 64-bits of tags. | ||
47 | - */ | ||
48 | -#define GMID_EL1_BS 6 | ||
49 | - | ||
50 | /* | ||
51 | * SVE predicates are 1/8 the size of SVE vectors, and cannot use | ||
52 | * the same simd_desc() encoding due to restrictions on size. | ||
53 | diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/target/arm/tcg/translate.h | ||
56 | +++ b/target/arm/tcg/translate.h | ||
57 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
58 | int8_t btype; | ||
59 | /* A copy of cpu->dcz_blocksize. */ | ||
60 | uint8_t dcz_blocksize; | ||
61 | + /* A copy of cpu->gm_blocksize. */ | ||
62 | + uint8_t gm_blocksize; | ||
63 | /* True if this page is guarded. */ | ||
64 | bool guarded_page; | ||
65 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ | ||
66 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/helper.c | ||
69 | +++ b/target/arm/helper.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = { | ||
71 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, | ||
72 | .access = PL1_RW, .accessfn = access_mte, | ||
73 | .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, | ||
74 | - { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | ||
75 | - .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | ||
76 | - .access = PL1_R, .accessfn = access_aa64_tid5, | ||
77 | - .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, | ||
78 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | ||
79 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | ||
80 | .type = ARM_CP_NO_RAW, | ||
81 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
82 | * then define only a RAZ/WI version of PSTATE.TCO. | ||
83 | */ | ||
84 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
85 | + ARMCPRegInfo gmid_reginfo = { | ||
86 | + .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | ||
87 | + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | ||
88 | + .access = PL1_R, .accessfn = access_aa64_tid5, | ||
89 | + .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, | ||
90 | + }; | ||
91 | + define_one_arm_cp_reg(cpu, &gmid_reginfo); | ||
92 | define_arm_cp_regs(cpu, mte_reginfo); | ||
93 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
94 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { | ||
95 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
96 | index XXXXXXX..XXXXXXX 100644 | ||
97 | --- a/target/arm/tcg/cpu64.c | ||
98 | +++ b/target/arm/tcg/cpu64.c | ||
99 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
100 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | ||
101 | cpu->dcz_blocksize = 7; /* 512 bytes */ | ||
102 | #endif | ||
103 | + cpu->gm_blocksize = 6; /* 256 bytes */ | ||
104 | |||
105 | cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); | ||
106 | cpu->sme_vq.supported = SVE_VQ_POW2_MAP; | ||
107 | diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c | ||
108 | index XXXXXXX..XXXXXXX 100644 | ||
109 | --- a/target/arm/tcg/mte_helper.c | ||
110 | +++ b/target/arm/tcg/mte_helper.c | ||
111 | @@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) | ||
23 | } | 112 | } |
24 | } | 113 | } |
25 | 114 | ||
26 | +static void acpi_ged_unplug_request_cb(HotplugHandler *hotplug_dev, | 115 | -#define LDGM_STGM_SIZE (4 << GMID_EL1_BS) |
27 | + DeviceState *dev, Error **errp) | 116 | - |
28 | +{ | 117 | uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) |
29 | + AcpiGedState *s = ACPI_GED(hotplug_dev); | ||
30 | + | ||
31 | + if ((object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && | ||
32 | + !(object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)))) { | ||
33 | + acpi_memory_unplug_request_cb(hotplug_dev, &s->memhp_state, dev, errp); | ||
34 | + } else { | ||
35 | + error_setg(errp, "acpi: device unplug request for unsupported device" | ||
36 | + " type: %s", object_get_typename(OBJECT(dev))); | ||
37 | + } | ||
38 | +} | ||
39 | + | ||
40 | +static void acpi_ged_unplug_cb(HotplugHandler *hotplug_dev, | ||
41 | + DeviceState *dev, Error **errp) | ||
42 | +{ | ||
43 | + AcpiGedState *s = ACPI_GED(hotplug_dev); | ||
44 | + | ||
45 | + if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | ||
46 | + acpi_memory_unplug_cb(&s->memhp_state, dev, errp); | ||
47 | + } else { | ||
48 | + error_setg(errp, "acpi: device unplug for unsupported device" | ||
49 | + " type: %s", object_get_typename(OBJECT(dev))); | ||
50 | + } | ||
51 | +} | ||
52 | + | ||
53 | static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev) | ||
54 | { | 118 | { |
55 | AcpiGedState *s = ACPI_GED(adev); | 119 | int mmu_idx = cpu_mmu_index(env, false); |
56 | @@ -XXX,XX +XXX,XX @@ static void acpi_ged_class_init(ObjectClass *class, void *data) | 120 | uintptr_t ra = GETPC(); |
57 | dc->vmsd = &vmstate_acpi_ged; | 121 | + int gm_bs = env_archcpu(env)->gm_blocksize; |
58 | 122 | + int gm_bs_bytes = 4 << gm_bs; | |
59 | hc->plug = acpi_ged_device_plug_cb; | 123 | void *tag_mem; |
60 | + hc->unplug_request = acpi_ged_unplug_request_cb; | 124 | |
61 | + hc->unplug = acpi_ged_unplug_cb; | 125 | - ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); |
62 | 126 | + ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | |
63 | adevc->send_event = acpi_ged_send_event; | 127 | |
64 | } | 128 | /* Trap if accessing an invalid page. */ |
65 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 129 | tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, |
66 | index XXXXXXX..XXXXXXX 100644 | 130 | - LDGM_STGM_SIZE, MMU_DATA_LOAD, |
67 | --- a/hw/arm/virt.c | 131 | - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); |
68 | +++ b/hw/arm/virt.c | 132 | + gm_bs_bytes, MMU_DATA_LOAD, |
69 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, | 133 | + gm_bs_bytes / (2 * TAG_GRANULE), ra); |
134 | |||
135 | /* The tag is squashed to zero if the page does not support tags. */ | ||
136 | if (!tag_mem) { | ||
137 | return 0; | ||
70 | } | 138 | } |
71 | } | 139 | |
72 | 140 | - QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); | |
73 | +static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev, | 141 | /* |
74 | + DeviceState *dev, Error **errp) | 142 | - * We are loading 64-bits worth of tags. The ordering of elements |
75 | +{ | 143 | - * within the word corresponds to a 64-bit little-endian operation. |
76 | + VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); | 144 | + * The ordering of elements within the word corresponds to |
77 | + Error *local_err = NULL; | 145 | + * a little-endian operation. |
78 | + | 146 | */ |
79 | + if (!vms->acpi_dev) { | 147 | - return ldq_le_p(tag_mem); |
80 | + error_setg(&local_err, | 148 | + switch (gm_bs) { |
81 | + "memory hotplug is not enabled: missing acpi-ged device"); | 149 | + case 6: |
82 | + goto out; | 150 | + /* 256 bytes -> 16 tags -> 64 result bits */ |
83 | + } | 151 | + return ldq_le_p(tag_mem); |
84 | + | 152 | + default: |
85 | + if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { | 153 | + /* cpu configured with unsupported gm blocksize. */ |
86 | + error_setg(&local_err, | 154 | + g_assert_not_reached(); |
87 | + "nvdimm device hot unplug is not supported yet."); | ||
88 | + goto out; | ||
89 | + } | ||
90 | + | ||
91 | + hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev, | ||
92 | + &local_err); | ||
93 | +out: | ||
94 | + error_propagate(errp, local_err); | ||
95 | +} | ||
96 | + | ||
97 | +static void virt_dimm_unplug(HotplugHandler *hotplug_dev, | ||
98 | + DeviceState *dev, Error **errp) | ||
99 | +{ | ||
100 | + VirtMachineState *vms = VIRT_MACHINE(hotplug_dev); | ||
101 | + Error *local_err = NULL; | ||
102 | + | ||
103 | + hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err); | ||
104 | + if (local_err) { | ||
105 | + goto out; | ||
106 | + } | ||
107 | + | ||
108 | + pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms)); | ||
109 | + qdev_unrealize(dev); | ||
110 | + | ||
111 | +out: | ||
112 | + error_propagate(errp, local_err); | ||
113 | +} | ||
114 | + | ||
115 | static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev, | ||
116 | DeviceState *dev, Error **errp) | ||
117 | { | ||
118 | - error_setg(errp, "device unplug request for unsupported device" | ||
119 | - " type: %s", object_get_typename(OBJECT(dev))); | ||
120 | + if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | ||
121 | + virt_dimm_unplug_request(hotplug_dev, dev, errp); | ||
122 | + } else { | ||
123 | + error_setg(errp, "device unplug request for unsupported device" | ||
124 | + " type: %s", object_get_typename(OBJECT(dev))); | ||
125 | + } | ||
126 | +} | ||
127 | + | ||
128 | +static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev, | ||
129 | + DeviceState *dev, Error **errp) | ||
130 | +{ | ||
131 | + if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { | ||
132 | + virt_dimm_unplug(hotplug_dev, dev, errp); | ||
133 | + } else { | ||
134 | + error_setg(errp, "virt: device unplug for unsupported device" | ||
135 | + " type: %s", object_get_typename(OBJECT(dev))); | ||
136 | + } | 155 | + } |
137 | } | 156 | } |
138 | 157 | ||
139 | static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, | 158 | void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) |
140 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | 159 | { |
141 | hc->pre_plug = virt_machine_device_pre_plug_cb; | 160 | int mmu_idx = cpu_mmu_index(env, false); |
142 | hc->plug = virt_machine_device_plug_cb; | 161 | uintptr_t ra = GETPC(); |
143 | hc->unplug_request = virt_machine_device_unplug_request_cb; | 162 | + int gm_bs = env_archcpu(env)->gm_blocksize; |
144 | + hc->unplug = virt_machine_device_unplug_cb; | 163 | + int gm_bs_bytes = 4 << gm_bs; |
145 | mc->numa_mem_supported = true; | 164 | void *tag_mem; |
146 | mc->nvdimm_supported = true; | 165 | |
147 | mc->auto_enable_numa_with_memhp = true; | 166 | - ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); |
167 | + ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | ||
168 | |||
169 | /* Trap if accessing an invalid page. */ | ||
170 | tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, | ||
171 | - LDGM_STGM_SIZE, MMU_DATA_LOAD, | ||
172 | - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); | ||
173 | + gm_bs_bytes, MMU_DATA_LOAD, | ||
174 | + gm_bs_bytes / (2 * TAG_GRANULE), ra); | ||
175 | |||
176 | /* | ||
177 | * Tag store only happens if the page support tags, | ||
178 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
179 | return; | ||
180 | } | ||
181 | |||
182 | - QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); | ||
183 | /* | ||
184 | - * We are storing 64-bits worth of tags. The ordering of elements | ||
185 | - * within the word corresponds to a 64-bit little-endian operation. | ||
186 | + * The ordering of elements within the word corresponds to | ||
187 | + * a little-endian operation. | ||
188 | */ | ||
189 | - stq_le_p(tag_mem, val); | ||
190 | + switch (gm_bs) { | ||
191 | + case 6: | ||
192 | + stq_le_p(tag_mem, val); | ||
193 | + break; | ||
194 | + default: | ||
195 | + /* cpu configured with unsupported gm blocksize. */ | ||
196 | + g_assert_not_reached(); | ||
197 | + } | ||
198 | } | ||
199 | |||
200 | void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
201 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
202 | index XXXXXXX..XXXXXXX 100644 | ||
203 | --- a/target/arm/tcg/translate-a64.c | ||
204 | +++ b/target/arm/tcg/translate-a64.c | ||
205 | @@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a) | ||
206 | gen_helper_stgm(cpu_env, addr, tcg_rt); | ||
207 | } else { | ||
208 | MMUAccessType acc = MMU_DATA_STORE; | ||
209 | - int size = 4 << GMID_EL1_BS; | ||
210 | + int size = 4 << s->gm_blocksize; | ||
211 | |||
212 | clean_addr = clean_data_tbi(s, addr); | ||
213 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); | ||
214 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a) | ||
215 | gen_helper_ldgm(tcg_rt, cpu_env, addr); | ||
216 | } else { | ||
217 | MMUAccessType acc = MMU_DATA_LOAD; | ||
218 | - int size = 4 << GMID_EL1_BS; | ||
219 | + int size = 4 << s->gm_blocksize; | ||
220 | |||
221 | clean_addr = clean_data_tbi(s, addr); | ||
222 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); | ||
223 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
224 | dc->cp_regs = arm_cpu->cp_regs; | ||
225 | dc->features = env->features; | ||
226 | dc->dcz_blocksize = arm_cpu->dcz_blocksize; | ||
227 | + dc->gm_blocksize = arm_cpu->gm_blocksize; | ||
228 | |||
229 | #ifdef CONFIG_USER_ONLY | ||
230 | /* In sve_probe_page, we assume TBI is enabled. */ | ||
148 | -- | 231 | -- |
149 | 2.20.1 | 232 | 2.34.1 |
150 | |||
151 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Since commit d70c996df23f, when enabling the PMU we get: | 3 | Support all of the easy GM block sizes. |
4 | Use direct memory operations, since the pointers are aligned. | ||
4 | 5 | ||
5 | $ qemu-system-aarch64 -cpu host,pmu=on -M virt,accel=kvm,gic-version=3 | 6 | While BS=2 (16 bytes, 1 tag) is a legal setting, that requires |
6 | Segmentation fault (core dumped) | 7 | an atomic store of one nibble. This is not difficult, but there |
8 | is also no point in supporting it until required. | ||
7 | 9 | ||
8 | Thread 1 "qemu-system-aar" received signal SIGSEGV, Segmentation fault. | 10 | Note that cortex-a710 sets GM blocksize to match its cacheline |
9 | 0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588 | 11 | size of 64 bytes. I expect many implementations will also |
10 | 2588 ret = ioctl(s->fd, type, arg); | 12 | match the cacheline, which makes 16 bytes very unlikely. |
11 | (gdb) bt | ||
12 | #0 0x0000aaaaaae356d0 in kvm_ioctl (s=0x0, type=44547) at accel/kvm/kvm-all.c:2588 | ||
13 | #1 0x0000aaaaaae31568 in kvm_check_extension (s=0x0, extension=126) at accel/kvm/kvm-all.c:916 | ||
14 | #2 0x0000aaaaaafce254 in kvm_arm_pmu_supported (cpu=0xaaaaac214ab0) at target/arm/kvm.c:213 | ||
15 | #3 0x0000aaaaaafc0f94 in arm_set_pmu (obj=0xaaaaac214ab0, value=true, errp=0xffffffffe438) at target/arm/cpu.c:1111 | ||
16 | #4 0x0000aaaaab5533ac in property_set_bool (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", opaque=0xaaaaac222730, errp=0xffffffffe438) at qom/object.c:2170 | ||
17 | #5 0x0000aaaaab5512f0 in object_property_set (obj=0xaaaaac214ab0, v=0xaaaaac223a80, name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1328 | ||
18 | #6 0x0000aaaaab551e10 in object_property_parse (obj=0xaaaaac214ab0, string=0xaaaaac11b4c0 "on", name=0xaaaaac11a970 "pmu", errp=0xffffffffe438) at qom/object.c:1561 | ||
19 | #7 0x0000aaaaab54ee8c in object_apply_global_props (obj=0xaaaaac214ab0, props=0xaaaaac018e20, errp=0xaaaaabd6fd88 <error_fatal>) at qom/object.c:407 | ||
20 | #8 0x0000aaaaab1dd5a4 in qdev_prop_set_globals (dev=0xaaaaac214ab0) at hw/core/qdev-properties.c:1218 | ||
21 | #9 0x0000aaaaab1d9fac in device_post_init (obj=0xaaaaac214ab0) at hw/core/qdev.c:1050 | ||
22 | ... | ||
23 | #15 0x0000aaaaab54f310 in object_initialize_with_type (obj=0xaaaaac214ab0, size=52208, type=0xaaaaabe237f0) at qom/object.c:512 | ||
24 | #16 0x0000aaaaab54fa24 in object_new_with_type (type=0xaaaaabe237f0) at qom/object.c:687 | ||
25 | #17 0x0000aaaaab54fa80 in object_new (typename=0xaaaaabe23970 "host-arm-cpu") at qom/object.c:702 | ||
26 | #18 0x0000aaaaaaf04a74 in machvirt_init (machine=0xaaaaac0a8550) at hw/arm/virt.c:1770 | ||
27 | #19 0x0000aaaaab1e8720 in machine_run_board_init (machine=0xaaaaac0a8550) at hw/core/machine.c:1138 | ||
28 | #20 0x0000aaaaaaf95394 in qemu_init (argc=5, argv=0xffffffffea58, envp=0xffffffffea88) at softmmu/vl.c:4348 | ||
29 | #21 0x0000aaaaaada3f74 in main (argc=<optimized out>, argv=<optimized out>, envp=<optimized out>) at softmmu/main.c:48 | ||
30 | 13 | ||
31 | This is because in frame #2, cpu->kvm_state is still NULL | 14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
32 | (the vCPU is not yet realized). | 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
33 | 16 | Message-id: 20230811214031.171020-4-richard.henderson@linaro.org | |
34 | KVM has a hard requirement of all cores supporting the same | ||
35 | feature set. We only need to check if the accelerator supports | ||
36 | a feature, not each vCPU individually. | ||
37 | |||
38 | Fix by removing the 'CPUState *cpu' argument from the | ||
39 | kvm_arm_<FEATURE>_supported() functions. | ||
40 | |||
41 | Fixes: d70c996df23f ('Use CPUState::kvm_state in kvm_arm_pmu_supported') | ||
42 | Reported-by: Haibo Xu <haibo.xu@linaro.org> | ||
43 | Reviewed-by: Andrew Jones <drjones@redhat.com> | ||
44 | Acked-by: Paolo Bonzini <pbonzini@redhat.com> | ||
45 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
46 | Suggested-by: Paolo Bonzini <pbonzini@redhat.com> | ||
47 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
48 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
49 | --- | 18 | --- |
50 | target/arm/kvm_arm.h | 21 +++++++++------------ | 19 | target/arm/cpu.c | 18 +++++++++--- |
51 | target/arm/cpu.c | 2 +- | 20 | target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------ |
52 | target/arm/cpu64.c | 10 +++++----- | 21 | 2 files changed, 62 insertions(+), 12 deletions(-) |
53 | target/arm/kvm.c | 4 ++-- | ||
54 | target/arm/kvm64.c | 14 +++++--------- | ||
55 | 5 files changed, 22 insertions(+), 29 deletions(-) | ||
56 | 22 | ||
57 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/target/arm/kvm_arm.h | ||
60 | +++ b/target/arm/kvm_arm.h | ||
61 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj); | ||
62 | |||
63 | /** | ||
64 | * kvm_arm_aarch32_supported: | ||
65 | - * @cs: CPUState | ||
66 | * | ||
67 | - * Returns: true if the KVM VCPU can enable AArch32 mode | ||
68 | + * Returns: true if KVM can enable AArch32 mode | ||
69 | * and false otherwise. | ||
70 | */ | ||
71 | -bool kvm_arm_aarch32_supported(CPUState *cs); | ||
72 | +bool kvm_arm_aarch32_supported(void); | ||
73 | |||
74 | /** | ||
75 | * kvm_arm_pmu_supported: | ||
76 | - * @cs: CPUState | ||
77 | * | ||
78 | - * Returns: true if the KVM VCPU can enable its PMU | ||
79 | + * Returns: true if KVM can enable the PMU | ||
80 | * and false otherwise. | ||
81 | */ | ||
82 | -bool kvm_arm_pmu_supported(CPUState *cs); | ||
83 | +bool kvm_arm_pmu_supported(void); | ||
84 | |||
85 | /** | ||
86 | * kvm_arm_sve_supported: | ||
87 | - * @cs: CPUState | ||
88 | * | ||
89 | - * Returns true if the KVM VCPU can enable SVE and false otherwise. | ||
90 | + * Returns true if KVM can enable SVE and false otherwise. | ||
91 | */ | ||
92 | -bool kvm_arm_sve_supported(CPUState *cs); | ||
93 | +bool kvm_arm_sve_supported(void); | ||
94 | |||
95 | /** | ||
96 | * kvm_arm_get_max_vm_ipa_size: | ||
97 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) | ||
98 | |||
99 | static inline void kvm_arm_add_vcpu_properties(Object *obj) {} | ||
100 | |||
101 | -static inline bool kvm_arm_aarch32_supported(CPUState *cs) | ||
102 | +static inline bool kvm_arm_aarch32_supported(void) | ||
103 | { | ||
104 | return false; | ||
105 | } | ||
106 | |||
107 | -static inline bool kvm_arm_pmu_supported(CPUState *cs) | ||
108 | +static inline bool kvm_arm_pmu_supported(void) | ||
109 | { | ||
110 | return false; | ||
111 | } | ||
112 | |||
113 | -static inline bool kvm_arm_sve_supported(CPUState *cs) | ||
114 | +static inline bool kvm_arm_sve_supported(void) | ||
115 | { | ||
116 | return false; | ||
117 | } | ||
118 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 23 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
119 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
120 | --- a/target/arm/cpu.c | 25 | --- a/target/arm/cpu.c |
121 | +++ b/target/arm/cpu.c | 26 | +++ b/target/arm/cpu.c |
122 | @@ -XXX,XX +XXX,XX @@ static void arm_set_pmu(Object *obj, bool value, Error **errp) | 27 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
123 | ARMCPU *cpu = ARM_CPU(obj); | 28 | ID_PFR1, VIRTUALIZATION, 0); |
124 | 29 | } | |
125 | if (value) { | 30 | |
126 | - if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) { | 31 | + if (cpu_isar_feature(aa64_mte, cpu)) { |
127 | + if (kvm_enabled() && !kvm_arm_pmu_supported()) { | 32 | + /* |
128 | error_setg(errp, "'pmu' feature not supported by KVM on this host"); | 33 | + * The architectural range of GM blocksize is 2-6, however qemu |
129 | return; | 34 | + * doesn't support blocksize of 2 (see HELPER(ldgm)). |
130 | } | 35 | + */ |
131 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 36 | + if (tcg_enabled()) { |
37 | + assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); | ||
38 | + } | ||
39 | + | ||
40 | #ifndef CONFIG_USER_ONLY | ||
41 | - if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { | ||
42 | /* | ||
43 | * Disable the MTE feature bits if we do not have tag-memory | ||
44 | * provided by the machine. | ||
45 | */ | ||
46 | - cpu->isar.id_aa64pfr1 = | ||
47 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
48 | - } | ||
49 | + if (cpu->tag_memory == NULL) { | ||
50 | + cpu->isar.id_aa64pfr1 = | ||
51 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
52 | + } | ||
53 | #endif | ||
54 | + } | ||
55 | |||
56 | if (tcg_enabled()) { | ||
57 | /* | ||
58 | diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c | ||
132 | index XXXXXXX..XXXXXXX 100644 | 59 | index XXXXXXX..XXXXXXX 100644 |
133 | --- a/target/arm/cpu64.c | 60 | --- a/target/arm/tcg/mte_helper.c |
134 | +++ b/target/arm/cpu64.c | 61 | +++ b/target/arm/tcg/mte_helper.c |
135 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) | 62 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) |
136 | 63 | int gm_bs = env_archcpu(env)->gm_blocksize; | |
137 | /* Collect the set of vector lengths supported by KVM. */ | 64 | int gm_bs_bytes = 4 << gm_bs; |
138 | bitmap_zero(kvm_supported, ARM_MAX_VQ); | 65 | void *tag_mem; |
139 | - if (kvm_enabled() && kvm_arm_sve_supported(CPU(cpu))) { | 66 | + uint64_t ret; |
140 | + if (kvm_enabled() && kvm_arm_sve_supported()) { | 67 | + int shift; |
141 | kvm_arm_sve_get_vls(CPU(cpu), kvm_supported); | 68 | |
142 | } else if (kvm_enabled()) { | 69 | ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); |
143 | assert(!cpu_isar_feature(aa64_sve, cpu)); | 70 | |
144 | @@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name, | 71 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) |
72 | |||
73 | /* | ||
74 | * The ordering of elements within the word corresponds to | ||
75 | - * a little-endian operation. | ||
76 | + * a little-endian operation. Computation of shift comes from | ||
77 | + * | ||
78 | + * index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE> | ||
79 | + * data<index*4+3:index*4> = tag | ||
80 | + * | ||
81 | + * Because of the alignment of ptr above, BS=6 has shift=0. | ||
82 | + * All memory operations are aligned. Defer support for BS=2, | ||
83 | + * requiring insertion or extraction of a nibble, until we | ||
84 | + * support a cpu that requires it. | ||
85 | */ | ||
86 | switch (gm_bs) { | ||
87 | + case 3: | ||
88 | + /* 32 bytes -> 2 tags -> 8 result bits */ | ||
89 | + ret = *(uint8_t *)tag_mem; | ||
90 | + break; | ||
91 | + case 4: | ||
92 | + /* 64 bytes -> 4 tags -> 16 result bits */ | ||
93 | + ret = cpu_to_le16(*(uint16_t *)tag_mem); | ||
94 | + break; | ||
95 | + case 5: | ||
96 | + /* 128 bytes -> 8 tags -> 32 result bits */ | ||
97 | + ret = cpu_to_le32(*(uint32_t *)tag_mem); | ||
98 | + break; | ||
99 | case 6: | ||
100 | /* 256 bytes -> 16 tags -> 64 result bits */ | ||
101 | - return ldq_le_p(tag_mem); | ||
102 | + return cpu_to_le64(*(uint64_t *)tag_mem); | ||
103 | default: | ||
104 | - /* cpu configured with unsupported gm blocksize. */ | ||
105 | + /* | ||
106 | + * CPU configured with unsupported/invalid gm blocksize. | ||
107 | + * This is detected early in arm_cpu_realizefn. | ||
108 | + */ | ||
109 | g_assert_not_reached(); | ||
110 | } | ||
111 | + shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; | ||
112 | + return ret << shift; | ||
113 | } | ||
114 | |||
115 | void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
116 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
117 | int gm_bs = env_archcpu(env)->gm_blocksize; | ||
118 | int gm_bs_bytes = 4 << gm_bs; | ||
119 | void *tag_mem; | ||
120 | + int shift; | ||
121 | |||
122 | ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | ||
123 | |||
124 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
145 | return; | 125 | return; |
146 | } | 126 | } |
147 | 127 | ||
148 | - if (kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) { | 128 | - /* |
149 | + if (kvm_enabled() && !kvm_arm_sve_supported()) { | 129 | - * The ordering of elements within the word corresponds to |
150 | error_setg(errp, "cannot set sve-max-vq"); | 130 | - * a little-endian operation. |
151 | error_append_hint(errp, "SVE not supported by KVM on this host\n"); | 131 | - */ |
152 | return; | 132 | + /* See LDGM for comments on BS and on shift. */ |
153 | @@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, | 133 | + shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; |
154 | return; | 134 | + val >>= shift; |
155 | } | 135 | switch (gm_bs) { |
156 | 136 | + case 3: | |
157 | - if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) { | 137 | + /* 32 bytes -> 2 tags -> 8 result bits */ |
158 | + if (value && kvm_enabled() && !kvm_arm_sve_supported()) { | 138 | + *(uint8_t *)tag_mem = val; |
159 | error_setg(errp, "cannot enable %s", name); | 139 | + break; |
160 | error_append_hint(errp, "SVE not supported by KVM on this host\n"); | 140 | + case 4: |
161 | return; | 141 | + /* 64 bytes -> 4 tags -> 16 result bits */ |
162 | @@ -XXX,XX +XXX,XX @@ static void cpu_arm_set_sve(Object *obj, Visitor *v, const char *name, | 142 | + *(uint16_t *)tag_mem = cpu_to_le16(val); |
163 | return; | 143 | + break; |
164 | } | 144 | + case 5: |
165 | 145 | + /* 128 bytes -> 8 tags -> 32 result bits */ | |
166 | - if (value && kvm_enabled() && !kvm_arm_sve_supported(CPU(cpu))) { | 146 | + *(uint32_t *)tag_mem = cpu_to_le32(val); |
167 | + if (value && kvm_enabled() && !kvm_arm_sve_supported()) { | 147 | + break; |
168 | error_setg(errp, "'sve' feature not supported by KVM on this host"); | 148 | case 6: |
169 | return; | 149 | - stq_le_p(tag_mem, val); |
170 | } | 150 | + /* 256 bytes -> 16 tags -> 64 result bits */ |
171 | @@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) | 151 | + *(uint64_t *)tag_mem = cpu_to_le64(val); |
172 | * uniform execution state like do_interrupt. | 152 | break; |
173 | */ | 153 | default: |
174 | if (value == false) { | 154 | /* cpu configured with unsupported gm blocksize. */ |
175 | - if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) { | ||
176 | + if (!kvm_enabled() || !kvm_arm_aarch32_supported()) { | ||
177 | error_setg(errp, "'aarch64' feature cannot be disabled " | ||
178 | "unless KVM is enabled and 32-bit EL1 " | ||
179 | "is supported"); | ||
180 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
181 | index XXXXXXX..XXXXXXX 100644 | ||
182 | --- a/target/arm/kvm.c | ||
183 | +++ b/target/arm/kvm.c | ||
184 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_add_vcpu_properties(Object *obj) | ||
185 | } | ||
186 | } | ||
187 | |||
188 | -bool kvm_arm_pmu_supported(CPUState *cpu) | ||
189 | +bool kvm_arm_pmu_supported(void) | ||
190 | { | ||
191 | - return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3); | ||
192 | + return kvm_check_extension(kvm_state, KVM_CAP_ARM_PMU_V3); | ||
193 | } | ||
194 | |||
195 | int kvm_arm_get_max_vm_ipa_size(MachineState *ms) | ||
196 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
197 | index XXXXXXX..XXXXXXX 100644 | ||
198 | --- a/target/arm/kvm64.c | ||
199 | +++ b/target/arm/kvm64.c | ||
200 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
201 | return true; | ||
202 | } | ||
203 | |||
204 | -bool kvm_arm_aarch32_supported(CPUState *cpu) | ||
205 | +bool kvm_arm_aarch32_supported(void) | ||
206 | { | ||
207 | - KVMState *s = KVM_STATE(current_accel()); | ||
208 | - | ||
209 | - return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT); | ||
210 | + return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); | ||
211 | } | ||
212 | |||
213 | -bool kvm_arm_sve_supported(CPUState *cpu) | ||
214 | +bool kvm_arm_sve_supported(void) | ||
215 | { | ||
216 | - KVMState *s = KVM_STATE(current_accel()); | ||
217 | - | ||
218 | - return kvm_check_extension(s, KVM_CAP_ARM_SVE); | ||
219 | + return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); | ||
220 | } | ||
221 | |||
222 | QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN != 1); | ||
223 | @@ -XXX,XX +XXX,XX @@ int kvm_arch_init_vcpu(CPUState *cs) | ||
224 | env->features &= ~(1ULL << ARM_FEATURE_PMU); | ||
225 | } | ||
226 | if (cpu_isar_feature(aa64_sve, cpu)) { | ||
227 | - assert(kvm_arm_sve_supported(cs)); | ||
228 | + assert(kvm_arm_sve_supported()); | ||
229 | cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
230 | } | ||
231 | |||
232 | -- | 155 | -- |
233 | 2.20.1 | 156 | 2.34.1 |
234 | |||
235 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | When the cpu support MTE, but the system does not, reduce cpu |
4 | Message-id: 20200617072539.32686-14-f4bug@amsat.org | 4 | support to user instructions at EL0 instead of completely |
5 | disabling MTE. If we encounter a cpu implementation which does | ||
6 | something else, we can revisit this setting. | ||
7 | |||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Message-id: 20230811214031.171020-5-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | hw/arm/mps2.c | 1 + | 13 | target/arm/cpu.c | 7 ++++--- |
9 | 1 file changed, 1 insertion(+) | 14 | 1 file changed, 4 insertions(+), 3 deletions(-) |
10 | 15 | ||
11 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | 16 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
12 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/mps2.c | 18 | --- a/target/arm/cpu.c |
14 | +++ b/hw/arm/mps2.c | 19 | +++ b/target/arm/cpu.c |
15 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 20 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
16 | 0x4002a000}; /* Shield1 */ | 21 | |
17 | sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL); | 22 | #ifndef CONFIG_USER_ONLY |
23 | /* | ||
24 | - * Disable the MTE feature bits if we do not have tag-memory | ||
25 | - * provided by the machine. | ||
26 | + * If we do not have tag-memory provided by the machine, | ||
27 | + * reduce MTE support to instructions enabled at EL0. | ||
28 | + * This matches Cortex-A710 BROADCASTMTE input being LOW. | ||
29 | */ | ||
30 | if (cpu->tag_memory == NULL) { | ||
31 | cpu->isar.id_aa64pfr1 = | ||
32 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
33 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); | ||
34 | } | ||
35 | #endif | ||
18 | } | 36 | } |
19 | + create_unimplemented_device("i2s", 0x40024000, 0x400); | ||
20 | |||
21 | /* In hardware this is a LAN9220; the LAN9118 is software compatible | ||
22 | * except that it doesn't support the checksum-offload feature. | ||
23 | -- | 37 | -- |
24 | 2.20.1 | 38 | 2.34.1 |
25 | |||
26 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | From 'Application Note AN385', chapter 3.14: | 3 | Do not hard-code the constants for Neoverse V1. |
4 | 4 | ||
5 | The SMM implements a simple SBCon interface based on I2C. | 5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | |||
7 | There are 4 SBCon interfaces on the FPGA APB subsystem. | ||
8 | |||
9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Message-id: 20200617072539.32686-13-f4bug@amsat.org | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20230811214031.171020-6-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 9 | --- |
14 | hw/arm/mps2.c | 8 ++++++++ | 10 | target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++-------------- |
15 | hw/arm/Kconfig | 1 + | 11 | 1 file changed, 32 insertions(+), 16 deletions(-) |
16 | 2 files changed, 9 insertions(+) | ||
17 | 12 | ||
18 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | 13 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
19 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/arm/mps2.c | 15 | --- a/target/arm/tcg/cpu64.c |
21 | +++ b/hw/arm/mps2.c | 16 | +++ b/target/arm/tcg/cpu64.c |
22 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ |
23 | #include "hw/misc/mps2-scc.h" | 18 | #include "qemu/module.h" |
24 | #include "hw/misc/mps2-fpgaio.h" | 19 | #include "qapi/visitor.h" |
25 | #include "hw/ssi/pl022.h" | 20 | #include "hw/qdev-properties.h" |
26 | +#include "hw/i2c/arm_sbcon_i2c.h" | 21 | +#include "qemu/units.h" |
27 | #include "hw/net/lan9118.h" | 22 | #include "internals.h" |
28 | #include "net/net.h" | 23 | #include "cpregs.h" |
29 | #include "hw/watchdog/cmsdk-apb-watchdog.h" | 24 | |
30 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 25 | +static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize, |
31 | qdev_get_gpio_in(orgate_dev, j)); | 26 | + unsigned cachesize) |
32 | } | 27 | +{ |
33 | } | 28 | + unsigned lg_linesize = ctz32(linesize); |
34 | + for (i = 0; i < 4; i++) { | 29 | + unsigned sets; |
35 | + static const hwaddr i2cbase[] = {0x40022000, /* Touch */ | 30 | + |
36 | + 0x40023000, /* Audio */ | 31 | + /* |
37 | + 0x40029000, /* Shield0 */ | 32 | + * The 64-bit CCSIDR_EL1 format is: |
38 | + 0x4002a000}; /* Shield1 */ | 33 | + * [55:32] number of sets - 1 |
39 | + sysbus_create_simple(TYPE_ARM_SBCON_I2C, i2cbase[i], NULL); | 34 | + * [23:3] associativity - 1 |
40 | + } | 35 | + * [2:0] log2(linesize) - 4 |
41 | 36 | + * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc | |
42 | /* In hardware this is a LAN9220; the LAN9118 is software compatible | 37 | + */ |
43 | * except that it doesn't support the checksum-offload feature. | 38 | + assert(assoc != 0); |
44 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 39 | + assert(is_power_of_2(linesize)); |
45 | index XXXXXXX..XXXXXXX 100644 | 40 | + assert(lg_linesize >= 4 && lg_linesize <= 7 + 4); |
46 | --- a/hw/arm/Kconfig | 41 | + |
47 | +++ b/hw/arm/Kconfig | 42 | + /* sets * associativity * linesize == cachesize. */ |
48 | @@ -XXX,XX +XXX,XX @@ config MPS2 | 43 | + sets = cachesize / (assoc * linesize); |
49 | select SPLIT_IRQ | 44 | + assert(cachesize % (assoc * linesize) == 0); |
50 | select UNIMP | 45 | + |
51 | select CMSDK_APB_WATCHDOG | 46 | + return ((uint64_t)(sets - 1) << 32) |
52 | + select VERSATILE_I2C | 47 | + | ((assoc - 1) << 3) |
53 | 48 | + | (lg_linesize - 4); | |
54 | config FSL_IMX7 | 49 | +} |
55 | bool | 50 | + |
51 | static void aarch64_a35_initfn(Object *obj) | ||
52 | { | ||
53 | ARMCPU *cpu = ARM_CPU(obj); | ||
54 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj) | ||
55 | * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, | ||
56 | * but also says it implements CCIDX, which means they should be | ||
57 | * 64-bit format. So we here use values which are based on the textual | ||
58 | - * information in chapter 2 of the TRM (and on the fact that | ||
59 | - * sets * associativity * linesize == cachesize). | ||
60 | - * | ||
61 | - * The 64-bit CCSIDR_EL1 format is: | ||
62 | - * [55:32] number of sets - 1 | ||
63 | - * [23:3] associativity - 1 | ||
64 | - * [2:0] log2(linesize) - 4 | ||
65 | - * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc | ||
66 | - * | ||
67 | - * L1: 4-way set associative 64-byte line size, total size 64K, | ||
68 | - * so sets is 256. | ||
69 | + * information in chapter 2 of the TRM: | ||
70 | * | ||
71 | + * L1: 4-way set associative 64-byte line size, total size 64K. | ||
72 | * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. | ||
73 | - * We pick 1MB, so this has 2048 sets. | ||
74 | - * | ||
75 | * L3: No L3 (this matches the CLIDR_EL1 value). | ||
76 | */ | ||
77 | - cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */ | ||
78 | - cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */ | ||
79 | - cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */ | ||
80 | + cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ | ||
81 | + cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ | ||
82 | + cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */ | ||
83 | |||
84 | /* From 3.2.115 SCTLR_EL3 */ | ||
85 | cpu->reset_sctlr = 0x30c50838; | ||
56 | -- | 86 | -- |
57 | 2.20.1 | 87 | 2.34.1 |
58 | |||
59 | diff view generated by jsdifflib |
1 | From: David CARLIER <devnexen@gmail.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | From 3025a0ce3fdf7d3559fc35a52c659f635f5c750c Mon Sep 17 00:00:00 2001 | 3 | Access to many of the special registers is enabled or disabled |
4 | From: David Carlier <devnexen@gmail.com> | 4 | by ACTLR_EL[23], which we implement as constant 0, which means |
5 | Date: Tue, 26 May 2020 21:35:27 +0100 | 5 | that all writes outside EL3 should trap. |
6 | Subject: [PATCH] util/oslib-posix : qemu_init_exec_dir implementation for Mac | ||
7 | 6 | ||
8 | Using dyld API to get the full path of the current process. | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | |||
10 | Signed-off-by: David Carlier <devnexen@gmail.com> | ||
11 | Message-id: CA+XhMqxwC10XHVs4Z-JfE0-WLAU3ztDuU9QKVi31mjr59HWCxg@mail.gmail.com | ||
12 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Message-id: 20230811214031.171020-7-richard.henderson@linaro.org | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 11 | --- |
15 | util/oslib-posix.c | 15 +++++++++++++++ | 12 | target/arm/cpregs.h | 2 ++ |
16 | 1 file changed, 15 insertions(+) | 13 | target/arm/helper.c | 4 ++-- |
14 | target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++--------- | ||
15 | 3 files changed, 41 insertions(+), 11 deletions(-) | ||
17 | 16 | ||
18 | diff --git a/util/oslib-posix.c b/util/oslib-posix.c | 17 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h |
19 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/util/oslib-posix.c | 19 | --- a/target/arm/cpregs.h |
21 | +++ b/util/oslib-posix.c | 20 | +++ b/target/arm/cpregs.h |
22 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } |
23 | #include <lwp.h> | 22 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); |
24 | #endif | 23 | #endif |
25 | 24 | ||
26 | +#ifdef __APPLE__ | 25 | +CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool); |
27 | +#include <mach-o/dyld.h> | ||
28 | +#endif | ||
29 | + | 26 | + |
30 | #include "qemu/mmap-alloc.h" | 27 | #endif /* TARGET_ARM_CPREGS_H */ |
31 | 28 | diff --git a/target/arm/helper.c b/target/arm/helper.c | |
32 | #ifdef CONFIG_DEBUG_STACK_USAGE | 29 | index XXXXXXX..XXXXXXX 100644 |
33 | @@ -XXX,XX +XXX,XX @@ void qemu_init_exec_dir(const char *argv0) | 30 | --- a/target/arm/helper.c |
34 | p = buf; | 31 | +++ b/target/arm/helper.c |
35 | } | 32 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, |
36 | } | 33 | } |
37 | +#elif defined(__APPLE__) | 34 | |
38 | + { | 35 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ |
39 | + char fpath[PATH_MAX]; | 36 | -static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, |
40 | + uint32_t len = sizeof(fpath); | 37 | - bool isread) |
41 | + if (_NSGetExecutablePath(fpath, &len) == 0) { | 38 | +CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, |
42 | + p = realpath(fpath, buf); | 39 | + bool isread) |
43 | + if (!p) { | 40 | { |
44 | + return; | 41 | if (arm_current_el(env) == 1) { |
45 | + } | 42 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; |
43 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/tcg/cpu64.c | ||
46 | +++ b/target/arm/tcg/cpu64.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj) | ||
48 | /* TODO: Add A64FX specific HPC extension registers */ | ||
49 | } | ||
50 | |||
51 | +static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r, | ||
52 | + bool read) | ||
53 | +{ | ||
54 | + if (!read) { | ||
55 | + int el = arm_current_el(env); | ||
56 | + | ||
57 | + /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */ | ||
58 | + if (el < 2 && arm_is_el2_enabled(env)) { | ||
59 | + return CP_ACCESS_TRAP_EL2; | ||
60 | + } | ||
61 | + /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */ | ||
62 | + if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { | ||
63 | + return CP_ACCESS_TRAP_EL3; | ||
46 | + } | 64 | + } |
47 | + } | 65 | + } |
48 | #endif | 66 | + return CP_ACCESS_OK; |
49 | /* If we don't have any way of figuring out the actual executable | 67 | +} |
50 | location then try argv[0]. */ | 68 | + |
69 | static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
70 | { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, | ||
71 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, | ||
72 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
73 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
74 | + /* Traps and enables are the same as for TCR_EL1. */ | ||
75 | + .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, }, | ||
76 | { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, | ||
77 | .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, | ||
78 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
79 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
80 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
81 | { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
82 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, | ||
83 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
84 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
85 | + .accessfn = access_actlr_w }, | ||
86 | { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, | ||
87 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, | ||
88 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
89 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
90 | + .accessfn = access_actlr_w }, | ||
91 | { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, | ||
92 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, | ||
93 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
94 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
95 | + .accessfn = access_actlr_w }, | ||
96 | /* | ||
97 | * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU | ||
98 | * (and in particular its system registers). | ||
99 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
100 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, | ||
101 | { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
102 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, | ||
103 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 }, | ||
104 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010, | ||
105 | + .accessfn = access_actlr_w }, | ||
106 | { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, | ||
107 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, | ||
108 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
109 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
110 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
111 | { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
112 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, | ||
113 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
114 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
115 | + .accessfn = access_actlr_w }, | ||
116 | { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64, | ||
117 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2, | ||
118 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
119 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
120 | + .accessfn = access_actlr_w }, | ||
121 | { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64, | ||
122 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1, | ||
123 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
124 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
125 | + .accessfn = access_actlr_w }, | ||
126 | { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64, | ||
127 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, | ||
128 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
129 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
130 | + .accessfn = access_actlr_w }, | ||
131 | }; | ||
132 | |||
133 | static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) | ||
51 | -- | 134 | -- |
52 | 2.20.1 | 135 | 2.34.1 |
53 | |||
54 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the Neon VREV64 insn from the 2-reg-misc grouping to decodetree. | ||
2 | 1 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200616170844.13318-2-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/arm/neon-dp.decode | 12 ++++++++ | ||
8 | target/arm/translate-neon.inc.c | 50 +++++++++++++++++++++++++++++++++ | ||
9 | target/arm/translate.c | 24 ++-------------- | ||
10 | 3 files changed, 64 insertions(+), 22 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/neon-dp.decode | ||
15 | +++ b/target/arm/neon-dp.decode | ||
16 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
17 | vm=%vm_dp vd=%vd_dp size=1 | ||
18 | VDUP_scalar 1111 001 1 1 . 11 index:1 100 .... 11 000 q:1 . 0 .... \ | ||
19 | vm=%vm_dp vd=%vd_dp size=2 | ||
20 | + | ||
21 | + ################################################################## | ||
22 | + # 2-reg-misc grouping: | ||
23 | + # 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4 | ||
24 | + ################################################################## | ||
25 | + | ||
26 | + &2misc vd vm q size | ||
27 | + | ||
28 | + @2misc .... ... .. . .. size:2 .. .... . .... q:1 . . .... \ | ||
29 | + &2misc vm=%vm_dp vd=%vd_dp | ||
30 | + | ||
31 | + VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc | ||
32 | ] | ||
33 | |||
34 | # Subgroup for size != 0b11 | ||
35 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/translate-neon.inc.c | ||
38 | +++ b/target/arm/translate-neon.inc.c | ||
39 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VDUP_scalar *a) | ||
40 | a->q ? 16 : 8, a->q ? 16 : 8); | ||
41 | return true; | ||
42 | } | ||
43 | + | ||
44 | +static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
45 | +{ | ||
46 | + int pass, half; | ||
47 | + | ||
48 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
49 | + return false; | ||
50 | + } | ||
51 | + | ||
52 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
53 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
54 | + ((a->vd | a->vm) & 0x10)) { | ||
55 | + return false; | ||
56 | + } | ||
57 | + | ||
58 | + if ((a->vd | a->vm) & a->q) { | ||
59 | + return false; | ||
60 | + } | ||
61 | + | ||
62 | + if (a->size == 3) { | ||
63 | + return false; | ||
64 | + } | ||
65 | + | ||
66 | + if (!vfp_access_check(s)) { | ||
67 | + return true; | ||
68 | + } | ||
69 | + | ||
70 | + for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
71 | + TCGv_i32 tmp[2]; | ||
72 | + | ||
73 | + for (half = 0; half < 2; half++) { | ||
74 | + tmp[half] = neon_load_reg(a->vm, pass * 2 + half); | ||
75 | + switch (a->size) { | ||
76 | + case 0: | ||
77 | + tcg_gen_bswap32_i32(tmp[half], tmp[half]); | ||
78 | + break; | ||
79 | + case 1: | ||
80 | + gen_swap_half(tmp[half]); | ||
81 | + break; | ||
82 | + case 2: | ||
83 | + break; | ||
84 | + default: | ||
85 | + g_assert_not_reached(); | ||
86 | + } | ||
87 | + } | ||
88 | + neon_store_reg(a->vd, pass * 2, tmp[1]); | ||
89 | + neon_store_reg(a->vd, pass * 2 + 1, tmp[0]); | ||
90 | + } | ||
91 | + return true; | ||
92 | +} | ||
93 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | --- a/target/arm/translate.c | ||
96 | +++ b/target/arm/translate.c | ||
97 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
98 | } | ||
99 | switch (op) { | ||
100 | case NEON_2RM_VREV64: | ||
101 | - for (pass = 0; pass < (q ? 2 : 1); pass++) { | ||
102 | - tmp = neon_load_reg(rm, pass * 2); | ||
103 | - tmp2 = neon_load_reg(rm, pass * 2 + 1); | ||
104 | - switch (size) { | ||
105 | - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; | ||
106 | - case 1: gen_swap_half(tmp); break; | ||
107 | - case 2: /* no-op */ break; | ||
108 | - default: abort(); | ||
109 | - } | ||
110 | - neon_store_reg(rd, pass * 2 + 1, tmp); | ||
111 | - if (size == 2) { | ||
112 | - neon_store_reg(rd, pass * 2, tmp2); | ||
113 | - } else { | ||
114 | - switch (size) { | ||
115 | - case 0: tcg_gen_bswap32_i32(tmp2, tmp2); break; | ||
116 | - case 1: gen_swap_half(tmp2); break; | ||
117 | - default: abort(); | ||
118 | - } | ||
119 | - neon_store_reg(rd, pass * 2, tmp2); | ||
120 | - } | ||
121 | - } | ||
122 | - break; | ||
123 | + /* handled by decodetree */ | ||
124 | + return 1; | ||
125 | case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U: | ||
126 | case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: | ||
127 | for (pass = 0; pass < q + 1; pass++) { | ||
128 | -- | ||
129 | 2.20.1 | ||
130 | |||
131 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the pairwise ops VPADDL and VPADAL in the 2-reg-misc grouping | ||
2 | to decodetree. | ||
3 | 1 | ||
4 | At this point we can get rid of the weird CPU_V001 #define that was | ||
5 | used to avoid having to explicitly list all the arguments being | ||
6 | passed to some TCG gen/helper functions. | ||
7 | |||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20200616170844.13318-3-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/arm/neon-dp.decode | 6 ++ | ||
13 | target/arm/translate-neon.inc.c | 149 ++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate.c | 35 +------- | ||
15 | 3 files changed, 157 insertions(+), 33 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/neon-dp.decode | ||
20 | +++ b/target/arm/neon-dp.decode | ||
21 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
22 | &2misc vm=%vm_dp vd=%vd_dp | ||
23 | |||
24 | VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc | ||
25 | + | ||
26 | + VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc | ||
27 | + VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc | ||
28 | + | ||
29 | + VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc | ||
30 | + VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc | ||
31 | ] | ||
32 | |||
33 | # Subgroup for size != 0b11 | ||
34 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/translate-neon.inc.c | ||
37 | +++ b/target/arm/translate-neon.inc.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | ||
39 | } | ||
40 | return true; | ||
41 | } | ||
42 | + | ||
43 | +static bool do_2misc_pairwise(DisasContext *s, arg_2misc *a, | ||
44 | + NeonGenWidenFn *widenfn, | ||
45 | + NeonGenTwo64OpFn *opfn, | ||
46 | + NeonGenTwo64OpFn *accfn) | ||
47 | +{ | ||
48 | + /* | ||
49 | + * Pairwise long operations: widen both halves of the pair, | ||
50 | + * combine the pairs with the opfn, and then possibly accumulate | ||
51 | + * into the destination with the accfn. | ||
52 | + */ | ||
53 | + int pass; | ||
54 | + | ||
55 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
56 | + return false; | ||
57 | + } | ||
58 | + | ||
59 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
60 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
61 | + ((a->vd | a->vm) & 0x10)) { | ||
62 | + return false; | ||
63 | + } | ||
64 | + | ||
65 | + if ((a->vd | a->vm) & a->q) { | ||
66 | + return false; | ||
67 | + } | ||
68 | + | ||
69 | + if (!widenfn) { | ||
70 | + return false; | ||
71 | + } | ||
72 | + | ||
73 | + if (!vfp_access_check(s)) { | ||
74 | + return true; | ||
75 | + } | ||
76 | + | ||
77 | + for (pass = 0; pass < a->q + 1; pass++) { | ||
78 | + TCGv_i32 tmp; | ||
79 | + TCGv_i64 rm0_64, rm1_64, rd_64; | ||
80 | + | ||
81 | + rm0_64 = tcg_temp_new_i64(); | ||
82 | + rm1_64 = tcg_temp_new_i64(); | ||
83 | + rd_64 = tcg_temp_new_i64(); | ||
84 | + tmp = neon_load_reg(a->vm, pass * 2); | ||
85 | + widenfn(rm0_64, tmp); | ||
86 | + tcg_temp_free_i32(tmp); | ||
87 | + tmp = neon_load_reg(a->vm, pass * 2 + 1); | ||
88 | + widenfn(rm1_64, tmp); | ||
89 | + tcg_temp_free_i32(tmp); | ||
90 | + opfn(rd_64, rm0_64, rm1_64); | ||
91 | + tcg_temp_free_i64(rm0_64); | ||
92 | + tcg_temp_free_i64(rm1_64); | ||
93 | + | ||
94 | + if (accfn) { | ||
95 | + TCGv_i64 tmp64 = tcg_temp_new_i64(); | ||
96 | + neon_load_reg64(tmp64, a->vd + pass); | ||
97 | + accfn(rd_64, tmp64, rd_64); | ||
98 | + tcg_temp_free_i64(tmp64); | ||
99 | + } | ||
100 | + neon_store_reg64(rd_64, a->vd + pass); | ||
101 | + tcg_temp_free_i64(rd_64); | ||
102 | + } | ||
103 | + return true; | ||
104 | +} | ||
105 | + | ||
106 | +static bool trans_VPADDL_S(DisasContext *s, arg_2misc *a) | ||
107 | +{ | ||
108 | + static NeonGenWidenFn * const widenfn[] = { | ||
109 | + gen_helper_neon_widen_s8, | ||
110 | + gen_helper_neon_widen_s16, | ||
111 | + tcg_gen_ext_i32_i64, | ||
112 | + NULL, | ||
113 | + }; | ||
114 | + static NeonGenTwo64OpFn * const opfn[] = { | ||
115 | + gen_helper_neon_paddl_u16, | ||
116 | + gen_helper_neon_paddl_u32, | ||
117 | + tcg_gen_add_i64, | ||
118 | + NULL, | ||
119 | + }; | ||
120 | + | ||
121 | + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL); | ||
122 | +} | ||
123 | + | ||
124 | +static bool trans_VPADDL_U(DisasContext *s, arg_2misc *a) | ||
125 | +{ | ||
126 | + static NeonGenWidenFn * const widenfn[] = { | ||
127 | + gen_helper_neon_widen_u8, | ||
128 | + gen_helper_neon_widen_u16, | ||
129 | + tcg_gen_extu_i32_i64, | ||
130 | + NULL, | ||
131 | + }; | ||
132 | + static NeonGenTwo64OpFn * const opfn[] = { | ||
133 | + gen_helper_neon_paddl_u16, | ||
134 | + gen_helper_neon_paddl_u32, | ||
135 | + tcg_gen_add_i64, | ||
136 | + NULL, | ||
137 | + }; | ||
138 | + | ||
139 | + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], NULL); | ||
140 | +} | ||
141 | + | ||
142 | +static bool trans_VPADAL_S(DisasContext *s, arg_2misc *a) | ||
143 | +{ | ||
144 | + static NeonGenWidenFn * const widenfn[] = { | ||
145 | + gen_helper_neon_widen_s8, | ||
146 | + gen_helper_neon_widen_s16, | ||
147 | + tcg_gen_ext_i32_i64, | ||
148 | + NULL, | ||
149 | + }; | ||
150 | + static NeonGenTwo64OpFn * const opfn[] = { | ||
151 | + gen_helper_neon_paddl_u16, | ||
152 | + gen_helper_neon_paddl_u32, | ||
153 | + tcg_gen_add_i64, | ||
154 | + NULL, | ||
155 | + }; | ||
156 | + static NeonGenTwo64OpFn * const accfn[] = { | ||
157 | + gen_helper_neon_addl_u16, | ||
158 | + gen_helper_neon_addl_u32, | ||
159 | + tcg_gen_add_i64, | ||
160 | + NULL, | ||
161 | + }; | ||
162 | + | ||
163 | + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], | ||
164 | + accfn[a->size]); | ||
165 | +} | ||
166 | + | ||
167 | +static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a) | ||
168 | +{ | ||
169 | + static NeonGenWidenFn * const widenfn[] = { | ||
170 | + gen_helper_neon_widen_u8, | ||
171 | + gen_helper_neon_widen_u16, | ||
172 | + tcg_gen_extu_i32_i64, | ||
173 | + NULL, | ||
174 | + }; | ||
175 | + static NeonGenTwo64OpFn * const opfn[] = { | ||
176 | + gen_helper_neon_paddl_u16, | ||
177 | + gen_helper_neon_paddl_u32, | ||
178 | + tcg_gen_add_i64, | ||
179 | + NULL, | ||
180 | + }; | ||
181 | + static NeonGenTwo64OpFn * const accfn[] = { | ||
182 | + gen_helper_neon_addl_u16, | ||
183 | + gen_helper_neon_addl_u32, | ||
184 | + tcg_gen_add_i64, | ||
185 | + NULL, | ||
186 | + }; | ||
187 | + | ||
188 | + return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], | ||
189 | + accfn[a->size]); | ||
190 | +} | ||
191 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
192 | index XXXXXXX..XXXXXXX 100644 | ||
193 | --- a/target/arm/translate.c | ||
194 | +++ b/target/arm/translate.c | ||
195 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc) | ||
196 | gen_rfe(s, pc, load_cpu_field(spsr)); | ||
197 | } | ||
198 | |||
199 | -#define CPU_V001 cpu_V0, cpu_V0, cpu_V1 | ||
200 | - | ||
201 | static int gen_neon_unzip(int rd, int rm, int size, int q) | ||
202 | { | ||
203 | TCGv_ptr pd, pm; | ||
204 | @@ -XXX,XX +XXX,XX @@ static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u) | ||
205 | tcg_temp_free_i32(src); | ||
206 | } | ||
207 | |||
208 | -static inline void gen_neon_addl(int size) | ||
209 | -{ | ||
210 | - switch (size) { | ||
211 | - case 0: gen_helper_neon_addl_u16(CPU_V001); break; | ||
212 | - case 1: gen_helper_neon_addl_u32(CPU_V001); break; | ||
213 | - case 2: tcg_gen_add_i64(CPU_V001); break; | ||
214 | - default: abort(); | ||
215 | - } | ||
216 | -} | ||
217 | - | ||
218 | static void gen_neon_narrow_op(int op, int u, int size, | ||
219 | TCGv_i32 dest, TCGv_i64 src) | ||
220 | { | ||
221 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
222 | } | ||
223 | switch (op) { | ||
224 | case NEON_2RM_VREV64: | ||
225 | - /* handled by decodetree */ | ||
226 | - return 1; | ||
227 | case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U: | ||
228 | case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: | ||
229 | - for (pass = 0; pass < q + 1; pass++) { | ||
230 | - tmp = neon_load_reg(rm, pass * 2); | ||
231 | - gen_neon_widen(cpu_V0, tmp, size, op & 1); | ||
232 | - tmp = neon_load_reg(rm, pass * 2 + 1); | ||
233 | - gen_neon_widen(cpu_V1, tmp, size, op & 1); | ||
234 | - switch (size) { | ||
235 | - case 0: gen_helper_neon_paddl_u16(CPU_V001); break; | ||
236 | - case 1: gen_helper_neon_paddl_u32(CPU_V001); break; | ||
237 | - case 2: tcg_gen_add_i64(CPU_V001); break; | ||
238 | - default: abort(); | ||
239 | - } | ||
240 | - if (op >= NEON_2RM_VPADAL) { | ||
241 | - /* Accumulate. */ | ||
242 | - neon_load_reg64(cpu_V1, rd + pass); | ||
243 | - gen_neon_addl(size); | ||
244 | - } | ||
245 | - neon_store_reg64(cpu_V0, rd + pass); | ||
246 | - } | ||
247 | - break; | ||
248 | + /* handled by decodetree */ | ||
249 | + return 1; | ||
250 | case NEON_2RM_VTRN: | ||
251 | if (size == 2) { | ||
252 | int n; | ||
253 | -- | ||
254 | 2.20.1 | ||
255 | |||
256 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the Neon VZIP and VUZP insns in the 2-reg-misc group to | ||
2 | decodetree. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20200616170844.13318-4-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/neon-dp.decode | 3 ++ | ||
9 | target/arm/translate-neon.inc.c | 74 ++++++++++++++++++++++++++ | ||
10 | target/arm/translate.c | 92 +-------------------------------- | ||
11 | 3 files changed, 79 insertions(+), 90 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/neon-dp.decode | ||
16 | +++ b/target/arm/neon-dp.decode | ||
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
18 | |||
19 | VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc | ||
20 | VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc | ||
21 | + | ||
22 | + VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc | ||
23 | + VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc | ||
24 | ] | ||
25 | |||
26 | # Subgroup for size != 0b11 | ||
27 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/translate-neon.inc.c | ||
30 | +++ b/target/arm/translate-neon.inc.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static bool trans_VPADAL_U(DisasContext *s, arg_2misc *a) | ||
32 | return do_2misc_pairwise(s, a, widenfn[a->size], opfn[a->size], | ||
33 | accfn[a->size]); | ||
34 | } | ||
35 | + | ||
36 | +typedef void ZipFn(TCGv_ptr, TCGv_ptr); | ||
37 | + | ||
38 | +static bool do_zip_uzp(DisasContext *s, arg_2misc *a, | ||
39 | + ZipFn *fn) | ||
40 | +{ | ||
41 | + TCGv_ptr pd, pm; | ||
42 | + | ||
43 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
44 | + return false; | ||
45 | + } | ||
46 | + | ||
47 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
48 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
49 | + ((a->vd | a->vm) & 0x10)) { | ||
50 | + return false; | ||
51 | + } | ||
52 | + | ||
53 | + if ((a->vd | a->vm) & a->q) { | ||
54 | + return false; | ||
55 | + } | ||
56 | + | ||
57 | + if (!fn) { | ||
58 | + /* Bad size or size/q combination */ | ||
59 | + return false; | ||
60 | + } | ||
61 | + | ||
62 | + if (!vfp_access_check(s)) { | ||
63 | + return true; | ||
64 | + } | ||
65 | + | ||
66 | + pd = vfp_reg_ptr(true, a->vd); | ||
67 | + pm = vfp_reg_ptr(true, a->vm); | ||
68 | + fn(pd, pm); | ||
69 | + tcg_temp_free_ptr(pd); | ||
70 | + tcg_temp_free_ptr(pm); | ||
71 | + return true; | ||
72 | +} | ||
73 | + | ||
74 | +static bool trans_VUZP(DisasContext *s, arg_2misc *a) | ||
75 | +{ | ||
76 | + static ZipFn * const fn[2][4] = { | ||
77 | + { | ||
78 | + gen_helper_neon_unzip8, | ||
79 | + gen_helper_neon_unzip16, | ||
80 | + NULL, | ||
81 | + NULL, | ||
82 | + }, { | ||
83 | + gen_helper_neon_qunzip8, | ||
84 | + gen_helper_neon_qunzip16, | ||
85 | + gen_helper_neon_qunzip32, | ||
86 | + NULL, | ||
87 | + } | ||
88 | + }; | ||
89 | + return do_zip_uzp(s, a, fn[a->q][a->size]); | ||
90 | +} | ||
91 | + | ||
92 | +static bool trans_VZIP(DisasContext *s, arg_2misc *a) | ||
93 | +{ | ||
94 | + static ZipFn * const fn[2][4] = { | ||
95 | + { | ||
96 | + gen_helper_neon_zip8, | ||
97 | + gen_helper_neon_zip16, | ||
98 | + NULL, | ||
99 | + NULL, | ||
100 | + }, { | ||
101 | + gen_helper_neon_qzip8, | ||
102 | + gen_helper_neon_qzip16, | ||
103 | + gen_helper_neon_qzip32, | ||
104 | + NULL, | ||
105 | + } | ||
106 | + }; | ||
107 | + return do_zip_uzp(s, a, fn[a->q][a->size]); | ||
108 | +} | ||
109 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
110 | index XXXXXXX..XXXXXXX 100644 | ||
111 | --- a/target/arm/translate.c | ||
112 | +++ b/target/arm/translate.c | ||
113 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc) | ||
114 | gen_rfe(s, pc, load_cpu_field(spsr)); | ||
115 | } | ||
116 | |||
117 | -static int gen_neon_unzip(int rd, int rm, int size, int q) | ||
118 | -{ | ||
119 | - TCGv_ptr pd, pm; | ||
120 | - | ||
121 | - if (!q && size == 2) { | ||
122 | - return 1; | ||
123 | - } | ||
124 | - pd = vfp_reg_ptr(true, rd); | ||
125 | - pm = vfp_reg_ptr(true, rm); | ||
126 | - if (q) { | ||
127 | - switch (size) { | ||
128 | - case 0: | ||
129 | - gen_helper_neon_qunzip8(pd, pm); | ||
130 | - break; | ||
131 | - case 1: | ||
132 | - gen_helper_neon_qunzip16(pd, pm); | ||
133 | - break; | ||
134 | - case 2: | ||
135 | - gen_helper_neon_qunzip32(pd, pm); | ||
136 | - break; | ||
137 | - default: | ||
138 | - abort(); | ||
139 | - } | ||
140 | - } else { | ||
141 | - switch (size) { | ||
142 | - case 0: | ||
143 | - gen_helper_neon_unzip8(pd, pm); | ||
144 | - break; | ||
145 | - case 1: | ||
146 | - gen_helper_neon_unzip16(pd, pm); | ||
147 | - break; | ||
148 | - default: | ||
149 | - abort(); | ||
150 | - } | ||
151 | - } | ||
152 | - tcg_temp_free_ptr(pd); | ||
153 | - tcg_temp_free_ptr(pm); | ||
154 | - return 0; | ||
155 | -} | ||
156 | - | ||
157 | -static int gen_neon_zip(int rd, int rm, int size, int q) | ||
158 | -{ | ||
159 | - TCGv_ptr pd, pm; | ||
160 | - | ||
161 | - if (!q && size == 2) { | ||
162 | - return 1; | ||
163 | - } | ||
164 | - pd = vfp_reg_ptr(true, rd); | ||
165 | - pm = vfp_reg_ptr(true, rm); | ||
166 | - if (q) { | ||
167 | - switch (size) { | ||
168 | - case 0: | ||
169 | - gen_helper_neon_qzip8(pd, pm); | ||
170 | - break; | ||
171 | - case 1: | ||
172 | - gen_helper_neon_qzip16(pd, pm); | ||
173 | - break; | ||
174 | - case 2: | ||
175 | - gen_helper_neon_qzip32(pd, pm); | ||
176 | - break; | ||
177 | - default: | ||
178 | - abort(); | ||
179 | - } | ||
180 | - } else { | ||
181 | - switch (size) { | ||
182 | - case 0: | ||
183 | - gen_helper_neon_zip8(pd, pm); | ||
184 | - break; | ||
185 | - case 1: | ||
186 | - gen_helper_neon_zip16(pd, pm); | ||
187 | - break; | ||
188 | - default: | ||
189 | - abort(); | ||
190 | - } | ||
191 | - } | ||
192 | - tcg_temp_free_ptr(pd); | ||
193 | - tcg_temp_free_ptr(pm); | ||
194 | - return 0; | ||
195 | -} | ||
196 | - | ||
197 | static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) | ||
198 | { | ||
199 | TCGv_i32 rd, tmp; | ||
200 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
201 | case NEON_2RM_VREV64: | ||
202 | case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U: | ||
203 | case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: | ||
204 | + case NEON_2RM_VUZP: | ||
205 | + case NEON_2RM_VZIP: | ||
206 | /* handled by decodetree */ | ||
207 | return 1; | ||
208 | case NEON_2RM_VTRN: | ||
209 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
210 | goto elementwise; | ||
211 | } | ||
212 | break; | ||
213 | - case NEON_2RM_VUZP: | ||
214 | - if (gen_neon_unzip(rd, rm, size, q)) { | ||
215 | - return 1; | ||
216 | - } | ||
217 | - break; | ||
218 | - case NEON_2RM_VZIP: | ||
219 | - if (gen_neon_zip(rd, rm, size, q)) { | ||
220 | - return 1; | ||
221 | - } | ||
222 | - break; | ||
223 | case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: | ||
224 | /* also VQMOVUN; op field and mnemonics don't line up */ | ||
225 | if (rm & 1) { | ||
226 | -- | ||
227 | 2.20.1 | ||
228 | |||
229 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the Neon narrowing moves VMQNV, VQMOVN, VQMOVUN in the 2-reg-misc | ||
2 | group to decodetree. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20200616170844.13318-5-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/neon-dp.decode | 9 ++++ | ||
9 | target/arm/translate-neon.inc.c | 59 ++++++++++++++++++++++++ | ||
10 | target/arm/translate.c | 81 +-------------------------------- | ||
11 | 3 files changed, 70 insertions(+), 79 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/neon-dp.decode | ||
16 | +++ b/target/arm/neon-dp.decode | ||
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
18 | |||
19 | @2misc .... ... .. . .. size:2 .. .... . .... q:1 . . .... \ | ||
20 | &2misc vm=%vm_dp vd=%vd_dp | ||
21 | + @2misc_q0 .... ... .. . .. size:2 .. .... . .... . . . .... \ | ||
22 | + &2misc vm=%vm_dp vd=%vd_dp q=0 | ||
23 | |||
24 | VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc | ||
25 | |||
26 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
27 | |||
28 | VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc | ||
29 | VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc | ||
30 | + | ||
31 | + VMOVN 1111 001 11 . 11 .. 10 .... 0 0100 0 . 0 .... @2misc_q0 | ||
32 | + # VQMOVUN: unsigned result (source is always signed) | ||
33 | + VQMOVUN 1111 001 11 . 11 .. 10 .... 0 0100 1 . 0 .... @2misc_q0 | ||
34 | + # VQMOVN: signed result, source may be signed (_S) or unsigned (_U) | ||
35 | + VQMOVN_S 1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0 | ||
36 | + VQMOVN_U 1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0 | ||
37 | ] | ||
38 | |||
39 | # Subgroup for size != 0b11 | ||
40 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/translate-neon.inc.c | ||
43 | +++ b/target/arm/translate-neon.inc.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static bool trans_VZIP(DisasContext *s, arg_2misc *a) | ||
45 | }; | ||
46 | return do_zip_uzp(s, a, fn[a->q][a->size]); | ||
47 | } | ||
48 | + | ||
49 | +static bool do_vmovn(DisasContext *s, arg_2misc *a, | ||
50 | + NeonGenNarrowEnvFn *narrowfn) | ||
51 | +{ | ||
52 | + TCGv_i64 rm; | ||
53 | + TCGv_i32 rd0, rd1; | ||
54 | + | ||
55 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
56 | + return false; | ||
57 | + } | ||
58 | + | ||
59 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
60 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
61 | + ((a->vd | a->vm) & 0x10)) { | ||
62 | + return false; | ||
63 | + } | ||
64 | + | ||
65 | + if (a->vm & 1) { | ||
66 | + return false; | ||
67 | + } | ||
68 | + | ||
69 | + if (!narrowfn) { | ||
70 | + return false; | ||
71 | + } | ||
72 | + | ||
73 | + if (!vfp_access_check(s)) { | ||
74 | + return true; | ||
75 | + } | ||
76 | + | ||
77 | + rm = tcg_temp_new_i64(); | ||
78 | + rd0 = tcg_temp_new_i32(); | ||
79 | + rd1 = tcg_temp_new_i32(); | ||
80 | + | ||
81 | + neon_load_reg64(rm, a->vm); | ||
82 | + narrowfn(rd0, cpu_env, rm); | ||
83 | + neon_load_reg64(rm, a->vm + 1); | ||
84 | + narrowfn(rd1, cpu_env, rm); | ||
85 | + neon_store_reg(a->vd, 0, rd0); | ||
86 | + neon_store_reg(a->vd, 1, rd1); | ||
87 | + tcg_temp_free_i64(rm); | ||
88 | + return true; | ||
89 | +} | ||
90 | + | ||
91 | +#define DO_VMOVN(INSN, FUNC) \ | ||
92 | + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ | ||
93 | + { \ | ||
94 | + static NeonGenNarrowEnvFn * const narrowfn[] = { \ | ||
95 | + FUNC##8, \ | ||
96 | + FUNC##16, \ | ||
97 | + FUNC##32, \ | ||
98 | + NULL, \ | ||
99 | + }; \ | ||
100 | + return do_vmovn(s, a, narrowfn[a->size]); \ | ||
101 | + } | ||
102 | + | ||
103 | +DO_VMOVN(VMOVN, gen_neon_narrow_u) | ||
104 | +DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat) | ||
105 | +DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s) | ||
106 | +DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u) | ||
107 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
108 | index XXXXXXX..XXXXXXX 100644 | ||
109 | --- a/target/arm/translate.c | ||
110 | +++ b/target/arm/translate.c | ||
111 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) | ||
112 | tcg_temp_free_i32(rd); | ||
113 | } | ||
114 | |||
115 | -static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src) | ||
116 | -{ | ||
117 | - switch (size) { | ||
118 | - case 0: gen_helper_neon_narrow_u8(dest, src); break; | ||
119 | - case 1: gen_helper_neon_narrow_u16(dest, src); break; | ||
120 | - case 2: tcg_gen_extrl_i64_i32(dest, src); break; | ||
121 | - default: abort(); | ||
122 | - } | ||
123 | -} | ||
124 | - | ||
125 | -static inline void gen_neon_narrow_sats(int size, TCGv_i32 dest, TCGv_i64 src) | ||
126 | -{ | ||
127 | - switch (size) { | ||
128 | - case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break; | ||
129 | - case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break; | ||
130 | - case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break; | ||
131 | - default: abort(); | ||
132 | - } | ||
133 | -} | ||
134 | - | ||
135 | -static inline void gen_neon_narrow_satu(int size, TCGv_i32 dest, TCGv_i64 src) | ||
136 | -{ | ||
137 | - switch (size) { | ||
138 | - case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break; | ||
139 | - case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break; | ||
140 | - case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break; | ||
141 | - default: abort(); | ||
142 | - } | ||
143 | -} | ||
144 | - | ||
145 | -static inline void gen_neon_unarrow_sats(int size, TCGv_i32 dest, TCGv_i64 src) | ||
146 | -{ | ||
147 | - switch (size) { | ||
148 | - case 0: gen_helper_neon_unarrow_sat8(dest, cpu_env, src); break; | ||
149 | - case 1: gen_helper_neon_unarrow_sat16(dest, cpu_env, src); break; | ||
150 | - case 2: gen_helper_neon_unarrow_sat32(dest, cpu_env, src); break; | ||
151 | - default: abort(); | ||
152 | - } | ||
153 | -} | ||
154 | - | ||
155 | static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u) | ||
156 | { | ||
157 | if (u) { | ||
158 | @@ -XXX,XX +XXX,XX @@ static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u) | ||
159 | tcg_temp_free_i32(src); | ||
160 | } | ||
161 | |||
162 | -static void gen_neon_narrow_op(int op, int u, int size, | ||
163 | - TCGv_i32 dest, TCGv_i64 src) | ||
164 | -{ | ||
165 | - if (op) { | ||
166 | - if (u) { | ||
167 | - gen_neon_unarrow_sats(size, dest, src); | ||
168 | - } else { | ||
169 | - gen_neon_narrow(size, dest, src); | ||
170 | - } | ||
171 | - } else { | ||
172 | - if (u) { | ||
173 | - gen_neon_narrow_satu(size, dest, src); | ||
174 | - } else { | ||
175 | - gen_neon_narrow_sats(size, dest, src); | ||
176 | - } | ||
177 | - } | ||
178 | -} | ||
179 | - | ||
180 | /* Symbolic constants for op fields for Neon 2-register miscellaneous. | ||
181 | * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B | ||
182 | * table A7-13. | ||
183 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
184 | !arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
185 | return 1; | ||
186 | } | ||
187 | - if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) && | ||
188 | - q && ((rm | rd) & 1)) { | ||
189 | + if (q && ((rm | rd) & 1)) { | ||
190 | return 1; | ||
191 | } | ||
192 | switch (op) { | ||
193 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
194 | case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: | ||
195 | case NEON_2RM_VUZP: | ||
196 | case NEON_2RM_VZIP: | ||
197 | + case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: | ||
198 | /* handled by decodetree */ | ||
199 | return 1; | ||
200 | case NEON_2RM_VTRN: | ||
201 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
202 | goto elementwise; | ||
203 | } | ||
204 | break; | ||
205 | - case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: | ||
206 | - /* also VQMOVUN; op field and mnemonics don't line up */ | ||
207 | - if (rm & 1) { | ||
208 | - return 1; | ||
209 | - } | ||
210 | - tmp2 = NULL; | ||
211 | - for (pass = 0; pass < 2; pass++) { | ||
212 | - neon_load_reg64(cpu_V0, rm + pass); | ||
213 | - tmp = tcg_temp_new_i32(); | ||
214 | - gen_neon_narrow_op(op == NEON_2RM_VMOVN, q, size, | ||
215 | - tmp, cpu_V0); | ||
216 | - if (pass == 0) { | ||
217 | - tmp2 = tmp; | ||
218 | - } else { | ||
219 | - neon_store_reg(rd, 0, tmp2); | ||
220 | - neon_store_reg(rd, 1, tmp); | ||
221 | - } | ||
222 | - } | ||
223 | - break; | ||
224 | case NEON_2RM_VSHLL: | ||
225 | if (q || (rd & 1)) { | ||
226 | return 1; | ||
227 | -- | ||
228 | 2.20.1 | ||
229 | |||
230 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the VSHLL insn in the 2-reg-misc Neon group to decodetree. | ||
2 | 1 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20200616170844.13318-6-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/arm/neon-dp.decode | 2 ++ | ||
8 | target/arm/translate-neon.inc.c | 52 +++++++++++++++++++++++++++++++++ | ||
9 | target/arm/translate.c | 35 +--------------------- | ||
10 | 3 files changed, 55 insertions(+), 34 deletions(-) | ||
11 | |||
12 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
13 | index XXXXXXX..XXXXXXX 100644 | ||
14 | --- a/target/arm/neon-dp.decode | ||
15 | +++ b/target/arm/neon-dp.decode | ||
16 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
17 | # VQMOVN: signed result, source may be signed (_S) or unsigned (_U) | ||
18 | VQMOVN_S 1111 001 11 . 11 .. 10 .... 0 0101 0 . 0 .... @2misc_q0 | ||
19 | VQMOVN_U 1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0 | ||
20 | + | ||
21 | + VSHLL 1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0 | ||
22 | ] | ||
23 | |||
24 | # Subgroup for size != 0b11 | ||
25 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/target/arm/translate-neon.inc.c | ||
28 | +++ b/target/arm/translate-neon.inc.c | ||
29 | @@ -XXX,XX +XXX,XX @@ DO_VMOVN(VMOVN, gen_neon_narrow_u) | ||
30 | DO_VMOVN(VQMOVUN, gen_helper_neon_unarrow_sat) | ||
31 | DO_VMOVN(VQMOVN_S, gen_helper_neon_narrow_sat_s) | ||
32 | DO_VMOVN(VQMOVN_U, gen_helper_neon_narrow_sat_u) | ||
33 | + | ||
34 | +static bool trans_VSHLL(DisasContext *s, arg_2misc *a) | ||
35 | +{ | ||
36 | + TCGv_i32 rm0, rm1; | ||
37 | + TCGv_i64 rd; | ||
38 | + static NeonGenWidenFn * const widenfns[] = { | ||
39 | + gen_helper_neon_widen_u8, | ||
40 | + gen_helper_neon_widen_u16, | ||
41 | + tcg_gen_extu_i32_i64, | ||
42 | + NULL, | ||
43 | + }; | ||
44 | + NeonGenWidenFn *widenfn = widenfns[a->size]; | ||
45 | + | ||
46 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
47 | + return false; | ||
48 | + } | ||
49 | + | ||
50 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
51 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
52 | + ((a->vd | a->vm) & 0x10)) { | ||
53 | + return false; | ||
54 | + } | ||
55 | + | ||
56 | + if (a->vd & 1) { | ||
57 | + return false; | ||
58 | + } | ||
59 | + | ||
60 | + if (!widenfn) { | ||
61 | + return false; | ||
62 | + } | ||
63 | + | ||
64 | + if (!vfp_access_check(s)) { | ||
65 | + return true; | ||
66 | + } | ||
67 | + | ||
68 | + rd = tcg_temp_new_i64(); | ||
69 | + | ||
70 | + rm0 = neon_load_reg(a->vm, 0); | ||
71 | + rm1 = neon_load_reg(a->vm, 1); | ||
72 | + | ||
73 | + widenfn(rd, rm0); | ||
74 | + tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
75 | + neon_store_reg64(rd, a->vd); | ||
76 | + widenfn(rd, rm1); | ||
77 | + tcg_gen_shli_i64(rd, rd, 8 << a->size); | ||
78 | + neon_store_reg64(rd, a->vd + 1); | ||
79 | + | ||
80 | + tcg_temp_free_i64(rd); | ||
81 | + tcg_temp_free_i32(rm0); | ||
82 | + tcg_temp_free_i32(rm1); | ||
83 | + return true; | ||
84 | +} | ||
85 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
86 | index XXXXXXX..XXXXXXX 100644 | ||
87 | --- a/target/arm/translate.c | ||
88 | +++ b/target/arm/translate.c | ||
89 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) | ||
90 | tcg_temp_free_i32(rd); | ||
91 | } | ||
92 | |||
93 | -static inline void gen_neon_widen(TCGv_i64 dest, TCGv_i32 src, int size, int u) | ||
94 | -{ | ||
95 | - if (u) { | ||
96 | - switch (size) { | ||
97 | - case 0: gen_helper_neon_widen_u8(dest, src); break; | ||
98 | - case 1: gen_helper_neon_widen_u16(dest, src); break; | ||
99 | - case 2: tcg_gen_extu_i32_i64(dest, src); break; | ||
100 | - default: abort(); | ||
101 | - } | ||
102 | - } else { | ||
103 | - switch (size) { | ||
104 | - case 0: gen_helper_neon_widen_s8(dest, src); break; | ||
105 | - case 1: gen_helper_neon_widen_s16(dest, src); break; | ||
106 | - case 2: tcg_gen_ext_i32_i64(dest, src); break; | ||
107 | - default: abort(); | ||
108 | - } | ||
109 | - } | ||
110 | - tcg_temp_free_i32(src); | ||
111 | -} | ||
112 | - | ||
113 | /* Symbolic constants for op fields for Neon 2-register miscellaneous. | ||
114 | * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B | ||
115 | * table A7-13. | ||
116 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
117 | case NEON_2RM_VUZP: | ||
118 | case NEON_2RM_VZIP: | ||
119 | case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: | ||
120 | + case NEON_2RM_VSHLL: | ||
121 | /* handled by decodetree */ | ||
122 | return 1; | ||
123 | case NEON_2RM_VTRN: | ||
124 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
125 | goto elementwise; | ||
126 | } | ||
127 | break; | ||
128 | - case NEON_2RM_VSHLL: | ||
129 | - if (q || (rd & 1)) { | ||
130 | - return 1; | ||
131 | - } | ||
132 | - tmp = neon_load_reg(rm, 0); | ||
133 | - tmp2 = neon_load_reg(rm, 1); | ||
134 | - for (pass = 0; pass < 2; pass++) { | ||
135 | - if (pass == 1) | ||
136 | - tmp = tmp2; | ||
137 | - gen_neon_widen(cpu_V0, tmp, size, 1); | ||
138 | - tcg_gen_shli_i64(cpu_V0, cpu_V0, 8 << size); | ||
139 | - neon_store_reg64(cpu_V0, rd + pass); | ||
140 | - } | ||
141 | - break; | ||
142 | case NEON_2RM_VCVT_F16_F32: | ||
143 | { | ||
144 | TCGv_ptr fpst; | ||
145 | -- | ||
146 | 2.20.1 | ||
147 | |||
148 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the Neon insns in the 2-reg-misc group which are | ||
2 | VCVT between f32 and f16 to decodetree. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20200616170844.13318-7-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/neon-dp.decode | 3 ++ | ||
9 | target/arm/translate-neon.inc.c | 96 +++++++++++++++++++++++++++++++++ | ||
10 | target/arm/translate.c | 65 ++-------------------- | ||
11 | 3 files changed, 102 insertions(+), 62 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/neon-dp.decode | ||
16 | +++ b/target/arm/neon-dp.decode | ||
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
18 | VQMOVN_U 1111 001 11 . 11 .. 10 .... 0 0101 1 . 0 .... @2misc_q0 | ||
19 | |||
20 | VSHLL 1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0 | ||
21 | + | ||
22 | + VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 | ||
23 | + VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 | ||
24 | ] | ||
25 | |||
26 | # Subgroup for size != 0b11 | ||
27 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/translate-neon.inc.c | ||
30 | +++ b/target/arm/translate-neon.inc.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *a) | ||
32 | tcg_temp_free_i32(rm1); | ||
33 | return true; | ||
34 | } | ||
35 | + | ||
36 | +static bool trans_VCVT_F16_F32(DisasContext *s, arg_2misc *a) | ||
37 | +{ | ||
38 | + TCGv_ptr fpst; | ||
39 | + TCGv_i32 ahp, tmp, tmp2, tmp3; | ||
40 | + | ||
41 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || | ||
42 | + !dc_isar_feature(aa32_fp16_spconv, s)) { | ||
43 | + return false; | ||
44 | + } | ||
45 | + | ||
46 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
47 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
48 | + ((a->vd | a->vm) & 0x10)) { | ||
49 | + return false; | ||
50 | + } | ||
51 | + | ||
52 | + if ((a->vm & 1) || (a->size != 1)) { | ||
53 | + return false; | ||
54 | + } | ||
55 | + | ||
56 | + if (!vfp_access_check(s)) { | ||
57 | + return true; | ||
58 | + } | ||
59 | + | ||
60 | + fpst = get_fpstatus_ptr(true); | ||
61 | + ahp = get_ahp_flag(); | ||
62 | + tmp = neon_load_reg(a->vm, 0); | ||
63 | + gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
64 | + tmp2 = neon_load_reg(a->vm, 1); | ||
65 | + gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); | ||
66 | + tcg_gen_shli_i32(tmp2, tmp2, 16); | ||
67 | + tcg_gen_or_i32(tmp2, tmp2, tmp); | ||
68 | + tcg_temp_free_i32(tmp); | ||
69 | + tmp = neon_load_reg(a->vm, 2); | ||
70 | + gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
71 | + tmp3 = neon_load_reg(a->vm, 3); | ||
72 | + neon_store_reg(a->vd, 0, tmp2); | ||
73 | + gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); | ||
74 | + tcg_gen_shli_i32(tmp3, tmp3, 16); | ||
75 | + tcg_gen_or_i32(tmp3, tmp3, tmp); | ||
76 | + neon_store_reg(a->vd, 1, tmp3); | ||
77 | + tcg_temp_free_i32(tmp); | ||
78 | + tcg_temp_free_i32(ahp); | ||
79 | + tcg_temp_free_ptr(fpst); | ||
80 | + | ||
81 | + return true; | ||
82 | +} | ||
83 | + | ||
84 | +static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) | ||
85 | +{ | ||
86 | + TCGv_ptr fpst; | ||
87 | + TCGv_i32 ahp, tmp, tmp2, tmp3; | ||
88 | + | ||
89 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || | ||
90 | + !dc_isar_feature(aa32_fp16_spconv, s)) { | ||
91 | + return false; | ||
92 | + } | ||
93 | + | ||
94 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
95 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
96 | + ((a->vd | a->vm) & 0x10)) { | ||
97 | + return false; | ||
98 | + } | ||
99 | + | ||
100 | + if ((a->vd & 1) || (a->size != 1)) { | ||
101 | + return false; | ||
102 | + } | ||
103 | + | ||
104 | + if (!vfp_access_check(s)) { | ||
105 | + return true; | ||
106 | + } | ||
107 | + | ||
108 | + fpst = get_fpstatus_ptr(true); | ||
109 | + ahp = get_ahp_flag(); | ||
110 | + tmp3 = tcg_temp_new_i32(); | ||
111 | + tmp = neon_load_reg(a->vm, 0); | ||
112 | + tmp2 = neon_load_reg(a->vm, 1); | ||
113 | + tcg_gen_ext16u_i32(tmp3, tmp); | ||
114 | + gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
115 | + neon_store_reg(a->vd, 0, tmp3); | ||
116 | + tcg_gen_shri_i32(tmp, tmp, 16); | ||
117 | + gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); | ||
118 | + neon_store_reg(a->vd, 1, tmp); | ||
119 | + tmp3 = tcg_temp_new_i32(); | ||
120 | + tcg_gen_ext16u_i32(tmp3, tmp2); | ||
121 | + gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
122 | + neon_store_reg(a->vd, 2, tmp3); | ||
123 | + tcg_gen_shri_i32(tmp2, tmp2, 16); | ||
124 | + gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); | ||
125 | + neon_store_reg(a->vd, 3, tmp2); | ||
126 | + tcg_temp_free_i32(ahp); | ||
127 | + tcg_temp_free_ptr(fpst); | ||
128 | + | ||
129 | + return true; | ||
130 | +} | ||
131 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
132 | index XXXXXXX..XXXXXXX 100644 | ||
133 | --- a/target/arm/translate.c | ||
134 | +++ b/target/arm/translate.c | ||
135 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
136 | int pass; | ||
137 | int u; | ||
138 | int vec_size; | ||
139 | - TCGv_i32 tmp, tmp2, tmp3; | ||
140 | + TCGv_i32 tmp, tmp2; | ||
141 | |||
142 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
143 | return 1; | ||
144 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
145 | case NEON_2RM_VZIP: | ||
146 | case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: | ||
147 | case NEON_2RM_VSHLL: | ||
148 | + case NEON_2RM_VCVT_F16_F32: | ||
149 | + case NEON_2RM_VCVT_F32_F16: | ||
150 | /* handled by decodetree */ | ||
151 | return 1; | ||
152 | case NEON_2RM_VTRN: | ||
153 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
154 | goto elementwise; | ||
155 | } | ||
156 | break; | ||
157 | - case NEON_2RM_VCVT_F16_F32: | ||
158 | - { | ||
159 | - TCGv_ptr fpst; | ||
160 | - TCGv_i32 ahp; | ||
161 | - | ||
162 | - if (!dc_isar_feature(aa32_fp16_spconv, s) || | ||
163 | - q || (rm & 1)) { | ||
164 | - return 1; | ||
165 | - } | ||
166 | - fpst = get_fpstatus_ptr(true); | ||
167 | - ahp = get_ahp_flag(); | ||
168 | - tmp = neon_load_reg(rm, 0); | ||
169 | - gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
170 | - tmp2 = neon_load_reg(rm, 1); | ||
171 | - gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); | ||
172 | - tcg_gen_shli_i32(tmp2, tmp2, 16); | ||
173 | - tcg_gen_or_i32(tmp2, tmp2, tmp); | ||
174 | - tcg_temp_free_i32(tmp); | ||
175 | - tmp = neon_load_reg(rm, 2); | ||
176 | - gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); | ||
177 | - tmp3 = neon_load_reg(rm, 3); | ||
178 | - neon_store_reg(rd, 0, tmp2); | ||
179 | - gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); | ||
180 | - tcg_gen_shli_i32(tmp3, tmp3, 16); | ||
181 | - tcg_gen_or_i32(tmp3, tmp3, tmp); | ||
182 | - neon_store_reg(rd, 1, tmp3); | ||
183 | - tcg_temp_free_i32(tmp); | ||
184 | - tcg_temp_free_i32(ahp); | ||
185 | - tcg_temp_free_ptr(fpst); | ||
186 | - break; | ||
187 | - } | ||
188 | - case NEON_2RM_VCVT_F32_F16: | ||
189 | - { | ||
190 | - TCGv_ptr fpst; | ||
191 | - TCGv_i32 ahp; | ||
192 | - if (!dc_isar_feature(aa32_fp16_spconv, s) || | ||
193 | - q || (rd & 1)) { | ||
194 | - return 1; | ||
195 | - } | ||
196 | - fpst = get_fpstatus_ptr(true); | ||
197 | - ahp = get_ahp_flag(); | ||
198 | - tmp3 = tcg_temp_new_i32(); | ||
199 | - tmp = neon_load_reg(rm, 0); | ||
200 | - tmp2 = neon_load_reg(rm, 1); | ||
201 | - tcg_gen_ext16u_i32(tmp3, tmp); | ||
202 | - gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
203 | - neon_store_reg(rd, 0, tmp3); | ||
204 | - tcg_gen_shri_i32(tmp, tmp, 16); | ||
205 | - gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); | ||
206 | - neon_store_reg(rd, 1, tmp); | ||
207 | - tmp3 = tcg_temp_new_i32(); | ||
208 | - tcg_gen_ext16u_i32(tmp3, tmp2); | ||
209 | - gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); | ||
210 | - neon_store_reg(rd, 2, tmp3); | ||
211 | - tcg_gen_shri_i32(tmp2, tmp2, 16); | ||
212 | - gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); | ||
213 | - neon_store_reg(rd, 3, tmp2); | ||
214 | - tcg_temp_free_i32(ahp); | ||
215 | - tcg_temp_free_ptr(fpst); | ||
216 | - break; | ||
217 | - } | ||
218 | case NEON_2RM_AESE: case NEON_2RM_AESMC: | ||
219 | if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) { | ||
220 | return 1; | ||
221 | -- | ||
222 | 2.20.1 | ||
223 | |||
224 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert to decodetree the insns in the Neon 2-reg-misc grouping which | ||
2 | we implement using gvec. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20200616170844.13318-8-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/neon-dp.decode | 11 +++++++ | ||
9 | target/arm/translate-neon.inc.c | 55 +++++++++++++++++++++++++++++++++ | ||
10 | target/arm/translate.c | 35 +++++---------------- | ||
11 | 3 files changed, 74 insertions(+), 27 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/neon-dp.decode | ||
16 | +++ b/target/arm/neon-dp.decode | ||
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
18 | VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc | ||
19 | VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc | ||
20 | |||
21 | + VMVN 1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc | ||
22 | + | ||
23 | VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc | ||
24 | VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc | ||
25 | |||
26 | + VCGT0 1111 001 11 . 11 .. 01 .... 0 0000 . . 0 .... @2misc | ||
27 | + VCGE0 1111 001 11 . 11 .. 01 .... 0 0001 . . 0 .... @2misc | ||
28 | + VCEQ0 1111 001 11 . 11 .. 01 .... 0 0010 . . 0 .... @2misc | ||
29 | + VCLE0 1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc | ||
30 | + VCLT0 1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc | ||
31 | + | ||
32 | + VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc | ||
33 | + VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc | ||
34 | + | ||
35 | VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc | ||
36 | VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc | ||
37 | |||
38 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/translate-neon.inc.c | ||
41 | +++ b/target/arm/translate-neon.inc.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2misc *a) | ||
43 | |||
44 | return true; | ||
45 | } | ||
46 | + | ||
47 | +static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) | ||
48 | +{ | ||
49 | + int vec_size = a->q ? 16 : 8; | ||
50 | + int rd_ofs = neon_reg_offset(a->vd, 0); | ||
51 | + int rm_ofs = neon_reg_offset(a->vm, 0); | ||
52 | + | ||
53 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
54 | + return false; | ||
55 | + } | ||
56 | + | ||
57 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
58 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
59 | + ((a->vd | a->vm) & 0x10)) { | ||
60 | + return false; | ||
61 | + } | ||
62 | + | ||
63 | + if (a->size == 3) { | ||
64 | + return false; | ||
65 | + } | ||
66 | + | ||
67 | + if ((a->vd | a->vm) & a->q) { | ||
68 | + return false; | ||
69 | + } | ||
70 | + | ||
71 | + if (!vfp_access_check(s)) { | ||
72 | + return true; | ||
73 | + } | ||
74 | + | ||
75 | + fn(a->size, rd_ofs, rm_ofs, vec_size, vec_size); | ||
76 | + | ||
77 | + return true; | ||
78 | +} | ||
79 | + | ||
80 | +#define DO_2MISC_VEC(INSN, FN) \ | ||
81 | + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ | ||
82 | + { \ | ||
83 | + return do_2misc_vec(s, a, FN); \ | ||
84 | + } | ||
85 | + | ||
86 | +DO_2MISC_VEC(VNEG, tcg_gen_gvec_neg) | ||
87 | +DO_2MISC_VEC(VABS, tcg_gen_gvec_abs) | ||
88 | +DO_2MISC_VEC(VCEQ0, gen_gvec_ceq0) | ||
89 | +DO_2MISC_VEC(VCGT0, gen_gvec_cgt0) | ||
90 | +DO_2MISC_VEC(VCLE0, gen_gvec_cle0) | ||
91 | +DO_2MISC_VEC(VCGE0, gen_gvec_cge0) | ||
92 | +DO_2MISC_VEC(VCLT0, gen_gvec_clt0) | ||
93 | + | ||
94 | +static bool trans_VMVN(DisasContext *s, arg_2misc *a) | ||
95 | +{ | ||
96 | + if (a->size != 0) { | ||
97 | + return false; | ||
98 | + } | ||
99 | + return do_2misc_vec(s, a, tcg_gen_gvec_not); | ||
100 | +} | ||
101 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
102 | index XXXXXXX..XXXXXXX 100644 | ||
103 | --- a/target/arm/translate.c | ||
104 | +++ b/target/arm/translate.c | ||
105 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
106 | int size; | ||
107 | int pass; | ||
108 | int u; | ||
109 | - int vec_size; | ||
110 | TCGv_i32 tmp, tmp2; | ||
111 | |||
112 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
113 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
114 | VFP_DREG_D(rd, insn); | ||
115 | VFP_DREG_M(rm, insn); | ||
116 | size = (insn >> 20) & 3; | ||
117 | - vec_size = q ? 16 : 8; | ||
118 | rd_ofs = neon_reg_offset(rd, 0); | ||
119 | rm_ofs = neon_reg_offset(rm, 0); | ||
120 | |||
121 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
122 | case NEON_2RM_VSHLL: | ||
123 | case NEON_2RM_VCVT_F16_F32: | ||
124 | case NEON_2RM_VCVT_F32_F16: | ||
125 | + case NEON_2RM_VMVN: | ||
126 | + case NEON_2RM_VNEG: | ||
127 | + case NEON_2RM_VABS: | ||
128 | + case NEON_2RM_VCEQ0: | ||
129 | + case NEON_2RM_VCGT0: | ||
130 | + case NEON_2RM_VCLE0: | ||
131 | + case NEON_2RM_VCGE0: | ||
132 | + case NEON_2RM_VCLT0: | ||
133 | /* handled by decodetree */ | ||
134 | return 1; | ||
135 | case NEON_2RM_VTRN: | ||
136 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
137 | q ? gen_helper_crypto_sha256su0 | ||
138 | : gen_helper_crypto_sha1su1); | ||
139 | break; | ||
140 | - case NEON_2RM_VMVN: | ||
141 | - tcg_gen_gvec_not(0, rd_ofs, rm_ofs, vec_size, vec_size); | ||
142 | - break; | ||
143 | - case NEON_2RM_VNEG: | ||
144 | - tcg_gen_gvec_neg(size, rd_ofs, rm_ofs, vec_size, vec_size); | ||
145 | - break; | ||
146 | - case NEON_2RM_VABS: | ||
147 | - tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_size); | ||
148 | - break; | ||
149 | - | ||
150 | - case NEON_2RM_VCEQ0: | ||
151 | - gen_gvec_ceq0(size, rd_ofs, rm_ofs, vec_size, vec_size); | ||
152 | - break; | ||
153 | - case NEON_2RM_VCGT0: | ||
154 | - gen_gvec_cgt0(size, rd_ofs, rm_ofs, vec_size, vec_size); | ||
155 | - break; | ||
156 | - case NEON_2RM_VCLE0: | ||
157 | - gen_gvec_cle0(size, rd_ofs, rm_ofs, vec_size, vec_size); | ||
158 | - break; | ||
159 | - case NEON_2RM_VCGE0: | ||
160 | - gen_gvec_cge0(size, rd_ofs, rm_ofs, vec_size, vec_size); | ||
161 | - break; | ||
162 | - case NEON_2RM_VCLT0: | ||
163 | - gen_gvec_clt0(size, rd_ofs, rm_ofs, vec_size, vec_size); | ||
164 | - break; | ||
165 | |||
166 | default: | ||
167 | elementwise: | ||
168 | -- | ||
169 | 2.20.1 | ||
170 | |||
171 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the Neon-2-reg misc crypto ops (AESE, AESMC, SHA1H, SHA1SU1) | ||
2 | to decodetree. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20200616170844.13318-9-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/neon-dp.decode | 12 ++++++++ | ||
9 | target/arm/translate-neon.inc.c | 42 ++++++++++++++++++++++++++ | ||
10 | target/arm/translate.c | 52 +++------------------------------ | ||
11 | 3 files changed, 58 insertions(+), 48 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/neon-dp.decode | ||
16 | +++ b/target/arm/neon-dp.decode | ||
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
18 | &2misc vm=%vm_dp vd=%vd_dp | ||
19 | @2misc_q0 .... ... .. . .. size:2 .. .... . .... . . . .... \ | ||
20 | &2misc vm=%vm_dp vd=%vd_dp q=0 | ||
21 | + @2misc_q1 .... ... .. . .. size:2 .. .... . .... . . . .... \ | ||
22 | + &2misc vm=%vm_dp vd=%vd_dp q=1 | ||
23 | |||
24 | VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc | ||
25 | |||
26 | VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc | ||
27 | VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc | ||
28 | |||
29 | + AESE 1111 001 11 . 11 .. 00 .... 0 0110 0 . 0 .... @2misc_q1 | ||
30 | + AESD 1111 001 11 . 11 .. 00 .... 0 0110 1 . 0 .... @2misc_q1 | ||
31 | + AESMC 1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1 | ||
32 | + AESIMC 1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1 | ||
33 | + | ||
34 | VMVN 1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc | ||
35 | |||
36 | VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc | ||
37 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
38 | VCLE0 1111 001 11 . 11 .. 01 .... 0 0011 . . 0 .... @2misc | ||
39 | VCLT0 1111 001 11 . 11 .. 01 .... 0 0100 . . 0 .... @2misc | ||
40 | |||
41 | + SHA1H 1111 001 11 . 11 .. 01 .... 0 0101 1 . 0 .... @2misc_q1 | ||
42 | + | ||
43 | VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc | ||
44 | VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc | ||
45 | |||
46 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
47 | |||
48 | VSHLL 1111 001 11 . 11 .. 10 .... 0 0110 0 . 0 .... @2misc_q0 | ||
49 | |||
50 | + SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1 | ||
51 | + SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1 | ||
52 | + | ||
53 | VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 | ||
54 | VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 | ||
55 | ] | ||
56 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/target/arm/translate-neon.inc.c | ||
59 | +++ b/target/arm/translate-neon.inc.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMVN(DisasContext *s, arg_2misc *a) | ||
61 | } | ||
62 | return do_2misc_vec(s, a, tcg_gen_gvec_not); | ||
63 | } | ||
64 | + | ||
65 | +#define WRAP_2M_3_OOL_FN(WRAPNAME, FUNC, DATA) \ | ||
66 | + static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ | ||
67 | + uint32_t rm_ofs, uint32_t oprsz, \ | ||
68 | + uint32_t maxsz) \ | ||
69 | + { \ | ||
70 | + tcg_gen_gvec_3_ool(rd_ofs, rd_ofs, rm_ofs, oprsz, maxsz, \ | ||
71 | + DATA, FUNC); \ | ||
72 | + } | ||
73 | + | ||
74 | +#define WRAP_2M_2_OOL_FN(WRAPNAME, FUNC, DATA) \ | ||
75 | + static void WRAPNAME(unsigned vece, uint32_t rd_ofs, \ | ||
76 | + uint32_t rm_ofs, uint32_t oprsz, \ | ||
77 | + uint32_t maxsz) \ | ||
78 | + { \ | ||
79 | + tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, oprsz, maxsz, DATA, FUNC); \ | ||
80 | + } | ||
81 | + | ||
82 | +WRAP_2M_3_OOL_FN(gen_AESE, gen_helper_crypto_aese, 0) | ||
83 | +WRAP_2M_3_OOL_FN(gen_AESD, gen_helper_crypto_aese, 1) | ||
84 | +WRAP_2M_2_OOL_FN(gen_AESMC, gen_helper_crypto_aesmc, 0) | ||
85 | +WRAP_2M_2_OOL_FN(gen_AESIMC, gen_helper_crypto_aesmc, 1) | ||
86 | +WRAP_2M_2_OOL_FN(gen_SHA1H, gen_helper_crypto_sha1h, 0) | ||
87 | +WRAP_2M_2_OOL_FN(gen_SHA1SU1, gen_helper_crypto_sha1su1, 0) | ||
88 | +WRAP_2M_2_OOL_FN(gen_SHA256SU0, gen_helper_crypto_sha256su0, 0) | ||
89 | + | ||
90 | +#define DO_2M_CRYPTO(INSN, FEATURE, SIZE) \ | ||
91 | + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ | ||
92 | + { \ | ||
93 | + if (!dc_isar_feature(FEATURE, s) || a->size != SIZE) { \ | ||
94 | + return false; \ | ||
95 | + } \ | ||
96 | + return do_2misc_vec(s, a, gen_##INSN); \ | ||
97 | + } | ||
98 | + | ||
99 | +DO_2M_CRYPTO(AESE, aa32_aes, 0) | ||
100 | +DO_2M_CRYPTO(AESD, aa32_aes, 0) | ||
101 | +DO_2M_CRYPTO(AESMC, aa32_aes, 0) | ||
102 | +DO_2M_CRYPTO(AESIMC, aa32_aes, 0) | ||
103 | +DO_2M_CRYPTO(SHA1H, aa32_sha1, 2) | ||
104 | +DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2) | ||
105 | +DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) | ||
106 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/target/arm/translate.c | ||
109 | +++ b/target/arm/translate.c | ||
110 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
111 | { | ||
112 | int op; | ||
113 | int q; | ||
114 | - int rd, rm, rd_ofs, rm_ofs; | ||
115 | + int rd, rm; | ||
116 | int size; | ||
117 | int pass; | ||
118 | int u; | ||
119 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
120 | VFP_DREG_D(rd, insn); | ||
121 | VFP_DREG_M(rm, insn); | ||
122 | size = (insn >> 20) & 3; | ||
123 | - rd_ofs = neon_reg_offset(rd, 0); | ||
124 | - rm_ofs = neon_reg_offset(rm, 0); | ||
125 | |||
126 | if ((insn & (1 << 23)) == 0) { | ||
127 | /* Three register same length: handled by decodetree */ | ||
128 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
129 | case NEON_2RM_VCLE0: | ||
130 | case NEON_2RM_VCGE0: | ||
131 | case NEON_2RM_VCLT0: | ||
132 | + case NEON_2RM_AESE: case NEON_2RM_AESMC: | ||
133 | + case NEON_2RM_SHA1H: | ||
134 | + case NEON_2RM_SHA1SU1: | ||
135 | /* handled by decodetree */ | ||
136 | return 1; | ||
137 | case NEON_2RM_VTRN: | ||
138 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
139 | goto elementwise; | ||
140 | } | ||
141 | break; | ||
142 | - case NEON_2RM_AESE: case NEON_2RM_AESMC: | ||
143 | - if (!dc_isar_feature(aa32_aes, s) || ((rm | rd) & 1)) { | ||
144 | - return 1; | ||
145 | - } | ||
146 | - /* | ||
147 | - * Bit 6 is the lowest opcode bit; it distinguishes | ||
148 | - * between encryption (AESE/AESMC) and decryption | ||
149 | - * (AESD/AESIMC). | ||
150 | - */ | ||
151 | - if (op == NEON_2RM_AESE) { | ||
152 | - tcg_gen_gvec_3_ool(vfp_reg_offset(true, rd), | ||
153 | - vfp_reg_offset(true, rd), | ||
154 | - vfp_reg_offset(true, rm), | ||
155 | - 16, 16, extract32(insn, 6, 1), | ||
156 | - gen_helper_crypto_aese); | ||
157 | - } else { | ||
158 | - tcg_gen_gvec_2_ool(vfp_reg_offset(true, rd), | ||
159 | - vfp_reg_offset(true, rm), | ||
160 | - 16, 16, extract32(insn, 6, 1), | ||
161 | - gen_helper_crypto_aesmc); | ||
162 | - } | ||
163 | - break; | ||
164 | - case NEON_2RM_SHA1H: | ||
165 | - if (!dc_isar_feature(aa32_sha1, s) || ((rm | rd) & 1)) { | ||
166 | - return 1; | ||
167 | - } | ||
168 | - tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0, | ||
169 | - gen_helper_crypto_sha1h); | ||
170 | - break; | ||
171 | - case NEON_2RM_SHA1SU1: | ||
172 | - if ((rm | rd) & 1) { | ||
173 | - return 1; | ||
174 | - } | ||
175 | - /* bit 6 (q): set -> SHA256SU0, cleared -> SHA1SU1 */ | ||
176 | - if (q) { | ||
177 | - if (!dc_isar_feature(aa32_sha2, s)) { | ||
178 | - return 1; | ||
179 | - } | ||
180 | - } else if (!dc_isar_feature(aa32_sha1, s)) { | ||
181 | - return 1; | ||
182 | - } | ||
183 | - tcg_gen_gvec_2_ool(rd_ofs, rm_ofs, 16, 16, 0, | ||
184 | - q ? gen_helper_crypto_sha256su0 | ||
185 | - : gen_helper_crypto_sha1su1); | ||
186 | - break; | ||
187 | |||
188 | default: | ||
189 | elementwise: | ||
190 | -- | ||
191 | 2.20.1 | ||
192 | |||
193 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The NeonGenOneOpFn typedef breaks with the pattern of the other | ||
2 | NeonGen*Fn typedefs, because it is a TCGv_i64 -> TCGv_i64 operation | ||
3 | but it does not have '64' in its name. Rename it to NeonGenOne64OpFn, | ||
4 | so that the old name is available for a TCGv_i32 -> TCGv_i32 operation | ||
5 | (which we will need in a subsequent commit). | ||
6 | 1 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20200616170844.13318-10-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/translate.h | 2 +- | ||
12 | target/arm/translate-a64.c | 4 ++-- | ||
13 | 2 files changed, 3 insertions(+), 3 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate.h | ||
18 | +++ b/target/arm/translate.h | ||
19 | @@ -XXX,XX +XXX,XX @@ typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); | ||
20 | typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); | ||
21 | typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); | ||
22 | typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | ||
23 | -typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); | ||
24 | +typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); | ||
25 | typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); | ||
26 | typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
27 | typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
28 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/translate-a64.c | ||
31 | +++ b/target/arm/translate-a64.c | ||
32 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, | ||
33 | } else { | ||
34 | for (pass = 0; pass < maxpass; pass++) { | ||
35 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | ||
36 | - NeonGenOneOpFn *genfn; | ||
37 | - static NeonGenOneOpFn * const fns[2][2] = { | ||
38 | + NeonGenOne64OpFn *genfn; | ||
39 | + static NeonGenOne64OpFn * const fns[2][2] = { | ||
40 | { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 }, | ||
41 | { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 }, | ||
42 | }; | ||
43 | -- | ||
44 | 2.20.1 | ||
45 | |||
46 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | All the other typedefs like these spell "Op" with a lowercase 'p'; | ||
2 | remane the NeonGenTwoSingleOPFn and NeonGenTwoDoubleOPFn typedefs to | ||
3 | match. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200616170844.13318-11-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate.h | 4 ++-- | ||
10 | target/arm/translate-a64.c | 4 ++-- | ||
11 | target/arm/translate-neon.inc.c | 2 +- | ||
12 | 3 files changed, 5 insertions(+), 5 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate.h | ||
17 | +++ b/target/arm/translate.h | ||
18 | @@ -XXX,XX +XXX,XX @@ typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); | ||
19 | typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); | ||
20 | typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); | ||
21 | typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); | ||
22 | -typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); | ||
23 | -typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | ||
24 | +typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); | ||
25 | +typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | ||
26 | typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); | ||
27 | typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); | ||
28 | typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
29 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/translate-a64.c | ||
32 | +++ b/target/arm/translate-a64.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, | ||
34 | TCGv_i64 tcg_op = tcg_temp_new_i64(); | ||
35 | TCGv_i64 tcg_zero = tcg_const_i64(0); | ||
36 | TCGv_i64 tcg_res = tcg_temp_new_i64(); | ||
37 | - NeonGenTwoDoubleOPFn *genfn; | ||
38 | + NeonGenTwoDoubleOpFn *genfn; | ||
39 | bool swap = false; | ||
40 | int pass; | ||
41 | |||
42 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, | ||
43 | TCGv_i32 tcg_op = tcg_temp_new_i32(); | ||
44 | TCGv_i32 tcg_zero = tcg_const_i32(0); | ||
45 | TCGv_i32 tcg_res = tcg_temp_new_i32(); | ||
46 | - NeonGenTwoSingleOPFn *genfn; | ||
47 | + NeonGenTwoSingleOpFn *genfn; | ||
48 | bool swap = false; | ||
49 | int pass, maxpasses; | ||
50 | |||
51 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/target/arm/translate-neon.inc.c | ||
54 | +++ b/target/arm/translate-neon.inc.c | ||
55 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSHLL_U_2sh(DisasContext *s, arg_2reg_shift *a) | ||
56 | } | ||
57 | |||
58 | static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a, | ||
59 | - NeonGenTwoSingleOPFn *fn) | ||
60 | + NeonGenTwoSingleOpFn *fn) | ||
61 | { | ||
62 | /* FP operations in 2-reg-and-shift group */ | ||
63 | TCGv_i32 tmp, shiftv; | ||
64 | -- | ||
65 | 2.20.1 | ||
66 | |||
67 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | To differenciate with the CMSDK APB peripheral region, | 3 | There is only one additional EL1 register modeled, which |
4 | rename this region 'CMSDK AHB peripheral region'. | 4 | also needs to use access_actlr_w. |
5 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | Message-id: 20230811214031.171020-8-richard.henderson@linaro.org |
8 | Message-id: 20200617072539.32686-8-f4bug@amsat.org | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 10 | --- |
11 | hw/arm/mps2.c | 3 ++- | 11 | target/arm/tcg/cpu64.c | 3 ++- |
12 | 1 file changed, 2 insertions(+), 1 deletion(-) | 12 | 1 file changed, 2 insertions(+), 1 deletion(-) |
13 | 13 | ||
14 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | 14 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/mps2.c | 16 | --- a/target/arm/tcg/cpu64.c |
17 | +++ b/hw/arm/mps2.c | 17 | +++ b/target/arm/tcg/cpu64.c |
18 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 18 | @@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) |
19 | */ | 19 | static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { |
20 | create_unimplemented_device("CMSDK APB peripheral region @0x40000000", | 20 | { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, |
21 | 0x40000000, 0x00010000); | 21 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, |
22 | - create_unimplemented_device("CMSDK peripheral region @0x40010000", | 22 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
23 | + create_unimplemented_device("CMSDK AHB peripheral region @0x40010000", | 23 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
24 | 0x40010000, 0x00010000); | 24 | + .accessfn = access_actlr_w }, |
25 | create_unimplemented_device("Extra peripheral region @0x40020000", | 25 | { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, |
26 | 0x40020000, 0x00010000); | 26 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, |
27 | + | 27 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
28 | create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000); | ||
29 | create_unimplemented_device("VGA", 0x41000000, 0x0200000); | ||
30 | |||
31 | -- | 28 | -- |
32 | 2.20.1 | 29 | 2.34.1 |
33 | |||
34 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing |
4 | Message-id: 20200617072539.32686-11-f4bug@amsat.org | 4 | external to the cpu, which is out of scope for QEMU. |
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20230811214031.171020-10-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 10 | --- |
8 | hw/arm/mps2.c | 9 +++++++++ | 11 | target/arm/cpu.c | 3 +++ |
9 | 1 file changed, 9 insertions(+) | 12 | 1 file changed, 3 insertions(+) |
10 | 13 | ||
11 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | 14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
12 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/mps2.c | 16 | --- a/target/arm/cpu.c |
14 | +++ b/hw/arm/mps2.c | 17 | +++ b/target/arm/cpu.c |
15 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
16 | #include "hw/timer/cmsdk-apb-timer.h" | 19 | /* FEAT_SPE (Statistical Profiling Extension) */ |
17 | #include "hw/timer/cmsdk-apb-dualtimer.h" | 20 | cpu->isar.id_aa64dfr0 = |
18 | #include "hw/misc/mps2-scc.h" | 21 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); |
19 | +#include "hw/misc/mps2-fpgaio.h" | 22 | + /* FEAT_TRBE (Trace Buffer Extension) */ |
20 | #include "hw/net/lan9118.h" | 23 | + cpu->isar.id_aa64dfr0 = |
21 | #include "net/net.h" | 24 | + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); |
22 | +#include "hw/watchdog/cmsdk-apb-watchdog.h" | 25 | /* FEAT_TRF (Self-hosted Trace Extension) */ |
23 | 26 | cpu->isar.id_aa64dfr0 = | |
24 | typedef enum MPS2FPGAType { | 27 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); |
25 | FPGA_AN385, | ||
26 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
27 | MemoryRegion sram; | ||
28 | /* FPGA APB subsystem */ | ||
29 | MPS2SCC scc; | ||
30 | + MPS2FPGAIO fpgaio; | ||
31 | /* CMSDK APB subsystem */ | ||
32 | CMSDKAPBDualTimer dualtimer; | ||
33 | + CMSDKAPBWatchdog watchdog; | ||
34 | } MPS2MachineState; | ||
35 | |||
36 | #define TYPE_MPS2_MACHINE "mps2" | ||
37 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | ||
38 | qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); | ||
39 | sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); | ||
40 | sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); | ||
41 | + object_initialize_child(OBJECT(mms), "fpgaio", | ||
42 | + &mms->fpgaio, TYPE_MPS2_FPGAIO); | ||
43 | + qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000); | ||
44 | + sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal); | ||
45 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000); | ||
46 | |||
47 | /* In hardware this is a LAN9220; the LAN9118 is software compatible | ||
48 | * except that it doesn't support the checksum-offload feature. | ||
49 | -- | 28 | -- |
50 | 2.20.1 | 29 | 2.34.1 |
51 | |||
52 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Register the GPIO peripherals as unimplemented to better | 3 | This feature allows the operating system to set TCR_ELx.HWU* |
4 | follow their accesses, for example booting Zephyr: | 4 | to allow the implementation to use the PBHA bits from the |
5 | block and page descriptors for for IMPLEMENTATION DEFINED | ||
6 | purposes. Since QEMU has no need to use these bits, we may | ||
7 | simply ignore them. | ||
5 | 8 | ||
6 | ---------------- | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | IN: arm_mps2_pinmux_init | ||
8 | 0x00001160: f64f 0231 movw r2, #0xf831 | ||
9 | 0x00001164: 4b06 ldr r3, [pc, #0x18] | ||
10 | 0x00001166: 2000 movs r0, #0 | ||
11 | 0x00001168: 619a str r2, [r3, #0x18] | ||
12 | 0x0000116a: f24c 426f movw r2, #0xc46f | ||
13 | 0x0000116e: f503 5380 add.w r3, r3, #0x1000 | ||
14 | 0x00001172: 619a str r2, [r3, #0x18] | ||
15 | 0x00001174: f44f 529e mov.w r2, #0x13c0 | ||
16 | 0x00001178: f503 5380 add.w r3, r3, #0x1000 | ||
17 | 0x0000117c: 619a str r2, [r3, #0x18] | ||
18 | 0x0000117e: 4770 bx lr | ||
19 | cmsdk-ahb-gpio: unimplemented device write (size 4, value 0xf831, offset 0x18) | ||
20 | cmsdk-ahb-gpio: unimplemented device write (size 4, value 0xc46f, offset 0x18) | ||
21 | cmsdk-ahb-gpio: unimplemented device write (size 4, value 0x13c0, offset 0x18) | ||
22 | |||
23 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
24 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 11 | Message-id: 20230811214031.171020-11-richard.henderson@linaro.org |
25 | Message-id: 20200617072539.32686-10-f4bug@amsat.org | ||
26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
27 | --- | 13 | --- |
28 | hw/arm/mps2.c | 8 ++++++-- | 14 | docs/system/arm/emulation.rst | 1 + |
29 | 1 file changed, 6 insertions(+), 2 deletions(-) | 15 | target/arm/tcg/cpu32.c | 2 +- |
16 | target/arm/tcg/cpu64.c | 2 +- | ||
17 | 3 files changed, 3 insertions(+), 2 deletions(-) | ||
30 | 18 | ||
31 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
32 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/hw/arm/mps2.c | 21 | --- a/docs/system/arm/emulation.rst |
34 | +++ b/hw/arm/mps2.c | 22 | +++ b/docs/system/arm/emulation.rst |
35 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
36 | MemoryRegion *system_memory = get_system_memory(); | 24 | - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) |
37 | MachineClass *mc = MACHINE_GET_CLASS(machine); | 25 | - FEAT_HCX (Support for the HCRX_EL2 register) |
38 | DeviceState *armv7m, *sccdev; | 26 | - FEAT_HPDS (Hierarchical permission disables) |
39 | + int i; | 27 | +- FEAT_HPDS2 (Translation table page-based hardware attributes) |
40 | 28 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) | |
41 | if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { | 29 | - FEAT_IDST (ID space trap handling) |
42 | error_report("This board can only be used with CPU %s", | 30 | - FEAT_IESB (Implicit error synchronization event) |
43 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 31 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c |
44 | */ | 32 | index XXXXXXX..XXXXXXX 100644 |
45 | Object *orgate; | 33 | --- a/target/arm/tcg/cpu32.c |
46 | DeviceState *orgate_dev; | 34 | +++ b/target/arm/tcg/cpu32.c |
47 | - int i; | 35 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) |
48 | 36 | cpu->isar.id_mmfr3 = t; | |
49 | orgate = object_new(TYPE_OR_IRQ); | 37 | |
50 | object_property_set_int(orgate, 6, "num-lines", &error_fatal); | 38 | t = cpu->isar.id_mmfr4; |
51 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 39 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ |
52 | */ | 40 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ |
53 | Object *orgate; | 41 | t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ |
54 | DeviceState *orgate_dev; | 42 | t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ |
55 | - int i; | 43 | t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ |
56 | 44 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | |
57 | orgate = object_new(TYPE_OR_IRQ); | 45 | index XXXXXXX..XXXXXXX 100644 |
58 | object_property_set_int(orgate, 10, "num-lines", &error_fatal); | 46 | --- a/target/arm/tcg/cpu64.c |
59 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 47 | +++ b/target/arm/tcg/cpu64.c |
60 | default: | 48 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) |
61 | g_assert_not_reached(); | 49 | t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ |
62 | } | 50 | t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ |
63 | + for (i = 0; i < 4; i++) { | 51 | t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ |
64 | + static const hwaddr gpiobase[] = {0x40010000, 0x40011000, | 52 | - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ |
65 | + 0x40012000, 0x40013000}; | 53 | + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */ |
66 | + create_unimplemented_device("cmsdk-ahb-gpio", gpiobase[i], 0x1000); | 54 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ |
67 | + } | 55 | t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ |
68 | 56 | t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ | |
69 | /* CMSDK APB subsystem */ | ||
70 | cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); | ||
71 | -- | 57 | -- |
72 | 2.20.1 | 58 | 2.34.1 |
73 | |||
74 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We already model the CMSDK APB watchdog device, let's use it! | 3 | This is a mandatory feature for Armv8.1 architectures but we don't |
4 | state the feature clearly in our emulation list. Also include | ||
5 | FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping. | ||
4 | 6 | ||
5 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
6 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
7 | Message-id: 20200617072539.32686-9-f4bug@amsat.org | 9 | Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Cc: qemu-stable@nongnu.org |
11 | Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org> | ||
12 | [PMM: pluralize 'instructions' in docs] | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 14 | --- |
11 | hw/arm/mps2.c | 7 +++++++ | 15 | docs/system/arm/emulation.rst | 1 + |
12 | hw/arm/Kconfig | 1 + | 16 | target/arm/tcg/cpu64.c | 2 +- |
13 | 2 files changed, 8 insertions(+) | 17 | 2 files changed, 2 insertions(+), 1 deletion(-) |
14 | 18 | ||
15 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
16 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/mps2.c | 21 | --- a/docs/system/arm/emulation.rst |
18 | +++ b/hw/arm/mps2.c | 22 | +++ b/docs/system/arm/emulation.rst |
19 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
20 | sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, | 24 | - FEAT_BBM at level 2 (Translation table break-before-make levels) |
21 | qdev_get_gpio_in(armv7m, 10)); | 25 | - FEAT_BF16 (AArch64 BFloat16 instructions) |
22 | sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); | 26 | - FEAT_BTI (Branch Target Identification) |
23 | + object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, | 27 | +- FEAT_CRC32 (CRC32 instructions) |
24 | + TYPE_CMSDK_APB_WATCHDOG); | 28 | - FEAT_CSV2 (Cache speculation variant 2) |
25 | + qdev_prop_set_uint32(DEVICE(&mms->watchdog), "wdogclk-frq", SYSCLK_FRQ); | 29 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) |
26 | + sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); | 30 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) |
27 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, | 31 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
28 | + qdev_get_gpio_in_named(armv7m, "NMI", 0)); | ||
29 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0x40008000); | ||
30 | |||
31 | /* FPGA APB subsystem */ | ||
32 | object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); | ||
33 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
34 | index XXXXXXX..XXXXXXX 100644 | 32 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/hw/arm/Kconfig | 33 | --- a/target/arm/tcg/cpu64.c |
36 | +++ b/hw/arm/Kconfig | 34 | +++ b/target/arm/tcg/cpu64.c |
37 | @@ -XXX,XX +XXX,XX @@ config MPS2 | 35 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) |
38 | select PL080 # DMA controller | 36 | t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ |
39 | select SPLIT_IRQ | 37 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ |
40 | select UNIMP | 38 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ |
41 | + select CMSDK_APB_WATCHDOG | 39 | - t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); |
42 | 40 | + t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ | |
43 | config FSL_IMX7 | 41 | t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ |
44 | bool | 42 | t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ |
43 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ | ||
45 | -- | 44 | -- |
46 | 2.20.1 | 45 | 2.34.1 |
47 | 46 | ||
48 | 47 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 3 | i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device. |
4 | Message-id: 20200617072539.32686-7-f4bug@amsat.org | 4 | In particular, register 22 is not present on i.MX6UL and this is actualy |
5 | The only register that is really emulated in the i.MX7 IOMUX GPR device. | ||
6 | |||
7 | Note: The i.MX6UL code is actually also implementing the IOMUX GPR device | ||
8 | as an unimplemented device at the same bus adress and the 2 instantiations | ||
9 | were actualy colliding. So we go back to the unimplemented device for now. | ||
10 | |||
11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
12 | Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 15 | --- |
8 | hw/arm/mps2.c | 5 ++++- | 16 | include/hw/arm/fsl-imx6ul.h | 2 -- |
9 | 1 file changed, 4 insertions(+), 1 deletion(-) | 17 | hw/arm/fsl-imx6ul.c | 11 ----------- |
18 | 2 files changed, 13 deletions(-) | ||
10 | 19 | ||
11 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | 20 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h |
12 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/mps2.c | 22 | --- a/include/hw/arm/fsl-imx6ul.h |
14 | +++ b/hw/arm/mps2.c | 23 | +++ b/include/hw/arm/fsl-imx6ul.h |
15 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 24 | @@ -XXX,XX +XXX,XX @@ |
16 | MemoryRegion blockram_m2; | 25 | #include "hw/misc/imx6ul_ccm.h" |
17 | MemoryRegion blockram_m3; | 26 | #include "hw/misc/imx6_src.h" |
18 | MemoryRegion sram; | 27 | #include "hw/misc/imx7_snvs.h" |
19 | + /* FPGA APB subsystem */ | 28 | -#include "hw/misc/imx7_gpr.h" |
20 | MPS2SCC scc; | 29 | #include "hw/intc/imx_gpcv2.h" |
21 | + /* CMSDK APB subsystem */ | 30 | #include "hw/watchdog/wdt_imx2.h" |
22 | CMSDKAPBDualTimer dualtimer; | 31 | #include "hw/gpio/imx_gpio.h" |
23 | } MPS2MachineState; | 32 | @@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState { |
24 | 33 | IMX6SRCState src; | |
25 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 34 | IMX7SNVSState snvs; |
26 | g_assert_not_reached(); | 35 | IMXGPCv2State gpcv2; |
36 | - IMX7GPRState gpr; | ||
37 | IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS]; | ||
38 | IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS]; | ||
39 | IMXSerialState uart[FSL_IMX6UL_NUM_UARTS]; | ||
40 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/arm/fsl-imx6ul.c | ||
43 | +++ b/hw/arm/fsl-imx6ul.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
45 | */ | ||
46 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
47 | |||
48 | - /* | ||
49 | - * GPR | ||
50 | - */ | ||
51 | - object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); | ||
52 | - | ||
53 | /* | ||
54 | * GPIOs 1 to 5 | ||
55 | */ | ||
56 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
57 | FSL_IMX6UL_WDOGn_IRQ[i])); | ||
27 | } | 58 | } |
28 | 59 | ||
29 | + /* CMSDK APB subsystem */ | 60 | - /* |
30 | cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); | 61 | - * GPR |
31 | cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); | 62 | - */ |
63 | - sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); | ||
64 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR); | ||
32 | - | 65 | - |
33 | object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, | 66 | /* |
34 | TYPE_CMSDK_APB_DUALTIMER); | 67 | * SDMA |
35 | qdev_prop_set_uint32(DEVICE(&mms->dualtimer), "pclk-frq", SYSCLK_FRQ); | 68 | */ |
36 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | ||
37 | qdev_get_gpio_in(armv7m, 10)); | ||
38 | sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0x40002000); | ||
39 | |||
40 | + /* FPGA APB subsystem */ | ||
41 | object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); | ||
42 | sccdev = DEVICE(&mms->scc); | ||
43 | qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); | ||
44 | -- | 69 | -- |
45 | 2.20.1 | 70 | 2.34.1 |
46 | |||
47 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | From 'Application Note AN385', chapter 3.9, SPI: | 3 | * Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file. |
4 | * Use those newly defined named constants whenever possible. | ||
5 | * Standardize the way we init a familly of unimplemented devices | ||
6 | - SAI | ||
7 | - PWM | ||
8 | - CAN | ||
9 | * Add/rework few comments | ||
4 | 10 | ||
5 | The SMM implements five PL022 SPI modules. | 11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
6 | 12 | Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net | |
7 | Two pairs of modules share the same OR-gated IRQ. | ||
8 | |||
9 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Message-id: 20200617072539.32686-12-f4bug@amsat.org | ||
11 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 15 | --- |
14 | hw/arm/mps2.c | 24 ++++++++++++++++++++++++ | 16 | include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++----- |
15 | hw/arm/Kconfig | 6 +++--- | 17 | hw/arm/fsl-imx6ul.c | 147 ++++++++++++++++++++++----------- |
16 | 2 files changed, 27 insertions(+), 3 deletions(-) | 18 | 2 files changed, 232 insertions(+), 71 deletions(-) |
17 | 19 | ||
18 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | 20 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h |
19 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/arm/mps2.c | 22 | --- a/include/hw/arm/fsl-imx6ul.h |
21 | +++ b/hw/arm/mps2.c | 23 | +++ b/include/hw/arm/fsl-imx6ul.h |
22 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ |
23 | #include "hw/timer/cmsdk-apb-dualtimer.h" | 25 | #include "exec/memory.h" |
24 | #include "hw/misc/mps2-scc.h" | 26 | #include "cpu.h" |
25 | #include "hw/misc/mps2-fpgaio.h" | 27 | #include "qom/object.h" |
26 | +#include "hw/ssi/pl022.h" | 28 | +#include "qemu/units.h" |
27 | #include "hw/net/lan9118.h" | 29 | |
28 | #include "net/net.h" | 30 | #define TYPE_FSL_IMX6UL "fsl-imx6ul" |
29 | #include "hw/watchdog/cmsdk-apb-watchdog.h" | 31 | OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL) |
30 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | 32 | @@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration { |
31 | qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", 25000000); | 33 | FSL_IMX6UL_NUM_ADCS = 2, |
32 | sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal); | 34 | FSL_IMX6UL_NUM_USB_PHYS = 2, |
33 | sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0x40028000); | 35 | FSL_IMX6UL_NUM_USBS = 2, |
34 | + sysbus_create_simple(TYPE_PL022, 0x40025000, /* External ADC */ | 36 | + FSL_IMX6UL_NUM_SAIS = 3, |
35 | + qdev_get_gpio_in(armv7m, 22)); | 37 | + FSL_IMX6UL_NUM_CANS = 2, |
36 | + for (i = 0; i < 2; i++) { | 38 | + FSL_IMX6UL_NUM_PWMS = 4, |
37 | + static const int spi_irqno[] = {11, 24}; | 39 | }; |
38 | + static const hwaddr spibase[] = {0x40020000, /* APB */ | 40 | |
39 | + 0x40021000, /* LCD */ | 41 | struct FslIMX6ULState { |
40 | + 0x40026000, /* Shield0 */ | 42 | @@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState { |
41 | + 0x40027000}; /* Shield1 */ | 43 | |
42 | + DeviceState *orgate_dev; | 44 | enum FslIMX6ULMemoryMap { |
43 | + Object *orgate; | 45 | FSL_IMX6UL_MMDC_ADDR = 0x80000000, |
44 | + int j; | 46 | - FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, |
45 | + | 47 | + FSL_IMX6UL_MMDC_SIZE = (2 * GiB), |
46 | + orgate = object_new(TYPE_OR_IRQ); | 48 | |
47 | + object_property_set_int(orgate, 2, "num-lines", &error_fatal); | 49 | FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000, |
48 | + orgate_dev = DEVICE(orgate); | 50 | - FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, |
49 | + qdev_realize(orgate_dev, NULL, &error_fatal); | 51 | - FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, |
50 | + qdev_connect_gpio_out(orgate_dev, 0, | 52 | - FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, |
51 | + qdev_get_gpio_in(armv7m, spi_irqno[i])); | 53 | - FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, |
52 | + for (j = 0; j < 2; j++) { | 54 | + FSL_IMX6UL_QSPI1_MEM_SIZE = (256 * MiB), |
53 | + sysbus_create_simple(TYPE_PL022, spibase[2 * i + j], | 55 | |
54 | + qdev_get_gpio_in(orgate_dev, j)); | 56 | - /* AIPS-2 */ |
55 | + } | 57 | + FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, |
58 | + FSL_IMX6UL_EIM_ALIAS_SIZE = (128 * MiB), | ||
59 | + | ||
60 | + FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, | ||
61 | + FSL_IMX6UL_EIM_CS_SIZE = (128 * MiB), | ||
62 | + | ||
63 | + FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, | ||
64 | + FSL_IMX6UL_AES_ENCRYPT_SIZE = (1 * MiB), | ||
65 | + | ||
66 | + FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, | ||
67 | + FSL_IMX6UL_QSPI1_RX_SIZE = (32 * MiB), | ||
68 | + | ||
69 | + /* AIPS-2 Begin */ | ||
70 | FSL_IMX6UL_UART6_ADDR = 0x021FC000, | ||
71 | + | ||
72 | FSL_IMX6UL_I2C4_ADDR = 0x021F8000, | ||
73 | + | ||
74 | FSL_IMX6UL_UART5_ADDR = 0x021F4000, | ||
75 | FSL_IMX6UL_UART4_ADDR = 0x021F0000, | ||
76 | FSL_IMX6UL_UART3_ADDR = 0x021EC000, | ||
77 | FSL_IMX6UL_UART2_ADDR = 0x021E8000, | ||
78 | + | ||
79 | FSL_IMX6UL_WDOG3_ADDR = 0x021E4000, | ||
80 | + | ||
81 | FSL_IMX6UL_QSPI_ADDR = 0x021E0000, | ||
82 | + FSL_IMX6UL_QSPI_SIZE = 0x500, | ||
83 | + | ||
84 | FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000, | ||
85 | + FSL_IMX6UL_SYS_CNT_CTRL_SIZE = (16 * KiB), | ||
86 | + | ||
87 | FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000, | ||
88 | + FSL_IMX6UL_SYS_CNT_CMP_SIZE = (16 * KiB), | ||
89 | + | ||
90 | FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000, | ||
91 | + FSL_IMX6UL_SYS_CNT_RD_SIZE = (16 * KiB), | ||
92 | + | ||
93 | FSL_IMX6UL_TZASC_ADDR = 0x021D0000, | ||
94 | + FSL_IMX6UL_TZASC_SIZE = (16 * KiB), | ||
95 | + | ||
96 | FSL_IMX6UL_PXP_ADDR = 0x021CC000, | ||
97 | + FSL_IMX6UL_PXP_SIZE = (16 * KiB), | ||
98 | + | ||
99 | FSL_IMX6UL_LCDIF_ADDR = 0x021C8000, | ||
100 | + FSL_IMX6UL_LCDIF_SIZE = 0x100, | ||
101 | + | ||
102 | FSL_IMX6UL_CSI_ADDR = 0x021C4000, | ||
103 | + FSL_IMX6UL_CSI_SIZE = 0x100, | ||
104 | + | ||
105 | FSL_IMX6UL_CSU_ADDR = 0x021C0000, | ||
106 | + FSL_IMX6UL_CSU_SIZE = (16 * KiB), | ||
107 | + | ||
108 | FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000, | ||
109 | + FSL_IMX6UL_OCOTP_CTRL_SIZE = (4 * KiB), | ||
110 | + | ||
111 | FSL_IMX6UL_EIM_ADDR = 0x021B8000, | ||
112 | + FSL_IMX6UL_EIM_SIZE = 0x100, | ||
113 | + | ||
114 | FSL_IMX6UL_SIM2_ADDR = 0x021B4000, | ||
115 | + | ||
116 | FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000, | ||
117 | + FSL_IMX6UL_MMDC_CFG_SIZE = (4 * KiB), | ||
118 | + | ||
119 | FSL_IMX6UL_ROMCP_ADDR = 0x021AC000, | ||
120 | + FSL_IMX6UL_ROMCP_SIZE = 0x300, | ||
121 | + | ||
122 | FSL_IMX6UL_I2C3_ADDR = 0x021A8000, | ||
123 | FSL_IMX6UL_I2C2_ADDR = 0x021A4000, | ||
124 | FSL_IMX6UL_I2C1_ADDR = 0x021A0000, | ||
125 | + | ||
126 | FSL_IMX6UL_ADC2_ADDR = 0x0219C000, | ||
127 | FSL_IMX6UL_ADC1_ADDR = 0x02198000, | ||
128 | + FSL_IMX6UL_ADCn_SIZE = 0x100, | ||
129 | + | ||
130 | FSL_IMX6UL_USDHC2_ADDR = 0x02194000, | ||
131 | FSL_IMX6UL_USDHC1_ADDR = 0x02190000, | ||
132 | - FSL_IMX6UL_SIM1_ADDR = 0x0218C000, | ||
133 | - FSL_IMX6UL_ENET1_ADDR = 0x02188000, | ||
134 | - FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, | ||
135 | - FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000, | ||
136 | - FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000, | ||
137 | - FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000, | ||
138 | - FSL_IMX6UL_CAAM_ADDR = 0x02140000, | ||
139 | - FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000, | ||
140 | |||
141 | - /* AIPS-1 */ | ||
142 | + FSL_IMX6UL_SIM1_ADDR = 0x0218C000, | ||
143 | + FSL_IMX6UL_SIMn_SIZE = (16 * KiB), | ||
144 | + | ||
145 | + FSL_IMX6UL_ENET1_ADDR = 0x02188000, | ||
146 | + | ||
147 | + FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, | ||
148 | + FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000, | ||
149 | + FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200, | ||
150 | + | ||
151 | + FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000, | ||
152 | + FSL_IMX6UL_USBO2_PL301_SIZE = (16 * KiB), | ||
153 | + | ||
154 | + FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000, | ||
155 | + FSL_IMX6UL_AIPS2_CFG_SIZE = 0x100, | ||
156 | + | ||
157 | + FSL_IMX6UL_CAAM_ADDR = 0x02140000, | ||
158 | + FSL_IMX6UL_CAAM_SIZE = (16 * KiB), | ||
159 | + | ||
160 | + FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000, | ||
161 | + FSL_IMX6UL_A7MPCORE_DAP_SIZE = (4 * KiB), | ||
162 | + /* AIPS-2 End */ | ||
163 | + | ||
164 | + /* AIPS-1 Begin */ | ||
165 | FSL_IMX6UL_PWM8_ADDR = 0x020FC000, | ||
166 | FSL_IMX6UL_PWM7_ADDR = 0x020F8000, | ||
167 | FSL_IMX6UL_PWM6_ADDR = 0x020F4000, | ||
168 | FSL_IMX6UL_PWM5_ADDR = 0x020F0000, | ||
169 | + | ||
170 | FSL_IMX6UL_SDMA_ADDR = 0x020EC000, | ||
171 | + FSL_IMX6UL_SDMA_SIZE = 0x300, | ||
172 | + | ||
173 | FSL_IMX6UL_GPT2_ADDR = 0x020E8000, | ||
174 | + | ||
175 | FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000, | ||
176 | + FSL_IMX6UL_IOMUXC_GPR_SIZE = 0x40, | ||
177 | + | ||
178 | FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000, | ||
179 | + FSL_IMX6UL_IOMUXC_SIZE = 0x700, | ||
180 | + | ||
181 | FSL_IMX6UL_GPC_ADDR = 0x020DC000, | ||
182 | + | ||
183 | FSL_IMX6UL_SRC_ADDR = 0x020D8000, | ||
184 | + | ||
185 | FSL_IMX6UL_EPIT2_ADDR = 0x020D4000, | ||
186 | FSL_IMX6UL_EPIT1_ADDR = 0x020D0000, | ||
187 | + | ||
188 | FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000, | ||
189 | + | ||
190 | FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000, | ||
191 | - FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024), | ||
192 | FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000, | ||
193 | - FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024), | ||
194 | + | ||
195 | FSL_IMX6UL_ANALOG_ADDR = 0x020C8000, | ||
196 | + FSL_IMX6UL_ANALOG_SIZE = 0x300, | ||
197 | + | ||
198 | FSL_IMX6UL_CCM_ADDR = 0x020C4000, | ||
199 | + | ||
200 | FSL_IMX6UL_WDOG2_ADDR = 0x020C0000, | ||
201 | FSL_IMX6UL_WDOG1_ADDR = 0x020BC000, | ||
202 | + | ||
203 | FSL_IMX6UL_KPP_ADDR = 0x020B8000, | ||
204 | + FSL_IMX6UL_KPP_SIZE = 0x10, | ||
205 | + | ||
206 | FSL_IMX6UL_ENET2_ADDR = 0x020B4000, | ||
207 | + | ||
208 | FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000, | ||
209 | + FSL_IMX6UL_SNVS_LP_SIZE = (16 * KiB), | ||
210 | + | ||
211 | FSL_IMX6UL_GPIO5_ADDR = 0x020AC000, | ||
212 | FSL_IMX6UL_GPIO4_ADDR = 0x020A8000, | ||
213 | FSL_IMX6UL_GPIO3_ADDR = 0x020A4000, | ||
214 | FSL_IMX6UL_GPIO2_ADDR = 0x020A0000, | ||
215 | FSL_IMX6UL_GPIO1_ADDR = 0x0209C000, | ||
216 | + | ||
217 | FSL_IMX6UL_GPT1_ADDR = 0x02098000, | ||
218 | + | ||
219 | FSL_IMX6UL_CAN2_ADDR = 0x02094000, | ||
220 | FSL_IMX6UL_CAN1_ADDR = 0x02090000, | ||
221 | + FSL_IMX6UL_CANn_SIZE = (4 * KiB), | ||
222 | + | ||
223 | FSL_IMX6UL_PWM4_ADDR = 0x0208C000, | ||
224 | FSL_IMX6UL_PWM3_ADDR = 0x02088000, | ||
225 | FSL_IMX6UL_PWM2_ADDR = 0x02084000, | ||
226 | FSL_IMX6UL_PWM1_ADDR = 0x02080000, | ||
227 | + FSL_IMX6UL_PWMn_SIZE = 0x20, | ||
228 | + | ||
229 | FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000, | ||
230 | + FSL_IMX6UL_AIPS1_CFG_SIZE = (16 * KiB), | ||
231 | + | ||
232 | FSL_IMX6UL_BEE_ADDR = 0x02044000, | ||
233 | + FSL_IMX6UL_BEE_SIZE = (16 * KiB), | ||
234 | + | ||
235 | FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000, | ||
236 | + FSL_IMX6UL_TOUCH_CTRL_SIZE = 0x100, | ||
237 | + | ||
238 | FSL_IMX6UL_SPBA_ADDR = 0x0203C000, | ||
239 | + FSL_IMX6UL_SPBA_SIZE = 0x100, | ||
240 | + | ||
241 | FSL_IMX6UL_ASRC_ADDR = 0x02034000, | ||
242 | + FSL_IMX6UL_ASRC_SIZE = 0x100, | ||
243 | + | ||
244 | FSL_IMX6UL_SAI3_ADDR = 0x02030000, | ||
245 | FSL_IMX6UL_SAI2_ADDR = 0x0202C000, | ||
246 | FSL_IMX6UL_SAI1_ADDR = 0x02028000, | ||
247 | + FSL_IMX6UL_SAIn_SIZE = 0x200, | ||
248 | + | ||
249 | FSL_IMX6UL_UART8_ADDR = 0x02024000, | ||
250 | FSL_IMX6UL_UART1_ADDR = 0x02020000, | ||
251 | FSL_IMX6UL_UART7_ADDR = 0x02018000, | ||
252 | + | ||
253 | FSL_IMX6UL_ECSPI4_ADDR = 0x02014000, | ||
254 | FSL_IMX6UL_ECSPI3_ADDR = 0x02010000, | ||
255 | FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000, | ||
256 | FSL_IMX6UL_ECSPI1_ADDR = 0x02008000, | ||
257 | + | ||
258 | FSL_IMX6UL_SPDIF_ADDR = 0x02004000, | ||
259 | + FSL_IMX6UL_SPDIF_SIZE = 0x100, | ||
260 | + /* AIPS-1 End */ | ||
261 | + | ||
262 | + FSL_IMX6UL_BCH_ADDR = 0x01808000, | ||
263 | + FSL_IMX6UL_BCH_SIZE = 0x200, | ||
264 | + | ||
265 | + FSL_IMX6UL_GPMI_ADDR = 0x01806000, | ||
266 | + FSL_IMX6UL_GPMI_SIZE = 0x200, | ||
267 | |||
268 | FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000, | ||
269 | - FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024), | ||
270 | + FSL_IMX6UL_APBH_DMA_SIZE = (4 * KiB), | ||
271 | |||
272 | FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000, | ||
273 | |||
274 | FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000, | ||
275 | - FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000, | ||
276 | + FSL_IMX6UL_OCRAM_ALIAS_SIZE = (384 * KiB), | ||
277 | + | ||
278 | FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000, | ||
279 | - FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000, | ||
280 | + FSL_IMX6UL_OCRAM_MEM_SIZE = (128 * KiB), | ||
281 | + | ||
282 | FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000, | ||
283 | - FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000, | ||
284 | + FSL_IMX6UL_CAAM_MEM_SIZE = (32 * KiB), | ||
285 | + | ||
286 | FSL_IMX6UL_ROM_ADDR = 0x00000000, | ||
287 | - FSL_IMX6UL_ROM_SIZE = 0x00018000, | ||
288 | + FSL_IMX6UL_ROM_SIZE = (96 * KiB), | ||
289 | }; | ||
290 | |||
291 | enum FslIMX6ULIRQs { | ||
292 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
293 | index XXXXXXX..XXXXXXX 100644 | ||
294 | --- a/hw/arm/fsl-imx6ul.c | ||
295 | +++ b/hw/arm/fsl-imx6ul.c | ||
296 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
297 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
298 | |||
299 | /* | ||
300 | - * GPIOs 1 to 5 | ||
301 | + * GPIOs | ||
302 | */ | ||
303 | for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { | ||
304 | snprintf(name, NAME_SIZE, "gpio%d", i); | ||
305 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
306 | } | ||
307 | |||
308 | /* | ||
309 | - * GPT 1, 2 | ||
310 | + * GPTs | ||
311 | */ | ||
312 | for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { | ||
313 | snprintf(name, NAME_SIZE, "gpt%d", i); | ||
314 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
315 | } | ||
316 | |||
317 | /* | ||
318 | - * EPIT 1, 2 | ||
319 | + * EPITs | ||
320 | */ | ||
321 | for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { | ||
322 | snprintf(name, NAME_SIZE, "epit%d", i + 1); | ||
323 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
324 | } | ||
325 | |||
326 | /* | ||
327 | - * eCSPI | ||
328 | + * eCSPIs | ||
329 | */ | ||
330 | for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { | ||
331 | snprintf(name, NAME_SIZE, "spi%d", i + 1); | ||
332 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
333 | } | ||
334 | |||
335 | /* | ||
336 | - * I2C | ||
337 | + * I2Cs | ||
338 | */ | ||
339 | for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { | ||
340 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); | ||
341 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
342 | } | ||
343 | |||
344 | /* | ||
345 | - * UART | ||
346 | + * UARTs | ||
347 | */ | ||
348 | for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { | ||
349 | snprintf(name, NAME_SIZE, "uart%d", i); | ||
350 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
351 | } | ||
352 | |||
353 | /* | ||
354 | - * Ethernet | ||
355 | + * Ethernets | ||
356 | */ | ||
357 | for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { | ||
358 | snprintf(name, NAME_SIZE, "eth%d", i); | ||
359 | object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); | ||
360 | } | ||
361 | |||
362 | - /* USB */ | ||
363 | + /* | ||
364 | + * USB PHYs | ||
365 | + */ | ||
366 | for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { | ||
367 | snprintf(name, NAME_SIZE, "usbphy%d", i); | ||
368 | object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); | ||
369 | } | ||
370 | + | ||
371 | + /* | ||
372 | + * USBs | ||
373 | + */ | ||
374 | for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { | ||
375 | snprintf(name, NAME_SIZE, "usb%d", i); | ||
376 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); | ||
377 | } | ||
378 | |||
379 | /* | ||
380 | - * SDHCI | ||
381 | + * SDHCIs | ||
382 | */ | ||
383 | for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | ||
384 | snprintf(name, NAME_SIZE, "usdhc%d", i); | ||
385 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
386 | } | ||
387 | |||
388 | /* | ||
389 | - * Watchdog | ||
390 | + * Watchdogs | ||
391 | */ | ||
392 | for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { | ||
393 | snprintf(name, NAME_SIZE, "wdt%d", i); | ||
394 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
395 | * A7MPCORE DAP | ||
396 | */ | ||
397 | create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, | ||
398 | - 0x100000); | ||
399 | + FSL_IMX6UL_A7MPCORE_DAP_SIZE); | ||
400 | |||
401 | /* | ||
402 | - * GPT 1, 2 | ||
403 | + * GPTs | ||
404 | */ | ||
405 | for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { | ||
406 | static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = { | ||
407 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
408 | } | ||
409 | |||
410 | /* | ||
411 | - * EPIT 1, 2 | ||
412 | + * EPITs | ||
413 | */ | ||
414 | for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { | ||
415 | static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = { | ||
416 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
417 | } | ||
418 | |||
419 | /* | ||
420 | - * GPIO | ||
421 | + * GPIOs | ||
422 | */ | ||
423 | for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { | ||
424 | static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = { | ||
425 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
426 | } | ||
427 | |||
428 | /* | ||
429 | - * IOMUXC and IOMUXC_GPR | ||
430 | + * IOMUXC | ||
431 | */ | ||
432 | - for (i = 0; i < 1; i++) { | ||
433 | - static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = { | ||
434 | - FSL_IMX6UL_IOMUXC_ADDR, | ||
435 | - FSL_IMX6UL_IOMUXC_GPR_ADDR, | ||
436 | - }; | ||
437 | - | ||
438 | - snprintf(name, NAME_SIZE, "iomuxc%d", i); | ||
439 | - create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000); | ||
440 | - } | ||
441 | + create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR, | ||
442 | + FSL_IMX6UL_IOMUXC_SIZE); | ||
443 | + create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR, | ||
444 | + FSL_IMX6UL_IOMUXC_GPR_SIZE); | ||
445 | |||
446 | /* | ||
447 | * CCM | ||
448 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
449 | sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); | ||
450 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); | ||
451 | |||
452 | - /* Initialize all ECSPI */ | ||
453 | + /* | ||
454 | + * ECSPIs | ||
455 | + */ | ||
456 | for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { | ||
457 | static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { | ||
458 | FSL_IMX6UL_ECSPI1_ADDR, | ||
459 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
460 | } | ||
461 | |||
462 | /* | ||
463 | - * I2C | ||
464 | + * I2Cs | ||
465 | */ | ||
466 | for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { | ||
467 | static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { | ||
468 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
469 | } | ||
470 | |||
471 | /* | ||
472 | - * UART | ||
473 | + * UARTs | ||
474 | */ | ||
475 | for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { | ||
476 | static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = { | ||
477 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
478 | } | ||
479 | |||
480 | /* | ||
481 | - * Ethernet | ||
482 | + * Ethernets | ||
483 | * | ||
484 | * We must use two loops since phy_connected affects the other interface | ||
485 | * and we have to set all properties before calling sysbus_realize(). | ||
486 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
487 | FSL_IMX6UL_ENETn_TIMER_IRQ[i])); | ||
488 | } | ||
489 | |||
490 | - /* USB */ | ||
491 | + /* | ||
492 | + * USB PHYs | ||
493 | + */ | ||
494 | for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { | ||
495 | + static const hwaddr | ||
496 | + FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = { | ||
497 | + FSL_IMX6UL_USBPHY1_ADDR, | ||
498 | + FSL_IMX6UL_USBPHY2_ADDR, | ||
499 | + }; | ||
500 | + | ||
501 | sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); | ||
502 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, | ||
503 | - FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000); | ||
504 | + FSL_IMX6UL_USB_PHYn_ADDR[i]); | ||
505 | } | ||
506 | |||
507 | + /* | ||
508 | + * USBs | ||
509 | + */ | ||
510 | for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { | ||
511 | + static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = { | ||
512 | + FSL_IMX6UL_USBO2_USB1_ADDR, | ||
513 | + FSL_IMX6UL_USBO2_USB2_ADDR, | ||
514 | + }; | ||
515 | + | ||
516 | static const int FSL_IMX6UL_USBn_IRQ[] = { | ||
517 | FSL_IMX6UL_USB1_IRQ, | ||
518 | FSL_IMX6UL_USB2_IRQ, | ||
519 | }; | ||
520 | + | ||
521 | sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); | ||
522 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, | ||
523 | - FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200); | ||
524 | + FSL_IMX6UL_USB02_USBn_ADDR[i]); | ||
525 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, | ||
526 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
527 | FSL_IMX6UL_USBn_IRQ[i])); | ||
528 | } | ||
529 | |||
530 | /* | ||
531 | - * USDHC | ||
532 | + * USDHCs | ||
533 | */ | ||
534 | for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | ||
535 | static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = { | ||
536 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
537 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); | ||
538 | |||
539 | /* | ||
540 | - * Watchdog | ||
541 | + * Watchdogs | ||
542 | */ | ||
543 | for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { | ||
544 | static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = { | ||
545 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
546 | FSL_IMX6UL_WDOG2_ADDR, | ||
547 | FSL_IMX6UL_WDOG3_ADDR, | ||
548 | }; | ||
549 | + | ||
550 | static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = { | ||
551 | FSL_IMX6UL_WDOG1_IRQ, | ||
552 | FSL_IMX6UL_WDOG2_IRQ, | ||
553 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
554 | /* | ||
555 | * SDMA | ||
556 | */ | ||
557 | - create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); | ||
558 | + create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, | ||
559 | + FSL_IMX6UL_SDMA_SIZE); | ||
560 | |||
561 | /* | ||
562 | - * SAI (Audio SSI (Synchronous Serial Interface)) | ||
563 | + * SAIs (Audio SSI (Synchronous Serial Interface)) | ||
564 | */ | ||
565 | - create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000); | ||
566 | - create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000); | ||
567 | - create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000); | ||
568 | + for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) { | ||
569 | + static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = { | ||
570 | + FSL_IMX6UL_SAI1_ADDR, | ||
571 | + FSL_IMX6UL_SAI2_ADDR, | ||
572 | + FSL_IMX6UL_SAI3_ADDR, | ||
573 | + }; | ||
574 | + | ||
575 | + snprintf(name, NAME_SIZE, "sai%d", i); | ||
576 | + create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i], | ||
577 | + FSL_IMX6UL_SAIn_SIZE); | ||
56 | + } | 578 | + } |
57 | 579 | ||
58 | /* In hardware this is a LAN9220; the LAN9118 is software compatible | 580 | /* |
59 | * except that it doesn't support the checksum-offload feature. | 581 | - * PWM |
60 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | 582 | + * PWMs |
61 | index XXXXXXX..XXXXXXX 100644 | 583 | */ |
62 | --- a/hw/arm/Kconfig | 584 | - create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000); |
63 | +++ b/hw/arm/Kconfig | 585 | - create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000); |
64 | @@ -XXX,XX +XXX,XX @@ config HIGHBANK | 586 | - create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000); |
65 | select ARM_TIMER # sp804 | 587 | - create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000); |
66 | select ARM_V7M | 588 | + for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) { |
67 | select PL011 # UART | 589 | + static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = { |
68 | - select PL022 # Serial port | 590 | + FSL_IMX6UL_PWM1_ADDR, |
69 | + select PL022 # SPI | 591 | + FSL_IMX6UL_PWM2_ADDR, |
70 | select PL031 # RTC | 592 | + FSL_IMX6UL_PWM3_ADDR, |
71 | select PL061 # GPIO | 593 | + FSL_IMX6UL_PWM4_ADDR, |
72 | select PL310 # cache controller | 594 | + }; |
73 | @@ -XXX,XX +XXX,XX @@ config STELLARIS | 595 | + |
74 | select CMSDK_APB_WATCHDOG | 596 | + snprintf(name, NAME_SIZE, "pwm%d", i); |
75 | select I2C | 597 | + create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i], |
76 | select PL011 # UART | 598 | + FSL_IMX6UL_PWMn_SIZE); |
77 | - select PL022 # Serial port | 599 | + } |
78 | + select PL022 # SPI | 600 | |
79 | select PL061 # GPIO | 601 | /* |
80 | select SSD0303 # OLED display | 602 | * Audio ASRC (asynchronous sample rate converter) |
81 | select SSD0323 # OLED display | 603 | */ |
82 | @@ -XXX,XX +XXX,XX @@ config MPS2 | 604 | - create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000); |
83 | select MPS2_FPGAIO | 605 | + create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, |
84 | select MPS2_SCC | 606 | + FSL_IMX6UL_ASRC_SIZE); |
85 | select OR_IRQ | 607 | |
86 | - select PL022 # Serial port | 608 | /* |
87 | + select PL022 # SPI | 609 | - * CAN |
88 | select PL080 # DMA controller | 610 | + * CANs |
89 | select SPLIT_IRQ | 611 | */ |
90 | select UNIMP | 612 | - create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000); |
613 | - create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000); | ||
614 | + for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) { | ||
615 | + static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = { | ||
616 | + FSL_IMX6UL_CAN1_ADDR, | ||
617 | + FSL_IMX6UL_CAN2_ADDR, | ||
618 | + }; | ||
619 | + | ||
620 | + snprintf(name, NAME_SIZE, "can%d", i); | ||
621 | + create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i], | ||
622 | + FSL_IMX6UL_CANn_SIZE); | ||
623 | + } | ||
624 | |||
625 | /* | ||
626 | * APHB_DMA | ||
627 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
628 | }; | ||
629 | |||
630 | snprintf(name, NAME_SIZE, "adc%d", i); | ||
631 | - create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000); | ||
632 | + create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], | ||
633 | + FSL_IMX6UL_ADCn_SIZE); | ||
634 | } | ||
635 | |||
636 | /* | ||
637 | * LCD | ||
638 | */ | ||
639 | - create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000); | ||
640 | + create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, | ||
641 | + FSL_IMX6UL_LCDIF_SIZE); | ||
642 | |||
643 | /* | ||
644 | * ROM memory | ||
91 | -- | 645 | -- |
92 | 2.20.1 | 646 | 2.34.1 |
93 | |||
94 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Use self-explicit definitions instead of magic values. | 3 | * Add TZASC as unimplemented device. |
4 | - Allow bare metal application to access this (unimplemented) device | ||
5 | * Add CSU as unimplemented device. | ||
6 | - Allow bare metal application to access this (unimplemented) device | ||
7 | * Add 4 missing PWM devices | ||
4 | 8 | ||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
6 | Message-id: 20200617072539.32686-3-f4bug@amsat.org | 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 13 | --- |
10 | hw/i2c/versatile_i2c.c | 14 ++++++++++---- | 14 | include/hw/arm/fsl-imx6ul.h | 2 +- |
11 | 1 file changed, 10 insertions(+), 4 deletions(-) | 15 | hw/arm/fsl-imx6ul.c | 16 ++++++++++++++++ |
16 | 2 files changed, 17 insertions(+), 1 deletion(-) | ||
12 | 17 | ||
13 | diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c | 18 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h |
14 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/i2c/versatile_i2c.c | 20 | --- a/include/hw/arm/fsl-imx6ul.h |
16 | +++ b/hw/i2c/versatile_i2c.c | 21 | +++ b/include/hw/arm/fsl-imx6ul.h |
17 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration { |
18 | #include "qemu/osdep.h" | 23 | FSL_IMX6UL_NUM_USBS = 2, |
19 | #include "hw/sysbus.h" | 24 | FSL_IMX6UL_NUM_SAIS = 3, |
20 | #include "hw/i2c/bitbang_i2c.h" | 25 | FSL_IMX6UL_NUM_CANS = 2, |
21 | +#include "hw/registerfields.h" | 26 | - FSL_IMX6UL_NUM_PWMS = 4, |
22 | #include "qemu/log.h" | 27 | + FSL_IMX6UL_NUM_PWMS = 8, |
23 | #include "qemu/module.h" | 28 | }; |
24 | 29 | ||
25 | @@ -XXX,XX +XXX,XX @@ typedef struct VersatileI2CState { | 30 | struct FslIMX6ULState { |
26 | int in; | 31 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c |
27 | } VersatileI2CState; | 32 | index XXXXXXX..XXXXXXX 100644 |
28 | 33 | --- a/hw/arm/fsl-imx6ul.c | |
29 | +REG32(CONTROL_GET, 0) | 34 | +++ b/hw/arm/fsl-imx6ul.c |
30 | +REG32(CONTROL_SET, 0) | 35 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) |
31 | +REG32(CONTROL_CLR, 4) | 36 | FSL_IMX6UL_PWM2_ADDR, |
37 | FSL_IMX6UL_PWM3_ADDR, | ||
38 | FSL_IMX6UL_PWM4_ADDR, | ||
39 | + FSL_IMX6UL_PWM5_ADDR, | ||
40 | + FSL_IMX6UL_PWM6_ADDR, | ||
41 | + FSL_IMX6UL_PWM7_ADDR, | ||
42 | + FSL_IMX6UL_PWM8_ADDR, | ||
43 | }; | ||
44 | |||
45 | snprintf(name, NAME_SIZE, "pwm%d", i); | ||
46 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
47 | create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, | ||
48 | FSL_IMX6UL_LCDIF_SIZE); | ||
49 | |||
50 | + /* | ||
51 | + * CSU | ||
52 | + */ | ||
53 | + create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR, | ||
54 | + FSL_IMX6UL_CSU_SIZE); | ||
32 | + | 55 | + |
33 | static uint64_t versatile_i2c_read(void *opaque, hwaddr offset, | 56 | + /* |
34 | unsigned size) | 57 | + * TZASC |
35 | { | 58 | + */ |
36 | VersatileI2CState *s = (VersatileI2CState *)opaque; | 59 | + create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR, |
37 | 60 | + FSL_IMX6UL_TZASC_SIZE); | |
38 | - if (offset == 0) { | 61 | + |
39 | + switch (offset) { | 62 | /* |
40 | + case A_CONTROL_SET: | 63 | * ROM memory |
41 | return (s->out & 1) | (s->in << 1); | 64 | */ |
42 | - } else { | ||
43 | + default: | ||
44 | qemu_log_mask(LOG_GUEST_ERROR, | ||
45 | "%s: Bad offset 0x%x\n", __func__, (int)offset); | ||
46 | return -1; | ||
47 | @@ -XXX,XX +XXX,XX @@ static void versatile_i2c_write(void *opaque, hwaddr offset, | ||
48 | VersatileI2CState *s = (VersatileI2CState *)opaque; | ||
49 | |||
50 | switch (offset) { | ||
51 | - case 0: | ||
52 | + case A_CONTROL_SET: | ||
53 | s->out |= value & 3; | ||
54 | break; | ||
55 | - case 4: | ||
56 | + case A_CONTROL_CLR: | ||
57 | s->out &= ~value; | ||
58 | break; | ||
59 | default: | ||
60 | -- | 65 | -- |
61 | 2.20.1 | 66 | 2.34.1 |
62 | 67 | ||
63 | 68 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Some cpu features may be enabled and disabled for all configurations | 3 | * Add Addr and size definition for all i.MX7 devices in i.MX7 header file. |
4 | that support the feature. Let's test that. | 4 | * Use those newly defined named constants whenever possible. |
5 | * Standardize the way we init a familly of unimplemented devices | ||
6 | - SAI | ||
7 | - PWM | ||
8 | - CAN | ||
9 | * Add/rework few comments | ||
5 | 10 | ||
6 | A recent regression[*] inspired adding these tests. | 11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
7 | 12 | Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net | |
8 | [*] '-cpu host,pmu=on' caused a segfault | ||
9 | |||
10 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
11 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
12 | Message-id: 20200623090622.30365-2-philmd@redhat.com | ||
13 | Message-Id: <20200623082310.17577-1-drjones@redhat.com> | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 15 | --- |
17 | tests/qtest/arm-cpu-features.c | 38 ++++++++++++++++++++++++++++++---- | 16 | include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++---------- |
18 | 1 file changed, 34 insertions(+), 4 deletions(-) | 17 | hw/arm/fsl-imx7.c | 130 ++++++++++----- |
18 | 2 files changed, 335 insertions(+), 125 deletions(-) | ||
19 | 19 | ||
20 | diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c | 20 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h |
21 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/tests/qtest/arm-cpu-features.c | 22 | --- a/include/hw/arm/fsl-imx7.h |
23 | +++ b/tests/qtest/arm-cpu-features.c | 23 | +++ b/include/hw/arm/fsl-imx7.h |
24 | @@ -XXX,XX +XXX,XX @@ static bool resp_get_feature(QDict *resp, const char *feature) | 24 | @@ -XXX,XX +XXX,XX @@ |
25 | qobject_unref(_resp); \ | 25 | #include "hw/misc/imx7_ccm.h" |
26 | }) | 26 | #include "hw/misc/imx7_snvs.h" |
27 | 27 | #include "hw/misc/imx7_gpr.h" | |
28 | -#define assert_feature(qts, cpu_type, feature, expected_value) \ | 28 | -#include "hw/misc/imx6_src.h" |
29 | +#define resp_assert_feature(resp, feature, expected_value) \ | 29 | #include "hw/watchdog/wdt_imx2.h" |
30 | ({ \ | 30 | #include "hw/gpio/imx_gpio.h" |
31 | - QDict *_resp, *_props; \ | 31 | #include "hw/char/imx_serial.h" |
32 | + QDict *_props; \ | 32 | @@ -XXX,XX +XXX,XX @@ |
33 | \ | 33 | #include "hw/usb/chipidea.h" |
34 | - _resp = do_query_no_props(qts, cpu_type); \ | 34 | #include "cpu.h" |
35 | g_assert(_resp); \ | 35 | #include "qom/object.h" |
36 | g_assert(resp_has_props(_resp)); \ | 36 | +#include "qemu/units.h" |
37 | _props = resp_get_props(_resp); \ | 37 | |
38 | g_assert(qdict_get(_props, feature)); \ | 38 | #define TYPE_FSL_IMX7 "fsl-imx7" |
39 | g_assert(qdict_get_bool(_props, feature) == (expected_value)); \ | 39 | OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) |
40 | +}) | 40 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration { |
41 | + | 41 | FSL_IMX7_NUM_ECSPIS = 4, |
42 | +#define assert_feature(qts, cpu_type, feature, expected_value) \ | 42 | FSL_IMX7_NUM_USBS = 3, |
43 | +({ \ | 43 | FSL_IMX7_NUM_ADCS = 2, |
44 | + QDict *_resp; \ | 44 | + FSL_IMX7_NUM_SAIS = 3, |
45 | + \ | 45 | + FSL_IMX7_NUM_CANS = 2, |
46 | + _resp = do_query_no_props(qts, cpu_type); \ | 46 | + FSL_IMX7_NUM_PWMS = 4, |
47 | + g_assert(_resp); \ | 47 | }; |
48 | + resp_assert_feature(_resp, feature, expected_value); \ | 48 | |
49 | + qobject_unref(_resp); \ | 49 | struct FslIMX7State { |
50 | +}) | 50 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
51 | + | 51 | |
52 | +#define assert_set_feature(qts, cpu_type, feature, value) \ | 52 | enum FslIMX7MemoryMap { |
53 | +({ \ | 53 | FSL_IMX7_MMDC_ADDR = 0x80000000, |
54 | + const char *_fmt = (value) ? "{ %s: true }" : "{ %s: false }"; \ | 54 | - FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, |
55 | + QDict *_resp; \ | 55 | + FSL_IMX7_MMDC_SIZE = (2 * GiB), |
56 | + \ | 56 | |
57 | + _resp = do_query(qts, cpu_type, _fmt, feature); \ | 57 | - FSL_IMX7_GPIO1_ADDR = 0x30200000, |
58 | + g_assert(_resp); \ | 58 | - FSL_IMX7_GPIO2_ADDR = 0x30210000, |
59 | + resp_assert_feature(_resp, feature, value); \ | 59 | - FSL_IMX7_GPIO3_ADDR = 0x30220000, |
60 | qobject_unref(_resp); \ | 60 | - FSL_IMX7_GPIO4_ADDR = 0x30230000, |
61 | }) | 61 | - FSL_IMX7_GPIO5_ADDR = 0x30240000, |
62 | 62 | - FSL_IMX7_GPIO6_ADDR = 0x30250000, | |
63 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion(const void *data) | 63 | - FSL_IMX7_GPIO7_ADDR = 0x30260000, |
64 | assert_error(qts, "host", "The CPU type 'host' requires KVM", NULL); | 64 | + FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000, |
65 | 65 | + FSL_IMX7_QSPI1_MEM_SIZE = (256 * MiB), | |
66 | /* Test expected feature presence/absence for some cpu types */ | 66 | |
67 | - assert_has_feature_enabled(qts, "max", "pmu"); | 67 | - FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, |
68 | assert_has_feature_enabled(qts, "cortex-a15", "pmu"); | 68 | + FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000, |
69 | assert_has_not_feature(qts, "cortex-a15", "aarch64"); | 69 | + FSL_IMX7_PCIE1_MEM_SIZE = (256 * MiB), |
70 | 70 | ||
71 | + /* Enabling and disabling pmu should always work. */ | 71 | - FSL_IMX7_WDOG1_ADDR = 0x30280000, |
72 | + assert_has_feature_enabled(qts, "max", "pmu"); | 72 | - FSL_IMX7_WDOG2_ADDR = 0x30290000, |
73 | + assert_set_feature(qts, "max", "pmu", false); | 73 | - FSL_IMX7_WDOG3_ADDR = 0x302A0000, |
74 | + assert_set_feature(qts, "max", "pmu", true); | 74 | - FSL_IMX7_WDOG4_ADDR = 0x302B0000, |
75 | + | 75 | + FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000, |
76 | assert_has_not_feature(qts, "max", "kvm-no-adjvtime"); | 76 | + FSL_IMX7_QSPI1_RX_BUF_SIZE = (32 * MiB), |
77 | 77 | ||
78 | if (g_str_equal(qtest_get_arch(), "aarch64")) { | 78 | - FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, |
79 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) | 79 | + /* PCIe Peripherals */ |
80 | + FSL_IMX7_PCIE_REG_ADDR = 0x33800000, | ||
81 | |||
82 | - FSL_IMX7_GPT1_ADDR = 0x302D0000, | ||
83 | - FSL_IMX7_GPT2_ADDR = 0x302E0000, | ||
84 | - FSL_IMX7_GPT3_ADDR = 0x302F0000, | ||
85 | - FSL_IMX7_GPT4_ADDR = 0x30300000, | ||
86 | + /* MMAP Peripherals */ | ||
87 | + FSL_IMX7_DMA_APBH_ADDR = 0x33000000, | ||
88 | + FSL_IMX7_DMA_APBH_SIZE = 0x8000, | ||
89 | |||
90 | - FSL_IMX7_IOMUXC_ADDR = 0x30330000, | ||
91 | - FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, | ||
92 | - FSL_IMX7_IOMUXCn_SIZE = 0x1000, | ||
93 | + /* GPV configuration */ | ||
94 | + FSL_IMX7_GPV6_ADDR = 0x32600000, | ||
95 | + FSL_IMX7_GPV5_ADDR = 0x32500000, | ||
96 | + FSL_IMX7_GPV4_ADDR = 0x32400000, | ||
97 | + FSL_IMX7_GPV3_ADDR = 0x32300000, | ||
98 | + FSL_IMX7_GPV2_ADDR = 0x32200000, | ||
99 | + FSL_IMX7_GPV1_ADDR = 0x32100000, | ||
100 | + FSL_IMX7_GPV0_ADDR = 0x32000000, | ||
101 | + FSL_IMX7_GPVn_SIZE = (1 * MiB), | ||
102 | |||
103 | - FSL_IMX7_OCOTP_ADDR = 0x30350000, | ||
104 | - FSL_IMX7_OCOTP_SIZE = 0x10000, | ||
105 | + /* Arm Peripherals */ | ||
106 | + FSL_IMX7_A7MPCORE_ADDR = 0x31000000, | ||
107 | |||
108 | - FSL_IMX7_ANALOG_ADDR = 0x30360000, | ||
109 | - FSL_IMX7_SNVS_ADDR = 0x30370000, | ||
110 | - FSL_IMX7_CCM_ADDR = 0x30380000, | ||
111 | + /* AIPS-3 Begin */ | ||
112 | |||
113 | - FSL_IMX7_SRC_ADDR = 0x30390000, | ||
114 | - FSL_IMX7_SRC_SIZE = 0x1000, | ||
115 | + FSL_IMX7_ENET2_ADDR = 0x30BF0000, | ||
116 | + FSL_IMX7_ENET1_ADDR = 0x30BE0000, | ||
117 | |||
118 | - FSL_IMX7_ADC1_ADDR = 0x30610000, | ||
119 | - FSL_IMX7_ADC2_ADDR = 0x30620000, | ||
120 | - FSL_IMX7_ADCn_SIZE = 0x1000, | ||
121 | + FSL_IMX7_SDMA_ADDR = 0x30BD0000, | ||
122 | + FSL_IMX7_SDMA_SIZE = (4 * KiB), | ||
123 | |||
124 | - FSL_IMX7_PWM1_ADDR = 0x30660000, | ||
125 | - FSL_IMX7_PWM2_ADDR = 0x30670000, | ||
126 | - FSL_IMX7_PWM3_ADDR = 0x30680000, | ||
127 | - FSL_IMX7_PWM4_ADDR = 0x30690000, | ||
128 | - FSL_IMX7_PWMn_SIZE = 0x10000, | ||
129 | + FSL_IMX7_EIM_ADDR = 0x30BC0000, | ||
130 | + FSL_IMX7_EIM_SIZE = (4 * KiB), | ||
131 | |||
132 | - FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, | ||
133 | - FSL_IMX7_PCIE_PHY_SIZE = 0x10000, | ||
134 | + FSL_IMX7_QSPI_ADDR = 0x30BB0000, | ||
135 | + FSL_IMX7_QSPI_SIZE = 0x8000, | ||
136 | |||
137 | - FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
138 | + FSL_IMX7_SIM2_ADDR = 0x30BA0000, | ||
139 | + FSL_IMX7_SIM1_ADDR = 0x30B90000, | ||
140 | + FSL_IMX7_SIMn_SIZE = (4 * KiB), | ||
141 | + | ||
142 | + FSL_IMX7_USDHC3_ADDR = 0x30B60000, | ||
143 | + FSL_IMX7_USDHC2_ADDR = 0x30B50000, | ||
144 | + FSL_IMX7_USDHC1_ADDR = 0x30B40000, | ||
145 | + | ||
146 | + FSL_IMX7_USB3_ADDR = 0x30B30000, | ||
147 | + FSL_IMX7_USBMISC3_ADDR = 0x30B30200, | ||
148 | + FSL_IMX7_USB2_ADDR = 0x30B20000, | ||
149 | + FSL_IMX7_USBMISC2_ADDR = 0x30B20200, | ||
150 | + FSL_IMX7_USB1_ADDR = 0x30B10000, | ||
151 | + FSL_IMX7_USBMISC1_ADDR = 0x30B10200, | ||
152 | + FSL_IMX7_USBMISCn_SIZE = 0x200, | ||
153 | + | ||
154 | + FSL_IMX7_USB_PL301_ADDR = 0x30AD0000, | ||
155 | + FSL_IMX7_USB_PL301_SIZE = (64 * KiB), | ||
156 | + | ||
157 | + FSL_IMX7_SEMAPHORE_HS_ADDR = 0x30AC0000, | ||
158 | + FSL_IMX7_SEMAPHORE_HS_SIZE = (64 * KiB), | ||
159 | + | ||
160 | + FSL_IMX7_MUB_ADDR = 0x30AB0000, | ||
161 | + FSL_IMX7_MUA_ADDR = 0x30AA0000, | ||
162 | + FSL_IMX7_MUn_SIZE = (KiB), | ||
163 | + | ||
164 | + FSL_IMX7_UART7_ADDR = 0x30A90000, | ||
165 | + FSL_IMX7_UART6_ADDR = 0x30A80000, | ||
166 | + FSL_IMX7_UART5_ADDR = 0x30A70000, | ||
167 | + FSL_IMX7_UART4_ADDR = 0x30A60000, | ||
168 | + | ||
169 | + FSL_IMX7_I2C4_ADDR = 0x30A50000, | ||
170 | + FSL_IMX7_I2C3_ADDR = 0x30A40000, | ||
171 | + FSL_IMX7_I2C2_ADDR = 0x30A30000, | ||
172 | + FSL_IMX7_I2C1_ADDR = 0x30A20000, | ||
173 | + | ||
174 | + FSL_IMX7_CAN2_ADDR = 0x30A10000, | ||
175 | + FSL_IMX7_CAN1_ADDR = 0x30A00000, | ||
176 | + FSL_IMX7_CANn_SIZE = (4 * KiB), | ||
177 | + | ||
178 | + FSL_IMX7_AIPS3_CONF_ADDR = 0x309F0000, | ||
179 | + FSL_IMX7_AIPS3_CONF_SIZE = (64 * KiB), | ||
180 | |||
181 | FSL_IMX7_CAAM_ADDR = 0x30900000, | ||
182 | - FSL_IMX7_CAAM_SIZE = 0x40000, | ||
183 | + FSL_IMX7_CAAM_SIZE = (256 * KiB), | ||
184 | |||
185 | - FSL_IMX7_CAN1_ADDR = 0x30A00000, | ||
186 | - FSL_IMX7_CAN2_ADDR = 0x30A10000, | ||
187 | - FSL_IMX7_CANn_SIZE = 0x10000, | ||
188 | + FSL_IMX7_SPBA_ADDR = 0x308F0000, | ||
189 | + FSL_IMX7_SPBA_SIZE = (4 * KiB), | ||
190 | |||
191 | - FSL_IMX7_I2C1_ADDR = 0x30A20000, | ||
192 | - FSL_IMX7_I2C2_ADDR = 0x30A30000, | ||
193 | - FSL_IMX7_I2C3_ADDR = 0x30A40000, | ||
194 | - FSL_IMX7_I2C4_ADDR = 0x30A50000, | ||
195 | + FSL_IMX7_SAI3_ADDR = 0x308C0000, | ||
196 | + FSL_IMX7_SAI2_ADDR = 0x308B0000, | ||
197 | + FSL_IMX7_SAI1_ADDR = 0x308A0000, | ||
198 | + FSL_IMX7_SAIn_SIZE = (4 * KiB), | ||
199 | |||
200 | - FSL_IMX7_ECSPI1_ADDR = 0x30820000, | ||
201 | - FSL_IMX7_ECSPI2_ADDR = 0x30830000, | ||
202 | - FSL_IMX7_ECSPI3_ADDR = 0x30840000, | ||
203 | - FSL_IMX7_ECSPI4_ADDR = 0x30630000, | ||
204 | - | ||
205 | - FSL_IMX7_LCDIF_ADDR = 0x30730000, | ||
206 | - FSL_IMX7_LCDIF_SIZE = 0x1000, | ||
207 | - | ||
208 | - FSL_IMX7_UART1_ADDR = 0x30860000, | ||
209 | + FSL_IMX7_UART3_ADDR = 0x30880000, | ||
210 | /* | ||
211 | * Some versions of the reference manual claim that UART2 is @ | ||
212 | * 0x30870000, but experiments with HW + DT files in upstream | ||
213 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap { | ||
214 | * actually located @ 0x30890000 | ||
215 | */ | ||
216 | FSL_IMX7_UART2_ADDR = 0x30890000, | ||
217 | - FSL_IMX7_UART3_ADDR = 0x30880000, | ||
218 | - FSL_IMX7_UART4_ADDR = 0x30A60000, | ||
219 | - FSL_IMX7_UART5_ADDR = 0x30A70000, | ||
220 | - FSL_IMX7_UART6_ADDR = 0x30A80000, | ||
221 | - FSL_IMX7_UART7_ADDR = 0x30A90000, | ||
222 | + FSL_IMX7_UART1_ADDR = 0x30860000, | ||
223 | |||
224 | - FSL_IMX7_SAI1_ADDR = 0x308A0000, | ||
225 | - FSL_IMX7_SAI2_ADDR = 0x308B0000, | ||
226 | - FSL_IMX7_SAI3_ADDR = 0x308C0000, | ||
227 | - FSL_IMX7_SAIn_SIZE = 0x10000, | ||
228 | + FSL_IMX7_ECSPI3_ADDR = 0x30840000, | ||
229 | + FSL_IMX7_ECSPI2_ADDR = 0x30830000, | ||
230 | + FSL_IMX7_ECSPI1_ADDR = 0x30820000, | ||
231 | + FSL_IMX7_ECSPIn_SIZE = (4 * KiB), | ||
232 | |||
233 | - FSL_IMX7_ENET1_ADDR = 0x30BE0000, | ||
234 | - FSL_IMX7_ENET2_ADDR = 0x30BF0000, | ||
235 | + /* AIPS-3 End */ | ||
236 | |||
237 | - FSL_IMX7_USB1_ADDR = 0x30B10000, | ||
238 | - FSL_IMX7_USBMISC1_ADDR = 0x30B10200, | ||
239 | - FSL_IMX7_USB2_ADDR = 0x30B20000, | ||
240 | - FSL_IMX7_USBMISC2_ADDR = 0x30B20200, | ||
241 | - FSL_IMX7_USB3_ADDR = 0x30B30000, | ||
242 | - FSL_IMX7_USBMISC3_ADDR = 0x30B30200, | ||
243 | - FSL_IMX7_USBMISCn_SIZE = 0x200, | ||
244 | + /* AIPS-2 Begin */ | ||
245 | |||
246 | - FSL_IMX7_USDHC1_ADDR = 0x30B40000, | ||
247 | - FSL_IMX7_USDHC2_ADDR = 0x30B50000, | ||
248 | - FSL_IMX7_USDHC3_ADDR = 0x30B60000, | ||
249 | + FSL_IMX7_AXI_DEBUG_MON_ADDR = 0x307E0000, | ||
250 | + FSL_IMX7_AXI_DEBUG_MON_SIZE = (64 * KiB), | ||
251 | |||
252 | - FSL_IMX7_SDMA_ADDR = 0x30BD0000, | ||
253 | - FSL_IMX7_SDMA_SIZE = 0x1000, | ||
254 | + FSL_IMX7_PERFMON2_ADDR = 0x307D0000, | ||
255 | + FSL_IMX7_PERFMON1_ADDR = 0x307C0000, | ||
256 | + FSL_IMX7_PERFMONn_SIZE = (64 * KiB), | ||
257 | + | ||
258 | + FSL_IMX7_DDRC_ADDR = 0x307A0000, | ||
259 | + FSL_IMX7_DDRC_SIZE = (4 * KiB), | ||
260 | + | ||
261 | + FSL_IMX7_DDRC_PHY_ADDR = 0x30790000, | ||
262 | + FSL_IMX7_DDRC_PHY_SIZE = (4 * KiB), | ||
263 | + | ||
264 | + FSL_IMX7_TZASC_ADDR = 0x30780000, | ||
265 | + FSL_IMX7_TZASC_SIZE = (64 * KiB), | ||
266 | + | ||
267 | + FSL_IMX7_MIPI_DSI_ADDR = 0x30760000, | ||
268 | + FSL_IMX7_MIPI_DSI_SIZE = (4 * KiB), | ||
269 | + | ||
270 | + FSL_IMX7_MIPI_CSI_ADDR = 0x30750000, | ||
271 | + FSL_IMX7_MIPI_CSI_SIZE = 0x4000, | ||
272 | + | ||
273 | + FSL_IMX7_LCDIF_ADDR = 0x30730000, | ||
274 | + FSL_IMX7_LCDIF_SIZE = 0x8000, | ||
275 | + | ||
276 | + FSL_IMX7_CSI_ADDR = 0x30710000, | ||
277 | + FSL_IMX7_CSI_SIZE = (4 * KiB), | ||
278 | + | ||
279 | + FSL_IMX7_PXP_ADDR = 0x30700000, | ||
280 | + FSL_IMX7_PXP_SIZE = 0x4000, | ||
281 | + | ||
282 | + FSL_IMX7_EPDC_ADDR = 0x306F0000, | ||
283 | + FSL_IMX7_EPDC_SIZE = (4 * KiB), | ||
284 | + | ||
285 | + FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, | ||
286 | + FSL_IMX7_PCIE_PHY_SIZE = (4 * KiB), | ||
287 | + | ||
288 | + FSL_IMX7_SYSCNT_CTRL_ADDR = 0x306C0000, | ||
289 | + FSL_IMX7_SYSCNT_CMP_ADDR = 0x306B0000, | ||
290 | + FSL_IMX7_SYSCNT_RD_ADDR = 0x306A0000, | ||
291 | + | ||
292 | + FSL_IMX7_PWM4_ADDR = 0x30690000, | ||
293 | + FSL_IMX7_PWM3_ADDR = 0x30680000, | ||
294 | + FSL_IMX7_PWM2_ADDR = 0x30670000, | ||
295 | + FSL_IMX7_PWM1_ADDR = 0x30660000, | ||
296 | + FSL_IMX7_PWMn_SIZE = (4 * KiB), | ||
297 | + | ||
298 | + FSL_IMX7_FlEXTIMER2_ADDR = 0x30650000, | ||
299 | + FSL_IMX7_FlEXTIMER1_ADDR = 0x30640000, | ||
300 | + FSL_IMX7_FLEXTIMERn_SIZE = (4 * KiB), | ||
301 | + | ||
302 | + FSL_IMX7_ECSPI4_ADDR = 0x30630000, | ||
303 | + | ||
304 | + FSL_IMX7_ADC2_ADDR = 0x30620000, | ||
305 | + FSL_IMX7_ADC1_ADDR = 0x30610000, | ||
306 | + FSL_IMX7_ADCn_SIZE = (4 * KiB), | ||
307 | + | ||
308 | + FSL_IMX7_AIPS2_CONF_ADDR = 0x305F0000, | ||
309 | + FSL_IMX7_AIPS2_CONF_SIZE = (64 * KiB), | ||
310 | + | ||
311 | + /* AIPS-2 End */ | ||
312 | + | ||
313 | + /* AIPS-1 Begin */ | ||
314 | + | ||
315 | + FSL_IMX7_CSU_ADDR = 0x303E0000, | ||
316 | + FSL_IMX7_CSU_SIZE = (64 * KiB), | ||
317 | + | ||
318 | + FSL_IMX7_RDC_ADDR = 0x303D0000, | ||
319 | + FSL_IMX7_RDC_SIZE = (4 * KiB), | ||
320 | + | ||
321 | + FSL_IMX7_SEMAPHORE2_ADDR = 0x303C0000, | ||
322 | + FSL_IMX7_SEMAPHORE1_ADDR = 0x303B0000, | ||
323 | + FSL_IMX7_SEMAPHOREn_SIZE = (4 * KiB), | ||
324 | + | ||
325 | + FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
326 | + | ||
327 | + FSL_IMX7_SRC_ADDR = 0x30390000, | ||
328 | + FSL_IMX7_SRC_SIZE = (4 * KiB), | ||
329 | + | ||
330 | + FSL_IMX7_CCM_ADDR = 0x30380000, | ||
331 | + | ||
332 | + FSL_IMX7_SNVS_HP_ADDR = 0x30370000, | ||
333 | + | ||
334 | + FSL_IMX7_ANALOG_ADDR = 0x30360000, | ||
335 | + | ||
336 | + FSL_IMX7_OCOTP_ADDR = 0x30350000, | ||
337 | + FSL_IMX7_OCOTP_SIZE = 0x10000, | ||
338 | + | ||
339 | + FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, | ||
340 | + FSL_IMX7_IOMUXC_GPR_SIZE = (4 * KiB), | ||
341 | + | ||
342 | + FSL_IMX7_IOMUXC_ADDR = 0x30330000, | ||
343 | + FSL_IMX7_IOMUXC_SIZE = (4 * KiB), | ||
344 | + | ||
345 | + FSL_IMX7_KPP_ADDR = 0x30320000, | ||
346 | + FSL_IMX7_KPP_SIZE = (4 * KiB), | ||
347 | + | ||
348 | + FSL_IMX7_ROMCP_ADDR = 0x30310000, | ||
349 | + FSL_IMX7_ROMCP_SIZE = (4 * KiB), | ||
350 | + | ||
351 | + FSL_IMX7_GPT4_ADDR = 0x30300000, | ||
352 | + FSL_IMX7_GPT3_ADDR = 0x302F0000, | ||
353 | + FSL_IMX7_GPT2_ADDR = 0x302E0000, | ||
354 | + FSL_IMX7_GPT1_ADDR = 0x302D0000, | ||
355 | + | ||
356 | + FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, | ||
357 | + FSL_IMX7_IOMUXC_LPSR_SIZE = (4 * KiB), | ||
358 | + | ||
359 | + FSL_IMX7_WDOG4_ADDR = 0x302B0000, | ||
360 | + FSL_IMX7_WDOG3_ADDR = 0x302A0000, | ||
361 | + FSL_IMX7_WDOG2_ADDR = 0x30290000, | ||
362 | + FSL_IMX7_WDOG1_ADDR = 0x30280000, | ||
363 | + | ||
364 | + FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, | ||
365 | + | ||
366 | + FSL_IMX7_GPIO7_ADDR = 0x30260000, | ||
367 | + FSL_IMX7_GPIO6_ADDR = 0x30250000, | ||
368 | + FSL_IMX7_GPIO5_ADDR = 0x30240000, | ||
369 | + FSL_IMX7_GPIO4_ADDR = 0x30230000, | ||
370 | + FSL_IMX7_GPIO3_ADDR = 0x30220000, | ||
371 | + FSL_IMX7_GPIO2_ADDR = 0x30210000, | ||
372 | + FSL_IMX7_GPIO1_ADDR = 0x30200000, | ||
373 | + | ||
374 | + FSL_IMX7_AIPS1_CONF_ADDR = 0x301F0000, | ||
375 | + FSL_IMX7_AIPS1_CONF_SIZE = (64 * KiB), | ||
376 | |||
377 | - FSL_IMX7_A7MPCORE_ADDR = 0x31000000, | ||
378 | FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000, | ||
379 | + FSL_IMX7_A7MPCORE_DAP_SIZE = (1 * MiB), | ||
380 | |||
381 | - FSL_IMX7_PCIE_REG_ADDR = 0x33800000, | ||
382 | - FSL_IMX7_PCIE_REG_SIZE = 16 * 1024, | ||
383 | + /* AIPS-1 End */ | ||
384 | |||
385 | - FSL_IMX7_GPR_ADDR = 0x30340000, | ||
386 | + FSL_IMX7_EIM_CS0_ADDR = 0x28000000, | ||
387 | + FSL_IMX7_EIM_CS0_SIZE = (128 * MiB), | ||
388 | |||
389 | - FSL_IMX7_DMA_APBH_ADDR = 0x33000000, | ||
390 | - FSL_IMX7_DMA_APBH_SIZE = 0x2000, | ||
391 | + FSL_IMX7_OCRAM_PXP_ADDR = 0x00940000, | ||
392 | + FSL_IMX7_OCRAM_PXP_SIZE = (32 * KiB), | ||
393 | + | ||
394 | + FSL_IMX7_OCRAM_EPDC_ADDR = 0x00920000, | ||
395 | + FSL_IMX7_OCRAM_EPDC_SIZE = (128 * KiB), | ||
396 | + | ||
397 | + FSL_IMX7_OCRAM_MEM_ADDR = 0x00900000, | ||
398 | + FSL_IMX7_OCRAM_MEM_SIZE = (128 * KiB), | ||
399 | + | ||
400 | + FSL_IMX7_TCMU_ADDR = 0x00800000, | ||
401 | + FSL_IMX7_TCMU_SIZE = (32 * KiB), | ||
402 | + | ||
403 | + FSL_IMX7_TCML_ADDR = 0x007F8000, | ||
404 | + FSL_IMX7_TCML_SIZE = (32 * KiB), | ||
405 | + | ||
406 | + FSL_IMX7_OCRAM_S_ADDR = 0x00180000, | ||
407 | + FSL_IMX7_OCRAM_S_SIZE = (32 * KiB), | ||
408 | + | ||
409 | + FSL_IMX7_CAAM_MEM_ADDR = 0x00100000, | ||
410 | + FSL_IMX7_CAAM_MEM_SIZE = (32 * KiB), | ||
411 | + | ||
412 | + FSL_IMX7_ROM_ADDR = 0x00000000, | ||
413 | + FSL_IMX7_ROM_SIZE = (96 * KiB), | ||
414 | }; | ||
415 | |||
416 | enum FslIMX7IRQs { | ||
417 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c | ||
418 | index XXXXXXX..XXXXXXX 100644 | ||
419 | --- a/hw/arm/fsl-imx7.c | ||
420 | +++ b/hw/arm/fsl-imx7.c | ||
421 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
422 | char name[NAME_SIZE]; | ||
423 | int i; | ||
424 | |||
425 | + /* | ||
426 | + * CPUs | ||
427 | + */ | ||
428 | for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) { | ||
429 | snprintf(name, NAME_SIZE, "cpu%d", i); | ||
430 | object_initialize_child(obj, name, &s->cpu[i], | ||
431 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
432 | TYPE_A15MPCORE_PRIV); | ||
433 | |||
434 | /* | ||
435 | - * GPIOs 1 to 7 | ||
436 | + * GPIOs | ||
437 | */ | ||
438 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { | ||
439 | snprintf(name, NAME_SIZE, "gpio%d", i); | ||
440 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
441 | } | ||
442 | |||
443 | /* | ||
444 | - * GPT1, 2, 3, 4 | ||
445 | + * GPTs | ||
446 | */ | ||
447 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { | ||
448 | snprintf(name, NAME_SIZE, "gpt%d", i); | ||
449 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
450 | */ | ||
451 | object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); | ||
452 | |||
453 | + /* | ||
454 | + * ECSPIs | ||
455 | + */ | ||
456 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { | ||
457 | snprintf(name, NAME_SIZE, "spi%d", i + 1); | ||
458 | object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); | ||
459 | } | ||
460 | |||
461 | - | ||
462 | + /* | ||
463 | + * I2Cs | ||
464 | + */ | ||
465 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { | ||
466 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); | ||
467 | object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); | ||
468 | } | ||
469 | |||
470 | /* | ||
471 | - * UART | ||
472 | + * UARTs | ||
473 | */ | ||
474 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { | ||
475 | snprintf(name, NAME_SIZE, "uart%d", i); | ||
476 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
477 | } | ||
478 | |||
479 | /* | ||
480 | - * Ethernet | ||
481 | + * Ethernets | ||
482 | */ | ||
483 | for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { | ||
484 | snprintf(name, NAME_SIZE, "eth%d", i); | ||
485 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
486 | } | ||
487 | |||
488 | /* | ||
489 | - * SDHCI | ||
490 | + * SDHCIs | ||
491 | */ | ||
492 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { | ||
493 | snprintf(name, NAME_SIZE, "usdhc%d", i); | ||
494 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
495 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
496 | |||
497 | /* | ||
498 | - * Watchdog | ||
499 | + * Watchdogs | ||
500 | */ | ||
501 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { | ||
502 | snprintf(name, NAME_SIZE, "wdt%d", i); | ||
503 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
504 | */ | ||
505 | object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); | ||
506 | |||
507 | + /* | ||
508 | + * PCIE | ||
509 | + */ | ||
510 | object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); | ||
511 | |||
512 | + /* | ||
513 | + * USBs | ||
514 | + */ | ||
515 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { | ||
516 | snprintf(name, NAME_SIZE, "usb%d", i); | ||
517 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); | ||
518 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
80 | return; | 519 | return; |
81 | } | 520 | } |
82 | 521 | ||
83 | + /* Enabling and disabling kvm-no-adjvtime should always work. */ | 522 | + /* |
84 | assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime"); | 523 | + * CPUs |
85 | + assert_set_feature(qts, "host", "kvm-no-adjvtime", true); | 524 | + */ |
86 | + assert_set_feature(qts, "host", "kvm-no-adjvtime", false); | 525 | for (i = 0; i < smp_cpus; i++) { |
87 | 526 | o = OBJECT(&s->cpu[i]); | |
88 | if (g_str_equal(qtest_get_arch(), "aarch64")) { | 527 | |
89 | bool kvm_supports_sve; | 528 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) |
90 | @@ -XXX,XX +XXX,XX @@ static void test_query_cpu_model_expansion_kvm(const void *data) | 529 | * A7MPCORE DAP |
91 | char *error; | 530 | */ |
92 | 531 | create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, | |
93 | assert_has_feature_enabled(qts, "host", "aarch64"); | 532 | - 0x100000); |
94 | + | 533 | + FSL_IMX7_A7MPCORE_DAP_SIZE); |
95 | + /* Enabling and disabling pmu should always work. */ | 534 | |
96 | assert_has_feature_enabled(qts, "host", "pmu"); | 535 | /* |
97 | + assert_set_feature(qts, "host", "pmu", false); | 536 | - * GPT1, 2, 3, 4 |
98 | + assert_set_feature(qts, "host", "pmu", true); | 537 | + * GPTs |
99 | 538 | */ | |
100 | assert_error(qts, "cortex-a15", | 539 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { |
101 | "We cannot guarantee the CPU type 'cortex-a15' works " | 540 | static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = { |
541 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
542 | FSL_IMX7_GPTn_IRQ[i])); | ||
543 | } | ||
544 | |||
545 | + /* | ||
546 | + * GPIOs | ||
547 | + */ | ||
548 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { | ||
549 | static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = { | ||
550 | FSL_IMX7_GPIO1_ADDR, | ||
551 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
552 | /* | ||
553 | * IOMUXC and IOMUXC_LPSR | ||
554 | */ | ||
555 | - for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) { | ||
556 | - static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = { | ||
557 | - FSL_IMX7_IOMUXC_ADDR, | ||
558 | - FSL_IMX7_IOMUXC_LPSR_ADDR, | ||
559 | - }; | ||
560 | - | ||
561 | - snprintf(name, NAME_SIZE, "iomuxc%d", i); | ||
562 | - create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i], | ||
563 | - FSL_IMX7_IOMUXCn_SIZE); | ||
564 | - } | ||
565 | + create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR, | ||
566 | + FSL_IMX7_IOMUXC_SIZE); | ||
567 | + create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR, | ||
568 | + FSL_IMX7_IOMUXC_LPSR_SIZE); | ||
569 | |||
570 | /* | ||
571 | * CCM | ||
572 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
573 | sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); | ||
574 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); | ||
575 | |||
576 | - /* Initialize all ECSPI */ | ||
577 | + /* | ||
578 | + * ECSPIs | ||
579 | + */ | ||
580 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { | ||
581 | static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = { | ||
582 | FSL_IMX7_ECSPI1_ADDR, | ||
583 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
584 | FSL_IMX7_SPIn_IRQ[i])); | ||
585 | } | ||
586 | |||
587 | + /* | ||
588 | + * I2Cs | ||
589 | + */ | ||
590 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { | ||
591 | static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = { | ||
592 | FSL_IMX7_I2C1_ADDR, | ||
593 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
594 | } | ||
595 | |||
596 | /* | ||
597 | - * UART | ||
598 | + * UARTs | ||
599 | */ | ||
600 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { | ||
601 | static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = { | ||
602 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
603 | } | ||
604 | |||
605 | /* | ||
606 | - * Ethernet | ||
607 | + * Ethernets | ||
608 | * | ||
609 | * We must use two loops since phy_connected affects the other interface | ||
610 | * and we have to set all properties before calling sysbus_realize(). | ||
611 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
612 | } | ||
613 | |||
614 | /* | ||
615 | - * USDHC | ||
616 | + * USDHCs | ||
617 | */ | ||
618 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { | ||
619 | static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = { | ||
620 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
621 | * SNVS | ||
622 | */ | ||
623 | sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); | ||
624 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR); | ||
625 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR); | ||
626 | |||
627 | /* | ||
628 | * SRC | ||
629 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
630 | create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); | ||
631 | |||
632 | /* | ||
633 | - * Watchdog | ||
634 | + * Watchdogs | ||
635 | */ | ||
636 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { | ||
637 | static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = { | ||
638 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
639 | create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE); | ||
640 | |||
641 | /* | ||
642 | - * PWM | ||
643 | + * PWMs | ||
644 | */ | ||
645 | - create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE); | ||
646 | - create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE); | ||
647 | - create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE); | ||
648 | - create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE); | ||
649 | + for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) { | ||
650 | + static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = { | ||
651 | + FSL_IMX7_PWM1_ADDR, | ||
652 | + FSL_IMX7_PWM2_ADDR, | ||
653 | + FSL_IMX7_PWM3_ADDR, | ||
654 | + FSL_IMX7_PWM4_ADDR, | ||
655 | + }; | ||
656 | + | ||
657 | + snprintf(name, NAME_SIZE, "pwm%d", i); | ||
658 | + create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i], | ||
659 | + FSL_IMX7_PWMn_SIZE); | ||
660 | + } | ||
661 | |||
662 | /* | ||
663 | - * CAN | ||
664 | + * CANs | ||
665 | */ | ||
666 | - create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE); | ||
667 | - create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE); | ||
668 | + for (i = 0; i < FSL_IMX7_NUM_CANS; i++) { | ||
669 | + static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = { | ||
670 | + FSL_IMX7_CAN1_ADDR, | ||
671 | + FSL_IMX7_CAN2_ADDR, | ||
672 | + }; | ||
673 | + | ||
674 | + snprintf(name, NAME_SIZE, "can%d", i); | ||
675 | + create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i], | ||
676 | + FSL_IMX7_CANn_SIZE); | ||
677 | + } | ||
678 | |||
679 | /* | ||
680 | - * SAI (Audio SSI (Synchronous Serial Interface)) | ||
681 | + * SAIs (Audio SSI (Synchronous Serial Interface)) | ||
682 | */ | ||
683 | - create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE); | ||
684 | - create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE); | ||
685 | - create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE); | ||
686 | + for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) { | ||
687 | + static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = { | ||
688 | + FSL_IMX7_SAI1_ADDR, | ||
689 | + FSL_IMX7_SAI2_ADDR, | ||
690 | + FSL_IMX7_SAI3_ADDR, | ||
691 | + }; | ||
692 | + | ||
693 | + snprintf(name, NAME_SIZE, "sai%d", i); | ||
694 | + create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i], | ||
695 | + FSL_IMX7_SAIn_SIZE); | ||
696 | + } | ||
697 | |||
698 | /* | ||
699 | * OCOTP | ||
700 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
701 | create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR, | ||
702 | FSL_IMX7_OCOTP_SIZE); | ||
703 | |||
704 | + /* | ||
705 | + * GPR | ||
706 | + */ | ||
707 | sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); | ||
708 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR); | ||
709 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR); | ||
710 | |||
711 | + /* | ||
712 | + * PCIE | ||
713 | + */ | ||
714 | sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); | ||
715 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); | ||
716 | |||
717 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
718 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); | ||
719 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); | ||
720 | |||
721 | - | ||
722 | + /* | ||
723 | + * USBs | ||
724 | + */ | ||
725 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { | ||
726 | static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = { | ||
727 | FSL_IMX7_USBMISC1_ADDR, | ||
728 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
729 | */ | ||
730 | create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, | ||
731 | FSL_IMX7_PCIE_PHY_SIZE); | ||
732 | + | ||
733 | } | ||
734 | |||
735 | static Property fsl_imx7_properties[] = { | ||
102 | -- | 736 | -- |
103 | 2.20.1 | 737 | 2.34.1 |
104 | |||
105 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Use self-explicit definitions instead of magic values. | 3 | * Add TZASC as unimplemented device. |
4 | - Allow bare metal application to access this (unimplemented) device | ||
5 | * Add CSU as unimplemented device. | ||
6 | - Allow bare metal application to access this (unimplemented) device | ||
7 | * Add various memory segments | ||
8 | - OCRAM | ||
9 | - OCRAM EPDC | ||
10 | - OCRAM PXP | ||
11 | - OCRAM S | ||
12 | - ROM | ||
13 | - CAAM | ||
4 | 14 | ||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 15 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
6 | Message-id: 20200617072539.32686-4-f4bug@amsat.org | 16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 19 | --- |
10 | hw/i2c/versatile_i2c.c | 7 +++++-- | 20 | include/hw/arm/fsl-imx7.h | 7 +++++ |
11 | 1 file changed, 5 insertions(+), 2 deletions(-) | 21 | hw/arm/fsl-imx7.c | 63 +++++++++++++++++++++++++++++++++++++++ |
22 | 2 files changed, 70 insertions(+) | ||
12 | 23 | ||
13 | diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c | 24 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h |
14 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/i2c/versatile_i2c.c | 26 | --- a/include/hw/arm/fsl-imx7.h |
16 | +++ b/hw/i2c/versatile_i2c.c | 27 | +++ b/include/hw/arm/fsl-imx7.h |
17 | @@ -XXX,XX +XXX,XX @@ REG32(CONTROL_GET, 0) | 28 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
18 | REG32(CONTROL_SET, 0) | 29 | IMX7GPRState gpr; |
19 | REG32(CONTROL_CLR, 4) | 30 | ChipideaState usb[FSL_IMX7_NUM_USBS]; |
20 | 31 | DesignwarePCIEHost pcie; | |
21 | +#define SCL BIT(0) | 32 | + MemoryRegion rom; |
22 | +#define SDA BIT(1) | 33 | + MemoryRegion caam; |
34 | + MemoryRegion ocram; | ||
35 | + MemoryRegion ocram_epdc; | ||
36 | + MemoryRegion ocram_pxp; | ||
37 | + MemoryRegion ocram_s; | ||
23 | + | 38 | + |
24 | static uint64_t versatile_i2c_read(void *opaque, hwaddr offset, | 39 | uint32_t phy_num[FSL_IMX7_NUM_ETHS]; |
25 | unsigned size) | 40 | bool phy_connected[FSL_IMX7_NUM_ETHS]; |
26 | { | 41 | }; |
27 | @@ -XXX,XX +XXX,XX @@ static void versatile_i2c_write(void *opaque, hwaddr offset, | 42 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c |
28 | qemu_log_mask(LOG_GUEST_ERROR, | 43 | index XXXXXXX..XXXXXXX 100644 |
29 | "%s: Bad offset 0x%x\n", __func__, (int)offset); | 44 | --- a/hw/arm/fsl-imx7.c |
30 | } | 45 | +++ b/hw/arm/fsl-imx7.c |
31 | - bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0); | 46 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) |
32 | - s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0); | 47 | create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, |
33 | + bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & SCL) != 0); | 48 | FSL_IMX7_PCIE_PHY_SIZE); |
34 | + s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0); | 49 | |
50 | + /* | ||
51 | + * CSU | ||
52 | + */ | ||
53 | + create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR, | ||
54 | + FSL_IMX7_CSU_SIZE); | ||
55 | + | ||
56 | + /* | ||
57 | + * TZASC | ||
58 | + */ | ||
59 | + create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR, | ||
60 | + FSL_IMX7_TZASC_SIZE); | ||
61 | + | ||
62 | + /* | ||
63 | + * OCRAM memory | ||
64 | + */ | ||
65 | + memory_region_init_ram(&s->ocram, NULL, "imx7.ocram", | ||
66 | + FSL_IMX7_OCRAM_MEM_SIZE, | ||
67 | + &error_abort); | ||
68 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR, | ||
69 | + &s->ocram); | ||
70 | + | ||
71 | + /* | ||
72 | + * OCRAM EPDC memory | ||
73 | + */ | ||
74 | + memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc", | ||
75 | + FSL_IMX7_OCRAM_EPDC_SIZE, | ||
76 | + &error_abort); | ||
77 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR, | ||
78 | + &s->ocram_epdc); | ||
79 | + | ||
80 | + /* | ||
81 | + * OCRAM PXP memory | ||
82 | + */ | ||
83 | + memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp", | ||
84 | + FSL_IMX7_OCRAM_PXP_SIZE, | ||
85 | + &error_abort); | ||
86 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR, | ||
87 | + &s->ocram_pxp); | ||
88 | + | ||
89 | + /* | ||
90 | + * OCRAM_S memory | ||
91 | + */ | ||
92 | + memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s", | ||
93 | + FSL_IMX7_OCRAM_S_SIZE, | ||
94 | + &error_abort); | ||
95 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR, | ||
96 | + &s->ocram_s); | ||
97 | + | ||
98 | + /* | ||
99 | + * ROM memory | ||
100 | + */ | ||
101 | + memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom", | ||
102 | + FSL_IMX7_ROM_SIZE, &error_abort); | ||
103 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR, | ||
104 | + &s->rom); | ||
105 | + | ||
106 | + /* | ||
107 | + * CAAM memory | ||
108 | + */ | ||
109 | + memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam", | ||
110 | + FSL_IMX7_CAAM_MEM_SIZE, &error_abort); | ||
111 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR, | ||
112 | + &s->caam); | ||
35 | } | 113 | } |
36 | 114 | ||
37 | static const MemoryRegionOps versatile_i2c_ops = { | 115 | static Property fsl_imx7_properties[] = { |
38 | -- | 116 | -- |
39 | 2.20.1 | 117 | 2.34.1 |
40 | 118 | ||
41 | 119 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | 'ARM SBCon two-wire serial bus interface' is the official | 3 | The SRC device is normally used to start the secondary CPU. |
4 | name describing the pair of registers used to bitbanging | 4 | |
5 | I2C in the Versatile boards. | 5 | When running Linux directly, QEMU is emulating a PSCI interface that UBOOT |
6 | 6 | is installing at boot time and therefore the fact that the SRC device is | |
7 | Make the private VersatileI2CState structure as public | 7 | unimplemented is hidden as Qemu respond directly to PSCI requets without |
8 | ArmSbconI2CState. | 8 | using the SRC device. |
9 | Add the TYPE_ARM_SBCON_I2C, alias to our current | 9 | |
10 | TYPE_VERSATILE_I2C model. | 10 | But if you try to run a more bare metal application (maybe uboot itself), |
11 | Rename the memory region description as 'arm_sbcon_i2c'. | 11 | then it is not possible to start the secondary CPU as the SRC is an |
12 | 12 | unimplemented device. | |
13 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 13 | |
14 | Message-id: 20200617072539.32686-5-f4bug@amsat.org | 14 | This patch adds the ability to start the secondary CPU through the SRC |
15 | device so that you can use this feature in bare metal applications. | ||
16 | |||
17 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 21 | --- |
18 | include/hw/i2c/arm_sbcon_i2c.h | 35 ++++++++++++++++++++++++++++++++++ | 22 | include/hw/arm/fsl-imx7.h | 3 +- |
19 | hw/i2c/versatile_i2c.c | 17 +++++------------ | 23 | include/hw/misc/imx7_src.h | 66 +++++++++ |
20 | MAINTAINERS | 1 + | 24 | hw/arm/fsl-imx7.c | 8 +- |
21 | 3 files changed, 41 insertions(+), 12 deletions(-) | 25 | hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++++++ |
22 | create mode 100644 include/hw/i2c/arm_sbcon_i2c.h | 26 | hw/misc/meson.build | 1 + |
23 | 27 | hw/misc/trace-events | 4 + | |
24 | diff --git a/include/hw/i2c/arm_sbcon_i2c.h b/include/hw/i2c/arm_sbcon_i2c.h | 28 | 6 files changed, 356 insertions(+), 2 deletions(-) |
29 | create mode 100644 include/hw/misc/imx7_src.h | ||
30 | create mode 100644 hw/misc/imx7_src.c | ||
31 | |||
32 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/include/hw/arm/fsl-imx7.h | ||
35 | +++ b/include/hw/arm/fsl-imx7.h | ||
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | #include "hw/misc/imx7_ccm.h" | ||
38 | #include "hw/misc/imx7_snvs.h" | ||
39 | #include "hw/misc/imx7_gpr.h" | ||
40 | +#include "hw/misc/imx7_src.h" | ||
41 | #include "hw/watchdog/wdt_imx2.h" | ||
42 | #include "hw/gpio/imx_gpio.h" | ||
43 | #include "hw/char/imx_serial.h" | ||
44 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { | ||
45 | IMX7CCMState ccm; | ||
46 | IMX7AnalogState analog; | ||
47 | IMX7SNVSState snvs; | ||
48 | + IMX7SRCState src; | ||
49 | IMXGPCv2State gpcv2; | ||
50 | IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; | ||
51 | IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; | ||
52 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap { | ||
53 | FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
54 | |||
55 | FSL_IMX7_SRC_ADDR = 0x30390000, | ||
56 | - FSL_IMX7_SRC_SIZE = (4 * KiB), | ||
57 | |||
58 | FSL_IMX7_CCM_ADDR = 0x30380000, | ||
59 | |||
60 | diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h | ||
25 | new file mode 100644 | 61 | new file mode 100644 |
26 | index XXXXXXX..XXXXXXX | 62 | index XXXXXXX..XXXXXXX |
27 | --- /dev/null | 63 | --- /dev/null |
28 | +++ b/include/hw/i2c/arm_sbcon_i2c.h | 64 | +++ b/include/hw/misc/imx7_src.h |
29 | @@ -XXX,XX +XXX,XX @@ | 65 | @@ -XXX,XX +XXX,XX @@ |
30 | +/* | 66 | +/* |
31 | + * ARM SBCon two-wire serial bus interface (I2C bitbang) | 67 | + * IMX7 System Reset Controller |
32 | + * a.k.a. | ||
33 | + * ARM Versatile I2C controller | ||
34 | + * | 68 | + * |
35 | + * Copyright (c) 2006-2007 CodeSourcery. | 69 | + * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net> |
36 | + * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com> | ||
37 | + * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
38 | + * | 70 | + * |
39 | + * SPDX-License-Identifier: GPL-2.0-or-later | 71 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
72 | + * See the COPYING file in the top-level directory. | ||
40 | + */ | 73 | + */ |
41 | +#ifndef HW_I2C_ARM_SBCON_H | 74 | + |
42 | +#define HW_I2C_ARM_SBCON_H | 75 | +#ifndef IMX7_SRC_H |
76 | +#define IMX7_SRC_H | ||
43 | + | 77 | + |
44 | +#include "hw/sysbus.h" | 78 | +#include "hw/sysbus.h" |
45 | +#include "hw/i2c/bitbang_i2c.h" | 79 | +#include "qemu/bitops.h" |
46 | + | 80 | +#include "qom/object.h" |
47 | +#define TYPE_VERSATILE_I2C "versatile_i2c" | 81 | + |
48 | +#define TYPE_ARM_SBCON_I2C TYPE_VERSATILE_I2C | 82 | +#define SRC_SCR 0 |
49 | + | 83 | +#define SRC_A7RCR0 1 |
50 | +#define ARM_SBCON_I2C(obj) \ | 84 | +#define SRC_A7RCR1 2 |
51 | + OBJECT_CHECK(ArmSbconI2CState, (obj), TYPE_ARM_SBCON_I2C) | 85 | +#define SRC_M4RCR 3 |
52 | + | 86 | +#define SRC_ERCR 5 |
53 | +typedef struct ArmSbconI2CState { | 87 | +#define SRC_HSICPHY_RCR 7 |
54 | + /*< private >*/ | 88 | +#define SRC_USBOPHY1_RCR 8 |
89 | +#define SRC_USBOPHY2_RCR 9 | ||
90 | +#define SRC_MPIPHY_RCR 10 | ||
91 | +#define SRC_PCIEPHY_RCR 11 | ||
92 | +#define SRC_SBMR1 22 | ||
93 | +#define SRC_SRSR 23 | ||
94 | +#define SRC_SISR 26 | ||
95 | +#define SRC_SIMR 27 | ||
96 | +#define SRC_SBMR2 28 | ||
97 | +#define SRC_GPR1 29 | ||
98 | +#define SRC_GPR2 30 | ||
99 | +#define SRC_GPR3 31 | ||
100 | +#define SRC_GPR4 32 | ||
101 | +#define SRC_GPR5 33 | ||
102 | +#define SRC_GPR6 34 | ||
103 | +#define SRC_GPR7 35 | ||
104 | +#define SRC_GPR8 36 | ||
105 | +#define SRC_GPR9 37 | ||
106 | +#define SRC_GPR10 38 | ||
107 | +#define SRC_MAX 39 | ||
108 | + | ||
109 | +/* SRC_A7SCR1 */ | ||
110 | +#define R_CORE1_ENABLE_SHIFT 1 | ||
111 | +#define R_CORE1_ENABLE_LENGTH 1 | ||
112 | +/* SRC_A7SCR0 */ | ||
113 | +#define R_CORE1_RST_SHIFT 5 | ||
114 | +#define R_CORE1_RST_LENGTH 1 | ||
115 | +#define R_CORE0_RST_SHIFT 4 | ||
116 | +#define R_CORE0_RST_LENGTH 1 | ||
117 | + | ||
118 | +#define TYPE_IMX7_SRC "imx7.src" | ||
119 | +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC) | ||
120 | + | ||
121 | +struct IMX7SRCState { | ||
122 | + /* <private> */ | ||
55 | + SysBusDevice parent_obj; | 123 | + SysBusDevice parent_obj; |
56 | + /*< public >*/ | 124 | + |
57 | + | 125 | + /* <public> */ |
58 | + MemoryRegion iomem; | 126 | + MemoryRegion iomem; |
59 | + bitbang_i2c_interface bitbang; | 127 | + |
60 | + int out; | 128 | + uint32_t regs[SRC_MAX]; |
61 | + int in; | 129 | +}; |
62 | +} ArmSbconI2CState; | 130 | + |
63 | + | 131 | +#endif /* IMX7_SRC_H */ |
64 | +#endif /* HW_I2C_ARM_SBCON_H */ | 132 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c |
65 | diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | 133 | index XXXXXXX..XXXXXXX 100644 |
67 | --- a/hw/i2c/versatile_i2c.c | 134 | --- a/hw/arm/fsl-imx7.c |
68 | +++ b/hw/i2c/versatile_i2c.c | 135 | +++ b/hw/arm/fsl-imx7.c |
136 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
137 | */ | ||
138 | object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); | ||
139 | |||
140 | + /* | ||
141 | + * SRC | ||
142 | + */ | ||
143 | + object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC); | ||
144 | + | ||
145 | /* | ||
146 | * ECSPIs | ||
147 | */ | ||
148 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
149 | /* | ||
150 | * SRC | ||
151 | */ | ||
152 | - create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); | ||
153 | + sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); | ||
154 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR); | ||
155 | |||
156 | /* | ||
157 | * Watchdogs | ||
158 | diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c | ||
159 | new file mode 100644 | ||
160 | index XXXXXXX..XXXXXXX | ||
161 | --- /dev/null | ||
162 | +++ b/hw/misc/imx7_src.c | ||
69 | @@ -XXX,XX +XXX,XX @@ | 163 | @@ -XXX,XX +XXX,XX @@ |
70 | /* | 164 | +/* |
71 | - * ARM Versatile I2C controller | 165 | + * IMX7 System Reset Controller |
72 | + * ARM SBCon two-wire serial bus interface (I2C bitbang) | 166 | + * |
73 | + * a.k.a. ARM Versatile I2C controller | 167 | + * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net> |
74 | * | 168 | + * |
75 | * Copyright (c) 2006-2007 CodeSourcery. | 169 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
76 | * Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com> | 170 | + * See the COPYING file in the top-level directory. |
77 | @@ -XXX,XX +XXX,XX @@ | 171 | + * |
78 | */ | 172 | + */ |
79 | 173 | + | |
80 | #include "qemu/osdep.h" | 174 | +#include "qemu/osdep.h" |
81 | -#include "hw/sysbus.h" | 175 | +#include "hw/misc/imx7_src.h" |
82 | -#include "hw/i2c/bitbang_i2c.h" | 176 | +#include "migration/vmstate.h" |
83 | +#include "hw/i2c/arm_sbcon_i2c.h" | 177 | +#include "qemu/bitops.h" |
84 | #include "hw/registerfields.h" | 178 | +#include "qemu/log.h" |
85 | #include "qemu/log.h" | 179 | +#include "qemu/main-loop.h" |
86 | #include "qemu/module.h" | 180 | +#include "qemu/module.h" |
87 | 181 | +#include "target/arm/arm-powerctl.h" | |
88 | -#define TYPE_VERSATILE_I2C "versatile_i2c" | 182 | +#include "hw/core/cpu.h" |
89 | #define VERSATILE_I2C(obj) \ | 183 | +#include "hw/registerfields.h" |
90 | OBJECT_CHECK(VersatileI2CState, (obj), TYPE_VERSATILE_I2C) | 184 | + |
91 | 185 | +#include "trace.h" | |
92 | -typedef struct VersatileI2CState { | 186 | + |
93 | - SysBusDevice parent_obj; | 187 | +static const char *imx7_src_reg_name(uint32_t reg) |
94 | +typedef ArmSbconI2CState VersatileI2CState; | 188 | +{ |
95 | 189 | + static char unknown[20]; | |
96 | - MemoryRegion iomem; | 190 | + |
97 | - bitbang_i2c_interface bitbang; | 191 | + switch (reg) { |
98 | - int out; | 192 | + case SRC_SCR: |
99 | - int in; | 193 | + return "SRC_SCR"; |
100 | -} VersatileI2CState; | 194 | + case SRC_A7RCR0: |
101 | 195 | + return "SRC_A7RCR0"; | |
102 | REG32(CONTROL_GET, 0) | 196 | + case SRC_A7RCR1: |
103 | REG32(CONTROL_SET, 0) | 197 | + return "SRC_A7RCR1"; |
104 | @@ -XXX,XX +XXX,XX @@ static void versatile_i2c_init(Object *obj) | 198 | + case SRC_M4RCR: |
105 | bus = i2c_init_bus(dev, "i2c"); | 199 | + return "SRC_M4RCR"; |
106 | bitbang_i2c_init(&s->bitbang, bus); | 200 | + case SRC_ERCR: |
107 | memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s, | 201 | + return "SRC_ERCR"; |
108 | - "versatile_i2c", 0x1000); | 202 | + case SRC_HSICPHY_RCR: |
109 | + "arm_sbcon_i2c", 0x1000); | 203 | + return "SRC_HSICPHY_RCR"; |
110 | sysbus_init_mmio(sbd, &s->iomem); | 204 | + case SRC_USBOPHY1_RCR: |
111 | } | 205 | + return "SRC_USBOPHY1_RCR"; |
112 | 206 | + case SRC_USBOPHY2_RCR: | |
113 | diff --git a/MAINTAINERS b/MAINTAINERS | 207 | + return "SRC_USBOPHY2_RCR"; |
208 | + case SRC_PCIEPHY_RCR: | ||
209 | + return "SRC_PCIEPHY_RCR"; | ||
210 | + case SRC_SBMR1: | ||
211 | + return "SRC_SBMR1"; | ||
212 | + case SRC_SRSR: | ||
213 | + return "SRC_SRSR"; | ||
214 | + case SRC_SISR: | ||
215 | + return "SRC_SISR"; | ||
216 | + case SRC_SIMR: | ||
217 | + return "SRC_SIMR"; | ||
218 | + case SRC_SBMR2: | ||
219 | + return "SRC_SBMR2"; | ||
220 | + case SRC_GPR1: | ||
221 | + return "SRC_GPR1"; | ||
222 | + case SRC_GPR2: | ||
223 | + return "SRC_GPR2"; | ||
224 | + case SRC_GPR3: | ||
225 | + return "SRC_GPR3"; | ||
226 | + case SRC_GPR4: | ||
227 | + return "SRC_GPR4"; | ||
228 | + case SRC_GPR5: | ||
229 | + return "SRC_GPR5"; | ||
230 | + case SRC_GPR6: | ||
231 | + return "SRC_GPR6"; | ||
232 | + case SRC_GPR7: | ||
233 | + return "SRC_GPR7"; | ||
234 | + case SRC_GPR8: | ||
235 | + return "SRC_GPR8"; | ||
236 | + case SRC_GPR9: | ||
237 | + return "SRC_GPR9"; | ||
238 | + case SRC_GPR10: | ||
239 | + return "SRC_GPR10"; | ||
240 | + default: | ||
241 | + sprintf(unknown, "%u ?", reg); | ||
242 | + return unknown; | ||
243 | + } | ||
244 | +} | ||
245 | + | ||
246 | +static const VMStateDescription vmstate_imx7_src = { | ||
247 | + .name = TYPE_IMX7_SRC, | ||
248 | + .version_id = 1, | ||
249 | + .minimum_version_id = 1, | ||
250 | + .fields = (VMStateField[]) { | ||
251 | + VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX), | ||
252 | + VMSTATE_END_OF_LIST() | ||
253 | + }, | ||
254 | +}; | ||
255 | + | ||
256 | +static void imx7_src_reset(DeviceState *dev) | ||
257 | +{ | ||
258 | + IMX7SRCState *s = IMX7_SRC(dev); | ||
259 | + | ||
260 | + memset(s->regs, 0, sizeof(s->regs)); | ||
261 | + | ||
262 | + /* Set reset values */ | ||
263 | + s->regs[SRC_SCR] = 0xA0; | ||
264 | + s->regs[SRC_SRSR] = 0x1; | ||
265 | + s->regs[SRC_SIMR] = 0x1F; | ||
266 | +} | ||
267 | + | ||
268 | +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size) | ||
269 | +{ | ||
270 | + uint32_t value = 0; | ||
271 | + IMX7SRCState *s = (IMX7SRCState *)opaque; | ||
272 | + uint32_t index = offset >> 2; | ||
273 | + | ||
274 | + if (index < SRC_MAX) { | ||
275 | + value = s->regs[index]; | ||
276 | + } else { | ||
277 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" | ||
278 | + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); | ||
279 | + } | ||
280 | + | ||
281 | + trace_imx7_src_read(imx7_src_reg_name(index), value); | ||
282 | + | ||
283 | + return value; | ||
284 | +} | ||
285 | + | ||
286 | + | ||
287 | +/* | ||
288 | + * The reset is asynchronous so we need to defer clearing the reset | ||
289 | + * bit until the work is completed. | ||
290 | + */ | ||
291 | + | ||
292 | +struct SRCSCRResetInfo { | ||
293 | + IMX7SRCState *s; | ||
294 | + uint32_t reset_bit; | ||
295 | +}; | ||
296 | + | ||
297 | +static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data) | ||
298 | +{ | ||
299 | + struct SRCSCRResetInfo *ri = data.host_ptr; | ||
300 | + IMX7SRCState *s = ri->s; | ||
301 | + | ||
302 | + assert(qemu_mutex_iothread_locked()); | ||
303 | + | ||
304 | + s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0); | ||
305 | + | ||
306 | + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); | ||
307 | + | ||
308 | + g_free(ri); | ||
309 | +} | ||
310 | + | ||
311 | +static void imx7_defer_clear_reset_bit(uint32_t cpuid, | ||
312 | + IMX7SRCState *s, | ||
313 | + uint32_t reset_shift) | ||
314 | +{ | ||
315 | + struct SRCSCRResetInfo *ri; | ||
316 | + CPUState *cpu = arm_get_cpu_by_id(cpuid); | ||
317 | + | ||
318 | + if (!cpu) { | ||
319 | + return; | ||
320 | + } | ||
321 | + | ||
322 | + ri = g_new(struct SRCSCRResetInfo, 1); | ||
323 | + ri->s = s; | ||
324 | + ri->reset_bit = reset_shift; | ||
325 | + | ||
326 | + async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri)); | ||
327 | +} | ||
328 | + | ||
329 | + | ||
330 | +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value, | ||
331 | + unsigned size) | ||
332 | +{ | ||
333 | + IMX7SRCState *s = (IMX7SRCState *)opaque; | ||
334 | + uint32_t index = offset >> 2; | ||
335 | + long unsigned int change_mask; | ||
336 | + uint32_t current_value = value; | ||
337 | + | ||
338 | + if (index >= SRC_MAX) { | ||
339 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" | ||
340 | + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); | ||
341 | + return; | ||
342 | + } | ||
343 | + | ||
344 | + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); | ||
345 | + | ||
346 | + change_mask = s->regs[index] ^ (uint32_t)current_value; | ||
347 | + | ||
348 | + switch (index) { | ||
349 | + case SRC_A7RCR0: | ||
350 | + if (FIELD_EX32(change_mask, CORE0, RST)) { | ||
351 | + arm_reset_cpu(0); | ||
352 | + imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT); | ||
353 | + } | ||
354 | + if (FIELD_EX32(change_mask, CORE1, RST)) { | ||
355 | + arm_reset_cpu(1); | ||
356 | + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); | ||
357 | + } | ||
358 | + s->regs[index] = current_value; | ||
359 | + break; | ||
360 | + case SRC_A7RCR1: | ||
361 | + /* | ||
362 | + * On real hardware when the system reset controller starts a | ||
363 | + * secondary CPU it runs through some boot ROM code which reads | ||
364 | + * the SRC_GPRX registers controlling the start address and branches | ||
365 | + * to it. | ||
366 | + * Here we are taking a short cut and branching directly to the | ||
367 | + * requested address (we don't want to run the boot ROM code inside | ||
368 | + * QEMU) | ||
369 | + */ | ||
370 | + if (FIELD_EX32(change_mask, CORE1, ENABLE)) { | ||
371 | + if (FIELD_EX32(current_value, CORE1, ENABLE)) { | ||
372 | + /* CORE 1 is brought up */ | ||
373 | + arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4], | ||
374 | + 3, false); | ||
375 | + } else { | ||
376 | + /* CORE 1 is shut down */ | ||
377 | + arm_set_cpu_off(1); | ||
378 | + } | ||
379 | + /* We clear the reset bits as the processor changed state */ | ||
380 | + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); | ||
381 | + clear_bit(R_CORE1_RST_SHIFT, &change_mask); | ||
382 | + } | ||
383 | + s->regs[index] = current_value; | ||
384 | + break; | ||
385 | + default: | ||
386 | + s->regs[index] = current_value; | ||
387 | + break; | ||
388 | + } | ||
389 | +} | ||
390 | + | ||
391 | +static const struct MemoryRegionOps imx7_src_ops = { | ||
392 | + .read = imx7_src_read, | ||
393 | + .write = imx7_src_write, | ||
394 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
395 | + .valid = { | ||
396 | + /* | ||
397 | + * Our device would not work correctly if the guest was doing | ||
398 | + * unaligned access. This might not be a limitation on the real | ||
399 | + * device but in practice there is no reason for a guest to access | ||
400 | + * this device unaligned. | ||
401 | + */ | ||
402 | + .min_access_size = 4, | ||
403 | + .max_access_size = 4, | ||
404 | + .unaligned = false, | ||
405 | + }, | ||
406 | +}; | ||
407 | + | ||
408 | +static void imx7_src_realize(DeviceState *dev, Error **errp) | ||
409 | +{ | ||
410 | + IMX7SRCState *s = IMX7_SRC(dev); | ||
411 | + | ||
412 | + memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s, | ||
413 | + TYPE_IMX7_SRC, 0x1000); | ||
414 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); | ||
415 | +} | ||
416 | + | ||
417 | +static void imx7_src_class_init(ObjectClass *klass, void *data) | ||
418 | +{ | ||
419 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
420 | + | ||
421 | + dc->realize = imx7_src_realize; | ||
422 | + dc->reset = imx7_src_reset; | ||
423 | + dc->vmsd = &vmstate_imx7_src; | ||
424 | + dc->desc = "i.MX6 System Reset Controller"; | ||
425 | +} | ||
426 | + | ||
427 | +static const TypeInfo imx7_src_info = { | ||
428 | + .name = TYPE_IMX7_SRC, | ||
429 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
430 | + .instance_size = sizeof(IMX7SRCState), | ||
431 | + .class_init = imx7_src_class_init, | ||
432 | +}; | ||
433 | + | ||
434 | +static void imx7_src_register_types(void) | ||
435 | +{ | ||
436 | + type_register_static(&imx7_src_info); | ||
437 | +} | ||
438 | + | ||
439 | +type_init(imx7_src_register_types) | ||
440 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
114 | index XXXXXXX..XXXXXXX 100644 | 441 | index XXXXXXX..XXXXXXX 100644 |
115 | --- a/MAINTAINERS | 442 | --- a/hw/misc/meson.build |
116 | +++ b/MAINTAINERS | 443 | +++ b/hw/misc/meson.build |
117 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> | 444 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( |
118 | L: qemu-arm@nongnu.org | 445 | 'imx6_src.c', |
119 | S: Maintained | 446 | 'imx6ul_ccm.c', |
120 | F: hw/*/versatile* | 447 | 'imx7_ccm.c', |
121 | +F: include/hw/i2c/arm_sbcon_i2c.h | 448 | + 'imx7_src.c', |
122 | F: hw/misc/arm_sysctl.c | 449 | 'imx7_gpr.c', |
123 | F: docs/system/arm/versatile.rst | 450 | 'imx7_snvs.c', |
124 | 451 | 'imx_ccm.c', | |
452 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
453 | index XXXXXXX..XXXXXXX 100644 | ||
454 | --- a/hw/misc/trace-events | ||
455 | +++ b/hw/misc/trace-events | ||
456 | @@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" | ||
457 | ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 | ||
458 | ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 | ||
459 | |||
460 | +# imx7_src.c | ||
461 | +imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 | ||
462 | +imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 | ||
463 | + | ||
464 | # iotkit-sysinfo.c | ||
465 | iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
466 | iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
125 | -- | 467 | -- |
126 | 2.20.1 | 468 | 2.34.1 |
127 | |||
128 | diff view generated by jsdifflib |
1 | Convert the Neon VTRN insn to decodetree. This is the last insn in the | 1 | The architecture requires (R_TYTWB) that an attempt to return from EL3 |
---|---|---|---|
2 | Neon data-processing group, so we can remove all the now-unused old | 2 | when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This |
3 | decoder framework. | 3 | enforces that the CPU can't ever be executing below EL3 with the |
4 | NSE,NS bits indicating an invalid security state.) | ||
4 | 5 | ||
5 | It's possible that there's a more efficient implementation of | 6 | We were missing this check; add it. |
6 | VTRN, but for this conversion we just copy the existing approach. | ||
7 | 7 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20200616170844.13318-21-peter.maydell@linaro.org | 10 | Message-id: 20230807150618.101357-1-peter.maydell@linaro.org |
11 | --- | 11 | --- |
12 | target/arm/neon-dp.decode | 2 +- | 12 | target/arm/tcg/helper-a64.c | 9 +++++++++ |
13 | target/arm/translate-neon.inc.c | 90 ++++++++ | 13 | 1 file changed, 9 insertions(+) |
14 | target/arm/translate.c | 363 +------------------------------- | ||
15 | 3 files changed, 93 insertions(+), 362 deletions(-) | ||
16 | 14 | ||
17 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 15 | diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/neon-dp.decode | 17 | --- a/target/arm/tcg/helper-a64.c |
20 | +++ b/target/arm/neon-dp.decode | 18 | +++ b/target/arm/tcg/helper-a64.c |
21 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 19 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) |
22 | VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc | 20 | spsr &= ~PSTATE_SS; |
23 | 21 | } | |
24 | VSWP 1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc | 22 | |
25 | - | 23 | + /* |
26 | + VTRN 1111 001 11 . 11 .. 10 .... 0 0001 . . 0 .... @2misc | 24 | + * FEAT_RME forbids return from EL3 with an invalid security state. |
27 | VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc | 25 | + * We don't need an explicit check for FEAT_RME here because we enforce |
28 | VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc | 26 | + * in scr_write() that you can't set the NSE bit without it. |
29 | 27 | + */ | |
30 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 28 | + if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) { |
31 | index XXXXXXX..XXXXXXX 100644 | 29 | + goto illegal_return; |
32 | --- a/target/arm/translate-neon.inc.c | ||
33 | +++ b/target/arm/translate-neon.inc.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a) | ||
35 | |||
36 | return true; | ||
37 | } | ||
38 | +static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) | ||
39 | +{ | ||
40 | + TCGv_i32 rd, tmp; | ||
41 | + | ||
42 | + rd = tcg_temp_new_i32(); | ||
43 | + tmp = tcg_temp_new_i32(); | ||
44 | + | ||
45 | + tcg_gen_shli_i32(rd, t0, 8); | ||
46 | + tcg_gen_andi_i32(rd, rd, 0xff00ff00); | ||
47 | + tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); | ||
48 | + tcg_gen_or_i32(rd, rd, tmp); | ||
49 | + | ||
50 | + tcg_gen_shri_i32(t1, t1, 8); | ||
51 | + tcg_gen_andi_i32(t1, t1, 0x00ff00ff); | ||
52 | + tcg_gen_andi_i32(tmp, t0, 0xff00ff00); | ||
53 | + tcg_gen_or_i32(t1, t1, tmp); | ||
54 | + tcg_gen_mov_i32(t0, rd); | ||
55 | + | ||
56 | + tcg_temp_free_i32(tmp); | ||
57 | + tcg_temp_free_i32(rd); | ||
58 | +} | ||
59 | + | ||
60 | +static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) | ||
61 | +{ | ||
62 | + TCGv_i32 rd, tmp; | ||
63 | + | ||
64 | + rd = tcg_temp_new_i32(); | ||
65 | + tmp = tcg_temp_new_i32(); | ||
66 | + | ||
67 | + tcg_gen_shli_i32(rd, t0, 16); | ||
68 | + tcg_gen_andi_i32(tmp, t1, 0xffff); | ||
69 | + tcg_gen_or_i32(rd, rd, tmp); | ||
70 | + tcg_gen_shri_i32(t1, t1, 16); | ||
71 | + tcg_gen_andi_i32(tmp, t0, 0xffff0000); | ||
72 | + tcg_gen_or_i32(t1, t1, tmp); | ||
73 | + tcg_gen_mov_i32(t0, rd); | ||
74 | + | ||
75 | + tcg_temp_free_i32(tmp); | ||
76 | + tcg_temp_free_i32(rd); | ||
77 | +} | ||
78 | + | ||
79 | +static bool trans_VTRN(DisasContext *s, arg_2misc *a) | ||
80 | +{ | ||
81 | + TCGv_i32 tmp, tmp2; | ||
82 | + int pass; | ||
83 | + | ||
84 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
85 | + return false; | ||
86 | + } | 30 | + } |
87 | + | 31 | + |
88 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | 32 | new_el = el_from_spsr(spsr); |
89 | + if (!dc_isar_feature(aa32_simd_r32, s) && | 33 | if (new_el == -1) { |
90 | + ((a->vd | a->vm) & 0x10)) { | 34 | goto illegal_return; |
91 | + return false; | ||
92 | + } | ||
93 | + | ||
94 | + if ((a->vd | a->vm) & a->q) { | ||
95 | + return false; | ||
96 | + } | ||
97 | + | ||
98 | + if (a->size == 3) { | ||
99 | + return false; | ||
100 | + } | ||
101 | + | ||
102 | + if (!vfp_access_check(s)) { | ||
103 | + return true; | ||
104 | + } | ||
105 | + | ||
106 | + if (a->size == 2) { | ||
107 | + for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) { | ||
108 | + tmp = neon_load_reg(a->vm, pass); | ||
109 | + tmp2 = neon_load_reg(a->vd, pass + 1); | ||
110 | + neon_store_reg(a->vm, pass, tmp2); | ||
111 | + neon_store_reg(a->vd, pass + 1, tmp); | ||
112 | + } | ||
113 | + } else { | ||
114 | + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
115 | + tmp = neon_load_reg(a->vm, pass); | ||
116 | + tmp2 = neon_load_reg(a->vd, pass); | ||
117 | + if (a->size == 0) { | ||
118 | + gen_neon_trn_u8(tmp, tmp2); | ||
119 | + } else { | ||
120 | + gen_neon_trn_u16(tmp, tmp2); | ||
121 | + } | ||
122 | + neon_store_reg(a->vm, pass, tmp2); | ||
123 | + neon_store_reg(a->vd, pass, tmp); | ||
124 | + } | ||
125 | + } | ||
126 | + return true; | ||
127 | +} | ||
128 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
129 | index XXXXXXX..XXXXXXX 100644 | ||
130 | --- a/target/arm/translate.c | ||
131 | +++ b/target/arm/translate.c | ||
132 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc) | ||
133 | gen_rfe(s, pc, load_cpu_field(spsr)); | ||
134 | } | ||
135 | |||
136 | -static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1) | ||
137 | -{ | ||
138 | - TCGv_i32 rd, tmp; | ||
139 | - | ||
140 | - rd = tcg_temp_new_i32(); | ||
141 | - tmp = tcg_temp_new_i32(); | ||
142 | - | ||
143 | - tcg_gen_shli_i32(rd, t0, 8); | ||
144 | - tcg_gen_andi_i32(rd, rd, 0xff00ff00); | ||
145 | - tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); | ||
146 | - tcg_gen_or_i32(rd, rd, tmp); | ||
147 | - | ||
148 | - tcg_gen_shri_i32(t1, t1, 8); | ||
149 | - tcg_gen_andi_i32(t1, t1, 0x00ff00ff); | ||
150 | - tcg_gen_andi_i32(tmp, t0, 0xff00ff00); | ||
151 | - tcg_gen_or_i32(t1, t1, tmp); | ||
152 | - tcg_gen_mov_i32(t0, rd); | ||
153 | - | ||
154 | - tcg_temp_free_i32(tmp); | ||
155 | - tcg_temp_free_i32(rd); | ||
156 | -} | ||
157 | - | ||
158 | -static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) | ||
159 | -{ | ||
160 | - TCGv_i32 rd, tmp; | ||
161 | - | ||
162 | - rd = tcg_temp_new_i32(); | ||
163 | - tmp = tcg_temp_new_i32(); | ||
164 | - | ||
165 | - tcg_gen_shli_i32(rd, t0, 16); | ||
166 | - tcg_gen_andi_i32(tmp, t1, 0xffff); | ||
167 | - tcg_gen_or_i32(rd, rd, tmp); | ||
168 | - tcg_gen_shri_i32(t1, t1, 16); | ||
169 | - tcg_gen_andi_i32(tmp, t0, 0xffff0000); | ||
170 | - tcg_gen_or_i32(t1, t1, tmp); | ||
171 | - tcg_gen_mov_i32(t0, rd); | ||
172 | - | ||
173 | - tcg_temp_free_i32(tmp); | ||
174 | - tcg_temp_free_i32(rd); | ||
175 | -} | ||
176 | - | ||
177 | -/* Symbolic constants for op fields for Neon 2-register miscellaneous. | ||
178 | - * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B | ||
179 | - * table A7-13. | ||
180 | - */ | ||
181 | -#define NEON_2RM_VREV64 0 | ||
182 | -#define NEON_2RM_VREV32 1 | ||
183 | -#define NEON_2RM_VREV16 2 | ||
184 | -#define NEON_2RM_VPADDL 4 | ||
185 | -#define NEON_2RM_VPADDL_U 5 | ||
186 | -#define NEON_2RM_AESE 6 /* Includes AESD */ | ||
187 | -#define NEON_2RM_AESMC 7 /* Includes AESIMC */ | ||
188 | -#define NEON_2RM_VCLS 8 | ||
189 | -#define NEON_2RM_VCLZ 9 | ||
190 | -#define NEON_2RM_VCNT 10 | ||
191 | -#define NEON_2RM_VMVN 11 | ||
192 | -#define NEON_2RM_VPADAL 12 | ||
193 | -#define NEON_2RM_VPADAL_U 13 | ||
194 | -#define NEON_2RM_VQABS 14 | ||
195 | -#define NEON_2RM_VQNEG 15 | ||
196 | -#define NEON_2RM_VCGT0 16 | ||
197 | -#define NEON_2RM_VCGE0 17 | ||
198 | -#define NEON_2RM_VCEQ0 18 | ||
199 | -#define NEON_2RM_VCLE0 19 | ||
200 | -#define NEON_2RM_VCLT0 20 | ||
201 | -#define NEON_2RM_SHA1H 21 | ||
202 | -#define NEON_2RM_VABS 22 | ||
203 | -#define NEON_2RM_VNEG 23 | ||
204 | -#define NEON_2RM_VCGT0_F 24 | ||
205 | -#define NEON_2RM_VCGE0_F 25 | ||
206 | -#define NEON_2RM_VCEQ0_F 26 | ||
207 | -#define NEON_2RM_VCLE0_F 27 | ||
208 | -#define NEON_2RM_VCLT0_F 28 | ||
209 | -#define NEON_2RM_VABS_F 30 | ||
210 | -#define NEON_2RM_VNEG_F 31 | ||
211 | -#define NEON_2RM_VSWP 32 | ||
212 | -#define NEON_2RM_VTRN 33 | ||
213 | -#define NEON_2RM_VUZP 34 | ||
214 | -#define NEON_2RM_VZIP 35 | ||
215 | -#define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */ | ||
216 | -#define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */ | ||
217 | -#define NEON_2RM_VSHLL 38 | ||
218 | -#define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */ | ||
219 | -#define NEON_2RM_VRINTN 40 | ||
220 | -#define NEON_2RM_VRINTX 41 | ||
221 | -#define NEON_2RM_VRINTA 42 | ||
222 | -#define NEON_2RM_VRINTZ 43 | ||
223 | -#define NEON_2RM_VCVT_F16_F32 44 | ||
224 | -#define NEON_2RM_VRINTM 45 | ||
225 | -#define NEON_2RM_VCVT_F32_F16 46 | ||
226 | -#define NEON_2RM_VRINTP 47 | ||
227 | -#define NEON_2RM_VCVTAU 48 | ||
228 | -#define NEON_2RM_VCVTAS 49 | ||
229 | -#define NEON_2RM_VCVTNU 50 | ||
230 | -#define NEON_2RM_VCVTNS 51 | ||
231 | -#define NEON_2RM_VCVTPU 52 | ||
232 | -#define NEON_2RM_VCVTPS 53 | ||
233 | -#define NEON_2RM_VCVTMU 54 | ||
234 | -#define NEON_2RM_VCVTMS 55 | ||
235 | -#define NEON_2RM_VRECPE 56 | ||
236 | -#define NEON_2RM_VRSQRTE 57 | ||
237 | -#define NEON_2RM_VRECPE_F 58 | ||
238 | -#define NEON_2RM_VRSQRTE_F 59 | ||
239 | -#define NEON_2RM_VCVT_FS 60 | ||
240 | -#define NEON_2RM_VCVT_FU 61 | ||
241 | -#define NEON_2RM_VCVT_SF 62 | ||
242 | -#define NEON_2RM_VCVT_UF 63 | ||
243 | - | ||
244 | -/* Each entry in this array has bit n set if the insn allows | ||
245 | - * size value n (otherwise it will UNDEF). Since unallocated | ||
246 | - * op values will have no bits set they always UNDEF. | ||
247 | - */ | ||
248 | -static const uint8_t neon_2rm_sizes[] = { | ||
249 | - [NEON_2RM_VREV64] = 0x7, | ||
250 | - [NEON_2RM_VREV32] = 0x3, | ||
251 | - [NEON_2RM_VREV16] = 0x1, | ||
252 | - [NEON_2RM_VPADDL] = 0x7, | ||
253 | - [NEON_2RM_VPADDL_U] = 0x7, | ||
254 | - [NEON_2RM_AESE] = 0x1, | ||
255 | - [NEON_2RM_AESMC] = 0x1, | ||
256 | - [NEON_2RM_VCLS] = 0x7, | ||
257 | - [NEON_2RM_VCLZ] = 0x7, | ||
258 | - [NEON_2RM_VCNT] = 0x1, | ||
259 | - [NEON_2RM_VMVN] = 0x1, | ||
260 | - [NEON_2RM_VPADAL] = 0x7, | ||
261 | - [NEON_2RM_VPADAL_U] = 0x7, | ||
262 | - [NEON_2RM_VQABS] = 0x7, | ||
263 | - [NEON_2RM_VQNEG] = 0x7, | ||
264 | - [NEON_2RM_VCGT0] = 0x7, | ||
265 | - [NEON_2RM_VCGE0] = 0x7, | ||
266 | - [NEON_2RM_VCEQ0] = 0x7, | ||
267 | - [NEON_2RM_VCLE0] = 0x7, | ||
268 | - [NEON_2RM_VCLT0] = 0x7, | ||
269 | - [NEON_2RM_SHA1H] = 0x4, | ||
270 | - [NEON_2RM_VABS] = 0x7, | ||
271 | - [NEON_2RM_VNEG] = 0x7, | ||
272 | - [NEON_2RM_VCGT0_F] = 0x4, | ||
273 | - [NEON_2RM_VCGE0_F] = 0x4, | ||
274 | - [NEON_2RM_VCEQ0_F] = 0x4, | ||
275 | - [NEON_2RM_VCLE0_F] = 0x4, | ||
276 | - [NEON_2RM_VCLT0_F] = 0x4, | ||
277 | - [NEON_2RM_VABS_F] = 0x4, | ||
278 | - [NEON_2RM_VNEG_F] = 0x4, | ||
279 | - [NEON_2RM_VSWP] = 0x1, | ||
280 | - [NEON_2RM_VTRN] = 0x7, | ||
281 | - [NEON_2RM_VUZP] = 0x7, | ||
282 | - [NEON_2RM_VZIP] = 0x7, | ||
283 | - [NEON_2RM_VMOVN] = 0x7, | ||
284 | - [NEON_2RM_VQMOVN] = 0x7, | ||
285 | - [NEON_2RM_VSHLL] = 0x7, | ||
286 | - [NEON_2RM_SHA1SU1] = 0x4, | ||
287 | - [NEON_2RM_VRINTN] = 0x4, | ||
288 | - [NEON_2RM_VRINTX] = 0x4, | ||
289 | - [NEON_2RM_VRINTA] = 0x4, | ||
290 | - [NEON_2RM_VRINTZ] = 0x4, | ||
291 | - [NEON_2RM_VCVT_F16_F32] = 0x2, | ||
292 | - [NEON_2RM_VRINTM] = 0x4, | ||
293 | - [NEON_2RM_VCVT_F32_F16] = 0x2, | ||
294 | - [NEON_2RM_VRINTP] = 0x4, | ||
295 | - [NEON_2RM_VCVTAU] = 0x4, | ||
296 | - [NEON_2RM_VCVTAS] = 0x4, | ||
297 | - [NEON_2RM_VCVTNU] = 0x4, | ||
298 | - [NEON_2RM_VCVTNS] = 0x4, | ||
299 | - [NEON_2RM_VCVTPU] = 0x4, | ||
300 | - [NEON_2RM_VCVTPS] = 0x4, | ||
301 | - [NEON_2RM_VCVTMU] = 0x4, | ||
302 | - [NEON_2RM_VCVTMS] = 0x4, | ||
303 | - [NEON_2RM_VRECPE] = 0x4, | ||
304 | - [NEON_2RM_VRSQRTE] = 0x4, | ||
305 | - [NEON_2RM_VRECPE_F] = 0x4, | ||
306 | - [NEON_2RM_VRSQRTE_F] = 0x4, | ||
307 | - [NEON_2RM_VCVT_FS] = 0x4, | ||
308 | - [NEON_2RM_VCVT_FU] = 0x4, | ||
309 | - [NEON_2RM_VCVT_SF] = 0x4, | ||
310 | - [NEON_2RM_VCVT_UF] = 0x4, | ||
311 | -}; | ||
312 | - | ||
313 | static void gen_gvec_fn3_qc(uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs, | ||
314 | uint32_t opr_sz, uint32_t max_sz, | ||
315 | gen_helper_gvec_3_ptr *fn) | ||
316 | @@ -XXX,XX +XXX,XX @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | ||
317 | tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]); | ||
318 | } | ||
319 | |||
320 | -/* Translate a NEON data processing instruction. Return nonzero if the | ||
321 | - instruction is invalid. | ||
322 | - We process data in a mixture of 32-bit and 64-bit chunks. | ||
323 | - Mostly we use 32-bit chunks so we can use normal scalar instructions. */ | ||
324 | - | ||
325 | -static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
326 | -{ | ||
327 | - int op; | ||
328 | - int q; | ||
329 | - int rd, rm; | ||
330 | - int size; | ||
331 | - int pass; | ||
332 | - int u; | ||
333 | - TCGv_i32 tmp, tmp2; | ||
334 | - | ||
335 | - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
336 | - return 1; | ||
337 | - } | ||
338 | - | ||
339 | - /* FIXME: this access check should not take precedence over UNDEF | ||
340 | - * for invalid encodings; we will generate incorrect syndrome information | ||
341 | - * for attempts to execute invalid vfp/neon encodings with FP disabled. | ||
342 | - */ | ||
343 | - if (s->fp_excp_el) { | ||
344 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
345 | - syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); | ||
346 | - return 0; | ||
347 | - } | ||
348 | - | ||
349 | - if (!s->vfp_enabled) | ||
350 | - return 1; | ||
351 | - q = (insn & (1 << 6)) != 0; | ||
352 | - u = (insn >> 24) & 1; | ||
353 | - VFP_DREG_D(rd, insn); | ||
354 | - VFP_DREG_M(rm, insn); | ||
355 | - size = (insn >> 20) & 3; | ||
356 | - | ||
357 | - if ((insn & (1 << 23)) == 0) { | ||
358 | - /* Three register same length: handled by decodetree */ | ||
359 | - return 1; | ||
360 | - } else if (insn & (1 << 4)) { | ||
361 | - /* Two registers and shift or reg and imm: handled by decodetree */ | ||
362 | - return 1; | ||
363 | - } else { /* (insn & 0x00800010 == 0x00800000) */ | ||
364 | - if (size != 3) { | ||
365 | - /* | ||
366 | - * Three registers of different lengths, or two registers and | ||
367 | - * a scalar: handled by decodetree | ||
368 | - */ | ||
369 | - return 1; | ||
370 | - } else { /* size == 3 */ | ||
371 | - if (!u) { | ||
372 | - /* Extract: handled by decodetree */ | ||
373 | - return 1; | ||
374 | - } else if ((insn & (1 << 11)) == 0) { | ||
375 | - /* Two register misc. */ | ||
376 | - op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf); | ||
377 | - size = (insn >> 18) & 3; | ||
378 | - /* UNDEF for unknown op values and bad op-size combinations */ | ||
379 | - if ((neon_2rm_sizes[op] & (1 << size)) == 0) { | ||
380 | - return 1; | ||
381 | - } | ||
382 | - if (q && ((rm | rd) & 1)) { | ||
383 | - return 1; | ||
384 | - } | ||
385 | - switch (op) { | ||
386 | - case NEON_2RM_VREV64: | ||
387 | - case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U: | ||
388 | - case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U: | ||
389 | - case NEON_2RM_VUZP: | ||
390 | - case NEON_2RM_VZIP: | ||
391 | - case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN: | ||
392 | - case NEON_2RM_VSHLL: | ||
393 | - case NEON_2RM_VCVT_F16_F32: | ||
394 | - case NEON_2RM_VCVT_F32_F16: | ||
395 | - case NEON_2RM_VMVN: | ||
396 | - case NEON_2RM_VNEG: | ||
397 | - case NEON_2RM_VABS: | ||
398 | - case NEON_2RM_VCEQ0: | ||
399 | - case NEON_2RM_VCGT0: | ||
400 | - case NEON_2RM_VCLE0: | ||
401 | - case NEON_2RM_VCGE0: | ||
402 | - case NEON_2RM_VCLT0: | ||
403 | - case NEON_2RM_AESE: case NEON_2RM_AESMC: | ||
404 | - case NEON_2RM_SHA1H: | ||
405 | - case NEON_2RM_SHA1SU1: | ||
406 | - case NEON_2RM_VREV32: | ||
407 | - case NEON_2RM_VREV16: | ||
408 | - case NEON_2RM_VCLS: | ||
409 | - case NEON_2RM_VCLZ: | ||
410 | - case NEON_2RM_VCNT: | ||
411 | - case NEON_2RM_VABS_F: | ||
412 | - case NEON_2RM_VNEG_F: | ||
413 | - case NEON_2RM_VRECPE: | ||
414 | - case NEON_2RM_VRSQRTE: | ||
415 | - case NEON_2RM_VQABS: | ||
416 | - case NEON_2RM_VQNEG: | ||
417 | - case NEON_2RM_VRECPE_F: | ||
418 | - case NEON_2RM_VRSQRTE_F: | ||
419 | - case NEON_2RM_VCVT_FS: | ||
420 | - case NEON_2RM_VCVT_FU: | ||
421 | - case NEON_2RM_VCVT_SF: | ||
422 | - case NEON_2RM_VCVT_UF: | ||
423 | - case NEON_2RM_VRINTX: | ||
424 | - case NEON_2RM_VCGT0_F: | ||
425 | - case NEON_2RM_VCGE0_F: | ||
426 | - case NEON_2RM_VCEQ0_F: | ||
427 | - case NEON_2RM_VCLE0_F: | ||
428 | - case NEON_2RM_VCLT0_F: | ||
429 | - case NEON_2RM_VRINTN: | ||
430 | - case NEON_2RM_VRINTA: | ||
431 | - case NEON_2RM_VRINTM: | ||
432 | - case NEON_2RM_VRINTP: | ||
433 | - case NEON_2RM_VRINTZ: | ||
434 | - case NEON_2RM_VCVTAU: | ||
435 | - case NEON_2RM_VCVTAS: | ||
436 | - case NEON_2RM_VCVTNU: | ||
437 | - case NEON_2RM_VCVTNS: | ||
438 | - case NEON_2RM_VCVTPU: | ||
439 | - case NEON_2RM_VCVTPS: | ||
440 | - case NEON_2RM_VCVTMU: | ||
441 | - case NEON_2RM_VCVTMS: | ||
442 | - case NEON_2RM_VSWP: | ||
443 | - /* handled by decodetree */ | ||
444 | - return 1; | ||
445 | - case NEON_2RM_VTRN: | ||
446 | - if (size == 2) { | ||
447 | - int n; | ||
448 | - for (n = 0; n < (q ? 4 : 2); n += 2) { | ||
449 | - tmp = neon_load_reg(rm, n); | ||
450 | - tmp2 = neon_load_reg(rd, n + 1); | ||
451 | - neon_store_reg(rm, n, tmp2); | ||
452 | - neon_store_reg(rd, n + 1, tmp); | ||
453 | - } | ||
454 | - } else { | ||
455 | - goto elementwise; | ||
456 | - } | ||
457 | - break; | ||
458 | - | ||
459 | - default: | ||
460 | - elementwise: | ||
461 | - for (pass = 0; pass < (q ? 4 : 2); pass++) { | ||
462 | - tmp = neon_load_reg(rm, pass); | ||
463 | - switch (op) { | ||
464 | - case NEON_2RM_VTRN: | ||
465 | - tmp2 = neon_load_reg(rd, pass); | ||
466 | - switch (size) { | ||
467 | - case 0: gen_neon_trn_u8(tmp, tmp2); break; | ||
468 | - case 1: gen_neon_trn_u16(tmp, tmp2); break; | ||
469 | - default: abort(); | ||
470 | - } | ||
471 | - neon_store_reg(rm, pass, tmp2); | ||
472 | - break; | ||
473 | - default: | ||
474 | - /* Reserved op values were caught by the | ||
475 | - * neon_2rm_sizes[] check earlier. | ||
476 | - */ | ||
477 | - abort(); | ||
478 | - } | ||
479 | - neon_store_reg(rd, pass, tmp); | ||
480 | - } | ||
481 | - break; | ||
482 | - } | ||
483 | - } else { | ||
484 | - /* VTBL, VTBX, VDUP: handled by decodetree */ | ||
485 | - return 1; | ||
486 | - } | ||
487 | - } | ||
488 | - } | ||
489 | - return 0; | ||
490 | -} | ||
491 | - | ||
492 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | ||
493 | { | ||
494 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | ||
495 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
496 | } | ||
497 | /* fall back to legacy decoder */ | ||
498 | |||
499 | - if (((insn >> 25) & 7) == 1) { | ||
500 | - /* NEON Data processing. */ | ||
501 | - if (disas_neon_data_insn(s, insn)) { | ||
502 | - goto illegal_op; | ||
503 | - } | ||
504 | - return; | ||
505 | - } | ||
506 | if ((insn & 0x0e000f00) == 0x0c000100) { | ||
507 | if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { | ||
508 | /* iWMMXt register transfer. */ | ||
509 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
510 | break; | ||
511 | } | ||
512 | if (((insn >> 24) & 3) == 3) { | ||
513 | - /* Translate into the equivalent ARM encoding. */ | ||
514 | - insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); | ||
515 | - if (disas_neon_data_insn(s, insn)) { | ||
516 | - goto illegal_op; | ||
517 | - } | ||
518 | + /* Neon DP, but failed disas_neon_dp() */ | ||
519 | + goto illegal_op; | ||
520 | } else if (((insn >> 8) & 0xe) == 10) { | ||
521 | /* VFP, but failed disas_vfp. */ | ||
522 | goto illegal_op; | ||
523 | -- | 35 | -- |
524 | 2.20.1 | 36 | 2.34.1 |
525 | |||
526 | diff view generated by jsdifflib |
1 | The functions neon_element_offset(), neon_load_element(), | 1 | In the m48t59 device we almost always use 64-bit arithmetic when |
---|---|---|---|
2 | neon_load_element64(), neon_store_element() and | 2 | dealing with time_t deltas. The one exception is in set_alarm(), |
3 | neon_store_element64() are used only in the translate-neon.inc.c | 3 | which currently uses a plain 'int' to hold the difference between two |
4 | file, so move their definitions there. | 4 | time_t values. Switch to int64_t instead to avoid any possible |
5 | 5 | overflow issues. | |
6 | Since the .inc.c file is #included in translate.c this doesn't make | ||
7 | much difference currently, but it's a more logical place to put the | ||
8 | functions and it might be helpful if we ever decide to try to make | ||
9 | the .inc.c files genuinely separate compilation units. | ||
10 | 6 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
13 | Message-id: 20200616170844.13318-22-peter.maydell@linaro.org | ||
14 | --- | 9 | --- |
15 | target/arm/translate-neon.inc.c | 101 ++++++++++++++++++++++++++++++++ | 10 | hw/rtc/m48t59.c | 2 +- |
16 | target/arm/translate.c | 101 -------------------------------- | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
17 | 2 files changed, 101 insertions(+), 101 deletions(-) | ||
18 | 12 | ||
19 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 13 | diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c |
20 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/translate-neon.inc.c | 15 | --- a/hw/rtc/m48t59.c |
22 | +++ b/target/arm/translate-neon.inc.c | 16 | +++ b/hw/rtc/m48t59.c |
23 | @@ -XXX,XX +XXX,XX @@ static inline int rsub_8(DisasContext *s, int x) | 17 | @@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque) |
24 | #include "decode-neon-ls.inc.c" | 18 | |
25 | #include "decode-neon-shared.inc.c" | 19 | static void set_alarm(M48t59State *NVRAM) |
26 | |||
27 | +/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | ||
28 | + * where 0 is the least significant end of the register. | ||
29 | + */ | ||
30 | +static inline long | ||
31 | +neon_element_offset(int reg, int element, MemOp size) | ||
32 | +{ | ||
33 | + int element_size = 1 << size; | ||
34 | + int ofs = element * element_size; | ||
35 | +#ifdef HOST_WORDS_BIGENDIAN | ||
36 | + /* Calculate the offset assuming fully little-endian, | ||
37 | + * then XOR to account for the order of the 8-byte units. | ||
38 | + */ | ||
39 | + if (element_size < 8) { | ||
40 | + ofs ^= 8 - element_size; | ||
41 | + } | ||
42 | +#endif | ||
43 | + return neon_reg_offset(reg, 0) + ofs; | ||
44 | +} | ||
45 | + | ||
46 | +static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) | ||
47 | +{ | ||
48 | + long offset = neon_element_offset(reg, ele, mop & MO_SIZE); | ||
49 | + | ||
50 | + switch (mop) { | ||
51 | + case MO_UB: | ||
52 | + tcg_gen_ld8u_i32(var, cpu_env, offset); | ||
53 | + break; | ||
54 | + case MO_UW: | ||
55 | + tcg_gen_ld16u_i32(var, cpu_env, offset); | ||
56 | + break; | ||
57 | + case MO_UL: | ||
58 | + tcg_gen_ld_i32(var, cpu_env, offset); | ||
59 | + break; | ||
60 | + default: | ||
61 | + g_assert_not_reached(); | ||
62 | + } | ||
63 | +} | ||
64 | + | ||
65 | +static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop) | ||
66 | +{ | ||
67 | + long offset = neon_element_offset(reg, ele, mop & MO_SIZE); | ||
68 | + | ||
69 | + switch (mop) { | ||
70 | + case MO_UB: | ||
71 | + tcg_gen_ld8u_i64(var, cpu_env, offset); | ||
72 | + break; | ||
73 | + case MO_UW: | ||
74 | + tcg_gen_ld16u_i64(var, cpu_env, offset); | ||
75 | + break; | ||
76 | + case MO_UL: | ||
77 | + tcg_gen_ld32u_i64(var, cpu_env, offset); | ||
78 | + break; | ||
79 | + case MO_Q: | ||
80 | + tcg_gen_ld_i64(var, cpu_env, offset); | ||
81 | + break; | ||
82 | + default: | ||
83 | + g_assert_not_reached(); | ||
84 | + } | ||
85 | +} | ||
86 | + | ||
87 | +static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var) | ||
88 | +{ | ||
89 | + long offset = neon_element_offset(reg, ele, size); | ||
90 | + | ||
91 | + switch (size) { | ||
92 | + case MO_8: | ||
93 | + tcg_gen_st8_i32(var, cpu_env, offset); | ||
94 | + break; | ||
95 | + case MO_16: | ||
96 | + tcg_gen_st16_i32(var, cpu_env, offset); | ||
97 | + break; | ||
98 | + case MO_32: | ||
99 | + tcg_gen_st_i32(var, cpu_env, offset); | ||
100 | + break; | ||
101 | + default: | ||
102 | + g_assert_not_reached(); | ||
103 | + } | ||
104 | +} | ||
105 | + | ||
106 | +static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var) | ||
107 | +{ | ||
108 | + long offset = neon_element_offset(reg, ele, size); | ||
109 | + | ||
110 | + switch (size) { | ||
111 | + case MO_8: | ||
112 | + tcg_gen_st8_i64(var, cpu_env, offset); | ||
113 | + break; | ||
114 | + case MO_16: | ||
115 | + tcg_gen_st16_i64(var, cpu_env, offset); | ||
116 | + break; | ||
117 | + case MO_32: | ||
118 | + tcg_gen_st32_i64(var, cpu_env, offset); | ||
119 | + break; | ||
120 | + case MO_64: | ||
121 | + tcg_gen_st_i64(var, cpu_env, offset); | ||
122 | + break; | ||
123 | + default: | ||
124 | + g_assert_not_reached(); | ||
125 | + } | ||
126 | +} | ||
127 | + | ||
128 | static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) | ||
129 | { | 20 | { |
130 | int opr_sz; | 21 | - int diff; |
131 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 22 | + int64_t diff; |
132 | index XXXXXXX..XXXXXXX 100644 | 23 | if (NVRAM->alrm_timer != NULL) { |
133 | --- a/target/arm/translate.c | 24 | timer_del(NVRAM->alrm_timer); |
134 | +++ b/target/arm/translate.c | 25 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
135 | @@ -XXX,XX +XXX,XX @@ neon_reg_offset (int reg, int n) | ||
136 | return vfp_reg_offset(0, sreg); | ||
137 | } | ||
138 | |||
139 | -/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, | ||
140 | - * where 0 is the least significant end of the register. | ||
141 | - */ | ||
142 | -static inline long | ||
143 | -neon_element_offset(int reg, int element, MemOp size) | ||
144 | -{ | ||
145 | - int element_size = 1 << size; | ||
146 | - int ofs = element * element_size; | ||
147 | -#ifdef HOST_WORDS_BIGENDIAN | ||
148 | - /* Calculate the offset assuming fully little-endian, | ||
149 | - * then XOR to account for the order of the 8-byte units. | ||
150 | - */ | ||
151 | - if (element_size < 8) { | ||
152 | - ofs ^= 8 - element_size; | ||
153 | - } | ||
154 | -#endif | ||
155 | - return neon_reg_offset(reg, 0) + ofs; | ||
156 | -} | ||
157 | - | ||
158 | static TCGv_i32 neon_load_reg(int reg, int pass) | ||
159 | { | ||
160 | TCGv_i32 tmp = tcg_temp_new_i32(); | ||
161 | @@ -XXX,XX +XXX,XX @@ static TCGv_i32 neon_load_reg(int reg, int pass) | ||
162 | return tmp; | ||
163 | } | ||
164 | |||
165 | -static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) | ||
166 | -{ | ||
167 | - long offset = neon_element_offset(reg, ele, mop & MO_SIZE); | ||
168 | - | ||
169 | - switch (mop) { | ||
170 | - case MO_UB: | ||
171 | - tcg_gen_ld8u_i32(var, cpu_env, offset); | ||
172 | - break; | ||
173 | - case MO_UW: | ||
174 | - tcg_gen_ld16u_i32(var, cpu_env, offset); | ||
175 | - break; | ||
176 | - case MO_UL: | ||
177 | - tcg_gen_ld_i32(var, cpu_env, offset); | ||
178 | - break; | ||
179 | - default: | ||
180 | - g_assert_not_reached(); | ||
181 | - } | ||
182 | -} | ||
183 | - | ||
184 | -static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop) | ||
185 | -{ | ||
186 | - long offset = neon_element_offset(reg, ele, mop & MO_SIZE); | ||
187 | - | ||
188 | - switch (mop) { | ||
189 | - case MO_UB: | ||
190 | - tcg_gen_ld8u_i64(var, cpu_env, offset); | ||
191 | - break; | ||
192 | - case MO_UW: | ||
193 | - tcg_gen_ld16u_i64(var, cpu_env, offset); | ||
194 | - break; | ||
195 | - case MO_UL: | ||
196 | - tcg_gen_ld32u_i64(var, cpu_env, offset); | ||
197 | - break; | ||
198 | - case MO_Q: | ||
199 | - tcg_gen_ld_i64(var, cpu_env, offset); | ||
200 | - break; | ||
201 | - default: | ||
202 | - g_assert_not_reached(); | ||
203 | - } | ||
204 | -} | ||
205 | - | ||
206 | static void neon_store_reg(int reg, int pass, TCGv_i32 var) | ||
207 | { | ||
208 | tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); | ||
209 | tcg_temp_free_i32(var); | ||
210 | } | ||
211 | |||
212 | -static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var) | ||
213 | -{ | ||
214 | - long offset = neon_element_offset(reg, ele, size); | ||
215 | - | ||
216 | - switch (size) { | ||
217 | - case MO_8: | ||
218 | - tcg_gen_st8_i32(var, cpu_env, offset); | ||
219 | - break; | ||
220 | - case MO_16: | ||
221 | - tcg_gen_st16_i32(var, cpu_env, offset); | ||
222 | - break; | ||
223 | - case MO_32: | ||
224 | - tcg_gen_st_i32(var, cpu_env, offset); | ||
225 | - break; | ||
226 | - default: | ||
227 | - g_assert_not_reached(); | ||
228 | - } | ||
229 | -} | ||
230 | - | ||
231 | -static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 var) | ||
232 | -{ | ||
233 | - long offset = neon_element_offset(reg, ele, size); | ||
234 | - | ||
235 | - switch (size) { | ||
236 | - case MO_8: | ||
237 | - tcg_gen_st8_i64(var, cpu_env, offset); | ||
238 | - break; | ||
239 | - case MO_16: | ||
240 | - tcg_gen_st16_i64(var, cpu_env, offset); | ||
241 | - break; | ||
242 | - case MO_32: | ||
243 | - tcg_gen_st32_i64(var, cpu_env, offset); | ||
244 | - break; | ||
245 | - case MO_64: | ||
246 | - tcg_gen_st_i64(var, cpu_env, offset); | ||
247 | - break; | ||
248 | - default: | ||
249 | - g_assert_not_reached(); | ||
250 | - } | ||
251 | -} | ||
252 | - | ||
253 | static inline void neon_load_reg64(TCGv_i64 var, int reg) | ||
254 | { | ||
255 | tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); | ||
256 | -- | 26 | -- |
257 | 2.20.1 | 27 | 2.34.1 |
258 | 28 | ||
259 | 29 | diff view generated by jsdifflib |
1 | Convert the Neon VSWP insn to decodetree. Since the new implementation | 1 | In the twl92230 device, use int64_t for the two state fields |
---|---|---|---|
2 | doesn't have to share a pass-loop with the other 2-reg-misc operations | 2 | sec_offset and alm_sec, because we set these to values that |
3 | we can implement the swap with 64-bit accesses rather than 32-bits | 3 | are either time_t or differences between two time_t values. |
4 | (which brings us into line with the pseudocode and is more efficient). | 4 | |
5 | These fields aren't saved in vmstate anywhere, so we can | ||
6 | safely widen them. | ||
5 | 7 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20200616170844.13318-20-peter.maydell@linaro.org | ||
9 | --- | 10 | --- |
10 | target/arm/neon-dp.decode | 2 ++ | 11 | hw/rtc/twl92230.c | 4 ++-- |
11 | target/arm/translate-neon.inc.c | 41 +++++++++++++++++++++++++++++++++ | 12 | 1 file changed, 2 insertions(+), 2 deletions(-) |
12 | target/arm/translate.c | 5 +--- | ||
13 | 3 files changed, 44 insertions(+), 4 deletions(-) | ||
14 | 13 | ||
15 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 14 | diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/neon-dp.decode | 16 | --- a/hw/rtc/twl92230.c |
18 | +++ b/target/arm/neon-dp.decode | 17 | +++ b/hw/rtc/twl92230.c |
19 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 18 | @@ -XXX,XX +XXX,XX @@ struct MenelausState { |
20 | VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc | 19 | struct tm tm; |
21 | VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc | 20 | struct tm new; |
22 | 21 | struct tm alm; | |
23 | + VSWP 1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc | 22 | - int sec_offset; |
24 | + | 23 | - int alm_sec; |
25 | VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc | 24 | + int64_t sec_offset; |
26 | VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc | 25 | + int64_t alm_sec; |
27 | 26 | int next_comp; | |
28 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 27 | } rtc; |
29 | index XXXXXXX..XXXXXXX 100644 | 28 | uint16_t rtc_next_vmstate; |
30 | --- a/target/arm/translate-neon.inc.c | ||
31 | +++ b/target/arm/translate-neon.inc.c | ||
32 | @@ -XXX,XX +XXX,XX @@ DO_VCVT(VCVTPU, FPROUNDING_POSINF, false) | ||
33 | DO_VCVT(VCVTPS, FPROUNDING_POSINF, true) | ||
34 | DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false) | ||
35 | DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true) | ||
36 | + | ||
37 | +static bool trans_VSWP(DisasContext *s, arg_2misc *a) | ||
38 | +{ | ||
39 | + TCGv_i64 rm, rd; | ||
40 | + int pass; | ||
41 | + | ||
42 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
43 | + return false; | ||
44 | + } | ||
45 | + | ||
46 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
47 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
48 | + ((a->vd | a->vm) & 0x10)) { | ||
49 | + return false; | ||
50 | + } | ||
51 | + | ||
52 | + if (a->size != 0) { | ||
53 | + return false; | ||
54 | + } | ||
55 | + | ||
56 | + if ((a->vd | a->vm) & a->q) { | ||
57 | + return false; | ||
58 | + } | ||
59 | + | ||
60 | + if (!vfp_access_check(s)) { | ||
61 | + return true; | ||
62 | + } | ||
63 | + | ||
64 | + rm = tcg_temp_new_i64(); | ||
65 | + rd = tcg_temp_new_i64(); | ||
66 | + for (pass = 0; pass < (a->q ? 2 : 1); pass++) { | ||
67 | + neon_load_reg64(rm, a->vm + pass); | ||
68 | + neon_load_reg64(rd, a->vd + pass); | ||
69 | + neon_store_reg64(rm, a->vd + pass); | ||
70 | + neon_store_reg64(rd, a->vm + pass); | ||
71 | + } | ||
72 | + tcg_temp_free_i64(rm); | ||
73 | + tcg_temp_free_i64(rd); | ||
74 | + | ||
75 | + return true; | ||
76 | +} | ||
77 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/target/arm/translate.c | ||
80 | +++ b/target/arm/translate.c | ||
81 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
82 | case NEON_2RM_VCVTPS: | ||
83 | case NEON_2RM_VCVTMU: | ||
84 | case NEON_2RM_VCVTMS: | ||
85 | + case NEON_2RM_VSWP: | ||
86 | /* handled by decodetree */ | ||
87 | return 1; | ||
88 | case NEON_2RM_VTRN: | ||
89 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
90 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | ||
91 | tmp = neon_load_reg(rm, pass); | ||
92 | switch (op) { | ||
93 | - case NEON_2RM_VSWP: | ||
94 | - tmp2 = neon_load_reg(rd, pass); | ||
95 | - neon_store_reg(rm, pass, tmp2); | ||
96 | - break; | ||
97 | case NEON_2RM_VTRN: | ||
98 | tmp2 = neon_load_reg(rd, pass); | ||
99 | switch (size) { | ||
100 | -- | 29 | -- |
101 | 2.20.1 | 30 | 2.34.1 |
102 | 31 | ||
103 | 32 | diff view generated by jsdifflib |
1 | Convert the VCVT instructions in the 2-reg-misc grouping to | 1 | In the aspeed_rtc device we store a difference between two time_t |
---|---|---|---|
2 | decodetree. | 2 | values in an 'int'. This is not really correct when time_t could |
3 | be 64 bits. Enlarge the field to 'int64_t'. | ||
4 | |||
5 | This is a migration compatibility break for the aspeed boards. | ||
6 | While we are changing the vmstate, remove the accidental | ||
7 | duplicate of the offset field. | ||
3 | 8 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
6 | Message-id: 20200616170844.13318-19-peter.maydell@linaro.org | ||
7 | --- | 11 | --- |
8 | target/arm/neon-dp.decode | 9 +++++ | 12 | include/hw/rtc/aspeed_rtc.h | 2 +- |
9 | target/arm/translate-neon.inc.c | 70 +++++++++++++++++++++++++++++++++ | 13 | hw/rtc/aspeed_rtc.c | 5 ++--- |
10 | target/arm/translate.c | 70 ++++----------------------------- | 14 | 2 files changed, 3 insertions(+), 4 deletions(-) |
11 | 3 files changed, 87 insertions(+), 62 deletions(-) | ||
12 | 15 | ||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 16 | diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h |
14 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/neon-dp.decode | 18 | --- a/include/hw/rtc/aspeed_rtc.h |
16 | +++ b/target/arm/neon-dp.decode | 19 | +++ b/include/hw/rtc/aspeed_rtc.h |
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 20 | @@ -XXX,XX +XXX,XX @@ struct AspeedRtcState { |
18 | 21 | qemu_irq irq; | |
19 | VRINTP 1111 001 11 . 11 .. 10 .... 0 1111 . . 0 .... @2misc | 22 | |
20 | 23 | uint32_t reg[0x18]; | |
21 | + VCVTAS 1111 001 11 . 11 .. 11 .... 0 0000 . . 0 .... @2misc | 24 | - int offset; |
22 | + VCVTAU 1111 001 11 . 11 .. 11 .... 0 0001 . . 0 .... @2misc | 25 | + int64_t offset; |
23 | + VCVTNS 1111 001 11 . 11 .. 11 .... 0 0010 . . 0 .... @2misc | 26 | |
24 | + VCVTNU 1111 001 11 . 11 .. 11 .... 0 0011 . . 0 .... @2misc | 27 | }; |
25 | + VCVTPS 1111 001 11 . 11 .. 11 .... 0 0100 . . 0 .... @2misc | 28 | |
26 | + VCVTPU 1111 001 11 . 11 .. 11 .... 0 0101 . . 0 .... @2misc | 29 | diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c |
27 | + VCVTMS 1111 001 11 . 11 .. 11 .... 0 0110 . . 0 .... @2misc | ||
28 | + VCVTMU 1111 001 11 . 11 .. 11 .... 0 0111 . . 0 .... @2misc | ||
29 | + | ||
30 | VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc | ||
31 | VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc | ||
32 | VRECPE_F 1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc | ||
33 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
34 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
35 | --- a/target/arm/translate-neon.inc.c | 31 | --- a/hw/rtc/aspeed_rtc.c |
36 | +++ b/target/arm/translate-neon.inc.c | 32 | +++ b/hw/rtc/aspeed_rtc.c |
37 | @@ -XXX,XX +XXX,XX @@ DO_VRINT(VRINTA, FPROUNDING_TIEAWAY) | 33 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = { |
38 | DO_VRINT(VRINTZ, FPROUNDING_ZERO) | 34 | |
39 | DO_VRINT(VRINTM, FPROUNDING_NEGINF) | 35 | static const VMStateDescription vmstate_aspeed_rtc = { |
40 | DO_VRINT(VRINTP, FPROUNDING_POSINF) | 36 | .name = TYPE_ASPEED_RTC, |
41 | + | 37 | - .version_id = 1, |
42 | +static bool do_vcvt(DisasContext *s, arg_2misc *a, int rmode, bool is_signed) | 38 | + .version_id = 2, |
43 | +{ | 39 | .fields = (VMStateField[]) { |
44 | + /* | 40 | VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18), |
45 | + * Handle a VCVT* operation by iterating 32 bits at a time, | 41 | - VMSTATE_INT32(offset, AspeedRtcState), |
46 | + * with a specified rounding mode in operation. | 42 | - VMSTATE_INT32(offset, AspeedRtcState), |
47 | + */ | 43 | + VMSTATE_INT64(offset, AspeedRtcState), |
48 | + int pass; | 44 | VMSTATE_END_OF_LIST() |
49 | + TCGv_ptr fpst; | 45 | } |
50 | + TCGv_i32 tcg_rmode, tcg_shift; | 46 | }; |
51 | + | ||
52 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || | ||
53 | + !arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
54 | + return false; | ||
55 | + } | ||
56 | + | ||
57 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
58 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
59 | + ((a->vd | a->vm) & 0x10)) { | ||
60 | + return false; | ||
61 | + } | ||
62 | + | ||
63 | + if (a->size != 2) { | ||
64 | + /* TODO: FP16 will be the size == 1 case */ | ||
65 | + return false; | ||
66 | + } | ||
67 | + | ||
68 | + if ((a->vd | a->vm) & a->q) { | ||
69 | + return false; | ||
70 | + } | ||
71 | + | ||
72 | + if (!vfp_access_check(s)) { | ||
73 | + return true; | ||
74 | + } | ||
75 | + | ||
76 | + fpst = get_fpstatus_ptr(1); | ||
77 | + tcg_shift = tcg_const_i32(0); | ||
78 | + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | ||
79 | + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); | ||
80 | + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
81 | + TCGv_i32 tmp = neon_load_reg(a->vm, pass); | ||
82 | + if (is_signed) { | ||
83 | + gen_helper_vfp_tosls(tmp, tmp, tcg_shift, fpst); | ||
84 | + } else { | ||
85 | + gen_helper_vfp_touls(tmp, tmp, tcg_shift, fpst); | ||
86 | + } | ||
87 | + neon_store_reg(a->vd, pass, tmp); | ||
88 | + } | ||
89 | + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); | ||
90 | + tcg_temp_free_i32(tcg_rmode); | ||
91 | + tcg_temp_free_i32(tcg_shift); | ||
92 | + tcg_temp_free_ptr(fpst); | ||
93 | + | ||
94 | + return true; | ||
95 | +} | ||
96 | + | ||
97 | +#define DO_VCVT(INSN, RMODE, SIGNED) \ | ||
98 | + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ | ||
99 | + { \ | ||
100 | + return do_vcvt(s, a, RMODE, SIGNED); \ | ||
101 | + } | ||
102 | + | ||
103 | +DO_VCVT(VCVTAU, FPROUNDING_TIEAWAY, false) | ||
104 | +DO_VCVT(VCVTAS, FPROUNDING_TIEAWAY, true) | ||
105 | +DO_VCVT(VCVTNU, FPROUNDING_TIEEVEN, false) | ||
106 | +DO_VCVT(VCVTNS, FPROUNDING_TIEEVEN, true) | ||
107 | +DO_VCVT(VCVTPU, FPROUNDING_POSINF, false) | ||
108 | +DO_VCVT(VCVTPS, FPROUNDING_POSINF, true) | ||
109 | +DO_VCVT(VCVTMU, FPROUNDING_NEGINF, false) | ||
110 | +DO_VCVT(VCVTMS, FPROUNDING_NEGINF, true) | ||
111 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
112 | index XXXXXXX..XXXXXXX 100644 | ||
113 | --- a/target/arm/translate.c | ||
114 | +++ b/target/arm/translate.c | ||
115 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) | ||
116 | #define NEON_2RM_VCVT_SF 62 | ||
117 | #define NEON_2RM_VCVT_UF 63 | ||
118 | |||
119 | -static bool neon_2rm_is_v8_op(int op) | ||
120 | -{ | ||
121 | - /* Return true if this neon 2reg-misc op is ARMv8 and up */ | ||
122 | - switch (op) { | ||
123 | - case NEON_2RM_VRINTN: | ||
124 | - case NEON_2RM_VRINTA: | ||
125 | - case NEON_2RM_VRINTM: | ||
126 | - case NEON_2RM_VRINTP: | ||
127 | - case NEON_2RM_VRINTZ: | ||
128 | - case NEON_2RM_VRINTX: | ||
129 | - case NEON_2RM_VCVTAU: | ||
130 | - case NEON_2RM_VCVTAS: | ||
131 | - case NEON_2RM_VCVTNU: | ||
132 | - case NEON_2RM_VCVTNS: | ||
133 | - case NEON_2RM_VCVTPU: | ||
134 | - case NEON_2RM_VCVTPS: | ||
135 | - case NEON_2RM_VCVTMU: | ||
136 | - case NEON_2RM_VCVTMS: | ||
137 | - return true; | ||
138 | - default: | ||
139 | - return false; | ||
140 | - } | ||
141 | -} | ||
142 | - | ||
143 | /* Each entry in this array has bit n set if the insn allows | ||
144 | * size value n (otherwise it will UNDEF). Since unallocated | ||
145 | * op values will have no bits set they always UNDEF. | ||
146 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
147 | if ((neon_2rm_sizes[op] & (1 << size)) == 0) { | ||
148 | return 1; | ||
149 | } | ||
150 | - if (neon_2rm_is_v8_op(op) && | ||
151 | - !arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
152 | - return 1; | ||
153 | - } | ||
154 | if (q && ((rm | rd) & 1)) { | ||
155 | return 1; | ||
156 | } | ||
157 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
158 | case NEON_2RM_VRINTM: | ||
159 | case NEON_2RM_VRINTP: | ||
160 | case NEON_2RM_VRINTZ: | ||
161 | + case NEON_2RM_VCVTAU: | ||
162 | + case NEON_2RM_VCVTAS: | ||
163 | + case NEON_2RM_VCVTNU: | ||
164 | + case NEON_2RM_VCVTNS: | ||
165 | + case NEON_2RM_VCVTPU: | ||
166 | + case NEON_2RM_VCVTPS: | ||
167 | + case NEON_2RM_VCVTMU: | ||
168 | + case NEON_2RM_VCVTMS: | ||
169 | /* handled by decodetree */ | ||
170 | return 1; | ||
171 | case NEON_2RM_VTRN: | ||
172 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
173 | } | ||
174 | neon_store_reg(rm, pass, tmp2); | ||
175 | break; | ||
176 | - case NEON_2RM_VCVTAU: | ||
177 | - case NEON_2RM_VCVTAS: | ||
178 | - case NEON_2RM_VCVTNU: | ||
179 | - case NEON_2RM_VCVTNS: | ||
180 | - case NEON_2RM_VCVTPU: | ||
181 | - case NEON_2RM_VCVTPS: | ||
182 | - case NEON_2RM_VCVTMU: | ||
183 | - case NEON_2RM_VCVTMS: | ||
184 | - { | ||
185 | - bool is_signed = !extract32(insn, 7, 1); | ||
186 | - TCGv_ptr fpst = get_fpstatus_ptr(1); | ||
187 | - TCGv_i32 tcg_rmode, tcg_shift; | ||
188 | - int rmode = fp_decode_rm[extract32(insn, 8, 2)]; | ||
189 | - | ||
190 | - tcg_shift = tcg_const_i32(0); | ||
191 | - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | ||
192 | - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, | ||
193 | - cpu_env); | ||
194 | - | ||
195 | - if (is_signed) { | ||
196 | - gen_helper_vfp_tosls(tmp, tmp, | ||
197 | - tcg_shift, fpst); | ||
198 | - } else { | ||
199 | - gen_helper_vfp_touls(tmp, tmp, | ||
200 | - tcg_shift, fpst); | ||
201 | - } | ||
202 | - | ||
203 | - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, | ||
204 | - cpu_env); | ||
205 | - tcg_temp_free_i32(tcg_rmode); | ||
206 | - tcg_temp_free_i32(tcg_shift); | ||
207 | - tcg_temp_free_ptr(fpst); | ||
208 | - break; | ||
209 | - } | ||
210 | default: | ||
211 | /* Reserved op values were caught by the | ||
212 | * neon_2rm_sizes[] check earlier. | ||
213 | -- | 47 | -- |
214 | 2.20.1 | 48 | 2.34.1 |
215 | 49 | ||
216 | 50 | diff view generated by jsdifflib |
1 | Make gen_swap_half() take a source and destination TCGv_i32 rather | 1 | The functions qemu_get_timedate() and qemu_timedate_diff() take |
---|---|---|---|
2 | than modifying the input TCGv_i32; we're going to want to be able to | 2 | and return a time offset as an integer. Coverity points out that |
3 | use it with the more flexible function signature, and this also | 3 | means that when an RTC device implementation holds an offset |
4 | brings it into line with other functions like gen_rev16() and | 4 | as a time_t, as the m48t59 does, the time_t will get truncated. |
5 | gen_revsh(). | 5 | (CID 1507157, 1517772). |
6 | |||
7 | The functions work with time_t internally, so make them use that type | ||
8 | in their APIs. | ||
9 | |||
10 | Note that this won't help any Y2038 issues where either the device | ||
11 | model itself is keeping the offset in a 32-bit integer, or where the | ||
12 | hardware under emulation has Y2038 or other rollover problems. If we | ||
13 | missed any cases of the former then hopefully Coverity will warn us | ||
14 | about them since after this patch we'd be truncating a time_t in | ||
15 | assignments from qemu_timedate_diff().) | ||
6 | 16 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | Message-id: 20200616170844.13318-12-peter.maydell@linaro.org | ||
10 | --- | 19 | --- |
11 | target/arm/translate-neon.inc.c | 2 +- | 20 | include/sysemu/rtc.h | 4 ++-- |
12 | target/arm/translate.c | 10 +++++----- | 21 | softmmu/rtc.c | 4 ++-- |
13 | 2 files changed, 6 insertions(+), 6 deletions(-) | 22 | 2 files changed, 4 insertions(+), 4 deletions(-) |
14 | 23 | ||
15 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 24 | diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h |
16 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-neon.inc.c | 26 | --- a/include/sysemu/rtc.h |
18 | +++ b/target/arm/translate-neon.inc.c | 27 | +++ b/include/sysemu/rtc.h |
19 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) | 28 | @@ -XXX,XX +XXX,XX @@ |
20 | tcg_gen_bswap32_i32(tmp[half], tmp[half]); | 29 | * The behaviour of the clock whose value this function returns will |
21 | break; | 30 | * depend on the -rtc command line option passed by the user. |
22 | case 1: | 31 | */ |
23 | - gen_swap_half(tmp[half]); | 32 | -void qemu_get_timedate(struct tm *tm, int offset); |
24 | + gen_swap_half(tmp[half], tmp[half]); | 33 | +void qemu_get_timedate(struct tm *tm, time_t offset); |
25 | break; | 34 | |
26 | case 2: | 35 | /** |
27 | break; | 36 | * qemu_timedate_diff: Return difference between a struct tm and the RTC |
28 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 37 | @@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset); |
38 | * a timestamp one hour further ahead than the current RTC time | ||
39 | * then this function will return 3600. | ||
40 | */ | ||
41 | -int qemu_timedate_diff(struct tm *tm); | ||
42 | +time_t qemu_timedate_diff(struct tm *tm); | ||
43 | |||
44 | #endif | ||
45 | diff --git a/softmmu/rtc.c b/softmmu/rtc.c | ||
29 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/target/arm/translate.c | 47 | --- a/softmmu/rtc.c |
31 | +++ b/target/arm/translate.c | 48 | +++ b/softmmu/rtc.c |
32 | @@ -XXX,XX +XXX,XX @@ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) | 49 | @@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock) |
50 | return value; | ||
33 | } | 51 | } |
34 | 52 | ||
35 | /* Swap low and high halfwords. */ | 53 | -void qemu_get_timedate(struct tm *tm, int offset) |
36 | -static void gen_swap_half(TCGv_i32 var) | 54 | +void qemu_get_timedate(struct tm *tm, time_t offset) |
37 | +static void gen_swap_half(TCGv_i32 dest, TCGv_i32 var) | ||
38 | { | 55 | { |
39 | - tcg_gen_rotri_i32(var, var, 16); | 56 | time_t ti = qemu_ref_timedate(rtc_clock); |
40 | + tcg_gen_rotri_i32(dest, var, 16); | 57 | |
58 | @@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset) | ||
59 | } | ||
41 | } | 60 | } |
42 | 61 | ||
43 | /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. | 62 | -int qemu_timedate_diff(struct tm *tm) |
44 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 63 | +time_t qemu_timedate_diff(struct tm *tm) |
45 | case NEON_2RM_VREV32: | 64 | { |
46 | switch (size) { | 65 | time_t seconds; |
47 | case 0: tcg_gen_bswap32_i32(tmp, tmp); break; | ||
48 | - case 1: gen_swap_half(tmp); break; | ||
49 | + case 1: gen_swap_half(tmp, tmp); break; | ||
50 | default: abort(); | ||
51 | } | ||
52 | break; | ||
53 | @@ -XXX,XX +XXX,XX @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) | ||
54 | t1 = load_reg(s, a->rn); | ||
55 | t2 = load_reg(s, a->rm); | ||
56 | if (m_swap) { | ||
57 | - gen_swap_half(t2); | ||
58 | + gen_swap_half(t2, t2); | ||
59 | } | ||
60 | gen_smul_dual(t1, t2); | ||
61 | |||
62 | @@ -XXX,XX +XXX,XX @@ static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) | ||
63 | t1 = load_reg(s, a->rn); | ||
64 | t2 = load_reg(s, a->rm); | ||
65 | if (m_swap) { | ||
66 | - gen_swap_half(t2); | ||
67 | + gen_swap_half(t2, t2); | ||
68 | } | ||
69 | gen_smul_dual(t1, t2); | ||
70 | 66 | ||
71 | -- | 67 | -- |
72 | 2.20.1 | 68 | 2.34.1 |
73 | 69 | ||
74 | 70 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the VREV32 and VREV16 insns in the Neon 2-reg-misc group | ||
2 | to decodetree. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20200616170844.13318-13-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/translate.h | 1 + | ||
9 | target/arm/neon-dp.decode | 2 ++ | ||
10 | target/arm/translate-neon.inc.c | 55 +++++++++++++++++++++++++++++++++ | ||
11 | target/arm/translate.c | 12 ++----- | ||
12 | 4 files changed, 60 insertions(+), 10 deletions(-) | ||
13 | |||
14 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/translate.h | ||
17 | +++ b/target/arm/translate.h | ||
18 | @@ -XXX,XX +XXX,XX @@ typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t, | ||
19 | uint32_t, uint32_t, uint32_t); | ||
20 | |||
21 | /* Function prototype for gen_ functions for calling Neon helpers */ | ||
22 | +typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); | ||
23 | typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); | ||
24 | typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); | ||
25 | typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); | ||
26 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/neon-dp.decode | ||
29 | +++ b/target/arm/neon-dp.decode | ||
30 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
31 | &2misc vm=%vm_dp vd=%vd_dp q=1 | ||
32 | |||
33 | VREV64 1111 001 11 . 11 .. 00 .... 0 0000 . . 0 .... @2misc | ||
34 | + VREV32 1111 001 11 . 11 .. 00 .... 0 0001 . . 0 .... @2misc | ||
35 | + VREV16 1111 001 11 . 11 .. 00 .... 0 0010 . . 0 .... @2misc | ||
36 | |||
37 | VPADDL_S 1111 001 11 . 11 .. 00 .... 0 0100 . . 0 .... @2misc | ||
38 | VPADDL_U 1111 001 11 . 11 .. 00 .... 0 0101 . . 0 .... @2misc | ||
39 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/target/arm/translate-neon.inc.c | ||
42 | +++ b/target/arm/translate-neon.inc.c | ||
43 | @@ -XXX,XX +XXX,XX @@ DO_2M_CRYPTO(AESIMC, aa32_aes, 0) | ||
44 | DO_2M_CRYPTO(SHA1H, aa32_sha1, 2) | ||
45 | DO_2M_CRYPTO(SHA1SU1, aa32_sha1, 2) | ||
46 | DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) | ||
47 | + | ||
48 | +static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) | ||
49 | +{ | ||
50 | + int pass; | ||
51 | + | ||
52 | + /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ | ||
53 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
54 | + return false; | ||
55 | + } | ||
56 | + | ||
57 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
58 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
59 | + ((a->vd | a->vm) & 0x10)) { | ||
60 | + return false; | ||
61 | + } | ||
62 | + | ||
63 | + if (!fn) { | ||
64 | + return false; | ||
65 | + } | ||
66 | + | ||
67 | + if ((a->vd | a->vm) & a->q) { | ||
68 | + return false; | ||
69 | + } | ||
70 | + | ||
71 | + if (!vfp_access_check(s)) { | ||
72 | + return true; | ||
73 | + } | ||
74 | + | ||
75 | + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
76 | + TCGv_i32 tmp = neon_load_reg(a->vm, pass); | ||
77 | + fn(tmp, tmp); | ||
78 | + neon_store_reg(a->vd, pass, tmp); | ||
79 | + } | ||
80 | + | ||
81 | + return true; | ||
82 | +} | ||
83 | + | ||
84 | +static bool trans_VREV32(DisasContext *s, arg_2misc *a) | ||
85 | +{ | ||
86 | + static NeonGenOneOpFn * const fn[] = { | ||
87 | + tcg_gen_bswap32_i32, | ||
88 | + gen_swap_half, | ||
89 | + NULL, | ||
90 | + NULL, | ||
91 | + }; | ||
92 | + return do_2misc(s, a, fn[a->size]); | ||
93 | +} | ||
94 | + | ||
95 | +static bool trans_VREV16(DisasContext *s, arg_2misc *a) | ||
96 | +{ | ||
97 | + if (a->size != 0) { | ||
98 | + return false; | ||
99 | + } | ||
100 | + return do_2misc(s, a, gen_rev16); | ||
101 | +} | ||
102 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
103 | index XXXXXXX..XXXXXXX 100644 | ||
104 | --- a/target/arm/translate.c | ||
105 | +++ b/target/arm/translate.c | ||
106 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
107 | case NEON_2RM_AESE: case NEON_2RM_AESMC: | ||
108 | case NEON_2RM_SHA1H: | ||
109 | case NEON_2RM_SHA1SU1: | ||
110 | + case NEON_2RM_VREV32: | ||
111 | + case NEON_2RM_VREV16: | ||
112 | /* handled by decodetree */ | ||
113 | return 1; | ||
114 | case NEON_2RM_VTRN: | ||
115 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
116 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | ||
117 | tmp = neon_load_reg(rm, pass); | ||
118 | switch (op) { | ||
119 | - case NEON_2RM_VREV32: | ||
120 | - switch (size) { | ||
121 | - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; | ||
122 | - case 1: gen_swap_half(tmp, tmp); break; | ||
123 | - default: abort(); | ||
124 | - } | ||
125 | - break; | ||
126 | - case NEON_2RM_VREV16: | ||
127 | - gen_rev16(tmp, tmp); | ||
128 | - break; | ||
129 | case NEON_2RM_VCLS: | ||
130 | switch (size) { | ||
131 | case 0: gen_helper_neon_cls_s8(tmp, tmp); break; | ||
132 | -- | ||
133 | 2.20.1 | ||
134 | |||
135 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the remaining ops in the Neon 2-reg-misc group which | ||
2 | can be implemented simply with our do_2misc() helper. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20200616170844.13318-14-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/neon-dp.decode | 10 +++++ | ||
9 | target/arm/translate-neon.inc.c | 69 +++++++++++++++++++++++++++++++++ | ||
10 | target/arm/translate.c | 38 ++++-------------- | ||
11 | 3 files changed, 86 insertions(+), 31 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/neon-dp.decode | ||
16 | +++ b/target/arm/neon-dp.decode | ||
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
18 | AESMC 1111 001 11 . 11 .. 00 .... 0 0111 0 . 0 .... @2misc_q1 | ||
19 | AESIMC 1111 001 11 . 11 .. 00 .... 0 0111 1 . 0 .... @2misc_q1 | ||
20 | |||
21 | + VCLS 1111 001 11 . 11 .. 00 .... 0 1000 . . 0 .... @2misc | ||
22 | + VCLZ 1111 001 11 . 11 .. 00 .... 0 1001 . . 0 .... @2misc | ||
23 | + VCNT 1111 001 11 . 11 .. 00 .... 0 1010 . . 0 .... @2misc | ||
24 | + | ||
25 | VMVN 1111 001 11 . 11 .. 00 .... 0 1011 . . 0 .... @2misc | ||
26 | |||
27 | VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc | ||
28 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
29 | VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc | ||
30 | VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc | ||
31 | |||
32 | + VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc | ||
33 | + VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc | ||
34 | + | ||
35 | VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc | ||
36 | VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc | ||
37 | |||
38 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
39 | |||
40 | VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 | ||
41 | VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 | ||
42 | + | ||
43 | + VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc | ||
44 | + VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc | ||
45 | ] | ||
46 | |||
47 | # Subgroup for size != 0b11 | ||
48 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/translate-neon.inc.c | ||
51 | +++ b/target/arm/translate-neon.inc.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV16(DisasContext *s, arg_2misc *a) | ||
53 | } | ||
54 | return do_2misc(s, a, gen_rev16); | ||
55 | } | ||
56 | + | ||
57 | +static bool trans_VCLS(DisasContext *s, arg_2misc *a) | ||
58 | +{ | ||
59 | + static NeonGenOneOpFn * const fn[] = { | ||
60 | + gen_helper_neon_cls_s8, | ||
61 | + gen_helper_neon_cls_s16, | ||
62 | + gen_helper_neon_cls_s32, | ||
63 | + NULL, | ||
64 | + }; | ||
65 | + return do_2misc(s, a, fn[a->size]); | ||
66 | +} | ||
67 | + | ||
68 | +static void do_VCLZ_32(TCGv_i32 rd, TCGv_i32 rm) | ||
69 | +{ | ||
70 | + tcg_gen_clzi_i32(rd, rm, 32); | ||
71 | +} | ||
72 | + | ||
73 | +static bool trans_VCLZ(DisasContext *s, arg_2misc *a) | ||
74 | +{ | ||
75 | + static NeonGenOneOpFn * const fn[] = { | ||
76 | + gen_helper_neon_clz_u8, | ||
77 | + gen_helper_neon_clz_u16, | ||
78 | + do_VCLZ_32, | ||
79 | + NULL, | ||
80 | + }; | ||
81 | + return do_2misc(s, a, fn[a->size]); | ||
82 | +} | ||
83 | + | ||
84 | +static bool trans_VCNT(DisasContext *s, arg_2misc *a) | ||
85 | +{ | ||
86 | + if (a->size != 0) { | ||
87 | + return false; | ||
88 | + } | ||
89 | + return do_2misc(s, a, gen_helper_neon_cnt_u8); | ||
90 | +} | ||
91 | + | ||
92 | +static bool trans_VABS_F(DisasContext *s, arg_2misc *a) | ||
93 | +{ | ||
94 | + if (a->size != 2) { | ||
95 | + return false; | ||
96 | + } | ||
97 | + /* TODO: FP16 : size == 1 */ | ||
98 | + return do_2misc(s, a, gen_helper_vfp_abss); | ||
99 | +} | ||
100 | + | ||
101 | +static bool trans_VNEG_F(DisasContext *s, arg_2misc *a) | ||
102 | +{ | ||
103 | + if (a->size != 2) { | ||
104 | + return false; | ||
105 | + } | ||
106 | + /* TODO: FP16 : size == 1 */ | ||
107 | + return do_2misc(s, a, gen_helper_vfp_negs); | ||
108 | +} | ||
109 | + | ||
110 | +static bool trans_VRECPE(DisasContext *s, arg_2misc *a) | ||
111 | +{ | ||
112 | + if (a->size != 2) { | ||
113 | + return false; | ||
114 | + } | ||
115 | + return do_2misc(s, a, gen_helper_recpe_u32); | ||
116 | +} | ||
117 | + | ||
118 | +static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a) | ||
119 | +{ | ||
120 | + if (a->size != 2) { | ||
121 | + return false; | ||
122 | + } | ||
123 | + return do_2misc(s, a, gen_helper_rsqrte_u32); | ||
124 | +} | ||
125 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
126 | index XXXXXXX..XXXXXXX 100644 | ||
127 | --- a/target/arm/translate.c | ||
128 | +++ b/target/arm/translate.c | ||
129 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
130 | case NEON_2RM_SHA1SU1: | ||
131 | case NEON_2RM_VREV32: | ||
132 | case NEON_2RM_VREV16: | ||
133 | + case NEON_2RM_VCLS: | ||
134 | + case NEON_2RM_VCLZ: | ||
135 | + case NEON_2RM_VCNT: | ||
136 | + case NEON_2RM_VABS_F: | ||
137 | + case NEON_2RM_VNEG_F: | ||
138 | + case NEON_2RM_VRECPE: | ||
139 | + case NEON_2RM_VRSQRTE: | ||
140 | /* handled by decodetree */ | ||
141 | return 1; | ||
142 | case NEON_2RM_VTRN: | ||
143 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
144 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | ||
145 | tmp = neon_load_reg(rm, pass); | ||
146 | switch (op) { | ||
147 | - case NEON_2RM_VCLS: | ||
148 | - switch (size) { | ||
149 | - case 0: gen_helper_neon_cls_s8(tmp, tmp); break; | ||
150 | - case 1: gen_helper_neon_cls_s16(tmp, tmp); break; | ||
151 | - case 2: gen_helper_neon_cls_s32(tmp, tmp); break; | ||
152 | - default: abort(); | ||
153 | - } | ||
154 | - break; | ||
155 | - case NEON_2RM_VCLZ: | ||
156 | - switch (size) { | ||
157 | - case 0: gen_helper_neon_clz_u8(tmp, tmp); break; | ||
158 | - case 1: gen_helper_neon_clz_u16(tmp, tmp); break; | ||
159 | - case 2: tcg_gen_clzi_i32(tmp, tmp, 32); break; | ||
160 | - default: abort(); | ||
161 | - } | ||
162 | - break; | ||
163 | - case NEON_2RM_VCNT: | ||
164 | - gen_helper_neon_cnt_u8(tmp, tmp); | ||
165 | - break; | ||
166 | case NEON_2RM_VQABS: | ||
167 | switch (size) { | ||
168 | case 0: | ||
169 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
170 | tcg_temp_free_ptr(fpstatus); | ||
171 | break; | ||
172 | } | ||
173 | - case NEON_2RM_VABS_F: | ||
174 | - gen_helper_vfp_abss(tmp, tmp); | ||
175 | - break; | ||
176 | - case NEON_2RM_VNEG_F: | ||
177 | - gen_helper_vfp_negs(tmp, tmp); | ||
178 | - break; | ||
179 | case NEON_2RM_VSWP: | ||
180 | tmp2 = neon_load_reg(rd, pass); | ||
181 | neon_store_reg(rm, pass, tmp2); | ||
182 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
183 | tcg_temp_free_ptr(fpst); | ||
184 | break; | ||
185 | } | ||
186 | - case NEON_2RM_VRECPE: | ||
187 | - gen_helper_recpe_u32(tmp, tmp); | ||
188 | - break; | ||
189 | - case NEON_2RM_VRSQRTE: | ||
190 | - gen_helper_rsqrte_u32(tmp, tmp); | ||
191 | - break; | ||
192 | case NEON_2RM_VRECPE_F: | ||
193 | { | ||
194 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
195 | -- | ||
196 | 2.20.1 | ||
197 | |||
198 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the Neon VQABS and VQNEG insns to decodetree. | ||
2 | Since these are the only ones which need cpu_env passing to | ||
3 | the helper, we wrap the helper rather than creating a whole | ||
4 | new do_2misc_env() function. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20200616170844.13318-15-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/neon-dp.decode | 3 +++ | ||
11 | target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++ | ||
12 | target/arm/translate.c | 30 ++-------------------------- | ||
13 | 3 files changed, 40 insertions(+), 28 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/neon-dp.decode | ||
18 | +++ b/target/arm/neon-dp.decode | ||
19 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
20 | VPADAL_S 1111 001 11 . 11 .. 00 .... 0 1100 . . 0 .... @2misc | ||
21 | VPADAL_U 1111 001 11 . 11 .. 00 .... 0 1101 . . 0 .... @2misc | ||
22 | |||
23 | + VQABS 1111 001 11 . 11 .. 00 .... 0 1110 . . 0 .... @2misc | ||
24 | + VQNEG 1111 001 11 . 11 .. 00 .... 0 1111 . . 0 .... @2misc | ||
25 | + | ||
26 | VCGT0 1111 001 11 . 11 .. 01 .... 0 0000 . . 0 .... @2misc | ||
27 | VCGE0 1111 001 11 . 11 .. 01 .... 0 0001 . . 0 .... @2misc | ||
28 | VCEQ0 1111 001 11 . 11 .. 01 .... 0 0010 . . 0 .... @2misc | ||
29 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/translate-neon.inc.c | ||
32 | +++ b/target/arm/translate-neon.inc.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRSQRTE(DisasContext *s, arg_2misc *a) | ||
34 | } | ||
35 | return do_2misc(s, a, gen_helper_rsqrte_u32); | ||
36 | } | ||
37 | + | ||
38 | +#define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \ | ||
39 | + static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \ | ||
40 | + { \ | ||
41 | + FUNC(d, cpu_env, m); \ | ||
42 | + } | ||
43 | + | ||
44 | +WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8) | ||
45 | +WRAP_1OP_ENV_FN(gen_VQABS_s16, gen_helper_neon_qabs_s16) | ||
46 | +WRAP_1OP_ENV_FN(gen_VQABS_s32, gen_helper_neon_qabs_s32) | ||
47 | +WRAP_1OP_ENV_FN(gen_VQNEG_s8, gen_helper_neon_qneg_s8) | ||
48 | +WRAP_1OP_ENV_FN(gen_VQNEG_s16, gen_helper_neon_qneg_s16) | ||
49 | +WRAP_1OP_ENV_FN(gen_VQNEG_s32, gen_helper_neon_qneg_s32) | ||
50 | + | ||
51 | +static bool trans_VQABS(DisasContext *s, arg_2misc *a) | ||
52 | +{ | ||
53 | + static NeonGenOneOpFn * const fn[] = { | ||
54 | + gen_VQABS_s8, | ||
55 | + gen_VQABS_s16, | ||
56 | + gen_VQABS_s32, | ||
57 | + NULL, | ||
58 | + }; | ||
59 | + return do_2misc(s, a, fn[a->size]); | ||
60 | +} | ||
61 | + | ||
62 | +static bool trans_VQNEG(DisasContext *s, arg_2misc *a) | ||
63 | +{ | ||
64 | + static NeonGenOneOpFn * const fn[] = { | ||
65 | + gen_VQNEG_s8, | ||
66 | + gen_VQNEG_s16, | ||
67 | + gen_VQNEG_s32, | ||
68 | + NULL, | ||
69 | + }; | ||
70 | + return do_2misc(s, a, fn[a->size]); | ||
71 | +} | ||
72 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/target/arm/translate.c | ||
75 | +++ b/target/arm/translate.c | ||
76 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
77 | case NEON_2RM_VNEG_F: | ||
78 | case NEON_2RM_VRECPE: | ||
79 | case NEON_2RM_VRSQRTE: | ||
80 | + case NEON_2RM_VQABS: | ||
81 | + case NEON_2RM_VQNEG: | ||
82 | /* handled by decodetree */ | ||
83 | return 1; | ||
84 | case NEON_2RM_VTRN: | ||
85 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
86 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | ||
87 | tmp = neon_load_reg(rm, pass); | ||
88 | switch (op) { | ||
89 | - case NEON_2RM_VQABS: | ||
90 | - switch (size) { | ||
91 | - case 0: | ||
92 | - gen_helper_neon_qabs_s8(tmp, cpu_env, tmp); | ||
93 | - break; | ||
94 | - case 1: | ||
95 | - gen_helper_neon_qabs_s16(tmp, cpu_env, tmp); | ||
96 | - break; | ||
97 | - case 2: | ||
98 | - gen_helper_neon_qabs_s32(tmp, cpu_env, tmp); | ||
99 | - break; | ||
100 | - default: abort(); | ||
101 | - } | ||
102 | - break; | ||
103 | - case NEON_2RM_VQNEG: | ||
104 | - switch (size) { | ||
105 | - case 0: | ||
106 | - gen_helper_neon_qneg_s8(tmp, cpu_env, tmp); | ||
107 | - break; | ||
108 | - case 1: | ||
109 | - gen_helper_neon_qneg_s16(tmp, cpu_env, tmp); | ||
110 | - break; | ||
111 | - case 2: | ||
112 | - gen_helper_neon_qneg_s32(tmp, cpu_env, tmp); | ||
113 | - break; | ||
114 | - default: abort(); | ||
115 | - } | ||
116 | - break; | ||
117 | case NEON_2RM_VCGT0_F: | ||
118 | { | ||
119 | TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
120 | -- | ||
121 | 2.20.1 | ||
122 | |||
123 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the Neon 2-reg-misc insns which are implemented with | ||
2 | simple calls to functions that take the input, output and | ||
3 | fpstatus pointer. | ||
4 | 1 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20200616170844.13318-16-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/translate.h | 1 + | ||
10 | target/arm/neon-dp.decode | 8 +++++ | ||
11 | target/arm/translate-neon.inc.c | 62 +++++++++++++++++++++++++++++++++ | ||
12 | target/arm/translate.c | 56 ++++------------------------- | ||
13 | 4 files changed, 78 insertions(+), 49 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate.h | ||
18 | +++ b/target/arm/translate.h | ||
19 | @@ -XXX,XX +XXX,XX @@ typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); | ||
20 | typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); | ||
21 | typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); | ||
22 | typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); | ||
23 | +typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr); | ||
24 | typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); | ||
25 | typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | ||
26 | typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); | ||
27 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/neon-dp.decode | ||
30 | +++ b/target/arm/neon-dp.decode | ||
31 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
32 | SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1 | ||
33 | SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1 | ||
34 | |||
35 | + VRINTX 1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc | ||
36 | + | ||
37 | VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 | ||
38 | VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 | ||
39 | |||
40 | VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc | ||
41 | VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc | ||
42 | + VRECPE_F 1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc | ||
43 | + VRSQRTE_F 1111 001 11 . 11 .. 11 .... 0 1011 . . 0 .... @2misc | ||
44 | + VCVT_FS 1111 001 11 . 11 .. 11 .... 0 1100 . . 0 .... @2misc | ||
45 | + VCVT_FU 1111 001 11 . 11 .. 11 .... 0 1101 . . 0 .... @2misc | ||
46 | + VCVT_SF 1111 001 11 . 11 .. 11 .... 0 1110 . . 0 .... @2misc | ||
47 | + VCVT_UF 1111 001 11 . 11 .. 11 .... 0 1111 . . 0 .... @2misc | ||
48 | ] | ||
49 | |||
50 | # Subgroup for size != 0b11 | ||
51 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/target/arm/translate-neon.inc.c | ||
54 | +++ b/target/arm/translate-neon.inc.c | ||
55 | @@ -XXX,XX +XXX,XX @@ static bool trans_VQNEG(DisasContext *s, arg_2misc *a) | ||
56 | }; | ||
57 | return do_2misc(s, a, fn[a->size]); | ||
58 | } | ||
59 | + | ||
60 | +static bool do_2misc_fp(DisasContext *s, arg_2misc *a, | ||
61 | + NeonGenOneSingleOpFn *fn) | ||
62 | +{ | ||
63 | + int pass; | ||
64 | + TCGv_ptr fpst; | ||
65 | + | ||
66 | + /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ | ||
67 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
68 | + return false; | ||
69 | + } | ||
70 | + | ||
71 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
72 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
73 | + ((a->vd | a->vm) & 0x10)) { | ||
74 | + return false; | ||
75 | + } | ||
76 | + | ||
77 | + if (a->size != 2) { | ||
78 | + /* TODO: FP16 will be the size == 1 case */ | ||
79 | + return false; | ||
80 | + } | ||
81 | + | ||
82 | + if ((a->vd | a->vm) & a->q) { | ||
83 | + return false; | ||
84 | + } | ||
85 | + | ||
86 | + if (!vfp_access_check(s)) { | ||
87 | + return true; | ||
88 | + } | ||
89 | + | ||
90 | + fpst = get_fpstatus_ptr(1); | ||
91 | + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | ||
92 | + TCGv_i32 tmp = neon_load_reg(a->vm, pass); | ||
93 | + fn(tmp, tmp, fpst); | ||
94 | + neon_store_reg(a->vd, pass, tmp); | ||
95 | + } | ||
96 | + tcg_temp_free_ptr(fpst); | ||
97 | + | ||
98 | + return true; | ||
99 | +} | ||
100 | + | ||
101 | +#define DO_2MISC_FP(INSN, FUNC) \ | ||
102 | + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ | ||
103 | + { \ | ||
104 | + return do_2misc_fp(s, a, FUNC); \ | ||
105 | + } | ||
106 | + | ||
107 | +DO_2MISC_FP(VRECPE_F, gen_helper_recpe_f32) | ||
108 | +DO_2MISC_FP(VRSQRTE_F, gen_helper_rsqrte_f32) | ||
109 | +DO_2MISC_FP(VCVT_FS, gen_helper_vfp_sitos) | ||
110 | +DO_2MISC_FP(VCVT_FU, gen_helper_vfp_uitos) | ||
111 | +DO_2MISC_FP(VCVT_SF, gen_helper_vfp_tosizs) | ||
112 | +DO_2MISC_FP(VCVT_UF, gen_helper_vfp_touizs) | ||
113 | + | ||
114 | +static bool trans_VRINTX(DisasContext *s, arg_2misc *a) | ||
115 | +{ | ||
116 | + if (!arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
117 | + return false; | ||
118 | + } | ||
119 | + return do_2misc_fp(s, a, gen_helper_rints_exact); | ||
120 | +} | ||
121 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
122 | index XXXXXXX..XXXXXXX 100644 | ||
123 | --- a/target/arm/translate.c | ||
124 | +++ b/target/arm/translate.c | ||
125 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
126 | case NEON_2RM_VRSQRTE: | ||
127 | case NEON_2RM_VQABS: | ||
128 | case NEON_2RM_VQNEG: | ||
129 | + case NEON_2RM_VRECPE_F: | ||
130 | + case NEON_2RM_VRSQRTE_F: | ||
131 | + case NEON_2RM_VCVT_FS: | ||
132 | + case NEON_2RM_VCVT_FU: | ||
133 | + case NEON_2RM_VCVT_SF: | ||
134 | + case NEON_2RM_VCVT_UF: | ||
135 | + case NEON_2RM_VRINTX: | ||
136 | /* handled by decodetree */ | ||
137 | return 1; | ||
138 | case NEON_2RM_VTRN: | ||
139 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
140 | tcg_temp_free_i32(tcg_rmode); | ||
141 | break; | ||
142 | } | ||
143 | - case NEON_2RM_VRINTX: | ||
144 | - { | ||
145 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
146 | - gen_helper_rints_exact(tmp, tmp, fpstatus); | ||
147 | - tcg_temp_free_ptr(fpstatus); | ||
148 | - break; | ||
149 | - } | ||
150 | case NEON_2RM_VCVTAU: | ||
151 | case NEON_2RM_VCVTAS: | ||
152 | case NEON_2RM_VCVTNU: | ||
153 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
154 | tcg_temp_free_ptr(fpst); | ||
155 | break; | ||
156 | } | ||
157 | - case NEON_2RM_VRECPE_F: | ||
158 | - { | ||
159 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
160 | - gen_helper_recpe_f32(tmp, tmp, fpstatus); | ||
161 | - tcg_temp_free_ptr(fpstatus); | ||
162 | - break; | ||
163 | - } | ||
164 | - case NEON_2RM_VRSQRTE_F: | ||
165 | - { | ||
166 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
167 | - gen_helper_rsqrte_f32(tmp, tmp, fpstatus); | ||
168 | - tcg_temp_free_ptr(fpstatus); | ||
169 | - break; | ||
170 | - } | ||
171 | - case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */ | ||
172 | - { | ||
173 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
174 | - gen_helper_vfp_sitos(tmp, tmp, fpstatus); | ||
175 | - tcg_temp_free_ptr(fpstatus); | ||
176 | - break; | ||
177 | - } | ||
178 | - case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */ | ||
179 | - { | ||
180 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
181 | - gen_helper_vfp_uitos(tmp, tmp, fpstatus); | ||
182 | - tcg_temp_free_ptr(fpstatus); | ||
183 | - break; | ||
184 | - } | ||
185 | - case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */ | ||
186 | - { | ||
187 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
188 | - gen_helper_vfp_tosizs(tmp, tmp, fpstatus); | ||
189 | - tcg_temp_free_ptr(fpstatus); | ||
190 | - break; | ||
191 | - } | ||
192 | - case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */ | ||
193 | - { | ||
194 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
195 | - gen_helper_vfp_touizs(tmp, tmp, fpstatus); | ||
196 | - tcg_temp_free_ptr(fpstatus); | ||
197 | - break; | ||
198 | - } | ||
199 | default: | ||
200 | /* Reserved op values were caught by the | ||
201 | * neon_2rm_sizes[] check earlier. | ||
202 | -- | ||
203 | 2.20.1 | ||
204 | |||
205 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | Convert the fp-compare-with-zero insns in the Neon 2-reg-misc group to | ||
2 | decodetree. | ||
3 | 1 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20200616170844.13318-17-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/neon-dp.decode | 6 ++++ | ||
9 | target/arm/translate-neon.inc.c | 28 ++++++++++++++++++ | ||
10 | target/arm/translate.c | 50 ++++----------------------------- | ||
11 | 3 files changed, 39 insertions(+), 45 deletions(-) | ||
12 | |||
13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/neon-dp.decode | ||
16 | +++ b/target/arm/neon-dp.decode | ||
17 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | ||
18 | VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc | ||
19 | VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc | ||
20 | |||
21 | + VCGT0_F 1111 001 11 . 11 .. 01 .... 0 1000 . . 0 .... @2misc | ||
22 | + VCGE0_F 1111 001 11 . 11 .. 01 .... 0 1001 . . 0 .... @2misc | ||
23 | + VCEQ0_F 1111 001 11 . 11 .. 01 .... 0 1010 . . 0 .... @2misc | ||
24 | + VCLE0_F 1111 001 11 . 11 .. 01 .... 0 1011 . . 0 .... @2misc | ||
25 | + VCLT0_F 1111 001 11 . 11 .. 01 .... 0 1100 . . 0 .... @2misc | ||
26 | + | ||
27 | VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc | ||
28 | VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc | ||
29 | |||
30 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/translate-neon.inc.c | ||
33 | +++ b/target/arm/translate-neon.inc.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRINTX(DisasContext *s, arg_2misc *a) | ||
35 | } | ||
36 | return do_2misc_fp(s, a, gen_helper_rints_exact); | ||
37 | } | ||
38 | + | ||
39 | +#define WRAP_FP_CMP0_FWD(WRAPNAME, FUNC) \ | ||
40 | + static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \ | ||
41 | + { \ | ||
42 | + TCGv_i32 zero = tcg_const_i32(0); \ | ||
43 | + FUNC(d, m, zero, fpst); \ | ||
44 | + tcg_temp_free_i32(zero); \ | ||
45 | + } | ||
46 | +#define WRAP_FP_CMP0_REV(WRAPNAME, FUNC) \ | ||
47 | + static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \ | ||
48 | + { \ | ||
49 | + TCGv_i32 zero = tcg_const_i32(0); \ | ||
50 | + FUNC(d, zero, m, fpst); \ | ||
51 | + tcg_temp_free_i32(zero); \ | ||
52 | + } | ||
53 | + | ||
54 | +#define DO_FP_CMP0(INSN, FUNC, REV) \ | ||
55 | + WRAP_FP_CMP0_##REV(gen_##INSN, FUNC) \ | ||
56 | + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ | ||
57 | + { \ | ||
58 | + return do_2misc_fp(s, a, gen_##INSN); \ | ||
59 | + } | ||
60 | + | ||
61 | +DO_FP_CMP0(VCGT0_F, gen_helper_neon_cgt_f32, FWD) | ||
62 | +DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD) | ||
63 | +DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD) | ||
64 | +DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV) | ||
65 | +DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV) | ||
66 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/translate.c | ||
69 | +++ b/target/arm/translate.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
71 | case NEON_2RM_VCVT_SF: | ||
72 | case NEON_2RM_VCVT_UF: | ||
73 | case NEON_2RM_VRINTX: | ||
74 | + case NEON_2RM_VCGT0_F: | ||
75 | + case NEON_2RM_VCGE0_F: | ||
76 | + case NEON_2RM_VCEQ0_F: | ||
77 | + case NEON_2RM_VCLE0_F: | ||
78 | + case NEON_2RM_VCLT0_F: | ||
79 | /* handled by decodetree */ | ||
80 | return 1; | ||
81 | case NEON_2RM_VTRN: | ||
82 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
83 | for (pass = 0; pass < (q ? 4 : 2); pass++) { | ||
84 | tmp = neon_load_reg(rm, pass); | ||
85 | switch (op) { | ||
86 | - case NEON_2RM_VCGT0_F: | ||
87 | - { | ||
88 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
89 | - tmp2 = tcg_const_i32(0); | ||
90 | - gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstatus); | ||
91 | - tcg_temp_free_i32(tmp2); | ||
92 | - tcg_temp_free_ptr(fpstatus); | ||
93 | - break; | ||
94 | - } | ||
95 | - case NEON_2RM_VCGE0_F: | ||
96 | - { | ||
97 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
98 | - tmp2 = tcg_const_i32(0); | ||
99 | - gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstatus); | ||
100 | - tcg_temp_free_i32(tmp2); | ||
101 | - tcg_temp_free_ptr(fpstatus); | ||
102 | - break; | ||
103 | - } | ||
104 | - case NEON_2RM_VCEQ0_F: | ||
105 | - { | ||
106 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
107 | - tmp2 = tcg_const_i32(0); | ||
108 | - gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstatus); | ||
109 | - tcg_temp_free_i32(tmp2); | ||
110 | - tcg_temp_free_ptr(fpstatus); | ||
111 | - break; | ||
112 | - } | ||
113 | - case NEON_2RM_VCLE0_F: | ||
114 | - { | ||
115 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
116 | - tmp2 = tcg_const_i32(0); | ||
117 | - gen_helper_neon_cge_f32(tmp, tmp2, tmp, fpstatus); | ||
118 | - tcg_temp_free_i32(tmp2); | ||
119 | - tcg_temp_free_ptr(fpstatus); | ||
120 | - break; | ||
121 | - } | ||
122 | - case NEON_2RM_VCLT0_F: | ||
123 | - { | ||
124 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | ||
125 | - tmp2 = tcg_const_i32(0); | ||
126 | - gen_helper_neon_cgt_f32(tmp, tmp2, tmp, fpstatus); | ||
127 | - tcg_temp_free_i32(tmp2); | ||
128 | - tcg_temp_free_ptr(fpstatus); | ||
129 | - break; | ||
130 | - } | ||
131 | case NEON_2RM_VSWP: | ||
132 | tmp2 = neon_load_reg(rd, pass); | ||
133 | neon_store_reg(rm, pass, tmp2); | ||
134 | -- | ||
135 | 2.20.1 | ||
136 | |||
137 | diff view generated by jsdifflib |
1 | Convert the Neon 2-reg-misc VRINT insns to decodetree. | 1 | Where architecturally one ARM_FEATURE_X flag implies another |
---|---|---|---|
2 | Giving these insns their own do_vrint() function allows us | 2 | ARM_FEATURE_Y, we allow the CPU init function to only set X, and then |
3 | to change the rounding mode just once at the start and end | 3 | set Y for it. Currently we do this in two places -- we set a few |
4 | rather than doing it for every element in the vector. | 4 | flags in arm_cpu_post_init() because we need them to decide which |
5 | properties to create on the CPU object, and then we do the rest in | ||
6 | arm_cpu_realizefn(). However, this is fragile, because it's easy to | ||
7 | add a new property and not notice that this means that an X-implies-Y | ||
8 | check now has to move from realize to post-init. | ||
9 | |||
10 | As a specific example, the pmsav7-dregion property is conditional | ||
11 | on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear | ||
12 | on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and | ||
13 | rely on V8-implies-V7, which doesn't happen until the realizefn. | ||
14 | |||
15 | Move all of these X-implies-Y checks into a new function, which | ||
16 | we call at the top of arm_cpu_post_init(), so the feature bits | ||
17 | are available at that point. | ||
18 | |||
19 | This does now give us the reverse issue, that if there's a feature | ||
20 | bit which is enabled or disabled by the setting of a property then | ||
21 | then X-implies-Y features that are dependent on that property need to | ||
22 | be in realize, not in this new function. But the only one of those | ||
23 | is the "EL3 implies VBAR" which is already in the right place, so | ||
24 | putting things this way round seems better to me. | ||
5 | 25 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 27 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20200616170844.13318-18-peter.maydell@linaro.org | 28 | Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org |
9 | --- | 29 | --- |
10 | target/arm/neon-dp.decode | 8 +++++ | 30 | target/arm/cpu.c | 179 +++++++++++++++++++++++++---------------------- |
11 | target/arm/translate-neon.inc.c | 61 +++++++++++++++++++++++++++++++++ | 31 | 1 file changed, 97 insertions(+), 82 deletions(-) |
12 | target/arm/translate.c | 31 +++-------------- | 32 | |
13 | 3 files changed, 74 insertions(+), 26 deletions(-) | 33 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
14 | |||
15 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
16 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/neon-dp.decode | 35 | --- a/target/arm/cpu.c |
18 | +++ b/target/arm/neon-dp.decode | 36 | +++ b/target/arm/cpu.c |
19 | @@ -XXX,XX +XXX,XX @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm | 37 | @@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) |
20 | SHA1SU1 1111 001 11 . 11 .. 10 .... 0 0111 0 . 0 .... @2misc_q1 | 38 | NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; |
21 | SHA256SU0 1111 001 11 . 11 .. 10 .... 0 0111 1 . 0 .... @2misc_q1 | 39 | } |
22 | 40 | ||
23 | + VRINTN 1111 001 11 . 11 .. 10 .... 0 1000 . . 0 .... @2misc | 41 | +static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) |
24 | VRINTX 1111 001 11 . 11 .. 10 .... 0 1001 . . 0 .... @2misc | ||
25 | + VRINTA 1111 001 11 . 11 .. 10 .... 0 1010 . . 0 .... @2misc | ||
26 | + VRINTZ 1111 001 11 . 11 .. 10 .... 0 1011 . . 0 .... @2misc | ||
27 | |||
28 | VCVT_F16_F32 1111 001 11 . 11 .. 10 .... 0 1100 0 . 0 .... @2misc_q0 | ||
29 | + | ||
30 | + VRINTM 1111 001 11 . 11 .. 10 .... 0 1101 . . 0 .... @2misc | ||
31 | + | ||
32 | VCVT_F32_F16 1111 001 11 . 11 .. 10 .... 0 1110 0 . 0 .... @2misc_q0 | ||
33 | |||
34 | + VRINTP 1111 001 11 . 11 .. 10 .... 0 1111 . . 0 .... @2misc | ||
35 | + | ||
36 | VRECPE 1111 001 11 . 11 .. 11 .... 0 1000 . . 0 .... @2misc | ||
37 | VRSQRTE 1111 001 11 . 11 .. 11 .... 0 1001 . . 0 .... @2misc | ||
38 | VRECPE_F 1111 001 11 . 11 .. 11 .... 0 1010 . . 0 .... @2misc | ||
39 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/target/arm/translate-neon.inc.c | ||
42 | +++ b/target/arm/translate-neon.inc.c | ||
43 | @@ -XXX,XX +XXX,XX @@ DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD) | ||
44 | DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD) | ||
45 | DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV) | ||
46 | DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV) | ||
47 | + | ||
48 | +static bool do_vrint(DisasContext *s, arg_2misc *a, int rmode) | ||
49 | +{ | 42 | +{ |
43 | + CPUARMState *env = &cpu->env; | ||
44 | + bool no_aa32 = false; | ||
45 | + | ||
50 | + /* | 46 | + /* |
51 | + * Handle a VRINT* operation by iterating 32 bits at a time, | 47 | + * Some features automatically imply others: set the feature |
52 | + * with a specified rounding mode in operation. | 48 | + * bits explicitly for these cases. |
53 | + */ | 49 | + */ |
54 | + int pass; | 50 | + |
55 | + TCGv_ptr fpst; | 51 | + if (arm_feature(env, ARM_FEATURE_M)) { |
56 | + TCGv_i32 tcg_rmode; | 52 | + set_feature(env, ARM_FEATURE_PMSA); |
57 | + | 53 | + } |
58 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON) || | 54 | + |
59 | + !arm_dc_feature(s, ARM_FEATURE_V8)) { | 55 | + if (arm_feature(env, ARM_FEATURE_V8)) { |
60 | + return false; | 56 | + if (arm_feature(env, ARM_FEATURE_M)) { |
61 | + } | 57 | + set_feature(env, ARM_FEATURE_V7); |
62 | + | 58 | + } else { |
63 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | 59 | + set_feature(env, ARM_FEATURE_V7VE); |
64 | + if (!dc_isar_feature(aa32_simd_r32, s) && | 60 | + } |
65 | + ((a->vd | a->vm) & 0x10)) { | 61 | + } |
66 | + return false; | 62 | + |
67 | + } | 63 | + /* |
68 | + | 64 | + * There exist AArch64 cpus without AArch32 support. When KVM |
69 | + if (a->size != 2) { | 65 | + * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. |
70 | + /* TODO: FP16 will be the size == 1 case */ | 66 | + * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. |
71 | + return false; | 67 | + * As a general principle, we also do not make ID register |
72 | + } | 68 | + * consistency checks anywhere unless using TCG, because only |
73 | + | 69 | + * for TCG would a consistency-check failure be a QEMU bug. |
74 | + if ((a->vd | a->vm) & a->q) { | 70 | + */ |
75 | + return false; | 71 | + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
76 | + } | 72 | + no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); |
77 | + | 73 | + } |
78 | + if (!vfp_access_check(s)) { | 74 | + |
79 | + return true; | 75 | + if (arm_feature(env, ARM_FEATURE_V7VE)) { |
80 | + } | 76 | + /* |
81 | + | 77 | + * v7 Virtualization Extensions. In real hardware this implies |
82 | + fpst = get_fpstatus_ptr(1); | 78 | + * EL2 and also the presence of the Security Extensions. |
83 | + tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | 79 | + * For QEMU, for backwards-compatibility we implement some |
84 | + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); | 80 | + * CPUs or CPU configs which have no actual EL2 or EL3 but do |
85 | + for (pass = 0; pass < (a->q ? 4 : 2); pass++) { | 81 | + * include the various other features that V7VE implies. |
86 | + TCGv_i32 tmp = neon_load_reg(a->vm, pass); | 82 | + * Presence of EL2 itself is ARM_FEATURE_EL2, and of the |
87 | + gen_helper_rints(tmp, tmp, fpst); | 83 | + * Security Extensions is ARM_FEATURE_EL3. |
88 | + neon_store_reg(a->vd, pass, tmp); | 84 | + */ |
89 | + } | 85 | + assert(!tcg_enabled() || no_aa32 || |
90 | + gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, cpu_env); | 86 | + cpu_isar_feature(aa32_arm_div, cpu)); |
91 | + tcg_temp_free_i32(tcg_rmode); | 87 | + set_feature(env, ARM_FEATURE_LPAE); |
92 | + tcg_temp_free_ptr(fpst); | 88 | + set_feature(env, ARM_FEATURE_V7); |
93 | + | 89 | + } |
94 | + return true; | 90 | + if (arm_feature(env, ARM_FEATURE_V7)) { |
91 | + set_feature(env, ARM_FEATURE_VAPA); | ||
92 | + set_feature(env, ARM_FEATURE_THUMB2); | ||
93 | + set_feature(env, ARM_FEATURE_MPIDR); | ||
94 | + if (!arm_feature(env, ARM_FEATURE_M)) { | ||
95 | + set_feature(env, ARM_FEATURE_V6K); | ||
96 | + } else { | ||
97 | + set_feature(env, ARM_FEATURE_V6); | ||
98 | + } | ||
99 | + | ||
100 | + /* | ||
101 | + * Always define VBAR for V7 CPUs even if it doesn't exist in | ||
102 | + * non-EL3 configs. This is needed by some legacy boards. | ||
103 | + */ | ||
104 | + set_feature(env, ARM_FEATURE_VBAR); | ||
105 | + } | ||
106 | + if (arm_feature(env, ARM_FEATURE_V6K)) { | ||
107 | + set_feature(env, ARM_FEATURE_V6); | ||
108 | + set_feature(env, ARM_FEATURE_MVFR); | ||
109 | + } | ||
110 | + if (arm_feature(env, ARM_FEATURE_V6)) { | ||
111 | + set_feature(env, ARM_FEATURE_V5); | ||
112 | + if (!arm_feature(env, ARM_FEATURE_M)) { | ||
113 | + assert(!tcg_enabled() || no_aa32 || | ||
114 | + cpu_isar_feature(aa32_jazelle, cpu)); | ||
115 | + set_feature(env, ARM_FEATURE_AUXCR); | ||
116 | + } | ||
117 | + } | ||
118 | + if (arm_feature(env, ARM_FEATURE_V5)) { | ||
119 | + set_feature(env, ARM_FEATURE_V4T); | ||
120 | + } | ||
121 | + if (arm_feature(env, ARM_FEATURE_LPAE)) { | ||
122 | + set_feature(env, ARM_FEATURE_V7MP); | ||
123 | + } | ||
124 | + if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | ||
125 | + set_feature(env, ARM_FEATURE_CBAR); | ||
126 | + } | ||
127 | + if (arm_feature(env, ARM_FEATURE_THUMB2) && | ||
128 | + !arm_feature(env, ARM_FEATURE_M)) { | ||
129 | + set_feature(env, ARM_FEATURE_THUMB_DSP); | ||
130 | + } | ||
95 | +} | 131 | +} |
96 | + | 132 | + |
97 | +#define DO_VRINT(INSN, RMODE) \ | 133 | void arm_cpu_post_init(Object *obj) |
98 | + static bool trans_##INSN(DisasContext *s, arg_2misc *a) \ | 134 | { |
99 | + { \ | 135 | ARMCPU *cpu = ARM_CPU(obj); |
100 | + return do_vrint(s, a, RMODE); \ | 136 | |
101 | + } | 137 | - /* M profile implies PMSA. We have to do this here rather than |
102 | + | 138 | - * in realize with the other feature-implication checks because |
103 | +DO_VRINT(VRINTN, FPROUNDING_TIEEVEN) | 139 | - * we look at the PMSA bit to see if we should add some properties. |
104 | +DO_VRINT(VRINTA, FPROUNDING_TIEAWAY) | 140 | + /* |
105 | +DO_VRINT(VRINTZ, FPROUNDING_ZERO) | 141 | + * Some features imply others. Figure this out now, because we |
106 | +DO_VRINT(VRINTM, FPROUNDING_NEGINF) | 142 | + * are going to look at the feature bits in deciding which |
107 | +DO_VRINT(VRINTP, FPROUNDING_POSINF) | 143 | + * properties to add. |
108 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 144 | */ |
109 | index XXXXXXX..XXXXXXX 100644 | 145 | - if (arm_feature(&cpu->env, ARM_FEATURE_M)) { |
110 | --- a/target/arm/translate.c | 146 | - set_feature(&cpu->env, ARM_FEATURE_PMSA); |
111 | +++ b/target/arm/translate.c | 147 | - } |
112 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 148 | + arm_cpu_propagate_feature_implications(cpu); |
113 | case NEON_2RM_VCEQ0_F: | 149 | |
114 | case NEON_2RM_VCLE0_F: | 150 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || |
115 | case NEON_2RM_VCLT0_F: | 151 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { |
116 | + case NEON_2RM_VRINTN: | 152 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
117 | + case NEON_2RM_VRINTA: | 153 | CPUARMState *env = &cpu->env; |
118 | + case NEON_2RM_VRINTM: | 154 | int pagebits; |
119 | + case NEON_2RM_VRINTP: | 155 | Error *local_err = NULL; |
120 | + case NEON_2RM_VRINTZ: | 156 | - bool no_aa32 = false; |
121 | /* handled by decodetree */ | 157 | |
122 | return 1; | 158 | /* Use pc-relative instructions in system-mode */ |
123 | case NEON_2RM_VTRN: | 159 | #ifndef CONFIG_USER_ONLY |
124 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 160 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
125 | } | 161 | cpu->isar.id_isar3 = u; |
126 | neon_store_reg(rm, pass, tmp2); | 162 | } |
127 | break; | 163 | |
128 | - case NEON_2RM_VRINTN: | 164 | - /* Some features automatically imply others: */ |
129 | - case NEON_2RM_VRINTA: | 165 | - if (arm_feature(env, ARM_FEATURE_V8)) { |
130 | - case NEON_2RM_VRINTM: | 166 | - if (arm_feature(env, ARM_FEATURE_M)) { |
131 | - case NEON_2RM_VRINTP: | 167 | - set_feature(env, ARM_FEATURE_V7); |
132 | - case NEON_2RM_VRINTZ: | 168 | - } else { |
133 | - { | 169 | - set_feature(env, ARM_FEATURE_V7VE); |
134 | - TCGv_i32 tcg_rmode; | 170 | - } |
135 | - TCGv_ptr fpstatus = get_fpstatus_ptr(1); | 171 | - } |
136 | - int rmode; | ||
137 | - | 172 | - |
138 | - if (op == NEON_2RM_VRINTZ) { | 173 | - /* |
139 | - rmode = FPROUNDING_ZERO; | 174 | - * There exist AArch64 cpus without AArch32 support. When KVM |
140 | - } else { | 175 | - * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. |
141 | - rmode = fp_decode_rm[((op & 0x6) >> 1) ^ 1]; | 176 | - * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. |
142 | - } | 177 | - * As a general principle, we also do not make ID register |
178 | - * consistency checks anywhere unless using TCG, because only | ||
179 | - * for TCG would a consistency-check failure be a QEMU bug. | ||
180 | - */ | ||
181 | - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
182 | - no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | ||
183 | - } | ||
143 | - | 184 | - |
144 | - tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); | 185 | - if (arm_feature(env, ARM_FEATURE_V7VE)) { |
145 | - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, | 186 | - /* v7 Virtualization Extensions. In real hardware this implies |
146 | - cpu_env); | 187 | - * EL2 and also the presence of the Security Extensions. |
147 | - gen_helper_rints(tmp, tmp, fpstatus); | 188 | - * For QEMU, for backwards-compatibility we implement some |
148 | - gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode, | 189 | - * CPUs or CPU configs which have no actual EL2 or EL3 but do |
149 | - cpu_env); | 190 | - * include the various other features that V7VE implies. |
150 | - tcg_temp_free_ptr(fpstatus); | 191 | - * Presence of EL2 itself is ARM_FEATURE_EL2, and of the |
151 | - tcg_temp_free_i32(tcg_rmode); | 192 | - * Security Extensions is ARM_FEATURE_EL3. |
152 | - break; | 193 | - */ |
153 | - } | 194 | - assert(!tcg_enabled() || no_aa32 || |
154 | case NEON_2RM_VCVTAU: | 195 | - cpu_isar_feature(aa32_arm_div, cpu)); |
155 | case NEON_2RM_VCVTAS: | 196 | - set_feature(env, ARM_FEATURE_LPAE); |
156 | case NEON_2RM_VCVTNU: | 197 | - set_feature(env, ARM_FEATURE_V7); |
198 | - } | ||
199 | - if (arm_feature(env, ARM_FEATURE_V7)) { | ||
200 | - set_feature(env, ARM_FEATURE_VAPA); | ||
201 | - set_feature(env, ARM_FEATURE_THUMB2); | ||
202 | - set_feature(env, ARM_FEATURE_MPIDR); | ||
203 | - if (!arm_feature(env, ARM_FEATURE_M)) { | ||
204 | - set_feature(env, ARM_FEATURE_V6K); | ||
205 | - } else { | ||
206 | - set_feature(env, ARM_FEATURE_V6); | ||
207 | - } | ||
208 | - | ||
209 | - /* Always define VBAR for V7 CPUs even if it doesn't exist in | ||
210 | - * non-EL3 configs. This is needed by some legacy boards. | ||
211 | - */ | ||
212 | - set_feature(env, ARM_FEATURE_VBAR); | ||
213 | - } | ||
214 | - if (arm_feature(env, ARM_FEATURE_V6K)) { | ||
215 | - set_feature(env, ARM_FEATURE_V6); | ||
216 | - set_feature(env, ARM_FEATURE_MVFR); | ||
217 | - } | ||
218 | - if (arm_feature(env, ARM_FEATURE_V6)) { | ||
219 | - set_feature(env, ARM_FEATURE_V5); | ||
220 | - if (!arm_feature(env, ARM_FEATURE_M)) { | ||
221 | - assert(!tcg_enabled() || no_aa32 || | ||
222 | - cpu_isar_feature(aa32_jazelle, cpu)); | ||
223 | - set_feature(env, ARM_FEATURE_AUXCR); | ||
224 | - } | ||
225 | - } | ||
226 | - if (arm_feature(env, ARM_FEATURE_V5)) { | ||
227 | - set_feature(env, ARM_FEATURE_V4T); | ||
228 | - } | ||
229 | - if (arm_feature(env, ARM_FEATURE_LPAE)) { | ||
230 | - set_feature(env, ARM_FEATURE_V7MP); | ||
231 | - } | ||
232 | - if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | ||
233 | - set_feature(env, ARM_FEATURE_CBAR); | ||
234 | - } | ||
235 | - if (arm_feature(env, ARM_FEATURE_THUMB2) && | ||
236 | - !arm_feature(env, ARM_FEATURE_M)) { | ||
237 | - set_feature(env, ARM_FEATURE_THUMB_DSP); | ||
238 | - } | ||
239 | |||
240 | /* | ||
241 | * We rely on no XScale CPU having VFP so we can use the same bits in the | ||
157 | -- | 242 | -- |
158 | 2.20.1 | 243 | 2.34.1 |
159 | |||
160 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In commit cfdb2c0c95ae9205b0 ("target/arm: Vectorize SABA/UABA") we | ||
2 | replaced the old handling of SABA/UABA with a vectorized implementation | ||
3 | which returns early rather than falling into the loop-ever-elements | ||
4 | code. We forgot to delete the part of the old looping code that | ||
5 | did the accumulate step, and Coverity correctly warns (CID 1428955) | ||
6 | that this code is now dead. Delete it. | ||
7 | 1 | ||
8 | Fixes: cfdb2c0c95ae9205b0 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20200619171547.29780-1-peter.maydell@linaro.org | ||
13 | --- | ||
14 | target/arm/translate-a64.c | 12 ------------ | ||
15 | 1 file changed, 12 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/translate-a64.c | ||
20 | +++ b/target/arm/translate-a64.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) | ||
22 | genfn(tcg_res, tcg_op1, tcg_op2); | ||
23 | } | ||
24 | |||
25 | - if (opcode == 0xf) { | ||
26 | - /* SABA, UABA: accumulating ops */ | ||
27 | - static NeonGenTwoOpFn * const fns[3] = { | ||
28 | - gen_helper_neon_add_u8, | ||
29 | - gen_helper_neon_add_u16, | ||
30 | - tcg_gen_add_i32, | ||
31 | - }; | ||
32 | - | ||
33 | - read_vec_element_i32(s, tcg_op1, rd, pass, MO_32); | ||
34 | - fns[size](tcg_res, tcg_op1, tcg_res); | ||
35 | - } | ||
36 | - | ||
37 | write_vec_element_i32(s, tcg_res, rd, pass, MO_32); | ||
38 | |||
39 | tcg_temp_free_i32(tcg_res); | ||
40 | -- | ||
41 | 2.20.1 | ||
42 | |||
43 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
2 | 1 | ||
3 | Add a trace event to see when a guest disable/enable the watchdog. | ||
4 | |||
5 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
6 | Message-id: 20200617072539.32686-2-f4bug@amsat.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | hw/watchdog/cmsdk-apb-watchdog.c | 1 + | ||
11 | hw/watchdog/trace-events | 1 + | ||
12 | 2 files changed, 2 insertions(+) | ||
13 | |||
14 | diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/watchdog/cmsdk-apb-watchdog.c | ||
17 | +++ b/hw/watchdog/cmsdk-apb-watchdog.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset, | ||
19 | break; | ||
20 | case A_WDOGLOCK: | ||
21 | s->lock = (value != WDOG_UNLOCK_VALUE); | ||
22 | + trace_cmsdk_apb_watchdog_lock(s->lock); | ||
23 | break; | ||
24 | case A_WDOGITCR: | ||
25 | if (s->is_luminary) { | ||
26 | diff --git a/hw/watchdog/trace-events b/hw/watchdog/trace-events | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/hw/watchdog/trace-events | ||
29 | +++ b/hw/watchdog/trace-events | ||
30 | @@ -XXX,XX +XXX,XX @@ | ||
31 | cmsdk_apb_watchdog_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
32 | cmsdk_apb_watchdog_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB watchdog write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
33 | cmsdk_apb_watchdog_reset(void) "CMSDK APB watchdog: reset" | ||
34 | +cmsdk_apb_watchdog_lock(uint32_t lock) "CMSDK APB watchdog: lock %" PRIu32 | ||
35 | -- | ||
36 | 2.20.1 | ||
37 | |||
38 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | M-profile CPUs generally allow configuration of the number of MPU |
---|---|---|---|
2 | regions that they have. We don't currently model this, so our | ||
3 | implementations of some of the board models provide CPUs with the | ||
4 | wrong number of regions. RTOSes like Zephyr that hardcode the | ||
5 | expected number of regions may therefore not run on the model if they | ||
6 | are set up to run on real hardware. | ||
2 | 7 | ||
3 | By using the TYPE_* definitions for devices, we can: | 8 | Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object, |
4 | - quickly find where devices are used with 'git-grep' | 9 | matching the ability of hardware to configure the number of Secure |
5 | - easily rename a device (one-line change). | 10 | and NonSecure regions separately. Our actual CPU implementation |
11 | doesn't currently support that, and it happens that none of the MPS | ||
12 | boards we model set the number of regions differently for Secure vs | ||
13 | NonSecure, so we provide an interface to the boards and SoCs that | ||
14 | won't need to change if we ever do add that functionality in future, | ||
15 | but make it an error to configure the two properties to different | ||
16 | values. | ||
6 | 17 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 18 | (The property name on the CPU is the somewhat misnamed-for-M-profile |
8 | Message-id: 20200617072539.32686-6-f4bug@amsat.org | 19 | "pmsav7-dregion", so we don't follow that naming convention for |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 20 | the properties here. The TRM doesn't say what the CPU configuration |
21 | variable names are, so we pick something, and follow the lowercase | ||
22 | convention we already have for properties here.) | ||
23 | |||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
25 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
26 | Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org | ||
11 | --- | 27 | --- |
12 | hw/arm/realview.c | 3 ++- | 28 | include/hw/arm/armv7m.h | 8 ++++++++ |
13 | hw/arm/versatilepb.c | 3 ++- | 29 | hw/arm/armv7m.c | 21 +++++++++++++++++++++ |
14 | hw/arm/vexpress.c | 3 ++- | 30 | 2 files changed, 29 insertions(+) |
15 | 3 files changed, 6 insertions(+), 3 deletions(-) | ||
16 | 31 | ||
17 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c | 32 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h |
18 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/hw/arm/realview.c | 34 | --- a/include/hw/arm/armv7m.h |
20 | +++ b/hw/arm/realview.c | 35 | +++ b/include/hw/arm/armv7m.h |
21 | @@ -XXX,XX +XXX,XX @@ | 36 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) |
22 | #include "hw/cpu/a9mpcore.h" | 37 | * + Property "vfp": enable VFP (forwarded to CPU object) |
23 | #include "hw/intc/realview_gic.h" | 38 | * + Property "dsp": enable DSP (forwarded to CPU object) |
24 | #include "hw/irq.h" | 39 | * + Property "enable-bitband": expose bitbanded IO |
25 | +#include "hw/i2c/arm_sbcon_i2c.h" | 40 | + * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded |
26 | 41 | + * to CPU object pmsav7-dregion property; default is whatever the default | |
27 | #define SMP_BOOT_ADDR 0xe0000000 | 42 | + * for the CPU is) |
28 | #define SMP_BOOTREG_ADDR 0x10000030 | 43 | + * + Property "mpu-s-regions": number of Secure MPU regions (default is |
29 | @@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine, | 44 | + * whatever the default for the CPU is; must currently be set to the same |
45 | + * value as mpu-ns-regions if the CPU implements the Security Extension) | ||
46 | * + Clock input "refclk" is the external reference clock for the systick timers | ||
47 | * + Clock input "cpuclk" is the main CPU clock | ||
48 | */ | ||
49 | @@ -XXX,XX +XXX,XX @@ struct ARMv7MState { | ||
50 | Object *idau; | ||
51 | uint32_t init_svtor; | ||
52 | uint32_t init_nsvtor; | ||
53 | + uint32_t mpu_ns_regions; | ||
54 | + uint32_t mpu_s_regions; | ||
55 | bool enable_bitband; | ||
56 | bool start_powered_off; | ||
57 | bool vfp; | ||
58 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/hw/arm/armv7m.c | ||
61 | +++ b/hw/arm/armv7m.c | ||
62 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
30 | } | 63 | } |
31 | } | 64 | } |
32 | 65 | ||
33 | - dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); | 66 | + /* |
34 | + dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL); | 67 | + * Real M-profile hardware can be configured with a different number of |
35 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); | 68 | + * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't |
36 | i2c_create_slave(i2c, "ds1338", 0x68); | 69 | + * support that yet, so catch attempts to select that. |
37 | 70 | + */ | |
38 | diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c | 71 | + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && |
39 | index XXXXXXX..XXXXXXX 100644 | 72 | + s->mpu_ns_regions != s->mpu_s_regions) { |
40 | --- a/hw/arm/versatilepb.c | 73 | + error_setg(errp, |
41 | +++ b/hw/arm/versatilepb.c | 74 | + "mpu-ns-regions and mpu-s-regions properties must have the same value"); |
42 | @@ -XXX,XX +XXX,XX @@ | 75 | + return; |
43 | #include "sysemu/sysemu.h" | 76 | + } |
44 | #include "hw/pci/pci.h" | 77 | + if (s->mpu_ns_regions != UINT_MAX && |
45 | #include "hw/i2c/i2c.h" | 78 | + object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) { |
46 | +#include "hw/i2c/arm_sbcon_i2c.h" | 79 | + if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion", |
47 | #include "hw/irq.h" | 80 | + s->mpu_ns_regions, errp)) { |
48 | #include "hw/boards.h" | 81 | + return; |
49 | #include "exec/address-spaces.h" | 82 | + } |
50 | @@ -XXX,XX +XXX,XX @@ static void versatile_init(MachineState *machine, int board_id) | 83 | + } |
51 | /* Add PL031 Real Time Clock. */ | 84 | + |
52 | sysbus_create_simple("pl031", 0x101e8000, pic[10]); | 85 | /* |
53 | 86 | * Tell the CPU where the NVIC is; it will fail realize if it doesn't | |
54 | - dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL); | 87 | * have one. Similarly, tell the NVIC where its CPU is. |
55 | + dev = sysbus_create_simple(TYPE_VERSATILE_I2C, 0x10002000, NULL); | 88 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { |
56 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); | 89 | false), |
57 | i2c_create_slave(i2c, "ds1338", 0x68); | 90 | DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true), |
58 | 91 | DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), | |
59 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c | 92 | + DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX), |
60 | index XXXXXXX..XXXXXXX 100644 | 93 | + DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX), |
61 | --- a/hw/arm/vexpress.c | 94 | DEFINE_PROP_END_OF_LIST(), |
62 | +++ b/hw/arm/vexpress.c | 95 | }; |
63 | @@ -XXX,XX +XXX,XX @@ | ||
64 | #include "hw/char/pl011.h" | ||
65 | #include "hw/cpu/a9mpcore.h" | ||
66 | #include "hw/cpu/a15mpcore.h" | ||
67 | +#include "hw/i2c/arm_sbcon_i2c.h" | ||
68 | |||
69 | #define VEXPRESS_BOARD_ID 0x8e0 | ||
70 | #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) | ||
71 | @@ -XXX,XX +XXX,XX @@ static void vexpress_common_init(MachineState *machine) | ||
72 | sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); | ||
73 | sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); | ||
74 | |||
75 | - dev = sysbus_create_simple("versatile_i2c", map[VE_SERIALDVI], NULL); | ||
76 | + dev = sysbus_create_simple(TYPE_VERSATILE_I2C, map[VE_SERIALDVI], NULL); | ||
77 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); | ||
78 | i2c_create_slave(i2c, "sii9022", 0x39); | ||
79 | 96 | ||
80 | -- | 97 | -- |
81 | 2.20.1 | 98 | 2.34.1 |
82 | 99 | ||
83 | 100 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The |
---|---|---|---|
2 | 2 | MPS2/MPS3 FPGA images don't override these except in the case of | |
3 | From 'Application Note AN521', chapter 4.7: | 3 | AN547, which uses 16 MPU regions. |
4 | 4 | ||
5 | The SMM implements four SBCon serial modules: | 5 | Define properties on the ARMSSE object for the MPU regions (using the |
6 | 6 | same names as the documented RTL configuration settings, and | |
7 | One SBCon module for use by the Color LCD touch interface. | 7 | following the pattern we already have for this device of using |
8 | One SBCon module to configure the audio controller. | 8 | all-caps names as the RTL does), and set them in the board code. |
9 | Two general purpose SBCon modules, that connect to the | 9 | |
10 | Expansion headers J7 and J8, are intended for use with the | 10 | We don't actually need to override the default except on AN547, |
11 | V2C-Shield1 which provide an I2C interface on the headers. | 11 | but it's simpler code to have the board code set them always |
12 | 12 | rather than tracking which board subtypes want to set them to | |
13 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 13 | a non-default value separately from what that value is. |
14 | Message-id: 20200617072539.32686-15-f4bug@amsat.org | 14 | |
15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524 |
16 | we now correctly use 8 MPU regions, while mps3-an547 stays at its | ||
17 | current 16 regions. | ||
18 | |||
19 | It's possible some guest code wrongly depended on the previous | ||
20 | incorrectly modeled number of memory regions. (Such guest code | ||
21 | should ideally check the number of regions via the MPU_TYPE | ||
22 | register.) The old behaviour can be obtained with additional | ||
23 | -global arguments to QEMU: | ||
24 | |||
25 | For mps2-an521 and mps2-an524: | ||
26 | -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16 | ||
27 | |||
28 | For mps2-an505: | ||
29 | -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 | ||
30 | |||
31 | NB that the way the implementation allows this use of -global | ||
32 | is slightly fragile: if the board code explicitly sets the | ||
33 | properties on the sse-200 object, this overrides the -global | ||
34 | command line option. So we rely on: | ||
35 | - the boards that need fixing all happen to use the SSE defaults | ||
36 | - we can write the board code to only set the property if it | ||
37 | is different from the default, rather than having all boards | ||
38 | explicitly set the property | ||
39 | - the board that does need to use a non-default value happens | ||
40 | to need to set it to the same value (16) we previously used | ||
41 | This works, but there are some kinds of refactoring of the | ||
42 | mps2-tz.c code that would break the support for -global here. | ||
43 | |||
44 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772 | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 45 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
46 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
47 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
48 | Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org | ||
17 | --- | 49 | --- |
18 | hw/arm/mps2-tz.c | 23 ++++++++++++++++++----- | 50 | include/hw/arm/armsse.h | 5 +++++ |
19 | 1 file changed, 18 insertions(+), 5 deletions(-) | 51 | hw/arm/armsse.c | 16 ++++++++++++++++ |
20 | 52 | hw/arm/mps2-tz.c | 29 +++++++++++++++++++++++++++++ | |
53 | 3 files changed, 50 insertions(+) | ||
54 | |||
55 | diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/include/hw/arm/armsse.h | ||
58 | +++ b/include/hw/arm/armsse.h | ||
59 | @@ -XXX,XX +XXX,XX @@ | ||
60 | * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an | ||
61 | * SSE-200 both are present; CPU0 in an SSE-200 has neither. | ||
62 | * Since the IoTKit has only one CPU, it does not have the CPU1_* properties. | ||
63 | + * + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S" | ||
64 | + * which set the number of MPU regions on the CPUs. If there is only one | ||
65 | + * CPU the CPU1 properties are not present. | ||
66 | * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, | ||
67 | * which are wired to its NVIC lines 32 .. n+32 | ||
68 | * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for | ||
69 | @@ -XXX,XX +XXX,XX @@ struct ARMSSE { | ||
70 | uint32_t exp_numirq; | ||
71 | uint32_t sram_addr_width; | ||
72 | uint32_t init_svtor; | ||
73 | + uint32_t cpu_mpu_ns[SSE_MAX_CPUS]; | ||
74 | + uint32_t cpu_mpu_s[SSE_MAX_CPUS]; | ||
75 | bool cpu_fpu[SSE_MAX_CPUS]; | ||
76 | bool cpu_dsp[SSE_MAX_CPUS]; | ||
77 | }; | ||
78 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | ||
79 | index XXXXXXX..XXXXXXX 100644 | ||
80 | --- a/hw/arm/armsse.c | ||
81 | +++ b/hw/arm/armsse.c | ||
82 | @@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = { | ||
83 | DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), | ||
84 | DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), | ||
85 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), | ||
86 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), | ||
87 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), | ||
88 | DEFINE_PROP_END_OF_LIST() | ||
89 | }; | ||
90 | |||
91 | @@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = { | ||
92 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), | ||
93 | DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), | ||
94 | DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), | ||
95 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), | ||
96 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), | ||
97 | + DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8), | ||
98 | + DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8), | ||
99 | DEFINE_PROP_END_OF_LIST() | ||
100 | }; | ||
101 | |||
102 | @@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = { | ||
103 | DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), | ||
104 | DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), | ||
105 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), | ||
106 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), | ||
107 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), | ||
108 | DEFINE_PROP_END_OF_LIST() | ||
109 | }; | ||
110 | |||
111 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) | ||
112 | return; | ||
113 | } | ||
114 | } | ||
115 | + if (!object_property_set_uint(cpuobj, "mpu-ns-regions", | ||
116 | + s->cpu_mpu_ns[i], errp)) { | ||
117 | + return; | ||
118 | + } | ||
119 | + if (!object_property_set_uint(cpuobj, "mpu-s-regions", | ||
120 | + s->cpu_mpu_s[i], errp)) { | ||
121 | + return; | ||
122 | + } | ||
123 | |||
124 | if (i > 0) { | ||
125 | memory_region_add_subregion_overlap(&s->cpu_container[i], 0, | ||
21 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | 126 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
22 | index XXXXXXX..XXXXXXX 100644 | 127 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/hw/arm/mps2-tz.c | 128 | --- a/hw/arm/mps2-tz.c |
24 | +++ b/hw/arm/mps2-tz.c | 129 | +++ b/hw/arm/mps2-tz.c |
25 | @@ -XXX,XX +XXX,XX @@ | 130 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { |
26 | #include "hw/arm/armsse.h" | 131 | int uart_overflow_irq; /* number of the combined UART overflow IRQ */ |
27 | #include "hw/dma/pl080.h" | 132 | uint32_t init_svtor; /* init-svtor setting for SSE */ |
28 | #include "hw/ssi/pl022.h" | 133 | uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ |
29 | +#include "hw/i2c/arm_sbcon_i2c.h" | 134 | + uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */ |
30 | #include "hw/net/lan9118.h" | 135 | + uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */ |
31 | #include "net/net.h" | 136 | + uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */ |
32 | #include "hw/core/split-irq.h" | 137 | + uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */ |
33 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 138 | const RAMInfo *raminfo; |
34 | TZPPC ppc[5]; | 139 | const char *armsse_type; |
35 | TZMPC ssram_mpc[3]; | 140 | uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */ |
36 | PL022State spi[5]; | 141 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) |
37 | - UnimplementedDeviceState i2c[4]; | 142 | #define MPS3_DDR_SIZE (2 * GiB) |
38 | + ArmSbconI2CState i2c[4]; | 143 | #endif |
39 | UnimplementedDeviceState i2s_audio; | 144 | |
40 | UnimplementedDeviceState gpio[4]; | 145 | +/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */ |
41 | UnimplementedDeviceState gfx; | 146 | +#define MPU_REGION_DEFAULT UINT32_MAX |
42 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, | 147 | + |
43 | return sysbus_mmio_get_region(s, 0); | 148 | static const uint32_t an505_oscclk[] = { |
149 | 40000000, | ||
150 | 24580000, | ||
151 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
152 | OBJECT(system_memory), &error_abort); | ||
153 | qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); | ||
154 | qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); | ||
155 | + if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) { | ||
156 | + qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns); | ||
157 | + } | ||
158 | + if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) { | ||
159 | + qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s); | ||
160 | + } | ||
161 | + if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) { | ||
162 | + if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) { | ||
163 | + qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns); | ||
164 | + } | ||
165 | + if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) { | ||
166 | + qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s); | ||
167 | + } | ||
168 | + } | ||
169 | qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); | ||
170 | qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); | ||
171 | qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); | ||
172 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data) | ||
173 | { | ||
174 | MachineClass *mc = MACHINE_CLASS(oc); | ||
175 | IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); | ||
176 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | ||
177 | |||
178 | mc->init = mps2tz_common_init; | ||
179 | mc->reset = mps2_machine_reset; | ||
180 | iic->check = mps2_tz_idau_check; | ||
181 | + | ||
182 | + /* Most machines leave these at the SSE defaults */ | ||
183 | + mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT; | ||
184 | + mmc->cpu0_mpu_s = MPU_REGION_DEFAULT; | ||
185 | + mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT; | ||
186 | + mmc->cpu1_mpu_s = MPU_REGION_DEFAULT; | ||
44 | } | 187 | } |
45 | 188 | ||
46 | +static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, | 189 | static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) |
47 | + const char *name, hwaddr size) | 190 | @@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data) |
48 | +{ | 191 | mmc->numirq = 96; |
49 | + ArmSbconI2CState *i2c = opaque; | 192 | mmc->uart_overflow_irq = 48; |
50 | + SysBusDevice *s; | 193 | mmc->init_svtor = 0x00000000; |
51 | + | 194 | + mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16; |
52 | + object_initialize_child(OBJECT(mms), name, i2c, TYPE_ARM_SBCON_I2C); | 195 | mmc->sram_addr_width = 21; |
53 | + s = SYS_BUS_DEVICE(i2c); | 196 | mmc->raminfo = an547_raminfo; |
54 | + sysbus_realize(s, &error_fatal); | 197 | mmc->armsse_type = TYPE_SSE300; |
55 | + return sysbus_mmio_get_region(s, 0); | ||
56 | +} | ||
57 | + | ||
58 | static void mps2tz_common_init(MachineState *machine) | ||
59 | { | ||
60 | MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); | ||
61 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
62 | { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, | ||
63 | { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, | ||
64 | { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, | ||
65 | - { "i2c0", make_unimp_dev, &mms->i2c[0], 0x40207000, 0x1000 }, | ||
66 | - { "i2c1", make_unimp_dev, &mms->i2c[1], 0x40208000, 0x1000 }, | ||
67 | - { "i2c2", make_unimp_dev, &mms->i2c[2], 0x4020c000, 0x1000 }, | ||
68 | - { "i2c3", make_unimp_dev, &mms->i2c[3], 0x4020d000, 0x1000 }, | ||
69 | + { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, | ||
70 | + { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, | ||
71 | + { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, | ||
72 | + { "i2c3", make_i2c, &mms->i2c[3], 0x4020d000, 0x1000 }, | ||
73 | }, | ||
74 | }, { | ||
75 | .name = "apb_ppcexp2", | ||
76 | -- | 198 | -- |
77 | 2.20.1 | 199 | 2.34.1 |
78 | 200 | ||
79 | 201 | diff view generated by jsdifflib |