hw_error() calls exit(). This a bit overkill when we can log
the accesses as unimplemented or guest error.

When fuzzing the devices, we don't want the whole process to
exit. Replace some hw_error() calls by qemu_log_mask().

Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"
Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,
the default value on the APB bus is 0.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Fixes -Wsometimes-uninitialized:

hw/timer/exynos4210_mct.c:1158:5: error: variable 'value' is used uninitialized whenever switch default is taken [-Werror,-Wsometimes-uninitialized]
    default:
    ^~~~~~~
hw/timer/exynos4210_mct.c:1163:12: note: uninitialized use occurs here
    return value;
           ^~~~~
hw/timer/exynos4210_mct.c:1063:19: note: initialize the variable 'value' to silence this warning
    uint32_t value;
                  ^
                   = 0
---
 hw/timer/exynos4210_mct.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
index 570cf7075b..29a4b10676 100644
--- a/hw/timer/exynos4210_mct.c
+++ b/hw/timer/exynos4210_mct.c
@@ -54,7 +54,6 @@
 
 #include "qemu/osdep.h"
 #include "qemu/log.h"
-#include "hw/hw.h"
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "qemu/timer.h"
@@ -62,7 +61,6 @@
 #include "hw/ptimer.h"
 
 #include "hw/arm/exynos4210.h"
-#include "hw/hw.h"
 #include "hw/irq.h"
 
 //#define DEBUG_MCT
@@ -1062,7 +1060,7 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
     int index;
     int shift;
     uint64_t count;
-    uint32_t value;
+    uint32_t value = 0;
     int lt_i;
 
     switch (offset) {
@@ -1158,8 +1156,8 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
         break;
 
     default:
-        hw_error("exynos4210.mct: bad read offset "
-                TARGET_FMT_plx "\n", offset);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+                      __func__, offset);
         break;
     }
     return value;
@@ -1484,8 +1482,8 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
         break;
 
     default:
-        hw_error("exynos4210.mct: bad write offset "
-                TARGET_FMT_plx "\n", offset);
+        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
+                      __func__, offset);
         break;
     }
 }
-- 
2.21.3

On Mon, May 18, 2020 at 7:05 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> hw_error() calls exit(). This a bit overkill when we can log
> the accesses as unimplemented or guest error.
>
> When fuzzing the devices, we don't want the whole process to
> exit. Replace some hw_error() calls by qemu_log_mask().
>
> Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"
> Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,
> the default value on the APB bus is 0.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
> v2: Fixes -Wsometimes-uninitialized:
>
> hw/timer/exynos4210_mct.c:1158:5: error: variable 'value' is used uninitialized whenever switch default is taken [-Werror,-Wsometimes-uninitialized]
>     default:
>     ^~~~~~~
> hw/timer/exynos4210_mct.c:1163:12: note: uninitialized use occurs here
>     return value;
>            ^~~~~
> hw/timer/exynos4210_mct.c:1063:19: note: initialize the variable 'value' to silence this warning
>     uint32_t value;
>                   ^
>                    = 0
> ---
>  hw/timer/exynos4210_mct.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c
> index 570cf7075b..29a4b10676 100644
> --- a/hw/timer/exynos4210_mct.c
> +++ b/hw/timer/exynos4210_mct.c
> @@ -54,7 +54,6 @@
>
>  #include "qemu/osdep.h"
>  #include "qemu/log.h"
> -#include "hw/hw.h"
>  #include "hw/sysbus.h"
>  #include "migration/vmstate.h"
>  #include "qemu/timer.h"
> @@ -62,7 +61,6 @@
>  #include "hw/ptimer.h"
>
>  #include "hw/arm/exynos4210.h"
> -#include "hw/hw.h"
>  #include "hw/irq.h"
>
>  //#define DEBUG_MCT
> @@ -1062,7 +1060,7 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
>      int index;
>      int shift;
>      uint64_t count;
> -    uint32_t value;
> +    uint32_t value = 0;
>      int lt_i;
>
>      switch (offset) {
> @@ -1158,8 +1156,8 @@ static uint64_t exynos4210_mct_read(void *opaque, hwaddr offset,
>          break;
>
>      default:
> -        hw_error("exynos4210.mct: bad read offset "
> -                TARGET_FMT_plx "\n", offset);
> +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
> +                      __func__, offset);
>          break;
>      }
>      return value;
> @@ -1484,8 +1482,8 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset,
>          break;
>
>      default:
> -        hw_error("exynos4210.mct: bad write offset "
> -                TARGET_FMT_plx "\n", offset);
> +        qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
> +                      __func__, offset);
>          break;
>      }
>  }
> --
> 2.21.3
>
>