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[88.21.202.17]) by smtp.gmail.com with ESMTPSA id s67sm16611946wmf.3.2020.05.18.07.03.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2020 07:03:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ynbMaAjpiD0x7UQ7qyXtXy4p3Mbw7B/2c81S4GZ2qwY=; b=BPO2G5bbStMKoFidT2VTx7PyLs2AYrJD/RBVIMqaeenYWBRdzL2WdryUCuQCPWh2jI 5mQ93bcfwgrCxHAJ/50H2TjtRxTFaNaNQRCABd0TXTwDbEEqlvX2dhlcOpAF513pM4rY VcC/wcwMDiile1YVcJwMZta5RWiCiyXRhaJp5pqjzv22qGrK1+dlr/IjYT285uUf809Z P++/5JlNgowdNArhzIBAXr2ADwvClY8PL7v+kER9RY1yndW8LhvcuSDbGnl1X5+sXQKO EXQtONRJiuKMWaZVg+vYrsr2JvVe1QE1XJ7mOZjdgQRDcQKYPOYdwJtDBgn5TgPmjy5v iIJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ynbMaAjpiD0x7UQ7qyXtXy4p3Mbw7B/2c81S4GZ2qwY=; b=QHGftmVvBSlO3EwE8vcgJpmZgdaIJdGy4SzsV3UHxgu6XRz5QCdGJ1QhYaJsE1H539 hKhUsBqXLv43PyA+HNBWWsUQLpUAoJ4LdDkE1xNlUEs1dXjVB/AaS8FH2TQu6Q+dFBwk 6l+POA6I16BMy1OjJ7XvF/sK6v1xqgJbgppfEd8VX97p9md2N1EFZNBE3p6m1zmKc3au KQ4FmzEcrozos9lItWTOwBD2NqCI6+shJwKU/6nK8eY4Ux1xfWxg5MVNqhW2WOcnIW8T dfI5CcvdUsMiVrorTpn/9+wfDMgb6HxIK91tcTNu+CwvDGgXXoRJzeBa8FaUMTmJHRhk QIsg== X-Gm-Message-State: AOAM5322Ldcf/wuXAQWsplJq+Ks3OhYtQ9njtlYmGaz7lEIcsO8zwVc9 RLLDB/u4HlDdsGaTwSZ5qdcyWpFf77E= X-Google-Smtp-Source: ABdhPJx2/rd8jVm3HNh1/wmz2D+7CQsQ4ipbpDiGkGN3TY9a38KhiUdJ+MoZ+WdrlRF+LFWAY0e6dw== X-Received: by 2002:a1c:acc8:: with SMTP id v191mr20554002wme.154.1589810600658; Mon, 18 May 2020 07:03:20 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 4/4] hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask() Date: Mon, 18 May 2020 16:03:09 +0200 Message-Id: <20200518140309.5220-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200518140309.5220-1-f4bug@amsat.org> References: <20200518140309.5220-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Paolo Bonzini , Igor Mitsyanko , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , "Edgar E. Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) hw_error() calls exit(). This a bit overkill when we can log the accesses as unimplemented or guest error. When fuzzing the devices, we don't want the whole process to exit. Replace some hw_error() calls by qemu_log_mask(). Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00" Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4, the default value on the APB bus is 0. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- v2: Fixes -Wsometimes-uninitialized: hw/timer/exynos4210_mct.c:1158:5: error: variable 'value' is used uninitial= ized whenever switch default is taken [-Werror,-Wsometimes-uninitialized] default: ^~~~~~~ hw/timer/exynos4210_mct.c:1163:12: note: uninitialized use occurs here return value; ^~~~~ hw/timer/exynos4210_mct.c:1063:19: note: initialize the variable 'value' to= silence this warning uint32_t value; ^ =3D 0 --- hw/timer/exynos4210_mct.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index 570cf7075b..29a4b10676 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -54,7 +54,6 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" -#include "hw/hw.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qemu/timer.h" @@ -62,7 +61,6 @@ #include "hw/ptimer.h" =20 #include "hw/arm/exynos4210.h" -#include "hw/hw.h" #include "hw/irq.h" =20 //#define DEBUG_MCT @@ -1062,7 +1060,7 @@ static uint64_t exynos4210_mct_read(void *opaque, hwa= ddr offset, int index; int shift; uint64_t count; - uint32_t value; + uint32_t value =3D 0; int lt_i; =20 switch (offset) { @@ -1158,8 +1156,8 @@ static uint64_t exynos4210_mct_read(void *opaque, hwa= ddr offset, break; =20 default: - hw_error("exynos4210.mct: bad read offset " - TARGET_FMT_plx "\n", offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + __func__, offset); break; } return value; @@ -1484,8 +1482,8 @@ static void exynos4210_mct_write(void *opaque, hwaddr= offset, break; =20 default: - hw_error("exynos4210.mct: bad write offset " - TARGET_FMT_plx "\n", offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + __func__, offset); break; } } --=20 2.21.3