Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups.

The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835:

Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504

for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:

target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100)

* Start of conversion of Neon insns to decodetree

* versal board: support SD and RTC

* Implement ARMv8.2-TTS2UXN

* Make VQDMULL undefined when U=1

* Some minor code cleanups

Edgar E. Iglesias (11):

hw/arm: versal: Remove inclusion of arm_gicv3_common.h

hw/arm: versal: Move misplaced comment

hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal

hw/arm: versal: Embed the UARTs into the SoC type

hw/arm: versal: Embed the GEMs into the SoC type

hw/arm: versal: Embed the ADMAs into the SoC type

hw/arm: versal: Embed the APUs into the SoC type

hw/arm: versal: Add support for SD

hw/arm: versal: Add support for the RTC

hw/arm: versal-virt: Add support for SD

hw/arm: versal-virt: Add support for the RTC

Fredrik Strupe (1):

target/arm: Make VQDMULL undefined when U=1

Peter Maydell (25):

target/arm: Don't use a TLB for ARMMMUIdx_Stage2

target/arm: Use enum constant in get_phys_addr_lpae() call

target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()

target/arm: Implement ARMv8.2-TTS2UXN

target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0

target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check

target/arm: Don't allow Thumb Neon insns without FEATURE_NEON

target/arm: Add stubs for AArch32 Neon decodetree

target/arm: Convert VCMLA (vector) to decodetree

target/arm: Convert VCADD (vector) to decodetree

target/arm: Convert V[US]DOT (vector) to decodetree

target/arm: Convert VFM[AS]L (vector) to decodetree

target/arm: Convert VCMLA (scalar) to decodetree

target/arm: Convert V[US]DOT (scalar) to decodetree

target/arm: Convert VFM[AS]L (scalar) to decodetree

target/arm: Convert Neon load/store multiple structures to decodetree

target/arm: Convert Neon 'load single structure to all lanes' to decodetree

target/arm: Convert Neon 'load/store single structure' to decodetree

target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree

target/arm: Convert Neon 3-reg-same logic ops to decodetree

target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree

target/arm: Convert Neon 3-reg-same comparisons to decodetree

target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree

target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree

target/arm: Move gen_ function typedefs to translate.h

Philippe Mathieu-Daudé (2):

hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string

target/arm: Use uint64_t for midr field in CPU state struct

include/hw/arm/xlnx-versal.h | 31 +-

target/arm/cpu-param.h | 2 +-

target/arm/cpu.h | 38 ++-

target/arm/translate-a64.h | 9 -

target/arm/translate.h | 26 ++

target/arm/neon-dp.decode | 86 +++++

target/arm/neon-ls.decode | 52 +++

target/arm/neon-shared.decode | 66 ++++

hw/arm/mps2-tz.c | 2 +-

hw/arm/xlnx-versal-virt.c | 74 ++++-

hw/arm/xlnx-versal.c | 115 +++++--

target/arm/cpu.c | 3 +-

target/arm/cpu64.c | 8 +-

target/arm/helper.c | 183 ++++------

target/arm/translate-a64.c | 17 -

target/arm/translate-neon.inc.c | 714 +++++++++++++++++++++++++++++++++++++++

target/arm/translate-vfp.inc.c | 6 -

target/arm/translate.c | 716 +++-------------------------------------

target/arm/Makefile.objs | 18 +

19 files changed, 1302 insertions(+), 864 deletions(-)

create mode 100644 target/arm/neon-dp.decode

create mode 100644 target/arm/neon-ls.decode

create mode 100644 target/arm/neon-shared.decode

create mode 100644 target/arm/translate-neon.inc.c

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the GEMs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20200427181649.26851-6-edgar.iglesias@gmail.com

include/hw/arm/xlnx-versal.h | 3 ++-

hw/arm/xlnx-versal.c | 15 ++++++++-------

2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h

--- a/include/hw/arm/xlnx-versal.h

+++ b/include/hw/arm/xlnx-versal.h

@@ -XXX,XX +XXX,XX @@

#include "hw/arm/boot.h"

#include "hw/intc/arm_gicv3.h"

#include "hw/char/pl011.h"

+#include "hw/net/cadence_gem.h"

#define TYPE_XLNX_VERSAL "xlnx-versal"

#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)

@@ -XXX,XX +XXX,XX @@ typedef struct Versal {

struct {

PL011State uart[XLNX_VERSAL_NR_UARTS];

- SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];

+ CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];

SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];

} iou;

} lpd;

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal.c

+++ b/hw/arm/xlnx-versal.c

@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)

DeviceState *dev;

MemoryRegion *mr;

- dev = qdev_create(NULL, "cadence_gem");

- s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);

- object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);

+ sysbus_init_child_obj(OBJECT(s), name,

+ &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]),

+ TYPE_CADENCE_GEM);

+ dev = DEVICE(&s->lpd.iou.gem[i]);

if (nd->used) {

qemu_check_nic_model(nd, "cadence_gem");

qdev_set_nic_properties(dev, nd);

}

- object_property_set_int(OBJECT(s->lpd.iou.gem[i]),

+ object_property_set_int(OBJECT(dev),

2, "num-priority-queues",

&error_abort);

- object_property_set_link(OBJECT(s->lpd.iou.gem[i]),

+ object_property_set_link(OBJECT(dev),

OBJECT(&s->mr_ps), "dma",

&error_abort);

qdev_init_nofail(dev);

- mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);

+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

memory_region_add_subregion(&s->mr_ps, addrs[i], mr);

- sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);

+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);

g_free(name);

}

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.

Represent it in QEMU's ARMCPU struct with a uint64_t, not a

uint32_t.

This fixes an error when compiling with -Werror=conversion

because we were manipulating the register value using a

local uint64_t variable:

target/arm/cpu64.c: In function ‘aarch64_max_initfn’:

target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]

628 | cpu->midr = t;

| ^

and future-proofs us against a possible future architecture

change using some of the top 32 bits.

Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Message-id: 20200428172634.29707-1-f4bug@amsat.org

target/arm/cpu.h | 2 +-

target/arm/cpu.c | 2 +-

2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ struct ARMCPU {

uint64_t id_aa64dfr0;

uint64_t id_aa64dfr1;

} isar;

- uint32_t midr;

+ uint64_t midr;

uint32_t revidr;

uint32_t reset_fpsid;

uint32_t ctr;

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {

static Property arm_cpu_properties[] = {

DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),

DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),

- DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),

+ DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),

DEFINE_PROP_UINT64("mp-affinity", ARMCPU,

mp_affinity, ARM64_AFFINITY_INVALID),

DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),

2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add support for SD.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20200427181649.26851-11-edgar.iglesias@gmail.com

hw/arm/xlnx-versal-virt.c | 46 +++++++++++++++++++++++++++++++++++++++

1 file changed, 46 insertions(+)

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c

--- a/hw/arm/xlnx-versal-virt.c

+++ b/hw/arm/xlnx-versal-virt.c

@@ -XXX,XX +XXX,XX @@

#include "hw/arm/sysbus-fdt.h"

#include "hw/arm/fdt.h"

#include "cpu.h"

+#include "hw/qdev-properties.h"

#include "hw/arm/xlnx-versal.h"

#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")

@@ -XXX,XX +XXX,XX @@ static void fdt_add_zdma_nodes(VersalVirt *s)

* If the user provides an Operating System to be loaded, we expect them

@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)

fdt_add_gic_nodes(s);

fdt_add_timer_nodes(s);

fdt_add_zdma_nodes(s);

+ fdt_add_sd_nodes(s);

fdt_add_cpu_nodes(s, psci_conduit);

fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);

fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);

@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)

memory_region_add_subregion_overlap(get_system_memory(),

0, &s->soc.fpd.apu.mr, 0);

+ /* Plugin SD cards. */

+ for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {

+ sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));

s->binfo.ram_size = machine->ram_size;

s->binfo.loader_start = 0x0;

s->binfo.get_dtb = versal_virt_get_dtb;

2.20.1

We're going to want at least some of the NeonGen* typedefs

for the refactored 32-bit Neon decoder, so move them all

to translate.h since it makes more sense to keep them in

one group.

Message-id: 20200430181003.21682-23-peter.maydell@linaro.org

target/arm/translate.h | 17 +++++++++++++++++

target/arm/translate-a64.c | 17 -----------------

2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,

typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,

uint32_t, uint32_t, uint32_t);

+/* Function prototype for gen_ functions for calling Neon helpers */

+typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);

+typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);

+typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);

+typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);

+typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);

+typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);

+typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);

+typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);

+typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);

+typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);

+typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);

+typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);

+typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);

+typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);

+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);

+

#endif /* TARGET_ARM_TRANSLATE_H */

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ typedef struct AArch64DecodeTable {

AArch64DecodeFn *disas_fn;

} AArch64DecodeTable;

-/* Function prototype for gen_ functions for calling Neon helpers */

-typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);

-typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);

-typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);

-typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);

-typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);

-typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);

-typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);

-typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);

-typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);

-typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);

-typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);

-typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);

-typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);

-typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);

-typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);

-

/* initialize TCG globals. */

void a64_translate_init(void)

{

2.20.1

Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.

Message-id: 20200430181003.21682-9-peter.maydell@linaro.org

target/arm/neon-shared.decode | 5 +++++

target/arm/translate-neon.inc.c | 40 +++++++++++++++++++++++++++++++++

target/arm/translate.c | 26 +--------------------

3 files changed, 46 insertions(+), 25 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode

--- a/target/arm/neon-shared.decode

+++ b/target/arm/neon-shared.decode

@@ -XXX,XX +XXX,XX @@ VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \

vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0

VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \

vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1

+

+VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \

+ vn=%vn_dp vd=%vd_dp size=0

+VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \

+ vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0

diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c

--- a/target/arm/translate-neon.inc.c

+++ b/target/arm/translate-neon.inc.c

@@ -XXX,XX +XXX,XX @@ static bool trans_VFML(DisasContext *s, arg_VFML *a)

gen_helper_gvec_fmlal_a32);

return true;

}

+

+static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)

+{

+ gen_helper_gvec_3_ptr *fn_gvec_ptr;

+ int opr_sz;

+ TCGv_ptr fpst;

+

+ if (!dc_isar_feature(aa32_vcma, s)) {

+ return false;

+ }

+ if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {

+ return false;

+ }

+

+ /* UNDEF accesses to D16-D31 if they don't exist. */

+ if (!dc_isar_feature(aa32_simd_r32, s) &&

+ ((a->vd | a->vn | a->vm) & 0x10)) {

+ return false;

+ }

+

+ if ((a->vd | a->vn) & a->q) {

+ return false;

+ }

+

+ if (!vfp_access_check(s)) {

+ return true;

+ }

+

+ fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx

+ : gen_helper_gvec_fcmlah_idx);

+ opr_sz = (1 + a->q) * 8;

+ fpst = get_fpstatus_ptr(1);

+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),

+ vfp_reg_offset(1, a->vn),

+ vfp_reg_offset(1, a->vm),

+ fpst, opr_sz, opr_sz,

+ (a->index << 2) | a->rot, fn_gvec_ptr);

+ tcg_temp_free_ptr(fpst);

+ return true;

+}

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)

bool is_long = false, q = extract32(insn, 6, 1);

bool ptr_is_env = false;

- if ((insn & 0xff000f10) == 0xfe000800) {

- /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */

- int rot = extract32(insn, 20, 2);

- int size = extract32(insn, 23, 1);

- int index;

-

- if (!dc_isar_feature(aa32_vcma, s)) {

- return 1;

- }

- if (size == 0) {

- if (!dc_isar_feature(aa32_fp16_arith, s)) {

- return 1;

- }

- /* For fp16, rm is just Vm, and index is M. */

- rm = extract32(insn, 0, 4);

- index = extract32(insn, 5, 1);

- } else {

- /* For fp32, rm is the usual M:Vm, and index is 0. */

- VFP_DREG_M(rm, insn);

- index = 0;

- }

- data = (index << 2) | rot;

- fn_gvec_ptr = (size ? gen_helper_gvec_fcmlas_idx

- : gen_helper_gvec_fcmlah_idx);

- } else if ((insn & 0xffb00f00) == 0xfe200d00) {

+ if ((insn & 0xffb00f00) == 0xfe200d00) {

/* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */

int u = extract32(insn, 4, 1);

2.20.1

Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the

3-reg-same grouping to decodetree.

Message-id: 20200430181003.21682-20-peter.maydell@linaro.org

target/arm/neon-dp.decode | 9 +++++++

target/arm/translate-neon.inc.c | 44 +++++++++++++++++++++++++++++++++

target/arm/translate.c | 28 +++------------------

3 files changed, 56 insertions(+), 25 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode

--- a/target/arm/neon-dp.decode

+++ b/target/arm/neon-dp.decode

@@ -XXX,XX +XXX,XX @@ VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same

VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same

VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same

+VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same

+VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same

+

VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same

VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same

VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same

@@ -XXX,XX +XXX,XX @@ VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same

VTST_3s 1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same

VCEQ_3s 1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same

+

+VMLA_3s 1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same

+VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same

+

+VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same

+VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same

diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c

--- a/target/arm/translate-neon.inc.c

+++ b/target/arm/translate-neon.inc.c

@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)

DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)

DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)

DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)

+DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul)

#define DO_3SAME_CMP(INSN, COND) \

static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \

@@ -XXX,XX +XXX,XX @@ DO_3SAME_GVEC4(VQADD_S, sqadd_op)

DO_3SAME_GVEC4(VQADD_U, uqadd_op)

DO_3SAME_GVEC4(VQSUB_S, sqsub_op)

DO_3SAME_GVEC4(VQSUB_U, uqsub_op)

+

+static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,

+ uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)

+{

+ tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,

+ 0, gen_helper_gvec_pmul_b);

+}

+

+static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)

+{

+ if (a->size != 0) {

+ return false;

+ }

+ return do_3same(s, a, gen_VMUL_p_3s);

+}

+

+#define DO_3SAME_GVEC3_NO_SZ_3(INSN, OPARRAY) \

+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \

+ uint32_t rn_ofs, uint32_t rm_ofs, \

+ uint32_t oprsz, uint32_t maxsz) \

+ { \

+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, \

+ oprsz, maxsz, &OPARRAY[vece]); \

+ } \

+ DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)

+

+

+DO_3SAME_GVEC3_NO_SZ_3(VMLA, mla_op)

+DO_3SAME_GVEC3_NO_SZ_3(VMLS, mls_op)

+

+#define DO_3SAME_GVEC3_SHIFT(INSN, OPARRAY) \

+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \

+ uint32_t rn_ofs, uint32_t rm_ofs, \

+ uint32_t oprsz, uint32_t maxsz) \

+ { \

+ /* Note the operation is vshl vd,vm,vn */ \

+ tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, \

+ oprsz, maxsz, &OPARRAY[vece]); \

+ } \

+ DO_3SAME(INSN, gen_##INSN##_3s)

+

+DO_3SAME_GVEC3_SHIFT(VSHL_S, sshl_op)

+DO_3SAME_GVEC3_SHIFT(VSHL_U, ushl_op)

diff --git a/target/arm/translate.c b/target/arm/translate.c

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)

}

return 1;

- case NEON_3R_VMUL: /* VMUL */

- if (u) {

- /* Polynomial case allows only P8. */

- if (size != 0) {

- return 1;

- }

- tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,

- 0, gen_helper_gvec_pmul_b);

- } else {

- tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs,

- vec_size, vec_size);

- }

- return 0;

-

- case NEON_3R_VML: /* VMLA, VMLS */

- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,

- u ? &mls_op[size] : &mla_op[size]);

- return 0;

-

- case NEON_3R_VSHL:

- /* Note the operation is vshl vd,vm,vn */

- tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,

- u ? &ushl_op[size] : &sshl_op[size]);

- return 0;

-

case NEON_3R_VADD_VSUB:

case NEON_3R_LOGIC:

case NEON_3R_VMAX:

@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)

case NEON_3R_VCGE:

case NEON_3R_VQADD:

case NEON_3R_VQSUB:

+ case NEON_3R_VMUL:

+ case NEON_3R_VML:

+ case NEON_3R_VSHL:

/* Already handled by decodetree */

return 1;

}

2.20.1

We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU

TLB. However we never actually use the TLB -- all stage 2 lookups

are done by direct calls to get_phys_addr_lpae() followed by a

physical address load via address_space_ld*().

Remove Stage2 from the list of ARM MMU indexes which correspond to

real core MMU indexes, and instead put it in the set of "NOTLB" ARM

MMU indexes.

This allows us to drop NB_MMU_MODES to 11. It also means we can

safely add support for the ARMv8.3-TTS2UXN extension, which adds

permission bits to the stage 2 descriptors which define execute

permission separatel for EL0 and EL1; supporting that while keeping

Stage2 in a QEMU TLB would require us to use separate TLBs for

"Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a

lot of extra complication given we aren't even using the QEMU TLB.

In the process of updating the comment on our MMU index use,

fix a couple of other minor errors:

* NS EL2 EL2&0 was missing from the list in the comment

* some text hadn't been updated from when we bumped NB_MMU_MODES

above 8

Message-id: 20200330210400.11724-2-peter.maydell@linaro.org

target/arm/cpu-param.h | 2 +-

target/arm/cpu.h | 21 +++++---

target/arm/helper.c | 112 ++++-------------------------------------

3 files changed, 27 insertions(+), 108 deletions(-)

@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);

* handling via the TLB. The only way to do a stage 1 translation without

* the immediate stage 2 translation is via the ATS or AT system insns,

* which can be slow-pathed and always do a page table walk.

+ * The only use of stage 2 translations is either as part of an s1+2

+ * lookup or when loading the descriptors during a stage 1 page table walk,

+ * and in both those cases we don't use the TLB.

* 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"

* translation regimes, because they map reasonably well to each other

* and they can't both be active at the same time.

@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);

* NS EL1 EL1&0 stage 1+2 (aka NS PL1)

* NS EL1 EL1&0 stage 1+2 +PAN

* NS EL0 EL2&0

+ * NS EL2 EL2&0

* NS EL2 EL2&0 +PAN

* NS EL2 (aka NS PL2)

* S EL0 EL1&0 (aka S PL0)

* S EL1 EL1&0 (not used if EL3 is 32 bit)

* S EL1 EL1&0 +PAN

* S EL3 (aka S PL1)

- * NS EL1&0 stage 2

*

- * for a total of 12 different mmu_idx.

+ * for a total of 11 different mmu_idx.

*

* R profile CPUs have an MPU, but can use the same set of MMU indexes

* as A profile. They only need to distinguish NS EL0 and NS EL1 (and

@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);

* are not quite the same -- different CPU types (most notably M profile

* vs A/R profile) would like to use MMU indexes with different semantics,

* but since we don't ever need to use all of those in a single CPU we

- * can avoid setting NB_MMU_MODES to more than 8. The lower bits of

+ * can avoid having to set NB_MMU_MODES to "total number of A profile MMU

+ * modes + total number of M profile MMU modes". The lower bits of

* ARMMMUIdx are the core TLB mmu index, and the higher bits are always

* the same for any particular CPU.

* Variables of type ARMMUIdx are always full values, and the core

@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {

ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,

ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A,

- ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A,

-

/*

* These are not allocated TLBs and are used only for AT system

* instructions or for the first stage of an S12 page table walk.

@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {

ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,

ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,

ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,

+ /*

+ * Not allocated a TLB: used only for second stage of an S12 page

+ * table walk, or for descriptor loads during first stage of an S1

+ * page table walk. Note that if we ever want to have a TLB for this

+ * then various TLB flush insns which currently are no-ops or flush

+ * only stage 1 MMU indexes will need to change to flush stage 2.

+ */

+ ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB,

/*

* M-profile.

@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {

TO_CORE_BIT(SE10_1),

TO_CORE_BIT(SE10_1_PAN),

TO_CORE_BIT(SE3),

- TO_CORE_BIT(Stage2),

TO_CORE_BIT(MUser),

TO_CORE_BIT(MPriv),

@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,

tlb_flush_by_mmuidx(cs,

ARMMMUIdxBit_E10_1 |

ARMMMUIdxBit_E10_1_PAN |

- ARMMMUIdxBit_E10_0 |

- ARMMMUIdxBit_Stage2);

+ ARMMMUIdxBit_E10_0);

}

static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,

@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,

tlb_flush_by_mmuidx_all_cpus_synced(cs,

ARMMMUIdxBit_E10_1 |

ARMMMUIdxBit_E10_1_PAN |

- ARMMMUIdxBit_E10_0 |

- ARMMMUIdxBit_Stage2);

+ ARMMMUIdxBit_E10_0);

}

-static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,

- uint64_t value)

-{

- /* Invalidate by IPA. This has to invalidate any structures that

- * contain only stage 2 translation information, but does not need

- * to apply to structures that contain combined stage 1 and stage 2

- * translation information.

- * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.

- */

- CPUState *cs = env_cpu(env);

- uint64_t pageaddr;

-

- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {

- return;

- }

-

- pageaddr = sextract64(value << 12, 0, 40);

-

- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);

-}

-

-static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,

- uint64_t value)

-{

- CPUState *cs = env_cpu(env);

- uint64_t pageaddr;

-

- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {

- return;

- }

-

- pageaddr = sextract64(value << 12, 0, 40);

-

- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,

- ARMMMUIdxBit_Stage2);

-}

static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,

uint64_t value)

@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,

tlb_flush_by_mmuidx(cs,

ARMMMUIdxBit_E10_1 |

ARMMMUIdxBit_E10_1_PAN |

- ARMMMUIdxBit_E10_0 |

- ARMMMUIdxBit_Stage2);

+ ARMMMUIdxBit_E10_0);

raw_write(env, ri, value);

}

}

@@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env)

return ARMMMUIdxBit_SE10_1 |

ARMMMUIdxBit_SE10_1_PAN |

ARMMMUIdxBit_SE10_0;

- } else if (arm_feature(env, ARM_FEATURE_EL2)) {

- return ARMMMUIdxBit_E10_1 |

- ARMMMUIdxBit_E10_1_PAN |

- ARMMMUIdxBit_E10_0 |

- ARMMMUIdxBit_Stage2;

} else {

return ARMMMUIdxBit_E10_1 |

ARMMMUIdxBit_E10_1_PAN |

@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,

ARMMMUIdxBit_SE3);

}

-static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,

- uint64_t value)

-{

- /* Invalidate by IPA. This has to invalidate any structures that

- * contain only stage 2 translation information, but does not need

- * to apply to structures that contain combined stage 1 and stage 2

- * translation information.

- * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.

- */

- ARMCPU *cpu = env_archcpu(env);

- CPUState *cs = CPU(cpu);

- uint64_t pageaddr;

-

- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {

- return;

- }

-

- pageaddr = sextract64(value << 12, 0, 48);

-

- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);

-}

-

-static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,

- uint64_t value)

-{

- CPUState *cs = env_cpu(env);

- uint64_t pageaddr;

-

- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {

- return;

- }

-

- pageaddr = sextract64(value << 12, 0, 48);

-

- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,

- ARMMMUIdxBit_Stage2);

-}

-

static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,

bool isread)

{

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {

.writefn = tlbi_aa64_vae1_write },

{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,

- .access = PL2_W, .type = ARM_CP_NO_RAW,

- .writefn = tlbi_aa64_ipas2e1is_write },

+ .access = PL2_W, .type = ARM_CP_NOP },

{ .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,

- .access = PL2_W, .type = ARM_CP_NO_RAW,

- .writefn = tlbi_aa64_ipas2e1is_write },

+ .access = PL2_W, .type = ARM_CP_NOP },

{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,

.access = PL2_W, .type = ARM_CP_NO_RAW,

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {

.writefn = tlbi_aa64_alle1is_write },

{ .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,

- .access = PL2_W, .type = ARM_CP_NO_RAW,

- .writefn = tlbi_aa64_ipas2e1_write },

+ .access = PL2_W, .type = ARM_CP_NOP },

{ .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,

- .access = PL2_W, .type = ARM_CP_NO_RAW,

- .writefn = tlbi_aa64_ipas2e1_write },

+ .access = PL2_W, .type = ARM_CP_NOP },

{ .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,

.access = PL2_W, .type = ARM_CP_NO_RAW,

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {

.writefn = tlbimva_hyp_is_write },

{ .name = "TLBIIPAS2",

.cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,

- .type = ARM_CP_NO_RAW, .access = PL2_W,

- .writefn = tlbiipas2_write },

+ .type = ARM_CP_NOP, .access = PL2_W },

{ .name = "TLBIIPAS2IS",

.cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,

- .type = ARM_CP_NO_RAW, .access = PL2_W,

- .writefn = tlbiipas2_is_write },

+ .type = ARM_CP_NOP, .access = PL2_W },

{ .name = "TLBIIPAS2L",

.cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,

- .type = ARM_CP_NO_RAW, .access = PL2_W,

- .writefn = tlbiipas2_write },

+ .type = ARM_CP_NOP, .access = PL2_W },

{ .name = "TLBIIPAS2LIS",

.cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,

- .type = ARM_CP_NO_RAW, .access = PL2_W,

- .writefn = tlbiipas2_is_write },

+ .type = ARM_CP_NOP, .access = PL2_W },

/* 32 bit cache operations */

{ .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,

.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },

2.20.1

Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping

to decodetree.

Message-id: 20200430181003.21682-19-peter.maydell@linaro.org

target/arm/neon-dp.decode | 6 ++++++

target/arm/translate-neon.inc.c | 15 +++++++++++++++

target/arm/translate.c | 14 ++------------

3 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode

--- a/target/arm/neon-dp.decode

+++ b/target/arm/neon-dp.decode

@@ -XXX,XX +XXX,XX @@

@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \

&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp

+VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same

+VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same

@3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \

&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0

@@ -XXX,XX +XXX,XX @@ VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic

VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic

VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic

+VQSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same

+VQSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same

+

VCGT_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same

VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same

VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same

diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-neon.inc.c

+++ b/target/arm/translate-neon.inc.c

@@ -XXX,XX +XXX,XX @@ static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,

tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);

}

DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)

+

+#define DO_3SAME_GVEC4(INSN, OPARRAY) \

+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \

+ uint32_t rn_ofs, uint32_t rm_ofs, \

+ uint32_t oprsz, uint32_t maxsz) \

+ { \

+ tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), \

+ rn_ofs, rm_ofs, oprsz, maxsz, &OPARRAY[vece]); \

+ } \

+ DO_3SAME(INSN, gen_##INSN##_3s)

+

+DO_3SAME_GVEC4(VQADD_S, sqadd_op)

+DO_3SAME_GVEC4(VQADD_U, uqadd_op)

+DO_3SAME_GVEC4(VQSUB_S, sqsub_op)

+DO_3SAME_GVEC4(VQSUB_U, uqsub_op)

diff --git a/target/arm/translate.c b/target/arm/translate.c