MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.

Represent it in QEMU's ARMCPU struct with a uint64_t, not a

uint32_t.

This fixes an error when compiling with -Werror=conversion

because we were manipulating the register value using a

local uint64_t variable:

target/arm/cpu64.c: In function ‘aarch64_max_initfn’:

target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]

628 | cpu->midr = t;

| ^

and future-proofs us against a possible future architecture

change using some of the top 32 bits.

Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Message-id: 20200428172634.29707-1-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

+/**

+ * get_phys_addr_lpae: perform one stage of page table walk, LPAE format

+ *

+ * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,

+ * prot and page_size may not be filled in, and the populated fsr value provides

+ * information on why the translation aborted, in the format of a long-format

+ * DFSR/IFSR fault register, with the following caveats:

+ * * the WnR bit is never set (the caller must do this).

+ *

+ * @env: CPUARMState

+ * @address: virtual address to get physical address for

+ * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH

+ * @mmu_idx: MMU index indicating required translation regime

+ * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table

+ * walk), must be true if this is stage 2 of a stage 1+2 walk for an

+ * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.

+ * @phys_ptr: set to the physical address corresponding to the virtual address

+ * @attrs: set to the memory transaction attributes to use

+ * @prot: set to the permissions for the page containing phys_ptr

+ * @page_size_ptr: set to the size of the page containing phys_ptr

+ * @fi: set to fault info if the translation fails

+ * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes

+ */

static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

MMUAccessType access_type, ARMMMUIdx mmu_idx,

+ bool s1_is_el0,

hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,

target_ulong *page_size_ptr,

ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)

@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,

/* S1 is done. Now do S2 translation. */

ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,

+ mmu_idx == ARMMMUIdx_E10_0,

phys_ptr, attrs, &s2_prot,

page_size, fi,

cacheattrs != NULL ? &cacheattrs2 : NULL);

@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,

}

if (regime_using_lpae_format(env, mmu_idx)) {

- return get_phys_addr_lpae(env, address, access_type, mmu_idx,

+ return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,

phys_ptr, attrs, prot, page_size,

fi, cacheattrs);

} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>