| 1 | Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups. | 1 | The following changes since commit b11728dc3ae67ddedf34b7a4f318170e7092803c: |
|---|---|---|---|
| 2 | 2 | ||
| 3 | thanks | 3 | Merge tag 'pull-riscv-to-apply-20230224' of github.com:palmer-dabbelt/qemu into staging (2023-02-26 20:14:46 +0000) |
| 4 | -- PMM | ||
| 5 | |||
| 6 | |||
| 7 | The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835: | ||
| 8 | |||
| 9 | Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100) | ||
| 10 | 4 | ||
| 11 | are available in the Git repository at: | 5 | are available in the Git repository at: |
| 12 | 6 | ||
| 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20230227 |
| 14 | 8 | ||
| 15 | for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211: | 9 | for you to fetch changes up to e844f0c5d0bd2c4d8d3c1622eb2a88586c9c4677: |
| 16 | 10 | ||
| 17 | target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100) | 11 | hw: Replace qemu_or_irq typedef by OrIRQState (2023-02-27 13:27:05 +0000) |
| 18 | 12 | ||
| 19 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
| 20 | target-arm queue: | 14 | target-arm queue: |
| 21 | * Start of conversion of Neon insns to decodetree | 15 | * Various code cleanups |
| 22 | * versal board: support SD and RTC | 16 | * More refactoring working towards allowing a build |
| 23 | * Implement ARMv8.2-TTS2UXN | 17 | without CONFIG_TCG |
| 24 | * Make VQDMULL undefined when U=1 | ||
| 25 | * Some minor code cleanups | ||
| 26 | 18 | ||
| 27 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
| 28 | Edgar E. Iglesias (11): | 20 | Claudio Fontana (2): |
| 29 | hw/arm: versal: Remove inclusion of arm_gicv3_common.h | 21 | target/arm: move helpers to tcg/ |
| 30 | hw/arm: versal: Move misplaced comment | 22 | target/arm: Move psci.c into the tcg directory |
| 31 | hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal | ||
| 32 | hw/arm: versal: Embed the UARTs into the SoC type | ||
| 33 | hw/arm: versal: Embed the GEMs into the SoC type | ||
| 34 | hw/arm: versal: Embed the ADMAs into the SoC type | ||
| 35 | hw/arm: versal: Embed the APUs into the SoC type | ||
| 36 | hw/arm: versal: Add support for SD | ||
| 37 | hw/arm: versal: Add support for the RTC | ||
| 38 | hw/arm: versal-virt: Add support for SD | ||
| 39 | hw/arm: versal-virt: Add support for the RTC | ||
| 40 | 23 | ||
| 41 | Fredrik Strupe (1): | 24 | Fabiano Rosas (9): |
| 42 | target/arm: Make VQDMULL undefined when U=1 | 25 | target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled |
| 26 | target/arm: Wrap TCG-only code in debug_helper.c | ||
| 27 | target/arm: move translate modules to tcg/ | ||
| 28 | target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled | ||
| 29 | target/arm: Move hflags code into the tcg directory | ||
| 30 | target/arm: Move regime_using_lpae_format into internal.h | ||
| 31 | target/arm: Don't access TCG code when debugging with KVM | ||
| 32 | cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code | ||
| 33 | tests/avocado: add machine:none tag to version.py | ||
| 43 | 34 | ||
| 44 | Peter Maydell (25): | 35 | Philippe Mathieu-Daudé (13): |
| 45 | target/arm: Don't use a TLB for ARMMMUIdx_Stage2 | 36 | hw/gpio/max7310: Simplify max7310_realize() |
| 46 | target/arm: Use enum constant in get_phys_addr_lpae() call | 37 | hw/char/pl011: Un-inline pl011_create() |
| 47 | target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae() | 38 | hw/char/pl011: Open-code pl011_luminary_create() |
| 48 | target/arm: Implement ARMv8.2-TTS2UXN | 39 | hw/char/xilinx_uartlite: Expose XILINX_UARTLITE QOM type |
| 49 | target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0 | 40 | hw/char/xilinx_uartlite: Open-code xilinx_uartlite_create() |
| 50 | target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check | 41 | hw/char/cmsdk-apb-uart: Open-code cmsdk_apb_uart_create() |
| 51 | target/arm: Don't allow Thumb Neon insns without FEATURE_NEON | 42 | hw/timer/cmsdk-apb-timer: Remove unused 'qdev-properties.h' header |
| 52 | target/arm: Add stubs for AArch32 Neon decodetree | 43 | hw/intc/armv7m_nvic: Use QOM cast CPU() macro |
| 53 | target/arm: Convert VCMLA (vector) to decodetree | 44 | hw/arm/musicpal: Remove unused dummy MemoryRegion |
| 54 | target/arm: Convert VCADD (vector) to decodetree | 45 | iothread: Remove unused IOThreadClass / IOTHREAD_CLASS |
| 55 | target/arm: Convert V[US]DOT (vector) to decodetree | 46 | hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() |
| 56 | target/arm: Convert VFM[AS]L (vector) to decodetree | 47 | hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() |
| 57 | target/arm: Convert VCMLA (scalar) to decodetree | 48 | hw: Replace qemu_or_irq typedef by OrIRQState |
| 58 | target/arm: Convert V[US]DOT (scalar) to decodetree | ||
| 59 | target/arm: Convert VFM[AS]L (scalar) to decodetree | ||
| 60 | target/arm: Convert Neon load/store multiple structures to decodetree | ||
| 61 | target/arm: Convert Neon 'load single structure to all lanes' to decodetree | ||
| 62 | target/arm: Convert Neon 'load/store single structure' to decodetree | ||
| 63 | target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree | ||
| 64 | target/arm: Convert Neon 3-reg-same logic ops to decodetree | ||
| 65 | target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree | ||
| 66 | target/arm: Convert Neon 3-reg-same comparisons to decodetree | ||
| 67 | target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree | ||
| 68 | target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree | ||
| 69 | target/arm: Move gen_ function typedefs to translate.h | ||
| 70 | 49 | ||
| 71 | Philippe Mathieu-Daudé (2): | 50 | Thomas Huth (1): |
| 72 | hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string | 51 | include/hw/arm/allwinner-a10.h: Remove superfluous includes from the header |
| 73 | target/arm: Use uint64_t for midr field in CPU state struct | ||
| 74 | 52 | ||
| 75 | include/hw/arm/xlnx-versal.h | 31 +- | 53 | MAINTAINERS | 1 + |
| 76 | target/arm/cpu-param.h | 2 +- | 54 | include/exec/cpu-defs.h | 6 + |
| 77 | target/arm/cpu.h | 38 ++- | 55 | include/hw/arm/allwinner-a10.h | 2 - |
| 78 | target/arm/translate-a64.h | 9 - | 56 | include/hw/arm/armsse.h | 6 +- |
| 79 | target/arm/translate.h | 26 ++ | 57 | include/hw/arm/bcm2835_peripherals.h | 2 +- |
| 80 | target/arm/neon-dp.decode | 86 +++++ | 58 | include/hw/arm/exynos4210.h | 4 +- |
| 81 | target/arm/neon-ls.decode | 52 +++ | 59 | include/hw/arm/stm32f205_soc.h | 2 +- |
| 82 | target/arm/neon-shared.decode | 66 ++++ | 60 | include/hw/arm/stm32f405_soc.h | 2 +- |
| 83 | hw/arm/mps2-tz.c | 2 +- | 61 | include/hw/arm/xlnx-versal.h | 6 +- |
| 84 | hw/arm/xlnx-versal-virt.c | 74 ++++- | 62 | include/hw/arm/xlnx-zynqmp.h | 2 +- |
| 85 | hw/arm/xlnx-versal.c | 115 +++++-- | 63 | include/hw/char/cmsdk-apb-uart.h | 34 --- |
| 86 | target/arm/cpu.c | 3 +- | 64 | include/hw/char/pl011.h | 36 +-- |
| 87 | target/arm/cpu64.c | 8 +- | 65 | include/hw/char/xilinx_uartlite.h | 22 +- |
| 88 | target/arm/helper.c | 183 ++++------ | 66 | include/hw/or-irq.h | 5 +- |
| 89 | target/arm/translate-a64.c | 17 - | 67 | include/hw/timer/cmsdk-apb-timer.h | 1 - |
| 90 | target/arm/translate-neon.inc.c | 714 +++++++++++++++++++++++++++++++++++++++ | 68 | target/arm/internals.h | 23 +- |
| 91 | target/arm/translate-vfp.inc.c | 6 - | 69 | target/arm/{ => tcg}/translate-a64.h | 0 |
| 92 | target/arm/translate.c | 716 +++------------------------------------- | 70 | target/arm/{ => tcg}/translate.h | 0 |
| 93 | target/arm/Makefile.objs | 18 + | 71 | target/arm/{ => tcg}/vec_internal.h | 0 |
| 94 | 19 files changed, 1302 insertions(+), 864 deletions(-) | 72 | target/arm/{ => tcg}/a32-uncond.decode | 0 |
| 95 | create mode 100644 target/arm/neon-dp.decode | 73 | target/arm/{ => tcg}/a32.decode | 0 |
| 96 | create mode 100644 target/arm/neon-ls.decode | 74 | target/arm/{ => tcg}/m-nocp.decode | 0 |
| 97 | create mode 100644 target/arm/neon-shared.decode | 75 | target/arm/{ => tcg}/mve.decode | 0 |
| 98 | create mode 100644 target/arm/translate-neon.inc.c | 76 | target/arm/{ => tcg}/neon-dp.decode | 0 |
| 77 | target/arm/{ => tcg}/neon-ls.decode | 0 | ||
| 78 | target/arm/{ => tcg}/neon-shared.decode | 0 | ||
| 79 | target/arm/{ => tcg}/sme-fa64.decode | 0 | ||
| 80 | target/arm/{ => tcg}/sme.decode | 0 | ||
| 81 | target/arm/{ => tcg}/sve.decode | 0 | ||
| 82 | target/arm/{ => tcg}/t16.decode | 0 | ||
| 83 | target/arm/{ => tcg}/t32.decode | 0 | ||
| 84 | target/arm/{ => tcg}/vfp-uncond.decode | 0 | ||
| 85 | target/arm/{ => tcg}/vfp.decode | 0 | ||
| 86 | hw/arm/allwinner-a10.c | 1 + | ||
| 87 | hw/arm/boot.c | 6 +- | ||
| 88 | hw/arm/exynos4210.c | 4 +- | ||
| 89 | hw/arm/mps2-tz.c | 2 +- | ||
| 90 | hw/arm/mps2.c | 41 ++- | ||
| 91 | hw/arm/musicpal.c | 4 - | ||
| 92 | hw/arm/stellaris.c | 11 +- | ||
| 93 | hw/char/pl011.c | 17 ++ | ||
| 94 | hw/char/xilinx_uartlite.c | 4 +- | ||
| 95 | hw/core/irq.c | 9 +- | ||
| 96 | hw/core/or-irq.c | 18 +- | ||
| 97 | hw/gpio/max7310.c | 5 +- | ||
| 98 | hw/intc/armv7m_nvic.c | 26 +- | ||
| 99 | hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 +- | ||
| 100 | hw/pci-host/raven.c | 2 +- | ||
| 101 | iothread.c | 4 - | ||
| 102 | target/arm/arm-powerctl.c | 7 +- | ||
| 103 | target/arm/cpu.c | 9 +- | ||
| 104 | target/arm/debug_helper.c | 490 ++++++++++++++++--------------- | ||
| 105 | target/arm/helper.c | 411 +------------------------- | ||
| 106 | target/arm/machine.c | 12 +- | ||
| 107 | target/arm/ptw.c | 4 + | ||
| 108 | target/arm/tcg-stubs.c | 27 ++ | ||
| 109 | target/arm/{ => tcg}/crypto_helper.c | 0 | ||
| 110 | target/arm/{ => tcg}/helper-a64.c | 0 | ||
| 111 | target/arm/tcg/hflags.c | 403 +++++++++++++++++++++++++ | ||
| 112 | target/arm/{ => tcg}/iwmmxt_helper.c | 0 | ||
| 113 | target/arm/{ => tcg}/m_helper.c | 0 | ||
| 114 | target/arm/{ => tcg}/mte_helper.c | 0 | ||
| 115 | target/arm/{ => tcg}/mve_helper.c | 0 | ||
| 116 | target/arm/{ => tcg}/neon_helper.c | 0 | ||
| 117 | target/arm/{ => tcg}/op_helper.c | 0 | ||
| 118 | target/arm/{ => tcg}/pauth_helper.c | 0 | ||
| 119 | target/arm/{ => tcg}/psci.c | 0 | ||
| 120 | target/arm/{ => tcg}/sme_helper.c | 0 | ||
| 121 | target/arm/{ => tcg}/sve_helper.c | 0 | ||
| 122 | target/arm/{ => tcg}/tlb_helper.c | 18 -- | ||
| 123 | target/arm/{ => tcg}/translate-a64.c | 0 | ||
| 124 | target/arm/{ => tcg}/translate-m-nocp.c | 0 | ||
| 125 | target/arm/{ => tcg}/translate-mve.c | 0 | ||
| 126 | target/arm/{ => tcg}/translate-neon.c | 0 | ||
| 127 | target/arm/{ => tcg}/translate-sme.c | 0 | ||
| 128 | target/arm/{ => tcg}/translate-sve.c | 0 | ||
| 129 | target/arm/{ => tcg}/translate-vfp.c | 0 | ||
| 130 | target/arm/{ => tcg}/translate.c | 0 | ||
| 131 | target/arm/{ => tcg}/vec_helper.c | 0 | ||
| 132 | target/arm/meson.build | 46 +-- | ||
| 133 | target/arm/tcg/meson.build | 50 ++++ | ||
| 134 | tests/avocado/version.py | 1 + | ||
| 135 | 82 files changed, 918 insertions(+), 875 deletions(-) | ||
| 136 | rename target/arm/{ => tcg}/translate-a64.h (100%) | ||
| 137 | rename target/arm/{ => tcg}/translate.h (100%) | ||
| 138 | rename target/arm/{ => tcg}/vec_internal.h (100%) | ||
| 139 | rename target/arm/{ => tcg}/a32-uncond.decode (100%) | ||
| 140 | rename target/arm/{ => tcg}/a32.decode (100%) | ||
| 141 | rename target/arm/{ => tcg}/m-nocp.decode (100%) | ||
| 142 | rename target/arm/{ => tcg}/mve.decode (100%) | ||
| 143 | rename target/arm/{ => tcg}/neon-dp.decode (100%) | ||
| 144 | rename target/arm/{ => tcg}/neon-ls.decode (100%) | ||
| 145 | rename target/arm/{ => tcg}/neon-shared.decode (100%) | ||
| 146 | rename target/arm/{ => tcg}/sme-fa64.decode (100%) | ||
| 147 | rename target/arm/{ => tcg}/sme.decode (100%) | ||
| 148 | rename target/arm/{ => tcg}/sve.decode (100%) | ||
| 149 | rename target/arm/{ => tcg}/t16.decode (100%) | ||
| 150 | rename target/arm/{ => tcg}/t32.decode (100%) | ||
| 151 | rename target/arm/{ => tcg}/vfp-uncond.decode (100%) | ||
| 152 | rename target/arm/{ => tcg}/vfp.decode (100%) | ||
| 153 | create mode 100644 target/arm/tcg-stubs.c | ||
| 154 | rename target/arm/{ => tcg}/crypto_helper.c (100%) | ||
| 155 | rename target/arm/{ => tcg}/helper-a64.c (100%) | ||
| 156 | create mode 100644 target/arm/tcg/hflags.c | ||
| 157 | rename target/arm/{ => tcg}/iwmmxt_helper.c (100%) | ||
| 158 | rename target/arm/{ => tcg}/m_helper.c (100%) | ||
| 159 | rename target/arm/{ => tcg}/mte_helper.c (100%) | ||
| 160 | rename target/arm/{ => tcg}/mve_helper.c (100%) | ||
| 161 | rename target/arm/{ => tcg}/neon_helper.c (100%) | ||
| 162 | rename target/arm/{ => tcg}/op_helper.c (100%) | ||
| 163 | rename target/arm/{ => tcg}/pauth_helper.c (100%) | ||
| 164 | rename target/arm/{ => tcg}/psci.c (100%) | ||
| 165 | rename target/arm/{ => tcg}/sme_helper.c (100%) | ||
| 166 | rename target/arm/{ => tcg}/sve_helper.c (100%) | ||
| 167 | rename target/arm/{ => tcg}/tlb_helper.c (94%) | ||
| 168 | rename target/arm/{ => tcg}/translate-a64.c (100%) | ||
| 169 | rename target/arm/{ => tcg}/translate-m-nocp.c (100%) | ||
| 170 | rename target/arm/{ => tcg}/translate-mve.c (100%) | ||
| 171 | rename target/arm/{ => tcg}/translate-neon.c (100%) | ||
| 172 | rename target/arm/{ => tcg}/translate-sme.c (100%) | ||
| 173 | rename target/arm/{ => tcg}/translate-sve.c (100%) | ||
| 174 | rename target/arm/{ => tcg}/translate-vfp.c (100%) | ||
| 175 | rename target/arm/{ => tcg}/translate.c (100%) | ||
| 176 | rename target/arm/{ => tcg}/vec_helper.c (100%) | ||
| 177 | create mode 100644 target/arm/tcg/meson.build | ||
| 99 | 178 | diff view generated by jsdifflib |
| 1 | We're going to want at least some of the NeonGen* typedefs | 1 | From: Thomas Huth <thuth@redhat.com> |
|---|---|---|---|
| 2 | for the refactored 32-bit Neon decoder, so move them all | ||
| 3 | to translate.h since it makes more sense to keep them in | ||
| 4 | one group. | ||
| 5 | 2 | ||
| 3 | pci_device.h is not needed at all in allwinner-a10.h, and serial.h | ||
| 4 | is only needed by the corresponding .c file. | ||
| 5 | |||
| 6 | Signed-off-by: Thomas Huth <thuth@redhat.com> | ||
| 7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 8 | Message-id: 20230215152233.210024-1-thuth@redhat.com | ||
| 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20200430181003.21682-23-peter.maydell@linaro.org | ||
| 9 | --- | 10 | --- |
| 10 | target/arm/translate.h | 17 +++++++++++++++++ | 11 | include/hw/arm/allwinner-a10.h | 2 -- |
| 11 | target/arm/translate-a64.c | 17 ----------------- | 12 | hw/arm/allwinner-a10.c | 1 + |
| 12 | 2 files changed, 17 insertions(+), 17 deletions(-) | 13 | 2 files changed, 1 insertion(+), 2 deletions(-) |
| 13 | 14 | ||
| 14 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 15 | diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h |
| 15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/arm/translate.h | 17 | --- a/include/hw/arm/allwinner-a10.h |
| 17 | +++ b/target/arm/translate.h | 18 | +++ b/include/hw/arm/allwinner-a10.h |
| 18 | @@ -XXX,XX +XXX,XX @@ typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, | 19 | @@ -XXX,XX +XXX,XX @@ |
| 19 | typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t, | 20 | #ifndef HW_ARM_ALLWINNER_A10_H |
| 20 | uint32_t, uint32_t, uint32_t); | 21 | #define HW_ARM_ALLWINNER_A10_H |
| 21 | 22 | ||
| 22 | +/* Function prototype for gen_ functions for calling Neon helpers */ | 23 | -#include "hw/char/serial.h" |
| 23 | +typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); | 24 | #include "hw/arm/boot.h" |
| 24 | +typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); | 25 | -#include "hw/pci/pci_device.h" |
| 25 | +typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); | 26 | #include "hw/timer/allwinner-a10-pit.h" |
| 26 | +typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); | 27 | #include "hw/intc/allwinner-a10-pic.h" |
| 27 | +typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); | 28 | #include "hw/net/allwinner_emac.h" |
| 28 | +typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); | 29 | diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c |
| 29 | +typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); | ||
| 30 | +typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); | ||
| 31 | +typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); | ||
| 32 | +typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | ||
| 33 | +typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); | ||
| 34 | +typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); | ||
| 35 | +typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
| 36 | +typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
| 37 | +typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
| 38 | + | ||
| 39 | #endif /* TARGET_ARM_TRANSLATE_H */ | ||
| 40 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
| 41 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
| 42 | --- a/target/arm/translate-a64.c | 31 | --- a/hw/arm/allwinner-a10.c |
| 43 | +++ b/target/arm/translate-a64.c | 32 | +++ b/hw/arm/allwinner-a10.c |
| 44 | @@ -XXX,XX +XXX,XX @@ typedef struct AArch64DecodeTable { | 33 | @@ -XXX,XX +XXX,XX @@ |
| 45 | AArch64DecodeFn *disas_fn; | 34 | #include "qemu/osdep.h" |
| 46 | } AArch64DecodeTable; | 35 | #include "qapi/error.h" |
| 47 | 36 | #include "qemu/module.h" | |
| 48 | -/* Function prototype for gen_ functions for calling Neon helpers */ | 37 | +#include "hw/char/serial.h" |
| 49 | -typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); | 38 | #include "hw/sysbus.h" |
| 50 | -typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); | 39 | #include "hw/arm/allwinner-a10.h" |
| 51 | -typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); | 40 | #include "hw/misc/unimp.h" |
| 52 | -typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); | ||
| 53 | -typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); | ||
| 54 | -typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); | ||
| 55 | -typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); | ||
| 56 | -typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); | ||
| 57 | -typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); | ||
| 58 | -typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); | ||
| 59 | -typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); | ||
| 60 | -typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); | ||
| 61 | -typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
| 62 | -typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
| 63 | -typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); | ||
| 64 | - | ||
| 65 | /* initialize TCG globals. */ | ||
| 66 | void a64_translate_init(void) | ||
| 67 | { | ||
| 68 | -- | 41 | -- |
| 69 | 2.20.1 | 42 | 2.34.1 |
| 70 | 43 | ||
| 71 | 44 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0. | 3 | This is in preparation for restricting compilation of some parts of |
| 4 | Represent it in QEMU's ARMCPU struct with a uint64_t, not a | 4 | debug_helper.c to TCG only. |
| 5 | uint32_t. | ||
| 6 | 5 | ||
| 7 | This fixes an error when compiling with -Werror=conversion | 6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
| 8 | because we were manipulating the register value using a | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | local uint64_t variable: | ||
| 10 | |||
| 11 | target/arm/cpu64.c: In function ‘aarch64_max_initfn’: | ||
| 12 | target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion] | ||
| 13 | 628 | cpu->midr = t; | ||
| 14 | | ^ | ||
| 15 | |||
| 16 | and future-proofs us against a possible future architecture | ||
| 17 | change using some of the top 32 bits. | ||
| 18 | |||
| 19 | Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
| 20 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 21 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 22 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
| 23 | Message-id: 20200428172634.29707-1-f4bug@amsat.org | ||
| 24 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 25 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 26 | --- | 9 | --- |
| 27 | target/arm/cpu.h | 2 +- | 10 | target/arm/cpu.c | 6 ++++-- |
| 28 | target/arm/cpu.c | 2 +- | 11 | target/arm/debug_helper.c | 16 ++++++++++++---- |
| 29 | 2 files changed, 2 insertions(+), 2 deletions(-) | 12 | target/arm/machine.c | 7 +++++-- |
| 13 | 3 files changed, 21 insertions(+), 8 deletions(-) | ||
| 30 | 14 | ||
| 31 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
| 32 | index XXXXXXX..XXXXXXX 100644 | ||
| 33 | --- a/target/arm/cpu.h | ||
| 34 | +++ b/target/arm/cpu.h | ||
| 35 | @@ -XXX,XX +XXX,XX @@ struct ARMCPU { | ||
| 36 | uint64_t id_aa64dfr0; | ||
| 37 | uint64_t id_aa64dfr1; | ||
| 38 | } isar; | ||
| 39 | - uint32_t midr; | ||
| 40 | + uint64_t midr; | ||
| 41 | uint32_t revidr; | ||
| 42 | uint32_t reset_fpsid; | ||
| 43 | uint32_t ctr; | ||
| 44 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 15 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
| 45 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 46 | --- a/target/arm/cpu.c | 17 | --- a/target/arm/cpu.c |
| 47 | +++ b/target/arm/cpu.c | 18 | +++ b/target/arm/cpu.c |
| 48 | @@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = { | 19 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj) |
| 49 | static Property arm_cpu_properties[] = { | 20 | } |
| 50 | DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false), | 21 | #endif |
| 51 | DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), | 22 | |
| 52 | - DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), | 23 | - hw_breakpoint_update_all(cpu); |
| 53 | + DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), | 24 | - hw_watchpoint_update_all(cpu); |
| 54 | DEFINE_PROP_UINT64("mp-affinity", ARMCPU, | 25 | + if (tcg_enabled()) { |
| 55 | mp_affinity, ARM64_AFFINITY_INVALID), | 26 | + hw_breakpoint_update_all(cpu); |
| 56 | DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), | 27 | + hw_watchpoint_update_all(cpu); |
| 28 | + } | ||
| 29 | arm_rebuild_hflags(env); | ||
| 30 | } | ||
| 31 | |||
| 32 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | ||
| 34 | --- a/target/arm/debug_helper.c | ||
| 35 | +++ b/target/arm/debug_helper.c | ||
| 36 | @@ -XXX,XX +XXX,XX @@ static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 37 | value &= ~3ULL; | ||
| 38 | |||
| 39 | raw_write(env, ri, value); | ||
| 40 | - hw_watchpoint_update(cpu, i); | ||
| 41 | + if (tcg_enabled()) { | ||
| 42 | + hw_watchpoint_update(cpu, i); | ||
| 43 | + } | ||
| 44 | } | ||
| 45 | |||
| 46 | static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 47 | @@ -XXX,XX +XXX,XX @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 48 | int i = ri->crm; | ||
| 49 | |||
| 50 | raw_write(env, ri, value); | ||
| 51 | - hw_watchpoint_update(cpu, i); | ||
| 52 | + if (tcg_enabled()) { | ||
| 53 | + hw_watchpoint_update(cpu, i); | ||
| 54 | + } | ||
| 55 | } | ||
| 56 | |||
| 57 | void hw_breakpoint_update(ARMCPU *cpu, int n) | ||
| 58 | @@ -XXX,XX +XXX,XX @@ static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 59 | int i = ri->crm; | ||
| 60 | |||
| 61 | raw_write(env, ri, value); | ||
| 62 | - hw_breakpoint_update(cpu, i); | ||
| 63 | + if (tcg_enabled()) { | ||
| 64 | + hw_breakpoint_update(cpu, i); | ||
| 65 | + } | ||
| 66 | } | ||
| 67 | |||
| 68 | static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 69 | @@ -XXX,XX +XXX,XX @@ static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 70 | value = deposit64(value, 8, 1, extract64(value, 7, 1)); | ||
| 71 | |||
| 72 | raw_write(env, ri, value); | ||
| 73 | - hw_breakpoint_update(cpu, i); | ||
| 74 | + if (tcg_enabled()) { | ||
| 75 | + hw_breakpoint_update(cpu, i); | ||
| 76 | + } | ||
| 77 | } | ||
| 78 | |||
| 79 | void define_debug_regs(ARMCPU *cpu) | ||
| 80 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
| 81 | index XXXXXXX..XXXXXXX 100644 | ||
| 82 | --- a/target/arm/machine.c | ||
| 83 | +++ b/target/arm/machine.c | ||
| 84 | @@ -XXX,XX +XXX,XX @@ | ||
| 85 | #include "cpu.h" | ||
| 86 | #include "qemu/error-report.h" | ||
| 87 | #include "sysemu/kvm.h" | ||
| 88 | +#include "sysemu/tcg.h" | ||
| 89 | #include "kvm_arm.h" | ||
| 90 | #include "internals.h" | ||
| 91 | #include "migration/cpu.h" | ||
| 92 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) | ||
| 93 | return -1; | ||
| 94 | } | ||
| 95 | |||
| 96 | - hw_breakpoint_update_all(cpu); | ||
| 97 | - hw_watchpoint_update_all(cpu); | ||
| 98 | + if (tcg_enabled()) { | ||
| 99 | + hw_breakpoint_update_all(cpu); | ||
| 100 | + hw_watchpoint_update_all(cpu); | ||
| 101 | + } | ||
| 102 | |||
| 103 | /* | ||
| 104 | * TCG gen_update_fp_context() relies on the invariant that | ||
| 57 | -- | 105 | -- |
| 58 | 2.20.1 | 106 | 2.34.1 |
| 59 | |||
| 60 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add support for SD. | 3 | The next few patches will move helpers under CONFIG_TCG. We'd prefer |
| 4 | to keep the debug helpers and debug registers close together, so | ||
| 5 | rearrange the file a bit to be able to wrap the helpers with a TCG | ||
| 6 | ifdef. | ||
| 4 | 7 | ||
| 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 8 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
| 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
| 8 | Message-id: 20200427181649.26851-11-edgar.iglesias@gmail.com | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | --- | 11 | --- |
| 11 | hw/arm/xlnx-versal-virt.c | 46 +++++++++++++++++++++++++++++++++++++++ | 12 | target/arm/debug_helper.c | 476 +++++++++++++++++++------------------- |
| 12 | 1 file changed, 46 insertions(+) | 13 | 1 file changed, 239 insertions(+), 237 deletions(-) |
| 13 | 14 | ||
| 14 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | 15 | diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/arm/xlnx-versal-virt.c | 17 | --- a/target/arm/debug_helper.c |
| 17 | +++ b/hw/arm/xlnx-versal-virt.c | 18 | +++ b/target/arm/debug_helper.c |
| 18 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ |
| 19 | #include "hw/arm/sysbus-fdt.h" | 20 | #include "cpregs.h" |
| 20 | #include "hw/arm/fdt.h" | 21 | #include "exec/exec-all.h" |
| 21 | #include "cpu.h" | 22 | #include "exec/helper-proto.h" |
| 22 | +#include "hw/qdev-properties.h" | 23 | +#include "sysemu/tcg.h" |
| 23 | #include "hw/arm/xlnx-versal.h" | 24 | |
| 24 | 25 | - | |
| 25 | #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") | 26 | +#ifdef CONFIG_TCG |
| 26 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_zdma_nodes(VersalVirt *s) | 27 | /* Return the Exception Level targeted by debug exceptions. */ |
| 28 | static int arm_debug_target_el(CPUARMState *env) | ||
| 29 | { | ||
| 30 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) | ||
| 31 | raise_exception_debug(env, EXCP_UDEF, syndrome); | ||
| 32 | } | ||
| 33 | |||
| 34 | +void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
| 35 | +{ | ||
| 36 | + CPUARMState *env = &cpu->env; | ||
| 37 | + vaddr len = 0; | ||
| 38 | + vaddr wvr = env->cp15.dbgwvr[n]; | ||
| 39 | + uint64_t wcr = env->cp15.dbgwcr[n]; | ||
| 40 | + int mask; | ||
| 41 | + int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | ||
| 42 | + | ||
| 43 | + if (env->cpu_watchpoint[n]) { | ||
| 44 | + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | ||
| 45 | + env->cpu_watchpoint[n] = NULL; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + if (!FIELD_EX64(wcr, DBGWCR, E)) { | ||
| 49 | + /* E bit clear : watchpoint disabled */ | ||
| 50 | + return; | ||
| 51 | + } | ||
| 52 | + | ||
| 53 | + switch (FIELD_EX64(wcr, DBGWCR, LSC)) { | ||
| 54 | + case 0: | ||
| 55 | + /* LSC 00 is reserved and must behave as if the wp is disabled */ | ||
| 56 | + return; | ||
| 57 | + case 1: | ||
| 58 | + flags |= BP_MEM_READ; | ||
| 59 | + break; | ||
| 60 | + case 2: | ||
| 61 | + flags |= BP_MEM_WRITE; | ||
| 62 | + break; | ||
| 63 | + case 3: | ||
| 64 | + flags |= BP_MEM_ACCESS; | ||
| 65 | + break; | ||
| 66 | + } | ||
| 67 | + | ||
| 68 | + /* | ||
| 69 | + * Attempts to use both MASK and BAS fields simultaneously are | ||
| 70 | + * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | ||
| 71 | + * thus generating a watchpoint for every byte in the masked region. | ||
| 72 | + */ | ||
| 73 | + mask = FIELD_EX64(wcr, DBGWCR, MASK); | ||
| 74 | + if (mask == 1 || mask == 2) { | ||
| 75 | + /* | ||
| 76 | + * Reserved values of MASK; we must act as if the mask value was | ||
| 77 | + * some non-reserved value, or as if the watchpoint were disabled. | ||
| 78 | + * We choose the latter. | ||
| 79 | + */ | ||
| 80 | + return; | ||
| 81 | + } else if (mask) { | ||
| 82 | + /* Watchpoint covers an aligned area up to 2GB in size */ | ||
| 83 | + len = 1ULL << mask; | ||
| 84 | + /* | ||
| 85 | + * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | ||
| 86 | + * whether the watchpoint fires when the unmasked bits match; we opt | ||
| 87 | + * to generate the exceptions. | ||
| 88 | + */ | ||
| 89 | + wvr &= ~(len - 1); | ||
| 90 | + } else { | ||
| 91 | + /* Watchpoint covers bytes defined by the byte address select bits */ | ||
| 92 | + int bas = FIELD_EX64(wcr, DBGWCR, BAS); | ||
| 93 | + int basstart; | ||
| 94 | + | ||
| 95 | + if (extract64(wvr, 2, 1)) { | ||
| 96 | + /* | ||
| 97 | + * Deprecated case of an only 4-aligned address. BAS[7:4] are | ||
| 98 | + * ignored, and BAS[3:0] define which bytes to watch. | ||
| 99 | + */ | ||
| 100 | + bas &= 0xf; | ||
| 101 | + } | ||
| 102 | + | ||
| 103 | + if (bas == 0) { | ||
| 104 | + /* This must act as if the watchpoint is disabled */ | ||
| 105 | + return; | ||
| 106 | + } | ||
| 107 | + | ||
| 108 | + /* | ||
| 109 | + * The BAS bits are supposed to be programmed to indicate a contiguous | ||
| 110 | + * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | ||
| 111 | + * we fire for each byte in the word/doubleword addressed by the WVR. | ||
| 112 | + * We choose to ignore any non-zero bits after the first range of 1s. | ||
| 113 | + */ | ||
| 114 | + basstart = ctz32(bas); | ||
| 115 | + len = cto32(bas >> basstart); | ||
| 116 | + wvr += basstart; | ||
| 117 | + } | ||
| 118 | + | ||
| 119 | + cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | ||
| 120 | + &env->cpu_watchpoint[n]); | ||
| 121 | +} | ||
| 122 | + | ||
| 123 | +void hw_watchpoint_update_all(ARMCPU *cpu) | ||
| 124 | +{ | ||
| 125 | + int i; | ||
| 126 | + CPUARMState *env = &cpu->env; | ||
| 127 | + | ||
| 128 | + /* | ||
| 129 | + * Completely clear out existing QEMU watchpoints and our array, to | ||
| 130 | + * avoid possible stale entries following migration load. | ||
| 131 | + */ | ||
| 132 | + cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | ||
| 133 | + memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | ||
| 134 | + | ||
| 135 | + for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | ||
| 136 | + hw_watchpoint_update(cpu, i); | ||
| 137 | + } | ||
| 138 | +} | ||
| 139 | + | ||
| 140 | +void hw_breakpoint_update(ARMCPU *cpu, int n) | ||
| 141 | +{ | ||
| 142 | + CPUARMState *env = &cpu->env; | ||
| 143 | + uint64_t bvr = env->cp15.dbgbvr[n]; | ||
| 144 | + uint64_t bcr = env->cp15.dbgbcr[n]; | ||
| 145 | + vaddr addr; | ||
| 146 | + int bt; | ||
| 147 | + int flags = BP_CPU; | ||
| 148 | + | ||
| 149 | + if (env->cpu_breakpoint[n]) { | ||
| 150 | + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); | ||
| 151 | + env->cpu_breakpoint[n] = NULL; | ||
| 152 | + } | ||
| 153 | + | ||
| 154 | + if (!extract64(bcr, 0, 1)) { | ||
| 155 | + /* E bit clear : watchpoint disabled */ | ||
| 156 | + return; | ||
| 157 | + } | ||
| 158 | + | ||
| 159 | + bt = extract64(bcr, 20, 4); | ||
| 160 | + | ||
| 161 | + switch (bt) { | ||
| 162 | + case 4: /* unlinked address mismatch (reserved if AArch64) */ | ||
| 163 | + case 5: /* linked address mismatch (reserved if AArch64) */ | ||
| 164 | + qemu_log_mask(LOG_UNIMP, | ||
| 165 | + "arm: address mismatch breakpoint types not implemented\n"); | ||
| 166 | + return; | ||
| 167 | + case 0: /* unlinked address match */ | ||
| 168 | + case 1: /* linked address match */ | ||
| 169 | + { | ||
| 170 | + /* | ||
| 171 | + * Bits [1:0] are RES0. | ||
| 172 | + * | ||
| 173 | + * It is IMPLEMENTATION DEFINED whether bits [63:49] | ||
| 174 | + * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit | ||
| 175 | + * of the VA field ([48] or [52] for FEAT_LVA), or whether the | ||
| 176 | + * value is read as written. It is CONSTRAINED UNPREDICTABLE | ||
| 177 | + * whether the RESS bits are ignored when comparing an address. | ||
| 178 | + * Therefore we are allowed to compare the entire register, which | ||
| 179 | + * lets us avoid considering whether FEAT_LVA is actually enabled. | ||
| 180 | + * | ||
| 181 | + * The BAS field is used to allow setting breakpoints on 16-bit | ||
| 182 | + * wide instructions; it is CONSTRAINED UNPREDICTABLE whether | ||
| 183 | + * a bp will fire if the addresses covered by the bp and the addresses | ||
| 184 | + * covered by the insn overlap but the insn doesn't start at the | ||
| 185 | + * start of the bp address range. We choose to require the insn and | ||
| 186 | + * the bp to have the same address. The constraints on writing to | ||
| 187 | + * BAS enforced in dbgbcr_write mean we have only four cases: | ||
| 188 | + * 0b0000 => no breakpoint | ||
| 189 | + * 0b0011 => breakpoint on addr | ||
| 190 | + * 0b1100 => breakpoint on addr + 2 | ||
| 191 | + * 0b1111 => breakpoint on addr | ||
| 192 | + * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | ||
| 193 | + */ | ||
| 194 | + int bas = extract64(bcr, 5, 4); | ||
| 195 | + addr = bvr & ~3ULL; | ||
| 196 | + if (bas == 0) { | ||
| 197 | + return; | ||
| 198 | + } | ||
| 199 | + if (bas == 0xc) { | ||
| 200 | + addr += 2; | ||
| 201 | + } | ||
| 202 | + break; | ||
| 203 | + } | ||
| 204 | + case 2: /* unlinked context ID match */ | ||
| 205 | + case 8: /* unlinked VMID match (reserved if no EL2) */ | ||
| 206 | + case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | ||
| 207 | + qemu_log_mask(LOG_UNIMP, | ||
| 208 | + "arm: unlinked context breakpoint types not implemented\n"); | ||
| 209 | + return; | ||
| 210 | + case 9: /* linked VMID match (reserved if no EL2) */ | ||
| 211 | + case 11: /* linked context ID and VMID match (reserved if no EL2) */ | ||
| 212 | + case 3: /* linked context ID match */ | ||
| 213 | + default: | ||
| 214 | + /* | ||
| 215 | + * We must generate no events for Linked context matches (unless | ||
| 216 | + * they are linked to by some other bp/wp, which is handled in | ||
| 217 | + * updates for the linking bp/wp). We choose to also generate no events | ||
| 218 | + * for reserved values. | ||
| 219 | + */ | ||
| 220 | + return; | ||
| 221 | + } | ||
| 222 | + | ||
| 223 | + cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | ||
| 224 | +} | ||
| 225 | + | ||
| 226 | +void hw_breakpoint_update_all(ARMCPU *cpu) | ||
| 227 | +{ | ||
| 228 | + int i; | ||
| 229 | + CPUARMState *env = &cpu->env; | ||
| 230 | + | ||
| 231 | + /* | ||
| 232 | + * Completely clear out existing QEMU breakpoints and our array, to | ||
| 233 | + * avoid possible stale entries following migration load. | ||
| 234 | + */ | ||
| 235 | + cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | ||
| 236 | + memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | ||
| 237 | + | ||
| 238 | + for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | ||
| 239 | + hw_breakpoint_update(cpu, i); | ||
| 240 | + } | ||
| 241 | +} | ||
| 242 | + | ||
| 243 | +#if !defined(CONFIG_USER_ONLY) | ||
| 244 | + | ||
| 245 | +vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) | ||
| 246 | +{ | ||
| 247 | + ARMCPU *cpu = ARM_CPU(cs); | ||
| 248 | + CPUARMState *env = &cpu->env; | ||
| 249 | + | ||
| 250 | + /* | ||
| 251 | + * In BE32 system mode, target memory is stored byteswapped (on a | ||
| 252 | + * little-endian host system), and by the time we reach here (via an | ||
| 253 | + * opcode helper) the addresses of subword accesses have been adjusted | ||
| 254 | + * to account for that, which means that watchpoints will not match. | ||
| 255 | + * Undo the adjustment here. | ||
| 256 | + */ | ||
| 257 | + if (arm_sctlr_b(env)) { | ||
| 258 | + if (len == 1) { | ||
| 259 | + addr ^= 3; | ||
| 260 | + } else if (len == 2) { | ||
| 261 | + addr ^= 2; | ||
| 262 | + } | ||
| 263 | + } | ||
| 264 | + | ||
| 265 | + return addr; | ||
| 266 | +} | ||
| 267 | + | ||
| 268 | +#endif /* !CONFIG_USER_ONLY */ | ||
| 269 | +#endif /* CONFIG_TCG */ | ||
| 270 | + | ||
| 271 | /* | ||
| 272 | * Check for traps to "powerdown debug" registers, which are controlled | ||
| 273 | * by MDCR.TDOSA | ||
| 274 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { | ||
| 275 | .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, | ||
| 276 | }; | ||
| 277 | |||
| 278 | -void hw_watchpoint_update(ARMCPU *cpu, int n) | ||
| 279 | -{ | ||
| 280 | - CPUARMState *env = &cpu->env; | ||
| 281 | - vaddr len = 0; | ||
| 282 | - vaddr wvr = env->cp15.dbgwvr[n]; | ||
| 283 | - uint64_t wcr = env->cp15.dbgwcr[n]; | ||
| 284 | - int mask; | ||
| 285 | - int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; | ||
| 286 | - | ||
| 287 | - if (env->cpu_watchpoint[n]) { | ||
| 288 | - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); | ||
| 289 | - env->cpu_watchpoint[n] = NULL; | ||
| 290 | - } | ||
| 291 | - | ||
| 292 | - if (!FIELD_EX64(wcr, DBGWCR, E)) { | ||
| 293 | - /* E bit clear : watchpoint disabled */ | ||
| 294 | - return; | ||
| 295 | - } | ||
| 296 | - | ||
| 297 | - switch (FIELD_EX64(wcr, DBGWCR, LSC)) { | ||
| 298 | - case 0: | ||
| 299 | - /* LSC 00 is reserved and must behave as if the wp is disabled */ | ||
| 300 | - return; | ||
| 301 | - case 1: | ||
| 302 | - flags |= BP_MEM_READ; | ||
| 303 | - break; | ||
| 304 | - case 2: | ||
| 305 | - flags |= BP_MEM_WRITE; | ||
| 306 | - break; | ||
| 307 | - case 3: | ||
| 308 | - flags |= BP_MEM_ACCESS; | ||
| 309 | - break; | ||
| 310 | - } | ||
| 311 | - | ||
| 312 | - /* | ||
| 313 | - * Attempts to use both MASK and BAS fields simultaneously are | ||
| 314 | - * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, | ||
| 315 | - * thus generating a watchpoint for every byte in the masked region. | ||
| 316 | - */ | ||
| 317 | - mask = FIELD_EX64(wcr, DBGWCR, MASK); | ||
| 318 | - if (mask == 1 || mask == 2) { | ||
| 319 | - /* | ||
| 320 | - * Reserved values of MASK; we must act as if the mask value was | ||
| 321 | - * some non-reserved value, or as if the watchpoint were disabled. | ||
| 322 | - * We choose the latter. | ||
| 323 | - */ | ||
| 324 | - return; | ||
| 325 | - } else if (mask) { | ||
| 326 | - /* Watchpoint covers an aligned area up to 2GB in size */ | ||
| 327 | - len = 1ULL << mask; | ||
| 328 | - /* | ||
| 329 | - * If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE | ||
| 330 | - * whether the watchpoint fires when the unmasked bits match; we opt | ||
| 331 | - * to generate the exceptions. | ||
| 332 | - */ | ||
| 333 | - wvr &= ~(len - 1); | ||
| 334 | - } else { | ||
| 335 | - /* Watchpoint covers bytes defined by the byte address select bits */ | ||
| 336 | - int bas = FIELD_EX64(wcr, DBGWCR, BAS); | ||
| 337 | - int basstart; | ||
| 338 | - | ||
| 339 | - if (extract64(wvr, 2, 1)) { | ||
| 340 | - /* | ||
| 341 | - * Deprecated case of an only 4-aligned address. BAS[7:4] are | ||
| 342 | - * ignored, and BAS[3:0] define which bytes to watch. | ||
| 343 | - */ | ||
| 344 | - bas &= 0xf; | ||
| 345 | - } | ||
| 346 | - | ||
| 347 | - if (bas == 0) { | ||
| 348 | - /* This must act as if the watchpoint is disabled */ | ||
| 349 | - return; | ||
| 350 | - } | ||
| 351 | - | ||
| 352 | - /* | ||
| 353 | - * The BAS bits are supposed to be programmed to indicate a contiguous | ||
| 354 | - * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether | ||
| 355 | - * we fire for each byte in the word/doubleword addressed by the WVR. | ||
| 356 | - * We choose to ignore any non-zero bits after the first range of 1s. | ||
| 357 | - */ | ||
| 358 | - basstart = ctz32(bas); | ||
| 359 | - len = cto32(bas >> basstart); | ||
| 360 | - wvr += basstart; | ||
| 361 | - } | ||
| 362 | - | ||
| 363 | - cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, | ||
| 364 | - &env->cpu_watchpoint[n]); | ||
| 365 | -} | ||
| 366 | - | ||
| 367 | -void hw_watchpoint_update_all(ARMCPU *cpu) | ||
| 368 | -{ | ||
| 369 | - int i; | ||
| 370 | - CPUARMState *env = &cpu->env; | ||
| 371 | - | ||
| 372 | - /* | ||
| 373 | - * Completely clear out existing QEMU watchpoints and our array, to | ||
| 374 | - * avoid possible stale entries following migration load. | ||
| 375 | - */ | ||
| 376 | - cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); | ||
| 377 | - memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); | ||
| 378 | - | ||
| 379 | - for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { | ||
| 380 | - hw_watchpoint_update(cpu, i); | ||
| 381 | - } | ||
| 382 | -} | ||
| 383 | - | ||
| 384 | static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 385 | uint64_t value) | ||
| 386 | { | ||
| 387 | @@ -XXX,XX +XXX,XX @@ static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 27 | } | 388 | } |
| 28 | } | 389 | } |
| 29 | 390 | ||
| 30 | +static void fdt_add_sd_nodes(VersalVirt *s) | 391 | -void hw_breakpoint_update(ARMCPU *cpu, int n) |
| 31 | +{ | 392 | -{ |
| 32 | + const char clocknames[] = "clk_xin\0clk_ahb"; | 393 | - CPUARMState *env = &cpu->env; |
| 33 | + const char compat[] = "arasan,sdhci-8.9a"; | 394 | - uint64_t bvr = env->cp15.dbgbvr[n]; |
| 34 | + int i; | 395 | - uint64_t bcr = env->cp15.dbgbcr[n]; |
| 35 | + | 396 | - vaddr addr; |
| 36 | + for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) { | 397 | - int bt; |
| 37 | + uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i; | 398 | - int flags = BP_CPU; |
| 38 | + char *name = g_strdup_printf("/sdhci@%" PRIx64, addr); | 399 | - |
| 39 | + | 400 | - if (env->cpu_breakpoint[n]) { |
| 40 | + qemu_fdt_add_subnode(s->fdt, name); | 401 | - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); |
| 41 | + | 402 | - env->cpu_breakpoint[n] = NULL; |
| 42 | + qemu_fdt_setprop_cells(s->fdt, name, "clocks", | 403 | - } |
| 43 | + s->phandle.clk_25Mhz, s->phandle.clk_25Mhz); | 404 | - |
| 44 | + qemu_fdt_setprop(s->fdt, name, "clock-names", | 405 | - if (!extract64(bcr, 0, 1)) { |
| 45 | + clocknames, sizeof(clocknames)); | 406 | - /* E bit clear : watchpoint disabled */ |
| 46 | + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", | 407 | - return; |
| 47 | + GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2, | 408 | - } |
| 48 | + GIC_FDT_IRQ_FLAGS_LEVEL_HI); | 409 | - |
| 49 | + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", | 410 | - bt = extract64(bcr, 20, 4); |
| 50 | + 2, addr, 2, MM_PMC_SD0_SIZE); | 411 | - |
| 51 | + qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); | 412 | - switch (bt) { |
| 52 | + g_free(name); | 413 | - case 4: /* unlinked address mismatch (reserved if AArch64) */ |
| 53 | + } | 414 | - case 5: /* linked address mismatch (reserved if AArch64) */ |
| 54 | +} | 415 | - qemu_log_mask(LOG_UNIMP, |
| 55 | + | 416 | - "arm: address mismatch breakpoint types not implemented\n"); |
| 56 | static void fdt_nop_memory_nodes(void *fdt, Error **errp) | 417 | - return; |
| 418 | - case 0: /* unlinked address match */ | ||
| 419 | - case 1: /* linked address match */ | ||
| 420 | - { | ||
| 421 | - /* | ||
| 422 | - * Bits [1:0] are RES0. | ||
| 423 | - * | ||
| 424 | - * It is IMPLEMENTATION DEFINED whether bits [63:49] | ||
| 425 | - * ([63:53] for FEAT_LVA) are hardwired to a copy of the sign bit | ||
| 426 | - * of the VA field ([48] or [52] for FEAT_LVA), or whether the | ||
| 427 | - * value is read as written. It is CONSTRAINED UNPREDICTABLE | ||
| 428 | - * whether the RESS bits are ignored when comparing an address. | ||
| 429 | - * Therefore we are allowed to compare the entire register, which | ||
| 430 | - * lets us avoid considering whether FEAT_LVA is actually enabled. | ||
| 431 | - * | ||
| 432 | - * The BAS field is used to allow setting breakpoints on 16-bit | ||
| 433 | - * wide instructions; it is CONSTRAINED UNPREDICTABLE whether | ||
| 434 | - * a bp will fire if the addresses covered by the bp and the addresses | ||
| 435 | - * covered by the insn overlap but the insn doesn't start at the | ||
| 436 | - * start of the bp address range. We choose to require the insn and | ||
| 437 | - * the bp to have the same address. The constraints on writing to | ||
| 438 | - * BAS enforced in dbgbcr_write mean we have only four cases: | ||
| 439 | - * 0b0000 => no breakpoint | ||
| 440 | - * 0b0011 => breakpoint on addr | ||
| 441 | - * 0b1100 => breakpoint on addr + 2 | ||
| 442 | - * 0b1111 => breakpoint on addr | ||
| 443 | - * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). | ||
| 444 | - */ | ||
| 445 | - int bas = extract64(bcr, 5, 4); | ||
| 446 | - addr = bvr & ~3ULL; | ||
| 447 | - if (bas == 0) { | ||
| 448 | - return; | ||
| 449 | - } | ||
| 450 | - if (bas == 0xc) { | ||
| 451 | - addr += 2; | ||
| 452 | - } | ||
| 453 | - break; | ||
| 454 | - } | ||
| 455 | - case 2: /* unlinked context ID match */ | ||
| 456 | - case 8: /* unlinked VMID match (reserved if no EL2) */ | ||
| 457 | - case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ | ||
| 458 | - qemu_log_mask(LOG_UNIMP, | ||
| 459 | - "arm: unlinked context breakpoint types not implemented\n"); | ||
| 460 | - return; | ||
| 461 | - case 9: /* linked VMID match (reserved if no EL2) */ | ||
| 462 | - case 11: /* linked context ID and VMID match (reserved if no EL2) */ | ||
| 463 | - case 3: /* linked context ID match */ | ||
| 464 | - default: | ||
| 465 | - /* | ||
| 466 | - * We must generate no events for Linked context matches (unless | ||
| 467 | - * they are linked to by some other bp/wp, which is handled in | ||
| 468 | - * updates for the linking bp/wp). We choose to also generate no events | ||
| 469 | - * for reserved values. | ||
| 470 | - */ | ||
| 471 | - return; | ||
| 472 | - } | ||
| 473 | - | ||
| 474 | - cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); | ||
| 475 | -} | ||
| 476 | - | ||
| 477 | -void hw_breakpoint_update_all(ARMCPU *cpu) | ||
| 478 | -{ | ||
| 479 | - int i; | ||
| 480 | - CPUARMState *env = &cpu->env; | ||
| 481 | - | ||
| 482 | - /* | ||
| 483 | - * Completely clear out existing QEMU breakpoints and our array, to | ||
| 484 | - * avoid possible stale entries following migration load. | ||
| 485 | - */ | ||
| 486 | - cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); | ||
| 487 | - memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); | ||
| 488 | - | ||
| 489 | - for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { | ||
| 490 | - hw_breakpoint_update(cpu, i); | ||
| 491 | - } | ||
| 492 | -} | ||
| 493 | - | ||
| 494 | static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 495 | uint64_t value) | ||
| 57 | { | 496 | { |
| 58 | Error *err = NULL; | 497 | @@ -XXX,XX +XXX,XX @@ void define_debug_regs(ARMCPU *cpu) |
| 59 | @@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s) | 498 | g_free(dbgwcr_el1_name); |
| 60 | } | 499 | } |
| 61 | } | 500 | } |
| 62 | 501 | - | |
| 63 | +static void sd_plugin_card(SDHCIState *sd, DriveInfo *di) | 502 | -#if !defined(CONFIG_USER_ONLY) |
| 64 | +{ | 503 | - |
| 65 | + BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL; | 504 | -vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) |
| 66 | + DeviceState *card; | 505 | -{ |
| 67 | + | 506 | - ARMCPU *cpu = ARM_CPU(cs); |
| 68 | + card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD); | 507 | - CPUARMState *env = &cpu->env; |
| 69 | + object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card), | 508 | - |
| 70 | + &error_fatal); | 509 | - /* |
| 71 | + qdev_prop_set_drive(card, "drive", blk, &error_fatal); | 510 | - * In BE32 system mode, target memory is stored byteswapped (on a |
| 72 | + object_property_set_bool(OBJECT(card), true, "realized", &error_fatal); | 511 | - * little-endian host system), and by the time we reach here (via an |
| 73 | +} | 512 | - * opcode helper) the addresses of subword accesses have been adjusted |
| 74 | + | 513 | - * to account for that, which means that watchpoints will not match. |
| 75 | static void versal_virt_init(MachineState *machine) | 514 | - * Undo the adjustment here. |
| 76 | { | 515 | - */ |
| 77 | VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine); | 516 | - if (arm_sctlr_b(env)) { |
| 78 | int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED; | 517 | - if (len == 1) { |
| 79 | + int i; | 518 | - addr ^= 3; |
| 80 | 519 | - } else if (len == 2) { | |
| 81 | /* | 520 | - addr ^= 2; |
| 82 | * If the user provides an Operating System to be loaded, we expect them | 521 | - } |
| 83 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) | 522 | - } |
| 84 | fdt_add_gic_nodes(s); | 523 | - |
| 85 | fdt_add_timer_nodes(s); | 524 | - return addr; |
| 86 | fdt_add_zdma_nodes(s); | 525 | -} |
| 87 | + fdt_add_sd_nodes(s); | 526 | - |
| 88 | fdt_add_cpu_nodes(s, psci_conduit); | 527 | -#endif |
| 89 | fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); | ||
| 90 | fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); | ||
| 91 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) | ||
| 92 | memory_region_add_subregion_overlap(get_system_memory(), | ||
| 93 | 0, &s->soc.fpd.apu.mr, 0); | ||
| 94 | |||
| 95 | + /* Plugin SD cards. */ | ||
| 96 | + for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) { | ||
| 97 | + sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD)); | ||
| 98 | + } | ||
| 99 | + | ||
| 100 | s->binfo.ram_size = machine->ram_size; | ||
| 101 | s->binfo.loader_start = 0x0; | ||
| 102 | s->binfo.get_dtb = versal_virt_get_dtb; | ||
| 103 | -- | 528 | -- |
| 104 | 2.20.1 | 529 | 2.34.1 |
| 105 | |||
| 106 | diff view generated by jsdifflib |
| 1 | Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 3-reg-same grouping to decodetree. | 2 | |
| 3 | 3 | Introduce the target/arm/tcg directory. Its purpose is to hold the TCG | |
| 4 | code that is selected by CONFIG_TCG. | ||
| 5 | |||
| 6 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | ||
| 7 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 11 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20200430181003.21682-20-peter.maydell@linaro.org | ||
| 7 | --- | 13 | --- |
| 8 | target/arm/neon-dp.decode | 9 +++++++ | 14 | MAINTAINERS | 1 + |
| 9 | target/arm/translate-neon.inc.c | 44 +++++++++++++++++++++++++++++++++ | 15 | target/arm/{ => tcg}/translate-a64.h | 0 |
| 10 | target/arm/translate.c | 28 +++------------------ | 16 | target/arm/{ => tcg}/translate.h | 0 |
| 11 | 3 files changed, 56 insertions(+), 25 deletions(-) | 17 | target/arm/{ => tcg}/a32-uncond.decode | 0 |
| 12 | 18 | target/arm/{ => tcg}/a32.decode | 0 | |
| 13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 19 | target/arm/{ => tcg}/m-nocp.decode | 0 |
| 20 | target/arm/{ => tcg}/mve.decode | 0 | ||
| 21 | target/arm/{ => tcg}/neon-dp.decode | 0 | ||
| 22 | target/arm/{ => tcg}/neon-ls.decode | 0 | ||
| 23 | target/arm/{ => tcg}/neon-shared.decode | 0 | ||
| 24 | target/arm/{ => tcg}/sme-fa64.decode | 0 | ||
| 25 | target/arm/{ => tcg}/sme.decode | 0 | ||
| 26 | target/arm/{ => tcg}/sve.decode | 0 | ||
| 27 | target/arm/{ => tcg}/t16.decode | 0 | ||
| 28 | target/arm/{ => tcg}/t32.decode | 0 | ||
| 29 | target/arm/{ => tcg}/vfp-uncond.decode | 0 | ||
| 30 | target/arm/{ => tcg}/vfp.decode | 0 | ||
| 31 | target/arm/{ => tcg}/translate-a64.c | 0 | ||
| 32 | target/arm/{ => tcg}/translate-m-nocp.c | 0 | ||
| 33 | target/arm/{ => tcg}/translate-mve.c | 0 | ||
| 34 | target/arm/{ => tcg}/translate-neon.c | 0 | ||
| 35 | target/arm/{ => tcg}/translate-sme.c | 0 | ||
| 36 | target/arm/{ => tcg}/translate-sve.c | 0 | ||
| 37 | target/arm/{ => tcg}/translate-vfp.c | 0 | ||
| 38 | target/arm/{ => tcg}/translate.c | 0 | ||
| 39 | target/arm/meson.build | 30 +++--------------- | ||
| 40 | target/arm/{ => tcg}/meson.build | 41 +------------------------ | ||
| 41 | 27 files changed, 6 insertions(+), 66 deletions(-) | ||
| 42 | rename target/arm/{ => tcg}/translate-a64.h (100%) | ||
| 43 | rename target/arm/{ => tcg}/translate.h (100%) | ||
| 44 | rename target/arm/{ => tcg}/a32-uncond.decode (100%) | ||
| 45 | rename target/arm/{ => tcg}/a32.decode (100%) | ||
| 46 | rename target/arm/{ => tcg}/m-nocp.decode (100%) | ||
| 47 | rename target/arm/{ => tcg}/mve.decode (100%) | ||
| 48 | rename target/arm/{ => tcg}/neon-dp.decode (100%) | ||
| 49 | rename target/arm/{ => tcg}/neon-ls.decode (100%) | ||
| 50 | rename target/arm/{ => tcg}/neon-shared.decode (100%) | ||
| 51 | rename target/arm/{ => tcg}/sme-fa64.decode (100%) | ||
| 52 | rename target/arm/{ => tcg}/sme.decode (100%) | ||
| 53 | rename target/arm/{ => tcg}/sve.decode (100%) | ||
| 54 | rename target/arm/{ => tcg}/t16.decode (100%) | ||
| 55 | rename target/arm/{ => tcg}/t32.decode (100%) | ||
| 56 | rename target/arm/{ => tcg}/vfp-uncond.decode (100%) | ||
| 57 | rename target/arm/{ => tcg}/vfp.decode (100%) | ||
| 58 | rename target/arm/{ => tcg}/translate-a64.c (100%) | ||
| 59 | rename target/arm/{ => tcg}/translate-m-nocp.c (100%) | ||
| 60 | rename target/arm/{ => tcg}/translate-mve.c (100%) | ||
| 61 | rename target/arm/{ => tcg}/translate-neon.c (100%) | ||
| 62 | rename target/arm/{ => tcg}/translate-sme.c (100%) | ||
| 63 | rename target/arm/{ => tcg}/translate-sve.c (100%) | ||
| 64 | rename target/arm/{ => tcg}/translate-vfp.c (100%) | ||
| 65 | rename target/arm/{ => tcg}/translate.c (100%) | ||
| 66 | copy target/arm/{ => tcg}/meson.build (64%) | ||
| 67 | |||
| 68 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | 69 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/target/arm/neon-dp.decode | 70 | --- a/MAINTAINERS |
| 16 | +++ b/target/arm/neon-dp.decode | 71 | +++ b/MAINTAINERS |
| 17 | @@ -XXX,XX +XXX,XX @@ VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same | 72 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> |
| 18 | VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same | 73 | L: qemu-arm@nongnu.org |
| 19 | VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same | 74 | S: Maintained |
| 20 | 75 | F: target/arm/ | |
| 21 | +VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same | 76 | +F: target/arm/tcg/ |
| 22 | +VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same | 77 | F: tests/tcg/arm/ |
| 78 | F: tests/tcg/aarch64/ | ||
| 79 | F: tests/qtest/arm-cpu-features.c | ||
| 80 | diff --git a/target/arm/translate-a64.h b/target/arm/tcg/translate-a64.h | ||
| 81 | similarity index 100% | ||
| 82 | rename from target/arm/translate-a64.h | ||
| 83 | rename to target/arm/tcg/translate-a64.h | ||
| 84 | diff --git a/target/arm/translate.h b/target/arm/tcg/translate.h | ||
| 85 | similarity index 100% | ||
| 86 | rename from target/arm/translate.h | ||
| 87 | rename to target/arm/tcg/translate.h | ||
| 88 | diff --git a/target/arm/a32-uncond.decode b/target/arm/tcg/a32-uncond.decode | ||
| 89 | similarity index 100% | ||
| 90 | rename from target/arm/a32-uncond.decode | ||
| 91 | rename to target/arm/tcg/a32-uncond.decode | ||
| 92 | diff --git a/target/arm/a32.decode b/target/arm/tcg/a32.decode | ||
| 93 | similarity index 100% | ||
| 94 | rename from target/arm/a32.decode | ||
| 95 | rename to target/arm/tcg/a32.decode | ||
| 96 | diff --git a/target/arm/m-nocp.decode b/target/arm/tcg/m-nocp.decode | ||
| 97 | similarity index 100% | ||
| 98 | rename from target/arm/m-nocp.decode | ||
| 99 | rename to target/arm/tcg/m-nocp.decode | ||
| 100 | diff --git a/target/arm/mve.decode b/target/arm/tcg/mve.decode | ||
| 101 | similarity index 100% | ||
| 102 | rename from target/arm/mve.decode | ||
| 103 | rename to target/arm/tcg/mve.decode | ||
| 104 | diff --git a/target/arm/neon-dp.decode b/target/arm/tcg/neon-dp.decode | ||
| 105 | similarity index 100% | ||
| 106 | rename from target/arm/neon-dp.decode | ||
| 107 | rename to target/arm/tcg/neon-dp.decode | ||
| 108 | diff --git a/target/arm/neon-ls.decode b/target/arm/tcg/neon-ls.decode | ||
| 109 | similarity index 100% | ||
| 110 | rename from target/arm/neon-ls.decode | ||
| 111 | rename to target/arm/tcg/neon-ls.decode | ||
| 112 | diff --git a/target/arm/neon-shared.decode b/target/arm/tcg/neon-shared.decode | ||
| 113 | similarity index 100% | ||
| 114 | rename from target/arm/neon-shared.decode | ||
| 115 | rename to target/arm/tcg/neon-shared.decode | ||
| 116 | diff --git a/target/arm/sme-fa64.decode b/target/arm/tcg/sme-fa64.decode | ||
| 117 | similarity index 100% | ||
| 118 | rename from target/arm/sme-fa64.decode | ||
| 119 | rename to target/arm/tcg/sme-fa64.decode | ||
| 120 | diff --git a/target/arm/sme.decode b/target/arm/tcg/sme.decode | ||
| 121 | similarity index 100% | ||
| 122 | rename from target/arm/sme.decode | ||
| 123 | rename to target/arm/tcg/sme.decode | ||
| 124 | diff --git a/target/arm/sve.decode b/target/arm/tcg/sve.decode | ||
| 125 | similarity index 100% | ||
| 126 | rename from target/arm/sve.decode | ||
| 127 | rename to target/arm/tcg/sve.decode | ||
| 128 | diff --git a/target/arm/t16.decode b/target/arm/tcg/t16.decode | ||
| 129 | similarity index 100% | ||
| 130 | rename from target/arm/t16.decode | ||
| 131 | rename to target/arm/tcg/t16.decode | ||
| 132 | diff --git a/target/arm/t32.decode b/target/arm/tcg/t32.decode | ||
| 133 | similarity index 100% | ||
| 134 | rename from target/arm/t32.decode | ||
| 135 | rename to target/arm/tcg/t32.decode | ||
| 136 | diff --git a/target/arm/vfp-uncond.decode b/target/arm/tcg/vfp-uncond.decode | ||
| 137 | similarity index 100% | ||
| 138 | rename from target/arm/vfp-uncond.decode | ||
| 139 | rename to target/arm/tcg/vfp-uncond.decode | ||
| 140 | diff --git a/target/arm/vfp.decode b/target/arm/tcg/vfp.decode | ||
| 141 | similarity index 100% | ||
| 142 | rename from target/arm/vfp.decode | ||
| 143 | rename to target/arm/tcg/vfp.decode | ||
| 144 | diff --git a/target/arm/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
| 145 | similarity index 100% | ||
| 146 | rename from target/arm/translate-a64.c | ||
| 147 | rename to target/arm/tcg/translate-a64.c | ||
| 148 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c | ||
| 149 | similarity index 100% | ||
| 150 | rename from target/arm/translate-m-nocp.c | ||
| 151 | rename to target/arm/tcg/translate-m-nocp.c | ||
| 152 | diff --git a/target/arm/translate-mve.c b/target/arm/tcg/translate-mve.c | ||
| 153 | similarity index 100% | ||
| 154 | rename from target/arm/translate-mve.c | ||
| 155 | rename to target/arm/tcg/translate-mve.c | ||
| 156 | diff --git a/target/arm/translate-neon.c b/target/arm/tcg/translate-neon.c | ||
| 157 | similarity index 100% | ||
| 158 | rename from target/arm/translate-neon.c | ||
| 159 | rename to target/arm/tcg/translate-neon.c | ||
| 160 | diff --git a/target/arm/translate-sme.c b/target/arm/tcg/translate-sme.c | ||
| 161 | similarity index 100% | ||
| 162 | rename from target/arm/translate-sme.c | ||
| 163 | rename to target/arm/tcg/translate-sme.c | ||
| 164 | diff --git a/target/arm/translate-sve.c b/target/arm/tcg/translate-sve.c | ||
| 165 | similarity index 100% | ||
| 166 | rename from target/arm/translate-sve.c | ||
| 167 | rename to target/arm/tcg/translate-sve.c | ||
| 168 | diff --git a/target/arm/translate-vfp.c b/target/arm/tcg/translate-vfp.c | ||
| 169 | similarity index 100% | ||
| 170 | rename from target/arm/translate-vfp.c | ||
| 171 | rename to target/arm/tcg/translate-vfp.c | ||
| 172 | diff --git a/target/arm/translate.c b/target/arm/tcg/translate.c | ||
| 173 | similarity index 100% | ||
| 174 | rename from target/arm/translate.c | ||
| 175 | rename to target/arm/tcg/translate.c | ||
| 176 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
| 177 | index XXXXXXX..XXXXXXX 100644 | ||
| 178 | --- a/target/arm/meson.build | ||
| 179 | +++ b/target/arm/meson.build | ||
| 180 | @@ -XXX,XX +XXX,XX @@ | ||
| 181 | -gen = [ | ||
| 182 | - decodetree.process('sve.decode', extra_args: '--decode=disas_sve'), | ||
| 183 | - decodetree.process('sme.decode', extra_args: '--decode=disas_sme'), | ||
| 184 | - decodetree.process('sme-fa64.decode', extra_args: '--static-decode=disas_sme_fa64'), | ||
| 185 | - decodetree.process('neon-shared.decode', extra_args: '--decode=disas_neon_shared'), | ||
| 186 | - decodetree.process('neon-dp.decode', extra_args: '--decode=disas_neon_dp'), | ||
| 187 | - decodetree.process('neon-ls.decode', extra_args: '--decode=disas_neon_ls'), | ||
| 188 | - decodetree.process('vfp.decode', extra_args: '--decode=disas_vfp'), | ||
| 189 | - decodetree.process('vfp-uncond.decode', extra_args: '--decode=disas_vfp_uncond'), | ||
| 190 | - decodetree.process('m-nocp.decode', extra_args: '--decode=disas_m_nocp'), | ||
| 191 | - decodetree.process('mve.decode', extra_args: '--decode=disas_mve'), | ||
| 192 | - decodetree.process('a32.decode', extra_args: '--static-decode=disas_a32'), | ||
| 193 | - decodetree.process('a32-uncond.decode', extra_args: '--static-decode=disas_a32_uncond'), | ||
| 194 | - decodetree.process('t32.decode', extra_args: '--static-decode=disas_t32'), | ||
| 195 | - decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']), | ||
| 196 | -] | ||
| 197 | - | ||
| 198 | arm_ss = ss.source_set() | ||
| 199 | -arm_ss.add(gen) | ||
| 200 | arm_ss.add(files( | ||
| 201 | 'cpu.c', | ||
| 202 | 'crypto_helper.c', | ||
| 203 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( | ||
| 204 | 'neon_helper.c', | ||
| 205 | 'op_helper.c', | ||
| 206 | 'tlb_helper.c', | ||
| 207 | - 'translate.c', | ||
| 208 | - 'translate-m-nocp.c', | ||
| 209 | - 'translate-mve.c', | ||
| 210 | - 'translate-neon.c', | ||
| 211 | - 'translate-vfp.c', | ||
| 212 | 'vec_helper.c', | ||
| 213 | 'vfp_helper.c', | ||
| 214 | 'cpu_tcg.c', | ||
| 215 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( | ||
| 216 | 'pauth_helper.c', | ||
| 217 | 'sve_helper.c', | ||
| 218 | 'sme_helper.c', | ||
| 219 | - 'translate-a64.c', | ||
| 220 | - 'translate-sve.c', | ||
| 221 | - 'translate-sme.c', | ||
| 222 | )) | ||
| 223 | |||
| 224 | arm_softmmu_ss = ss.source_set() | ||
| 225 | @@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files( | ||
| 226 | |||
| 227 | subdir('hvf') | ||
| 228 | |||
| 229 | +if 'CONFIG_TCG' in config_all | ||
| 230 | + subdir('tcg') | ||
| 231 | +endif | ||
| 23 | + | 232 | + |
| 24 | VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same | 233 | target_arch += {'arm': arm_ss} |
| 25 | VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same | 234 | target_softmmu_arch += {'arm': arm_softmmu_ss} |
| 26 | VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same | 235 | diff --git a/target/arm/meson.build b/target/arm/tcg/meson.build |
| 27 | @@ -XXX,XX +XXX,XX @@ VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same | 236 | similarity index 64% |
| 28 | 237 | copy from target/arm/meson.build | |
| 29 | VTST_3s 1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same | 238 | copy to target/arm/tcg/meson.build |
| 30 | VCEQ_3s 1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same | 239 | index XXXXXXX..XXXXXXX 100644 |
| 240 | --- a/target/arm/meson.build | ||
| 241 | +++ b/target/arm/tcg/meson.build | ||
| 242 | @@ -XXX,XX +XXX,XX @@ gen = [ | ||
| 243 | decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-decode=disas_t16']), | ||
| 244 | ] | ||
| 245 | |||
| 246 | -arm_ss = ss.source_set() | ||
| 247 | arm_ss.add(gen) | ||
| 31 | + | 248 | + |
| 32 | +VMLA_3s 1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same | 249 | arm_ss.add(files( |
| 33 | +VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same | 250 | - 'cpu.c', |
| 34 | + | 251 | - 'crypto_helper.c', |
| 35 | +VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same | 252 | - 'debug_helper.c', |
| 36 | +VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same | 253 | - 'gdbstub.c', |
| 37 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 254 | - 'helper.c', |
| 38 | index XXXXXXX..XXXXXXX 100644 | 255 | - 'iwmmxt_helper.c', |
| 39 | --- a/target/arm/translate-neon.inc.c | 256 | - 'm_helper.c', |
| 40 | +++ b/target/arm/translate-neon.inc.c | 257 | - 'mve_helper.c', |
| 41 | @@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax) | 258 | - 'neon_helper.c', |
| 42 | DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax) | 259 | - 'op_helper.c', |
| 43 | DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin) | 260 | - 'tlb_helper.c', |
| 44 | DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin) | 261 | 'translate.c', |
| 45 | +DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul) | 262 | 'translate-m-nocp.c', |
| 46 | 263 | 'translate-mve.c', | |
| 47 | #define DO_3SAME_CMP(INSN, COND) \ | 264 | 'translate-neon.c', |
| 48 | static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ | 265 | 'translate-vfp.c', |
| 49 | @@ -XXX,XX +XXX,XX @@ DO_3SAME_GVEC4(VQADD_S, sqadd_op) | 266 | - 'vec_helper.c', |
| 50 | DO_3SAME_GVEC4(VQADD_U, uqadd_op) | 267 | - 'vfp_helper.c', |
| 51 | DO_3SAME_GVEC4(VQSUB_S, sqsub_op) | 268 | - 'cpu_tcg.c', |
| 52 | DO_3SAME_GVEC4(VQSUB_U, uqsub_op) | 269 | )) |
| 53 | + | 270 | -arm_ss.add(zlib) |
| 54 | +static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | 271 | - |
| 55 | + uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) | 272 | -arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) |
| 56 | +{ | 273 | |
| 57 | + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, | 274 | arm_ss.add(when: 'TARGET_AARCH64', if_true: files( |
| 58 | + 0, gen_helper_gvec_pmul_b); | 275 | - 'cpu64.c', |
| 59 | +} | 276 | - 'gdbstub64.c', |
| 60 | + | 277 | - 'helper-a64.c', |
| 61 | +static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a) | 278 | - 'mte_helper.c', |
| 62 | +{ | 279 | - 'pauth_helper.c', |
| 63 | + if (a->size != 0) { | 280 | - 'sve_helper.c', |
| 64 | + return false; | 281 | - 'sme_helper.c', |
| 65 | + } | 282 | 'translate-a64.c', |
| 66 | + return do_3same(s, a, gen_VMUL_p_3s); | 283 | 'translate-sve.c', |
| 67 | +} | 284 | 'translate-sme.c', |
| 68 | + | 285 | )) |
| 69 | +#define DO_3SAME_GVEC3_NO_SZ_3(INSN, OPARRAY) \ | 286 | - |
| 70 | + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ | 287 | -arm_softmmu_ss = ss.source_set() |
| 71 | + uint32_t rn_ofs, uint32_t rm_ofs, \ | 288 | -arm_softmmu_ss.add(files( |
| 72 | + uint32_t oprsz, uint32_t maxsz) \ | 289 | - 'arch_dump.c', |
| 73 | + { \ | 290 | - 'arm-powerctl.c', |
| 74 | + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, \ | 291 | - 'machine.c', |
| 75 | + oprsz, maxsz, &OPARRAY[vece]); \ | 292 | - 'monitor.c', |
| 76 | + } \ | 293 | - 'psci.c', |
| 77 | + DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s) | 294 | - 'ptw.c', |
| 78 | + | 295 | -)) |
| 79 | + | 296 | - |
| 80 | +DO_3SAME_GVEC3_NO_SZ_3(VMLA, mla_op) | 297 | -subdir('hvf') |
| 81 | +DO_3SAME_GVEC3_NO_SZ_3(VMLS, mls_op) | 298 | - |
| 82 | + | 299 | -target_arch += {'arm': arm_ss} |
| 83 | +#define DO_3SAME_GVEC3_SHIFT(INSN, OPARRAY) \ | 300 | -target_softmmu_arch += {'arm': arm_softmmu_ss} |
| 84 | + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ | ||
| 85 | + uint32_t rn_ofs, uint32_t rm_ofs, \ | ||
| 86 | + uint32_t oprsz, uint32_t maxsz) \ | ||
| 87 | + { \ | ||
| 88 | + /* Note the operation is vshl vd,vm,vn */ \ | ||
| 89 | + tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, \ | ||
| 90 | + oprsz, maxsz, &OPARRAY[vece]); \ | ||
| 91 | + } \ | ||
| 92 | + DO_3SAME(INSN, gen_##INSN##_3s) | ||
| 93 | + | ||
| 94 | +DO_3SAME_GVEC3_SHIFT(VSHL_S, sshl_op) | ||
| 95 | +DO_3SAME_GVEC3_SHIFT(VSHL_U, ushl_op) | ||
| 96 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 97 | index XXXXXXX..XXXXXXX 100644 | ||
| 98 | --- a/target/arm/translate.c | ||
| 99 | +++ b/target/arm/translate.c | ||
| 100 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 101 | } | ||
| 102 | return 1; | ||
| 103 | |||
| 104 | - case NEON_3R_VMUL: /* VMUL */ | ||
| 105 | - if (u) { | ||
| 106 | - /* Polynomial case allows only P8. */ | ||
| 107 | - if (size != 0) { | ||
| 108 | - return 1; | ||
| 109 | - } | ||
| 110 | - tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size, | ||
| 111 | - 0, gen_helper_gvec_pmul_b); | ||
| 112 | - } else { | ||
| 113 | - tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs, | ||
| 114 | - vec_size, vec_size); | ||
| 115 | - } | ||
| 116 | - return 0; | ||
| 117 | - | ||
| 118 | - case NEON_3R_VML: /* VMLA, VMLS */ | ||
| 119 | - tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size, | ||
| 120 | - u ? &mls_op[size] : &mla_op[size]); | ||
| 121 | - return 0; | ||
| 122 | - | ||
| 123 | - case NEON_3R_VSHL: | ||
| 124 | - /* Note the operation is vshl vd,vm,vn */ | ||
| 125 | - tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size, | ||
| 126 | - u ? &ushl_op[size] : &sshl_op[size]); | ||
| 127 | - return 0; | ||
| 128 | - | ||
| 129 | case NEON_3R_VADD_VSUB: | ||
| 130 | case NEON_3R_LOGIC: | ||
| 131 | case NEON_3R_VMAX: | ||
| 132 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 133 | case NEON_3R_VCGE: | ||
| 134 | case NEON_3R_VQADD: | ||
| 135 | case NEON_3R_VQSUB: | ||
| 136 | + case NEON_3R_VMUL: | ||
| 137 | + case NEON_3R_VML: | ||
| 138 | + case NEON_3R_VSHL: | ||
| 139 | /* Already handled by decodetree */ | ||
| 140 | return 1; | ||
| 141 | } | ||
| 142 | -- | 301 | -- |
| 143 | 2.20.1 | 302 | 2.34.1 |
| 144 | 303 | ||
| 145 | 304 | diff view generated by jsdifflib |
| 1 | Add the infrastructure for building and invoking a decodetree decoder | 1 | From: Claudio Fontana <cfontana@suse.de> |
|---|---|---|---|
| 2 | for the AArch32 Neon encodings. At the moment the new decoder covers | 2 | |
| 3 | nothing, so we always fall back to the existing hand-written decode. | 3 | Signed-off-by: Claudio Fontana <cfontana@suse.de> |
| 4 | 4 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | |
| 5 | We follow the same pattern we did for the VFP decodetree conversion | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 6 | (commit 78e138bc1f672c145ef6ace74617d and following): code that deals | 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 7 | with Neon will be moving gradually out to translate-neon.vfp.inc, | 7 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 8 | which we #include into translate.c. | ||
| 9 | |||
| 10 | In order to share the decode files between A32 and T32, we | ||
| 11 | split Neon into 3 parts: | ||
| 12 | * data-processing | ||
| 13 | * load-store | ||
| 14 | * 'shared' encodings | ||
| 15 | |||
| 16 | The first two groups of instructions have similar but not identical | ||
| 17 | A32 and T32 encodings, so we need to manually transform the T32 | ||
| 18 | encoding into the A32 one before calling the decoder; the third group | ||
| 19 | covers the Neon instructions which are identical in A32 and T32. | ||
| 20 | |||
| 21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 23 | Message-id: 20200430181003.21682-4-peter.maydell@linaro.org | ||
| 24 | --- | 9 | --- |
| 25 | target/arm/neon-dp.decode | 29 ++++++++++++++++++++++++++ | 10 | target/arm/{ => tcg}/vec_internal.h | 0 |
| 26 | target/arm/neon-ls.decode | 29 ++++++++++++++++++++++++++ | 11 | target/arm/tcg-stubs.c | 23 +++++++++++++++++++++++ |
| 27 | target/arm/neon-shared.decode | 27 +++++++++++++++++++++++++ | 12 | target/arm/{ => tcg}/crypto_helper.c | 0 |
| 28 | target/arm/translate-neon.inc.c | 32 +++++++++++++++++++++++++++++ | 13 | target/arm/{ => tcg}/helper-a64.c | 0 |
| 29 | target/arm/translate.c | 36 +++++++++++++++++++++++++++++++-- | 14 | target/arm/{ => tcg}/iwmmxt_helper.c | 0 |
| 30 | target/arm/Makefile.objs | 18 +++++++++++++++++ | 15 | target/arm/{ => tcg}/m_helper.c | 0 |
| 31 | 6 files changed, 169 insertions(+), 2 deletions(-) | 16 | target/arm/{ => tcg}/mte_helper.c | 0 |
| 32 | create mode 100644 target/arm/neon-dp.decode | 17 | target/arm/{ => tcg}/mve_helper.c | 0 |
| 33 | create mode 100644 target/arm/neon-ls.decode | 18 | target/arm/{ => tcg}/neon_helper.c | 0 |
| 34 | create mode 100644 target/arm/neon-shared.decode | 19 | target/arm/{ => tcg}/op_helper.c | 0 |
| 35 | create mode 100644 target/arm/translate-neon.inc.c | 20 | target/arm/{ => tcg}/pauth_helper.c | 0 |
| 36 | 21 | target/arm/{ => tcg}/sme_helper.c | 0 | |
| 37 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 22 | target/arm/{ => tcg}/sve_helper.c | 0 |
| 23 | target/arm/{ => tcg}/tlb_helper.c | 0 | ||
| 24 | target/arm/{ => tcg}/vec_helper.c | 0 | ||
| 25 | target/arm/meson.build | 15 ++------------- | ||
| 26 | target/arm/tcg/meson.build | 13 +++++++++++++ | ||
| 27 | 17 files changed, 38 insertions(+), 13 deletions(-) | ||
| 28 | rename target/arm/{ => tcg}/vec_internal.h (100%) | ||
| 29 | create mode 100644 target/arm/tcg-stubs.c | ||
| 30 | rename target/arm/{ => tcg}/crypto_helper.c (100%) | ||
| 31 | rename target/arm/{ => tcg}/helper-a64.c (100%) | ||
| 32 | rename target/arm/{ => tcg}/iwmmxt_helper.c (100%) | ||
| 33 | rename target/arm/{ => tcg}/m_helper.c (100%) | ||
| 34 | rename target/arm/{ => tcg}/mte_helper.c (100%) | ||
| 35 | rename target/arm/{ => tcg}/mve_helper.c (100%) | ||
| 36 | rename target/arm/{ => tcg}/neon_helper.c (100%) | ||
| 37 | rename target/arm/{ => tcg}/op_helper.c (100%) | ||
| 38 | rename target/arm/{ => tcg}/pauth_helper.c (100%) | ||
| 39 | rename target/arm/{ => tcg}/sme_helper.c (100%) | ||
| 40 | rename target/arm/{ => tcg}/sve_helper.c (100%) | ||
| 41 | rename target/arm/{ => tcg}/tlb_helper.c (100%) | ||
| 42 | rename target/arm/{ => tcg}/vec_helper.c (100%) | ||
| 43 | |||
| 44 | diff --git a/target/arm/vec_internal.h b/target/arm/tcg/vec_internal.h | ||
| 45 | similarity index 100% | ||
| 46 | rename from target/arm/vec_internal.h | ||
| 47 | rename to target/arm/tcg/vec_internal.h | ||
| 48 | diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c | ||
| 38 | new file mode 100644 | 49 | new file mode 100644 |
| 39 | index XXXXXXX..XXXXXXX | 50 | index XXXXXXX..XXXXXXX |
| 40 | --- /dev/null | 51 | --- /dev/null |
| 41 | +++ b/target/arm/neon-dp.decode | 52 | +++ b/target/arm/tcg-stubs.c |
| 42 | @@ -XXX,XX +XXX,XX @@ | ||
| 43 | +# AArch32 Neon data-processing instruction descriptions | ||
| 44 | +# | ||
| 45 | +# Copyright (c) 2020 Linaro, Ltd | ||
| 46 | +# | ||
| 47 | +# This library is free software; you can redistribute it and/or | ||
| 48 | +# modify it under the terms of the GNU Lesser General Public | ||
| 49 | +# License as published by the Free Software Foundation; either | ||
| 50 | +# version 2 of the License, or (at your option) any later version. | ||
| 51 | +# | ||
| 52 | +# This library is distributed in the hope that it will be useful, | ||
| 53 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 54 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 55 | +# Lesser General Public License for more details. | ||
| 56 | +# | ||
| 57 | +# You should have received a copy of the GNU Lesser General Public | ||
| 58 | +# License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
| 59 | + | ||
| 60 | +# | ||
| 61 | +# This file is processed by scripts/decodetree.py | ||
| 62 | +# | ||
| 63 | + | ||
| 64 | +# Encodings for Neon data processing instructions where the T32 encoding | ||
| 65 | +# is a simple transformation of the A32 encoding. | ||
| 66 | +# More specifically, this file covers instructions where the A32 encoding is | ||
| 67 | +# 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq | ||
| 68 | +# and the T32 encoding is | ||
| 69 | +# 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq | ||
| 70 | +# This file works on the A32 encoding only; calling code for T32 has to | ||
| 71 | +# transform the insn into the A32 version first. | ||
| 72 | diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode | ||
| 73 | new file mode 100644 | ||
| 74 | index XXXXXXX..XXXXXXX | ||
| 75 | --- /dev/null | ||
| 76 | +++ b/target/arm/neon-ls.decode | ||
| 77 | @@ -XXX,XX +XXX,XX @@ | ||
| 78 | +# AArch32 Neon load/store instruction descriptions | ||
| 79 | +# | ||
| 80 | +# Copyright (c) 2020 Linaro, Ltd | ||
| 81 | +# | ||
| 82 | +# This library is free software; you can redistribute it and/or | ||
| 83 | +# modify it under the terms of the GNU Lesser General Public | ||
| 84 | +# License as published by the Free Software Foundation; either | ||
| 85 | +# version 2 of the License, or (at your option) any later version. | ||
| 86 | +# | ||
| 87 | +# This library is distributed in the hope that it will be useful, | ||
| 88 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 89 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 90 | +# Lesser General Public License for more details. | ||
| 91 | +# | ||
| 92 | +# You should have received a copy of the GNU Lesser General Public | ||
| 93 | +# License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
| 94 | + | ||
| 95 | +# | ||
| 96 | +# This file is processed by scripts/decodetree.py | ||
| 97 | +# | ||
| 98 | + | ||
| 99 | +# Encodings for Neon load/store instructions where the T32 encoding | ||
| 100 | +# is a simple transformation of the A32 encoding. | ||
| 101 | +# More specifically, this file covers instructions where the A32 encoding is | ||
| 102 | +# 0b1111_0100_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx | ||
| 103 | +# and the T32 encoding is | ||
| 104 | +# 0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx | ||
| 105 | +# This file works on the A32 encoding only; calling code for T32 has to | ||
| 106 | +# transform the insn into the A32 version first. | ||
| 107 | diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode | ||
| 108 | new file mode 100644 | ||
| 109 | index XXXXXXX..XXXXXXX | ||
| 110 | --- /dev/null | ||
| 111 | +++ b/target/arm/neon-shared.decode | ||
| 112 | @@ -XXX,XX +XXX,XX @@ | ||
| 113 | +# AArch32 Neon instruction descriptions | ||
| 114 | +# | ||
| 115 | +# Copyright (c) 2020 Linaro, Ltd | ||
| 116 | +# | ||
| 117 | +# This library is free software; you can redistribute it and/or | ||
| 118 | +# modify it under the terms of the GNU Lesser General Public | ||
| 119 | +# License as published by the Free Software Foundation; either | ||
| 120 | +# version 2 of the License, or (at your option) any later version. | ||
| 121 | +# | ||
| 122 | +# This library is distributed in the hope that it will be useful, | ||
| 123 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 124 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 125 | +# Lesser General Public License for more details. | ||
| 126 | +# | ||
| 127 | +# You should have received a copy of the GNU Lesser General Public | ||
| 128 | +# License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
| 129 | + | ||
| 130 | +# | ||
| 131 | +# This file is processed by scripts/decodetree.py | ||
| 132 | +# | ||
| 133 | + | ||
| 134 | +# Encodings for Neon instructions whose encoding is the same for | ||
| 135 | +# both A32 and T32. | ||
| 136 | + | ||
| 137 | +# More specifically, this covers: | ||
| 138 | +# 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx | ||
| 139 | +# 3same ext: 0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx | ||
| 140 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 141 | new file mode 100644 | ||
| 142 | index XXXXXXX..XXXXXXX | ||
| 143 | --- /dev/null | ||
| 144 | +++ b/target/arm/translate-neon.inc.c | ||
| 145 | @@ -XXX,XX +XXX,XX @@ | 53 | @@ -XXX,XX +XXX,XX @@ |
| 146 | +/* | 54 | +/* |
| 147 | + * ARM translation: AArch32 Neon instructions | 55 | + * QEMU ARM stubs for some TCG helper functions |
| 148 | + * | 56 | + * |
| 149 | + * Copyright (c) 2003 Fabrice Bellard | 57 | + * Copyright 2021 SUSE LLC |
| 150 | + * Copyright (c) 2005-2007 CodeSourcery | ||
| 151 | + * Copyright (c) 2007 OpenedHand, Ltd. | ||
| 152 | + * Copyright (c) 2020 Linaro, Ltd. | ||
| 153 | + * | 58 | + * |
| 154 | + * This library is free software; you can redistribute it and/or | 59 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 155 | + * modify it under the terms of the GNU Lesser General Public | 60 | + * See the COPYING file in the top-level directory. |
| 156 | + * License as published by the Free Software Foundation; either | ||
| 157 | + * version 2 of the License, or (at your option) any later version. | ||
| 158 | + * | ||
| 159 | + * This library is distributed in the hope that it will be useful, | ||
| 160 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 161 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
| 162 | + * Lesser General Public License for more details. | ||
| 163 | + * | ||
| 164 | + * You should have received a copy of the GNU Lesser General Public | ||
| 165 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
| 166 | + */ | 61 | + */ |
| 167 | + | 62 | + |
| 168 | +/* | 63 | +#include "qemu/osdep.h" |
| 169 | + * This file is intended to be included from translate.c; it uses | 64 | +#include "cpu.h" |
| 170 | + * some macros and definitions provided by that file. | 65 | +#include "internals.h" |
| 171 | + * It might be possible to convert it to a standalone .c file eventually. | ||
| 172 | + */ | ||
| 173 | + | 66 | + |
| 174 | +/* Include the generated Neon decoder */ | 67 | +void write_v7m_exception(CPUARMState *env, uint32_t new_exc) |
| 175 | +#include "decode-neon-dp.inc.c" | 68 | +{ |
| 176 | +#include "decode-neon-ls.inc.c" | 69 | + g_assert_not_reached(); |
| 177 | +#include "decode-neon-shared.inc.c" | 70 | +} |
| 178 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 71 | + |
| 72 | +void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, | ||
| 73 | + uint32_t target_el, uintptr_t ra) | ||
| 74 | +{ | ||
| 75 | + g_assert_not_reached(); | ||
| 76 | +} | ||
| 77 | diff --git a/target/arm/crypto_helper.c b/target/arm/tcg/crypto_helper.c | ||
| 78 | similarity index 100% | ||
| 79 | rename from target/arm/crypto_helper.c | ||
| 80 | rename to target/arm/tcg/crypto_helper.c | ||
| 81 | diff --git a/target/arm/helper-a64.c b/target/arm/tcg/helper-a64.c | ||
| 82 | similarity index 100% | ||
| 83 | rename from target/arm/helper-a64.c | ||
| 84 | rename to target/arm/tcg/helper-a64.c | ||
| 85 | diff --git a/target/arm/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c | ||
| 86 | similarity index 100% | ||
| 87 | rename from target/arm/iwmmxt_helper.c | ||
| 88 | rename to target/arm/tcg/iwmmxt_helper.c | ||
| 89 | diff --git a/target/arm/m_helper.c b/target/arm/tcg/m_helper.c | ||
| 90 | similarity index 100% | ||
| 91 | rename from target/arm/m_helper.c | ||
| 92 | rename to target/arm/tcg/m_helper.c | ||
| 93 | diff --git a/target/arm/mte_helper.c b/target/arm/tcg/mte_helper.c | ||
| 94 | similarity index 100% | ||
| 95 | rename from target/arm/mte_helper.c | ||
| 96 | rename to target/arm/tcg/mte_helper.c | ||
| 97 | diff --git a/target/arm/mve_helper.c b/target/arm/tcg/mve_helper.c | ||
| 98 | similarity index 100% | ||
| 99 | rename from target/arm/mve_helper.c | ||
| 100 | rename to target/arm/tcg/mve_helper.c | ||
| 101 | diff --git a/target/arm/neon_helper.c b/target/arm/tcg/neon_helper.c | ||
| 102 | similarity index 100% | ||
| 103 | rename from target/arm/neon_helper.c | ||
| 104 | rename to target/arm/tcg/neon_helper.c | ||
| 105 | diff --git a/target/arm/op_helper.c b/target/arm/tcg/op_helper.c | ||
| 106 | similarity index 100% | ||
| 107 | rename from target/arm/op_helper.c | ||
| 108 | rename to target/arm/tcg/op_helper.c | ||
| 109 | diff --git a/target/arm/pauth_helper.c b/target/arm/tcg/pauth_helper.c | ||
| 110 | similarity index 100% | ||
| 111 | rename from target/arm/pauth_helper.c | ||
| 112 | rename to target/arm/tcg/pauth_helper.c | ||
| 113 | diff --git a/target/arm/sme_helper.c b/target/arm/tcg/sme_helper.c | ||
| 114 | similarity index 100% | ||
| 115 | rename from target/arm/sme_helper.c | ||
| 116 | rename to target/arm/tcg/sme_helper.c | ||
| 117 | diff --git a/target/arm/sve_helper.c b/target/arm/tcg/sve_helper.c | ||
| 118 | similarity index 100% | ||
| 119 | rename from target/arm/sve_helper.c | ||
| 120 | rename to target/arm/tcg/sve_helper.c | ||
| 121 | diff --git a/target/arm/tlb_helper.c b/target/arm/tcg/tlb_helper.c | ||
| 122 | similarity index 100% | ||
| 123 | rename from target/arm/tlb_helper.c | ||
| 124 | rename to target/arm/tcg/tlb_helper.c | ||
| 125 | diff --git a/target/arm/vec_helper.c b/target/arm/tcg/vec_helper.c | ||
| 126 | similarity index 100% | ||
| 127 | rename from target/arm/vec_helper.c | ||
| 128 | rename to target/arm/tcg/vec_helper.c | ||
| 129 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
| 179 | index XXXXXXX..XXXXXXX 100644 | 130 | index XXXXXXX..XXXXXXX 100644 |
| 180 | --- a/target/arm/translate.c | 131 | --- a/target/arm/meson.build |
| 181 | +++ b/target/arm/translate.c | 132 | +++ b/target/arm/meson.build |
| 182 | @@ -XXX,XX +XXX,XX @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) | 133 | @@ -XXX,XX +XXX,XX @@ |
| 183 | 134 | arm_ss = ss.source_set() | |
| 184 | #define ARM_CP_RW_BIT (1 << 20) | 135 | arm_ss.add(files( |
| 185 | 136 | 'cpu.c', | |
| 186 | -/* Include the VFP decoder */ | 137 | - 'crypto_helper.c', |
| 187 | +/* Include the VFP and Neon decoders */ | 138 | 'debug_helper.c', |
| 188 | #include "translate-vfp.inc.c" | 139 | 'gdbstub.c', |
| 189 | +#include "translate-neon.inc.c" | 140 | 'helper.c', |
| 190 | 141 | - 'iwmmxt_helper.c', | |
| 191 | static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) | 142 | - 'm_helper.c', |
| 192 | { | 143 | - 'mve_helper.c', |
| 193 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 144 | - 'neon_helper.c', |
| 194 | /* Unconditional instructions. */ | 145 | - 'op_helper.c', |
| 195 | /* TODO: Perhaps merge these into one decodetree output file. */ | 146 | - 'tlb_helper.c', |
| 196 | if (disas_a32_uncond(s, insn) || | 147 | - 'vec_helper.c', |
| 197 | - disas_vfp_uncond(s, insn)) { | 148 | 'vfp_helper.c', |
| 198 | + disas_vfp_uncond(s, insn) || | 149 | 'cpu_tcg.c', |
| 199 | + disas_neon_dp(s, insn) || | 150 | )) |
| 200 | + disas_neon_ls(s, insn) || | 151 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_false: fil |
| 201 | + disas_neon_shared(s, insn)) { | 152 | arm_ss.add(when: 'TARGET_AARCH64', if_true: files( |
| 202 | return; | 153 | 'cpu64.c', |
| 203 | } | 154 | 'gdbstub64.c', |
| 204 | /* fall back to legacy decoder */ | 155 | - 'helper-a64.c', |
| 205 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 156 | - 'mte_helper.c', |
| 206 | ARCH(6T2); | 157 | - 'pauth_helper.c', |
| 207 | } | 158 | - 'sve_helper.c', |
| 208 | 159 | - 'sme_helper.c', | |
| 209 | + if ((insn & 0xef000000) == 0xef000000) { | 160 | )) |
| 210 | + /* | 161 | |
| 211 | + * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq | 162 | arm_softmmu_ss = ss.source_set() |
| 212 | + * transform into | 163 | @@ -XXX,XX +XXX,XX @@ subdir('hvf') |
| 213 | + * A32 encodings 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq | 164 | |
| 214 | + */ | 165 | if 'CONFIG_TCG' in config_all |
| 215 | + uint32_t a32_insn = (insn & 0xe2ffffff) | | 166 | subdir('tcg') |
| 216 | + ((insn & (1 << 28)) >> 4) | (1 << 28); | 167 | +else |
| 217 | + | 168 | + arm_ss.add(files('tcg-stubs.c')) |
| 218 | + if (disas_neon_dp(s, a32_insn)) { | 169 | endif |
| 219 | + return; | 170 | |
| 220 | + } | 171 | target_arch += {'arm': arm_ss} |
| 221 | + } | 172 | diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build |
| 222 | + | ||
| 223 | + if ((insn & 0xff100000) == 0xf9000000) { | ||
| 224 | + /* | ||
| 225 | + * T32 encodings 0b1111_1001_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq | ||
| 226 | + * transform into | ||
| 227 | + * A32 encodings 0b1111_0100_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq | ||
| 228 | + */ | ||
| 229 | + uint32_t a32_insn = (insn & 0x00ffffff) | 0xf4000000; | ||
| 230 | + | ||
| 231 | + if (disas_neon_ls(s, a32_insn)) { | ||
| 232 | + return; | ||
| 233 | + } | ||
| 234 | + } | ||
| 235 | + | ||
| 236 | /* | ||
| 237 | * TODO: Perhaps merge these into one decodetree output file. | ||
| 238 | * Note disas_vfp is written for a32 with cond field in the | ||
| 239 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
| 240 | */ | ||
| 241 | if (disas_t32(s, insn) || | ||
| 242 | disas_vfp_uncond(s, insn) || | ||
| 243 | + disas_neon_shared(s, insn) || | ||
| 244 | ((insn >> 28) == 0xe && disas_vfp(s, insn))) { | ||
| 245 | return; | ||
| 246 | } | ||
| 247 | diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs | ||
| 248 | index XXXXXXX..XXXXXXX 100644 | 173 | index XXXXXXX..XXXXXXX 100644 |
| 249 | --- a/target/arm/Makefile.objs | 174 | --- a/target/arm/tcg/meson.build |
| 250 | +++ b/target/arm/Makefile.objs | 175 | +++ b/target/arm/tcg/meson.build |
| 251 | @@ -XXX,XX +XXX,XX @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE) | 176 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( |
| 252 | $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\ | 177 | 'translate-mve.c', |
| 253 | "GEN", $(TARGET_DIR)$@) | 178 | 'translate-neon.c', |
| 254 | 179 | 'translate-vfp.c', | |
| 255 | +target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE) | 180 | + 'crypto_helper.c', |
| 256 | + $(call quiet-command,\ | 181 | + 'iwmmxt_helper.c', |
| 257 | + $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\ | 182 | + 'm_helper.c', |
| 258 | + "GEN", $(TARGET_DIR)$@) | 183 | + 'mve_helper.c', |
| 259 | + | 184 | + 'neon_helper.c', |
| 260 | +target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE) | 185 | + 'op_helper.c', |
| 261 | + $(call quiet-command,\ | 186 | + 'tlb_helper.c', |
| 262 | + $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\ | 187 | + 'vec_helper.c', |
| 263 | + "GEN", $(TARGET_DIR)$@) | 188 | )) |
| 264 | + | 189 | |
| 265 | +target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE) | 190 | arm_ss.add(when: 'TARGET_AARCH64', if_true: files( |
| 266 | + $(call quiet-command,\ | 191 | 'translate-a64.c', |
| 267 | + $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\ | 192 | 'translate-sve.c', |
| 268 | + "GEN", $(TARGET_DIR)$@) | 193 | 'translate-sme.c', |
| 269 | + | 194 | + 'helper-a64.c', |
| 270 | target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE) | 195 | + 'mte_helper.c', |
| 271 | $(call quiet-command,\ | 196 | + 'pauth_helper.c', |
| 272 | $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\ | 197 | + 'sme_helper.c', |
| 273 | @@ -XXX,XX +XXX,XX @@ target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE) | 198 | + 'sve_helper.c', |
| 274 | "GEN", $(TARGET_DIR)$@) | 199 | )) |
| 275 | |||
| 276 | target/arm/translate-sve.o: target/arm/decode-sve.inc.c | ||
| 277 | +target/arm/translate.o: target/arm/decode-neon-shared.inc.c | ||
| 278 | +target/arm/translate.o: target/arm/decode-neon-dp.inc.c | ||
| 279 | +target/arm/translate.o: target/arm/decode-neon-ls.inc.c | ||
| 280 | target/arm/translate.o: target/arm/decode-vfp.inc.c | ||
| 281 | target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c | ||
| 282 | target/arm/translate.o: target/arm/decode-a32.inc.c | ||
| 283 | -- | 200 | -- |
| 284 | 2.20.1 | 201 | 2.34.1 |
| 285 | 202 | ||
| 286 | 203 | diff view generated by jsdifflib |
| 1 | Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping | 1 | From: Claudio Fontana <cfontana@suse.de> |
|---|---|---|---|
| 2 | to decodetree. | ||
| 3 | 2 | ||
| 3 | Signed-off-by: Claudio Fontana <cfontana@suse.de> | ||
| 4 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 7 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20200430181003.21682-19-peter.maydell@linaro.org | ||
| 7 | --- | 9 | --- |
| 8 | target/arm/neon-dp.decode | 6 ++++++ | 10 | target/arm/{ => tcg}/psci.c | 0 |
| 9 | target/arm/translate-neon.inc.c | 15 +++++++++++++++ | 11 | target/arm/meson.build | 1 - |
| 10 | target/arm/translate.c | 14 ++------------ | 12 | target/arm/tcg/meson.build | 4 ++++ |
| 11 | 3 files changed, 23 insertions(+), 12 deletions(-) | 13 | 3 files changed, 4 insertions(+), 1 deletion(-) |
| 14 | rename target/arm/{ => tcg}/psci.c (100%) | ||
| 12 | 15 | ||
| 13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | 16 | diff --git a/target/arm/psci.c b/target/arm/tcg/psci.c |
| 17 | similarity index 100% | ||
| 18 | rename from target/arm/psci.c | ||
| 19 | rename to target/arm/tcg/psci.c | ||
| 20 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/target/arm/neon-dp.decode | 22 | --- a/target/arm/meson.build |
| 16 | +++ b/target/arm/neon-dp.decode | 23 | +++ b/target/arm/meson.build |
| 17 | @@ -XXX,XX +XXX,XX @@ | 24 | @@ -XXX,XX +XXX,XX @@ arm_softmmu_ss.add(files( |
| 18 | @3same .... ... . . . size:2 .... .... .... . q:1 . . .... \ | 25 | 'arm-powerctl.c', |
| 19 | &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp | 26 | 'machine.c', |
| 20 | 27 | 'monitor.c', | |
| 21 | +VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same | 28 | - 'psci.c', |
| 22 | +VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same | 29 | 'ptw.c', |
| 30 | )) | ||
| 31 | |||
| 32 | diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | ||
| 34 | --- a/target/arm/tcg/meson.build | ||
| 35 | +++ b/target/arm/tcg/meson.build | ||
| 36 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( | ||
| 37 | 'sme_helper.c', | ||
| 38 | 'sve_helper.c', | ||
| 39 | )) | ||
| 23 | + | 40 | + |
| 24 | @3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \ | 41 | +arm_softmmu_ss.add(files( |
| 25 | &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 | 42 | + 'psci.c', |
| 26 | 43 | +)) | |
| 27 | @@ -XXX,XX +XXX,XX @@ VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic | ||
| 28 | VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic | ||
| 29 | VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic | ||
| 30 | |||
| 31 | +VQSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same | ||
| 32 | +VQSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same | ||
| 33 | + | ||
| 34 | VCGT_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same | ||
| 35 | VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same | ||
| 36 | VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same | ||
| 37 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 38 | index XXXXXXX..XXXXXXX 100644 | ||
| 39 | --- a/target/arm/translate-neon.inc.c | ||
| 40 | +++ b/target/arm/translate-neon.inc.c | ||
| 41 | @@ -XXX,XX +XXX,XX @@ static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | ||
| 42 | tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]); | ||
| 43 | } | ||
| 44 | DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s) | ||
| 45 | + | ||
| 46 | +#define DO_3SAME_GVEC4(INSN, OPARRAY) \ | ||
| 47 | + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ | ||
| 48 | + uint32_t rn_ofs, uint32_t rm_ofs, \ | ||
| 49 | + uint32_t oprsz, uint32_t maxsz) \ | ||
| 50 | + { \ | ||
| 51 | + tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), \ | ||
| 52 | + rn_ofs, rm_ofs, oprsz, maxsz, &OPARRAY[vece]); \ | ||
| 53 | + } \ | ||
| 54 | + DO_3SAME(INSN, gen_##INSN##_3s) | ||
| 55 | + | ||
| 56 | +DO_3SAME_GVEC4(VQADD_S, sqadd_op) | ||
| 57 | +DO_3SAME_GVEC4(VQADD_U, uqadd_op) | ||
| 58 | +DO_3SAME_GVEC4(VQSUB_S, sqsub_op) | ||
| 59 | +DO_3SAME_GVEC4(VQSUB_U, uqsub_op) | ||
| 60 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 61 | index XXXXXXX..XXXXXXX 100644 | ||
| 62 | --- a/target/arm/translate.c | ||
| 63 | +++ b/target/arm/translate.c | ||
| 64 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 65 | } | ||
| 66 | return 1; | ||
| 67 | |||
| 68 | - case NEON_3R_VQADD: | ||
| 69 | - tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), | ||
| 70 | - rn_ofs, rm_ofs, vec_size, vec_size, | ||
| 71 | - (u ? uqadd_op : sqadd_op) + size); | ||
| 72 | - return 0; | ||
| 73 | - | ||
| 74 | - case NEON_3R_VQSUB: | ||
| 75 | - tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), | ||
| 76 | - rn_ofs, rm_ofs, vec_size, vec_size, | ||
| 77 | - (u ? uqsub_op : sqsub_op) + size); | ||
| 78 | - return 0; | ||
| 79 | - | ||
| 80 | case NEON_3R_VMUL: /* VMUL */ | ||
| 81 | if (u) { | ||
| 82 | /* Polynomial case allows only P8. */ | ||
| 83 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 84 | case NEON_3R_VTST_VCEQ: | ||
| 85 | case NEON_3R_VCGT: | ||
| 86 | case NEON_3R_VCGE: | ||
| 87 | + case NEON_3R_VQADD: | ||
| 88 | + case NEON_3R_VQSUB: | ||
| 89 | /* Already handled by decodetree */ | ||
| 90 | return 1; | ||
| 91 | } | ||
| 92 | -- | 44 | -- |
| 93 | 2.20.1 | 45 | 2.34.1 |
| 94 | 46 | ||
| 95 | 47 | diff view generated by jsdifflib |
| 1 | The ARMv8.2-TTS2UXN feature extends the XN field in stage 2 | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | translation table descriptors from just bit [54] to bits [54:53], | 2 | |
| 3 | allowing stage 2 to control execution permissions separately for EL0 | 3 | This is in preparation to moving the hflags code into its own file |
| 4 | and EL1. Implement the new semantics of the XN field and enable | 4 | under the tcg/ directory. |
| 5 | the feature for our 'max' CPU. | 5 | |
| 6 | 6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | |
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Message-id: 20200330210400.11724-5-peter.maydell@linaro.org | ||
| 11 | --- | 10 | --- |
| 12 | target/arm/cpu.h | 15 +++++++++++++++ | 11 | hw/arm/boot.c | 6 +++++- |
| 13 | target/arm/cpu.c | 1 + | 12 | hw/intc/armv7m_nvic.c | 20 +++++++++++++------- |
| 14 | target/arm/cpu64.c | 2 ++ | 13 | target/arm/arm-powerctl.c | 7 +++++-- |
| 15 | target/arm/helper.c | 37 +++++++++++++++++++++++++++++++------ | 14 | target/arm/cpu.c | 3 ++- |
| 16 | 4 files changed, 49 insertions(+), 6 deletions(-) | 15 | target/arm/helper.c | 18 +++++++++++++----- |
| 17 | 16 | target/arm/machine.c | 5 ++++- | |
| 18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | 6 files changed, 42 insertions(+), 17 deletions(-) |
| 19 | index XXXXXXX..XXXXXXX 100644 | 18 | |
| 20 | --- a/target/arm/cpu.h | 19 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
| 21 | +++ b/target/arm/cpu.h | 20 | index XXXXXXX..XXXXXXX 100644 |
| 22 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) | 21 | --- a/hw/arm/boot.c |
| 23 | return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0; | 22 | +++ b/hw/arm/boot.c |
| 24 | } | 23 | @@ -XXX,XX +XXX,XX @@ |
| 25 | 24 | #include "hw/arm/boot.h" | |
| 26 | +static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id) | 25 | #include "hw/arm/linux-boot-if.h" |
| 27 | +{ | 26 | #include "sysemu/kvm.h" |
| 28 | + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0; | 27 | +#include "sysemu/tcg.h" |
| 29 | +} | 28 | #include "sysemu/sysemu.h" |
| 30 | + | 29 | #include "sysemu/numa.h" |
| 31 | /* | 30 | #include "hw/boards.h" |
| 32 | * 64-bit feature tests via id registers. | 31 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) |
| 33 | */ | 32 | info->secondary_cpu_reset_hook(cpu, info); |
| 34 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) | 33 | } |
| 35 | return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0; | 34 | } |
| 36 | } | 35 | - arm_rebuild_hflags(env); |
| 37 | 36 | + | |
| 38 | +static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) | 37 | + if (tcg_enabled()) { |
| 39 | +{ | 38 | + arm_rebuild_hflags(env); |
| 40 | + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; | 39 | + } |
| 41 | +} | 40 | } |
| 42 | + | 41 | } |
| 43 | /* | 42 | |
| 44 | * Feature tests for "does this exist in either 32-bit or 64-bit?" | 43 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c |
| 45 | */ | 44 | index XXXXXXX..XXXXXXX 100644 |
| 46 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) | 45 | --- a/hw/intc/armv7m_nvic.c |
| 47 | return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); | 46 | +++ b/hw/intc/armv7m_nvic.c |
| 48 | } | 47 | @@ -XXX,XX +XXX,XX @@ |
| 49 | 48 | #include "hw/intc/armv7m_nvic.h" | |
| 50 | +static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id) | 49 | #include "hw/irq.h" |
| 51 | +{ | 50 | #include "hw/qdev-properties.h" |
| 52 | + return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); | 51 | +#include "sysemu/tcg.h" |
| 53 | +} | 52 | #include "sysemu/runstate.h" |
| 54 | + | 53 | #include "target/arm/cpu.h" |
| 55 | /* | 54 | #include "exec/exec-all.h" |
| 56 | * Forward to the above feature tests given an ARMCPU pointer. | 55 | @@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, |
| 57 | */ | 56 | /* This is UNPREDICTABLE; treat as RAZ/WI */ |
| 57 | |||
| 58 | exit_ok: | ||
| 59 | - /* Ensure any changes made are reflected in the cached hflags. */ | ||
| 60 | - arm_rebuild_hflags(&s->cpu->env); | ||
| 61 | + if (tcg_enabled()) { | ||
| 62 | + /* Ensure any changes made are reflected in the cached hflags. */ | ||
| 63 | + arm_rebuild_hflags(&s->cpu->env); | ||
| 64 | + } | ||
| 65 | return MEMTX_OK; | ||
| 66 | } | ||
| 67 | |||
| 68 | @@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev) | ||
| 69 | } | ||
| 70 | } | ||
| 71 | |||
| 72 | - /* | ||
| 73 | - * We updated state that affects the CPU's MMUidx and thus its hflags; | ||
| 74 | - * and we can't guarantee that we run before the CPU reset function. | ||
| 75 | - */ | ||
| 76 | - arm_rebuild_hflags(&s->cpu->env); | ||
| 77 | + if (tcg_enabled()) { | ||
| 78 | + /* | ||
| 79 | + * We updated state that affects the CPU's MMUidx and thus its | ||
| 80 | + * hflags; and we can't guarantee that we run before the CPU | ||
| 81 | + * reset function. | ||
| 82 | + */ | ||
| 83 | + arm_rebuild_hflags(&s->cpu->env); | ||
| 84 | + } | ||
| 85 | } | ||
| 86 | |||
| 87 | static void nvic_systick_trigger(void *opaque, int n, int level) | ||
| 88 | diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c | ||
| 89 | index XXXXXXX..XXXXXXX 100644 | ||
| 90 | --- a/target/arm/arm-powerctl.c | ||
| 91 | +++ b/target/arm/arm-powerctl.c | ||
| 92 | @@ -XXX,XX +XXX,XX @@ | ||
| 93 | #include "arm-powerctl.h" | ||
| 94 | #include "qemu/log.h" | ||
| 95 | #include "qemu/main-loop.h" | ||
| 96 | +#include "sysemu/tcg.h" | ||
| 97 | |||
| 98 | #ifndef DEBUG_ARM_POWERCTL | ||
| 99 | #define DEBUG_ARM_POWERCTL 0 | ||
| 100 | @@ -XXX,XX +XXX,XX @@ static void arm_set_cpu_on_async_work(CPUState *target_cpu_state, | ||
| 101 | target_cpu->env.regs[0] = info->context_id; | ||
| 102 | } | ||
| 103 | |||
| 104 | - /* CP15 update requires rebuilding hflags */ | ||
| 105 | - arm_rebuild_hflags(&target_cpu->env); | ||
| 106 | + if (tcg_enabled()) { | ||
| 107 | + /* CP15 update requires rebuilding hflags */ | ||
| 108 | + arm_rebuild_hflags(&target_cpu->env); | ||
| 109 | + } | ||
| 110 | |||
| 111 | /* Start the new CPU at the requested address */ | ||
| 112 | cpu_set_pc(target_cpu_state, info->entry); | ||
| 58 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 113 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
| 59 | index XXXXXXX..XXXXXXX 100644 | 114 | index XXXXXXX..XXXXXXX 100644 |
| 60 | --- a/target/arm/cpu.c | 115 | --- a/target/arm/cpu.c |
| 61 | +++ b/target/arm/cpu.c | 116 | +++ b/target/arm/cpu.c |
| 62 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | 117 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset_hold(Object *obj) |
| 63 | t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | 118 | if (tcg_enabled()) { |
| 64 | t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | 119 | hw_breakpoint_update_all(cpu); |
| 65 | t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ | 120 | hw_watchpoint_update_all(cpu); |
| 66 | + t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ | 121 | + |
| 67 | cpu->isar.id_mmfr4 = t; | 122 | + arm_rebuild_hflags(env); |
| 68 | } | 123 | } |
| 69 | #endif | 124 | - arm_rebuild_hflags(env); |
| 70 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 125 | } |
| 71 | index XXXXXXX..XXXXXXX 100644 | 126 | |
| 72 | --- a/target/arm/cpu64.c | 127 | #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) |
| 73 | +++ b/target/arm/cpu64.c | ||
| 74 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 75 | t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); | ||
| 76 | t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ | ||
| 77 | t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ | ||
| 78 | + t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ | ||
| 79 | cpu->isar.id_aa64mmfr1 = t; | ||
| 80 | |||
| 81 | t = cpu->isar.id_aa64mmfr2; | ||
| 82 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 83 | u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ | ||
| 84 | u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
| 85 | u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ | ||
| 86 | + u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
| 87 | cpu->isar.id_mmfr4 = u; | ||
| 88 | |||
| 89 | u = cpu->isar.id_aa64dfr0; | ||
| 90 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 128 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
| 91 | index XXXXXXX..XXXXXXX 100644 | 129 | index XXXXXXX..XXXXXXX 100644 |
| 92 | --- a/target/arm/helper.c | 130 | --- a/target/arm/helper.c |
| 93 | +++ b/target/arm/helper.c | 131 | +++ b/target/arm/helper.c |
| 94 | @@ -XXX,XX +XXX,XX @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) | 132 | @@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 95 | * | 133 | /* This may enable/disable the MMU, so do a TLB flush. */ |
| 96 | * @env: CPUARMState | 134 | tlb_flush(CPU(cpu)); |
| 97 | * @s2ap: The 2-bit stage2 access permissions (S2AP) | 135 | |
| 98 | - * @xn: XN (execute-never) bit | 136 | - if (ri->type & ARM_CP_SUPPRESS_TB_END) { |
| 99 | + * @xn: XN (execute-never) bits | 137 | + if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) { |
| 100 | + * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 | 138 | /* |
| 101 | */ | 139 | * Normally we would always end the TB on an SCTLR write; see the |
| 102 | -static int get_S2prot(CPUARMState *env, int s2ap, int xn) | 140 | * comment in ARMCPRegInfo sctlr initialization below for why Xscale |
| 103 | +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) | 141 | @@ -XXX,XX +XXX,XX @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask) |
| 104 | { | 142 | memset(env->zarray, 0, sizeof(env->zarray)); |
| 105 | int prot = 0; | 143 | } |
| 106 | 144 | ||
| 107 | @@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn) | 145 | - arm_rebuild_hflags(env); |
| 108 | if (s2ap & 2) { | 146 | + if (tcg_enabled()) { |
| 109 | prot |= PAGE_WRITE; | 147 | + arm_rebuild_hflags(env); |
| 110 | } | 148 | + } |
| 111 | - if (!xn) { | 149 | } |
| 112 | - if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { | 150 | |
| 113 | + | 151 | static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, |
| 114 | + if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { | 152 | @@ -XXX,XX +XXX,XX @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, |
| 115 | + switch (xn) { | 153 | } |
| 116 | + case 0: | 154 | mask &= ~CACHED_CPSR_BITS; |
| 117 | prot |= PAGE_EXEC; | 155 | env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask); |
| 118 | + break; | 156 | - if (rebuild_hflags) { |
| 119 | + case 1: | 157 | + if (tcg_enabled() && rebuild_hflags) { |
| 120 | + if (s1_is_el0) { | 158 | arm_rebuild_hflags(env); |
| 121 | + prot |= PAGE_EXEC; | 159 | } |
| 122 | + } | 160 | } |
| 123 | + break; | 161 | @@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, |
| 124 | + case 2: | 162 | env->regs[14] = env->regs[15] + offset; |
| 125 | + break; | 163 | } |
| 126 | + case 3: | 164 | env->regs[15] = newpc; |
| 127 | + if (!s1_is_el0) { | 165 | - arm_rebuild_hflags(env); |
| 128 | + prot |= PAGE_EXEC; | 166 | + |
| 129 | + } | 167 | + if (tcg_enabled()) { |
| 130 | + break; | 168 | + arm_rebuild_hflags(env); |
| 131 | + default: | 169 | + } |
| 132 | + g_assert_not_reached(); | 170 | } |
| 133 | + } | 171 | |
| 134 | + } else { | 172 | static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) |
| 135 | + if (!extract32(xn, 1, 1)) { | 173 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) |
| 136 | + if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { | 174 | pstate_write(env, PSTATE_DAIF | new_mode); |
| 137 | + prot |= PAGE_EXEC; | 175 | env->aarch64 = true; |
| 138 | + } | 176 | aarch64_restore_sp(env, new_el); |
| 139 | } | 177 | - helper_rebuild_hflags_a64(env, new_el); |
| 140 | } | 178 | + |
| 141 | return prot; | 179 | + if (tcg_enabled()) { |
| 142 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | 180 | + helper_rebuild_hflags_a64(env, new_el); |
| 143 | } | 181 | + } |
| 144 | 182 | ||
| 145 | ap = extract32(attrs, 4, 2); | 183 | env->pc = addr; |
| 146 | - xn = extract32(attrs, 12, 1); | 184 | |
| 147 | 185 | diff --git a/target/arm/machine.c b/target/arm/machine.c | |
| 148 | if (mmu_idx == ARMMMUIdx_Stage2) { | 186 | index XXXXXXX..XXXXXXX 100644 |
| 149 | ns = true; | 187 | --- a/target/arm/machine.c |
| 150 | - *prot = get_S2prot(env, ap, xn); | 188 | +++ b/target/arm/machine.c |
| 151 | + xn = extract32(attrs, 11, 2); | 189 | @@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id) |
| 152 | + *prot = get_S2prot(env, ap, xn, s1_is_el0); | 190 | if (!kvm_enabled()) { |
| 153 | } else { | 191 | pmu_op_finish(&cpu->env); |
| 154 | ns = extract32(attrs, 3, 1); | 192 | } |
| 155 | + xn = extract32(attrs, 12, 1); | 193 | - arm_rebuild_hflags(&cpu->env); |
| 156 | pxn = extract32(attrs, 11, 1); | 194 | + |
| 157 | *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); | 195 | + if (tcg_enabled()) { |
| 158 | } | 196 | + arm_rebuild_hflags(&cpu->env); |
| 197 | + } | ||
| 198 | |||
| 199 | return 0; | ||
| 200 | } | ||
| 159 | -- | 201 | -- |
| 160 | 2.20.1 | 202 | 2.34.1 |
| 161 | 203 | ||
| 162 | 204 | diff view generated by jsdifflib |
| 1 | Convert the Neon "load/store multiple structures" insns to decodetree. | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | The hflags are used only for TCG code, so introduce a new file | ||
| 4 | hflags.c to keep that code. | ||
| 5 | |||
| 6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20200430181003.21682-12-peter.maydell@linaro.org | ||
| 6 | --- | 10 | --- |
| 7 | target/arm/neon-ls.decode | 7 ++ | 11 | target/arm/internals.h | 2 + |
| 8 | target/arm/translate-neon.inc.c | 124 ++++++++++++++++++++++++++++++++ | 12 | target/arm/helper.c | 393 +----------------------------------- |
| 9 | target/arm/translate.c | 91 +---------------------- | 13 | target/arm/tcg-stubs.c | 4 + |
| 10 | 3 files changed, 133 insertions(+), 89 deletions(-) | 14 | target/arm/tcg/hflags.c | 403 +++++++++++++++++++++++++++++++++++++ |
| 15 | target/arm/tcg/meson.build | 1 + | ||
| 16 | 5 files changed, 411 insertions(+), 392 deletions(-) | ||
| 17 | create mode 100644 target/arm/tcg/hflags.c | ||
| 11 | 18 | ||
| 12 | diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode | 19 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
| 13 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/target/arm/neon-ls.decode | 21 | --- a/target/arm/internals.h |
| 15 | +++ b/target/arm/neon-ls.decode | 22 | +++ b/target/arm/internals.h |
| 16 | @@ -XXX,XX +XXX,XX @@ | 23 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, |
| 17 | # 0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx | 24 | |
| 18 | # This file works on the A32 encoding only; calling code for T32 has to | 25 | int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); |
| 19 | # transform the insn into the A32 version first. | 26 | int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); |
| 20 | + | 27 | +int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx); |
| 21 | +%vd_dp 22:1 12:4 | 28 | |
| 22 | + | 29 | /* Determine if allocation tags are available. */ |
| 23 | +# Neon load/store multiple structures | 30 | static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, |
| 24 | + | 31 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_fgt_active(CPUARMState *env, int el) |
| 25 | +VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \ | 32 | (!arm_feature(env, ARM_FEATURE_EL3) || (env->cp15.scr_el3 & SCR_FGTEN)); |
| 26 | + vd=%vd_dp | 33 | } |
| 27 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 34 | |
| 35 | +void assert_hflags_rebuild_correctly(CPUARMState *env); | ||
| 36 | #endif | ||
| 37 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 28 | index XXXXXXX..XXXXXXX 100644 | 38 | index XXXXXXX..XXXXXXX 100644 |
| 29 | --- a/target/arm/translate-neon.inc.c | 39 | --- a/target/arm/helper.c |
| 30 | +++ b/target/arm/translate-neon.inc.c | 40 | +++ b/target/arm/helper.c |
| 31 | @@ -XXX,XX +XXX,XX @@ static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a) | 41 | @@ -XXX,XX +XXX,XX @@ int sme_exception_el(CPUARMState *env, int el) |
| 32 | gen_helper_gvec_fmlal_idx_a32); | 42 | return 0; |
| 33 | return true; | ||
| 34 | } | 43 | } |
| 35 | + | 44 | |
| 36 | +static struct { | 45 | -/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ |
| 37 | + int nregs; | 46 | -static bool sme_fa64(CPUARMState *env, int el) |
| 38 | + int interleave; | 47 | -{ |
| 39 | + int spacing; | 48 | - if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { |
| 40 | +} const neon_ls_element_type[11] = { | 49 | - return false; |
| 41 | + {1, 4, 1}, | 50 | - } |
| 42 | + {1, 4, 2}, | 51 | - |
| 43 | + {4, 1, 1}, | 52 | - if (el <= 1 && !el_is_in_host(env, el)) { |
| 44 | + {2, 2, 2}, | 53 | - if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { |
| 45 | + {1, 3, 1}, | 54 | - return false; |
| 46 | + {1, 3, 2}, | 55 | - } |
| 47 | + {3, 1, 1}, | 56 | - } |
| 48 | + {1, 1, 1}, | 57 | - if (el <= 2 && arm_is_el2_enabled(env)) { |
| 49 | + {1, 2, 1}, | 58 | - if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { |
| 50 | + {1, 2, 2}, | 59 | - return false; |
| 51 | + {2, 1, 1} | 60 | - } |
| 52 | +}; | 61 | - } |
| 53 | + | 62 | - if (arm_feature(env, ARM_FEATURE_EL3)) { |
| 54 | +static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn, | 63 | - if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { |
| 55 | + int stride) | 64 | - return false; |
| 56 | +{ | 65 | - } |
| 57 | + if (rm != 15) { | 66 | - } |
| 58 | + TCGv_i32 base; | 67 | - |
| 59 | + | 68 | - return true; |
| 60 | + base = load_reg(s, rn); | 69 | -} |
| 61 | + if (rm == 13) { | 70 | - |
| 62 | + tcg_gen_addi_i32(base, base, stride); | 71 | /* |
| 63 | + } else { | 72 | * Given that SVE is enabled, return the vector length for EL. |
| 64 | + TCGv_i32 index; | 73 | */ |
| 65 | + index = load_reg(s, rm); | 74 | @@ -XXX,XX +XXX,XX @@ int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) |
| 66 | + tcg_gen_add_i32(base, base, index); | 75 | } |
| 67 | + tcg_temp_free_i32(index); | ||
| 68 | + } | ||
| 69 | + store_reg(s, rn, base); | ||
| 70 | + } | ||
| 71 | +} | ||
| 72 | + | ||
| 73 | +static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) | ||
| 74 | +{ | ||
| 75 | + /* Neon load/store multiple structures */ | ||
| 76 | + int nregs, interleave, spacing, reg, n; | ||
| 77 | + MemOp endian = s->be_data; | ||
| 78 | + int mmu_idx = get_mem_index(s); | ||
| 79 | + int size = a->size; | ||
| 80 | + TCGv_i64 tmp64; | ||
| 81 | + TCGv_i32 addr, tmp; | ||
| 82 | + | ||
| 83 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
| 84 | + return false; | ||
| 85 | + } | ||
| 86 | + | ||
| 87 | + /* UNDEF accesses to D16-D31 if they don't exist */ | ||
| 88 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | ||
| 89 | + return false; | ||
| 90 | + } | ||
| 91 | + if (a->itype > 10) { | ||
| 92 | + return false; | ||
| 93 | + } | ||
| 94 | + /* Catch UNDEF cases for bad values of align field */ | ||
| 95 | + switch (a->itype & 0xc) { | ||
| 96 | + case 4: | ||
| 97 | + if (a->align >= 2) { | ||
| 98 | + return false; | ||
| 99 | + } | ||
| 100 | + break; | ||
| 101 | + case 8: | ||
| 102 | + if (a->align == 3) { | ||
| 103 | + return false; | ||
| 104 | + } | ||
| 105 | + break; | ||
| 106 | + default: | ||
| 107 | + break; | ||
| 108 | + } | ||
| 109 | + nregs = neon_ls_element_type[a->itype].nregs; | ||
| 110 | + interleave = neon_ls_element_type[a->itype].interleave; | ||
| 111 | + spacing = neon_ls_element_type[a->itype].spacing; | ||
| 112 | + if (size == 3 && (interleave | spacing) != 1) { | ||
| 113 | + return false; | ||
| 114 | + } | ||
| 115 | + | ||
| 116 | + if (!vfp_access_check(s)) { | ||
| 117 | + return true; | ||
| 118 | + } | ||
| 119 | + | ||
| 120 | + /* For our purposes, bytes are always little-endian. */ | ||
| 121 | + if (size == 0) { | ||
| 122 | + endian = MO_LE; | ||
| 123 | + } | ||
| 124 | + /* | ||
| 125 | + * Consecutive little-endian elements from a single register | ||
| 126 | + * can be promoted to a larger little-endian operation. | ||
| 127 | + */ | ||
| 128 | + if (interleave == 1 && endian == MO_LE) { | ||
| 129 | + size = 3; | ||
| 130 | + } | ||
| 131 | + tmp64 = tcg_temp_new_i64(); | ||
| 132 | + addr = tcg_temp_new_i32(); | ||
| 133 | + tmp = tcg_const_i32(1 << size); | ||
| 134 | + load_reg_var(s, addr, a->rn); | ||
| 135 | + for (reg = 0; reg < nregs; reg++) { | ||
| 136 | + for (n = 0; n < 8 >> size; n++) { | ||
| 137 | + int xs; | ||
| 138 | + for (xs = 0; xs < interleave; xs++) { | ||
| 139 | + int tt = a->vd + reg + spacing * xs; | ||
| 140 | + | ||
| 141 | + if (a->l) { | ||
| 142 | + gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size); | ||
| 143 | + neon_store_element64(tt, n, size, tmp64); | ||
| 144 | + } else { | ||
| 145 | + neon_load_element64(tmp64, tt, n, size); | ||
| 146 | + gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size); | ||
| 147 | + } | ||
| 148 | + tcg_gen_add_i32(addr, addr, tmp); | ||
| 149 | + } | ||
| 150 | + } | ||
| 151 | + } | ||
| 152 | + tcg_temp_free_i32(addr); | ||
| 153 | + tcg_temp_free_i32(tmp); | ||
| 154 | + tcg_temp_free_i64(tmp64); | ||
| 155 | + | ||
| 156 | + gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8); | ||
| 157 | + return true; | ||
| 158 | +} | ||
| 159 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 160 | index XXXXXXX..XXXXXXX 100644 | ||
| 161 | --- a/target/arm/translate.c | ||
| 162 | +++ b/target/arm/translate.c | ||
| 163 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) | ||
| 164 | } | 76 | } |
| 165 | 77 | ||
| 166 | 78 | -static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) | |
| 167 | -static struct { | 79 | +int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) |
| 168 | - int nregs; | ||
| 169 | - int interleave; | ||
| 170 | - int spacing; | ||
| 171 | -} const neon_ls_element_type[11] = { | ||
| 172 | - {1, 4, 1}, | ||
| 173 | - {1, 4, 2}, | ||
| 174 | - {4, 1, 1}, | ||
| 175 | - {2, 2, 2}, | ||
| 176 | - {1, 3, 1}, | ||
| 177 | - {1, 3, 2}, | ||
| 178 | - {3, 1, 1}, | ||
| 179 | - {1, 1, 1}, | ||
| 180 | - {1, 2, 1}, | ||
| 181 | - {1, 2, 2}, | ||
| 182 | - {2, 1, 1} | ||
| 183 | -}; | ||
| 184 | - | ||
| 185 | /* Translate a NEON load/store element instruction. Return nonzero if the | ||
| 186 | instruction is invalid. */ | ||
| 187 | static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) | ||
| 188 | { | 80 | { |
| 189 | int rd, rn, rm; | 81 | if (regime_has_2_ranges(mmu_idx)) { |
| 190 | - int op; | 82 | return extract64(tcr, 57, 2); |
| 191 | int nregs; | 83 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) |
| 192 | - int interleave; | 84 | return arm_mmu_idx_el(env, arm_current_el(env)); |
| 193 | - int spacing; | 85 | } |
| 194 | int stride; | 86 | |
| 195 | int size; | 87 | -static inline bool fgt_svc(CPUARMState *env, int el) |
| 196 | int reg; | 88 | -{ |
| 197 | int load; | 89 | - /* |
| 198 | - int n; | 90 | - * Assuming fine-grained-traps are active, return true if we |
| 199 | int vec_size; | 91 | - * should be trapping on SVC instructions. Only AArch64 can |
| 200 | - int mmu_idx; | 92 | - * trap on an SVC at EL1, but we don't need to special-case this |
| 201 | - MemOp endian; | 93 | - * because if this is AArch32 EL1 then arm_fgt_active() is false. |
| 202 | TCGv_i32 addr; | 94 | - * We also know el is 0 or 1. |
| 203 | TCGv_i32 tmp; | 95 | - */ |
| 204 | - TCGv_i32 tmp2; | 96 | - return el == 0 ? |
| 205 | - TCGv_i64 tmp64; | 97 | - FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) : |
| 206 | 98 | - FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); | |
| 207 | if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | 99 | -} |
| 208 | return 1; | 100 | - |
| 209 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) | 101 | -static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, |
| 210 | rn = (insn >> 16) & 0xf; | 102 | - ARMMMUIdx mmu_idx, |
| 211 | rm = insn & 0xf; | 103 | - CPUARMTBFlags flags) |
| 212 | load = (insn & (1 << 21)) != 0; | 104 | -{ |
| 213 | - endian = s->be_data; | 105 | - DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); |
| 214 | - mmu_idx = get_mem_index(s); | 106 | - DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); |
| 215 | if ((insn & (1 << 23)) == 0) { | 107 | - |
| 216 | - /* Load store all elements. */ | 108 | - if (arm_singlestep_active(env)) { |
| 217 | - op = (insn >> 8) & 0xf; | 109 | - DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); |
| 218 | - size = (insn >> 6) & 3; | 110 | - } |
| 219 | - if (op > 10) | 111 | - |
| 220 | - return 1; | 112 | - return flags; |
| 221 | - /* Catch UNDEF cases for bad values of align field */ | 113 | -} |
| 222 | - switch (op & 0xc) { | 114 | - |
| 223 | - case 4: | 115 | -static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, |
| 224 | - if (((insn >> 5) & 1) == 1) { | 116 | - ARMMMUIdx mmu_idx, |
| 225 | - return 1; | 117 | - CPUARMTBFlags flags) |
| 118 | -{ | ||
| 119 | - bool sctlr_b = arm_sctlr_b(env); | ||
| 120 | - | ||
| 121 | - if (sctlr_b) { | ||
| 122 | - DP_TBFLAG_A32(flags, SCTLR__B, 1); | ||
| 123 | - } | ||
| 124 | - if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { | ||
| 125 | - DP_TBFLAG_ANY(flags, BE_DATA, 1); | ||
| 126 | - } | ||
| 127 | - DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); | ||
| 128 | - | ||
| 129 | - return rebuild_hflags_common(env, fp_el, mmu_idx, flags); | ||
| 130 | -} | ||
| 131 | - | ||
| 132 | -static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, | ||
| 133 | - ARMMMUIdx mmu_idx) | ||
| 134 | -{ | ||
| 135 | - CPUARMTBFlags flags = {}; | ||
| 136 | - uint32_t ccr = env->v7m.ccr[env->v7m.secure]; | ||
| 137 | - | ||
| 138 | - /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ | ||
| 139 | - if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { | ||
| 140 | - DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | ||
| 141 | - } | ||
| 142 | - | ||
| 143 | - if (arm_v7m_is_handler_mode(env)) { | ||
| 144 | - DP_TBFLAG_M32(flags, HANDLER, 1); | ||
| 145 | - } | ||
| 146 | - | ||
| 147 | - /* | ||
| 148 | - * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN | ||
| 149 | - * is suppressing them because the requested execution priority | ||
| 150 | - * is less than 0. | ||
| 151 | - */ | ||
| 152 | - if (arm_feature(env, ARM_FEATURE_V8) && | ||
| 153 | - !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && | ||
| 154 | - (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { | ||
| 155 | - DP_TBFLAG_M32(flags, STACKCHECK, 1); | ||
| 156 | - } | ||
| 157 | - | ||
| 158 | - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { | ||
| 159 | - DP_TBFLAG_M32(flags, SECURE, 1); | ||
| 160 | - } | ||
| 161 | - | ||
| 162 | - return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | ||
| 163 | -} | ||
| 164 | - | ||
| 165 | -static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, | ||
| 166 | - ARMMMUIdx mmu_idx) | ||
| 167 | -{ | ||
| 168 | - CPUARMTBFlags flags = {}; | ||
| 169 | - int el = arm_current_el(env); | ||
| 170 | - | ||
| 171 | - if (arm_sctlr(env, el) & SCTLR_A) { | ||
| 172 | - DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | ||
| 173 | - } | ||
| 174 | - | ||
| 175 | - if (arm_el_is_aa64(env, 1)) { | ||
| 176 | - DP_TBFLAG_A32(flags, VFPEN, 1); | ||
| 177 | - } | ||
| 178 | - | ||
| 179 | - if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && | ||
| 180 | - (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | ||
| 181 | - DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); | ||
| 182 | - } | ||
| 183 | - | ||
| 184 | - if (arm_fgt_active(env, el)) { | ||
| 185 | - DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); | ||
| 186 | - if (fgt_svc(env, el)) { | ||
| 187 | - DP_TBFLAG_ANY(flags, FGT_SVC, 1); | ||
| 188 | - } | ||
| 189 | - } | ||
| 190 | - | ||
| 191 | - if (env->uncached_cpsr & CPSR_IL) { | ||
| 192 | - DP_TBFLAG_ANY(flags, PSTATE__IL, 1); | ||
| 193 | - } | ||
| 194 | - | ||
| 195 | - /* | ||
| 196 | - * The SME exception we are testing for is raised via | ||
| 197 | - * AArch64.CheckFPAdvSIMDEnabled(), as called from | ||
| 198 | - * AArch32.CheckAdvSIMDOrFPEnabled(). | ||
| 199 | - */ | ||
| 200 | - if (el == 0 | ||
| 201 | - && FIELD_EX64(env->svcr, SVCR, SM) | ||
| 202 | - && (!arm_is_el2_enabled(env) | ||
| 203 | - || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) | ||
| 204 | - && arm_el_is_aa64(env, 1) | ||
| 205 | - && !sme_fa64(env, el)) { | ||
| 206 | - DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); | ||
| 207 | - } | ||
| 208 | - | ||
| 209 | - return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | ||
| 210 | -} | ||
| 211 | - | ||
| 212 | -static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, | ||
| 213 | - ARMMMUIdx mmu_idx) | ||
| 214 | -{ | ||
| 215 | - CPUARMTBFlags flags = {}; | ||
| 216 | - ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); | ||
| 217 | - uint64_t tcr = regime_tcr(env, mmu_idx); | ||
| 218 | - uint64_t sctlr; | ||
| 219 | - int tbii, tbid; | ||
| 220 | - | ||
| 221 | - DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); | ||
| 222 | - | ||
| 223 | - /* Get control bits for tagged addresses. */ | ||
| 224 | - tbid = aa64_va_parameter_tbi(tcr, mmu_idx); | ||
| 225 | - tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); | ||
| 226 | - | ||
| 227 | - DP_TBFLAG_A64(flags, TBII, tbii); | ||
| 228 | - DP_TBFLAG_A64(flags, TBID, tbid); | ||
| 229 | - | ||
| 230 | - if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { | ||
| 231 | - int sve_el = sve_exception_el(env, el); | ||
| 232 | - | ||
| 233 | - /* | ||
| 234 | - * If either FP or SVE are disabled, translator does not need len. | ||
| 235 | - * If SVE EL > FP EL, FP exception has precedence, and translator | ||
| 236 | - * does not need SVE EL. Save potential re-translations by forcing | ||
| 237 | - * the unneeded data to zero. | ||
| 238 | - */ | ||
| 239 | - if (fp_el != 0) { | ||
| 240 | - if (sve_el > fp_el) { | ||
| 241 | - sve_el = 0; | ||
| 226 | - } | 242 | - } |
| 243 | - } else if (sve_el == 0) { | ||
| 244 | - DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); | ||
| 245 | - } | ||
| 246 | - DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); | ||
| 247 | - } | ||
| 248 | - if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { | ||
| 249 | - int sme_el = sme_exception_el(env, el); | ||
| 250 | - bool sm = FIELD_EX64(env->svcr, SVCR, SM); | ||
| 251 | - | ||
| 252 | - DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); | ||
| 253 | - if (sme_el == 0) { | ||
| 254 | - /* Similarly, do not compute SVL if SME is disabled. */ | ||
| 255 | - int svl = sve_vqm1_for_el_sm(env, el, true); | ||
| 256 | - DP_TBFLAG_A64(flags, SVL, svl); | ||
| 257 | - if (sm) { | ||
| 258 | - /* If SVE is disabled, we will not have set VL above. */ | ||
| 259 | - DP_TBFLAG_A64(flags, VL, svl); | ||
| 260 | - } | ||
| 261 | - } | ||
| 262 | - if (sm) { | ||
| 263 | - DP_TBFLAG_A64(flags, PSTATE_SM, 1); | ||
| 264 | - DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); | ||
| 265 | - } | ||
| 266 | - DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); | ||
| 267 | - } | ||
| 268 | - | ||
| 269 | - sctlr = regime_sctlr(env, stage1); | ||
| 270 | - | ||
| 271 | - if (sctlr & SCTLR_A) { | ||
| 272 | - DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | ||
| 273 | - } | ||
| 274 | - | ||
| 275 | - if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { | ||
| 276 | - DP_TBFLAG_ANY(flags, BE_DATA, 1); | ||
| 277 | - } | ||
| 278 | - | ||
| 279 | - if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { | ||
| 280 | - /* | ||
| 281 | - * In order to save space in flags, we record only whether | ||
| 282 | - * pauth is "inactive", meaning all insns are implemented as | ||
| 283 | - * a nop, or "active" when some action must be performed. | ||
| 284 | - * The decision of which action to take is left to a helper. | ||
| 285 | - */ | ||
| 286 | - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { | ||
| 287 | - DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); | ||
| 288 | - } | ||
| 289 | - } | ||
| 290 | - | ||
| 291 | - if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { | ||
| 292 | - /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ | ||
| 293 | - if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { | ||
| 294 | - DP_TBFLAG_A64(flags, BT, 1); | ||
| 295 | - } | ||
| 296 | - } | ||
| 297 | - | ||
| 298 | - /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ | ||
| 299 | - if (!(env->pstate & PSTATE_UAO)) { | ||
| 300 | - switch (mmu_idx) { | ||
| 301 | - case ARMMMUIdx_E10_1: | ||
| 302 | - case ARMMMUIdx_E10_1_PAN: | ||
| 303 | - /* TODO: ARMv8.3-NV */ | ||
| 304 | - DP_TBFLAG_A64(flags, UNPRIV, 1); | ||
| 227 | - break; | 305 | - break; |
| 228 | - case 8: | 306 | - case ARMMMUIdx_E20_2: |
| 229 | - if (((insn >> 4) & 3) == 3) { | 307 | - case ARMMMUIdx_E20_2_PAN: |
| 230 | - return 1; | 308 | - /* |
| 309 | - * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is | ||
| 310 | - * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. | ||
| 311 | - */ | ||
| 312 | - if (env->cp15.hcr_el2 & HCR_TGE) { | ||
| 313 | - DP_TBFLAG_A64(flags, UNPRIV, 1); | ||
| 231 | - } | 314 | - } |
| 232 | - break; | 315 | - break; |
| 233 | - default: | 316 | - default: |
| 234 | - break; | 317 | - break; |
| 235 | - } | 318 | - } |
| 236 | - nregs = neon_ls_element_type[op].nregs; | 319 | - } |
| 237 | - interleave = neon_ls_element_type[op].interleave; | 320 | - |
| 238 | - spacing = neon_ls_element_type[op].spacing; | 321 | - if (env->pstate & PSTATE_IL) { |
| 239 | - if (size == 3 && (interleave | spacing) != 1) { | 322 | - DP_TBFLAG_ANY(flags, PSTATE__IL, 1); |
| 240 | - return 1; | 323 | - } |
| 241 | - } | 324 | - |
| 242 | - /* For our purposes, bytes are always little-endian. */ | 325 | - if (arm_fgt_active(env, el)) { |
| 243 | - if (size == 0) { | 326 | - DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); |
| 244 | - endian = MO_LE; | 327 | - if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { |
| 245 | - } | 328 | - DP_TBFLAG_A64(flags, FGT_ERET, 1); |
| 246 | - /* Consecutive little-endian elements from a single register | 329 | - } |
| 247 | - * can be promoted to a larger little-endian operation. | 330 | - if (fgt_svc(env, el)) { |
| 331 | - DP_TBFLAG_ANY(flags, FGT_SVC, 1); | ||
| 332 | - } | ||
| 333 | - } | ||
| 334 | - | ||
| 335 | - if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { | ||
| 336 | - /* | ||
| 337 | - * Set MTE_ACTIVE if any access may be Checked, and leave clear | ||
| 338 | - * if all accesses must be Unchecked: | ||
| 339 | - * 1) If no TBI, then there are no tags in the address to check, | ||
| 340 | - * 2) If Tag Check Override, then all accesses are Unchecked, | ||
| 341 | - * 3) If Tag Check Fail == 0, then Checked access have no effect, | ||
| 342 | - * 4) If no Allocation Tag Access, then all accesses are Unchecked. | ||
| 248 | - */ | 343 | - */ |
| 249 | - if (interleave == 1 && endian == MO_LE) { | 344 | - if (allocation_tag_access_enabled(env, el, sctlr)) { |
| 250 | - size = 3; | 345 | - DP_TBFLAG_A64(flags, ATA, 1); |
| 251 | - } | 346 | - if (tbid |
| 252 | - tmp64 = tcg_temp_new_i64(); | 347 | - && !(env->pstate & PSTATE_TCO) |
| 253 | - addr = tcg_temp_new_i32(); | 348 | - && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { |
| 254 | - tmp2 = tcg_const_i32(1 << size); | 349 | - DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); |
| 255 | - load_reg_var(s, addr, rn); | ||
| 256 | - for (reg = 0; reg < nregs; reg++) { | ||
| 257 | - for (n = 0; n < 8 >> size; n++) { | ||
| 258 | - int xs; | ||
| 259 | - for (xs = 0; xs < interleave; xs++) { | ||
| 260 | - int tt = rd + reg + spacing * xs; | ||
| 261 | - | ||
| 262 | - if (load) { | ||
| 263 | - gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size); | ||
| 264 | - neon_store_element64(tt, n, size, tmp64); | ||
| 265 | - } else { | ||
| 266 | - neon_load_element64(tmp64, tt, n, size); | ||
| 267 | - gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size); | ||
| 268 | - } | ||
| 269 | - tcg_gen_add_i32(addr, addr, tmp2); | ||
| 270 | - } | ||
| 271 | - } | 350 | - } |
| 272 | - } | 351 | - } |
| 273 | - tcg_temp_free_i32(addr); | 352 | - /* And again for unprivileged accesses, if required. */ |
| 274 | - tcg_temp_free_i32(tmp2); | 353 | - if (EX_TBFLAG_A64(flags, UNPRIV) |
| 275 | - tcg_temp_free_i64(tmp64); | 354 | - && tbid |
| 276 | - stride = nregs * interleave * 8; | 355 | - && !(env->pstate & PSTATE_TCO) |
| 277 | + /* Load store all elements -- handled already by decodetree */ | 356 | - && (sctlr & SCTLR_TCF0) |
| 278 | + return 1; | 357 | - && allocation_tag_access_enabled(env, 0, sctlr)) { |
| 279 | } else { | 358 | - DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); |
| 280 | size = (insn >> 10) & 3; | 359 | - } |
| 281 | if (size == 3) { | 360 | - /* Cache TCMA as well as TBI. */ |
| 361 | - DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); | ||
| 362 | - } | ||
| 363 | - | ||
| 364 | - return rebuild_hflags_common(env, fp_el, mmu_idx, flags); | ||
| 365 | -} | ||
| 366 | - | ||
| 367 | -static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) | ||
| 368 | -{ | ||
| 369 | - int el = arm_current_el(env); | ||
| 370 | - int fp_el = fp_exception_el(env, el); | ||
| 371 | - ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 372 | - | ||
| 373 | - if (is_a64(env)) { | ||
| 374 | - return rebuild_hflags_a64(env, el, fp_el, mmu_idx); | ||
| 375 | - } else if (arm_feature(env, ARM_FEATURE_M)) { | ||
| 376 | - return rebuild_hflags_m32(env, fp_el, mmu_idx); | ||
| 377 | - } else { | ||
| 378 | - return rebuild_hflags_a32(env, fp_el, mmu_idx); | ||
| 379 | - } | ||
| 380 | -} | ||
| 381 | - | ||
| 382 | -void arm_rebuild_hflags(CPUARMState *env) | ||
| 383 | -{ | ||
| 384 | - env->hflags = rebuild_hflags_internal(env); | ||
| 385 | -} | ||
| 386 | - | ||
| 387 | -/* | ||
| 388 | - * If we have triggered a EL state change we can't rely on the | ||
| 389 | - * translator having passed it to us, we need to recompute. | ||
| 390 | - */ | ||
| 391 | -void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) | ||
| 392 | -{ | ||
| 393 | - int el = arm_current_el(env); | ||
| 394 | - int fp_el = fp_exception_el(env, el); | ||
| 395 | - ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 396 | - | ||
| 397 | - env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); | ||
| 398 | -} | ||
| 399 | - | ||
| 400 | -void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) | ||
| 401 | -{ | ||
| 402 | - int fp_el = fp_exception_el(env, el); | ||
| 403 | - ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 404 | - | ||
| 405 | - env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); | ||
| 406 | -} | ||
| 407 | - | ||
| 408 | -/* | ||
| 409 | - * If we have triggered a EL state change we can't rely on the | ||
| 410 | - * translator having passed it to us, we need to recompute. | ||
| 411 | - */ | ||
| 412 | -void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) | ||
| 413 | -{ | ||
| 414 | - int el = arm_current_el(env); | ||
| 415 | - int fp_el = fp_exception_el(env, el); | ||
| 416 | - ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 417 | - env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | ||
| 418 | -} | ||
| 419 | - | ||
| 420 | -void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) | ||
| 421 | -{ | ||
| 422 | - int fp_el = fp_exception_el(env, el); | ||
| 423 | - ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 424 | - | ||
| 425 | - env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | ||
| 426 | -} | ||
| 427 | - | ||
| 428 | -void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) | ||
| 429 | -{ | ||
| 430 | - int fp_el = fp_exception_el(env, el); | ||
| 431 | - ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 432 | - | ||
| 433 | - env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); | ||
| 434 | -} | ||
| 435 | - | ||
| 436 | -static inline void assert_hflags_rebuild_correctly(CPUARMState *env) | ||
| 437 | -{ | ||
| 438 | -#ifdef CONFIG_DEBUG_TCG | ||
| 439 | - CPUARMTBFlags c = env->hflags; | ||
| 440 | - CPUARMTBFlags r = rebuild_hflags_internal(env); | ||
| 441 | - | ||
| 442 | - if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) { | ||
| 443 | - fprintf(stderr, "TCG hflags mismatch " | ||
| 444 | - "(current:(0x%08x,0x" TARGET_FMT_lx ")" | ||
| 445 | - " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", | ||
| 446 | - c.flags, c.flags2, r.flags, r.flags2); | ||
| 447 | - abort(); | ||
| 448 | - } | ||
| 449 | -#endif | ||
| 450 | -} | ||
| 451 | - | ||
| 452 | static bool mve_no_pred(CPUARMState *env) | ||
| 453 | { | ||
| 454 | /* | ||
| 455 | diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c | ||
| 456 | index XXXXXXX..XXXXXXX 100644 | ||
| 457 | --- a/target/arm/tcg-stubs.c | ||
| 458 | +++ b/target/arm/tcg-stubs.c | ||
| 459 | @@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, | ||
| 460 | { | ||
| 461 | g_assert_not_reached(); | ||
| 462 | } | ||
| 463 | +/* Temporarily while cpu_get_tb_cpu_state() is still in common code */ | ||
| 464 | +void assert_hflags_rebuild_correctly(CPUARMState *env) | ||
| 465 | +{ | ||
| 466 | +} | ||
| 467 | diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c | ||
| 468 | new file mode 100644 | ||
| 469 | index XXXXXXX..XXXXXXX | ||
| 470 | --- /dev/null | ||
| 471 | +++ b/target/arm/tcg/hflags.c | ||
| 472 | @@ -XXX,XX +XXX,XX @@ | ||
| 473 | +/* | ||
| 474 | + * ARM hflags | ||
| 475 | + * | ||
| 476 | + * This code is licensed under the GNU GPL v2 or later. | ||
| 477 | + * | ||
| 478 | + * SPDX-License-Identifier: GPL-2.0-or-later | ||
| 479 | + */ | ||
| 480 | +#include "qemu/osdep.h" | ||
| 481 | +#include "cpu.h" | ||
| 482 | +#include "internals.h" | ||
| 483 | +#include "exec/helper-proto.h" | ||
| 484 | +#include "cpregs.h" | ||
| 485 | + | ||
| 486 | +static inline bool fgt_svc(CPUARMState *env, int el) | ||
| 487 | +{ | ||
| 488 | + /* | ||
| 489 | + * Assuming fine-grained-traps are active, return true if we | ||
| 490 | + * should be trapping on SVC instructions. Only AArch64 can | ||
| 491 | + * trap on an SVC at EL1, but we don't need to special-case this | ||
| 492 | + * because if this is AArch32 EL1 then arm_fgt_active() is false. | ||
| 493 | + * We also know el is 0 or 1. | ||
| 494 | + */ | ||
| 495 | + return el == 0 ? | ||
| 496 | + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL0) : | ||
| 497 | + FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); | ||
| 498 | +} | ||
| 499 | + | ||
| 500 | +static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, | ||
| 501 | + ARMMMUIdx mmu_idx, | ||
| 502 | + CPUARMTBFlags flags) | ||
| 503 | +{ | ||
| 504 | + DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el); | ||
| 505 | + DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); | ||
| 506 | + | ||
| 507 | + if (arm_singlestep_active(env)) { | ||
| 508 | + DP_TBFLAG_ANY(flags, SS_ACTIVE, 1); | ||
| 509 | + } | ||
| 510 | + | ||
| 511 | + return flags; | ||
| 512 | +} | ||
| 513 | + | ||
| 514 | +static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el, | ||
| 515 | + ARMMMUIdx mmu_idx, | ||
| 516 | + CPUARMTBFlags flags) | ||
| 517 | +{ | ||
| 518 | + bool sctlr_b = arm_sctlr_b(env); | ||
| 519 | + | ||
| 520 | + if (sctlr_b) { | ||
| 521 | + DP_TBFLAG_A32(flags, SCTLR__B, 1); | ||
| 522 | + } | ||
| 523 | + if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) { | ||
| 524 | + DP_TBFLAG_ANY(flags, BE_DATA, 1); | ||
| 525 | + } | ||
| 526 | + DP_TBFLAG_A32(flags, NS, !access_secure_reg(env)); | ||
| 527 | + | ||
| 528 | + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); | ||
| 529 | +} | ||
| 530 | + | ||
| 531 | +static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, | ||
| 532 | + ARMMMUIdx mmu_idx) | ||
| 533 | +{ | ||
| 534 | + CPUARMTBFlags flags = {}; | ||
| 535 | + uint32_t ccr = env->v7m.ccr[env->v7m.secure]; | ||
| 536 | + | ||
| 537 | + /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */ | ||
| 538 | + if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) { | ||
| 539 | + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | ||
| 540 | + } | ||
| 541 | + | ||
| 542 | + if (arm_v7m_is_handler_mode(env)) { | ||
| 543 | + DP_TBFLAG_M32(flags, HANDLER, 1); | ||
| 544 | + } | ||
| 545 | + | ||
| 546 | + /* | ||
| 547 | + * v8M always applies stack limit checks unless CCR.STKOFHFNMIGN | ||
| 548 | + * is suppressing them because the requested execution priority | ||
| 549 | + * is less than 0. | ||
| 550 | + */ | ||
| 551 | + if (arm_feature(env, ARM_FEATURE_V8) && | ||
| 552 | + !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && | ||
| 553 | + (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) { | ||
| 554 | + DP_TBFLAG_M32(flags, STACKCHECK, 1); | ||
| 555 | + } | ||
| 556 | + | ||
| 557 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) { | ||
| 558 | + DP_TBFLAG_M32(flags, SECURE, 1); | ||
| 559 | + } | ||
| 560 | + | ||
| 561 | + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | ||
| 562 | +} | ||
| 563 | + | ||
| 564 | +/* This corresponds to the ARM pseudocode function IsFullA64Enabled(). */ | ||
| 565 | +static bool sme_fa64(CPUARMState *env, int el) | ||
| 566 | +{ | ||
| 567 | + if (!cpu_isar_feature(aa64_sme_fa64, env_archcpu(env))) { | ||
| 568 | + return false; | ||
| 569 | + } | ||
| 570 | + | ||
| 571 | + if (el <= 1 && !el_is_in_host(env, el)) { | ||
| 572 | + if (!FIELD_EX64(env->vfp.smcr_el[1], SMCR, FA64)) { | ||
| 573 | + return false; | ||
| 574 | + } | ||
| 575 | + } | ||
| 576 | + if (el <= 2 && arm_is_el2_enabled(env)) { | ||
| 577 | + if (!FIELD_EX64(env->vfp.smcr_el[2], SMCR, FA64)) { | ||
| 578 | + return false; | ||
| 579 | + } | ||
| 580 | + } | ||
| 581 | + if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
| 582 | + if (!FIELD_EX64(env->vfp.smcr_el[3], SMCR, FA64)) { | ||
| 583 | + return false; | ||
| 584 | + } | ||
| 585 | + } | ||
| 586 | + | ||
| 587 | + return true; | ||
| 588 | +} | ||
| 589 | + | ||
| 590 | +static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, | ||
| 591 | + ARMMMUIdx mmu_idx) | ||
| 592 | +{ | ||
| 593 | + CPUARMTBFlags flags = {}; | ||
| 594 | + int el = arm_current_el(env); | ||
| 595 | + | ||
| 596 | + if (arm_sctlr(env, el) & SCTLR_A) { | ||
| 597 | + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | ||
| 598 | + } | ||
| 599 | + | ||
| 600 | + if (arm_el_is_aa64(env, 1)) { | ||
| 601 | + DP_TBFLAG_A32(flags, VFPEN, 1); | ||
| 602 | + } | ||
| 603 | + | ||
| 604 | + if (el < 2 && env->cp15.hstr_el2 && arm_is_el2_enabled(env) && | ||
| 605 | + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) { | ||
| 606 | + DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1); | ||
| 607 | + } | ||
| 608 | + | ||
| 609 | + if (arm_fgt_active(env, el)) { | ||
| 610 | + DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); | ||
| 611 | + if (fgt_svc(env, el)) { | ||
| 612 | + DP_TBFLAG_ANY(flags, FGT_SVC, 1); | ||
| 613 | + } | ||
| 614 | + } | ||
| 615 | + | ||
| 616 | + if (env->uncached_cpsr & CPSR_IL) { | ||
| 617 | + DP_TBFLAG_ANY(flags, PSTATE__IL, 1); | ||
| 618 | + } | ||
| 619 | + | ||
| 620 | + /* | ||
| 621 | + * The SME exception we are testing for is raised via | ||
| 622 | + * AArch64.CheckFPAdvSIMDEnabled(), as called from | ||
| 623 | + * AArch32.CheckAdvSIMDOrFPEnabled(). | ||
| 624 | + */ | ||
| 625 | + if (el == 0 | ||
| 626 | + && FIELD_EX64(env->svcr, SVCR, SM) | ||
| 627 | + && (!arm_is_el2_enabled(env) | ||
| 628 | + || (arm_el_is_aa64(env, 2) && !(env->cp15.hcr_el2 & HCR_TGE))) | ||
| 629 | + && arm_el_is_aa64(env, 1) | ||
| 630 | + && !sme_fa64(env, el)) { | ||
| 631 | + DP_TBFLAG_A32(flags, SME_TRAP_NONSTREAMING, 1); | ||
| 632 | + } | ||
| 633 | + | ||
| 634 | + return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); | ||
| 635 | +} | ||
| 636 | + | ||
| 637 | +static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, | ||
| 638 | + ARMMMUIdx mmu_idx) | ||
| 639 | +{ | ||
| 640 | + CPUARMTBFlags flags = {}; | ||
| 641 | + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); | ||
| 642 | + uint64_t tcr = regime_tcr(env, mmu_idx); | ||
| 643 | + uint64_t sctlr; | ||
| 644 | + int tbii, tbid; | ||
| 645 | + | ||
| 646 | + DP_TBFLAG_ANY(flags, AARCH64_STATE, 1); | ||
| 647 | + | ||
| 648 | + /* Get control bits for tagged addresses. */ | ||
| 649 | + tbid = aa64_va_parameter_tbi(tcr, mmu_idx); | ||
| 650 | + tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); | ||
| 651 | + | ||
| 652 | + DP_TBFLAG_A64(flags, TBII, tbii); | ||
| 653 | + DP_TBFLAG_A64(flags, TBID, tbid); | ||
| 654 | + | ||
| 655 | + if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { | ||
| 656 | + int sve_el = sve_exception_el(env, el); | ||
| 657 | + | ||
| 658 | + /* | ||
| 659 | + * If either FP or SVE are disabled, translator does not need len. | ||
| 660 | + * If SVE EL > FP EL, FP exception has precedence, and translator | ||
| 661 | + * does not need SVE EL. Save potential re-translations by forcing | ||
| 662 | + * the unneeded data to zero. | ||
| 663 | + */ | ||
| 664 | + if (fp_el != 0) { | ||
| 665 | + if (sve_el > fp_el) { | ||
| 666 | + sve_el = 0; | ||
| 667 | + } | ||
| 668 | + } else if (sve_el == 0) { | ||
| 669 | + DP_TBFLAG_A64(flags, VL, sve_vqm1_for_el(env, el)); | ||
| 670 | + } | ||
| 671 | + DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); | ||
| 672 | + } | ||
| 673 | + if (cpu_isar_feature(aa64_sme, env_archcpu(env))) { | ||
| 674 | + int sme_el = sme_exception_el(env, el); | ||
| 675 | + bool sm = FIELD_EX64(env->svcr, SVCR, SM); | ||
| 676 | + | ||
| 677 | + DP_TBFLAG_A64(flags, SMEEXC_EL, sme_el); | ||
| 678 | + if (sme_el == 0) { | ||
| 679 | + /* Similarly, do not compute SVL if SME is disabled. */ | ||
| 680 | + int svl = sve_vqm1_for_el_sm(env, el, true); | ||
| 681 | + DP_TBFLAG_A64(flags, SVL, svl); | ||
| 682 | + if (sm) { | ||
| 683 | + /* If SVE is disabled, we will not have set VL above. */ | ||
| 684 | + DP_TBFLAG_A64(flags, VL, svl); | ||
| 685 | + } | ||
| 686 | + } | ||
| 687 | + if (sm) { | ||
| 688 | + DP_TBFLAG_A64(flags, PSTATE_SM, 1); | ||
| 689 | + DP_TBFLAG_A64(flags, SME_TRAP_NONSTREAMING, !sme_fa64(env, el)); | ||
| 690 | + } | ||
| 691 | + DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); | ||
| 692 | + } | ||
| 693 | + | ||
| 694 | + sctlr = regime_sctlr(env, stage1); | ||
| 695 | + | ||
| 696 | + if (sctlr & SCTLR_A) { | ||
| 697 | + DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); | ||
| 698 | + } | ||
| 699 | + | ||
| 700 | + if (arm_cpu_data_is_big_endian_a64(el, sctlr)) { | ||
| 701 | + DP_TBFLAG_ANY(flags, BE_DATA, 1); | ||
| 702 | + } | ||
| 703 | + | ||
| 704 | + if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) { | ||
| 705 | + /* | ||
| 706 | + * In order to save space in flags, we record only whether | ||
| 707 | + * pauth is "inactive", meaning all insns are implemented as | ||
| 708 | + * a nop, or "active" when some action must be performed. | ||
| 709 | + * The decision of which action to take is left to a helper. | ||
| 710 | + */ | ||
| 711 | + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { | ||
| 712 | + DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1); | ||
| 713 | + } | ||
| 714 | + } | ||
| 715 | + | ||
| 716 | + if (cpu_isar_feature(aa64_bti, env_archcpu(env))) { | ||
| 717 | + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ | ||
| 718 | + if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { | ||
| 719 | + DP_TBFLAG_A64(flags, BT, 1); | ||
| 720 | + } | ||
| 721 | + } | ||
| 722 | + | ||
| 723 | + /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ | ||
| 724 | + if (!(env->pstate & PSTATE_UAO)) { | ||
| 725 | + switch (mmu_idx) { | ||
| 726 | + case ARMMMUIdx_E10_1: | ||
| 727 | + case ARMMMUIdx_E10_1_PAN: | ||
| 728 | + /* TODO: ARMv8.3-NV */ | ||
| 729 | + DP_TBFLAG_A64(flags, UNPRIV, 1); | ||
| 730 | + break; | ||
| 731 | + case ARMMMUIdx_E20_2: | ||
| 732 | + case ARMMMUIdx_E20_2_PAN: | ||
| 733 | + /* | ||
| 734 | + * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is | ||
| 735 | + * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. | ||
| 736 | + */ | ||
| 737 | + if (env->cp15.hcr_el2 & HCR_TGE) { | ||
| 738 | + DP_TBFLAG_A64(flags, UNPRIV, 1); | ||
| 739 | + } | ||
| 740 | + break; | ||
| 741 | + default: | ||
| 742 | + break; | ||
| 743 | + } | ||
| 744 | + } | ||
| 745 | + | ||
| 746 | + if (env->pstate & PSTATE_IL) { | ||
| 747 | + DP_TBFLAG_ANY(flags, PSTATE__IL, 1); | ||
| 748 | + } | ||
| 749 | + | ||
| 750 | + if (arm_fgt_active(env, el)) { | ||
| 751 | + DP_TBFLAG_ANY(flags, FGT_ACTIVE, 1); | ||
| 752 | + if (FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, ERET)) { | ||
| 753 | + DP_TBFLAG_A64(flags, FGT_ERET, 1); | ||
| 754 | + } | ||
| 755 | + if (fgt_svc(env, el)) { | ||
| 756 | + DP_TBFLAG_ANY(flags, FGT_SVC, 1); | ||
| 757 | + } | ||
| 758 | + } | ||
| 759 | + | ||
| 760 | + if (cpu_isar_feature(aa64_mte, env_archcpu(env))) { | ||
| 761 | + /* | ||
| 762 | + * Set MTE_ACTIVE if any access may be Checked, and leave clear | ||
| 763 | + * if all accesses must be Unchecked: | ||
| 764 | + * 1) If no TBI, then there are no tags in the address to check, | ||
| 765 | + * 2) If Tag Check Override, then all accesses are Unchecked, | ||
| 766 | + * 3) If Tag Check Fail == 0, then Checked access have no effect, | ||
| 767 | + * 4) If no Allocation Tag Access, then all accesses are Unchecked. | ||
| 768 | + */ | ||
| 769 | + if (allocation_tag_access_enabled(env, el, sctlr)) { | ||
| 770 | + DP_TBFLAG_A64(flags, ATA, 1); | ||
| 771 | + if (tbid | ||
| 772 | + && !(env->pstate & PSTATE_TCO) | ||
| 773 | + && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { | ||
| 774 | + DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); | ||
| 775 | + } | ||
| 776 | + } | ||
| 777 | + /* And again for unprivileged accesses, if required. */ | ||
| 778 | + if (EX_TBFLAG_A64(flags, UNPRIV) | ||
| 779 | + && tbid | ||
| 780 | + && !(env->pstate & PSTATE_TCO) | ||
| 781 | + && (sctlr & SCTLR_TCF0) | ||
| 782 | + && allocation_tag_access_enabled(env, 0, sctlr)) { | ||
| 783 | + DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); | ||
| 784 | + } | ||
| 785 | + /* Cache TCMA as well as TBI. */ | ||
| 786 | + DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); | ||
| 787 | + } | ||
| 788 | + | ||
| 789 | + return rebuild_hflags_common(env, fp_el, mmu_idx, flags); | ||
| 790 | +} | ||
| 791 | + | ||
| 792 | +static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) | ||
| 793 | +{ | ||
| 794 | + int el = arm_current_el(env); | ||
| 795 | + int fp_el = fp_exception_el(env, el); | ||
| 796 | + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 797 | + | ||
| 798 | + if (is_a64(env)) { | ||
| 799 | + return rebuild_hflags_a64(env, el, fp_el, mmu_idx); | ||
| 800 | + } else if (arm_feature(env, ARM_FEATURE_M)) { | ||
| 801 | + return rebuild_hflags_m32(env, fp_el, mmu_idx); | ||
| 802 | + } else { | ||
| 803 | + return rebuild_hflags_a32(env, fp_el, mmu_idx); | ||
| 804 | + } | ||
| 805 | +} | ||
| 806 | + | ||
| 807 | +void arm_rebuild_hflags(CPUARMState *env) | ||
| 808 | +{ | ||
| 809 | + env->hflags = rebuild_hflags_internal(env); | ||
| 810 | +} | ||
| 811 | + | ||
| 812 | +/* | ||
| 813 | + * If we have triggered a EL state change we can't rely on the | ||
| 814 | + * translator having passed it to us, we need to recompute. | ||
| 815 | + */ | ||
| 816 | +void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env) | ||
| 817 | +{ | ||
| 818 | + int el = arm_current_el(env); | ||
| 819 | + int fp_el = fp_exception_el(env, el); | ||
| 820 | + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 821 | + | ||
| 822 | + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); | ||
| 823 | +} | ||
| 824 | + | ||
| 825 | +void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el) | ||
| 826 | +{ | ||
| 827 | + int fp_el = fp_exception_el(env, el); | ||
| 828 | + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 829 | + | ||
| 830 | + env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx); | ||
| 831 | +} | ||
| 832 | + | ||
| 833 | +/* | ||
| 834 | + * If we have triggered a EL state change we can't rely on the | ||
| 835 | + * translator having passed it to us, we need to recompute. | ||
| 836 | + */ | ||
| 837 | +void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env) | ||
| 838 | +{ | ||
| 839 | + int el = arm_current_el(env); | ||
| 840 | + int fp_el = fp_exception_el(env, el); | ||
| 841 | + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 842 | + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | ||
| 843 | +} | ||
| 844 | + | ||
| 845 | +void HELPER(rebuild_hflags_a32)(CPUARMState *env, int el) | ||
| 846 | +{ | ||
| 847 | + int fp_el = fp_exception_el(env, el); | ||
| 848 | + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 849 | + | ||
| 850 | + env->hflags = rebuild_hflags_a32(env, fp_el, mmu_idx); | ||
| 851 | +} | ||
| 852 | + | ||
| 853 | +void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) | ||
| 854 | +{ | ||
| 855 | + int fp_el = fp_exception_el(env, el); | ||
| 856 | + ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); | ||
| 857 | + | ||
| 858 | + env->hflags = rebuild_hflags_a64(env, el, fp_el, mmu_idx); | ||
| 859 | +} | ||
| 860 | + | ||
| 861 | +void assert_hflags_rebuild_correctly(CPUARMState *env) | ||
| 862 | +{ | ||
| 863 | +#ifdef CONFIG_DEBUG_TCG | ||
| 864 | + CPUARMTBFlags c = env->hflags; | ||
| 865 | + CPUARMTBFlags r = rebuild_hflags_internal(env); | ||
| 866 | + | ||
| 867 | + if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) { | ||
| 868 | + fprintf(stderr, "TCG hflags mismatch " | ||
| 869 | + "(current:(0x%08x,0x" TARGET_FMT_lx ")" | ||
| 870 | + " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n", | ||
| 871 | + c.flags, c.flags2, r.flags, r.flags2); | ||
| 872 | + abort(); | ||
| 873 | + } | ||
| 874 | +#endif | ||
| 875 | +} | ||
| 876 | diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build | ||
| 877 | index XXXXXXX..XXXXXXX 100644 | ||
| 878 | --- a/target/arm/tcg/meson.build | ||
| 879 | +++ b/target/arm/tcg/meson.build | ||
| 880 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( | ||
| 881 | 'translate-neon.c', | ||
| 882 | 'translate-vfp.c', | ||
| 883 | 'crypto_helper.c', | ||
| 884 | + 'hflags.c', | ||
| 885 | 'iwmmxt_helper.c', | ||
| 886 | 'm_helper.c', | ||
| 887 | 'mve_helper.c', | ||
| 282 | -- | 888 | -- |
| 283 | 2.20.1 | 889 | 2.34.1 |
| 284 | 890 | ||
| 285 | 891 | diff view generated by jsdifflib |
| 1 | Convert the Neon 3-reg-same VADD and VSUB insns to decodetree. | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Note that we don't need the neon_3r_sizes[op] check here because all | 3 | This function is needed by common code (ptw.c), so move it along with |
| 4 | size values are OK for VADD and VSUB; we'll add this when we convert | 4 | the other regime_* functions in internal.h. When we enable the build |
| 5 | the first insn that has size restrictions. | 5 | without TCG, the tlb_helper.c file will not be present. |
| 6 | 6 | ||
| 7 | For this we need one of the GVecGen*Fn typedefs currently in | 7 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
| 8 | translate-a64.h; move them all to translate.h as a block so they | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 9 | are visible to the 32-bit decoder. | 9 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | --- | ||
| 12 | target/arm/internals.h | 21 ++++++++++++++++++--- | ||
| 13 | target/arm/tcg/tlb_helper.c | 18 ------------------ | ||
| 14 | 2 files changed, 18 insertions(+), 21 deletions(-) | ||
| 10 | 15 | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
| 12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 13 | Message-id: 20200430181003.21682-15-peter.maydell@linaro.org | ||
| 14 | --- | ||
| 15 | target/arm/translate-a64.h | 9 -------- | ||
| 16 | target/arm/translate.h | 9 ++++++++ | ||
| 17 | target/arm/neon-dp.decode | 17 +++++++++++++++ | ||
| 18 | target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++ | ||
| 19 | target/arm/translate.c | 14 ++++-------- | ||
| 20 | 5 files changed, 68 insertions(+), 19 deletions(-) | ||
| 21 | |||
| 22 | diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h | ||
| 23 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 24 | --- a/target/arm/translate-a64.h | 18 | --- a/target/arm/internals.h |
| 25 | +++ b/target/arm/translate-a64.h | 19 | +++ b/target/arm/internals.h |
| 26 | @@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s) | 20 | @@ -XXX,XX +XXX,XX @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); |
| 27 | 21 | /* Return the MMU index for a v7M CPU in the specified security state */ | |
| 28 | bool disas_sve(DisasContext *, uint32_t); | 22 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); |
| 29 | 23 | ||
| 30 | -/* Note that the gvec expanders operate on offsets + sizes. */ | 24 | -/* Return true if the translation regime is using LPAE format page tables */ |
| 31 | -typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); | 25 | -bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); |
| 32 | -typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, | ||
| 33 | - uint32_t, uint32_t); | ||
| 34 | -typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, | ||
| 35 | - uint32_t, uint32_t, uint32_t); | ||
| 36 | -typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t, | ||
| 37 | - uint32_t, uint32_t, uint32_t); | ||
| 38 | - | 26 | - |
| 39 | #endif /* TARGET_ARM_TRANSLATE_A64_H */ | 27 | /* |
| 40 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 28 | * Return true if the stage 1 translation regime is using LPAE |
| 41 | index XXXXXXX..XXXXXXX 100644 | 29 | * format page tables |
| 42 | --- a/target/arm/translate.h | 30 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) |
| 43 | +++ b/target/arm/translate.h | 31 | return env->cp15.tcr_el[regime_el(env, mmu_idx)]; |
| 44 | @@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); | ||
| 45 | #define dc_isar_feature(name, ctx) \ | ||
| 46 | ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); }) | ||
| 47 | |||
| 48 | +/* Note that the gvec expanders operate on offsets + sizes. */ | ||
| 49 | +typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); | ||
| 50 | +typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, | ||
| 51 | + uint32_t, uint32_t); | ||
| 52 | +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, | ||
| 53 | + uint32_t, uint32_t, uint32_t); | ||
| 54 | +typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t, | ||
| 55 | + uint32_t, uint32_t, uint32_t); | ||
| 56 | + | ||
| 57 | #endif /* TARGET_ARM_TRANSLATE_H */ | ||
| 58 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
| 59 | index XXXXXXX..XXXXXXX 100644 | ||
| 60 | --- a/target/arm/neon-dp.decode | ||
| 61 | +++ b/target/arm/neon-dp.decode | ||
| 62 | @@ -XXX,XX +XXX,XX @@ | ||
| 63 | # | ||
| 64 | # This file is processed by scripts/decodetree.py | ||
| 65 | # | ||
| 66 | +# VFP/Neon register fields; same as vfp.decode | ||
| 67 | +%vm_dp 5:1 0:4 | ||
| 68 | +%vn_dp 7:1 16:4 | ||
| 69 | +%vd_dp 22:1 12:4 | ||
| 70 | |||
| 71 | # Encodings for Neon data processing instructions where the T32 encoding | ||
| 72 | # is a simple transformation of the A32 encoding. | ||
| 73 | @@ -XXX,XX +XXX,XX @@ | ||
| 74 | # 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq | ||
| 75 | # This file works on the A32 encoding only; calling code for T32 has to | ||
| 76 | # transform the insn into the A32 version first. | ||
| 77 | + | ||
| 78 | +###################################################################### | ||
| 79 | +# 3-reg-same grouping: | ||
| 80 | +# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4 | ||
| 81 | +###################################################################### | ||
| 82 | + | ||
| 83 | +&3same vm vn vd q size | ||
| 84 | + | ||
| 85 | +@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \ | ||
| 86 | + &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
| 87 | + | ||
| 88 | +VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same | ||
| 89 | +VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same | ||
| 90 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 91 | index XXXXXXX..XXXXXXX 100644 | ||
| 92 | --- a/target/arm/translate-neon.inc.c | ||
| 93 | +++ b/target/arm/translate-neon.inc.c | ||
| 94 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) | ||
| 95 | |||
| 96 | return true; | ||
| 97 | } | 32 | } |
| 98 | + | 33 | |
| 99 | +static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) | 34 | +/* Return true if the translation regime is using LPAE format page tables */ |
| 35 | +static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
| 100 | +{ | 36 | +{ |
| 101 | + int vec_size = a->q ? 16 : 8; | 37 | + int el = regime_el(env, mmu_idx); |
| 102 | + int rd_ofs = neon_reg_offset(a->vd, 0); | 38 | + if (el == 2 || arm_el_is_aa64(env, el)) { |
| 103 | + int rn_ofs = neon_reg_offset(a->vn, 0); | ||
| 104 | + int rm_ofs = neon_reg_offset(a->vm, 0); | ||
| 105 | + | ||
| 106 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
| 107 | + return false; | ||
| 108 | + } | ||
| 109 | + | ||
| 110 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
| 111 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
| 112 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
| 113 | + return false; | ||
| 114 | + } | ||
| 115 | + | ||
| 116 | + if ((a->vn | a->vm | a->vd) & a->q) { | ||
| 117 | + return false; | ||
| 118 | + } | ||
| 119 | + | ||
| 120 | + if (!vfp_access_check(s)) { | ||
| 121 | + return true; | 39 | + return true; |
| 122 | + } | 40 | + } |
| 123 | + | 41 | + if (arm_feature(env, ARM_FEATURE_PMSA) && |
| 124 | + fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); | 42 | + arm_feature(env, ARM_FEATURE_V8)) { |
| 125 | + return true; | 43 | + return true; |
| 44 | + } | ||
| 45 | + if (arm_feature(env, ARM_FEATURE_LPAE) | ||
| 46 | + && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { | ||
| 47 | + return true; | ||
| 48 | + } | ||
| 49 | + return false; | ||
| 126 | +} | 50 | +} |
| 127 | + | 51 | + |
| 128 | +#define DO_3SAME(INSN, FUNC) \ | 52 | /** |
| 129 | + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ | 53 | * arm_num_brps: Return number of implemented breakpoints. |
| 130 | + { \ | 54 | * Note that the ID register BRPS field is "number of bps - 1", |
| 131 | + return do_3same(s, a, FUNC); \ | 55 | diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c |
| 132 | + } | ||
| 133 | + | ||
| 134 | +DO_3SAME(VADD, tcg_gen_gvec_add) | ||
| 135 | +DO_3SAME(VSUB, tcg_gen_gvec_sub) | ||
| 136 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 137 | index XXXXXXX..XXXXXXX 100644 | 56 | index XXXXXXX..XXXXXXX 100644 |
| 138 | --- a/target/arm/translate.c | 57 | --- a/target/arm/tcg/tlb_helper.c |
| 139 | +++ b/target/arm/translate.c | 58 | +++ b/target/arm/tcg/tlb_helper.c |
| 140 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 59 | @@ -XXX,XX +XXX,XX @@ |
| 141 | } | 60 | #include "exec/helper-proto.h" |
| 142 | return 0; | 61 | |
| 143 | 62 | ||
| 144 | - case NEON_3R_VADD_VSUB: | 63 | -/* Return true if the translation regime is using LPAE format page tables */ |
| 145 | - if (u) { | 64 | -bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) |
| 146 | - tcg_gen_gvec_sub(size, rd_ofs, rn_ofs, rm_ofs, | 65 | -{ |
| 147 | - vec_size, vec_size); | 66 | - int el = regime_el(env, mmu_idx); |
| 148 | - } else { | 67 | - if (el == 2 || arm_el_is_aa64(env, el)) { |
| 149 | - tcg_gen_gvec_add(size, rd_ofs, rn_ofs, rm_ofs, | 68 | - return true; |
| 150 | - vec_size, vec_size); | 69 | - } |
| 151 | - } | 70 | - if (arm_feature(env, ARM_FEATURE_PMSA) && |
| 152 | - return 0; | 71 | - arm_feature(env, ARM_FEATURE_V8)) { |
| 72 | - return true; | ||
| 73 | - } | ||
| 74 | - if (arm_feature(env, ARM_FEATURE_LPAE) | ||
| 75 | - && (regime_tcr(env, mmu_idx) & TTBCR_EAE)) { | ||
| 76 | - return true; | ||
| 77 | - } | ||
| 78 | - return false; | ||
| 79 | -} | ||
| 153 | - | 80 | - |
| 154 | case NEON_3R_VQADD: | 81 | /* |
| 155 | tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), | 82 | * Returns true if the stage 1 translation regime is using LPAE format page |
| 156 | rn_ofs, rm_ofs, vec_size, vec_size, | 83 | * tables. Used when raising alignment exceptions, whose FSR changes depending |
| 157 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 158 | tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size, | ||
| 159 | u ? &ushl_op[size] : &sshl_op[size]); | ||
| 160 | return 0; | ||
| 161 | + | ||
| 162 | + case NEON_3R_VADD_VSUB: | ||
| 163 | + /* Already handled by decodetree */ | ||
| 164 | + return 1; | ||
| 165 | } | ||
| 166 | |||
| 167 | if (size == 3) { | ||
| 168 | -- | 84 | -- |
| 169 | 2.20.1 | 85 | 2.34.1 |
| 170 | 86 | ||
| 171 | 87 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Fix typo xlnx-ve -> xlnx-versal. | 3 | When TCG is disabled this part of the code should not be reachable, so |
| 4 | wrap it with an ifdef for now. | ||
| 4 | 5 | ||
| 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 6 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
| 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 8 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
| 9 | Message-id: 20200427181649.26851-4-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 10 | --- |
| 12 | hw/arm/xlnx-versal-virt.c | 2 +- | 11 | target/arm/ptw.c | 4 ++++ |
| 13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 4 insertions(+) |
| 14 | 13 | ||
| 15 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | 14 | diff --git a/target/arm/ptw.c b/target/arm/ptw.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/hw/arm/xlnx-versal-virt.c | 16 | --- a/target/arm/ptw.c |
| 18 | +++ b/hw/arm/xlnx-versal-virt.c | 17 | +++ b/target/arm/ptw.c |
| 19 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) | 18 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, |
| 20 | psci_conduit = QEMU_PSCI_CONDUIT_SMC; | 19 | ptw->out_host = NULL; |
| 20 | ptw->out_rw = false; | ||
| 21 | } else { | ||
| 22 | +#ifdef CONFIG_TCG | ||
| 23 | CPUTLBEntryFull *full; | ||
| 24 | int flags; | ||
| 25 | |||
| 26 | @@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, | ||
| 27 | ptw->out_rw = full->prot & PAGE_WRITE; | ||
| 28 | pte_attrs = full->pte_attrs; | ||
| 29 | pte_secure = full->attrs.secure; | ||
| 30 | +#else | ||
| 31 | + g_assert_not_reached(); | ||
| 32 | +#endif | ||
| 21 | } | 33 | } |
| 22 | 34 | ||
| 23 | - sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc, | 35 | if (regime_is_stage2(s2_mmu_idx)) { |
| 24 | + sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc, | ||
| 25 | sizeof(s->soc), TYPE_XLNX_VERSAL); | ||
| 26 | object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram), | ||
| 27 | "ddr", &error_abort); | ||
| 28 | -- | 36 | -- |
| 29 | 2.20.1 | 37 | 2.34.1 |
| 30 | 38 | ||
| 31 | 39 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Embed the ADMAs into the SoC type. | 3 | This struct has no dependencies on TCG code and it is being used in |
| 4 | target/arm/ptw.c to simplify the passing around of page table walk | ||
| 5 | results. Those routines can be reached by KVM code via the gdbstub | ||
| 6 | breakpoint code, so take the structure out of CONFIG_TCG to make it | ||
| 7 | visible when building with --disable-tcg. | ||
| 4 | 8 | ||
| 5 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 12 | Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 9 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
| 10 | Message-id: 20200427181649.26851-7-edgar.iglesias@gmail.com | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | --- | 14 | --- |
| 13 | include/hw/arm/xlnx-versal.h | 3 ++- | 15 | include/exec/cpu-defs.h | 6 ++++++ |
| 14 | hw/arm/xlnx-versal.c | 14 +++++++------- | 16 | 1 file changed, 6 insertions(+) |
| 15 | 2 files changed, 9 insertions(+), 8 deletions(-) | ||
| 16 | 17 | ||
| 17 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 18 | diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h |
| 18 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/include/hw/arm/xlnx-versal.h | 20 | --- a/include/exec/cpu-defs.h |
| 20 | +++ b/include/hw/arm/xlnx-versal.h | 21 | +++ b/include/exec/cpu-defs.h |
| 21 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntry { |
| 22 | #include "hw/arm/boot.h" | 23 | |
| 23 | #include "hw/intc/arm_gicv3.h" | 24 | QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); |
| 24 | #include "hw/char/pl011.h" | 25 | |
| 25 | +#include "hw/dma/xlnx-zdma.h" | 26 | + |
| 26 | #include "hw/net/cadence_gem.h" | 27 | +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ |
| 27 | 28 | + | |
| 28 | #define TYPE_XLNX_VERSAL "xlnx-versal" | 29 | +#if !defined(CONFIG_USER_ONLY) |
| 29 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | 30 | /* |
| 30 | struct { | 31 | * The full TLB entry, which is not accessed by generated TCG code, |
| 31 | PL011State uart[XLNX_VERSAL_NR_UARTS]; | 32 | * so the layout is not as critical as that of CPUTLBEntry. This is |
| 32 | CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; | 33 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull { |
| 33 | - SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS]; | 34 | TARGET_PAGE_ENTRY_EXTRA |
| 34 | + XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; | 35 | #endif |
| 35 | } iou; | 36 | } CPUTLBEntryFull; |
| 36 | } lpd; | 37 | +#endif /* !CONFIG_USER_ONLY */ |
| 37 | 38 | ||
| 38 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | 39 | +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) |
| 39 | index XXXXXXX..XXXXXXX 100644 | 40 | /* |
| 40 | --- a/hw/arm/xlnx-versal.c | 41 | * Data elements that are per MMU mode, minus the bits accessed by |
| 41 | +++ b/hw/arm/xlnx-versal.c | 42 | * the TCG fast path. |
| 42 | @@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic) | ||
| 43 | DeviceState *dev; | ||
| 44 | MemoryRegion *mr; | ||
| 45 | |||
| 46 | - dev = qdev_create(NULL, "xlnx.zdma"); | ||
| 47 | - s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev); | ||
| 48 | - object_property_set_int(OBJECT(s->lpd.iou.adma[i]), 128, "bus-width", | ||
| 49 | - &error_abort); | ||
| 50 | - object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal); | ||
| 51 | + sysbus_init_child_obj(OBJECT(s), name, | ||
| 52 | + &s->lpd.iou.adma[i], sizeof(s->lpd.iou.adma[i]), | ||
| 53 | + TYPE_XLNX_ZDMA); | ||
| 54 | + dev = DEVICE(&s->lpd.iou.adma[i]); | ||
| 55 | + object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort); | ||
| 56 | qdev_init_nofail(dev); | ||
| 57 | |||
| 58 | - mr = sysbus_mmio_get_region(s->lpd.iou.adma[i], 0); | ||
| 59 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | ||
| 60 | memory_region_add_subregion(&s->mr_ps, | ||
| 61 | MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr); | ||
| 62 | |||
| 63 | - sysbus_connect_irq(s->lpd.iou.adma[i], 0, pic[VERSAL_ADMA_IRQ_0 + i]); | ||
| 64 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]); | ||
| 65 | g_free(name); | ||
| 66 | } | ||
| 67 | } | ||
| 68 | -- | 43 | -- |
| 69 | 2.20.1 | 44 | 2.34.1 |
| 70 | 45 | ||
| 71 | 46 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Fabiano Rosas <farosas@suse.de> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Embed the GEMs into the SoC type. | 3 | This test currently fails when run on a host for which the QEMU target |
| 4 | has no default machine set: | ||
| 4 | 5 | ||
| 5 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | 6 | ERROR| Output: qemu-system-aarch64: No machine specified, and there is |
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 7 | no default |
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 8 | |
| 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 9 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 10 | Signed-off-by: Fabiano Rosas <farosas@suse.de> |
| 10 | Message-id: 20200427181649.26851-6-edgar.iglesias@gmail.com | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | --- | 12 | --- |
| 13 | include/hw/arm/xlnx-versal.h | 3 ++- | 13 | tests/avocado/version.py | 1 + |
| 14 | hw/arm/xlnx-versal.c | 15 ++++++++------- | 14 | 1 file changed, 1 insertion(+) |
| 15 | 2 files changed, 10 insertions(+), 8 deletions(-) | ||
| 16 | 15 | ||
| 17 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 16 | diff --git a/tests/avocado/version.py b/tests/avocado/version.py |
| 18 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/include/hw/arm/xlnx-versal.h | 18 | --- a/tests/avocado/version.py |
| 20 | +++ b/include/hw/arm/xlnx-versal.h | 19 | +++ b/tests/avocado/version.py |
| 21 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
| 22 | #include "hw/arm/boot.h" | 21 | class Version(QemuSystemTest): |
| 23 | #include "hw/intc/arm_gicv3.h" | 22 | """ |
| 24 | #include "hw/char/pl011.h" | 23 | :avocado: tags=quick |
| 25 | +#include "hw/net/cadence_gem.h" | 24 | + :avocado: tags=machine:none |
| 26 | 25 | """ | |
| 27 | #define TYPE_XLNX_VERSAL "xlnx-versal" | 26 | def test_qmp_human_info_version(self): |
| 28 | #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) | 27 | self.vm.add_args('-nodefaults') |
| 29 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | ||
| 30 | |||
| 31 | struct { | ||
| 32 | PL011State uart[XLNX_VERSAL_NR_UARTS]; | ||
| 33 | - SysBusDevice *gem[XLNX_VERSAL_NR_GEMS]; | ||
| 34 | + CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; | ||
| 35 | SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS]; | ||
| 36 | } iou; | ||
| 37 | } lpd; | ||
| 38 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | ||
| 40 | --- a/hw/arm/xlnx-versal.c | ||
| 41 | +++ b/hw/arm/xlnx-versal.c | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic) | ||
| 43 | DeviceState *dev; | ||
| 44 | MemoryRegion *mr; | ||
| 45 | |||
| 46 | - dev = qdev_create(NULL, "cadence_gem"); | ||
| 47 | - s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev); | ||
| 48 | - object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal); | ||
| 49 | + sysbus_init_child_obj(OBJECT(s), name, | ||
| 50 | + &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]), | ||
| 51 | + TYPE_CADENCE_GEM); | ||
| 52 | + dev = DEVICE(&s->lpd.iou.gem[i]); | ||
| 53 | if (nd->used) { | ||
| 54 | qemu_check_nic_model(nd, "cadence_gem"); | ||
| 55 | qdev_set_nic_properties(dev, nd); | ||
| 56 | } | ||
| 57 | - object_property_set_int(OBJECT(s->lpd.iou.gem[i]), | ||
| 58 | + object_property_set_int(OBJECT(dev), | ||
| 59 | 2, "num-priority-queues", | ||
| 60 | &error_abort); | ||
| 61 | - object_property_set_link(OBJECT(s->lpd.iou.gem[i]), | ||
| 62 | + object_property_set_link(OBJECT(dev), | ||
| 63 | OBJECT(&s->mr_ps), "dma", | ||
| 64 | &error_abort); | ||
| 65 | qdev_init_nofail(dev); | ||
| 66 | |||
| 67 | - mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0); | ||
| 68 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | ||
| 69 | memory_region_add_subregion(&s->mr_ps, addrs[i], mr); | ||
| 70 | |||
| 71 | - sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]); | ||
| 72 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); | ||
| 73 | g_free(name); | ||
| 74 | } | ||
| 75 | } | ||
| 76 | -- | 28 | -- |
| 77 | 2.20.1 | 29 | 2.34.1 |
| 78 | 30 | ||
| 79 | 31 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add support for the RTC. | 3 | Since &I2C_SLAVE(dev)->qdev == dev, no need to go back and |
| 4 | forth with QOM type casting. Directly use 'dev'. | ||
| 4 | 5 | ||
| 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 7 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 8 | Message-id: 20230220115114.25237-2-philmd@linaro.org |
| 8 | Message-id: 20200427181649.26851-12-edgar.iglesias@gmail.com | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | --- | 10 | --- |
| 11 | hw/arm/xlnx-versal-virt.c | 22 ++++++++++++++++++++++ | 11 | hw/gpio/max7310.c | 5 ++--- |
| 12 | 1 file changed, 22 insertions(+) | 12 | 1 file changed, 2 insertions(+), 3 deletions(-) |
| 13 | 13 | ||
| 14 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | 14 | diff --git a/hw/gpio/max7310.c b/hw/gpio/max7310.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/hw/arm/xlnx-versal-virt.c | 16 | --- a/hw/gpio/max7310.c |
| 17 | +++ b/hw/arm/xlnx-versal-virt.c | 17 | +++ b/hw/gpio/max7310.c |
| 18 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_sd_nodes(VersalVirt *s) | 18 | @@ -XXX,XX +XXX,XX @@ static void max7310_gpio_set(void *opaque, int line, int level) |
| 19 | } | 19 | * but also accepts sequences that are not SMBus so return an I2C device. */ |
| 20 | static void max7310_realize(DeviceState *dev, Error **errp) | ||
| 21 | { | ||
| 22 | - I2CSlave *i2c = I2C_SLAVE(dev); | ||
| 23 | MAX7310State *s = MAX7310(dev); | ||
| 24 | |||
| 25 | - qdev_init_gpio_in(&i2c->qdev, max7310_gpio_set, 8); | ||
| 26 | - qdev_init_gpio_out(&i2c->qdev, s->handler, 8); | ||
| 27 | + qdev_init_gpio_in(dev, max7310_gpio_set, ARRAY_SIZE(s->handler)); | ||
| 28 | + qdev_init_gpio_out(dev, s->handler, ARRAY_SIZE(s->handler)); | ||
| 20 | } | 29 | } |
| 21 | 30 | ||
| 22 | +static void fdt_add_rtc_node(VersalVirt *s) | 31 | static void max7310_class_init(ObjectClass *klass, void *data) |
| 23 | +{ | ||
| 24 | + const char compat[] = "xlnx,zynqmp-rtc"; | ||
| 25 | + const char interrupt_names[] = "alarm\0sec"; | ||
| 26 | + char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC); | ||
| 27 | + | ||
| 28 | + qemu_fdt_add_subnode(s->fdt, name); | ||
| 29 | + | ||
| 30 | + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", | ||
| 31 | + GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ, | ||
| 32 | + GIC_FDT_IRQ_FLAGS_LEVEL_HI, | ||
| 33 | + GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ, | ||
| 34 | + GIC_FDT_IRQ_FLAGS_LEVEL_HI); | ||
| 35 | + qemu_fdt_setprop(s->fdt, name, "interrupt-names", | ||
| 36 | + interrupt_names, sizeof(interrupt_names)); | ||
| 37 | + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", | ||
| 38 | + 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE); | ||
| 39 | + qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat)); | ||
| 40 | + g_free(name); | ||
| 41 | +} | ||
| 42 | + | ||
| 43 | static void fdt_nop_memory_nodes(void *fdt, Error **errp) | ||
| 44 | { | ||
| 45 | Error *err = NULL; | ||
| 46 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) | ||
| 47 | fdt_add_timer_nodes(s); | ||
| 48 | fdt_add_zdma_nodes(s); | ||
| 49 | fdt_add_sd_nodes(s); | ||
| 50 | + fdt_add_rtc_node(s); | ||
| 51 | fdt_add_cpu_nodes(s, psci_conduit); | ||
| 52 | fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); | ||
| 53 | fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); | ||
| 54 | -- | 32 | -- |
| 55 | 2.20.1 | 33 | 2.34.1 |
| 56 | 34 | ||
| 57 | 35 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Add support for SD. | 3 | pl011_create() is only used in DeviceRealize handlers, |
| 4 | not a hot-path. Inlining is not justified. | ||
| 4 | 5 | ||
| 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | 9 | Message-id: 20230220115114.25237-3-philmd@linaro.org |
| 9 | Message-id: 20200427181649.26851-9-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 11 | --- |
| 12 | include/hw/arm/xlnx-versal.h | 12 ++++++++++++ | 12 | include/hw/char/pl011.h | 19 +------------------ |
| 13 | hw/arm/xlnx-versal.c | 31 +++++++++++++++++++++++++++++++ | 13 | hw/char/pl011.c | 17 +++++++++++++++++ |
| 14 | 2 files changed, 43 insertions(+) | 14 | 2 files changed, 18 insertions(+), 18 deletions(-) |
| 15 | 15 | ||
| 16 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 16 | diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h |
| 17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/include/hw/arm/xlnx-versal.h | 18 | --- a/include/hw/char/pl011.h |
| 19 | +++ b/include/hw/arm/xlnx-versal.h | 19 | +++ b/include/hw/char/pl011.h |
| 20 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
| 21 | 21 | #ifndef HW_PL011_H | |
| 22 | #define HW_PL011_H | ||
| 23 | |||
| 24 | -#include "hw/qdev-properties.h" | ||
| 22 | #include "hw/sysbus.h" | 25 | #include "hw/sysbus.h" |
| 23 | #include "hw/arm/boot.h" | 26 | #include "chardev/char-fe.h" |
| 24 | +#include "hw/sd/sdhci.h" | 27 | -#include "qapi/error.h" |
| 25 | #include "hw/intc/arm_gicv3.h" | 28 | #include "qom/object.h" |
| 29 | |||
| 30 | #define TYPE_PL011 "pl011" | ||
| 31 | @@ -XXX,XX +XXX,XX @@ struct PL011State { | ||
| 32 | const unsigned char *id; | ||
| 33 | }; | ||
| 34 | |||
| 35 | -static inline DeviceState *pl011_create(hwaddr addr, | ||
| 36 | - qemu_irq irq, | ||
| 37 | - Chardev *chr) | ||
| 38 | -{ | ||
| 39 | - DeviceState *dev; | ||
| 40 | - SysBusDevice *s; | ||
| 41 | - | ||
| 42 | - dev = qdev_new("pl011"); | ||
| 43 | - s = SYS_BUS_DEVICE(dev); | ||
| 44 | - qdev_prop_set_chr(dev, "chardev", chr); | ||
| 45 | - sysbus_realize_and_unref(s, &error_fatal); | ||
| 46 | - sysbus_mmio_map(s, 0, addr); | ||
| 47 | - sysbus_connect_irq(s, 0, irq); | ||
| 48 | - | ||
| 49 | - return dev; | ||
| 50 | -} | ||
| 51 | +DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr); | ||
| 52 | |||
| 53 | static inline DeviceState *pl011_luminary_create(hwaddr addr, | ||
| 54 | qemu_irq irq, | ||
| 55 | diff --git a/hw/char/pl011.c b/hw/char/pl011.c | ||
| 56 | index XXXXXXX..XXXXXXX 100644 | ||
| 57 | --- a/hw/char/pl011.c | ||
| 58 | +++ b/hw/char/pl011.c | ||
| 59 | @@ -XXX,XX +XXX,XX @@ | ||
| 60 | */ | ||
| 61 | |||
| 62 | #include "qemu/osdep.h" | ||
| 63 | +#include "qapi/error.h" | ||
| 26 | #include "hw/char/pl011.h" | 64 | #include "hw/char/pl011.h" |
| 27 | #include "hw/dma/xlnx-zdma.h" | 65 | #include "hw/irq.h" |
| 66 | #include "hw/sysbus.h" | ||
| 67 | #include "hw/qdev-clock.h" | ||
| 68 | +#include "hw/qdev-properties.h" | ||
| 69 | #include "hw/qdev-properties-system.h" | ||
| 70 | #include "migration/vmstate.h" | ||
| 71 | #include "chardev/char-fe.h" | ||
| 28 | @@ -XXX,XX +XXX,XX @@ | 72 | @@ -XXX,XX +XXX,XX @@ |
| 29 | #define XLNX_VERSAL_NR_UARTS 2 | 73 | #include "qemu/module.h" |
| 30 | #define XLNX_VERSAL_NR_GEMS 2 | 74 | #include "trace.h" |
| 31 | #define XLNX_VERSAL_NR_ADMAS 8 | 75 | |
| 32 | +#define XLNX_VERSAL_NR_SDS 2 | 76 | +DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) |
| 33 | #define XLNX_VERSAL_NR_IRQS 192 | 77 | +{ |
| 34 | 78 | + DeviceState *dev; | |
| 35 | typedef struct Versal { | 79 | + SysBusDevice *s; |
| 36 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | ||
| 37 | } iou; | ||
| 38 | } lpd; | ||
| 39 | |||
| 40 | + /* The Platform Management Controller subsystem. */ | ||
| 41 | + struct { | ||
| 42 | + struct { | ||
| 43 | + SDHCIState sd[XLNX_VERSAL_NR_SDS]; | ||
| 44 | + } iou; | ||
| 45 | + } pmc; | ||
| 46 | + | 80 | + |
| 47 | struct { | 81 | + dev = qdev_new("pl011"); |
| 48 | MemoryRegion *mr_ddr; | 82 | + s = SYS_BUS_DEVICE(dev); |
| 49 | uint32_t psci_conduit; | 83 | + qdev_prop_set_chr(dev, "chardev", chr); |
| 50 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | 84 | + sysbus_realize_and_unref(s, &error_fatal); |
| 51 | #define VERSAL_GEM1_IRQ_0 58 | 85 | + sysbus_mmio_map(s, 0, addr); |
| 52 | #define VERSAL_GEM1_WAKE_IRQ_0 59 | 86 | + sysbus_connect_irq(s, 0, irq); |
| 53 | #define VERSAL_ADMA_IRQ_0 60 | ||
| 54 | +#define VERSAL_SD0_IRQ_0 126 | ||
| 55 | |||
| 56 | /* Architecturally reserved IRQs suitable for virtualization. */ | ||
| 57 | #define VERSAL_RSVD_IRQ_FIRST 111 | ||
| 58 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | ||
| 59 | #define MM_FPD_CRF 0xfd1a0000U | ||
| 60 | #define MM_FPD_CRF_SIZE 0x140000 | ||
| 61 | |||
| 62 | +#define MM_PMC_SD0 0xf1040000U | ||
| 63 | +#define MM_PMC_SD0_SIZE 0x10000 | ||
| 64 | #define MM_PMC_CRP 0xf1260000U | ||
| 65 | #define MM_PMC_CRP_SIZE 0x10000 | ||
| 66 | #endif | ||
| 67 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
| 68 | index XXXXXXX..XXXXXXX 100644 | ||
| 69 | --- a/hw/arm/xlnx-versal.c | ||
| 70 | +++ b/hw/arm/xlnx-versal.c | ||
| 71 | @@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic) | ||
| 72 | } | ||
| 73 | } | ||
| 74 | |||
| 75 | +#define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */ | ||
| 76 | +static void versal_create_sds(Versal *s, qemu_irq *pic) | ||
| 77 | +{ | ||
| 78 | + int i; | ||
| 79 | + | 87 | + |
| 80 | + for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) { | 88 | + return dev; |
| 81 | + DeviceState *dev; | ||
| 82 | + MemoryRegion *mr; | ||
| 83 | + | ||
| 84 | + sysbus_init_child_obj(OBJECT(s), "sd[*]", | ||
| 85 | + &s->pmc.iou.sd[i], sizeof(s->pmc.iou.sd[i]), | ||
| 86 | + TYPE_SYSBUS_SDHCI); | ||
| 87 | + dev = DEVICE(&s->pmc.iou.sd[i]); | ||
| 88 | + | ||
| 89 | + object_property_set_uint(OBJECT(dev), | ||
| 90 | + 3, "sd-spec-version", &error_fatal); | ||
| 91 | + object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg", | ||
| 92 | + &error_fatal); | ||
| 93 | + object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal); | ||
| 94 | + qdev_init_nofail(dev); | ||
| 95 | + | ||
| 96 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | ||
| 97 | + memory_region_add_subregion(&s->mr_ps, | ||
| 98 | + MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr); | ||
| 99 | + | ||
| 100 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, | ||
| 101 | + pic[VERSAL_SD0_IRQ_0 + i * 2]); | ||
| 102 | + } | ||
| 103 | +} | 89 | +} |
| 104 | + | 90 | + |
| 105 | /* This takes the board allocated linear DDR memory and creates aliases | 91 | #define PL011_INT_TX 0x20 |
| 106 | * for each split DDR range/aperture on the Versal address map. | 92 | #define PL011_INT_RX 0x10 |
| 107 | */ | ||
| 108 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | ||
| 109 | versal_create_uarts(s, pic); | ||
| 110 | versal_create_gems(s, pic); | ||
| 111 | versal_create_admas(s, pic); | ||
| 112 | + versal_create_sds(s, pic); | ||
| 113 | versal_map_ddr(s); | ||
| 114 | versal_unimp(s); | ||
| 115 | 93 | ||
| 116 | -- | 94 | -- |
| 117 | 2.20.1 | 95 | 2.34.1 |
| 118 | 96 | ||
| 119 | 97 | diff view generated by jsdifflib |
| 1 | Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | to decodetree. These are the last ones in the group so we can remove | ||
| 3 | all the legacy decode for the group. | ||
| 4 | 2 | ||
| 5 | Note that in disas_thumb2_insn() the parts of this encoding space | 3 | pl011_luminary_create() is only used for the Stellaris board, |
| 6 | where the decodetree decoder returns false will correctly be directed | 4 | open-code it. |
| 7 | to illegal_op by the "(insn & (1 << 28))" check so they won't fall | ||
| 8 | into disas_coproc_insn() by mistake. | ||
| 9 | 5 | ||
| 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 7 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20230220115114.25237-4-philmd@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Message-id: 20200430181003.21682-11-peter.maydell@linaro.org | ||
| 13 | --- | 11 | --- |
| 14 | target/arm/neon-shared.decode | 7 +++ | 12 | include/hw/char/pl011.h | 17 ----------------- |
| 15 | target/arm/translate-neon.inc.c | 32 ++++++++++ | 13 | hw/arm/stellaris.c | 11 ++++++++--- |
| 16 | target/arm/translate.c | 107 +------------------------------- | 14 | 2 files changed, 8 insertions(+), 20 deletions(-) |
| 17 | 3 files changed, 40 insertions(+), 106 deletions(-) | ||
| 18 | 15 | ||
| 19 | diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode | 16 | diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h |
| 20 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 21 | --- a/target/arm/neon-shared.decode | 18 | --- a/include/hw/char/pl011.h |
| 22 | +++ b/target/arm/neon-shared.decode | 19 | +++ b/include/hw/char/pl011.h |
| 23 | @@ -XXX,XX +XXX,XX @@ VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \ | 20 | @@ -XXX,XX +XXX,XX @@ struct PL011State { |
| 24 | 21 | ||
| 25 | VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \ | 22 | DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr); |
| 26 | vm=%vm_dp vn=%vn_dp vd=%vd_dp | 23 | |
| 27 | + | 24 | -static inline DeviceState *pl011_luminary_create(hwaddr addr, |
| 28 | +%vfml_scalar_q0_rm 0:3 5:1 | 25 | - qemu_irq irq, |
| 29 | +%vfml_scalar_q1_index 5:1 3:1 | 26 | - Chardev *chr) |
| 30 | +VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1 index:1 ... \ | 27 | -{ |
| 31 | + rm=%vfml_scalar_q0_rm vn=%vn_sp vd=%vd_dp q=0 | 28 | - DeviceState *dev; |
| 32 | +VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \ | 29 | - SysBusDevice *s; |
| 33 | + index=%vfml_scalar_q1_index vn=%vn_dp vd=%vd_dp q=1 | ||
| 34 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 35 | index XXXXXXX..XXXXXXX 100644 | ||
| 36 | --- a/target/arm/translate-neon.inc.c | ||
| 37 | +++ b/target/arm/translate-neon.inc.c | ||
| 38 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a) | ||
| 39 | tcg_temp_free_ptr(fpst); | ||
| 40 | return true; | ||
| 41 | } | ||
| 42 | + | ||
| 43 | +static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a) | ||
| 44 | +{ | ||
| 45 | + int opr_sz; | ||
| 46 | + | ||
| 47 | + if (!dc_isar_feature(aa32_fhm, s)) { | ||
| 48 | + return false; | ||
| 49 | + } | ||
| 50 | + | ||
| 51 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
| 52 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
| 53 | + ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) { | ||
| 54 | + return false; | ||
| 55 | + } | ||
| 56 | + | ||
| 57 | + if (a->vd & a->q) { | ||
| 58 | + return false; | ||
| 59 | + } | ||
| 60 | + | ||
| 61 | + if (!vfp_access_check(s)) { | ||
| 62 | + return true; | ||
| 63 | + } | ||
| 64 | + | ||
| 65 | + opr_sz = (1 + a->q) * 8; | ||
| 66 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), | ||
| 67 | + vfp_reg_offset(a->q, a->vn), | ||
| 68 | + vfp_reg_offset(a->q, a->rm), | ||
| 69 | + cpu_env, opr_sz, opr_sz, | ||
| 70 | + (a->index << 2) | a->s, /* is_2 == 0 */ | ||
| 71 | + gen_helper_gvec_fmlal_idx_a32); | ||
| 72 | + return true; | ||
| 73 | +} | ||
| 74 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 75 | index XXXXXXX..XXXXXXX 100644 | ||
| 76 | --- a/target/arm/translate.c | ||
| 77 | +++ b/target/arm/translate.c | ||
| 78 | @@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn) | ||
| 79 | } | ||
| 80 | |||
| 81 | #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n)) | ||
| 82 | -#define VFP_SREG(insn, bigbit, smallbit) \ | ||
| 83 | - ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) | ||
| 84 | #define VFP_DREG(reg, insn, bigbit, smallbit) do { \ | ||
| 85 | if (dc_isar_feature(aa32_simd_r32, s)) { \ | ||
| 86 | reg = (((insn) >> (bigbit)) & 0x0f) \ | ||
| 87 | @@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn) | ||
| 88 | reg = ((insn) >> (bigbit)) & 0x0f; \ | ||
| 89 | }} while (0) | ||
| 90 | |||
| 91 | -#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22) | ||
| 92 | #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22) | ||
| 93 | -#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7) | ||
| 94 | #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7) | ||
| 95 | -#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5) | ||
| 96 | #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5) | ||
| 97 | |||
| 98 | static void gen_neon_dup_low16(TCGv_i32 var) | ||
| 99 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 100 | return 0; | ||
| 101 | } | ||
| 102 | |||
| 103 | -/* Advanced SIMD two registers and a scalar extension. | ||
| 104 | - * 31 24 23 22 20 16 12 11 10 9 8 3 0 | ||
| 105 | - * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | ||
| 106 | - * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | ||
| 107 | - * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | ||
| 108 | - * | ||
| 109 | - */ | ||
| 110 | - | 30 | - |
| 111 | -static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) | 31 | - dev = qdev_new("pl011_luminary"); |
| 112 | -{ | 32 | - s = SYS_BUS_DEVICE(dev); |
| 113 | - gen_helper_gvec_3 *fn_gvec = NULL; | 33 | - qdev_prop_set_chr(dev, "chardev", chr); |
| 114 | - gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL; | 34 | - sysbus_realize_and_unref(s, &error_fatal); |
| 115 | - int rd, rn, rm, opr_sz, data; | 35 | - sysbus_mmio_map(s, 0, addr); |
| 116 | - int off_rn, off_rm; | 36 | - sysbus_connect_irq(s, 0, irq); |
| 117 | - bool is_long = false, q = extract32(insn, 6, 1); | ||
| 118 | - bool ptr_is_env = false; | ||
| 119 | - | 37 | - |
| 120 | - if ((insn & 0xffa00f10) == 0xfe000810) { | 38 | - return dev; |
| 121 | - /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */ | ||
| 122 | - int is_s = extract32(insn, 20, 1); | ||
| 123 | - int vm20 = extract32(insn, 0, 3); | ||
| 124 | - int vm3 = extract32(insn, 3, 1); | ||
| 125 | - int m = extract32(insn, 5, 1); | ||
| 126 | - int index; | ||
| 127 | - | ||
| 128 | - if (!dc_isar_feature(aa32_fhm, s)) { | ||
| 129 | - return 1; | ||
| 130 | - } | ||
| 131 | - if (q) { | ||
| 132 | - rm = vm20; | ||
| 133 | - index = m * 2 + vm3; | ||
| 134 | - } else { | ||
| 135 | - rm = vm20 * 2 + m; | ||
| 136 | - index = vm3; | ||
| 137 | - } | ||
| 138 | - is_long = true; | ||
| 139 | - data = (index << 2) | is_s; /* is_2 == 0 */ | ||
| 140 | - fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32; | ||
| 141 | - ptr_is_env = true; | ||
| 142 | - } else { | ||
| 143 | - return 1; | ||
| 144 | - } | ||
| 145 | - | ||
| 146 | - VFP_DREG_D(rd, insn); | ||
| 147 | - if (rd & q) { | ||
| 148 | - return 1; | ||
| 149 | - } | ||
| 150 | - if (q || !is_long) { | ||
| 151 | - VFP_DREG_N(rn, insn); | ||
| 152 | - if (rn & q & !is_long) { | ||
| 153 | - return 1; | ||
| 154 | - } | ||
| 155 | - off_rn = vfp_reg_offset(1, rn); | ||
| 156 | - off_rm = vfp_reg_offset(1, rm); | ||
| 157 | - } else { | ||
| 158 | - rn = VFP_SREG_N(insn); | ||
| 159 | - off_rn = vfp_reg_offset(0, rn); | ||
| 160 | - off_rm = vfp_reg_offset(0, rm); | ||
| 161 | - } | ||
| 162 | - if (s->fp_excp_el) { | ||
| 163 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
| 164 | - syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); | ||
| 165 | - return 0; | ||
| 166 | - } | ||
| 167 | - if (!s->vfp_enabled) { | ||
| 168 | - return 1; | ||
| 169 | - } | ||
| 170 | - | ||
| 171 | - opr_sz = (1 + q) * 8; | ||
| 172 | - if (fn_gvec_ptr) { | ||
| 173 | - TCGv_ptr ptr; | ||
| 174 | - if (ptr_is_env) { | ||
| 175 | - ptr = cpu_env; | ||
| 176 | - } else { | ||
| 177 | - ptr = get_fpstatus_ptr(1); | ||
| 178 | - } | ||
| 179 | - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr, | ||
| 180 | - opr_sz, opr_sz, data, fn_gvec_ptr); | ||
| 181 | - if (!ptr_is_env) { | ||
| 182 | - tcg_temp_free_ptr(ptr); | ||
| 183 | - } | ||
| 184 | - } else { | ||
| 185 | - tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm, | ||
| 186 | - opr_sz, opr_sz, data, fn_gvec); | ||
| 187 | - } | ||
| 188 | - return 0; | ||
| 189 | -} | 39 | -} |
| 190 | - | 40 | - |
| 191 | static int disas_coproc_insn(DisasContext *s, uint32_t insn) | 41 | #endif |
| 192 | { | 42 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c |
| 193 | int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2; | 43 | index XXXXXXX..XXXXXXX 100644 |
| 194 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 44 | --- a/hw/arm/stellaris.c |
| 195 | } | 45 | +++ b/hw/arm/stellaris.c |
| 196 | } | 46 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
| 197 | } | 47 | |
| 198 | - } else if ((insn & 0x0f000a00) == 0x0e000800 | 48 | for (i = 0; i < 4; i++) { |
| 199 | - && arm_dc_feature(s, ARM_FEATURE_V8)) { | 49 | if (board->dc2 & (1 << i)) { |
| 200 | - if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | 50 | - pl011_luminary_create(0x4000c000 + i * 0x1000, |
| 201 | - goto illegal_op; | 51 | - qdev_get_gpio_in(nvic, uart_irq[i]), |
| 202 | - } | 52 | - serial_hd(i)); |
| 203 | - return; | 53 | + SysBusDevice *sbd; |
| 54 | + | ||
| 55 | + dev = qdev_new("pl011_luminary"); | ||
| 56 | + sbd = SYS_BUS_DEVICE(dev); | ||
| 57 | + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); | ||
| 58 | + sysbus_realize_and_unref(sbd, &error_fatal); | ||
| 59 | + sysbus_mmio_map(sbd, 0, 0x4000c000 + i * 0x1000); | ||
| 60 | + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(nvic, uart_irq[i])); | ||
| 204 | } | 61 | } |
| 205 | goto illegal_op; | ||
| 206 | } | 62 | } |
| 207 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 63 | if (board->dc2 & (1 << 4)) { |
| 208 | } | ||
| 209 | break; | ||
| 210 | } | ||
| 211 | - if ((insn & 0xff000a00) == 0xfe000800 | ||
| 212 | - && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
| 213 | - /* The Thumb2 and ARM encodings are identical. */ | ||
| 214 | - if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | ||
| 215 | - goto illegal_op; | ||
| 216 | - } | ||
| 217 | - } else if (((insn >> 24) & 3) == 3) { | ||
| 218 | + if (((insn >> 24) & 3) == 3) { | ||
| 219 | /* Translate into the equivalent ARM encoding. */ | ||
| 220 | insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); | ||
| 221 | if (disas_neon_data_insn(s, insn)) { | ||
| 222 | -- | 64 | -- |
| 223 | 2.20.1 | 65 | 2.34.1 |
| 224 | 66 | ||
| 225 | 67 | diff view generated by jsdifflib |
| 1 | Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree. | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20230220115114.25237-5-philmd@linaro.org | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20200430181003.21682-9-peter.maydell@linaro.org | ||
| 6 | --- | 8 | --- |
| 7 | target/arm/neon-shared.decode | 5 +++++ | 9 | include/hw/char/xilinx_uartlite.h | 6 +++++- |
| 8 | target/arm/translate-neon.inc.c | 40 +++++++++++++++++++++++++++++++++ | 10 | hw/char/xilinx_uartlite.c | 4 +--- |
| 9 | target/arm/translate.c | 26 +-------------------- | 11 | 2 files changed, 6 insertions(+), 4 deletions(-) |
| 10 | 3 files changed, 46 insertions(+), 25 deletions(-) | ||
| 11 | 12 | ||
| 12 | diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode | 13 | diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uartlite.h |
| 13 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 14 | --- a/target/arm/neon-shared.decode | 15 | --- a/include/hw/char/xilinx_uartlite.h |
| 15 | +++ b/target/arm/neon-shared.decode | 16 | +++ b/include/hw/char/xilinx_uartlite.h |
| 16 | @@ -XXX,XX +XXX,XX @@ VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \ | 17 | @@ -XXX,XX +XXX,XX @@ |
| 17 | vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0 | 18 | #include "hw/qdev-properties.h" |
| 18 | VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \ | 19 | #include "hw/sysbus.h" |
| 19 | vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1 | 20 | #include "qapi/error.h" |
| 21 | +#include "qom/object.h" | ||
| 20 | + | 22 | + |
| 21 | +VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \ | 23 | +#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" |
| 22 | + vn=%vn_dp vd=%vd_dp size=0 | 24 | +OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE) |
| 23 | +VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \ | 25 | |
| 24 | + vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0 | 26 | static inline DeviceState *xilinx_uartlite_create(hwaddr addr, |
| 25 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 27 | qemu_irq irq, |
| 28 | @@ -XXX,XX +XXX,XX @@ static inline DeviceState *xilinx_uartlite_create(hwaddr addr, | ||
| 29 | DeviceState *dev; | ||
| 30 | SysBusDevice *s; | ||
| 31 | |||
| 32 | - dev = qdev_new("xlnx.xps-uartlite"); | ||
| 33 | + dev = qdev_new(TYPE_XILINX_UARTLITE); | ||
| 34 | s = SYS_BUS_DEVICE(dev); | ||
| 35 | qdev_prop_set_chr(dev, "chardev", chr); | ||
| 36 | sysbus_realize_and_unref(s, &error_fatal); | ||
| 37 | diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c | ||
| 26 | index XXXXXXX..XXXXXXX 100644 | 38 | index XXXXXXX..XXXXXXX 100644 |
| 27 | --- a/target/arm/translate-neon.inc.c | 39 | --- a/hw/char/xilinx_uartlite.c |
| 28 | +++ b/target/arm/translate-neon.inc.c | 40 | +++ b/hw/char/xilinx_uartlite.c |
| 29 | @@ -XXX,XX +XXX,XX @@ static bool trans_VFML(DisasContext *s, arg_VFML *a) | 41 | @@ -XXX,XX +XXX,XX @@ |
| 30 | gen_helper_gvec_fmlal_a32); | 42 | |
| 31 | return true; | 43 | #include "qemu/osdep.h" |
| 32 | } | 44 | #include "qemu/log.h" |
| 33 | + | 45 | +#include "hw/char/xilinx_uartlite.h" |
| 34 | +static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a) | 46 | #include "hw/irq.h" |
| 35 | +{ | 47 | #include "hw/qdev-properties.h" |
| 36 | + gen_helper_gvec_3_ptr *fn_gvec_ptr; | 48 | #include "hw/qdev-properties-system.h" |
| 37 | + int opr_sz; | 49 | @@ -XXX,XX +XXX,XX @@ |
| 38 | + TCGv_ptr fpst; | 50 | #define CONTROL_RST_RX 0x02 |
| 39 | + | 51 | #define CONTROL_IE 0x10 |
| 40 | + if (!dc_isar_feature(aa32_vcma, s)) { | 52 | |
| 41 | + return false; | 53 | -#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" |
| 42 | + } | 54 | -OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE) |
| 43 | + if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) { | ||
| 44 | + return false; | ||
| 45 | + } | ||
| 46 | + | ||
| 47 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
| 48 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
| 49 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
| 50 | + return false; | ||
| 51 | + } | ||
| 52 | + | ||
| 53 | + if ((a->vd | a->vn) & a->q) { | ||
| 54 | + return false; | ||
| 55 | + } | ||
| 56 | + | ||
| 57 | + if (!vfp_access_check(s)) { | ||
| 58 | + return true; | ||
| 59 | + } | ||
| 60 | + | ||
| 61 | + fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx | ||
| 62 | + : gen_helper_gvec_fcmlah_idx); | ||
| 63 | + opr_sz = (1 + a->q) * 8; | ||
| 64 | + fpst = get_fpstatus_ptr(1); | ||
| 65 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), | ||
| 66 | + vfp_reg_offset(1, a->vn), | ||
| 67 | + vfp_reg_offset(1, a->vm), | ||
| 68 | + fpst, opr_sz, opr_sz, | ||
| 69 | + (a->index << 2) | a->rot, fn_gvec_ptr); | ||
| 70 | + tcg_temp_free_ptr(fpst); | ||
| 71 | + return true; | ||
| 72 | +} | ||
| 73 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 74 | index XXXXXXX..XXXXXXX 100644 | ||
| 75 | --- a/target/arm/translate.c | ||
| 76 | +++ b/target/arm/translate.c | ||
| 77 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) | ||
| 78 | bool is_long = false, q = extract32(insn, 6, 1); | ||
| 79 | bool ptr_is_env = false; | ||
| 80 | |||
| 81 | - if ((insn & 0xff000f10) == 0xfe000800) { | ||
| 82 | - /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ | ||
| 83 | - int rot = extract32(insn, 20, 2); | ||
| 84 | - int size = extract32(insn, 23, 1); | ||
| 85 | - int index; | ||
| 86 | - | 55 | - |
| 87 | - if (!dc_isar_feature(aa32_vcma, s)) { | 56 | struct XilinxUARTLite { |
| 88 | - return 1; | 57 | SysBusDevice parent_obj; |
| 89 | - } | ||
| 90 | - if (size == 0) { | ||
| 91 | - if (!dc_isar_feature(aa32_fp16_arith, s)) { | ||
| 92 | - return 1; | ||
| 93 | - } | ||
| 94 | - /* For fp16, rm is just Vm, and index is M. */ | ||
| 95 | - rm = extract32(insn, 0, 4); | ||
| 96 | - index = extract32(insn, 5, 1); | ||
| 97 | - } else { | ||
| 98 | - /* For fp32, rm is the usual M:Vm, and index is 0. */ | ||
| 99 | - VFP_DREG_M(rm, insn); | ||
| 100 | - index = 0; | ||
| 101 | - } | ||
| 102 | - data = (index << 2) | rot; | ||
| 103 | - fn_gvec_ptr = (size ? gen_helper_gvec_fcmlas_idx | ||
| 104 | - : gen_helper_gvec_fcmlah_idx); | ||
| 105 | - } else if ((insn & 0xffb00f00) == 0xfe200d00) { | ||
| 106 | + if ((insn & 0xffb00f00) == 0xfe200d00) { | ||
| 107 | /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */ | ||
| 108 | int u = extract32(insn, 4, 1); | ||
| 109 | 58 | ||
| 110 | -- | 59 | -- |
| 111 | 2.20.1 | 60 | 2.34.1 |
| 112 | 61 | ||
| 113 | 62 | diff view generated by jsdifflib |
| 1 | From: Philippe Mathieu-Daudé <f4bug@amsat.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | By using the TYPE_* definitions for devices, we can: | 3 | Open-code the single use of xilinx_uartlite_create(). |
| 4 | - quickly find where devices are used with 'git-grep' | ||
| 5 | - easily rename a device (one-line change). | ||
| 6 | 4 | ||
| 7 | Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 8 | Message-id: 20200428154650.21991-1-f4bug@amsat.org | 6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
| 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
| 8 | Message-id: 20230220115114.25237-6-philmd@linaro.org | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 10 | --- |
| 12 | hw/arm/mps2-tz.c | 2 +- | 11 | include/hw/char/xilinx_uartlite.h | 20 -------------------- |
| 13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | hw/microblaze/petalogix_s3adsp1800_mmu.c | 7 +++++-- |
| 13 | 2 files changed, 5 insertions(+), 22 deletions(-) | ||
| 14 | 14 | ||
| 15 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | 15 | diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uartlite.h |
| 16 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/hw/arm/mps2-tz.c | 17 | --- a/include/hw/char/xilinx_uartlite.h |
| 18 | +++ b/hw/arm/mps2-tz.c | 18 | +++ b/include/hw/char/xilinx_uartlite.h |
| 19 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | 19 | @@ -XXX,XX +XXX,XX @@ |
| 20 | exit(EXIT_FAILURE); | 20 | #ifndef XILINX_UARTLITE_H |
| 21 | #define XILINX_UARTLITE_H | ||
| 22 | |||
| 23 | -#include "hw/qdev-properties.h" | ||
| 24 | -#include "hw/sysbus.h" | ||
| 25 | -#include "qapi/error.h" | ||
| 26 | #include "qom/object.h" | ||
| 27 | |||
| 28 | #define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite" | ||
| 29 | OBJECT_DECLARE_SIMPLE_TYPE(XilinxUARTLite, XILINX_UARTLITE) | ||
| 30 | |||
| 31 | -static inline DeviceState *xilinx_uartlite_create(hwaddr addr, | ||
| 32 | - qemu_irq irq, | ||
| 33 | - Chardev *chr) | ||
| 34 | -{ | ||
| 35 | - DeviceState *dev; | ||
| 36 | - SysBusDevice *s; | ||
| 37 | - | ||
| 38 | - dev = qdev_new(TYPE_XILINX_UARTLITE); | ||
| 39 | - s = SYS_BUS_DEVICE(dev); | ||
| 40 | - qdev_prop_set_chr(dev, "chardev", chr); | ||
| 41 | - sysbus_realize_and_unref(s, &error_fatal); | ||
| 42 | - sysbus_mmio_map(s, 0, addr); | ||
| 43 | - sysbus_connect_irq(s, 0, irq); | ||
| 44 | - | ||
| 45 | - return dev; | ||
| 46 | -} | ||
| 47 | - | ||
| 48 | #endif | ||
| 49 | diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c | ||
| 50 | index XXXXXXX..XXXXXXX 100644 | ||
| 51 | --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c | ||
| 52 | +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c | ||
| 53 | @@ -XXX,XX +XXX,XX @@ petalogix_s3adsp1800_init(MachineState *machine) | ||
| 54 | irq[i] = qdev_get_gpio_in(dev, i); | ||
| 21 | } | 55 | } |
| 22 | 56 | ||
| 23 | - sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, | 57 | - xilinx_uartlite_create(UARTLITE_BASEADDR, irq[UARTLITE_IRQ], |
| 24 | + sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit, | 58 | - serial_hd(0)); |
| 25 | sizeof(mms->iotkit), mmc->armsse_type); | 59 | + dev = qdev_new(TYPE_XILINX_UARTLITE); |
| 26 | iotkitdev = DEVICE(&mms->iotkit); | 60 | + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); |
| 27 | object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory), | 61 | + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
| 62 | + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); | ||
| 63 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]); | ||
| 64 | |||
| 65 | /* 2 timers at irq 2 @ 62 Mhz. */ | ||
| 66 | dev = qdev_new("xlnx.xps-timer"); | ||
| 28 | -- | 67 | -- |
| 29 | 2.20.1 | 68 | 2.34.1 |
| 30 | 69 | ||
| 31 | 70 | diff view generated by jsdifflib |
| 1 | Convert the Neon "load/store single structure to one lane" insns to | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | decodetree. | ||
| 3 | 2 | ||
| 4 | As this is the last set of insns in the neon load/store group, | 3 | cmsdk_apb_uart_create() is only used twice in the same |
| 5 | we can remove the whole disas_neon_ls_insn() function. | 4 | file. Open-code it. |
| 6 | 5 | ||
| 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 8 | Message-id: 20230220115114.25237-7-philmd@linaro.org | ||
| 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 9 | Message-id: 20200430181003.21682-14-peter.maydell@linaro.org | ||
| 10 | --- | 10 | --- |
| 11 | target/arm/neon-ls.decode | 11 +++ | 11 | include/hw/char/cmsdk-apb-uart.h | 34 -------------------------- |
| 12 | target/arm/translate-neon.inc.c | 89 +++++++++++++++++++ | 12 | hw/arm/mps2.c | 41 +++++++++++++++++++++----------- |
| 13 | target/arm/translate.c | 147 -------------------------------- | 13 | 2 files changed, 27 insertions(+), 48 deletions(-) |
| 14 | 3 files changed, 100 insertions(+), 147 deletions(-) | ||
| 15 | 14 | ||
| 16 | diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode | 15 | diff --git a/include/hw/char/cmsdk-apb-uart.h b/include/hw/char/cmsdk-apb-uart.h |
| 17 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/target/arm/neon-ls.decode | 17 | --- a/include/hw/char/cmsdk-apb-uart.h |
| 19 | +++ b/target/arm/neon-ls.decode | 18 | +++ b/include/hw/char/cmsdk-apb-uart.h |
| 20 | @@ -XXX,XX +XXX,XX @@ VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \ | ||
| 21 | |||
| 22 | VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \ | ||
| 23 | vd=%vd_dp | ||
| 24 | + | ||
| 25 | +# Neon load/store single structure to one lane | ||
| 26 | +%imm1_5_p1 5:1 !function=plus1 | ||
| 27 | +%imm1_6_p1 6:1 !function=plus1 | ||
| 28 | + | ||
| 29 | +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \ | ||
| 30 | + vd=%vd_dp size=0 stride=1 | ||
| 31 | +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \ | ||
| 32 | + vd=%vd_dp size=1 stride=%imm1_5_p1 | ||
| 33 | +VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \ | ||
| 34 | + vd=%vd_dp size=2 stride=%imm1_6_p1 | ||
| 35 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 36 | index XXXXXXX..XXXXXXX 100644 | ||
| 37 | --- a/target/arm/translate-neon.inc.c | ||
| 38 | +++ b/target/arm/translate-neon.inc.c | ||
| 39 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ |
| 40 | * It might be possible to convert it to a standalone .c file eventually. | 20 | #ifndef CMSDK_APB_UART_H |
| 41 | */ | 21 | #define CMSDK_APB_UART_H |
| 42 | 22 | ||
| 43 | +static inline int plus1(DisasContext *s, int x) | 23 | -#include "hw/qdev-properties.h" |
| 44 | +{ | 24 | #include "hw/sysbus.h" |
| 45 | + return x + 1; | 25 | #include "chardev/char-fe.h" |
| 46 | +} | 26 | -#include "qapi/error.h" |
| 47 | + | 27 | #include "qom/object.h" |
| 48 | /* Include the generated Neon decoder */ | 28 | |
| 49 | #include "decode-neon-dp.inc.c" | 29 | #define TYPE_CMSDK_APB_UART "cmsdk-apb-uart" |
| 50 | #include "decode-neon-ls.inc.c" | 30 | @@ -XXX,XX +XXX,XX @@ struct CMSDKAPBUART { |
| 51 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) | 31 | uint8_t rxbuf; |
| 52 | 32 | }; | |
| 53 | return true; | 33 | |
| 54 | } | 34 | -/** |
| 55 | + | 35 | - * cmsdk_apb_uart_create - convenience function to create TYPE_CMSDK_APB_UART |
| 56 | +static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a) | 36 | - * @addr: location in system memory to map registers |
| 57 | +{ | 37 | - * @chr: Chardev backend to connect UART to, or NULL if no backend |
| 58 | + /* Neon load/store single structure to one lane */ | 38 | - * @pclk_frq: frequency in Hz of the PCLK clock (used for calculating baud rate) |
| 59 | + int reg; | 39 | - */ |
| 60 | + int nregs = a->n + 1; | 40 | -static inline DeviceState *cmsdk_apb_uart_create(hwaddr addr, |
| 61 | + int vd = a->vd; | 41 | - qemu_irq txint, |
| 62 | + TCGv_i32 addr, tmp; | 42 | - qemu_irq rxint, |
| 63 | + | 43 | - qemu_irq txovrint, |
| 64 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | 44 | - qemu_irq rxovrint, |
| 65 | + return false; | 45 | - qemu_irq uartint, |
| 66 | + } | 46 | - Chardev *chr, |
| 67 | + | 47 | - uint32_t pclk_frq) |
| 68 | + /* UNDEF accesses to D16-D31 if they don't exist */ | 48 | -{ |
| 69 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | 49 | - DeviceState *dev; |
| 70 | + return false; | 50 | - SysBusDevice *s; |
| 71 | + } | ||
| 72 | + | ||
| 73 | + /* Catch the UNDEF cases. This is unavoidably a bit messy. */ | ||
| 74 | + switch (nregs) { | ||
| 75 | + case 1: | ||
| 76 | + if (((a->align & (1 << a->size)) != 0) || | ||
| 77 | + (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) { | ||
| 78 | + return false; | ||
| 79 | + } | ||
| 80 | + break; | ||
| 81 | + case 3: | ||
| 82 | + if ((a->align & 1) != 0) { | ||
| 83 | + return false; | ||
| 84 | + } | ||
| 85 | + /* fall through */ | ||
| 86 | + case 2: | ||
| 87 | + if (a->size == 2 && (a->align & 2) != 0) { | ||
| 88 | + return false; | ||
| 89 | + } | ||
| 90 | + break; | ||
| 91 | + case 4: | ||
| 92 | + if ((a->size == 2) && ((a->align & 3) == 3)) { | ||
| 93 | + return false; | ||
| 94 | + } | ||
| 95 | + break; | ||
| 96 | + default: | ||
| 97 | + abort(); | ||
| 98 | + } | ||
| 99 | + if ((vd + a->stride * (nregs - 1)) > 31) { | ||
| 100 | + /* | ||
| 101 | + * Attempts to write off the end of the register file are | ||
| 102 | + * UNPREDICTABLE; we choose to UNDEF because otherwise we would | ||
| 103 | + * access off the end of the array that holds the register data. | ||
| 104 | + */ | ||
| 105 | + return false; | ||
| 106 | + } | ||
| 107 | + | ||
| 108 | + if (!vfp_access_check(s)) { | ||
| 109 | + return true; | ||
| 110 | + } | ||
| 111 | + | ||
| 112 | + tmp = tcg_temp_new_i32(); | ||
| 113 | + addr = tcg_temp_new_i32(); | ||
| 114 | + load_reg_var(s, addr, a->rn); | ||
| 115 | + /* | ||
| 116 | + * TODO: if we implemented alignment exceptions, we should check | ||
| 117 | + * addr against the alignment encoded in a->align here. | ||
| 118 | + */ | ||
| 119 | + for (reg = 0; reg < nregs; reg++) { | ||
| 120 | + if (a->l) { | ||
| 121 | + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), | ||
| 122 | + s->be_data | a->size); | ||
| 123 | + neon_store_element(vd, a->reg_idx, a->size, tmp); | ||
| 124 | + } else { /* Store */ | ||
| 125 | + neon_load_element(tmp, vd, a->reg_idx, a->size); | ||
| 126 | + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), | ||
| 127 | + s->be_data | a->size); | ||
| 128 | + } | ||
| 129 | + vd += a->stride; | ||
| 130 | + tcg_gen_addi_i32(addr, addr, 1 << a->size); | ||
| 131 | + } | ||
| 132 | + tcg_temp_free_i32(addr); | ||
| 133 | + tcg_temp_free_i32(tmp); | ||
| 134 | + | ||
| 135 | + gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs); | ||
| 136 | + | ||
| 137 | + return true; | ||
| 138 | +} | ||
| 139 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 140 | index XXXXXXX..XXXXXXX 100644 | ||
| 141 | --- a/target/arm/translate.c | ||
| 142 | +++ b/target/arm/translate.c | ||
| 143 | @@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1) | ||
| 144 | tcg_temp_free_i32(rd); | ||
| 145 | } | ||
| 146 | |||
| 147 | - | 51 | - |
| 148 | -/* Translate a NEON load/store element instruction. Return nonzero if the | 52 | - dev = qdev_new(TYPE_CMSDK_APB_UART); |
| 149 | - instruction is invalid. */ | 53 | - s = SYS_BUS_DEVICE(dev); |
| 150 | -static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) | 54 | - qdev_prop_set_chr(dev, "chardev", chr); |
| 151 | -{ | 55 | - qdev_prop_set_uint32(dev, "pclk-frq", pclk_frq); |
| 152 | - int rd, rn, rm; | 56 | - sysbus_realize_and_unref(s, &error_fatal); |
| 153 | - int nregs; | 57 | - sysbus_mmio_map(s, 0, addr); |
| 154 | - int stride; | 58 | - sysbus_connect_irq(s, 0, txint); |
| 155 | - int size; | 59 | - sysbus_connect_irq(s, 1, rxint); |
| 156 | - int reg; | 60 | - sysbus_connect_irq(s, 2, txovrint); |
| 157 | - int load; | 61 | - sysbus_connect_irq(s, 3, rxovrint); |
| 158 | - TCGv_i32 addr; | 62 | - sysbus_connect_irq(s, 4, uartint); |
| 159 | - TCGv_i32 tmp; | 63 | - return dev; |
| 160 | - | ||
| 161 | - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
| 162 | - return 1; | ||
| 163 | - } | ||
| 164 | - | ||
| 165 | - /* FIXME: this access check should not take precedence over UNDEF | ||
| 166 | - * for invalid encodings; we will generate incorrect syndrome information | ||
| 167 | - * for attempts to execute invalid vfp/neon encodings with FP disabled. | ||
| 168 | - */ | ||
| 169 | - if (s->fp_excp_el) { | ||
| 170 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
| 171 | - syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); | ||
| 172 | - return 0; | ||
| 173 | - } | ||
| 174 | - | ||
| 175 | - if (!s->vfp_enabled) | ||
| 176 | - return 1; | ||
| 177 | - VFP_DREG_D(rd, insn); | ||
| 178 | - rn = (insn >> 16) & 0xf; | ||
| 179 | - rm = insn & 0xf; | ||
| 180 | - load = (insn & (1 << 21)) != 0; | ||
| 181 | - if ((insn & (1 << 23)) == 0) { | ||
| 182 | - /* Load store all elements -- handled already by decodetree */ | ||
| 183 | - return 1; | ||
| 184 | - } else { | ||
| 185 | - size = (insn >> 10) & 3; | ||
| 186 | - if (size == 3) { | ||
| 187 | - /* Load single element to all lanes -- handled by decodetree */ | ||
| 188 | - return 1; | ||
| 189 | - } else { | ||
| 190 | - /* Single element. */ | ||
| 191 | - int idx = (insn >> 4) & 0xf; | ||
| 192 | - int reg_idx; | ||
| 193 | - switch (size) { | ||
| 194 | - case 0: | ||
| 195 | - reg_idx = (insn >> 5) & 7; | ||
| 196 | - stride = 1; | ||
| 197 | - break; | ||
| 198 | - case 1: | ||
| 199 | - reg_idx = (insn >> 6) & 3; | ||
| 200 | - stride = (insn & (1 << 5)) ? 2 : 1; | ||
| 201 | - break; | ||
| 202 | - case 2: | ||
| 203 | - reg_idx = (insn >> 7) & 1; | ||
| 204 | - stride = (insn & (1 << 6)) ? 2 : 1; | ||
| 205 | - break; | ||
| 206 | - default: | ||
| 207 | - abort(); | ||
| 208 | - } | ||
| 209 | - nregs = ((insn >> 8) & 3) + 1; | ||
| 210 | - /* Catch the UNDEF cases. This is unavoidably a bit messy. */ | ||
| 211 | - switch (nregs) { | ||
| 212 | - case 1: | ||
| 213 | - if (((idx & (1 << size)) != 0) || | ||
| 214 | - (size == 2 && ((idx & 3) == 1 || (idx & 3) == 2))) { | ||
| 215 | - return 1; | ||
| 216 | - } | ||
| 217 | - break; | ||
| 218 | - case 3: | ||
| 219 | - if ((idx & 1) != 0) { | ||
| 220 | - return 1; | ||
| 221 | - } | ||
| 222 | - /* fall through */ | ||
| 223 | - case 2: | ||
| 224 | - if (size == 2 && (idx & 2) != 0) { | ||
| 225 | - return 1; | ||
| 226 | - } | ||
| 227 | - break; | ||
| 228 | - case 4: | ||
| 229 | - if ((size == 2) && ((idx & 3) == 3)) { | ||
| 230 | - return 1; | ||
| 231 | - } | ||
| 232 | - break; | ||
| 233 | - default: | ||
| 234 | - abort(); | ||
| 235 | - } | ||
| 236 | - if ((rd + stride * (nregs - 1)) > 31) { | ||
| 237 | - /* Attempts to write off the end of the register file | ||
| 238 | - * are UNPREDICTABLE; we choose to UNDEF because otherwise | ||
| 239 | - * the neon_load_reg() would write off the end of the array. | ||
| 240 | - */ | ||
| 241 | - return 1; | ||
| 242 | - } | ||
| 243 | - tmp = tcg_temp_new_i32(); | ||
| 244 | - addr = tcg_temp_new_i32(); | ||
| 245 | - load_reg_var(s, addr, rn); | ||
| 246 | - for (reg = 0; reg < nregs; reg++) { | ||
| 247 | - if (load) { | ||
| 248 | - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), | ||
| 249 | - s->be_data | size); | ||
| 250 | - neon_store_element(rd, reg_idx, size, tmp); | ||
| 251 | - } else { /* Store */ | ||
| 252 | - neon_load_element(tmp, rd, reg_idx, size); | ||
| 253 | - gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), | ||
| 254 | - s->be_data | size); | ||
| 255 | - } | ||
| 256 | - rd += stride; | ||
| 257 | - tcg_gen_addi_i32(addr, addr, 1 << size); | ||
| 258 | - } | ||
| 259 | - tcg_temp_free_i32(addr); | ||
| 260 | - tcg_temp_free_i32(tmp); | ||
| 261 | - stride = nregs * (1 << size); | ||
| 262 | - } | ||
| 263 | - } | ||
| 264 | - if (rm != 15) { | ||
| 265 | - TCGv_i32 base; | ||
| 266 | - | ||
| 267 | - base = load_reg(s, rn); | ||
| 268 | - if (rm == 13) { | ||
| 269 | - tcg_gen_addi_i32(base, base, stride); | ||
| 270 | - } else { | ||
| 271 | - TCGv_i32 index; | ||
| 272 | - index = load_reg(s, rm); | ||
| 273 | - tcg_gen_add_i32(base, base, index); | ||
| 274 | - tcg_temp_free_i32(index); | ||
| 275 | - } | ||
| 276 | - store_reg(s, rn, base); | ||
| 277 | - } | ||
| 278 | - return 0; | ||
| 279 | -} | 64 | -} |
| 280 | - | 65 | - |
| 281 | static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src) | 66 | #endif |
| 282 | { | 67 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c |
| 283 | switch (size) { | 68 | index XXXXXXX..XXXXXXX 100644 |
| 284 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 69 | --- a/hw/arm/mps2.c |
| 70 | +++ b/hw/arm/mps2.c | ||
| 71 | @@ -XXX,XX +XXX,XX @@ | ||
| 72 | #include "hw/boards.h" | ||
| 73 | #include "exec/address-spaces.h" | ||
| 74 | #include "sysemu/sysemu.h" | ||
| 75 | +#include "hw/qdev-properties.h" | ||
| 76 | #include "hw/misc/unimp.h" | ||
| 77 | #include "hw/char/cmsdk-apb-uart.h" | ||
| 78 | #include "hw/timer/cmsdk-apb-timer.h" | ||
| 79 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | ||
| 80 | qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); | ||
| 81 | |||
| 82 | for (i = 0; i < 5; i++) { | ||
| 83 | + DeviceState *dev; | ||
| 84 | + SysBusDevice *s; | ||
| 85 | + | ||
| 86 | static const hwaddr uartbase[] = {0x40004000, 0x40005000, | ||
| 87 | 0x40006000, 0x40007000, | ||
| 88 | 0x40009000}; | ||
| 89 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | ||
| 90 | rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1); | ||
| 285 | } | 91 | } |
| 286 | return; | 92 | |
| 287 | } | 93 | - cmsdk_apb_uart_create(uartbase[i], |
| 288 | - if ((insn & 0x0f100000) == 0x04000000) { | 94 | - qdev_get_gpio_in(armv7m, uartirq[i] + 1), |
| 289 | - /* NEON load/store. */ | 95 | - qdev_get_gpio_in(armv7m, uartirq[i]), |
| 290 | - if (disas_neon_ls_insn(s, insn)) { | 96 | - txovrint, rxovrint, |
| 291 | - goto illegal_op; | 97 | - NULL, |
| 292 | - } | 98 | - serial_hd(i), SYSCLK_FRQ); |
| 293 | - return; | 99 | + dev = qdev_new(TYPE_CMSDK_APB_UART); |
| 294 | - } | 100 | + s = SYS_BUS_DEVICE(dev); |
| 295 | if ((insn & 0x0e000f00) == 0x0c000100) { | 101 | + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
| 296 | if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { | 102 | + qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); |
| 297 | /* iWMMXt register transfer. */ | 103 | + sysbus_realize_and_unref(s, &error_fatal); |
| 298 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 104 | + sysbus_mmio_map(s, 0, uartbase[i]); |
| 105 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in(armv7m, uartirq[i] + 1)); | ||
| 106 | + sysbus_connect_irq(s, 1, qdev_get_gpio_in(armv7m, uartirq[i])); | ||
| 107 | + sysbus_connect_irq(s, 2, txovrint); | ||
| 108 | + sysbus_connect_irq(s, 3, rxovrint); | ||
| 299 | } | 109 | } |
| 300 | break; | 110 | break; |
| 301 | case 12: | 111 | } |
| 302 | - if ((insn & 0x01100000) == 0x01000000) { | 112 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) |
| 303 | - if (disas_neon_ls_insn(s, insn)) { | 113 | 0x4002c000, 0x4002d000, |
| 304 | - goto illegal_op; | 114 | 0x4002e000}; |
| 305 | - } | 115 | Object *txrx_orgate; |
| 306 | - break; | 116 | - DeviceState *txrx_orgate_dev; |
| 307 | - } | 117 | + DeviceState *txrx_orgate_dev, *dev; |
| 308 | goto illegal_op; | 118 | + SysBusDevice *s; |
| 309 | default: | 119 | |
| 310 | illegal_op: | 120 | txrx_orgate = object_new(TYPE_OR_IRQ); |
| 121 | object_property_set_int(txrx_orgate, "num-lines", 2, &error_fatal); | ||
| 122 | @@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine) | ||
| 123 | txrx_orgate_dev = DEVICE(txrx_orgate); | ||
| 124 | qdev_connect_gpio_out(txrx_orgate_dev, 0, | ||
| 125 | qdev_get_gpio_in(armv7m, uart_txrx_irqno[i])); | ||
| 126 | - cmsdk_apb_uart_create(uartbase[i], | ||
| 127 | - qdev_get_gpio_in(txrx_orgate_dev, 0), | ||
| 128 | - qdev_get_gpio_in(txrx_orgate_dev, 1), | ||
| 129 | - qdev_get_gpio_in(orgate_dev, i * 2), | ||
| 130 | - qdev_get_gpio_in(orgate_dev, i * 2 + 1), | ||
| 131 | - NULL, | ||
| 132 | - serial_hd(i), SYSCLK_FRQ); | ||
| 133 | + | ||
| 134 | + dev = qdev_new(TYPE_CMSDK_APB_UART); | ||
| 135 | + s = SYS_BUS_DEVICE(dev); | ||
| 136 | + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); | ||
| 137 | + qdev_prop_set_uint32(dev, "pclk-frq", SYSCLK_FRQ); | ||
| 138 | + sysbus_realize_and_unref(s, &error_fatal); | ||
| 139 | + sysbus_mmio_map(s, 0, uartbase[i]); | ||
| 140 | + sysbus_connect_irq(s, 0, qdev_get_gpio_in(txrx_orgate_dev, 0)); | ||
| 141 | + sysbus_connect_irq(s, 1, qdev_get_gpio_in(txrx_orgate_dev, 1)); | ||
| 142 | + sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); | ||
| 143 | + sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); | ||
| 144 | } | ||
| 145 | break; | ||
| 146 | } | ||
| 311 | -- | 147 | -- |
| 312 | 2.20.1 | 148 | 2.34.1 |
| 313 | 149 | ||
| 314 | 150 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Remove inclusion of arm_gicv3_common.h, this already gets | 3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 4 | included via xlnx-versal.h. | 4 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
| 5 | 5 | Message-id: 20230220115114.25237-8-philmd@linaro.org | |
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
| 9 | Message-id: 20200427181649.26851-2-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 7 | --- |
| 12 | hw/arm/xlnx-versal.c | 1 - | 8 | include/hw/timer/cmsdk-apb-timer.h | 1 - |
| 13 | 1 file changed, 1 deletion(-) | 9 | 1 file changed, 1 deletion(-) |
| 14 | 10 | ||
| 15 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | 11 | diff --git a/include/hw/timer/cmsdk-apb-timer.h b/include/hw/timer/cmsdk-apb-timer.h |
| 16 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/hw/arm/xlnx-versal.c | 13 | --- a/include/hw/timer/cmsdk-apb-timer.h |
| 18 | +++ b/hw/arm/xlnx-versal.c | 14 | +++ b/include/hw/timer/cmsdk-apb-timer.h |
| 19 | @@ -XXX,XX +XXX,XX @@ | 15 | @@ -XXX,XX +XXX,XX @@ |
| 20 | #include "hw/arm/boot.h" | 16 | #ifndef CMSDK_APB_TIMER_H |
| 21 | #include "kvm_arm.h" | 17 | #define CMSDK_APB_TIMER_H |
| 22 | #include "hw/misc/unimp.h" | 18 | |
| 23 | -#include "hw/intc/arm_gicv3_common.h" | 19 | -#include "hw/qdev-properties.h" |
| 24 | #include "hw/arm/xlnx-versal.h" | 20 | #include "hw/sysbus.h" |
| 25 | #include "hw/char/pl011.h" | 21 | #include "hw/ptimer.h" |
| 26 | 22 | #include "hw/clock.h" | |
| 27 | -- | 23 | -- |
| 28 | 2.20.1 | 24 | 2.34.1 |
| 29 | 25 | ||
| 30 | 26 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Move misplaced comment. | 3 | Avoid accessing 'parent_obj' directly. |
| 4 | 4 | ||
| 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> |
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Message-id: 20230220115114.25237-9-philmd@linaro.org |
| 8 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
| 9 | Message-id: 20200427181649.26851-3-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 9 | --- |
| 12 | hw/arm/xlnx-versal.c | 2 +- | 10 | hw/intc/armv7m_nvic.c | 6 +++--- |
| 13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 11 | 1 file changed, 3 insertions(+), 3 deletions(-) |
| 14 | 12 | ||
| 15 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | 13 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c |
| 16 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
| 17 | --- a/hw/arm/xlnx-versal.c | 15 | --- a/hw/intc/armv7m_nvic.c |
| 18 | +++ b/hw/arm/xlnx-versal.c | 16 | +++ b/hw/intc/armv7m_nvic.c |
| 19 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | 17 | @@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, |
| 20 | 18 | * which saves having to have an extra argument is_terminal | |
| 21 | obj = object_new(XLNX_VERSAL_ACPU_TYPE); | 19 | * that we'd only use in one place. |
| 22 | if (!obj) { | 20 | */ |
| 23 | - /* Secondary CPUs start in PSCI powered-down state */ | 21 | - cpu_abort(&s->cpu->parent_obj, |
| 24 | error_report("Unable to create apu.cpu[%d] of type %s", | 22 | + cpu_abort(CPU(s->cpu), |
| 25 | i, XLNX_VERSAL_ACPU_TYPE); | 23 | "Lockup: can't take terminal derived exception " |
| 26 | exit(EXIT_FAILURE); | 24 | "(original exception priority %d)\n", |
| 27 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | 25 | s->vectpending_prio); |
| 28 | object_property_set_int(obj, s->cfg.psci_conduit, | 26 | @@ -XXX,XX +XXX,XX @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure, |
| 29 | "psci-conduit", &error_abort); | 27 | * Lockup condition due to a guest bug. We don't model |
| 30 | if (i) { | 28 | * Lockup, so report via cpu_abort() instead. |
| 31 | + /* Secondary CPUs start in PSCI powered-down state */ | 29 | */ |
| 32 | object_property_set_bool(obj, true, | 30 | - cpu_abort(&s->cpu->parent_obj, |
| 33 | "start-powered-off", &error_abort); | 31 | + cpu_abort(CPU(s->cpu), |
| 32 | "Lockup: can't escalate %d to HardFault " | ||
| 33 | "(current priority %d)\n", irq, running); | ||
| 34 | } | ||
| 35 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_lazyfp(NVICState *s, int irq, bool secure) | ||
| 36 | * We want to escalate to HardFault but the context the | ||
| 37 | * FP state belongs to prevents the exception pre-empting. | ||
| 38 | */ | ||
| 39 | - cpu_abort(&s->cpu->parent_obj, | ||
| 40 | + cpu_abort(CPU(s->cpu), | ||
| 41 | "Lockup: can't escalate to HardFault during " | ||
| 42 | "lazy FP register stacking\n"); | ||
| 34 | } | 43 | } |
| 35 | -- | 44 | -- |
| 36 | 2.20.1 | 45 | 2.34.1 |
| 37 | 46 | ||
| 38 | 47 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | hw/arm: versal: Add support for the RTC. | 3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 4 | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | |
| 5 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 8 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
| 9 | Message-id: 20200427181649.26851-10-edgar.iglesias@gmail.com | ||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 11 | --- | 6 | --- |
| 12 | include/hw/arm/xlnx-versal.h | 8 ++++++++ | 7 | hw/arm/musicpal.c | 4 ---- |
| 13 | hw/arm/xlnx-versal.c | 21 +++++++++++++++++++++ | 8 | 1 file changed, 4 deletions(-) |
| 14 | 2 files changed, 29 insertions(+) | ||
| 15 | 9 | ||
| 16 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 10 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c |
| 17 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
| 18 | --- a/include/hw/arm/xlnx-versal.h | 12 | --- a/hw/arm/musicpal.c |
| 19 | +++ b/include/hw/arm/xlnx-versal.h | 13 | +++ b/hw/arm/musicpal.c |
| 20 | @@ -XXX,XX +XXX,XX @@ | 14 | @@ -XXX,XX +XXX,XX @@ struct musicpal_key_state { |
| 21 | #include "hw/char/pl011.h" | 15 | SysBusDevice parent_obj; |
| 22 | #include "hw/dma/xlnx-zdma.h" | 16 | /*< public >*/ |
| 23 | #include "hw/net/cadence_gem.h" | 17 | |
| 24 | +#include "hw/rtc/xlnx-zynqmp-rtc.h" | 18 | - MemoryRegion iomem; |
| 25 | 19 | uint32_t kbd_extended; | |
| 26 | #define TYPE_XLNX_VERSAL "xlnx-versal" | 20 | uint32_t pressed_keys; |
| 27 | #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) | 21 | qemu_irq out[8]; |
| 28 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | 22 | @@ -XXX,XX +XXX,XX @@ static void musicpal_key_init(Object *obj) |
| 29 | struct { | 23 | DeviceState *dev = DEVICE(sbd); |
| 30 | SDHCIState sd[XLNX_VERSAL_NR_SDS]; | 24 | musicpal_key_state *s = MUSICPAL_KEY(dev); |
| 31 | } iou; | 25 | |
| 32 | + | 26 | - memory_region_init(&s->iomem, obj, "dummy", 0); |
| 33 | + XlnxZynqMPRTC rtc; | 27 | - sysbus_init_mmio(sbd, &s->iomem); |
| 34 | } pmc; | 28 | - |
| 35 | 29 | s->kbd_extended = 0; | |
| 36 | struct { | 30 | s->pressed_keys = 0; |
| 37 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | ||
| 38 | #define VERSAL_GEM1_IRQ_0 58 | ||
| 39 | #define VERSAL_GEM1_WAKE_IRQ_0 59 | ||
| 40 | #define VERSAL_ADMA_IRQ_0 60 | ||
| 41 | +#define VERSAL_RTC_APB_ERR_IRQ 121 | ||
| 42 | #define VERSAL_SD0_IRQ_0 126 | ||
| 43 | +#define VERSAL_RTC_ALARM_IRQ 142 | ||
| 44 | +#define VERSAL_RTC_SECONDS_IRQ 143 | ||
| 45 | |||
| 46 | /* Architecturally reserved IRQs suitable for virtualization. */ | ||
| 47 | #define VERSAL_RSVD_IRQ_FIRST 111 | ||
| 48 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | ||
| 49 | #define MM_PMC_SD0_SIZE 0x10000 | ||
| 50 | #define MM_PMC_CRP 0xf1260000U | ||
| 51 | #define MM_PMC_CRP_SIZE 0x10000 | ||
| 52 | +#define MM_PMC_RTC 0xf12a0000 | ||
| 53 | +#define MM_PMC_RTC_SIZE 0x10000 | ||
| 54 | #endif | ||
| 55 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
| 56 | index XXXXXXX..XXXXXXX 100644 | ||
| 57 | --- a/hw/arm/xlnx-versal.c | ||
| 58 | +++ b/hw/arm/xlnx-versal.c | ||
| 59 | @@ -XXX,XX +XXX,XX @@ static void versal_create_sds(Versal *s, qemu_irq *pic) | ||
| 60 | } | ||
| 61 | } | ||
| 62 | |||
| 63 | +static void versal_create_rtc(Versal *s, qemu_irq *pic) | ||
| 64 | +{ | ||
| 65 | + SysBusDevice *sbd; | ||
| 66 | + MemoryRegion *mr; | ||
| 67 | + | ||
| 68 | + sysbus_init_child_obj(OBJECT(s), "rtc", &s->pmc.rtc, sizeof(s->pmc.rtc), | ||
| 69 | + TYPE_XLNX_ZYNQMP_RTC); | ||
| 70 | + sbd = SYS_BUS_DEVICE(&s->pmc.rtc); | ||
| 71 | + qdev_init_nofail(DEVICE(sbd)); | ||
| 72 | + | ||
| 73 | + mr = sysbus_mmio_get_region(sbd, 0); | ||
| 74 | + memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr); | ||
| 75 | + | ||
| 76 | + /* | ||
| 77 | + * TODO: Connect the ALARM and SECONDS interrupts once our RTC model | ||
| 78 | + * supports them. | ||
| 79 | + */ | ||
| 80 | + sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]); | ||
| 81 | +} | ||
| 82 | + | ||
| 83 | /* This takes the board allocated linear DDR memory and creates aliases | ||
| 84 | * for each split DDR range/aperture on the Versal address map. | ||
| 85 | */ | ||
| 86 | @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) | ||
| 87 | versal_create_gems(s, pic); | ||
| 88 | versal_create_admas(s, pic); | ||
| 89 | versal_create_sds(s, pic); | ||
| 90 | + versal_create_rtc(s, pic); | ||
| 91 | versal_map_ddr(s); | ||
| 92 | versal_unimp(s); | ||
| 93 | 31 | ||
| 94 | -- | 32 | -- |
| 95 | 2.20.1 | 33 | 2.34.1 |
| 96 | 34 | ||
| 97 | 35 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Embed the UARTs into the SoC type. | 3 | Since commit be8d853766 ("iothread: add I/O thread object") we |
| 4 | never used IOThreadClass / IOTHREAD_CLASS() / IOTHREAD_GET_CLASS(), | ||
| 5 | remove these definitions. | ||
| 4 | 6 | ||
| 5 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 8 | Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> |
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | Message-id: 20230113200138.52869-2-philmd@linaro.org |
| 9 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
| 10 | Message-id: 20200427181649.26851-5-edgar.iglesias@gmail.com | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | --- | 12 | --- |
| 13 | include/hw/arm/xlnx-versal.h | 3 ++- | 13 | iothread.c | 4 ---- |
| 14 | hw/arm/xlnx-versal.c | 12 ++++++------ | 14 | 1 file changed, 4 deletions(-) |
| 15 | 2 files changed, 8 insertions(+), 7 deletions(-) | ||
| 16 | 15 | ||
| 17 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 16 | diff --git a/iothread.c b/iothread.c |
| 18 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
| 19 | --- a/include/hw/arm/xlnx-versal.h | 18 | --- a/iothread.c |
| 20 | +++ b/include/hw/arm/xlnx-versal.h | 19 | +++ b/iothread.c |
| 21 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ |
| 22 | #include "hw/sysbus.h" | 21 | #include "qemu/rcu.h" |
| 23 | #include "hw/arm/boot.h" | 22 | #include "qemu/main-loop.h" |
| 24 | #include "hw/intc/arm_gicv3.h" | 23 | |
| 25 | +#include "hw/char/pl011.h" | 24 | -typedef ObjectClass IOThreadClass; |
| 26 | 25 | - | |
| 27 | #define TYPE_XLNX_VERSAL "xlnx-versal" | 26 | -DECLARE_CLASS_CHECKERS(IOThreadClass, IOTHREAD, |
| 28 | #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) | 27 | - TYPE_IOTHREAD) |
| 29 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | 28 | |
| 30 | MemoryRegion mr_ocm; | 29 | #ifdef CONFIG_POSIX |
| 31 | 30 | /* Benchmark results from 2016 on NVMe SSD drives show max polling times around | |
| 32 | struct { | ||
| 33 | - SysBusDevice *uart[XLNX_VERSAL_NR_UARTS]; | ||
| 34 | + PL011State uart[XLNX_VERSAL_NR_UARTS]; | ||
| 35 | SysBusDevice *gem[XLNX_VERSAL_NR_GEMS]; | ||
| 36 | SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS]; | ||
| 37 | } iou; | ||
| 38 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
| 39 | index XXXXXXX..XXXXXXX 100644 | ||
| 40 | --- a/hw/arm/xlnx-versal.c | ||
| 41 | +++ b/hw/arm/xlnx-versal.c | ||
| 42 | @@ -XXX,XX +XXX,XX @@ | ||
| 43 | #include "kvm_arm.h" | ||
| 44 | #include "hw/misc/unimp.h" | ||
| 45 | #include "hw/arm/xlnx-versal.h" | ||
| 46 | -#include "hw/char/pl011.h" | ||
| 47 | |||
| 48 | #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") | ||
| 49 | #define GEM_REVISION 0x40070106 | ||
| 50 | @@ -XXX,XX +XXX,XX @@ static void versal_create_uarts(Versal *s, qemu_irq *pic) | ||
| 51 | DeviceState *dev; | ||
| 52 | MemoryRegion *mr; | ||
| 53 | |||
| 54 | - dev = qdev_create(NULL, TYPE_PL011); | ||
| 55 | - s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev); | ||
| 56 | + sysbus_init_child_obj(OBJECT(s), name, | ||
| 57 | + &s->lpd.iou.uart[i], sizeof(s->lpd.iou.uart[i]), | ||
| 58 | + TYPE_PL011); | ||
| 59 | + dev = DEVICE(&s->lpd.iou.uart[i]); | ||
| 60 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); | ||
| 61 | - object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal); | ||
| 62 | qdev_init_nofail(dev); | ||
| 63 | |||
| 64 | - mr = sysbus_mmio_get_region(s->lpd.iou.uart[i], 0); | ||
| 65 | + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); | ||
| 66 | memory_region_add_subregion(&s->mr_ps, addrs[i], mr); | ||
| 67 | |||
| 68 | - sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]); | ||
| 69 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]); | ||
| 70 | g_free(name); | ||
| 71 | } | ||
| 72 | } | ||
| 73 | -- | 31 | -- |
| 74 | 2.20.1 | 32 | 2.34.1 |
| 75 | 33 | ||
| 76 | 34 | diff view generated by jsdifflib |
| 1 | From: Fredrik Strupe <fredrik@strupe.net> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | According to Arm ARM, VQDMULL is only valid when U=0, while having | 3 | QOM *DECLARE* macros expect a typedef as first argument, |
| 4 | U=1 is unallocated. | 4 | not a structure. Replace 'struct IRQState' by 'IRQState' |
| 5 | to avoid when modifying the macros: | ||
| 5 | 6 | ||
| 6 | Signed-off-by: Fredrik Strupe <fredrik@strupe.net> | 7 | ../hw/core/irq.c:29:1: error: declaration of anonymous struct must be a definition |
| 7 | Fixes: 695272dcb976 ("target-arm: Handle UNDEF cases for Neon 3-regs-different-widths") | 8 | DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ, |
| 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | ^ |
| 10 | |||
| 11 | Use OBJECT_DECLARE_SIMPLE_TYPE instead of DECLARE_INSTANCE_CHECKER. | ||
| 12 | |||
| 13 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 14 | Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
| 15 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 16 | Message-id: 20230113200138.52869-3-philmd@linaro.org | ||
| 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 10 | --- | 18 | --- |
| 11 | target/arm/translate.c | 2 +- | 19 | hw/core/irq.c | 9 ++++----- |
| 12 | 1 file changed, 1 insertion(+), 1 deletion(-) | 20 | 1 file changed, 4 insertions(+), 5 deletions(-) |
| 13 | 21 | ||
| 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 22 | diff --git a/hw/core/irq.c b/hw/core/irq.c |
| 15 | index XXXXXXX..XXXXXXX 100644 | 23 | index XXXXXXX..XXXXXXX 100644 |
| 16 | --- a/target/arm/translate.c | 24 | --- a/hw/core/irq.c |
| 17 | +++ b/target/arm/translate.c | 25 | +++ b/hw/core/irq.c |
| 18 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 26 | @@ -XXX,XX +XXX,XX @@ |
| 19 | {0, 0, 0, 0}, /* VMLSL */ | 27 | #include "hw/irq.h" |
| 20 | {0, 0, 0, 9}, /* VQDMLSL */ | 28 | #include "qom/object.h" |
| 21 | {0, 0, 0, 0}, /* Integer VMULL */ | 29 | |
| 22 | - {0, 0, 0, 1}, /* VQDMULL */ | 30 | -DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ, |
| 23 | + {0, 0, 0, 9}, /* VQDMULL */ | 31 | - TYPE_IRQ) |
| 24 | {0, 0, 0, 0xa}, /* Polynomial VMULL */ | 32 | +OBJECT_DECLARE_SIMPLE_TYPE(IRQState, IRQ) |
| 25 | {0, 0, 0, 7}, /* Reserved: always UNDEF */ | 33 | |
| 26 | }; | 34 | struct IRQState { |
| 35 | Object parent_obj; | ||
| 36 | @@ -XXX,XX +XXX,XX @@ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n) | ||
| 37 | |||
| 38 | qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n) | ||
| 39 | { | ||
| 40 | - struct IRQState *irq; | ||
| 41 | + IRQState *irq; | ||
| 42 | |||
| 43 | irq = IRQ(object_new(TYPE_IRQ)); | ||
| 44 | irq->handler = handler; | ||
| 45 | @@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq) | ||
| 46 | |||
| 47 | static void qemu_notirq(void *opaque, int line, int level) | ||
| 48 | { | ||
| 49 | - struct IRQState *irq = opaque; | ||
| 50 | + IRQState *irq = opaque; | ||
| 51 | |||
| 52 | irq->handler(irq->opaque, irq->n, !level); | ||
| 53 | } | ||
| 54 | @@ -XXX,XX +XXX,XX @@ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n) | ||
| 55 | static const TypeInfo irq_type_info = { | ||
| 56 | .name = TYPE_IRQ, | ||
| 57 | .parent = TYPE_OBJECT, | ||
| 58 | - .instance_size = sizeof(struct IRQState), | ||
| 59 | + .instance_size = sizeof(IRQState), | ||
| 60 | }; | ||
| 61 | |||
| 62 | static void irq_register_types(void) | ||
| 27 | -- | 63 | -- |
| 28 | 2.20.1 | 64 | 2.34.1 |
| 29 | 65 | ||
| 30 | 66 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU | ||
| 2 | TLB. However we never actually use the TLB -- all stage 2 lookups | ||
| 3 | are done by direct calls to get_phys_addr_lpae() followed by a | ||
| 4 | physical address load via address_space_ld*(). | ||
| 5 | 1 | ||
| 6 | Remove Stage2 from the list of ARM MMU indexes which correspond to | ||
| 7 | real core MMU indexes, and instead put it in the set of "NOTLB" ARM | ||
| 8 | MMU indexes. | ||
| 9 | |||
| 10 | This allows us to drop NB_MMU_MODES to 11. It also means we can | ||
| 11 | safely add support for the ARMv8.3-TTS2UXN extension, which adds | ||
| 12 | permission bits to the stage 2 descriptors which define execute | ||
| 13 | permission separatel for EL0 and EL1; supporting that while keeping | ||
| 14 | Stage2 in a QEMU TLB would require us to use separate TLBs for | ||
| 15 | "Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a | ||
| 16 | lot of extra complication given we aren't even using the QEMU TLB. | ||
| 17 | |||
| 18 | In the process of updating the comment on our MMU index use, | ||
| 19 | fix a couple of other minor errors: | ||
| 20 | * NS EL2 EL2&0 was missing from the list in the comment | ||
| 21 | * some text hadn't been updated from when we bumped NB_MMU_MODES | ||
| 22 | above 8 | ||
| 23 | |||
| 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 25 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 26 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 27 | Message-id: 20200330210400.11724-2-peter.maydell@linaro.org | ||
| 28 | --- | ||
| 29 | target/arm/cpu-param.h | 2 +- | ||
| 30 | target/arm/cpu.h | 21 +++++--- | ||
| 31 | target/arm/helper.c | 112 ++++------------------------------------- | ||
| 32 | 3 files changed, 27 insertions(+), 108 deletions(-) | ||
| 33 | |||
| 34 | diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h | ||
| 35 | index XXXXXXX..XXXXXXX 100644 | ||
| 36 | --- a/target/arm/cpu-param.h | ||
| 37 | +++ b/target/arm/cpu-param.h | ||
| 38 | @@ -XXX,XX +XXX,XX @@ | ||
| 39 | # define TARGET_PAGE_BITS_MIN 10 | ||
| 40 | #endif | ||
| 41 | |||
| 42 | -#define NB_MMU_MODES 12 | ||
| 43 | +#define NB_MMU_MODES 11 | ||
| 44 | |||
| 45 | #endif | ||
| 46 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
| 47 | index XXXXXXX..XXXXXXX 100644 | ||
| 48 | --- a/target/arm/cpu.h | ||
| 49 | +++ b/target/arm/cpu.h | ||
| 50 | @@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); | ||
| 51 | * handling via the TLB. The only way to do a stage 1 translation without | ||
| 52 | * the immediate stage 2 translation is via the ATS or AT system insns, | ||
| 53 | * which can be slow-pathed and always do a page table walk. | ||
| 54 | + * The only use of stage 2 translations is either as part of an s1+2 | ||
| 55 | + * lookup or when loading the descriptors during a stage 1 page table walk, | ||
| 56 | + * and in both those cases we don't use the TLB. | ||
| 57 | * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" | ||
| 58 | * translation regimes, because they map reasonably well to each other | ||
| 59 | * and they can't both be active at the same time. | ||
| 60 | @@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); | ||
| 61 | * NS EL1 EL1&0 stage 1+2 (aka NS PL1) | ||
| 62 | * NS EL1 EL1&0 stage 1+2 +PAN | ||
| 63 | * NS EL0 EL2&0 | ||
| 64 | + * NS EL2 EL2&0 | ||
| 65 | * NS EL2 EL2&0 +PAN | ||
| 66 | * NS EL2 (aka NS PL2) | ||
| 67 | * S EL0 EL1&0 (aka S PL0) | ||
| 68 | * S EL1 EL1&0 (not used if EL3 is 32 bit) | ||
| 69 | * S EL1 EL1&0 +PAN | ||
| 70 | * S EL3 (aka S PL1) | ||
| 71 | - * NS EL1&0 stage 2 | ||
| 72 | * | ||
| 73 | - * for a total of 12 different mmu_idx. | ||
| 74 | + * for a total of 11 different mmu_idx. | ||
| 75 | * | ||
| 76 | * R profile CPUs have an MPU, but can use the same set of MMU indexes | ||
| 77 | * as A profile. They only need to distinguish NS EL0 and NS EL1 (and | ||
| 78 | @@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); | ||
| 79 | * are not quite the same -- different CPU types (most notably M profile | ||
| 80 | * vs A/R profile) would like to use MMU indexes with different semantics, | ||
| 81 | * but since we don't ever need to use all of those in a single CPU we | ||
| 82 | - * can avoid setting NB_MMU_MODES to more than 8. The lower bits of | ||
| 83 | + * can avoid having to set NB_MMU_MODES to "total number of A profile MMU | ||
| 84 | + * modes + total number of M profile MMU modes". The lower bits of | ||
| 85 | * ARMMMUIdx are the core TLB mmu index, and the higher bits are always | ||
| 86 | * the same for any particular CPU. | ||
| 87 | * Variables of type ARMMUIdx are always full values, and the core | ||
| 88 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx { | ||
| 89 | ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A, | ||
| 90 | ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A, | ||
| 91 | |||
| 92 | - ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A, | ||
| 93 | - | ||
| 94 | /* | ||
| 95 | * These are not allocated TLBs and are used only for AT system | ||
| 96 | * instructions or for the first stage of an S12 page table walk. | ||
| 97 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx { | ||
| 98 | ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, | ||
| 99 | ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, | ||
| 100 | ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, | ||
| 101 | + /* | ||
| 102 | + * Not allocated a TLB: used only for second stage of an S12 page | ||
| 103 | + * table walk, or for descriptor loads during first stage of an S1 | ||
| 104 | + * page table walk. Note that if we ever want to have a TLB for this | ||
| 105 | + * then various TLB flush insns which currently are no-ops or flush | ||
| 106 | + * only stage 1 MMU indexes will need to change to flush stage 2. | ||
| 107 | + */ | ||
| 108 | + ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB, | ||
| 109 | |||
| 110 | /* | ||
| 111 | * M-profile. | ||
| 112 | @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit { | ||
| 113 | TO_CORE_BIT(SE10_1), | ||
| 114 | TO_CORE_BIT(SE10_1_PAN), | ||
| 115 | TO_CORE_BIT(SE3), | ||
| 116 | - TO_CORE_BIT(Stage2), | ||
| 117 | |||
| 118 | TO_CORE_BIT(MUser), | ||
| 119 | TO_CORE_BIT(MPriv), | ||
| 120 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 121 | index XXXXXXX..XXXXXXX 100644 | ||
| 122 | --- a/target/arm/helper.c | ||
| 123 | +++ b/target/arm/helper.c | ||
| 124 | @@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 125 | tlb_flush_by_mmuidx(cs, | ||
| 126 | ARMMMUIdxBit_E10_1 | | ||
| 127 | ARMMMUIdxBit_E10_1_PAN | | ||
| 128 | - ARMMMUIdxBit_E10_0 | | ||
| 129 | - ARMMMUIdxBit_Stage2); | ||
| 130 | + ARMMMUIdxBit_E10_0); | ||
| 131 | } | ||
| 132 | |||
| 133 | static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 134 | @@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 135 | tlb_flush_by_mmuidx_all_cpus_synced(cs, | ||
| 136 | ARMMMUIdxBit_E10_1 | | ||
| 137 | ARMMMUIdxBit_E10_1_PAN | | ||
| 138 | - ARMMMUIdxBit_E10_0 | | ||
| 139 | - ARMMMUIdxBit_Stage2); | ||
| 140 | + ARMMMUIdxBit_E10_0); | ||
| 141 | } | ||
| 142 | |||
| 143 | -static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 144 | - uint64_t value) | ||
| 145 | -{ | ||
| 146 | - /* Invalidate by IPA. This has to invalidate any structures that | ||
| 147 | - * contain only stage 2 translation information, but does not need | ||
| 148 | - * to apply to structures that contain combined stage 1 and stage 2 | ||
| 149 | - * translation information. | ||
| 150 | - * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | ||
| 151 | - */ | ||
| 152 | - CPUState *cs = env_cpu(env); | ||
| 153 | - uint64_t pageaddr; | ||
| 154 | - | ||
| 155 | - if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | ||
| 156 | - return; | ||
| 157 | - } | ||
| 158 | - | ||
| 159 | - pageaddr = sextract64(value << 12, 0, 40); | ||
| 160 | - | ||
| 161 | - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); | ||
| 162 | -} | ||
| 163 | - | ||
| 164 | -static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 165 | - uint64_t value) | ||
| 166 | -{ | ||
| 167 | - CPUState *cs = env_cpu(env); | ||
| 168 | - uint64_t pageaddr; | ||
| 169 | - | ||
| 170 | - if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | ||
| 171 | - return; | ||
| 172 | - } | ||
| 173 | - | ||
| 174 | - pageaddr = sextract64(value << 12, 0, 40); | ||
| 175 | - | ||
| 176 | - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | ||
| 177 | - ARMMMUIdxBit_Stage2); | ||
| 178 | -} | ||
| 179 | |||
| 180 | static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 181 | uint64_t value) | ||
| 182 | @@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 183 | tlb_flush_by_mmuidx(cs, | ||
| 184 | ARMMMUIdxBit_E10_1 | | ||
| 185 | ARMMMUIdxBit_E10_1_PAN | | ||
| 186 | - ARMMMUIdxBit_E10_0 | | ||
| 187 | - ARMMMUIdxBit_Stage2); | ||
| 188 | + ARMMMUIdxBit_E10_0); | ||
| 189 | raw_write(env, ri, value); | ||
| 190 | } | ||
| 191 | } | ||
| 192 | @@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env) | ||
| 193 | return ARMMMUIdxBit_SE10_1 | | ||
| 194 | ARMMMUIdxBit_SE10_1_PAN | | ||
| 195 | ARMMMUIdxBit_SE10_0; | ||
| 196 | - } else if (arm_feature(env, ARM_FEATURE_EL2)) { | ||
| 197 | - return ARMMMUIdxBit_E10_1 | | ||
| 198 | - ARMMMUIdxBit_E10_1_PAN | | ||
| 199 | - ARMMMUIdxBit_E10_0 | | ||
| 200 | - ARMMMUIdxBit_Stage2; | ||
| 201 | } else { | ||
| 202 | return ARMMMUIdxBit_E10_1 | | ||
| 203 | ARMMMUIdxBit_E10_1_PAN | | ||
| 204 | @@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 205 | ARMMMUIdxBit_SE3); | ||
| 206 | } | ||
| 207 | |||
| 208 | -static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 209 | - uint64_t value) | ||
| 210 | -{ | ||
| 211 | - /* Invalidate by IPA. This has to invalidate any structures that | ||
| 212 | - * contain only stage 2 translation information, but does not need | ||
| 213 | - * to apply to structures that contain combined stage 1 and stage 2 | ||
| 214 | - * translation information. | ||
| 215 | - * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero. | ||
| 216 | - */ | ||
| 217 | - ARMCPU *cpu = env_archcpu(env); | ||
| 218 | - CPUState *cs = CPU(cpu); | ||
| 219 | - uint64_t pageaddr; | ||
| 220 | - | ||
| 221 | - if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | ||
| 222 | - return; | ||
| 223 | - } | ||
| 224 | - | ||
| 225 | - pageaddr = sextract64(value << 12, 0, 48); | ||
| 226 | - | ||
| 227 | - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2); | ||
| 228 | -} | ||
| 229 | - | ||
| 230 | -static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 231 | - uint64_t value) | ||
| 232 | -{ | ||
| 233 | - CPUState *cs = env_cpu(env); | ||
| 234 | - uint64_t pageaddr; | ||
| 235 | - | ||
| 236 | - if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) { | ||
| 237 | - return; | ||
| 238 | - } | ||
| 239 | - | ||
| 240 | - pageaddr = sextract64(value << 12, 0, 48); | ||
| 241 | - | ||
| 242 | - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, | ||
| 243 | - ARMMMUIdxBit_Stage2); | ||
| 244 | -} | ||
| 245 | - | ||
| 246 | static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, | ||
| 247 | bool isread) | ||
| 248 | { | ||
| 249 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
| 250 | .writefn = tlbi_aa64_vae1_write }, | ||
| 251 | { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64, | ||
| 252 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | ||
| 253 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 254 | - .writefn = tlbi_aa64_ipas2e1is_write }, | ||
| 255 | + .access = PL2_W, .type = ARM_CP_NOP }, | ||
| 256 | { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64, | ||
| 257 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | ||
| 258 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 259 | - .writefn = tlbi_aa64_ipas2e1is_write }, | ||
| 260 | + .access = PL2_W, .type = ARM_CP_NOP }, | ||
| 261 | { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64, | ||
| 262 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4, | ||
| 263 | .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 264 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
| 265 | .writefn = tlbi_aa64_alle1is_write }, | ||
| 266 | { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64, | ||
| 267 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | ||
| 268 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 269 | - .writefn = tlbi_aa64_ipas2e1_write }, | ||
| 270 | + .access = PL2_W, .type = ARM_CP_NOP }, | ||
| 271 | { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64, | ||
| 272 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | ||
| 273 | - .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 274 | - .writefn = tlbi_aa64_ipas2e1_write }, | ||
| 275 | + .access = PL2_W, .type = ARM_CP_NOP }, | ||
| 276 | { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64, | ||
| 277 | .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4, | ||
| 278 | .access = PL2_W, .type = ARM_CP_NO_RAW, | ||
| 279 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = { | ||
| 280 | .writefn = tlbimva_hyp_is_write }, | ||
| 281 | { .name = "TLBIIPAS2", | ||
| 282 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1, | ||
| 283 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
| 284 | - .writefn = tlbiipas2_write }, | ||
| 285 | + .type = ARM_CP_NOP, .access = PL2_W }, | ||
| 286 | { .name = "TLBIIPAS2IS", | ||
| 287 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1, | ||
| 288 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
| 289 | - .writefn = tlbiipas2_is_write }, | ||
| 290 | + .type = ARM_CP_NOP, .access = PL2_W }, | ||
| 291 | { .name = "TLBIIPAS2L", | ||
| 292 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5, | ||
| 293 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
| 294 | - .writefn = tlbiipas2_write }, | ||
| 295 | + .type = ARM_CP_NOP, .access = PL2_W }, | ||
| 296 | { .name = "TLBIIPAS2LIS", | ||
| 297 | .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5, | ||
| 298 | - .type = ARM_CP_NO_RAW, .access = PL2_W, | ||
| 299 | - .writefn = tlbiipas2_is_write }, | ||
| 300 | + .type = ARM_CP_NOP, .access = PL2_W }, | ||
| 301 | /* 32 bit cache operations */ | ||
| 302 | { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, | ||
| 303 | .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access }, | ||
| 304 | -- | ||
| 305 | 2.20.1 | ||
| 306 | |||
| 307 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | The access_type argument to get_phys_addr_lpae() is an MMUAccessType; | ||
| 2 | use the enum constant MMU_DATA_LOAD rather than a literal 0 when we | ||
| 3 | call it in S1_ptw_translate(). | ||
| 4 | 1 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 8 | Message-id: 20200330210400.11724-3-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/arm/helper.c | 5 +++-- | ||
| 11 | 1 file changed, 3 insertions(+), 2 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/helper.c | ||
| 16 | +++ b/target/arm/helper.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | ||
| 18 | pcacheattrs = &cacheattrs; | ||
| 19 | } | ||
| 20 | |||
| 21 | - ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa, | ||
| 22 | - &txattrs, &s2prot, &s2size, fi, pcacheattrs); | ||
| 23 | + ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2, | ||
| 24 | + &s2pa, &txattrs, &s2prot, &s2size, fi, | ||
| 25 | + pcacheattrs); | ||
| 26 | if (ret) { | ||
| 27 | assert(fi->type != ARMFault_None); | ||
| 28 | fi->s2addr = addr; | ||
| 29 | -- | ||
| 30 | 2.20.1 | ||
| 31 | |||
| 32 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know | ||
| 2 | whether the stage 1 access is for EL0 or not, because whether | ||
| 3 | exec permission is given can depend on whether this is an EL0 | ||
| 4 | or EL1 access. Add a new argument to get_phys_addr_lpae() so | ||
| 5 | the call sites can pass this information in. | ||
| 6 | 1 | ||
| 7 | Since get_phys_addr_lpae() doesn't already have a doc comment, | ||
| 8 | add one so we have a place to put the documentation of the | ||
| 9 | semantics of the new s1_is_el0 argument. | ||
| 10 | |||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 12 | Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | ||
| 13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 14 | Message-id: 20200330210400.11724-4-peter.maydell@linaro.org | ||
| 15 | --- | ||
| 16 | target/arm/helper.c | 29 ++++++++++++++++++++++++++++- | ||
| 17 | 1 file changed, 28 insertions(+), 1 deletion(-) | ||
| 18 | |||
| 19 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/target/arm/helper.c | ||
| 22 | +++ b/target/arm/helper.c | ||
| 23 | @@ -XXX,XX +XXX,XX @@ | ||
| 24 | |||
| 25 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | ||
| 26 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | ||
| 27 | + bool s1_is_el0, | ||
| 28 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, | ||
| 29 | target_ulong *page_size_ptr, | ||
| 30 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); | ||
| 31 | @@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, | ||
| 32 | } | ||
| 33 | |||
| 34 | ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2, | ||
| 35 | + false, | ||
| 36 | &s2pa, &txattrs, &s2prot, &s2size, fi, | ||
| 37 | pcacheattrs); | ||
| 38 | if (ret) { | ||
| 39 | @@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, | ||
| 40 | }; | ||
| 41 | } | ||
| 42 | |||
| 43 | +/** | ||
| 44 | + * get_phys_addr_lpae: perform one stage of page table walk, LPAE format | ||
| 45 | + * | ||
| 46 | + * Returns false if the translation was successful. Otherwise, phys_ptr, attrs, | ||
| 47 | + * prot and page_size may not be filled in, and the populated fsr value provides | ||
| 48 | + * information on why the translation aborted, in the format of a long-format | ||
| 49 | + * DFSR/IFSR fault register, with the following caveats: | ||
| 50 | + * * the WnR bit is never set (the caller must do this). | ||
| 51 | + * | ||
| 52 | + * @env: CPUARMState | ||
| 53 | + * @address: virtual address to get physical address for | ||
| 54 | + * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH | ||
| 55 | + * @mmu_idx: MMU index indicating required translation regime | ||
| 56 | + * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table | ||
| 57 | + * walk), must be true if this is stage 2 of a stage 1+2 walk for an | ||
| 58 | + * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored. | ||
| 59 | + * @phys_ptr: set to the physical address corresponding to the virtual address | ||
| 60 | + * @attrs: set to the memory transaction attributes to use | ||
| 61 | + * @prot: set to the permissions for the page containing phys_ptr | ||
| 62 | + * @page_size_ptr: set to the size of the page containing phys_ptr | ||
| 63 | + * @fi: set to fault info if the translation fails | ||
| 64 | + * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes | ||
| 65 | + */ | ||
| 66 | static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | ||
| 67 | MMUAccessType access_type, ARMMMUIdx mmu_idx, | ||
| 68 | + bool s1_is_el0, | ||
| 69 | hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot, | ||
| 70 | target_ulong *page_size_ptr, | ||
| 71 | ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) | ||
| 72 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, | ||
| 73 | |||
| 74 | /* S1 is done. Now do S2 translation. */ | ||
| 75 | ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2, | ||
| 76 | + mmu_idx == ARMMMUIdx_E10_0, | ||
| 77 | phys_ptr, attrs, &s2_prot, | ||
| 78 | page_size, fi, | ||
| 79 | cacheattrs != NULL ? &cacheattrs2 : NULL); | ||
| 80 | @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, | ||
| 81 | } | ||
| 82 | |||
| 83 | if (regime_using_lpae_format(env, mmu_idx)) { | ||
| 84 | - return get_phys_addr_lpae(env, address, access_type, mmu_idx, | ||
| 85 | + return get_phys_addr_lpae(env, address, access_type, mmu_idx, false, | ||
| 86 | phys_ptr, attrs, prot, page_size, | ||
| 87 | fi, cacheattrs); | ||
| 88 | } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { | ||
| 89 | -- | ||
| 90 | 2.20.1 | ||
| 91 | |||
| 92 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | In aarch64_max_initfn() we update both 32-bit and 64-bit ID | ||
| 2 | registers. The intended pattern is that for 64-bit ID registers we | ||
| 3 | use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID | ||
| 4 | registers use FIELD_DP32 and the uint32_t 'u' register. For | ||
| 5 | ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of | ||
| 6 | this 64-bit ID register would end up always zero. Luckily at the | ||
| 7 | moment that's what they should be anyway, so this bug has no visible | ||
| 8 | effects. | ||
| 9 | 1 | ||
| 10 | Use the right-sized variable. | ||
| 11 | |||
| 12 | Fixes: 3bec78447a958d481991 | ||
| 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 14 | Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
| 15 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 16 | Message-id: 20200423110915.10527-1-peter.maydell@linaro.org | ||
| 17 | --- | ||
| 18 | target/arm/cpu64.c | 6 +++--- | ||
| 19 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
| 20 | |||
| 21 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
| 22 | index XXXXXXX..XXXXXXX 100644 | ||
| 23 | --- a/target/arm/cpu64.c | ||
| 24 | +++ b/target/arm/cpu64.c | ||
| 25 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
| 26 | u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ | ||
| 27 | cpu->isar.id_mmfr4 = u; | ||
| 28 | |||
| 29 | - u = cpu->isar.id_aa64dfr0; | ||
| 30 | - u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | ||
| 31 | - cpu->isar.id_aa64dfr0 = u; | ||
| 32 | + t = cpu->isar.id_aa64dfr0; | ||
| 33 | + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ | ||
| 34 | + cpu->isar.id_aa64dfr0 = t; | ||
| 35 | |||
| 36 | u = cpu->isar.id_dfr0; | ||
| 37 | u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ | ||
| 38 | -- | ||
| 39 | 2.20.1 | ||
| 40 | |||
| 41 | diff view generated by jsdifflib |
| 1 | Convert the Neon "load single structure to all lanes" insns to | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | decodetree. | ||
| 3 | 2 | ||
| 3 | Missed during automatic conversion from commit 8063396bf3 | ||
| 4 | ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). | ||
| 5 | |||
| 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 7 | Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
| 8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
| 9 | Message-id: 20230113200138.52869-4-philmd@linaro.org | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20200430181003.21682-13-peter.maydell@linaro.org | ||
| 7 | --- | 11 | --- |
| 8 | target/arm/neon-ls.decode | 5 +++ | 12 | include/hw/or-irq.h | 3 +-- |
| 9 | target/arm/translate-neon.inc.c | 73 +++++++++++++++++++++++++++++++++ | 13 | 1 file changed, 1 insertion(+), 2 deletions(-) |
| 10 | target/arm/translate.c | 55 +------------------------ | ||
| 11 | 3 files changed, 80 insertions(+), 53 deletions(-) | ||
| 12 | 14 | ||
| 13 | diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode | 15 | diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h |
| 14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
| 15 | --- a/target/arm/neon-ls.decode | 17 | --- a/include/hw/or-irq.h |
| 16 | +++ b/target/arm/neon-ls.decode | 18 | +++ b/include/hw/or-irq.h |
| 17 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ |
| 18 | 20 | ||
| 19 | VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \ | 21 | typedef struct OrIRQState qemu_or_irq; |
| 20 | vd=%vd_dp | 22 | |
| 21 | + | 23 | -DECLARE_INSTANCE_CHECKER(qemu_or_irq, OR_IRQ, |
| 22 | +# Neon load single element to all lanes | 24 | - TYPE_OR_IRQ) |
| 23 | + | 25 | +OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ) |
| 24 | +VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \ | 26 | |
| 25 | + vd=%vd_dp | 27 | struct OrIRQState { |
| 26 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | 28 | DeviceState parent_obj; |
| 27 | index XXXXXXX..XXXXXXX 100644 | ||
| 28 | --- a/target/arm/translate-neon.inc.c | ||
| 29 | +++ b/target/arm/translate-neon.inc.c | ||
| 30 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a) | ||
| 31 | gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8); | ||
| 32 | return true; | ||
| 33 | } | ||
| 34 | + | ||
| 35 | +static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a) | ||
| 36 | +{ | ||
| 37 | + /* Neon load single structure to all lanes */ | ||
| 38 | + int reg, stride, vec_size; | ||
| 39 | + int vd = a->vd; | ||
| 40 | + int size = a->size; | ||
| 41 | + int nregs = a->n + 1; | ||
| 42 | + TCGv_i32 addr, tmp; | ||
| 43 | + | ||
| 44 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
| 45 | + return false; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + /* UNDEF accesses to D16-D31 if they don't exist */ | ||
| 49 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | ||
| 50 | + return false; | ||
| 51 | + } | ||
| 52 | + | ||
| 53 | + if (size == 3) { | ||
| 54 | + if (nregs != 4 || a->a == 0) { | ||
| 55 | + return false; | ||
| 56 | + } | ||
| 57 | + /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */ | ||
| 58 | + size = 2; | ||
| 59 | + } | ||
| 60 | + if (nregs == 1 && a->a == 1 && size == 0) { | ||
| 61 | + return false; | ||
| 62 | + } | ||
| 63 | + if (nregs == 3 && a->a == 1) { | ||
| 64 | + return false; | ||
| 65 | + } | ||
| 66 | + | ||
| 67 | + if (!vfp_access_check(s)) { | ||
| 68 | + return true; | ||
| 69 | + } | ||
| 70 | + | ||
| 71 | + /* | ||
| 72 | + * VLD1 to all lanes: T bit indicates how many Dregs to write. | ||
| 73 | + * VLD2/3/4 to all lanes: T bit indicates register stride. | ||
| 74 | + */ | ||
| 75 | + stride = a->t ? 2 : 1; | ||
| 76 | + vec_size = nregs == 1 ? stride * 8 : 8; | ||
| 77 | + | ||
| 78 | + tmp = tcg_temp_new_i32(); | ||
| 79 | + addr = tcg_temp_new_i32(); | ||
| 80 | + load_reg_var(s, addr, a->rn); | ||
| 81 | + for (reg = 0; reg < nregs; reg++) { | ||
| 82 | + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), | ||
| 83 | + s->be_data | size); | ||
| 84 | + if ((vd & 1) && vec_size == 16) { | ||
| 85 | + /* | ||
| 86 | + * We cannot write 16 bytes at once because the | ||
| 87 | + * destination is unaligned. | ||
| 88 | + */ | ||
| 89 | + tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), | ||
| 90 | + 8, 8, tmp); | ||
| 91 | + tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0), | ||
| 92 | + neon_reg_offset(vd, 0), 8, 8); | ||
| 93 | + } else { | ||
| 94 | + tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), | ||
| 95 | + vec_size, vec_size, tmp); | ||
| 96 | + } | ||
| 97 | + tcg_gen_addi_i32(addr, addr, 1 << size); | ||
| 98 | + vd += stride; | ||
| 99 | + } | ||
| 100 | + tcg_temp_free_i32(tmp); | ||
| 101 | + tcg_temp_free_i32(addr); | ||
| 102 | + | ||
| 103 | + gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << size) * nregs); | ||
| 104 | + | ||
| 105 | + return true; | ||
| 106 | +} | ||
| 107 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 108 | index XXXXXXX..XXXXXXX 100644 | ||
| 109 | --- a/target/arm/translate.c | ||
| 110 | +++ b/target/arm/translate.c | ||
| 111 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) | ||
| 112 | int size; | ||
| 113 | int reg; | ||
| 114 | int load; | ||
| 115 | - int vec_size; | ||
| 116 | TCGv_i32 addr; | ||
| 117 | TCGv_i32 tmp; | ||
| 118 | |||
| 119 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) | ||
| 120 | } else { | ||
| 121 | size = (insn >> 10) & 3; | ||
| 122 | if (size == 3) { | ||
| 123 | - /* Load single element to all lanes. */ | ||
| 124 | - int a = (insn >> 4) & 1; | ||
| 125 | - if (!load) { | ||
| 126 | - return 1; | ||
| 127 | - } | ||
| 128 | - size = (insn >> 6) & 3; | ||
| 129 | - nregs = ((insn >> 8) & 3) + 1; | ||
| 130 | - | ||
| 131 | - if (size == 3) { | ||
| 132 | - if (nregs != 4 || a == 0) { | ||
| 133 | - return 1; | ||
| 134 | - } | ||
| 135 | - /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */ | ||
| 136 | - size = 2; | ||
| 137 | - } | ||
| 138 | - if (nregs == 1 && a == 1 && size == 0) { | ||
| 139 | - return 1; | ||
| 140 | - } | ||
| 141 | - if (nregs == 3 && a == 1) { | ||
| 142 | - return 1; | ||
| 143 | - } | ||
| 144 | - addr = tcg_temp_new_i32(); | ||
| 145 | - load_reg_var(s, addr, rn); | ||
| 146 | - | ||
| 147 | - /* VLD1 to all lanes: bit 5 indicates how many Dregs to write. | ||
| 148 | - * VLD2/3/4 to all lanes: bit 5 indicates register stride. | ||
| 149 | - */ | ||
| 150 | - stride = (insn & (1 << 5)) ? 2 : 1; | ||
| 151 | - vec_size = nregs == 1 ? stride * 8 : 8; | ||
| 152 | - | ||
| 153 | - tmp = tcg_temp_new_i32(); | ||
| 154 | - for (reg = 0; reg < nregs; reg++) { | ||
| 155 | - gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), | ||
| 156 | - s->be_data | size); | ||
| 157 | - if ((rd & 1) && vec_size == 16) { | ||
| 158 | - /* We cannot write 16 bytes at once because the | ||
| 159 | - * destination is unaligned. | ||
| 160 | - */ | ||
| 161 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0), | ||
| 162 | - 8, 8, tmp); | ||
| 163 | - tcg_gen_gvec_mov(0, neon_reg_offset(rd + 1, 0), | ||
| 164 | - neon_reg_offset(rd, 0), 8, 8); | ||
| 165 | - } else { | ||
| 166 | - tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0), | ||
| 167 | - vec_size, vec_size, tmp); | ||
| 168 | - } | ||
| 169 | - tcg_gen_addi_i32(addr, addr, 1 << size); | ||
| 170 | - rd += stride; | ||
| 171 | - } | ||
| 172 | - tcg_temp_free_i32(tmp); | ||
| 173 | - tcg_temp_free_i32(addr); | ||
| 174 | - stride = (1 << size) * nregs; | ||
| 175 | + /* Load single element to all lanes -- handled by decodetree */ | ||
| 176 | + return 1; | ||
| 177 | } else { | ||
| 178 | /* Single element. */ | ||
| 179 | int idx = (insn >> 4) & 0xf; | ||
| 180 | -- | 29 | -- |
| 181 | 2.20.1 | 30 | 2.34.1 |
| 182 | 31 | ||
| 183 | 32 | diff view generated by jsdifflib |
| 1 | From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
|---|---|---|---|
| 2 | 2 | ||
| 3 | Embed the APUs into the SoC type. | 3 | OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState |
| 4 | 4 | declaration for free. Besides, the QOM code style is to use | |
| 5 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> | 5 | the structure name as typedef, and QEMU style is to use Camel |
| 6 | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 6 | Case, so rename qemu_or_irq as OrIRQState. |
| 7 | |||
| 8 | Mechanical change using: | ||
| 9 | |||
| 10 | $ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git grep -l qemu_or_irq) | ||
| 11 | |||
| 12 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
| 13 | Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
| 7 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 14 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> |
| 8 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 15 | Message-id: 20230113200138.52869-5-philmd@linaro.org |
| 9 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
| 10 | Message-id: 20200427181649.26851-8-edgar.iglesias@gmail.com | ||
| 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
| 12 | --- | 17 | --- |
| 13 | include/hw/arm/xlnx-versal.h | 2 +- | 18 | include/hw/arm/armsse.h | 6 +++--- |
| 14 | hw/arm/xlnx-versal-virt.c | 4 ++-- | 19 | include/hw/arm/bcm2835_peripherals.h | 2 +- |
| 15 | hw/arm/xlnx-versal.c | 19 +++++-------------- | 20 | include/hw/arm/exynos4210.h | 4 ++-- |
| 16 | 3 files changed, 8 insertions(+), 17 deletions(-) | 21 | include/hw/arm/stm32f205_soc.h | 2 +- |
| 17 | 22 | include/hw/arm/stm32f405_soc.h | 2 +- | |
| 23 | include/hw/arm/xlnx-versal.h | 6 +++--- | ||
| 24 | include/hw/arm/xlnx-zynqmp.h | 2 +- | ||
| 25 | include/hw/or-irq.h | 2 -- | ||
| 26 | hw/arm/exynos4210.c | 4 ++-- | ||
| 27 | hw/arm/mps2-tz.c | 2 +- | ||
| 28 | hw/core/or-irq.c | 18 +++++++++--------- | ||
| 29 | hw/pci-host/raven.c | 2 +- | ||
| 30 | 12 files changed, 25 insertions(+), 27 deletions(-) | ||
| 31 | |||
| 32 | diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | ||
| 34 | --- a/include/hw/arm/armsse.h | ||
| 35 | +++ b/include/hw/arm/armsse.h | ||
| 36 | @@ -XXX,XX +XXX,XX @@ struct ARMSSE { | ||
| 37 | TZPPC apb_ppc[NUM_INTERNAL_PPCS]; | ||
| 38 | TZMPC mpc[IOTS_NUM_MPC]; | ||
| 39 | CMSDKAPBTimer timer[3]; | ||
| 40 | - qemu_or_irq ppc_irq_orgate; | ||
| 41 | + OrIRQState ppc_irq_orgate; | ||
| 42 | SplitIRQ sec_resp_splitter; | ||
| 43 | SplitIRQ ppc_irq_splitter[NUM_PPCS]; | ||
| 44 | SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC]; | ||
| 45 | - qemu_or_irq mpc_irq_orgate; | ||
| 46 | - qemu_or_irq nmi_orgate; | ||
| 47 | + OrIRQState mpc_irq_orgate; | ||
| 48 | + OrIRQState nmi_orgate; | ||
| 49 | |||
| 50 | SplitIRQ cpu_irq_splitter[NUM_SSE_IRQS]; | ||
| 51 | |||
| 52 | diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h | ||
| 53 | index XXXXXXX..XXXXXXX 100644 | ||
| 54 | --- a/include/hw/arm/bcm2835_peripherals.h | ||
| 55 | +++ b/include/hw/arm/bcm2835_peripherals.h | ||
| 56 | @@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState { | ||
| 57 | BCM2835AuxState aux; | ||
| 58 | BCM2835FBState fb; | ||
| 59 | BCM2835DMAState dma; | ||
| 60 | - qemu_or_irq orgated_dma_irq; | ||
| 61 | + OrIRQState orgated_dma_irq; | ||
| 62 | BCM2835ICState ic; | ||
| 63 | BCM2835PropertyState property; | ||
| 64 | BCM2835RngState rng; | ||
| 65 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | ||
| 66 | index XXXXXXX..XXXXXXX 100644 | ||
| 67 | --- a/include/hw/arm/exynos4210.h | ||
| 68 | +++ b/include/hw/arm/exynos4210.h | ||
| 69 | @@ -XXX,XX +XXX,XX @@ struct Exynos4210State { | ||
| 70 | MemoryRegion boot_secondary; | ||
| 71 | MemoryRegion bootreg_mem; | ||
| 72 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | ||
| 73 | - qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | ||
| 74 | - qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
| 75 | + OrIRQState pl330_irq_orgate[EXYNOS4210_NUM_DMA]; | ||
| 76 | + OrIRQState cpu_irq_orgate[EXYNOS4210_NCPUS]; | ||
| 77 | A9MPPrivState a9mpcore; | ||
| 78 | Exynos4210GicState ext_gic; | ||
| 79 | Exynos4210CombinerState int_combiner; | ||
| 80 | diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h | ||
| 81 | index XXXXXXX..XXXXXXX 100644 | ||
| 82 | --- a/include/hw/arm/stm32f205_soc.h | ||
| 83 | +++ b/include/hw/arm/stm32f205_soc.h | ||
| 84 | @@ -XXX,XX +XXX,XX @@ struct STM32F205State { | ||
| 85 | STM32F2XXADCState adc[STM_NUM_ADCS]; | ||
| 86 | STM32F2XXSPIState spi[STM_NUM_SPIS]; | ||
| 87 | |||
| 88 | - qemu_or_irq *adc_irqs; | ||
| 89 | + OrIRQState *adc_irqs; | ||
| 90 | |||
| 91 | MemoryRegion sram; | ||
| 92 | MemoryRegion flash; | ||
| 93 | diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h | ||
| 94 | index XXXXXXX..XXXXXXX 100644 | ||
| 95 | --- a/include/hw/arm/stm32f405_soc.h | ||
| 96 | +++ b/include/hw/arm/stm32f405_soc.h | ||
| 97 | @@ -XXX,XX +XXX,XX @@ struct STM32F405State { | ||
| 98 | STM32F4xxExtiState exti; | ||
| 99 | STM32F2XXUsartState usart[STM_NUM_USARTS]; | ||
| 100 | STM32F2XXTimerState timer[STM_NUM_TIMERS]; | ||
| 101 | - qemu_or_irq adc_irqs; | ||
| 102 | + OrIRQState adc_irqs; | ||
| 103 | STM32F2XXADCState adc[STM_NUM_ADCS]; | ||
| 104 | STM32F2XXSPIState spi[STM_NUM_SPIS]; | ||
| 105 | |||
| 18 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | 106 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h |
| 19 | index XXXXXXX..XXXXXXX 100644 | 107 | index XXXXXXX..XXXXXXX 100644 |
| 20 | --- a/include/hw/arm/xlnx-versal.h | 108 | --- a/include/hw/arm/xlnx-versal.h |
| 21 | +++ b/include/hw/arm/xlnx-versal.h | 109 | +++ b/include/hw/arm/xlnx-versal.h |
| 22 | @@ -XXX,XX +XXX,XX @@ typedef struct Versal { | 110 | @@ -XXX,XX +XXX,XX @@ struct Versal { |
| 111 | } rpu; | ||
| 112 | |||
| 113 | struct { | ||
| 114 | - qemu_or_irq irq_orgate; | ||
| 115 | + OrIRQState irq_orgate; | ||
| 116 | XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; | ||
| 117 | } xram; | ||
| 118 | |||
| 119 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
| 120 | XlnxCSUDMA dma_src; | ||
| 121 | XlnxCSUDMA dma_dst; | ||
| 122 | MemoryRegion linear_mr; | ||
| 123 | - qemu_or_irq irq_orgate; | ||
| 124 | + OrIRQState irq_orgate; | ||
| 125 | } ospi; | ||
| 126 | } iou; | ||
| 127 | |||
| 128 | @@ -XXX,XX +XXX,XX @@ struct Versal { | ||
| 129 | XlnxVersalEFuseCtrl efuse_ctrl; | ||
| 130 | XlnxVersalEFuseCache efuse_cache; | ||
| 131 | |||
| 132 | - qemu_or_irq apb_irq_orgate; | ||
| 133 | + OrIRQState apb_irq_orgate; | ||
| 134 | } pmc; | ||
| 135 | |||
| 23 | struct { | 136 | struct { |
| 24 | struct { | 137 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h |
| 25 | MemoryRegion mr; | 138 | index XXXXXXX..XXXXXXX 100644 |
| 26 | - ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS]; | 139 | --- a/include/hw/arm/xlnx-zynqmp.h |
| 27 | + ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; | 140 | +++ b/include/hw/arm/xlnx-zynqmp.h |
| 28 | GICv3State gic; | 141 | @@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState { |
| 29 | } apu; | 142 | XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; |
| 30 | } fpd; | 143 | XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; |
| 31 | diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c | 144 | XlnxCSUDMA qspi_dma; |
| 32 | index XXXXXXX..XXXXXXX 100644 | 145 | - qemu_or_irq qspi_irq_orgate; |
| 33 | --- a/hw/arm/xlnx-versal-virt.c | 146 | + OrIRQState qspi_irq_orgate; |
| 34 | +++ b/hw/arm/xlnx-versal-virt.c | 147 | XlnxZynqMPAPUCtrl apu_ctrl; |
| 35 | @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) | 148 | XlnxZynqMPCRF crf; |
| 36 | s->binfo.get_dtb = versal_virt_get_dtb; | 149 | CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; |
| 37 | s->binfo.modify_dtb = versal_virt_modify_dtb; | 150 | diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h |
| 38 | if (machine->kernel_filename) { | 151 | index XXXXXXX..XXXXXXX 100644 |
| 39 | - arm_load_kernel(s->soc.fpd.apu.cpu[0], machine, &s->binfo); | 152 | --- a/include/hw/or-irq.h |
| 40 | + arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo); | 153 | +++ b/include/hw/or-irq.h |
| 41 | } else { | 154 | @@ -XXX,XX +XXX,XX @@ |
| 42 | - AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0], | 155 | */ |
| 43 | + AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0], | 156 | #define MAX_OR_LINES 48 |
| 44 | &s->binfo); | 157 | |
| 45 | /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL). | 158 | -typedef struct OrIRQState qemu_or_irq; |
| 46 | * Offset things by 4K. */ | ||
| 47 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
| 48 | index XXXXXXX..XXXXXXX 100644 | ||
| 49 | --- a/hw/arm/xlnx-versal.c | ||
| 50 | +++ b/hw/arm/xlnx-versal.c | ||
| 51 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | ||
| 52 | |||
| 53 | for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { | ||
| 54 | Object *obj; | ||
| 55 | - char *name; | ||
| 56 | - | 159 | - |
| 57 | - obj = object_new(XLNX_VERSAL_ACPU_TYPE); | 160 | OBJECT_DECLARE_SIMPLE_TYPE(OrIRQState, OR_IRQ) |
| 58 | - if (!obj) { | 161 | |
| 59 | - error_report("Unable to create apu.cpu[%d] of type %s", | 162 | struct OrIRQState { |
| 60 | - i, XLNX_VERSAL_ACPU_TYPE); | 163 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c |
| 61 | - exit(EXIT_FAILURE); | 164 | index XXXXXXX..XXXXXXX 100644 |
| 62 | - } | 165 | --- a/hw/arm/exynos4210.c |
| 63 | - | 166 | +++ b/hw/arm/exynos4210.c |
| 64 | - name = g_strdup_printf("apu-cpu[%d]", i); | 167 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu) |
| 65 | - object_property_add_child(OBJECT(s), name, obj, &error_fatal); | 168 | return (0x9 << ARM_AFF1_SHIFT) | cpu; |
| 66 | - g_free(name); | ||
| 67 | |||
| 68 | + object_initialize_child(OBJECT(s), "apu-cpu[*]", | ||
| 69 | + &s->fpd.apu.cpu[i], sizeof(s->fpd.apu.cpu[i]), | ||
| 70 | + XLNX_VERSAL_ACPU_TYPE, &error_abort, NULL); | ||
| 71 | + obj = OBJECT(&s->fpd.apu.cpu[i]); | ||
| 72 | object_property_set_int(obj, s->cfg.psci_conduit, | ||
| 73 | "psci-conduit", &error_abort); | ||
| 74 | if (i) { | ||
| 75 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s) | ||
| 76 | object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory", | ||
| 77 | &error_abort); | ||
| 78 | object_property_set_bool(obj, true, "realized", &error_fatal); | ||
| 79 | - s->fpd.apu.cpu[i] = ARM_CPU(obj); | ||
| 80 | } | ||
| 81 | } | 169 | } |
| 82 | 170 | ||
| 83 | @@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic) | 171 | -static DeviceState *pl330_create(uint32_t base, qemu_or_irq *orgate, |
| 84 | } | 172 | +static DeviceState *pl330_create(uint32_t base, OrIRQState *orgate, |
| 85 | 173 | qemu_irq irq, int nreq, int nevents, int width) | |
| 86 | for (i = 0; i < nr_apu_cpus; i++) { | 174 | { |
| 87 | - DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]); | 175 | SysBusDevice *busdev; |
| 88 | + DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]); | 176 | @@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj) |
| 89 | int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; | 177 | |
| 90 | qemu_irq maint_irq; | 178 | for (i = 0; i < ARRAY_SIZE(s->pl330_irq_orgate); i++) { |
| 91 | int ti; | 179 | char *name = g_strdup_printf("pl330-irq-orgate%d", i); |
| 180 | - qemu_or_irq *orgate = &s->pl330_irq_orgate[i]; | ||
| 181 | + OrIRQState *orgate = &s->pl330_irq_orgate[i]; | ||
| 182 | |||
| 183 | object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); | ||
| 184 | g_free(name); | ||
| 185 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | ||
| 186 | index XXXXXXX..XXXXXXX 100644 | ||
| 187 | --- a/hw/arm/mps2-tz.c | ||
| 188 | +++ b/hw/arm/mps2-tz.c | ||
| 189 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineState { | ||
| 190 | TZMSC msc[4]; | ||
| 191 | CMSDKAPBUART uart[6]; | ||
| 192 | SplitIRQ sec_resp_splitter; | ||
| 193 | - qemu_or_irq uart_irq_orgate; | ||
| 194 | + OrIRQState uart_irq_orgate; | ||
| 195 | DeviceState *lan9118; | ||
| 196 | SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; | ||
| 197 | Clock *sysclk; | ||
| 198 | diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c | ||
| 199 | index XXXXXXX..XXXXXXX 100644 | ||
| 200 | --- a/hw/core/or-irq.c | ||
| 201 | +++ b/hw/core/or-irq.c | ||
| 202 | @@ -XXX,XX +XXX,XX @@ | ||
| 203 | |||
| 204 | static void or_irq_handler(void *opaque, int n, int level) | ||
| 205 | { | ||
| 206 | - qemu_or_irq *s = OR_IRQ(opaque); | ||
| 207 | + OrIRQState *s = OR_IRQ(opaque); | ||
| 208 | int or_level = 0; | ||
| 209 | int i; | ||
| 210 | |||
| 211 | @@ -XXX,XX +XXX,XX @@ static void or_irq_handler(void *opaque, int n, int level) | ||
| 212 | |||
| 213 | static void or_irq_reset(DeviceState *dev) | ||
| 214 | { | ||
| 215 | - qemu_or_irq *s = OR_IRQ(dev); | ||
| 216 | + OrIRQState *s = OR_IRQ(dev); | ||
| 217 | int i; | ||
| 218 | |||
| 219 | for (i = 0; i < MAX_OR_LINES; i++) { | ||
| 220 | @@ -XXX,XX +XXX,XX @@ static void or_irq_reset(DeviceState *dev) | ||
| 221 | |||
| 222 | static void or_irq_realize(DeviceState *dev, Error **errp) | ||
| 223 | { | ||
| 224 | - qemu_or_irq *s = OR_IRQ(dev); | ||
| 225 | + OrIRQState *s = OR_IRQ(dev); | ||
| 226 | |||
| 227 | assert(s->num_lines <= MAX_OR_LINES); | ||
| 228 | |||
| 229 | @@ -XXX,XX +XXX,XX @@ static void or_irq_realize(DeviceState *dev, Error **errp) | ||
| 230 | |||
| 231 | static void or_irq_init(Object *obj) | ||
| 232 | { | ||
| 233 | - qemu_or_irq *s = OR_IRQ(obj); | ||
| 234 | + OrIRQState *s = OR_IRQ(obj); | ||
| 235 | |||
| 236 | qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1); | ||
| 237 | } | ||
| 238 | @@ -XXX,XX +XXX,XX @@ static void or_irq_init(Object *obj) | ||
| 239 | |||
| 240 | static bool vmstate_extras_needed(void *opaque) | ||
| 241 | { | ||
| 242 | - qemu_or_irq *s = OR_IRQ(opaque); | ||
| 243 | + OrIRQState *s = OR_IRQ(opaque); | ||
| 244 | |||
| 245 | return s->num_lines >= OLD_MAX_OR_LINES; | ||
| 246 | } | ||
| 247 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq_extras = { | ||
| 248 | .minimum_version_id = 1, | ||
| 249 | .needed = vmstate_extras_needed, | ||
| 250 | .fields = (VMStateField[]) { | ||
| 251 | - VMSTATE_VARRAY_UINT16_UNSAFE(levels, qemu_or_irq, num_lines, 0, | ||
| 252 | + VMSTATE_VARRAY_UINT16_UNSAFE(levels, OrIRQState, num_lines, 0, | ||
| 253 | vmstate_info_bool, bool), | ||
| 254 | VMSTATE_END_OF_LIST(), | ||
| 255 | }, | ||
| 256 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq = { | ||
| 257 | .version_id = 1, | ||
| 258 | .minimum_version_id = 1, | ||
| 259 | .fields = (VMStateField[]) { | ||
| 260 | - VMSTATE_BOOL_SUB_ARRAY(levels, qemu_or_irq, 0, OLD_MAX_OR_LINES), | ||
| 261 | + VMSTATE_BOOL_SUB_ARRAY(levels, OrIRQState, 0, OLD_MAX_OR_LINES), | ||
| 262 | VMSTATE_END_OF_LIST(), | ||
| 263 | }, | ||
| 264 | .subsections = (const VMStateDescription*[]) { | ||
| 265 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_or_irq = { | ||
| 266 | }; | ||
| 267 | |||
| 268 | static Property or_irq_properties[] = { | ||
| 269 | - DEFINE_PROP_UINT16("num-lines", qemu_or_irq, num_lines, 1), | ||
| 270 | + DEFINE_PROP_UINT16("num-lines", OrIRQState, num_lines, 1), | ||
| 271 | DEFINE_PROP_END_OF_LIST(), | ||
| 272 | }; | ||
| 273 | |||
| 274 | @@ -XXX,XX +XXX,XX @@ static void or_irq_class_init(ObjectClass *klass, void *data) | ||
| 275 | static const TypeInfo or_irq_type_info = { | ||
| 276 | .name = TYPE_OR_IRQ, | ||
| 277 | .parent = TYPE_DEVICE, | ||
| 278 | - .instance_size = sizeof(qemu_or_irq), | ||
| 279 | + .instance_size = sizeof(OrIRQState), | ||
| 280 | .instance_init = or_irq_init, | ||
| 281 | .class_init = or_irq_class_init, | ||
| 282 | }; | ||
| 283 | diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c | ||
| 284 | index XXXXXXX..XXXXXXX 100644 | ||
| 285 | --- a/hw/pci-host/raven.c | ||
| 286 | +++ b/hw/pci-host/raven.c | ||
| 287 | @@ -XXX,XX +XXX,XX @@ DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE, | ||
| 288 | struct PRePPCIState { | ||
| 289 | PCIHostState parent_obj; | ||
| 290 | |||
| 291 | - qemu_or_irq *or_irq; | ||
| 292 | + OrIRQState *or_irq; | ||
| 293 | qemu_irq pci_irqs[PCI_NUM_PINS]; | ||
| 294 | PCIBus pci_bus; | ||
| 295 | AddressSpace pci_io_as; | ||
| 92 | -- | 296 | -- |
| 93 | 2.20.1 | 297 | 2.34.1 |
| 94 | 298 | ||
| 95 | 299 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Somewhere along theline we accidentally added a duplicate | ||
| 2 | "using D16-D31 when they don't exist" check to do_vfm_dp() | ||
| 3 | (probably an artifact of a patchseries rebase). Remove it. | ||
| 4 | 1 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 8 | Message-id: 20200430181003.21682-2-peter.maydell@linaro.org | ||
| 9 | --- | ||
| 10 | target/arm/translate-vfp.inc.c | 6 ------ | ||
| 11 | 1 file changed, 6 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/translate-vfp.inc.c | ||
| 16 | +++ b/target/arm/translate-vfp.inc.c | ||
| 17 | @@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d) | ||
| 18 | return false; | ||
| 19 | } | ||
| 20 | |||
| 21 | - /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
| 22 | - if (!dc_isar_feature(aa32_simd_r32, s) && | ||
| 23 | - ((a->vd | a->vn | a->vm) & 0x10)) { | ||
| 24 | - return false; | ||
| 25 | - } | ||
| 26 | - | ||
| 27 | if (!vfp_access_check(s)) { | ||
| 28 | return true; | ||
| 29 | } | ||
| 30 | -- | ||
| 31 | 2.20.1 | ||
| 32 | |||
| 33 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | We were accidentally permitting decode of Thumb Neon insns even if | ||
| 2 | the CPU didn't have the FEATURE_NEON bit set, because the feature | ||
| 3 | check was being done before the call to disas_neon_data_insn() and | ||
| 4 | disas_neon_ls_insn() in the Arm decoder but was omitted from the | ||
| 5 | Thumb decoder. Push the feature bit check down into the called | ||
| 6 | functions so it is done for both Arm and Thumb encodings. | ||
| 7 | 1 | ||
| 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 10 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
| 11 | Message-id: 20200430181003.21682-3-peter.maydell@linaro.org | ||
| 12 | --- | ||
| 13 | target/arm/translate.c | 16 ++++++++-------- | ||
| 14 | 1 file changed, 8 insertions(+), 8 deletions(-) | ||
| 15 | |||
| 16 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 17 | index XXXXXXX..XXXXXXX 100644 | ||
| 18 | --- a/target/arm/translate.c | ||
| 19 | +++ b/target/arm/translate.c | ||
| 20 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) | ||
| 21 | TCGv_i32 tmp2; | ||
| 22 | TCGv_i64 tmp64; | ||
| 23 | |||
| 24 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
| 25 | + return 1; | ||
| 26 | + } | ||
| 27 | + | ||
| 28 | /* FIXME: this access check should not take precedence over UNDEF | ||
| 29 | * for invalid encodings; we will generate incorrect syndrome information | ||
| 30 | * for attempts to execute invalid vfp/neon encodings with FP disabled. | ||
| 31 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 32 | TCGv_ptr ptr1, ptr2, ptr3; | ||
| 33 | TCGv_i64 tmp64; | ||
| 34 | |||
| 35 | + if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
| 36 | + return 1; | ||
| 37 | + } | ||
| 38 | + | ||
| 39 | /* FIXME: this access check should not take precedence over UNDEF | ||
| 40 | * for invalid encodings; we will generate incorrect syndrome information | ||
| 41 | * for attempts to execute invalid vfp/neon encodings with FP disabled. | ||
| 42 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
| 43 | |||
| 44 | if (((insn >> 25) & 7) == 1) { | ||
| 45 | /* NEON Data processing. */ | ||
| 46 | - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
| 47 | - goto illegal_op; | ||
| 48 | - } | ||
| 49 | - | ||
| 50 | if (disas_neon_data_insn(s, insn)) { | ||
| 51 | goto illegal_op; | ||
| 52 | } | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
| 54 | } | ||
| 55 | if ((insn & 0x0f100000) == 0x04000000) { | ||
| 56 | /* NEON load/store. */ | ||
| 57 | - if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { | ||
| 58 | - goto illegal_op; | ||
| 59 | - } | ||
| 60 | - | ||
| 61 | if (disas_neon_ls_insn(s, insn)) { | ||
| 62 | goto illegal_op; | ||
| 63 | } | ||
| 64 | -- | ||
| 65 | 2.20.1 | ||
| 66 | |||
| 67 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Convert the VCMLA (vector) insns in the 3same extension group to | ||
| 2 | decodetree. | ||
| 3 | 1 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20200430181003.21682-5-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/arm/neon-shared.decode | 11 ++++++++++ | ||
| 9 | target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++ | ||
| 10 | target/arm/translate.c | 11 +--------- | ||
| 11 | 3 files changed, 49 insertions(+), 10 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/neon-shared.decode | ||
| 16 | +++ b/target/arm/neon-shared.decode | ||
| 17 | @@ -XXX,XX +XXX,XX @@ | ||
| 18 | # More specifically, this covers: | ||
| 19 | # 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx | ||
| 20 | # 3same ext: 0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx | ||
| 21 | + | ||
| 22 | +# VFP/Neon register fields; same as vfp.decode | ||
| 23 | +%vm_dp 5:1 0:4 | ||
| 24 | +%vm_sp 0:4 5:1 | ||
| 25 | +%vn_dp 7:1 16:4 | ||
| 26 | +%vn_sp 16:4 7:1 | ||
| 27 | +%vd_dp 22:1 12:4 | ||
| 28 | +%vd_sp 12:4 22:1 | ||
| 29 | + | ||
| 30 | +VCMLA 1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \ | ||
| 31 | + vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
| 32 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 33 | index XXXXXXX..XXXXXXX 100644 | ||
| 34 | --- a/target/arm/translate-neon.inc.c | ||
| 35 | +++ b/target/arm/translate-neon.inc.c | ||
| 36 | @@ -XXX,XX +XXX,XX @@ | ||
| 37 | #include "decode-neon-dp.inc.c" | ||
| 38 | #include "decode-neon-ls.inc.c" | ||
| 39 | #include "decode-neon-shared.inc.c" | ||
| 40 | + | ||
| 41 | +static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) | ||
| 42 | +{ | ||
| 43 | + int opr_sz; | ||
| 44 | + TCGv_ptr fpst; | ||
| 45 | + gen_helper_gvec_3_ptr *fn_gvec_ptr; | ||
| 46 | + | ||
| 47 | + if (!dc_isar_feature(aa32_vcma, s) | ||
| 48 | + || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { | ||
| 49 | + return false; | ||
| 50 | + } | ||
| 51 | + | ||
| 52 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
| 53 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
| 54 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
| 55 | + return false; | ||
| 56 | + } | ||
| 57 | + | ||
| 58 | + if ((a->vn | a->vm | a->vd) & a->q) { | ||
| 59 | + return false; | ||
| 60 | + } | ||
| 61 | + | ||
| 62 | + if (!vfp_access_check(s)) { | ||
| 63 | + return true; | ||
| 64 | + } | ||
| 65 | + | ||
| 66 | + opr_sz = (1 + a->q) * 8; | ||
| 67 | + fpst = get_fpstatus_ptr(1); | ||
| 68 | + fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; | ||
| 69 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), | ||
| 70 | + vfp_reg_offset(1, a->vn), | ||
| 71 | + vfp_reg_offset(1, a->vm), | ||
| 72 | + fpst, opr_sz, opr_sz, a->rot, | ||
| 73 | + fn_gvec_ptr); | ||
| 74 | + tcg_temp_free_ptr(fpst); | ||
| 75 | + return true; | ||
| 76 | +} | ||
| 77 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 78 | index XXXXXXX..XXXXXXX 100644 | ||
| 79 | --- a/target/arm/translate.c | ||
| 80 | +++ b/target/arm/translate.c | ||
| 81 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | ||
| 82 | bool is_long = false, q = extract32(insn, 6, 1); | ||
| 83 | bool ptr_is_env = false; | ||
| 84 | |||
| 85 | - if ((insn & 0xfe200f10) == 0xfc200800) { | ||
| 86 | - /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ | ||
| 87 | - int size = extract32(insn, 20, 1); | ||
| 88 | - data = extract32(insn, 23, 2); /* rot */ | ||
| 89 | - if (!dc_isar_feature(aa32_vcma, s) | ||
| 90 | - || (!size && !dc_isar_feature(aa32_fp16_arith, s))) { | ||
| 91 | - return 1; | ||
| 92 | - } | ||
| 93 | - fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah; | ||
| 94 | - } else if ((insn & 0xfea00f10) == 0xfc800800) { | ||
| 95 | + if ((insn & 0xfea00f10) == 0xfc800800) { | ||
| 96 | /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */ | ||
| 97 | int size = extract32(insn, 20, 1); | ||
| 98 | data = extract32(insn, 24, 1); /* rot */ | ||
| 99 | -- | ||
| 100 | 2.20.1 | ||
| 101 | |||
| 102 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Convert the VCADD (vector) insns to decodetree. | ||
| 2 | 1 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20200430181003.21682-6-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/arm/neon-shared.decode | 3 +++ | ||
| 8 | target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++ | ||
| 9 | target/arm/translate.c | 11 +--------- | ||
| 10 | 3 files changed, 41 insertions(+), 10 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/arm/neon-shared.decode | ||
| 15 | +++ b/target/arm/neon-shared.decode | ||
| 16 | @@ -XXX,XX +XXX,XX @@ | ||
| 17 | |||
| 18 | VCMLA 1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \ | ||
| 19 | vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
| 20 | + | ||
| 21 | +VCADD 1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \ | ||
| 22 | + vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
| 23 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 24 | index XXXXXXX..XXXXXXX 100644 | ||
| 25 | --- a/target/arm/translate-neon.inc.c | ||
| 26 | +++ b/target/arm/translate-neon.inc.c | ||
| 27 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) | ||
| 28 | tcg_temp_free_ptr(fpst); | ||
| 29 | return true; | ||
| 30 | } | ||
| 31 | + | ||
| 32 | +static bool trans_VCADD(DisasContext *s, arg_VCADD *a) | ||
| 33 | +{ | ||
| 34 | + int opr_sz; | ||
| 35 | + TCGv_ptr fpst; | ||
| 36 | + gen_helper_gvec_3_ptr *fn_gvec_ptr; | ||
| 37 | + | ||
| 38 | + if (!dc_isar_feature(aa32_vcma, s) | ||
| 39 | + || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { | ||
| 40 | + return false; | ||
| 41 | + } | ||
| 42 | + | ||
| 43 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
| 44 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
| 45 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
| 46 | + return false; | ||
| 47 | + } | ||
| 48 | + | ||
| 49 | + if ((a->vn | a->vm | a->vd) & a->q) { | ||
| 50 | + return false; | ||
| 51 | + } | ||
| 52 | + | ||
| 53 | + if (!vfp_access_check(s)) { | ||
| 54 | + return true; | ||
| 55 | + } | ||
| 56 | + | ||
| 57 | + opr_sz = (1 + a->q) * 8; | ||
| 58 | + fpst = get_fpstatus_ptr(1); | ||
| 59 | + fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; | ||
| 60 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), | ||
| 61 | + vfp_reg_offset(1, a->vn), | ||
| 62 | + vfp_reg_offset(1, a->vm), | ||
| 63 | + fpst, opr_sz, opr_sz, a->rot, | ||
| 64 | + fn_gvec_ptr); | ||
| 65 | + tcg_temp_free_ptr(fpst); | ||
| 66 | + return true; | ||
| 67 | +} | ||
| 68 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 69 | index XXXXXXX..XXXXXXX 100644 | ||
| 70 | --- a/target/arm/translate.c | ||
| 71 | +++ b/target/arm/translate.c | ||
| 72 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | ||
| 73 | bool is_long = false, q = extract32(insn, 6, 1); | ||
| 74 | bool ptr_is_env = false; | ||
| 75 | |||
| 76 | - if ((insn & 0xfea00f10) == 0xfc800800) { | ||
| 77 | - /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */ | ||
| 78 | - int size = extract32(insn, 20, 1); | ||
| 79 | - data = extract32(insn, 24, 1); /* rot */ | ||
| 80 | - if (!dc_isar_feature(aa32_vcma, s) | ||
| 81 | - || (!size && !dc_isar_feature(aa32_fp16_arith, s))) { | ||
| 82 | - return 1; | ||
| 83 | - } | ||
| 84 | - fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh; | ||
| 85 | - } else if ((insn & 0xfeb00f00) == 0xfc200d00) { | ||
| 86 | + if ((insn & 0xfeb00f00) == 0xfc200d00) { | ||
| 87 | /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */ | ||
| 88 | bool u = extract32(insn, 4, 1); | ||
| 89 | if (!dc_isar_feature(aa32_dp, s)) { | ||
| 90 | -- | ||
| 91 | 2.20.1 | ||
| 92 | |||
| 93 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Convert the V[US]DOT (vector) insns to decodetree. | ||
| 2 | 1 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20200430181003.21682-7-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/arm/neon-shared.decode | 4 ++++ | ||
| 8 | target/arm/translate-neon.inc.c | 32 ++++++++++++++++++++++++++++++++ | ||
| 9 | target/arm/translate.c | 9 +-------- | ||
| 10 | 3 files changed, 37 insertions(+), 8 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/arm/neon-shared.decode | ||
| 15 | +++ b/target/arm/neon-shared.decode | ||
| 16 | @@ -XXX,XX +XXX,XX @@ VCMLA 1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \ | ||
| 17 | |||
| 18 | VCADD 1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \ | ||
| 19 | vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
| 20 | + | ||
| 21 | +# VUDOT and VSDOT | ||
| 22 | +VDOT 1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \ | ||
| 23 | + vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
| 24 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/target/arm/translate-neon.inc.c | ||
| 27 | +++ b/target/arm/translate-neon.inc.c | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a) | ||
| 29 | tcg_temp_free_ptr(fpst); | ||
| 30 | return true; | ||
| 31 | } | ||
| 32 | + | ||
| 33 | +static bool trans_VDOT(DisasContext *s, arg_VDOT *a) | ||
| 34 | +{ | ||
| 35 | + int opr_sz; | ||
| 36 | + gen_helper_gvec_3 *fn_gvec; | ||
| 37 | + | ||
| 38 | + if (!dc_isar_feature(aa32_dp, s)) { | ||
| 39 | + return false; | ||
| 40 | + } | ||
| 41 | + | ||
| 42 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
| 43 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
| 44 | + ((a->vd | a->vn | a->vm) & 0x10)) { | ||
| 45 | + return false; | ||
| 46 | + } | ||
| 47 | + | ||
| 48 | + if ((a->vn | a->vm | a->vd) & a->q) { | ||
| 49 | + return false; | ||
| 50 | + } | ||
| 51 | + | ||
| 52 | + if (!vfp_access_check(s)) { | ||
| 53 | + return true; | ||
| 54 | + } | ||
| 55 | + | ||
| 56 | + opr_sz = (1 + a->q) * 8; | ||
| 57 | + fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b; | ||
| 58 | + tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd), | ||
| 59 | + vfp_reg_offset(1, a->vn), | ||
| 60 | + vfp_reg_offset(1, a->vm), | ||
| 61 | + opr_sz, opr_sz, 0, fn_gvec); | ||
| 62 | + return true; | ||
| 63 | +} | ||
| 64 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 65 | index XXXXXXX..XXXXXXX 100644 | ||
| 66 | --- a/target/arm/translate.c | ||
| 67 | +++ b/target/arm/translate.c | ||
| 68 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | ||
| 69 | bool is_long = false, q = extract32(insn, 6, 1); | ||
| 70 | bool ptr_is_env = false; | ||
| 71 | |||
| 72 | - if ((insn & 0xfeb00f00) == 0xfc200d00) { | ||
| 73 | - /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */ | ||
| 74 | - bool u = extract32(insn, 4, 1); | ||
| 75 | - if (!dc_isar_feature(aa32_dp, s)) { | ||
| 76 | - return 1; | ||
| 77 | - } | ||
| 78 | - fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b; | ||
| 79 | - } else if ((insn & 0xff300f10) == 0xfc200810) { | ||
| 80 | + if ((insn & 0xff300f10) == 0xfc200810) { | ||
| 81 | /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */ | ||
| 82 | int is_s = extract32(insn, 23, 1); | ||
| 83 | if (!dc_isar_feature(aa32_fhm, s)) { | ||
| 84 | -- | ||
| 85 | 2.20.1 | ||
| 86 | |||
| 87 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Convert the VFM[AS]L (vector) insns to decodetree. This is the last | ||
| 2 | insn in the legacy decoder for the 3same_ext group, so we can | ||
| 3 | delete the legacy decoder function for the group entirely. | ||
| 4 | 1 | ||
| 5 | Note that in disas_thumb2_insn() the parts of this encoding space | ||
| 6 | where the decodetree decoder returns false will correctly be directed | ||
| 7 | to illegal_op by the "(insn & (1 << 28))" check so they won't fall | ||
| 8 | into disas_coproc_insn() by mistake. | ||
| 9 | |||
| 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 12 | Message-id: 20200430181003.21682-8-peter.maydell@linaro.org | ||
| 13 | --- | ||
| 14 | target/arm/neon-shared.decode | 6 +++ | ||
| 15 | target/arm/translate-neon.inc.c | 31 +++++++++++ | ||
| 16 | target/arm/translate.c | 92 +-------------------------------- | ||
| 17 | 3 files changed, 38 insertions(+), 91 deletions(-) | ||
| 18 | |||
| 19 | diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode | ||
| 20 | index XXXXXXX..XXXXXXX 100644 | ||
| 21 | --- a/target/arm/neon-shared.decode | ||
| 22 | +++ b/target/arm/neon-shared.decode | ||
| 23 | @@ -XXX,XX +XXX,XX @@ VCADD 1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \ | ||
| 24 | # VUDOT and VSDOT | ||
| 25 | VDOT 1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \ | ||
| 26 | vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
| 27 | + | ||
| 28 | +# VFM[AS]L | ||
| 29 | +VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \ | ||
| 30 | + vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0 | ||
| 31 | +VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \ | ||
| 32 | + vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1 | ||
| 33 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 34 | index XXXXXXX..XXXXXXX 100644 | ||
| 35 | --- a/target/arm/translate-neon.inc.c | ||
| 36 | +++ b/target/arm/translate-neon.inc.c | ||
| 37 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDOT(DisasContext *s, arg_VDOT *a) | ||
| 38 | opr_sz, opr_sz, 0, fn_gvec); | ||
| 39 | return true; | ||
| 40 | } | ||
| 41 | + | ||
| 42 | +static bool trans_VFML(DisasContext *s, arg_VFML *a) | ||
| 43 | +{ | ||
| 44 | + int opr_sz; | ||
| 45 | + | ||
| 46 | + if (!dc_isar_feature(aa32_fhm, s)) { | ||
| 47 | + return false; | ||
| 48 | + } | ||
| 49 | + | ||
| 50 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
| 51 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
| 52 | + (a->vd & 0x10)) { | ||
| 53 | + return false; | ||
| 54 | + } | ||
| 55 | + | ||
| 56 | + if (a->vd & a->q) { | ||
| 57 | + return false; | ||
| 58 | + } | ||
| 59 | + | ||
| 60 | + if (!vfp_access_check(s)) { | ||
| 61 | + return true; | ||
| 62 | + } | ||
| 63 | + | ||
| 64 | + opr_sz = (1 + a->q) * 8; | ||
| 65 | + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), | ||
| 66 | + vfp_reg_offset(a->q, a->vn), | ||
| 67 | + vfp_reg_offset(a->q, a->vm), | ||
| 68 | + cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */ | ||
| 69 | + gen_helper_gvec_fmlal_a32); | ||
| 70 | + return true; | ||
| 71 | +} | ||
| 72 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 73 | index XXXXXXX..XXXXXXX 100644 | ||
| 74 | --- a/target/arm/translate.c | ||
| 75 | +++ b/target/arm/translate.c | ||
| 76 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 77 | return 0; | ||
| 78 | } | ||
| 79 | |||
| 80 | -/* Advanced SIMD three registers of the same length extension. | ||
| 81 | - * 31 25 23 22 20 16 12 11 10 9 8 3 0 | ||
| 82 | - * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | ||
| 83 | - * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm | | ||
| 84 | - * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ | ||
| 85 | - */ | ||
| 86 | -static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) | ||
| 87 | -{ | ||
| 88 | - gen_helper_gvec_3 *fn_gvec = NULL; | ||
| 89 | - gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL; | ||
| 90 | - int rd, rn, rm, opr_sz; | ||
| 91 | - int data = 0; | ||
| 92 | - int off_rn, off_rm; | ||
| 93 | - bool is_long = false, q = extract32(insn, 6, 1); | ||
| 94 | - bool ptr_is_env = false; | ||
| 95 | - | ||
| 96 | - if ((insn & 0xff300f10) == 0xfc200810) { | ||
| 97 | - /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */ | ||
| 98 | - int is_s = extract32(insn, 23, 1); | ||
| 99 | - if (!dc_isar_feature(aa32_fhm, s)) { | ||
| 100 | - return 1; | ||
| 101 | - } | ||
| 102 | - is_long = true; | ||
| 103 | - data = is_s; /* is_2 == 0 */ | ||
| 104 | - fn_gvec_ptr = gen_helper_gvec_fmlal_a32; | ||
| 105 | - ptr_is_env = true; | ||
| 106 | - } else { | ||
| 107 | - return 1; | ||
| 108 | - } | ||
| 109 | - | ||
| 110 | - VFP_DREG_D(rd, insn); | ||
| 111 | - if (rd & q) { | ||
| 112 | - return 1; | ||
| 113 | - } | ||
| 114 | - if (q || !is_long) { | ||
| 115 | - VFP_DREG_N(rn, insn); | ||
| 116 | - VFP_DREG_M(rm, insn); | ||
| 117 | - if ((rn | rm) & q & !is_long) { | ||
| 118 | - return 1; | ||
| 119 | - } | ||
| 120 | - off_rn = vfp_reg_offset(1, rn); | ||
| 121 | - off_rm = vfp_reg_offset(1, rm); | ||
| 122 | - } else { | ||
| 123 | - rn = VFP_SREG_N(insn); | ||
| 124 | - rm = VFP_SREG_M(insn); | ||
| 125 | - off_rn = vfp_reg_offset(0, rn); | ||
| 126 | - off_rm = vfp_reg_offset(0, rm); | ||
| 127 | - } | ||
| 128 | - | ||
| 129 | - if (s->fp_excp_el) { | ||
| 130 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
| 131 | - syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); | ||
| 132 | - return 0; | ||
| 133 | - } | ||
| 134 | - if (!s->vfp_enabled) { | ||
| 135 | - return 1; | ||
| 136 | - } | ||
| 137 | - | ||
| 138 | - opr_sz = (1 + q) * 8; | ||
| 139 | - if (fn_gvec_ptr) { | ||
| 140 | - TCGv_ptr ptr; | ||
| 141 | - if (ptr_is_env) { | ||
| 142 | - ptr = cpu_env; | ||
| 143 | - } else { | ||
| 144 | - ptr = get_fpstatus_ptr(1); | ||
| 145 | - } | ||
| 146 | - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr, | ||
| 147 | - opr_sz, opr_sz, data, fn_gvec_ptr); | ||
| 148 | - if (!ptr_is_env) { | ||
| 149 | - tcg_temp_free_ptr(ptr); | ||
| 150 | - } | ||
| 151 | - } else { | ||
| 152 | - tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm, | ||
| 153 | - opr_sz, opr_sz, data, fn_gvec); | ||
| 154 | - } | ||
| 155 | - return 0; | ||
| 156 | -} | ||
| 157 | - | ||
| 158 | /* Advanced SIMD two registers and a scalar extension. | ||
| 159 | * 31 24 23 22 20 16 12 11 10 9 8 3 0 | ||
| 160 | * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+ | ||
| 161 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
| 162 | } | ||
| 163 | } | ||
| 164 | } | ||
| 165 | - } else if ((insn & 0x0e000a00) == 0x0c000800 | ||
| 166 | - && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
| 167 | - if (disas_neon_insn_3same_ext(s, insn)) { | ||
| 168 | - goto illegal_op; | ||
| 169 | - } | ||
| 170 | - return; | ||
| 171 | } else if ((insn & 0x0f000a00) == 0x0e000800 | ||
| 172 | && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
| 173 | if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | ||
| 174 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
| 175 | } | ||
| 176 | break; | ||
| 177 | } | ||
| 178 | - if ((insn & 0xfe000a00) == 0xfc000800 | ||
| 179 | + if ((insn & 0xff000a00) == 0xfe000800 | ||
| 180 | && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
| 181 | /* The Thumb2 and ARM encodings are identical. */ | ||
| 182 | - if (disas_neon_insn_3same_ext(s, insn)) { | ||
| 183 | - goto illegal_op; | ||
| 184 | - } | ||
| 185 | - } else if ((insn & 0xff000a00) == 0xfe000800 | ||
| 186 | - && arm_dc_feature(s, ARM_FEATURE_V8)) { | ||
| 187 | - /* The Thumb2 and ARM encodings are identical. */ | ||
| 188 | if (disas_neon_insn_2reg_scalar_ext(s, insn)) { | ||
| 189 | goto illegal_op; | ||
| 190 | } | ||
| 191 | -- | ||
| 192 | 2.20.1 | ||
| 193 | |||
| 194 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group | ||
| 2 | to decodetree. | ||
| 3 | 1 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20200430181003.21682-10-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/arm/neon-shared.decode | 3 +++ | ||
| 9 | target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++ | ||
| 10 | target/arm/translate.c | 13 +----------- | ||
| 11 | 3 files changed, 39 insertions(+), 12 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/neon-shared.decode | ||
| 16 | +++ b/target/arm/neon-shared.decode | ||
| 17 | @@ -XXX,XX +XXX,XX @@ VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \ | ||
| 18 | vn=%vn_dp vd=%vd_dp size=0 | ||
| 19 | VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \ | ||
| 20 | vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0 | ||
| 21 | + | ||
| 22 | +VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \ | ||
| 23 | + vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
| 24 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 25 | index XXXXXXX..XXXXXXX 100644 | ||
| 26 | --- a/target/arm/translate-neon.inc.c | ||
| 27 | +++ b/target/arm/translate-neon.inc.c | ||
| 28 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a) | ||
| 29 | tcg_temp_free_ptr(fpst); | ||
| 30 | return true; | ||
| 31 | } | ||
| 32 | + | ||
| 33 | +static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a) | ||
| 34 | +{ | ||
| 35 | + gen_helper_gvec_3 *fn_gvec; | ||
| 36 | + int opr_sz; | ||
| 37 | + TCGv_ptr fpst; | ||
| 38 | + | ||
| 39 | + if (!dc_isar_feature(aa32_dp, s)) { | ||
| 40 | + return false; | ||
| 41 | + } | ||
| 42 | + | ||
| 43 | + /* UNDEF accesses to D16-D31 if they don't exist. */ | ||
| 44 | + if (!dc_isar_feature(aa32_simd_r32, s) && | ||
| 45 | + ((a->vd | a->vn) & 0x10)) { | ||
| 46 | + return false; | ||
| 47 | + } | ||
| 48 | + | ||
| 49 | + if ((a->vd | a->vn) & a->q) { | ||
| 50 | + return false; | ||
| 51 | + } | ||
| 52 | + | ||
| 53 | + if (!vfp_access_check(s)) { | ||
| 54 | + return true; | ||
| 55 | + } | ||
| 56 | + | ||
| 57 | + fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b; | ||
| 58 | + opr_sz = (1 + a->q) * 8; | ||
| 59 | + fpst = get_fpstatus_ptr(1); | ||
| 60 | + tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd), | ||
| 61 | + vfp_reg_offset(1, a->vn), | ||
| 62 | + vfp_reg_offset(1, a->rm), | ||
| 63 | + opr_sz, opr_sz, a->index, fn_gvec); | ||
| 64 | + tcg_temp_free_ptr(fpst); | ||
| 65 | + return true; | ||
| 66 | +} | ||
| 67 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 68 | index XXXXXXX..XXXXXXX 100644 | ||
| 69 | --- a/target/arm/translate.c | ||
| 70 | +++ b/target/arm/translate.c | ||
| 71 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) | ||
| 72 | bool is_long = false, q = extract32(insn, 6, 1); | ||
| 73 | bool ptr_is_env = false; | ||
| 74 | |||
| 75 | - if ((insn & 0xffb00f00) == 0xfe200d00) { | ||
| 76 | - /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */ | ||
| 77 | - int u = extract32(insn, 4, 1); | ||
| 78 | - | ||
| 79 | - if (!dc_isar_feature(aa32_dp, s)) { | ||
| 80 | - return 1; | ||
| 81 | - } | ||
| 82 | - fn_gvec = u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b; | ||
| 83 | - /* rm is just Vm, and index is M. */ | ||
| 84 | - data = extract32(insn, 5, 1); /* index */ | ||
| 85 | - rm = extract32(insn, 0, 4); | ||
| 86 | - } else if ((insn & 0xffa00f10) == 0xfe000810) { | ||
| 87 | + if ((insn & 0xffa00f10) == 0xfe000810) { | ||
| 88 | /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */ | ||
| 89 | int is_s = extract32(insn, 20, 1); | ||
| 90 | int vm20 = extract32(insn, 0, 3); | ||
| 91 | -- | ||
| 92 | 2.20.1 | ||
| 93 | |||
| 94 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Convert the Neon logic ops in the 3-reg-same grouping to decodetree. | ||
| 2 | Note that for the logic ops the 'size' field forms part of their | ||
| 3 | decode and the actual operations are always bitwise. | ||
| 4 | 1 | ||
| 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 7 | Message-id: 20200430181003.21682-16-peter.maydell@linaro.org | ||
| 8 | --- | ||
| 9 | target/arm/neon-dp.decode | 12 +++++++++++ | ||
| 10 | target/arm/translate-neon.inc.c | 19 +++++++++++++++++ | ||
| 11 | target/arm/translate.c | 38 +-------------------------------- | ||
| 12 | 3 files changed, 32 insertions(+), 37 deletions(-) | ||
| 13 | |||
| 14 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
| 15 | index XXXXXXX..XXXXXXX 100644 | ||
| 16 | --- a/target/arm/neon-dp.decode | ||
| 17 | +++ b/target/arm/neon-dp.decode | ||
| 18 | @@ -XXX,XX +XXX,XX @@ | ||
| 19 | @3same .... ... . . . size:2 .... .... .... . q:1 . . .... \ | ||
| 20 | &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp | ||
| 21 | |||
| 22 | +@3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \ | ||
| 23 | + &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0 | ||
| 24 | + | ||
| 25 | +VAND_3s 1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic | ||
| 26 | +VBIC_3s 1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic | ||
| 27 | +VORR_3s 1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic | ||
| 28 | +VORN_3s 1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic | ||
| 29 | +VEOR_3s 1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic | ||
| 30 | +VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic | ||
| 31 | +VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic | ||
| 32 | +VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic | ||
| 33 | + | ||
| 34 | VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same | ||
| 35 | VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same | ||
| 36 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 37 | index XXXXXXX..XXXXXXX 100644 | ||
| 38 | --- a/target/arm/translate-neon.inc.c | ||
| 39 | +++ b/target/arm/translate-neon.inc.c | ||
| 40 | @@ -XXX,XX +XXX,XX @@ static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) | ||
| 41 | |||
| 42 | DO_3SAME(VADD, tcg_gen_gvec_add) | ||
| 43 | DO_3SAME(VSUB, tcg_gen_gvec_sub) | ||
| 44 | +DO_3SAME(VAND, tcg_gen_gvec_and) | ||
| 45 | +DO_3SAME(VBIC, tcg_gen_gvec_andc) | ||
| 46 | +DO_3SAME(VORR, tcg_gen_gvec_or) | ||
| 47 | +DO_3SAME(VORN, tcg_gen_gvec_orc) | ||
| 48 | +DO_3SAME(VEOR, tcg_gen_gvec_xor) | ||
| 49 | + | ||
| 50 | +/* These insns are all gvec_bitsel but with the inputs in various orders. */ | ||
| 51 | +#define DO_3SAME_BITSEL(INSN, O1, O2, O3) \ | ||
| 52 | + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ | ||
| 53 | + uint32_t rn_ofs, uint32_t rm_ofs, \ | ||
| 54 | + uint32_t oprsz, uint32_t maxsz) \ | ||
| 55 | + { \ | ||
| 56 | + tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz); \ | ||
| 57 | + } \ | ||
| 58 | + DO_3SAME(INSN, gen_##INSN##_3s) | ||
| 59 | + | ||
| 60 | +DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs) | ||
| 61 | +DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs) | ||
| 62 | +DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs) | ||
| 63 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 64 | index XXXXXXX..XXXXXXX 100644 | ||
| 65 | --- a/target/arm/translate.c | ||
| 66 | +++ b/target/arm/translate.c | ||
| 67 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 68 | } | ||
| 69 | return 1; | ||
| 70 | |||
| 71 | - case NEON_3R_LOGIC: /* Logic ops. */ | ||
| 72 | - switch ((u << 2) | size) { | ||
| 73 | - case 0: /* VAND */ | ||
| 74 | - tcg_gen_gvec_and(0, rd_ofs, rn_ofs, rm_ofs, | ||
| 75 | - vec_size, vec_size); | ||
| 76 | - break; | ||
| 77 | - case 1: /* VBIC */ | ||
| 78 | - tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs, | ||
| 79 | - vec_size, vec_size); | ||
| 80 | - break; | ||
| 81 | - case 2: /* VORR */ | ||
| 82 | - tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, | ||
| 83 | - vec_size, vec_size); | ||
| 84 | - break; | ||
| 85 | - case 3: /* VORN */ | ||
| 86 | - tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs, | ||
| 87 | - vec_size, vec_size); | ||
| 88 | - break; | ||
| 89 | - case 4: /* VEOR */ | ||
| 90 | - tcg_gen_gvec_xor(0, rd_ofs, rn_ofs, rm_ofs, | ||
| 91 | - vec_size, vec_size); | ||
| 92 | - break; | ||
| 93 | - case 5: /* VBSL */ | ||
| 94 | - tcg_gen_gvec_bitsel(MO_8, rd_ofs, rd_ofs, rn_ofs, rm_ofs, | ||
| 95 | - vec_size, vec_size); | ||
| 96 | - break; | ||
| 97 | - case 6: /* VBIT */ | ||
| 98 | - tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rn_ofs, rd_ofs, | ||
| 99 | - vec_size, vec_size); | ||
| 100 | - break; | ||
| 101 | - case 7: /* VBIF */ | ||
| 102 | - tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rd_ofs, rn_ofs, | ||
| 103 | - vec_size, vec_size); | ||
| 104 | - break; | ||
| 105 | - } | ||
| 106 | - return 0; | ||
| 107 | - | ||
| 108 | case NEON_3R_VQADD: | ||
| 109 | tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), | ||
| 110 | rn_ofs, rm_ofs, vec_size, vec_size, | ||
| 111 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 112 | return 0; | ||
| 113 | |||
| 114 | case NEON_3R_VADD_VSUB: | ||
| 115 | + case NEON_3R_LOGIC: | ||
| 116 | /* Already handled by decodetree */ | ||
| 117 | return 1; | ||
| 118 | } | ||
| 119 | -- | ||
| 120 | 2.20.1 | ||
| 121 | |||
| 122 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree. | ||
| 2 | 1 | ||
| 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 5 | Message-id: 20200430181003.21682-17-peter.maydell@linaro.org | ||
| 6 | --- | ||
| 7 | target/arm/neon-dp.decode | 5 +++++ | ||
| 8 | target/arm/translate-neon.inc.c | 14 ++++++++++++++ | ||
| 9 | target/arm/translate.c | 21 ++------------------- | ||
| 10 | 3 files changed, 21 insertions(+), 19 deletions(-) | ||
| 11 | |||
| 12 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
| 13 | index XXXXXXX..XXXXXXX 100644 | ||
| 14 | --- a/target/arm/neon-dp.decode | ||
| 15 | +++ b/target/arm/neon-dp.decode | ||
| 16 | @@ -XXX,XX +XXX,XX @@ VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic | ||
| 17 | VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic | ||
| 18 | VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic | ||
| 19 | |||
| 20 | +VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same | ||
| 21 | +VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same | ||
| 22 | +VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same | ||
| 23 | +VMIN_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same | ||
| 24 | + | ||
| 25 | VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same | ||
| 26 | VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same | ||
| 27 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 28 | index XXXXXXX..XXXXXXX 100644 | ||
| 29 | --- a/target/arm/translate-neon.inc.c | ||
| 30 | +++ b/target/arm/translate-neon.inc.c | ||
| 31 | @@ -XXX,XX +XXX,XX @@ DO_3SAME(VEOR, tcg_gen_gvec_xor) | ||
| 32 | DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs) | ||
| 33 | DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs) | ||
| 34 | DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs) | ||
| 35 | + | ||
| 36 | +#define DO_3SAME_NO_SZ_3(INSN, FUNC) \ | ||
| 37 | + static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \ | ||
| 38 | + { \ | ||
| 39 | + if (a->size == 3) { \ | ||
| 40 | + return false; \ | ||
| 41 | + } \ | ||
| 42 | + return do_3same(s, a, FUNC); \ | ||
| 43 | + } | ||
| 44 | + | ||
| 45 | +DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax) | ||
| 46 | +DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax) | ||
| 47 | +DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin) | ||
| 48 | +DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin) | ||
| 49 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 50 | index XXXXXXX..XXXXXXX 100644 | ||
| 51 | --- a/target/arm/translate.c | ||
| 52 | +++ b/target/arm/translate.c | ||
| 53 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 54 | rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); | ||
| 55 | return 0; | ||
| 56 | |||
| 57 | - case NEON_3R_VMAX: | ||
| 58 | - if (u) { | ||
| 59 | - tcg_gen_gvec_umax(size, rd_ofs, rn_ofs, rm_ofs, | ||
| 60 | - vec_size, vec_size); | ||
| 61 | - } else { | ||
| 62 | - tcg_gen_gvec_smax(size, rd_ofs, rn_ofs, rm_ofs, | ||
| 63 | - vec_size, vec_size); | ||
| 64 | - } | ||
| 65 | - return 0; | ||
| 66 | - case NEON_3R_VMIN: | ||
| 67 | - if (u) { | ||
| 68 | - tcg_gen_gvec_umin(size, rd_ofs, rn_ofs, rm_ofs, | ||
| 69 | - vec_size, vec_size); | ||
| 70 | - } else { | ||
| 71 | - tcg_gen_gvec_smin(size, rd_ofs, rn_ofs, rm_ofs, | ||
| 72 | - vec_size, vec_size); | ||
| 73 | - } | ||
| 74 | - return 0; | ||
| 75 | - | ||
| 76 | case NEON_3R_VSHL: | ||
| 77 | /* Note the operation is vshl vd,vm,vn */ | ||
| 78 | tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size, | ||
| 79 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 80 | |||
| 81 | case NEON_3R_VADD_VSUB: | ||
| 82 | case NEON_3R_LOGIC: | ||
| 83 | + case NEON_3R_VMAX: | ||
| 84 | + case NEON_3R_VMIN: | ||
| 85 | /* Already handled by decodetree */ | ||
| 86 | return 1; | ||
| 87 | } | ||
| 88 | -- | ||
| 89 | 2.20.1 | ||
| 90 | |||
| 91 | diff view generated by jsdifflib |
Deleted patch | |||
|---|---|---|---|
| 1 | Convert the Neon comparison ops in the 3-reg-same grouping | ||
| 2 | to decodetree. | ||
| 3 | 1 | ||
| 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
| 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
| 6 | Message-id: 20200430181003.21682-18-peter.maydell@linaro.org | ||
| 7 | --- | ||
| 8 | target/arm/neon-dp.decode | 8 ++++++++ | ||
| 9 | target/arm/translate-neon.inc.c | 22 ++++++++++++++++++++++ | ||
| 10 | target/arm/translate.c | 23 +++-------------------- | ||
| 11 | 3 files changed, 33 insertions(+), 20 deletions(-) | ||
| 12 | |||
| 13 | diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode | ||
| 14 | index XXXXXXX..XXXXXXX 100644 | ||
| 15 | --- a/target/arm/neon-dp.decode | ||
| 16 | +++ b/target/arm/neon-dp.decode | ||
| 17 | @@ -XXX,XX +XXX,XX @@ VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic | ||
| 18 | VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic | ||
| 19 | VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic | ||
| 20 | |||
| 21 | +VCGT_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same | ||
| 22 | +VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same | ||
| 23 | +VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same | ||
| 24 | +VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same | ||
| 25 | + | ||
| 26 | VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same | ||
| 27 | VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same | ||
| 28 | VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same | ||
| 29 | @@ -XXX,XX +XXX,XX @@ VMIN_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same | ||
| 30 | |||
| 31 | VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same | ||
| 32 | VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same | ||
| 33 | + | ||
| 34 | +VTST_3s 1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same | ||
| 35 | +VCEQ_3s 1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same | ||
| 36 | diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c | ||
| 37 | index XXXXXXX..XXXXXXX 100644 | ||
| 38 | --- a/target/arm/translate-neon.inc.c | ||
| 39 | +++ b/target/arm/translate-neon.inc.c | ||
| 40 | @@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax) | ||
| 41 | DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax) | ||
| 42 | DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin) | ||
| 43 | DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin) | ||
| 44 | + | ||
| 45 | +#define DO_3SAME_CMP(INSN, COND) \ | ||
| 46 | + static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \ | ||
| 47 | + uint32_t rn_ofs, uint32_t rm_ofs, \ | ||
| 48 | + uint32_t oprsz, uint32_t maxsz) \ | ||
| 49 | + { \ | ||
| 50 | + tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \ | ||
| 51 | + } \ | ||
| 52 | + DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s) | ||
| 53 | + | ||
| 54 | +DO_3SAME_CMP(VCGT_S, TCG_COND_GT) | ||
| 55 | +DO_3SAME_CMP(VCGT_U, TCG_COND_GTU) | ||
| 56 | +DO_3SAME_CMP(VCGE_S, TCG_COND_GE) | ||
| 57 | +DO_3SAME_CMP(VCGE_U, TCG_COND_GEU) | ||
| 58 | +DO_3SAME_CMP(VCEQ, TCG_COND_EQ) | ||
| 59 | + | ||
| 60 | +static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, | ||
| 61 | + uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) | ||
| 62 | +{ | ||
| 63 | + tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]); | ||
| 64 | +} | ||
| 65 | +DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s) | ||
| 66 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
| 67 | index XXXXXXX..XXXXXXX 100644 | ||
| 68 | --- a/target/arm/translate.c | ||
| 69 | +++ b/target/arm/translate.c | ||
| 70 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 71 | u ? &mls_op[size] : &mla_op[size]); | ||
| 72 | return 0; | ||
| 73 | |||
| 74 | - case NEON_3R_VTST_VCEQ: | ||
| 75 | - if (u) { /* VCEQ */ | ||
| 76 | - tcg_gen_gvec_cmp(TCG_COND_EQ, size, rd_ofs, rn_ofs, rm_ofs, | ||
| 77 | - vec_size, vec_size); | ||
| 78 | - } else { /* VTST */ | ||
| 79 | - tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, | ||
| 80 | - vec_size, vec_size, &cmtst_op[size]); | ||
| 81 | - } | ||
| 82 | - return 0; | ||
| 83 | - | ||
| 84 | - case NEON_3R_VCGT: | ||
| 85 | - tcg_gen_gvec_cmp(u ? TCG_COND_GTU : TCG_COND_GT, size, | ||
| 86 | - rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); | ||
| 87 | - return 0; | ||
| 88 | - | ||
| 89 | - case NEON_3R_VCGE: | ||
| 90 | - tcg_gen_gvec_cmp(u ? TCG_COND_GEU : TCG_COND_GE, size, | ||
| 91 | - rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); | ||
| 92 | - return 0; | ||
| 93 | - | ||
| 94 | case NEON_3R_VSHL: | ||
| 95 | /* Note the operation is vshl vd,vm,vn */ | ||
| 96 | tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size, | ||
| 97 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | ||
| 98 | case NEON_3R_LOGIC: | ||
| 99 | case NEON_3R_VMAX: | ||
| 100 | case NEON_3R_VMIN: | ||
| 101 | + case NEON_3R_VTST_VCEQ: | ||
| 102 | + case NEON_3R_VCGT: | ||
| 103 | + case NEON_3R_VCGE: | ||
| 104 | /* Already handled by decodetree */ | ||
| 105 | return 1; | ||
| 106 | } | ||
| 107 | -- | ||
| 108 | 2.20.1 | ||
| 109 | |||
| 110 | diff view generated by jsdifflib |