1
Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups.
1
Massive pullreq but almost all of that is RTH's SVE
2
refactoring patchset. The other interesting thing here is
3
the fix for compiling on aarch64 macos.
2
4
3
thanks
5
thanks
4
-- PMM
6
-- PMM
5
7
8
The following changes since commit f7a1ea403e0282a7f57edd4298c4f65f24165da5:
6
9
7
The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835:
10
Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging (2022-05-29 16:34:56 -0700)
8
9
Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100)
10
11
11
are available in the Git repository at:
12
are available in the Git repository at:
12
13
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220530
14
15
15
for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:
16
for you to fetch changes up to b1071174d2a2ab371082b7d4b5f19e98edc61ac6:
16
17
17
target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100)
18
target/arm: Remove aa64_sve check from before disas_sve (2022-05-30 17:05:12 +0100)
18
19
19
----------------------------------------------------------------
20
----------------------------------------------------------------
20
target-arm queue:
21
target-arm queue:
21
* Start of conversion of Neon insns to decodetree
22
* docs/system/arm: Add FEAT_HCX to list of emulated features
22
* versal board: support SD and RTC
23
* target/arm/hvf: Include missing "cpregs.h"
23
* Implement ARMv8.2-TTS2UXN
24
* hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready
24
* Make VQDMULL undefined when U=1
25
* SVE: refactor to use TRANS/TRANS_FEAT macros and push
25
* Some minor code cleanups
26
SVE feature check down to individual insn level
26
27
27
----------------------------------------------------------------
28
----------------------------------------------------------------
28
Edgar E. Iglesias (11):
29
Icenowy Zheng (1):
29
hw/arm: versal: Remove inclusion of arm_gicv3_common.h
30
hw/sd/allwinner-sdhost: report FIFO water level as 1 when data ready
30
hw/arm: versal: Move misplaced comment
31
hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal
32
hw/arm: versal: Embed the UARTs into the SoC type
33
hw/arm: versal: Embed the GEMs into the SoC type
34
hw/arm: versal: Embed the ADMAs into the SoC type
35
hw/arm: versal: Embed the APUs into the SoC type
36
hw/arm: versal: Add support for SD
37
hw/arm: versal: Add support for the RTC
38
hw/arm: versal-virt: Add support for SD
39
hw/arm: versal-virt: Add support for the RTC
40
31
41
Fredrik Strupe (1):
32
Peter Maydell (1):
42
target/arm: Make VQDMULL undefined when U=1
33
docs/system/arm: Add FEAT_HCX to list of emulated features
43
34
44
Peter Maydell (25):
35
Philippe Mathieu-Daudé (1):
45
target/arm: Don't use a TLB for ARMMMUIdx_Stage2
36
target/arm/hvf: Include missing "cpregs.h"
46
target/arm: Use enum constant in get_phys_addr_lpae() call
47
target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()
48
target/arm: Implement ARMv8.2-TTS2UXN
49
target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0
50
target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
51
target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
52
target/arm: Add stubs for AArch32 Neon decodetree
53
target/arm: Convert VCMLA (vector) to decodetree
54
target/arm: Convert VCADD (vector) to decodetree
55
target/arm: Convert V[US]DOT (vector) to decodetree
56
target/arm: Convert VFM[AS]L (vector) to decodetree
57
target/arm: Convert VCMLA (scalar) to decodetree
58
target/arm: Convert V[US]DOT (scalar) to decodetree
59
target/arm: Convert VFM[AS]L (scalar) to decodetree
60
target/arm: Convert Neon load/store multiple structures to decodetree
61
target/arm: Convert Neon 'load single structure to all lanes' to decodetree
62
target/arm: Convert Neon 'load/store single structure' to decodetree
63
target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
64
target/arm: Convert Neon 3-reg-same logic ops to decodetree
65
target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
66
target/arm: Convert Neon 3-reg-same comparisons to decodetree
67
target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
68
target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
69
target/arm: Move gen_ function typedefs to translate.h
70
37
71
Philippe Mathieu-Daudé (2):
38
Richard Henderson (114):
72
hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string
39
target/arm: Introduce TRANS, TRANS_FEAT
73
target/arm: Use uint64_t for midr field in CPU state struct
40
target/arm: Move null function and sve check into gen_gvec_ool_zz
41
target/arm: Use TRANS_FEAT for gen_gvec_ool_zz
42
target/arm: Move null function and sve check into gen_gvec_ool_zzz
43
target/arm: Introduce gen_gvec_ool_arg_zzz
44
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzz
45
target/arm: Use TRANS_FEAT for do_sve2_zzz_ool
46
target/arm: Move null function and sve check into gen_gvec_ool_zzzz
47
target/arm: Use TRANS_FEAT for gen_gvec_ool_zzzz
48
target/arm: Introduce gen_gvec_ool_arg_zzzz
49
target/arm: Use TRANS_FEAT for do_sve2_zzzz_ool
50
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzzz
51
target/arm: Rename do_zzxz_ool to gen_gvec_ool_arg_zzxz
52
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzxz
53
target/arm: Use TRANS_FEAT for do_sve2_zzz_data
54
target/arm: Use TRANS_FEAT for do_sve2_zzzz_data
55
target/arm: Use TRANS_FEAT for do_sve2_zzw_data
56
target/arm: Use TRANS_FEAT for USDOT_zzzz
57
target/arm: Move null function and sve check into gen_gvec_ool_zzp
58
target/arm: Introduce gen_gvec_ool_arg_zpz
59
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz
60
target/arm: Use TRANS_FEAT for do_sve2_zpz_data
61
target/arm: Rename do_zpzi_ool to gen_gvec_ool_arg_zpzi
62
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzi
63
target/arm: Move null function and sve check into gen_gvec_ool_zzzp
64
target/arm: Introduce gen_gvec_ool_arg_zpzz
65
target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzz
66
target/arm: Use TRANS_FEAT for do_sve2_zpzz_ool
67
target/arm: Merge gen_gvec_fn_zz into do_mov_z
68
target/arm: Move null function and sve check into gen_gvec_fn_zzz
69
target/arm: Rename do_zzz_fn to gen_gvec_fn_arg_zzz
70
target/arm: More use of gen_gvec_fn_arg_zzz
71
target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz
72
target/arm: Use TRANS_FEAT for do_sve2_fn_zzz
73
target/arm: Use TRANS_FEAT for RAX1
74
target/arm: Introduce gen_gvec_fn_arg_zzzz
75
target/arm: Use TRANS_FEAT for do_sve2_zzzz_fn
76
target/arm: Introduce gen_gvec_fn_zzi
77
target/arm: Use TRANS_FEAT for do_zz_dbm
78
target/arm: Hoist sve access check through do_sel_z
79
target/arm: Introduce gen_gvec_fn_arg_zzi
80
target/arm: Use TRANS_FEAT for do_sve2_fn2i
81
target/arm: Use TRANS_FEAT for do_vpz_ool
82
target/arm: Use TRANS_FEAT for do_shift_imm
83
target/arm: Introduce do_shift_zpzi
84
target/arm: Use TRANS_FEAT for do_shift_zpzi
85
target/arm: Use TRANS_FEAT for do_zpzzz_ool
86
target/arm: Move sve check into do_index
87
target/arm: Use TRANS_FEAT for do_index
88
target/arm: Use TRANS_FEAT for do_adr
89
target/arm: Use TRANS_FEAT for do_predset
90
target/arm: Use TRANS_FEAT for RDFFR, WRFFR
91
target/arm: Use TRANS_FEAT for do_pfirst_pnext
92
target/arm: Use TRANS_FEAT for do_EXT
93
target/arm: Use TRANS_FEAT for do_perm_pred3
94
target/arm: Use TRANS_FEAT for do_perm_pred2
95
target/arm: Move sve zip high_ofs into simd_data
96
target/arm: Use gen_gvec_ool_arg_zzz for do_zip, do_zip_q
97
target/arm: Use TRANS_FEAT for do_zip, do_zip_q
98
target/arm: Use TRANS_FEAT for do_clast_vector
99
target/arm: Use TRANS_FEAT for do_clast_fp
100
target/arm: Use TRANS_FEAT for do_clast_general
101
target/arm: Use TRANS_FEAT for do_last_fp
102
target/arm: Use TRANS_FEAT for do_last_general
103
target/arm: Use TRANS_FEAT for SPLICE
104
target/arm: Use TRANS_FEAT for do_ppzz_flags
105
target/arm: Use TRANS_FEAT for do_sve2_ppzz_flags
106
target/arm: Use TRANS_FEAT for do_ppzi_flags
107
target/arm: Use TRANS_FEAT for do_brk2, do_brk3
108
target/arm: Use TRANS_FEAT for MUL_zzi
109
target/arm: Reject dup_i w/ shifted byte early
110
target/arm: Reject add/sub w/ shifted byte early
111
target/arm: Reject copy w/ shifted byte early
112
target/arm: Use TRANS_FEAT for ADD_zzi
113
target/arm: Use TRANS_FEAT for do_zzi_sat
114
target/arm: Use TRANS_FEAT for do_zzi_ool
115
target/arm: Introduce gen_gvec_{ptr,fpst}_zzzz
116
target/arm: Use TRANS_FEAT for FMMLA
117
target/arm: Move sve check into gen_gvec_fn_ppp
118
target/arm: Implement NOT (prediates) alias
119
target/arm: Use TRANS_FEAT for SEL_zpzz
120
target/arm: Use TRANS_FEAT for MOVPRFX
121
target/arm: Use TRANS_FEAT for FMLA
122
target/arm: Use TRANS_FEAT for BFMLA
123
target/arm: Rename do_zzz_fp to gen_gvec_ool_fpst_arg_zzz
124
target/arm: Use TRANS_FEAT for DO_FP3
125
target/arm: Use TRANS_FEAT for FMUL_zzx
126
target/arm: Use TRANS_FEAT for FTMAD
127
target/arm: Move null function and sve check into do_reduce
128
target/arm: Use TRANS_FEAT for do_reduce
129
target/arm: Use TRANS_FEAT for FRECPE, FRSQRTE
130
target/arm: Expand frint_fns for MO_8
131
target/arm: Rename do_zpz_ptr to gen_gvec_ool_fpst_arg_zpz
132
target/arm: Move null function and sve check into do_frint_mode
133
target/arm: Use TRANS_FEAT for do_frint_mode
134
target/arm: Use TRANS_FEAT for FLOGB
135
target/arm: Use TRANS_FEAT for do_ppz_fp
136
target/arm: Rename do_zpzz_ptr to gen_gvec_fpst_arg_zpzz
137
target/arm: Use TRANS_FEAT for gen_gvec_fpst_arg_zpzz
138
target/arm: Use TRANS_FEAT for FCADD
139
target/arm: Introduce gen_gvec_fpst_zzzzp
140
target/arm: Use TRANS_FEAT for gen_gvec_fpst_zzzzp
141
target/arm: Move null function and sve check into do_fp_imm
142
target/arm: Use TRANS_FEAT for DO_FP_IMM
143
target/arm: Use TRANS_FEAT for DO_FPCMP
144
target/arm: Remove assert in trans_FCMLA_zzxz
145
target/arm: Use TRANS_FEAT for FCMLA_zzxz
146
target/arm: Use TRANS_FEAT for do_narrow_extract
147
target/arm: Use TRANS_FEAT for do_shll_tb
148
target/arm: Use TRANS_FEAT for do_shr_narrow
149
target/arm: Use TRANS_FEAT for do_FMLAL_zzzw
150
target/arm: Use TRANS_FEAT for do_FMLAL_zzxw
151
target/arm: Add sve feature check for remaining trans_* functions
152
target/arm: Remove aa64_sve check from before disas_sve
74
153
75
include/hw/arm/xlnx-versal.h | 31 +-
154
docs/system/arm/emulation.rst | 1 +
76
target/arm/cpu-param.h | 2 +-
155
target/arm/translate.h | 11 +
77
target/arm/cpu.h | 38 ++-
156
target/arm/sve.decode | 57 +-
78
target/arm/translate-a64.h | 9 -
157
hw/sd/allwinner-sdhost.c | 7 +
79
target/arm/translate.h | 26 ++
158
target/arm/hvf/hvf.c | 1 +
80
target/arm/neon-dp.decode | 86 +++++
159
target/arm/sve_helper.c | 6 +-
81
target/arm/neon-ls.decode | 52 +++
160
target/arm/translate-a64.c | 2 +-
82
target/arm/neon-shared.decode | 66 ++++
161
target/arm/translate-sve.c | 5367 +++++++++++++++--------------------------
83
hw/arm/mps2-tz.c | 2 +-
162
8 files changed, 2067 insertions(+), 3385 deletions(-)
84
hw/arm/xlnx-versal-virt.c | 74 ++++-
85
hw/arm/xlnx-versal.c | 115 +++++--
86
target/arm/cpu.c | 3 +-
87
target/arm/cpu64.c | 8 +-
88
target/arm/helper.c | 183 ++++------
89
target/arm/translate-a64.c | 17 -
90
target/arm/translate-neon.inc.c | 714 +++++++++++++++++++++++++++++++++++++++
91
target/arm/translate-vfp.inc.c | 6 -
92
target/arm/translate.c | 716 +++-------------------------------------
93
target/arm/Makefile.objs | 18 +
94
19 files changed, 1302 insertions(+), 864 deletions(-)
95
create mode 100644 target/arm/neon-dp.decode
96
create mode 100644 target/arm/neon-ls.decode
97
create mode 100644 target/arm/neon-shared.decode
98
create mode 100644 target/arm/translate-neon.inc.c
99
163
diff view generated by jsdifflib
1
Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping
1
In commit 5814d587fe861fe9 we added support for emulating
2
to decodetree.
2
FEAT_HCX (Support for the HCRX_EL2 register). However we
3
forgot to add it to the list in emulated.rst. Correct the
4
omission.
3
5
6
Fixes: 5814d587fe861fe9 ("target/arm: Enable FEAT_HCX for -cpu max")
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200430181003.21682-19-peter.maydell@linaro.org
9
Message-id: 20220520084320.424166-1-peter.maydell@linaro.org
7
---
10
---
8
target/arm/neon-dp.decode | 6 ++++++
11
docs/system/arm/emulation.rst | 1 +
9
target/arm/translate-neon.inc.c | 15 +++++++++++++++
12
1 file changed, 1 insertion(+)
10
target/arm/translate.c | 14 ++------------
11
3 files changed, 23 insertions(+), 12 deletions(-)
12
13
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
14
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
16
--- a/docs/system/arm/emulation.rst
16
+++ b/target/arm/neon-dp.decode
17
+++ b/docs/system/arm/emulation.rst
17
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
18
@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
19
- FEAT_FRINTTS (Floating-point to integer instructions)
19
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
20
- FEAT_FlagM (Flag manipulation instructions v2)
20
21
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
21
+VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
22
+- FEAT_HCX (Support for the HCRX_EL2 register)
22
+VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
23
- FEAT_HPDS (Hierarchical permission disables)
23
+
24
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
24
@3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \
25
- FEAT_IDST (ID space trap handling)
25
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
26
27
@@ -XXX,XX +XXX,XX @@ VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
28
VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
29
VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
30
31
+VQSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
32
+VQSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
33
+
34
VCGT_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
35
VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
36
VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
37
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate-neon.inc.c
40
+++ b/target/arm/translate-neon.inc.c
41
@@ -XXX,XX +XXX,XX @@ static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
42
tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);
43
}
44
DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)
45
+
46
+#define DO_3SAME_GVEC4(INSN, OPARRAY) \
47
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
48
+ uint32_t rn_ofs, uint32_t rm_ofs, \
49
+ uint32_t oprsz, uint32_t maxsz) \
50
+ { \
51
+ tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), \
52
+ rn_ofs, rm_ofs, oprsz, maxsz, &OPARRAY[vece]); \
53
+ } \
54
+ DO_3SAME(INSN, gen_##INSN##_3s)
55
+
56
+DO_3SAME_GVEC4(VQADD_S, sqadd_op)
57
+DO_3SAME_GVEC4(VQADD_U, uqadd_op)
58
+DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
59
+DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
60
diff --git a/target/arm/translate.c b/target/arm/translate.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/translate.c
63
+++ b/target/arm/translate.c
64
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
65
}
66
return 1;
67
68
- case NEON_3R_VQADD:
69
- tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
70
- rn_ofs, rm_ofs, vec_size, vec_size,
71
- (u ? uqadd_op : sqadd_op) + size);
72
- return 0;
73
-
74
- case NEON_3R_VQSUB:
75
- tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
76
- rn_ofs, rm_ofs, vec_size, vec_size,
77
- (u ? uqsub_op : sqsub_op) + size);
78
- return 0;
79
-
80
case NEON_3R_VMUL: /* VMUL */
81
if (u) {
82
/* Polynomial case allows only P8. */
83
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
84
case NEON_3R_VTST_VCEQ:
85
case NEON_3R_VCGT:
86
case NEON_3R_VCGE:
87
+ case NEON_3R_VQADD:
88
+ case NEON_3R_VQSUB:
89
/* Already handled by decodetree */
90
return 1;
91
}
92
--
26
--
93
2.20.1
27
2.25.1
94
95
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.
3
Fix when building HVF on macOS Aarch64:
4
Represent it in QEMU's ARMCPU struct with a uint64_t, not a
5
uint32_t.
6
4
7
This fixes an error when compiling with -Werror=conversion
5
target/arm/hvf/hvf.c:586:15: error: unknown type name 'ARMCPRegInfo'; did you mean 'ARMCPUInfo'?
8
because we were manipulating the register value using a
6
const ARMCPRegInfo *ri;
9
local uint64_t variable:
7
^~~~~~~~~~~~
8
ARMCPUInfo
9
target/arm/cpu-qom.h:38:3: note: 'ARMCPUInfo' declared here
10
} ARMCPUInfo;
11
^
12
target/arm/hvf/hvf.c:589:14: error: implicit declaration of function 'get_arm_cp_reginfo' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
13
ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
14
^
15
target/arm/hvf/hvf.c:589:12: warning: incompatible integer to pointer conversion assigning to 'const ARMCPUInfo *' (aka 'const struct ARMCPUInfo *') from 'int' [-Wint-conversion]
16
ri = get_arm_cp_reginfo(arm_cpu->cp_regs, key);
17
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
18
target/arm/hvf/hvf.c:591:26: error: no member named 'type' in 'struct ARMCPUInfo'
19
assert(!(ri->type & ARM_CP_NO_RAW));
20
~~ ^
21
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/usr/include/assert.h:99:25: note: expanded from macro 'assert'
22
(__builtin_expect(!(e), 0) ? __assert_rtn(__func__, __ASSERT_FILE_NAME, __LINE__, #e) : (void)0)
23
^
24
target/arm/hvf/hvf.c:591:33: error: use of undeclared identifier 'ARM_CP_NO_RAW'
25
assert(!(ri->type & ARM_CP_NO_RAW));
26
^
27
1 warning and 4 errors generated.
10
28
11
target/arm/cpu64.c: In function ‘aarch64_max_initfn’:
29
Fixes: cf7c6d1004 ("target/arm: Split out cpregs.h")
12
target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]
30
Reported-by: Duncan Bayne <duncan@bayne.id.au>
13
628 | cpu->midr = t;
14
| ^
15
16
and future-proofs us against a possible future architecture
17
change using some of the top 32 bits.
18
19
Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
20
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
31
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
22
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
32
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-id: 20200428172634.29707-1-f4bug@amsat.org
33
Message-id: 20220525161926.34233-1-philmd@fungible.com
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
34
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1029
35
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
36
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
---
37
---
27
target/arm/cpu.h | 2 +-
38
target/arm/hvf/hvf.c | 1 +
28
target/arm/cpu.c | 2 +-
39
1 file changed, 1 insertion(+)
29
2 files changed, 2 insertions(+), 2 deletions(-)
30
40
31
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
41
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
32
index XXXXXXX..XXXXXXX 100644
42
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/cpu.h
43
--- a/target/arm/hvf/hvf.c
34
+++ b/target/arm/cpu.h
44
+++ b/target/arm/hvf/hvf.c
35
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
45
@@ -XXX,XX +XXX,XX @@
36
uint64_t id_aa64dfr0;
46
#include "sysemu/hvf_int.h"
37
uint64_t id_aa64dfr1;
47
#include "sysemu/hw_accel.h"
38
} isar;
48
#include "hvf_arm.h"
39
- uint32_t midr;
49
+#include "cpregs.h"
40
+ uint64_t midr;
50
41
uint32_t revidr;
51
#include <mach/mach_time.h>
42
uint32_t reset_fpsid;
52
43
uint32_t ctr;
44
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu.c
47
+++ b/target/arm/cpu.c
48
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
49
static Property arm_cpu_properties[] = {
50
DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
51
DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
52
- DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
53
+ DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
54
DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
55
mp_affinity, ARM64_AFFINITY_INVALID),
56
DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
57
--
53
--
58
2.20.1
54
2.25.1
59
55
60
56
diff view generated by jsdifflib
1
Convert the Neon comparison ops in the 3-reg-same grouping
1
From: Icenowy Zheng <uwu@icenowy.me>
2
to decodetree.
3
2
3
U-Boot queries the FIFO water level to reduce checking status register
4
when doing PIO SD card operation.
5
6
Report a FIFO water level of 1 when data is ready, to prevent the code
7
from trying to read 0 words from the FIFO each time.
8
9
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
10
Message-id: 20220520124200.2112699-1-uwu@icenowy.me
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200430181003.21682-18-peter.maydell@linaro.org
7
---
13
---
8
target/arm/neon-dp.decode | 8 ++++++++
14
hw/sd/allwinner-sdhost.c | 7 +++++++
9
target/arm/translate-neon.inc.c | 22 ++++++++++++++++++++++
15
1 file changed, 7 insertions(+)
10
target/arm/translate.c | 23 +++--------------------
11
3 files changed, 33 insertions(+), 20 deletions(-)
12
16
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
17
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
19
--- a/hw/sd/allwinner-sdhost.c
16
+++ b/target/arm/neon-dp.decode
20
+++ b/hw/sd/allwinner-sdhost.c
17
@@ -XXX,XX +XXX,XX @@ VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
21
@@ -XXX,XX +XXX,XX @@ enum {
18
VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
22
};
19
VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
23
20
24
enum {
21
+VCGT_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
25
+ SD_STAR_FIFO_EMPTY = (1 << 2),
22
+VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
26
SD_STAR_CARD_PRESENT = (1 << 8),
23
+VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
27
+ SD_STAR_FIFO_LEVEL_1 = (1 << 17),
24
+VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
28
};
25
+
29
26
VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
30
enum {
27
VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
31
@@ -XXX,XX +XXX,XX @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
28
VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
32
break;
29
@@ -XXX,XX +XXX,XX @@ VMIN_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
33
case REG_SD_STAR: /* Status */
30
34
res = s->status;
31
VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
35
+ if (sdbus_data_ready(&s->sdbus)) {
32
VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
36
+ res |= SD_STAR_FIFO_LEVEL_1;
33
+
37
+ } else {
34
+VTST_3s 1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
38
+ res |= SD_STAR_FIFO_EMPTY;
35
+VCEQ_3s 1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
39
+ }
36
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
40
break;
37
index XXXXXXX..XXXXXXX 100644
41
case REG_SD_FWLR: /* FIFO Water Level */
38
--- a/target/arm/translate-neon.inc.c
42
res = s->fifo_wlevel;
39
+++ b/target/arm/translate-neon.inc.c
40
@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
41
DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
42
DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
43
DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
44
+
45
+#define DO_3SAME_CMP(INSN, COND) \
46
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
47
+ uint32_t rn_ofs, uint32_t rm_ofs, \
48
+ uint32_t oprsz, uint32_t maxsz) \
49
+ { \
50
+ tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \
51
+ } \
52
+ DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
53
+
54
+DO_3SAME_CMP(VCGT_S, TCG_COND_GT)
55
+DO_3SAME_CMP(VCGT_U, TCG_COND_GTU)
56
+DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
57
+DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
58
+DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
59
+
60
+static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
61
+ uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
62
+{
63
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);
64
+}
65
+DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)
66
diff --git a/target/arm/translate.c b/target/arm/translate.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/translate.c
69
+++ b/target/arm/translate.c
70
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
71
u ? &mls_op[size] : &mla_op[size]);
72
return 0;
73
74
- case NEON_3R_VTST_VCEQ:
75
- if (u) { /* VCEQ */
76
- tcg_gen_gvec_cmp(TCG_COND_EQ, size, rd_ofs, rn_ofs, rm_ofs,
77
- vec_size, vec_size);
78
- } else { /* VTST */
79
- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
80
- vec_size, vec_size, &cmtst_op[size]);
81
- }
82
- return 0;
83
-
84
- case NEON_3R_VCGT:
85
- tcg_gen_gvec_cmp(u ? TCG_COND_GTU : TCG_COND_GT, size,
86
- rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
87
- return 0;
88
-
89
- case NEON_3R_VCGE:
90
- tcg_gen_gvec_cmp(u ? TCG_COND_GEU : TCG_COND_GE, size,
91
- rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
92
- return 0;
93
-
94
case NEON_3R_VSHL:
95
/* Note the operation is vshl vd,vm,vn */
96
tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
97
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
98
case NEON_3R_LOGIC:
99
case NEON_3R_VMAX:
100
case NEON_3R_VMIN:
101
+ case NEON_3R_VTST_VCEQ:
102
+ case NEON_3R_VCGT:
103
+ case NEON_3R_VCGE:
104
/* Already handled by decodetree */
105
return 1;
106
}
107
--
43
--
108
2.20.1
44
2.25.1
109
110
diff view generated by jsdifflib
1
We're going to want at least some of the NeonGen* typedefs
1
From: Richard Henderson <richard.henderson@linaro.org>
2
for the refactored 32-bit Neon decoder, so move them all
3
to translate.h since it makes more sense to keep them in
4
one group.
5
2
3
Steal the idea for these leaf function expanders from PowerPC.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-2-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200430181003.21682-23-peter.maydell@linaro.org
9
---
9
---
10
target/arm/translate.h | 17 +++++++++++++++++
10
target/arm/translate.h | 11 +++++++++++
11
target/arm/translate-a64.c | 17 -----------------
11
1 file changed, 11 insertions(+)
12
2 files changed, 17 insertions(+), 17 deletions(-)
13
12
14
diff --git a/target/arm/translate.h b/target/arm/translate.h
13
diff --git a/target/arm/translate.h b/target/arm/translate.h
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.h
15
--- a/target/arm/translate.h
17
+++ b/target/arm/translate.h
16
+++ b/target/arm/translate.h
18
@@ -XXX,XX +XXX,XX @@ typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
17
@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
19
typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
18
*/
20
uint32_t, uint32_t, uint32_t);
19
uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
21
20
22
+/* Function prototype for gen_ functions for calling Neon helpers */
21
+/*
23
+typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
22
+ * Helpers for implementing sets of trans_* functions.
24
+typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
23
+ * Defer the implementation of NAME to FUNC, with optional extra arguments.
25
+typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
24
+ */
26
+typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
25
+#define TRANS(NAME, FUNC, ...) \
27
+typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
26
+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
28
+typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
27
+ { return FUNC(s, __VA_ARGS__); }
29
+typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
28
+#define TRANS_FEAT(NAME, FEAT, FUNC, ...) \
30
+typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
29
+ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
31
+typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
30
+ { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
32
+typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
33
+typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
34
+typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
35
+typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
36
+typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
37
+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
38
+
31
+
39
#endif /* TARGET_ARM_TRANSLATE_H */
32
#endif /* TARGET_ARM_TRANSLATE_H */
40
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate-a64.c
43
+++ b/target/arm/translate-a64.c
44
@@ -XXX,XX +XXX,XX @@ typedef struct AArch64DecodeTable {
45
AArch64DecodeFn *disas_fn;
46
} AArch64DecodeTable;
47
48
-/* Function prototype for gen_ functions for calling Neon helpers */
49
-typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
50
-typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
51
-typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
52
-typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
53
-typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
54
-typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
55
-typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
56
-typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
57
-typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
58
-typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
59
-typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
60
-typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
61
-typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
62
-typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
63
-typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
64
-
65
/* initialize TCG globals. */
66
void a64_translate_init(void)
67
{
68
--
33
--
69
2.20.1
34
2.25.1
70
71
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-3-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 36 +++++++++++++++---------------------
9
1 file changed, 15 insertions(+), 21 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static int pred_gvec_reg_size(DisasContext *s)
16
}
17
18
/* Invoke an out-of-line helper on 2 Zregs. */
19
-static void gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
20
+static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
21
int rd, int rn, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vsz, vsz, data, fn);
27
+ if (fn == NULL) {
28
+ return false;
29
+ }
30
+ if (sve_access_check(s)) {
31
+ unsigned vsz = vec_full_reg_size(s);
32
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, rd),
33
+ vec_full_reg_offset(s, rn),
34
+ vsz, vsz, data, fn);
35
+ }
36
+ return true;
37
}
38
39
/* Invoke an out-of-line helper on 3 Zregs. */
40
@@ -XXX,XX +XXX,XX @@ static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
41
gen_helper_sve_fexpa_s,
42
gen_helper_sve_fexpa_d,
43
};
44
- if (a->esz == 0) {
45
- return false;
46
- }
47
- if (sve_access_check(s)) {
48
- gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
49
- }
50
- return true;
51
+ return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
52
}
53
54
static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
55
@@ -XXX,XX +XXX,XX @@ static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
56
gen_helper_sve_rev_b, gen_helper_sve_rev_h,
57
gen_helper_sve_rev_s, gen_helper_sve_rev_d
58
};
59
-
60
- if (sve_access_check(s)) {
61
- gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
62
- }
63
- return true;
64
+ return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
65
}
66
67
static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
68
@@ -XXX,XX +XXX,XX @@ static bool trans_AESMC(DisasContext *s, arg_AESMC *a)
69
if (!dc_isar_feature(aa64_sve2_aes, s)) {
70
return false;
71
}
72
- if (sve_access_check(s)) {
73
- gen_gvec_ool_zz(s, gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt);
74
- }
75
- return true;
76
+ return gen_gvec_ool_zz(s, gen_helper_crypto_aesmc,
77
+ a->rd, a->rd, a->decrypt);
78
}
79
80
static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
81
--
82
2.25.1
diff view generated by jsdifflib
1
Convert the Neon "load/store single structure to one lane" insns to
1
From: Richard Henderson <richard.henderson@linaro.org>
2
decodetree.
3
2
4
As this is the last set of insns in the neon load/store group,
3
Convert SVE translation functions using gen_gvec_ool_zz to TRANS_FEAT.
5
we can remove the whole disas_neon_ls_insn() function.
6
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-4-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200430181003.21682-14-peter.maydell@linaro.org
10
---
9
---
11
target/arm/neon-ls.decode | 11 +++
10
target/arm/translate-sve.c | 39 +++++++++++++-------------------------
12
target/arm/translate-neon.inc.c | 89 +++++++++++++++++++
11
1 file changed, 13 insertions(+), 26 deletions(-)
13
target/arm/translate.c | 147 --------------------------------
14
3 files changed, 100 insertions(+), 147 deletions(-)
15
12
16
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/neon-ls.decode
15
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/neon-ls.decode
16
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
17
@@ -XXX,XX +XXX,XX @@ static bool trans_ADR_u32(DisasContext *s, arg_rrri *a)
21
18
*** SVE Integer Misc - Unpredicated Group
22
VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
23
vd=%vd_dp
24
+
25
+# Neon load/store single structure to one lane
26
+%imm1_5_p1 5:1 !function=plus1
27
+%imm1_6_p1 6:1 !function=plus1
28
+
29
+VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
30
+ vd=%vd_dp size=0 stride=1
31
+VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \
32
+ vd=%vd_dp size=1 stride=%imm1_5_p1
33
+VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \
34
+ vd=%vd_dp size=2 stride=%imm1_6_p1
35
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
36
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/translate-neon.inc.c
38
+++ b/target/arm/translate-neon.inc.c
39
@@ -XXX,XX +XXX,XX @@
40
* It might be possible to convert it to a standalone .c file eventually.
41
*/
19
*/
42
20
43
+static inline int plus1(DisasContext *s, int x)
21
-static bool trans_FEXPA(DisasContext *s, arg_rr_esz *a)
44
+{
22
-{
45
+ return x + 1;
23
- static gen_helper_gvec_2 * const fns[4] = {
46
+}
24
- NULL,
47
+
25
- gen_helper_sve_fexpa_h,
48
/* Include the generated Neon decoder */
26
- gen_helper_sve_fexpa_s,
49
#include "decode-neon-dp.inc.c"
27
- gen_helper_sve_fexpa_d,
50
#include "decode-neon-ls.inc.c"
28
- };
51
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
29
- return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
52
30
-}
31
+static gen_helper_gvec_2 * const fexpa_fns[4] = {
32
+ NULL, gen_helper_sve_fexpa_h,
33
+ gen_helper_sve_fexpa_s, gen_helper_sve_fexpa_d,
34
+};
35
+TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
36
+ fexpa_fns[a->esz], a->rd, a->rn, 0)
37
38
static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
39
{
40
@@ -XXX,XX +XXX,XX @@ static bool trans_INSR_r(DisasContext *s, arg_rrr_esz *a)
53
return true;
41
return true;
54
}
42
}
55
+
43
56
+static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
44
-static bool trans_REV_v(DisasContext *s, arg_rr_esz *a)
57
+{
45
-{
58
+ /* Neon load/store single structure to one lane */
46
- static gen_helper_gvec_2 * const fns[4] = {
59
+ int reg;
47
- gen_helper_sve_rev_b, gen_helper_sve_rev_h,
60
+ int nregs = a->n + 1;
48
- gen_helper_sve_rev_s, gen_helper_sve_rev_d
61
+ int vd = a->vd;
49
- };
62
+ TCGv_i32 addr, tmp;
50
- return gen_gvec_ool_zz(s, fns[a->esz], a->rd, a->rn, 0);
63
+
51
-}
64
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
52
+static gen_helper_gvec_2 * const rev_fns[4] = {
65
+ return false;
53
+ gen_helper_sve_rev_b, gen_helper_sve_rev_h,
66
+ }
54
+ gen_helper_sve_rev_s, gen_helper_sve_rev_d
67
+
55
+};
68
+ /* UNDEF accesses to D16-D31 if they don't exist */
56
+TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn, 0)
69
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
57
70
+ return false;
58
static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
71
+ }
59
{
72
+
60
@@ -XXX,XX +XXX,XX @@ static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
73
+ /* Catch the UNDEF cases. This is unavoidably a bit messy. */
61
return true;
74
+ switch (nregs) {
75
+ case 1:
76
+ if (((a->align & (1 << a->size)) != 0) ||
77
+ (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
78
+ return false;
79
+ }
80
+ break;
81
+ case 3:
82
+ if ((a->align & 1) != 0) {
83
+ return false;
84
+ }
85
+ /* fall through */
86
+ case 2:
87
+ if (a->size == 2 && (a->align & 2) != 0) {
88
+ return false;
89
+ }
90
+ break;
91
+ case 4:
92
+ if ((a->size == 2) && ((a->align & 3) == 3)) {
93
+ return false;
94
+ }
95
+ break;
96
+ default:
97
+ abort();
98
+ }
99
+ if ((vd + a->stride * (nregs - 1)) > 31) {
100
+ /*
101
+ * Attempts to write off the end of the register file are
102
+ * UNPREDICTABLE; we choose to UNDEF because otherwise we would
103
+ * access off the end of the array that holds the register data.
104
+ */
105
+ return false;
106
+ }
107
+
108
+ if (!vfp_access_check(s)) {
109
+ return true;
110
+ }
111
+
112
+ tmp = tcg_temp_new_i32();
113
+ addr = tcg_temp_new_i32();
114
+ load_reg_var(s, addr, a->rn);
115
+ /*
116
+ * TODO: if we implemented alignment exceptions, we should check
117
+ * addr against the alignment encoded in a->align here.
118
+ */
119
+ for (reg = 0; reg < nregs; reg++) {
120
+ if (a->l) {
121
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
122
+ s->be_data | a->size);
123
+ neon_store_element(vd, a->reg_idx, a->size, tmp);
124
+ } else { /* Store */
125
+ neon_load_element(tmp, vd, a->reg_idx, a->size);
126
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
127
+ s->be_data | a->size);
128
+ }
129
+ vd += a->stride;
130
+ tcg_gen_addi_i32(addr, addr, 1 << a->size);
131
+ }
132
+ tcg_temp_free_i32(addr);
133
+ tcg_temp_free_i32(tmp);
134
+
135
+ gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs);
136
+
137
+ return true;
138
+}
139
diff --git a/target/arm/translate.c b/target/arm/translate.c
140
index XXXXXXX..XXXXXXX 100644
141
--- a/target/arm/translate.c
142
+++ b/target/arm/translate.c
143
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
144
tcg_temp_free_i32(rd);
145
}
62
}
146
63
147
-
64
-static bool trans_AESMC(DisasContext *s, arg_AESMC *a)
148
-/* Translate a NEON load/store element instruction. Return nonzero if the
149
- instruction is invalid. */
150
-static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
151
-{
65
-{
152
- int rd, rn, rm;
66
- if (!dc_isar_feature(aa64_sve2_aes, s)) {
153
- int nregs;
67
- return false;
154
- int stride;
155
- int size;
156
- int reg;
157
- int load;
158
- TCGv_i32 addr;
159
- TCGv_i32 tmp;
160
-
161
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
162
- return 1;
163
- }
68
- }
164
-
69
- return gen_gvec_ool_zz(s, gen_helper_crypto_aesmc,
165
- /* FIXME: this access check should not take precedence over UNDEF
70
- a->rd, a->rd, a->decrypt);
166
- * for invalid encodings; we will generate incorrect syndrome information
167
- * for attempts to execute invalid vfp/neon encodings with FP disabled.
168
- */
169
- if (s->fp_excp_el) {
170
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
171
- syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
172
- return 0;
173
- }
174
-
175
- if (!s->vfp_enabled)
176
- return 1;
177
- VFP_DREG_D(rd, insn);
178
- rn = (insn >> 16) & 0xf;
179
- rm = insn & 0xf;
180
- load = (insn & (1 << 21)) != 0;
181
- if ((insn & (1 << 23)) == 0) {
182
- /* Load store all elements -- handled already by decodetree */
183
- return 1;
184
- } else {
185
- size = (insn >> 10) & 3;
186
- if (size == 3) {
187
- /* Load single element to all lanes -- handled by decodetree */
188
- return 1;
189
- } else {
190
- /* Single element. */
191
- int idx = (insn >> 4) & 0xf;
192
- int reg_idx;
193
- switch (size) {
194
- case 0:
195
- reg_idx = (insn >> 5) & 7;
196
- stride = 1;
197
- break;
198
- case 1:
199
- reg_idx = (insn >> 6) & 3;
200
- stride = (insn & (1 << 5)) ? 2 : 1;
201
- break;
202
- case 2:
203
- reg_idx = (insn >> 7) & 1;
204
- stride = (insn & (1 << 6)) ? 2 : 1;
205
- break;
206
- default:
207
- abort();
208
- }
209
- nregs = ((insn >> 8) & 3) + 1;
210
- /* Catch the UNDEF cases. This is unavoidably a bit messy. */
211
- switch (nregs) {
212
- case 1:
213
- if (((idx & (1 << size)) != 0) ||
214
- (size == 2 && ((idx & 3) == 1 || (idx & 3) == 2))) {
215
- return 1;
216
- }
217
- break;
218
- case 3:
219
- if ((idx & 1) != 0) {
220
- return 1;
221
- }
222
- /* fall through */
223
- case 2:
224
- if (size == 2 && (idx & 2) != 0) {
225
- return 1;
226
- }
227
- break;
228
- case 4:
229
- if ((size == 2) && ((idx & 3) == 3)) {
230
- return 1;
231
- }
232
- break;
233
- default:
234
- abort();
235
- }
236
- if ((rd + stride * (nregs - 1)) > 31) {
237
- /* Attempts to write off the end of the register file
238
- * are UNPREDICTABLE; we choose to UNDEF because otherwise
239
- * the neon_load_reg() would write off the end of the array.
240
- */
241
- return 1;
242
- }
243
- tmp = tcg_temp_new_i32();
244
- addr = tcg_temp_new_i32();
245
- load_reg_var(s, addr, rn);
246
- for (reg = 0; reg < nregs; reg++) {
247
- if (load) {
248
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
249
- s->be_data | size);
250
- neon_store_element(rd, reg_idx, size, tmp);
251
- } else { /* Store */
252
- neon_load_element(tmp, rd, reg_idx, size);
253
- gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
254
- s->be_data | size);
255
- }
256
- rd += stride;
257
- tcg_gen_addi_i32(addr, addr, 1 << size);
258
- }
259
- tcg_temp_free_i32(addr);
260
- tcg_temp_free_i32(tmp);
261
- stride = nregs * (1 << size);
262
- }
263
- }
264
- if (rm != 15) {
265
- TCGv_i32 base;
266
-
267
- base = load_reg(s, rn);
268
- if (rm == 13) {
269
- tcg_gen_addi_i32(base, base, stride);
270
- } else {
271
- TCGv_i32 index;
272
- index = load_reg(s, rm);
273
- tcg_gen_add_i32(base, base, index);
274
- tcg_temp_free_i32(index);
275
- }
276
- store_reg(s, rn, base);
277
- }
278
- return 0;
279
-}
71
-}
280
-
72
+TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
281
static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
73
+ gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
74
75
static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
282
{
76
{
283
switch (size) {
284
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
285
}
286
return;
287
}
288
- if ((insn & 0x0f100000) == 0x04000000) {
289
- /* NEON load/store. */
290
- if (disas_neon_ls_insn(s, insn)) {
291
- goto illegal_op;
292
- }
293
- return;
294
- }
295
if ((insn & 0x0e000f00) == 0x0c000100) {
296
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
297
/* iWMMXt register transfer. */
298
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
299
}
300
break;
301
case 12:
302
- if ((insn & 0x01100000) == 0x01000000) {
303
- if (disas_neon_ls_insn(s, insn)) {
304
- goto illegal_op;
305
- }
306
- break;
307
- }
308
goto illegal_op;
309
default:
310
illegal_op:
311
--
77
--
312
2.20.1
78
2.25.1
313
314
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-5-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 74 ++++++++++++--------------------------
9
1 file changed, 23 insertions(+), 51 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 3 Zregs. */
19
-static void gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
20
+static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
21
int rd, int rn, int rm, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm),
27
- vsz, vsz, data, fn);
28
+ if (fn == NULL) {
29
+ return false;
30
+ }
31
+ if (sve_access_check(s)) {
32
+ unsigned vsz = vec_full_reg_size(s);
33
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
34
+ vec_full_reg_offset(s, rn),
35
+ vec_full_reg_offset(s, rm),
36
+ vsz, vsz, data, fn);
37
+ }
38
+ return true;
39
}
40
41
/* Invoke an out-of-line helper on 4 Zregs. */
42
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
43
44
static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
45
{
46
- if (fn == NULL) {
47
- return false;
48
- }
49
- if (sve_access_check(s)) {
50
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
51
- }
52
- return true;
53
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
54
}
55
56
#define DO_ZZW(NAME, name) \
57
@@ -XXX,XX +XXX,XX @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
58
59
static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
60
{
61
- if (sve_access_check(s)) {
62
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
63
- }
64
- return true;
65
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
66
}
67
68
static bool trans_ADR_p32(DisasContext *s, arg_rrri *a)
69
@@ -XXX,XX +XXX,XX @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
70
gen_helper_sve_ftssel_s,
71
gen_helper_sve_ftssel_d,
72
};
73
- if (a->esz == 0) {
74
- return false;
75
- }
76
- if (sve_access_check(s)) {
77
- gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
78
- }
79
- return true;
80
+ return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
81
}
82
83
/*
84
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
85
gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
86
gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
87
};
88
-
89
- if (sve_access_check(s)) {
90
- gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
91
- }
92
- return true;
93
+ return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
94
}
95
96
static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
97
@@ -XXX,XX +XXX,XX @@ static bool trans_TBX(DisasContext *s, arg_rrr_esz *a)
98
if (!dc_isar_feature(aa64_sve2, s)) {
99
return false;
100
}
101
- if (sve_access_check(s)) {
102
- gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
103
- }
104
- return true;
105
+ return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
106
}
107
108
static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
109
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
110
static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
111
gen_helper_gvec_3 *fn)
112
{
113
- if (sve_access_check(s)) {
114
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
115
- }
116
- return true;
117
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
118
}
119
120
static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
121
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
122
static bool do_sve2_zzz_ool(DisasContext *s, arg_rrr_esz *a,
123
gen_helper_gvec_3 *fn)
124
{
125
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
126
+ if (!dc_isar_feature(aa64_sve2, s)) {
127
return false;
128
}
129
- if (sve_access_check(s)) {
130
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
131
- }
132
- return true;
133
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
134
}
135
136
static bool trans_SMULH_zzz(DisasContext *s, arg_rrr_esz *a)
137
@@ -XXX,XX +XXX,XX @@ static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
138
if (!dc_isar_feature(aa64_sve2_aes, s)) {
139
return false;
140
}
141
- if (sve_access_check(s)) {
142
- gen_gvec_ool_zzz(s, gen_helper_crypto_aese,
143
- a->rd, a->rn, a->rm, decrypt);
144
- }
145
- return true;
146
+ return gen_gvec_ool_zzz(s, gen_helper_crypto_aese,
147
+ a->rd, a->rn, a->rm, decrypt);
148
}
149
150
static bool trans_AESE(DisasContext *s, arg_rrr_esz *a)
151
@@ -XXX,XX +XXX,XX @@ static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
152
if (!dc_isar_feature(aa64_sve2_sm4, s)) {
153
return false;
154
}
155
- if (sve_access_check(s)) {
156
- gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
157
- }
158
- return true;
159
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
160
}
161
162
static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
163
--
164
2.25.1
diff view generated by jsdifflib
1
Convert the VFM[AS]L (vector) insns to decodetree. This is the last
1
From: Richard Henderson <richard.henderson@linaro.org>
2
insn in the legacy decoder for the 3same_ext group, so we can
3
delete the legacy decoder function for the group entirely.
4
2
5
Note that in disas_thumb2_insn() the parts of this encoding space
3
Use gen_gvec_ool_arg_zzz instead of gen_gvec_ool_zzz
6
where the decodetree decoder returns false will correctly be directed
4
when the arguments come from arg_rrr_esz.
7
to illegal_op by the "(insn & (1 << 28))" check so they won't fall
5
Replaces do_zzw_ool and do_zzz_data_ool.
8
into disas_coproc_insn() by mistake.
9
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-6-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200430181003.21682-8-peter.maydell@linaro.org
13
---
11
---
14
target/arm/neon-shared.decode | 6 +++
12
target/arm/translate-sve.c | 48 +++++++++++++++++---------------------
15
target/arm/translate-neon.inc.c | 31 +++++++++++
13
1 file changed, 21 insertions(+), 27 deletions(-)
16
target/arm/translate.c | 92 +--------------------------------
17
3 files changed, 38 insertions(+), 91 deletions(-)
18
14
19
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
20
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/neon-shared.decode
17
--- a/target/arm/translate-sve.c
22
+++ b/target/arm/neon-shared.decode
18
+++ b/target/arm/translate-sve.c
23
@@ -XXX,XX +XXX,XX @@ VCADD 1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
24
# VUDOT and VSDOT
25
VDOT 1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
26
vm=%vm_dp vn=%vn_dp vd=%vd_dp
27
+
28
+# VFM[AS]L
29
+VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
30
+ vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0
31
+VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
32
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
33
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate-neon.inc.c
36
+++ b/target/arm/translate-neon.inc.c
37
@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
38
opr_sz, opr_sz, 0, fn_gvec);
39
return true;
20
return true;
40
}
21
}
22
23
+static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
24
+ arg_rrr_esz *a, int data)
25
+{
26
+ return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
27
+}
41
+
28
+
42
+static bool trans_VFML(DisasContext *s, arg_VFML *a)
29
/* Invoke an out-of-line helper on 4 Zregs. */
43
+{
30
static void gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
44
+ int opr_sz;
31
int rd, int rn, int rm, int ra, int data)
45
+
32
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
46
+ if (!dc_isar_feature(aa32_fhm, s)) {
33
return do_shift_imm(s, a, false, tcg_gen_gvec_shli);
47
+ return false;
48
+ }
49
+
50
+ /* UNDEF accesses to D16-D31 if they don't exist. */
51
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
52
+ (a->vd & 0x10)) {
53
+ return false;
54
+ }
55
+
56
+ if (a->vd & a->q) {
57
+ return false;
58
+ }
59
+
60
+ if (!vfp_access_check(s)) {
61
+ return true;
62
+ }
63
+
64
+ opr_sz = (1 + a->q) * 8;
65
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
66
+ vfp_reg_offset(a->q, a->vn),
67
+ vfp_reg_offset(a->q, a->vm),
68
+ cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
69
+ gen_helper_gvec_fmlal_a32);
70
+ return true;
71
+}
72
diff --git a/target/arm/translate.c b/target/arm/translate.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/arm/translate.c
75
+++ b/target/arm/translate.c
76
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
77
return 0;
78
}
34
}
79
35
80
-/* Advanced SIMD three registers of the same length extension.
36
-static bool do_zzw_ool(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
81
- * 31 25 23 22 20 16 12 11 10 9 8 3 0
82
- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
83
- * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
84
- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
85
- */
86
-static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
87
-{
37
-{
88
- gen_helper_gvec_3 *fn_gvec = NULL;
38
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
89
- gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
90
- int rd, rn, rm, opr_sz;
91
- int data = 0;
92
- int off_rn, off_rm;
93
- bool is_long = false, q = extract32(insn, 6, 1);
94
- bool ptr_is_env = false;
95
-
96
- if ((insn & 0xff300f10) == 0xfc200810) {
97
- /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
98
- int is_s = extract32(insn, 23, 1);
99
- if (!dc_isar_feature(aa32_fhm, s)) {
100
- return 1;
101
- }
102
- is_long = true;
103
- data = is_s; /* is_2 == 0 */
104
- fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
105
- ptr_is_env = true;
106
- } else {
107
- return 1;
108
- }
109
-
110
- VFP_DREG_D(rd, insn);
111
- if (rd & q) {
112
- return 1;
113
- }
114
- if (q || !is_long) {
115
- VFP_DREG_N(rn, insn);
116
- VFP_DREG_M(rm, insn);
117
- if ((rn | rm) & q & !is_long) {
118
- return 1;
119
- }
120
- off_rn = vfp_reg_offset(1, rn);
121
- off_rm = vfp_reg_offset(1, rm);
122
- } else {
123
- rn = VFP_SREG_N(insn);
124
- rm = VFP_SREG_M(insn);
125
- off_rn = vfp_reg_offset(0, rn);
126
- off_rm = vfp_reg_offset(0, rm);
127
- }
128
-
129
- if (s->fp_excp_el) {
130
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
131
- syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
132
- return 0;
133
- }
134
- if (!s->vfp_enabled) {
135
- return 1;
136
- }
137
-
138
- opr_sz = (1 + q) * 8;
139
- if (fn_gvec_ptr) {
140
- TCGv_ptr ptr;
141
- if (ptr_is_env) {
142
- ptr = cpu_env;
143
- } else {
144
- ptr = get_fpstatus_ptr(1);
145
- }
146
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
147
- opr_sz, opr_sz, data, fn_gvec_ptr);
148
- if (!ptr_is_env) {
149
- tcg_temp_free_ptr(ptr);
150
- }
151
- } else {
152
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
153
- opr_sz, opr_sz, data, fn_gvec);
154
- }
155
- return 0;
156
-}
39
-}
157
-
40
-
158
/* Advanced SIMD two registers and a scalar extension.
41
#define DO_ZZW(NAME, name) \
159
* 31 24 23 22 20 16 12 11 10 9 8 3 0
42
static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \
160
* +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
43
{ \
161
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
44
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \
162
}
45
gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \
163
}
46
gen_helper_sve_##name##_zzw_s, NULL \
164
}
47
}; \
165
- } else if ((insn & 0x0e000a00) == 0x0c000800
48
- return do_zzw_ool(s, a, fns[a->esz]); \
166
- && arm_dc_feature(s, ARM_FEATURE_V8)) {
49
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0); \
167
- if (disas_neon_insn_3same_ext(s, insn)) {
50
}
168
- goto illegal_op;
51
169
- }
52
DO_ZZW(ASR, asr)
170
- return;
53
@@ -XXX,XX +XXX,XX @@ static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
171
} else if ((insn & 0x0f000a00) == 0x0e000800
54
gen_helper_sve_ftssel_s,
172
&& arm_dc_feature(s, ARM_FEATURE_V8)) {
55
gen_helper_sve_ftssel_d,
173
if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
56
};
174
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
57
- return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
175
}
58
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
176
break;
59
}
177
}
60
178
- if ((insn & 0xfe000a00) == 0xfc000800
61
/*
179
+ if ((insn & 0xff000a00) == 0xfe000800
62
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
180
&& arm_dc_feature(s, ARM_FEATURE_V8)) {
63
gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
181
/* The Thumb2 and ARM encodings are identical. */
64
gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
182
- if (disas_neon_insn_3same_ext(s, insn)) {
65
};
183
- goto illegal_op;
66
- return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
184
- }
67
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
185
- } else if ((insn & 0xff000a00) == 0xfe000800
68
}
186
- && arm_dc_feature(s, ARM_FEATURE_V8)) {
69
187
- /* The Thumb2 and ARM encodings are identical. */
70
static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
188
if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
71
@@ -XXX,XX +XXX,XX @@ static bool trans_TBX(DisasContext *s, arg_rrr_esz *a)
189
goto illegal_op;
72
if (!dc_isar_feature(aa64_sve2, s)) {
190
}
73
return false;
74
}
75
- return gen_gvec_ool_zzz(s, fns[a->esz], a->rd, a->rn, a->rm, 0);
76
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
77
}
78
79
static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
80
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
81
return true;
82
}
83
84
-static bool do_zzz_data_ool(DisasContext *s, arg_rrr_esz *a, int data,
85
- gen_helper_gvec_3 *fn)
86
-{
87
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
88
-}
89
-
90
static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
91
{
92
return do_zip(s, a, false);
93
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const uzp_fns[4] = {
94
95
static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a)
96
{
97
- return do_zzz_data_ool(s, a, 0, uzp_fns[a->esz]);
98
+ return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 0);
99
}
100
101
static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a)
102
{
103
- return do_zzz_data_ool(s, a, 1 << a->esz, uzp_fns[a->esz]);
104
+ return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 1 << a->esz);
105
}
106
107
static bool trans_UZP1_q(DisasContext *s, arg_rrr_esz *a)
108
@@ -XXX,XX +XXX,XX @@ static bool trans_UZP1_q(DisasContext *s, arg_rrr_esz *a)
109
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
110
return false;
111
}
112
- return do_zzz_data_ool(s, a, 0, gen_helper_sve2_uzp_q);
113
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 0);
114
}
115
116
static bool trans_UZP2_q(DisasContext *s, arg_rrr_esz *a)
117
@@ -XXX,XX +XXX,XX @@ static bool trans_UZP2_q(DisasContext *s, arg_rrr_esz *a)
118
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
119
return false;
120
}
121
- return do_zzz_data_ool(s, a, 16, gen_helper_sve2_uzp_q);
122
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 16);
123
}
124
125
static gen_helper_gvec_3 * const trn_fns[4] = {
126
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const trn_fns[4] = {
127
128
static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a)
129
{
130
- return do_zzz_data_ool(s, a, 0, trn_fns[a->esz]);
131
+ return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 0);
132
}
133
134
static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a)
135
{
136
- return do_zzz_data_ool(s, a, 1 << a->esz, trn_fns[a->esz]);
137
+ return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 1 << a->esz);
138
}
139
140
static bool trans_TRN1_q(DisasContext *s, arg_rrr_esz *a)
141
@@ -XXX,XX +XXX,XX @@ static bool trans_TRN1_q(DisasContext *s, arg_rrr_esz *a)
142
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
143
return false;
144
}
145
- return do_zzz_data_ool(s, a, 0, gen_helper_sve2_trn_q);
146
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 0);
147
}
148
149
static bool trans_TRN2_q(DisasContext *s, arg_rrr_esz *a)
150
@@ -XXX,XX +XXX,XX @@ static bool trans_TRN2_q(DisasContext *s, arg_rrr_esz *a)
151
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
152
return false;
153
}
154
- return do_zzz_data_ool(s, a, 16, gen_helper_sve2_trn_q);
155
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 16);
156
}
157
158
/*
159
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zzz_ool(DisasContext *s, arg_rrr_esz *a,
160
if (!dc_isar_feature(aa64_sve2, s)) {
161
return false;
162
}
163
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
164
+ return gen_gvec_ool_arg_zzz(s, fn, a, 0);
165
}
166
167
static bool trans_SMULH_zzz(DisasContext *s, arg_rrr_esz *a)
168
@@ -XXX,XX +XXX,XX @@ static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
169
if (!dc_isar_feature(aa64_sve2_aes, s)) {
170
return false;
171
}
172
- return gen_gvec_ool_zzz(s, gen_helper_crypto_aese,
173
- a->rd, a->rn, a->rm, decrypt);
174
+ return gen_gvec_ool_arg_zzz(s, gen_helper_crypto_aese, a, decrypt);
175
}
176
177
static bool trans_AESE(DisasContext *s, arg_rrr_esz *a)
178
@@ -XXX,XX +XXX,XX @@ static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
179
if (!dc_isar_feature(aa64_sve2_sm4, s)) {
180
return false;
181
}
182
- return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, 0);
183
+ return gen_gvec_ool_arg_zzz(s, fn, a, 0);
184
}
185
186
static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
191
--
187
--
192
2.20.1
188
2.25.1
193
194
diff view generated by jsdifflib
1
Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Convert SVE translation functions using
4
gen_gvec_ool_arg_zzz to TRANS_FEAT.
5
6
Remove trivial wrappers do_aese, do_sm4.
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220527181907.189259-7-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200430181003.21682-17-peter.maydell@linaro.org
6
---
12
---
7
target/arm/neon-dp.decode | 5 +++++
13
target/arm/translate-sve.c | 165 ++++++++++---------------------------
8
target/arm/translate-neon.inc.c | 14 ++++++++++++++
14
1 file changed, 45 insertions(+), 120 deletions(-)
9
target/arm/translate.c | 21 ++-------------------
15
10
3 files changed, 21 insertions(+), 19 deletions(-)
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
11
12
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
13
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/neon-dp.decode
18
--- a/target/arm/translate-sve.c
15
+++ b/target/arm/neon-dp.decode
19
+++ b/target/arm/translate-sve.c
16
@@ -XXX,XX +XXX,XX @@ VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
20
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
17
VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
21
}
18
VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
22
19
23
#define DO_ZZW(NAME, name) \
20
+VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
24
-static bool trans_##NAME##_zzw(DisasContext *s, arg_rrr_esz *a) \
21
+VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
25
-{ \
22
+VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
26
- static gen_helper_gvec_3 * const fns[4] = { \
23
+VMIN_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
27
+ static gen_helper_gvec_3 * const name##_zzw_fns[4] = { \
24
+
28
gen_helper_sve_##name##_zzw_b, gen_helper_sve_##name##_zzw_h, \
25
VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
29
gen_helper_sve_##name##_zzw_s, NULL \
26
VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
30
}; \
27
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
31
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0); \
28
index XXXXXXX..XXXXXXX 100644
32
-}
29
--- a/target/arm/translate-neon.inc.c
33
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_arg_zzz, \
30
+++ b/target/arm/translate-neon.inc.c
34
+ name##_zzw_fns[a->esz], a, 0)
31
@@ -XXX,XX +XXX,XX @@ DO_3SAME(VEOR, tcg_gen_gvec_xor)
35
32
DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
36
-DO_ZZW(ASR, asr)
33
DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
37
-DO_ZZW(LSR, lsr)
34
DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
38
-DO_ZZW(LSL, lsl)
35
+
39
+DO_ZZW(ASR_zzw, asr)
36
+#define DO_3SAME_NO_SZ_3(INSN, FUNC) \
40
+DO_ZZW(LSR_zzw, lsr)
37
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
41
+DO_ZZW(LSL_zzw, lsl)
38
+ { \
42
39
+ if (a->size == 3) { \
43
#undef DO_ZZW
40
+ return false; \
44
41
+ } \
45
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_2 * const fexpa_fns[4] = {
42
+ return do_3same(s, a, FUNC); \
46
TRANS_FEAT(FEXPA, aa64_sve, gen_gvec_ool_zz,
43
+ }
47
fexpa_fns[a->esz], a->rd, a->rn, 0)
44
+
48
45
+DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
49
-static bool trans_FTSSEL(DisasContext *s, arg_rrr_esz *a)
46
+DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
50
-{
47
+DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
51
- static gen_helper_gvec_3 * const fns[4] = {
48
+DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
52
- NULL,
49
diff --git a/target/arm/translate.c b/target/arm/translate.c
53
- gen_helper_sve_ftssel_h,
50
index XXXXXXX..XXXXXXX 100644
54
- gen_helper_sve_ftssel_s,
51
--- a/target/arm/translate.c
55
- gen_helper_sve_ftssel_d,
52
+++ b/target/arm/translate.c
56
- };
53
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
57
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
54
rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
58
-}
55
return 0;
59
+static gen_helper_gvec_3 * const ftssel_fns[4] = {
56
60
+ NULL, gen_helper_sve_ftssel_h,
57
- case NEON_3R_VMAX:
61
+ gen_helper_sve_ftssel_s, gen_helper_sve_ftssel_d,
58
- if (u) {
62
+};
59
- tcg_gen_gvec_umax(size, rd_ofs, rn_ofs, rm_ofs,
63
+TRANS_FEAT(FTSSEL, aa64_sve, gen_gvec_ool_arg_zzz, ftssel_fns[a->esz], a, 0)
60
- vec_size, vec_size);
64
61
- } else {
65
/*
62
- tcg_gen_gvec_smax(size, rd_ofs, rn_ofs, rm_ofs,
66
*** SVE Predicate Logical Operations Group
63
- vec_size, vec_size);
67
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_2 * const rev_fns[4] = {
64
- }
68
};
65
- return 0;
69
TRANS_FEAT(REV_v, aa64_sve, gen_gvec_ool_zz, rev_fns[a->esz], a->rd, a->rn, 0)
66
- case NEON_3R_VMIN:
70
67
- if (u) {
71
-static bool trans_TBL(DisasContext *s, arg_rrr_esz *a)
68
- tcg_gen_gvec_umin(size, rd_ofs, rn_ofs, rm_ofs,
72
-{
69
- vec_size, vec_size);
73
- static gen_helper_gvec_3 * const fns[4] = {
70
- } else {
74
- gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
71
- tcg_gen_gvec_smin(size, rd_ofs, rn_ofs, rm_ofs,
75
- gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
72
- vec_size, vec_size);
76
- };
73
- }
77
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
74
- return 0;
78
-}
75
-
79
+static gen_helper_gvec_3 * const sve_tbl_fns[4] = {
76
case NEON_3R_VSHL:
80
+ gen_helper_sve_tbl_b, gen_helper_sve_tbl_h,
77
/* Note the operation is vshl vd,vm,vn */
81
+ gen_helper_sve_tbl_s, gen_helper_sve_tbl_d
78
tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
82
+};
79
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
83
+TRANS_FEAT(TBL, aa64_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz], a, 0)
80
84
81
case NEON_3R_VADD_VSUB:
85
static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
82
case NEON_3R_LOGIC:
86
{
83
+ case NEON_3R_VMAX:
87
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
84
+ case NEON_3R_VMIN:
88
return true;
85
/* Already handled by decodetree */
89
}
86
return 1;
90
87
}
91
-static bool trans_TBX(DisasContext *s, arg_rrr_esz *a)
92
-{
93
- static gen_helper_gvec_3 * const fns[4] = {
94
- gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h,
95
- gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d
96
- };
97
-
98
- if (!dc_isar_feature(aa64_sve2, s)) {
99
- return false;
100
- }
101
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, 0);
102
-}
103
+static gen_helper_gvec_3 * const tbx_fns[4] = {
104
+ gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h,
105
+ gen_helper_sve2_tbx_s, gen_helper_sve2_tbx_d
106
+};
107
+TRANS_FEAT(TBX, aa64_sve2, gen_gvec_ool_arg_zzz, tbx_fns[a->esz], a, 0)
108
109
static bool trans_UNPK(DisasContext *s, arg_UNPK *a)
110
{
111
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const uzp_fns[4] = {
112
gen_helper_sve_uzp_s, gen_helper_sve_uzp_d,
113
};
114
115
-static bool trans_UZP1_z(DisasContext *s, arg_rrr_esz *a)
116
-{
117
- return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 0);
118
-}
119
+TRANS_FEAT(UZP1_z, aa64_sve, gen_gvec_ool_arg_zzz,
120
+ uzp_fns[a->esz], a, 0)
121
+TRANS_FEAT(UZP2_z, aa64_sve, gen_gvec_ool_arg_zzz,
122
+ uzp_fns[a->esz], a, 1 << a->esz)
123
124
-static bool trans_UZP2_z(DisasContext *s, arg_rrr_esz *a)
125
-{
126
- return gen_gvec_ool_arg_zzz(s, uzp_fns[a->esz], a, 1 << a->esz);
127
-}
128
-
129
-static bool trans_UZP1_q(DisasContext *s, arg_rrr_esz *a)
130
-{
131
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
132
- return false;
133
- }
134
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 0);
135
-}
136
-
137
-static bool trans_UZP2_q(DisasContext *s, arg_rrr_esz *a)
138
-{
139
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
140
- return false;
141
- }
142
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_uzp_q, a, 16);
143
-}
144
+TRANS_FEAT(UZP1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
145
+ gen_helper_sve2_uzp_q, a, 0)
146
+TRANS_FEAT(UZP2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
147
+ gen_helper_sve2_uzp_q, a, 16)
148
149
static gen_helper_gvec_3 * const trn_fns[4] = {
150
gen_helper_sve_trn_b, gen_helper_sve_trn_h,
151
gen_helper_sve_trn_s, gen_helper_sve_trn_d,
152
};
153
154
-static bool trans_TRN1_z(DisasContext *s, arg_rrr_esz *a)
155
-{
156
- return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 0);
157
-}
158
+TRANS_FEAT(TRN1_z, aa64_sve, gen_gvec_ool_arg_zzz,
159
+ trn_fns[a->esz], a, 0)
160
+TRANS_FEAT(TRN2_z, aa64_sve, gen_gvec_ool_arg_zzz,
161
+ trn_fns[a->esz], a, 1 << a->esz)
162
163
-static bool trans_TRN2_z(DisasContext *s, arg_rrr_esz *a)
164
-{
165
- return gen_gvec_ool_arg_zzz(s, trn_fns[a->esz], a, 1 << a->esz);
166
-}
167
-
168
-static bool trans_TRN1_q(DisasContext *s, arg_rrr_esz *a)
169
-{
170
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
171
- return false;
172
- }
173
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 0);
174
-}
175
-
176
-static bool trans_TRN2_q(DisasContext *s, arg_rrr_esz *a)
177
-{
178
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
179
- return false;
180
- }
181
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_trn_q, a, 16);
182
-}
183
+TRANS_FEAT(TRN1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
184
+ gen_helper_sve2_trn_q, a, 0)
185
+TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
186
+ gen_helper_sve2_trn_q, a, 16)
187
188
/*
189
*** SVE Permute Vector - Predicated Group
190
@@ -XXX,XX +XXX,XX @@ static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
191
TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
192
gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
193
194
-static bool do_aese(DisasContext *s, arg_rrr_esz *a, bool decrypt)
195
-{
196
- if (!dc_isar_feature(aa64_sve2_aes, s)) {
197
- return false;
198
- }
199
- return gen_gvec_ool_arg_zzz(s, gen_helper_crypto_aese, a, decrypt);
200
-}
201
+TRANS_FEAT(AESE, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
202
+ gen_helper_crypto_aese, a, false)
203
+TRANS_FEAT(AESD, aa64_sve2_aes, gen_gvec_ool_arg_zzz,
204
+ gen_helper_crypto_aese, a, true)
205
206
-static bool trans_AESE(DisasContext *s, arg_rrr_esz *a)
207
-{
208
- return do_aese(s, a, false);
209
-}
210
-
211
-static bool trans_AESD(DisasContext *s, arg_rrr_esz *a)
212
-{
213
- return do_aese(s, a, true);
214
-}
215
-
216
-static bool do_sm4(DisasContext *s, arg_rrr_esz *a, gen_helper_gvec_3 *fn)
217
-{
218
- if (!dc_isar_feature(aa64_sve2_sm4, s)) {
219
- return false;
220
- }
221
- return gen_gvec_ool_arg_zzz(s, fn, a, 0);
222
-}
223
-
224
-static bool trans_SM4E(DisasContext *s, arg_rrr_esz *a)
225
-{
226
- return do_sm4(s, a, gen_helper_crypto_sm4e);
227
-}
228
-
229
-static bool trans_SM4EKEY(DisasContext *s, arg_rrr_esz *a)
230
-{
231
- return do_sm4(s, a, gen_helper_crypto_sm4ekey);
232
-}
233
+TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
234
+ gen_helper_crypto_sm4e, a, 0)
235
+TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
236
+ gen_helper_crypto_sm4ekey, a, 0)
237
238
static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
239
{
88
--
240
--
89
2.20.1
241
2.25.1
90
91
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zzz_ool
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-8-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 88 ++++++++++++++------------------------
12
1 file changed, 31 insertions(+), 57 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
19
return true;
20
}
21
22
-static bool do_sve2_zzz_ool(DisasContext *s, arg_rrr_esz *a,
23
- gen_helper_gvec_3 *fn)
24
-{
25
- if (!dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zzz(s, fn, a, 0);
29
-}
30
+static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
31
+ gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h,
32
+ gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d,
33
+};
34
+TRANS_FEAT(SMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
35
+ smulh_zzz_fns[a->esz], a, 0)
36
37
-static bool trans_SMULH_zzz(DisasContext *s, arg_rrr_esz *a)
38
-{
39
- static gen_helper_gvec_3 * const fns[4] = {
40
- gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h,
41
- gen_helper_gvec_smulh_s, gen_helper_gvec_smulh_d,
42
- };
43
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
44
-}
45
+static gen_helper_gvec_3 * const umulh_zzz_fns[4] = {
46
+ gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h,
47
+ gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d,
48
+};
49
+TRANS_FEAT(UMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
50
+ umulh_zzz_fns[a->esz], a, 0)
51
52
-static bool trans_UMULH_zzz(DisasContext *s, arg_rrr_esz *a)
53
-{
54
- static gen_helper_gvec_3 * const fns[4] = {
55
- gen_helper_gvec_umulh_b, gen_helper_gvec_umulh_h,
56
- gen_helper_gvec_umulh_s, gen_helper_gvec_umulh_d,
57
- };
58
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
59
-}
60
+TRANS_FEAT(PMUL_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
61
+ gen_helper_gvec_pmul_b, a, 0)
62
63
-static bool trans_PMUL_zzz(DisasContext *s, arg_rrr_esz *a)
64
-{
65
- return do_sve2_zzz_ool(s, a, gen_helper_gvec_pmul_b);
66
-}
67
+static gen_helper_gvec_3 * const sqdmulh_zzz_fns[4] = {
68
+ gen_helper_sve2_sqdmulh_b, gen_helper_sve2_sqdmulh_h,
69
+ gen_helper_sve2_sqdmulh_s, gen_helper_sve2_sqdmulh_d,
70
+};
71
+TRANS_FEAT(SQDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
72
+ sqdmulh_zzz_fns[a->esz], a, 0)
73
74
-static bool trans_SQDMULH_zzz(DisasContext *s, arg_rrr_esz *a)
75
-{
76
- static gen_helper_gvec_3 * const fns[4] = {
77
- gen_helper_sve2_sqdmulh_b, gen_helper_sve2_sqdmulh_h,
78
- gen_helper_sve2_sqdmulh_s, gen_helper_sve2_sqdmulh_d,
79
- };
80
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
81
-}
82
-
83
-static bool trans_SQRDMULH_zzz(DisasContext *s, arg_rrr_esz *a)
84
-{
85
- static gen_helper_gvec_3 * const fns[4] = {
86
- gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h,
87
- gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d,
88
- };
89
- return do_sve2_zzz_ool(s, a, fns[a->esz]);
90
-}
91
+static gen_helper_gvec_3 * const sqrdmulh_zzz_fns[4] = {
92
+ gen_helper_sve2_sqrdmulh_b, gen_helper_sve2_sqrdmulh_h,
93
+ gen_helper_sve2_sqrdmulh_s, gen_helper_sve2_sqrdmulh_d,
94
+};
95
+TRANS_FEAT(SQRDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
96
+ sqrdmulh_zzz_fns[a->esz], a, 0)
97
98
/*
99
* SVE2 Integer - Predicated
100
@@ -XXX,XX +XXX,XX @@ static bool trans_UQRSHRNT(DisasContext *s, arg_rri_esz *a)
101
}
102
103
#define DO_SVE2_ZZZ_NARROW(NAME, name) \
104
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
105
-{ \
106
- static gen_helper_gvec_3 * const fns[4] = { \
107
+ static gen_helper_gvec_3 * const name##_fns[4] = { \
108
NULL, gen_helper_sve2_##name##_h, \
109
gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
110
}; \
111
- return do_sve2_zzz_ool(s, a, fns[a->esz]); \
112
-}
113
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzz, \
114
+ name##_fns[a->esz], a, 0)
115
116
DO_SVE2_ZZZ_NARROW(ADDHNB, addhnb)
117
DO_SVE2_ZZZ_NARROW(ADDHNT, addhnt)
118
@@ -XXX,XX +XXX,XX @@ static bool trans_HISTCNT(DisasContext *s, arg_rprr_esz *a)
119
return do_sve2_zpzz_ool(s, a, fns[a->esz - 2]);
120
}
121
122
-static bool trans_HISTSEG(DisasContext *s, arg_rrr_esz *a)
123
-{
124
- if (a->esz != 0) {
125
- return false;
126
- }
127
- return do_sve2_zzz_ool(s, a, gen_helper_sve2_histseg);
128
-}
129
+TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
130
+ a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
131
132
static bool do_sve2_zpzz_fp(DisasContext *s, arg_rprr_esz *a,
133
gen_helper_gvec_4_ptr *fn)
134
--
135
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-9-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 102 ++++++++++++++-----------------------
9
1 file changed, 38 insertions(+), 64 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 4 Zregs. */
19
-static void gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
20
+static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
21
int rd, int rn, int rm, int ra, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm),
27
- vec_full_reg_offset(s, ra),
28
- vsz, vsz, data, fn);
29
+ if (fn == NULL) {
30
+ return false;
31
+ }
32
+ if (sve_access_check(s)) {
33
+ unsigned vsz = vec_full_reg_size(s);
34
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
35
+ vec_full_reg_offset(s, rn),
36
+ vec_full_reg_offset(s, rm),
37
+ vec_full_reg_offset(s, ra),
38
+ vsz, vsz, data, fn);
39
+ }
40
+ return true;
41
}
42
43
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
44
@@ -XXX,XX +XXX,XX @@ static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
45
if (!dc_isar_feature(aa64_sve2, s)) {
46
return false;
47
}
48
- if (sve_access_check(s)) {
49
- gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
50
- (a->rn + 1) % 32, a->rm, 0);
51
- }
52
- return true;
53
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
54
+ (a->rn + 1) % 32, a->rm, 0);
55
}
56
57
static gen_helper_gvec_3 * const tbx_fns[4] = {
58
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzzz(DisasContext *s, arg_DOT_zzzz *a)
59
{ gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h },
60
{ gen_helper_gvec_udot_b, gen_helper_gvec_udot_h }
61
};
62
-
63
- if (sve_access_check(s)) {
64
- gen_gvec_ool_zzzz(s, fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0);
65
- }
66
- return true;
67
+ return gen_gvec_ool_zzzz(s, fns[a->u][a->sz],
68
+ a->rd, a->rn, a->rm, a->ra, 0);
69
}
70
71
/*
72
@@ -XXX,XX +XXX,XX @@ static bool trans_DOT_zzzz(DisasContext *s, arg_DOT_zzzz *a)
73
static bool do_zzxz_ool(DisasContext *s, arg_rrxr_esz *a,
74
gen_helper_gvec_4 *fn)
75
{
76
- if (fn == NULL) {
77
- return false;
78
- }
79
- if (sve_access_check(s)) {
80
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
81
- }
82
- return true;
83
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
84
}
85
86
#define DO_RRXR(NAME, FUNC) \
87
@@ -XXX,XX +XXX,XX @@ static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
88
static bool do_sve2_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
89
gen_helper_gvec_4 *fn, int data)
90
{
91
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
92
+ if (!dc_isar_feature(aa64_sve2, s)) {
93
return false;
94
}
95
- if (sve_access_check(s)) {
96
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
97
- }
98
- return true;
99
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
100
}
101
102
static bool do_abal(DisasContext *s, arg_rrrr_esz *a, bool uns, bool sel)
103
@@ -XXX,XX +XXX,XX @@ static bool trans_CMLA_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
104
if (!dc_isar_feature(aa64_sve2, s)) {
105
return false;
106
}
107
- if (sve_access_check(s)) {
108
- gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot);
109
- }
110
- return true;
111
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
112
+ a->rm, a->ra, a->rot);
113
}
114
115
static bool trans_CDOT_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
116
{
117
- if (!dc_isar_feature(aa64_sve2, s) || a->esz < MO_32) {
118
+ static gen_helper_gvec_4 * const fns[] = {
119
+ NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d
120
+ };
121
+
122
+ if (!dc_isar_feature(aa64_sve2, s)) {
123
return false;
124
}
125
- if (sve_access_check(s)) {
126
- gen_helper_gvec_4 *fn = (a->esz == MO_32
127
- ? gen_helper_sve2_cdot_zzzz_s
128
- : gen_helper_sve2_cdot_zzzz_d);
129
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->rot);
130
- }
131
- return true;
132
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
133
+ a->rm, a->ra, a->rot);
134
}
135
136
static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a)
137
@@ -XXX,XX +XXX,XX @@ static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a)
138
if (!dc_isar_feature(aa64_sve2, s)) {
139
return false;
140
}
141
- if (sve_access_check(s)) {
142
- gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot);
143
- }
144
- return true;
145
+ return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
146
+ a->rm, a->ra, a->rot);
147
}
148
149
static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
150
@@ -XXX,XX +XXX,XX @@ static bool do_i8mm_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
151
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
152
return false;
153
}
154
- if (sve_access_check(s)) {
155
- gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
156
- }
157
- return true;
158
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
159
}
160
161
static bool trans_SMMLA(DisasContext *s, arg_rrrr_esz *a)
162
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a)
163
if (!dc_isar_feature(aa64_sve_bf16, s)) {
164
return false;
165
}
166
- if (sve_access_check(s)) {
167
- gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot,
168
- a->rd, a->rn, a->rm, a->ra, 0);
169
- }
170
- return true;
171
+ return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot,
172
+ a->rd, a->rn, a->rm, a->ra, 0);
173
}
174
175
static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
176
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
177
if (!dc_isar_feature(aa64_sve_bf16, s)) {
178
return false;
179
}
180
- if (sve_access_check(s)) {
181
- gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx,
182
- a->rd, a->rn, a->rm, a->ra, a->index);
183
- }
184
- return true;
185
+ return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx,
186
+ a->rd, a->rn, a->rm, a->ra, a->index);
187
}
188
189
static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
190
@@ -XXX,XX +XXX,XX @@ static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
191
if (!dc_isar_feature(aa64_sve_bf16, s)) {
192
return false;
193
}
194
- if (sve_access_check(s)) {
195
- gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla,
196
- a->rd, a->rn, a->rm, a->ra, 0);
197
- }
198
- return true;
199
+ return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla,
200
+ a->rd, a->rn, a->rm, a->ra, 0);
201
}
202
203
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
204
--
205
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_ool_zzzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-10-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 89 +++++++++++++-------------------------
12
1 file changed, 29 insertions(+), 60 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const sve_tbl_fns[4] = {
19
};
20
TRANS_FEAT(TBL, aa64_sve, gen_gvec_ool_arg_zzz, sve_tbl_fns[a->esz], a, 0)
21
22
-static bool trans_TBL_sve2(DisasContext *s, arg_rrr_esz *a)
23
-{
24
- static gen_helper_gvec_4 * const fns[4] = {
25
- gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h,
26
- gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d
27
- };
28
-
29
- if (!dc_isar_feature(aa64_sve2, s)) {
30
- return false;
31
- }
32
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
33
- (a->rn + 1) % 32, a->rm, 0);
34
-}
35
+static gen_helper_gvec_4 * const sve2_tbl_fns[4] = {
36
+ gen_helper_sve2_tbl_b, gen_helper_sve2_tbl_h,
37
+ gen_helper_sve2_tbl_s, gen_helper_sve2_tbl_d
38
+};
39
+TRANS_FEAT(TBL_sve2, aa64_sve2, gen_gvec_ool_zzzz, sve2_tbl_fns[a->esz],
40
+ a->rd, a->rn, (a->rn + 1) % 32, a->rm, 0)
41
42
static gen_helper_gvec_3 * const tbx_fns[4] = {
43
gen_helper_sve2_tbx_b, gen_helper_sve2_tbx_h,
44
@@ -XXX,XX +XXX,XX @@ DO_ZZI(UMIN, umin)
45
46
#undef DO_ZZI
47
48
-static bool trans_DOT_zzzz(DisasContext *s, arg_DOT_zzzz *a)
49
-{
50
- static gen_helper_gvec_4 * const fns[2][2] = {
51
- { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h },
52
- { gen_helper_gvec_udot_b, gen_helper_gvec_udot_h }
53
- };
54
- return gen_gvec_ool_zzzz(s, fns[a->u][a->sz],
55
- a->rd, a->rn, a->rm, a->ra, 0);
56
-}
57
+static gen_helper_gvec_4 * const dot_fns[2][2] = {
58
+ { gen_helper_gvec_sdot_b, gen_helper_gvec_sdot_h },
59
+ { gen_helper_gvec_udot_b, gen_helper_gvec_udot_h }
60
+};
61
+TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz,
62
+ dot_fns[a->u][a->sz], a->rd, a->rn, a->rm, a->ra, 0)
63
64
/*
65
* SVE Multiply - Indexed
66
@@ -XXX,XX +XXX,XX @@ static bool trans_UMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
67
return do_umlsl_zzzw(s, a, true);
68
}
69
70
-static bool trans_CMLA_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
71
-{
72
- static gen_helper_gvec_4 * const fns[] = {
73
- gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h,
74
- gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d,
75
- };
76
+static gen_helper_gvec_4 * const cmla_fns[] = {
77
+ gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h,
78
+ gen_helper_sve2_cmla_zzzz_s, gen_helper_sve2_cmla_zzzz_d,
79
+};
80
+TRANS_FEAT(CMLA_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
81
+ cmla_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
82
83
- if (!dc_isar_feature(aa64_sve2, s)) {
84
- return false;
85
- }
86
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
87
- a->rm, a->ra, a->rot);
88
-}
89
+static gen_helper_gvec_4 * const cdot_fns[] = {
90
+ NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d
91
+};
92
+TRANS_FEAT(CDOT_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
93
+ cdot_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
94
95
-static bool trans_CDOT_zzzz(DisasContext *s, arg_CMLA_zzzz *a)
96
-{
97
- static gen_helper_gvec_4 * const fns[] = {
98
- NULL, NULL, gen_helper_sve2_cdot_zzzz_s, gen_helper_sve2_cdot_zzzz_d
99
- };
100
-
101
- if (!dc_isar_feature(aa64_sve2, s)) {
102
- return false;
103
- }
104
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
105
- a->rm, a->ra, a->rot);
106
-}
107
-
108
-static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a)
109
-{
110
- static gen_helper_gvec_4 * const fns[] = {
111
- gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h,
112
- gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d,
113
- };
114
-
115
- if (!dc_isar_feature(aa64_sve2, s)) {
116
- return false;
117
- }
118
- return gen_gvec_ool_zzzz(s, fns[a->esz], a->rd, a->rn,
119
- a->rm, a->ra, a->rot);
120
-}
121
+static gen_helper_gvec_4 * const sqrdcmlah_fns[] = {
122
+ gen_helper_sve2_sqrdcmlah_zzzz_b, gen_helper_sve2_sqrdcmlah_zzzz_h,
123
+ gen_helper_sve2_sqrdcmlah_zzzz_s, gen_helper_sve2_sqrdcmlah_zzzz_d,
124
+};
125
+TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
126
+ sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
127
128
static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
129
{
130
--
131
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Use gen_gvec_ool_arg_zzzz instead of gen_gvec_ool_zzzz
4
when the arguments come from arg_rrrr_esz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-11-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 16 ++++++++++------
12
1 file changed, 10 insertions(+), 6 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
19
return true;
20
}
21
22
+static bool gen_gvec_ool_arg_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
23
+ arg_rrrr_esz *a, int data)
24
+{
25
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
26
+}
27
+
28
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
29
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
30
int rd, int rn, int pg, int data)
31
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
32
if (!dc_isar_feature(aa64_sve2, s)) {
33
return false;
34
}
35
- return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
36
+ return gen_gvec_ool_arg_zzzz(s, fn, a, data);
37
}
38
39
static bool do_abal(DisasContext *s, arg_rrrr_esz *a, bool uns, bool sel)
40
@@ -XXX,XX +XXX,XX @@ static bool do_i8mm_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
41
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
42
return false;
43
}
44
- return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
45
+ return gen_gvec_ool_arg_zzzz(s, fn, a, data);
46
}
47
48
static bool trans_SMMLA(DisasContext *s, arg_rrrr_esz *a)
49
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a)
50
if (!dc_isar_feature(aa64_sve_bf16, s)) {
51
return false;
52
}
53
- return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot,
54
- a->rd, a->rn, a->rm, a->ra, 0);
55
+ return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfdot, a, 0);
56
}
57
58
static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
59
@@ -XXX,XX +XXX,XX @@ static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
60
if (!dc_isar_feature(aa64_sve_bf16, s)) {
61
return false;
62
}
63
- return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfmmla,
64
- a->rd, a->rn, a->rm, a->ra, 0);
65
+ return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfmmla, a, 0);
66
}
67
68
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
69
--
70
2.25.1
diff view generated by jsdifflib
1
Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
Note that for the logic ops the 'size' field forms part of their
3
decode and the actual operations are always bitwise.
4
2
3
Convert SVE translation functions using do_sve2_zzzz_ool
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-12-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20200430181003.21682-16-peter.maydell@linaro.org
8
---
10
---
9
target/arm/neon-dp.decode | 12 +++++++++++
11
target/arm/translate-sve.c | 263 +++++++++++--------------------------
10
target/arm/translate-neon.inc.c | 19 +++++++++++++++++
12
1 file changed, 79 insertions(+), 184 deletions(-)
11
target/arm/translate.c | 38 +--------------------------------
12
3 files changed, 32 insertions(+), 37 deletions(-)
13
13
14
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/neon-dp.decode
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/neon-dp.decode
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
19
@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
19
return do_cadd(s, a, true, true);
20
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
20
}
21
21
22
+@3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \
22
-static bool do_sve2_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
23
+ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
23
- gen_helper_gvec_4 *fn, int data)
24
+
24
-{
25
+VAND_3s 1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
25
- if (!dc_isar_feature(aa64_sve2, s)) {
26
+VBIC_3s 1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
26
- return false;
27
+VORR_3s 1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
27
- }
28
+VORN_3s 1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
28
- return gen_gvec_ool_arg_zzzz(s, fn, a, data);
29
+VEOR_3s 1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
29
-}
30
+VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
30
+static gen_helper_gvec_4 * const sabal_fns[4] = {
31
+VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
31
+ NULL, gen_helper_sve2_sabal_h,
32
+VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
32
+ gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d,
33
+
33
+};
34
VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
34
+TRANS_FEAT(SABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a, 0)
35
VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
35
+TRANS_FEAT(SABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, sabal_fns[a->esz], a, 1)
36
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
36
37
index XXXXXXX..XXXXXXX 100644
37
-static bool do_abal(DisasContext *s, arg_rrrr_esz *a, bool uns, bool sel)
38
--- a/target/arm/translate-neon.inc.c
38
-{
39
+++ b/target/arm/translate-neon.inc.c
39
- static gen_helper_gvec_4 * const fns[2][4] = {
40
@@ -XXX,XX +XXX,XX @@ static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
40
- { NULL, gen_helper_sve2_sabal_h,
41
41
- gen_helper_sve2_sabal_s, gen_helper_sve2_sabal_d },
42
DO_3SAME(VADD, tcg_gen_gvec_add)
42
- { NULL, gen_helper_sve2_uabal_h,
43
DO_3SAME(VSUB, tcg_gen_gvec_sub)
43
- gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d },
44
+DO_3SAME(VAND, tcg_gen_gvec_and)
44
- };
45
+DO_3SAME(VBIC, tcg_gen_gvec_andc)
45
- return do_sve2_zzzz_ool(s, a, fns[uns][a->esz], sel);
46
+DO_3SAME(VORR, tcg_gen_gvec_or)
46
-}
47
+DO_3SAME(VORN, tcg_gen_gvec_orc)
47
-
48
+DO_3SAME(VEOR, tcg_gen_gvec_xor)
48
-static bool trans_SABALB(DisasContext *s, arg_rrrr_esz *a)
49
+
49
-{
50
+/* These insns are all gvec_bitsel but with the inputs in various orders. */
50
- return do_abal(s, a, false, false);
51
+#define DO_3SAME_BITSEL(INSN, O1, O2, O3) \
51
-}
52
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
52
-
53
+ uint32_t rn_ofs, uint32_t rm_ofs, \
53
-static bool trans_SABALT(DisasContext *s, arg_rrrr_esz *a)
54
+ uint32_t oprsz, uint32_t maxsz) \
54
-{
55
+ { \
55
- return do_abal(s, a, false, true);
56
+ tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz); \
56
-}
57
+ } \
57
-
58
+ DO_3SAME(INSN, gen_##INSN##_3s)
58
-static bool trans_UABALB(DisasContext *s, arg_rrrr_esz *a)
59
+
59
-{
60
+DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
60
- return do_abal(s, a, true, false);
61
+DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
61
-}
62
+DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
62
-
63
diff --git a/target/arm/translate.c b/target/arm/translate.c
63
-static bool trans_UABALT(DisasContext *s, arg_rrrr_esz *a)
64
index XXXXXXX..XXXXXXX 100644
64
-{
65
--- a/target/arm/translate.c
65
- return do_abal(s, a, true, true);
66
+++ b/target/arm/translate.c
66
-}
67
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
67
+static gen_helper_gvec_4 * const uabal_fns[4] = {
68
}
68
+ NULL, gen_helper_sve2_uabal_h,
69
return 1;
69
+ gen_helper_sve2_uabal_s, gen_helper_sve2_uabal_d,
70
70
+};
71
- case NEON_3R_LOGIC: /* Logic ops. */
71
+TRANS_FEAT(UABALB, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a, 0)
72
- switch ((u << 2) | size) {
72
+TRANS_FEAT(UABALT, aa64_sve2, gen_gvec_ool_arg_zzzz, uabal_fns[a->esz], a, 1)
73
- case 0: /* VAND */
73
74
- tcg_gen_gvec_and(0, rd_ofs, rn_ofs, rm_ofs,
74
static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel)
75
- vec_size, vec_size);
75
{
76
- break;
76
@@ -XXX,XX +XXX,XX @@ static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel)
77
- case 1: /* VBIC */
77
* Note that in this case the ESZ field encodes both size and sign.
78
- tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
78
* Split out 'subtract' into bit 1 of the data field for the helper.
79
- vec_size, vec_size);
79
*/
80
- break;
80
- return do_sve2_zzzz_ool(s, a, fns[a->esz & 1], (a->esz & 2) | sel);
81
- case 2: /* VORR */
81
+ return gen_gvec_ool_arg_zzzz(s, fns[a->esz & 1], a, (a->esz & 2) | sel);
82
- tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
82
}
83
- vec_size, vec_size);
83
84
- break;
84
-static bool trans_ADCLB(DisasContext *s, arg_rrrr_esz *a)
85
- case 3: /* VORN */
85
-{
86
- tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
86
- return do_adcl(s, a, false);
87
- vec_size, vec_size);
87
-}
88
- break;
88
-
89
- case 4: /* VEOR */
89
-static bool trans_ADCLT(DisasContext *s, arg_rrrr_esz *a)
90
- tcg_gen_gvec_xor(0, rd_ofs, rn_ofs, rm_ofs,
90
-{
91
- vec_size, vec_size);
91
- return do_adcl(s, a, true);
92
- break;
92
-}
93
- case 5: /* VBSL */
93
+TRANS_FEAT(ADCLB, aa64_sve2, do_adcl, a, false)
94
- tcg_gen_gvec_bitsel(MO_8, rd_ofs, rd_ofs, rn_ofs, rm_ofs,
94
+TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true)
95
- vec_size, vec_size);
95
96
- break;
96
static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
97
- case 6: /* VBIT */
97
{
98
- tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rn_ofs, rd_ofs,
98
@@ -XXX,XX +XXX,XX @@ static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a)
99
- vec_size, vec_size);
99
return true;
100
- break;
100
}
101
- case 7: /* VBIF */
101
102
- tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rd_ofs, rn_ofs,
102
-static bool do_sqdmlal_zzzw(DisasContext *s, arg_rrrr_esz *a,
103
- vec_size, vec_size);
103
- bool sel1, bool sel2)
104
- break;
104
-{
105
- }
105
- static gen_helper_gvec_4 * const fns[] = {
106
- return 0;
106
- NULL, gen_helper_sve2_sqdmlal_zzzw_h,
107
-
107
- gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d,
108
case NEON_3R_VQADD:
108
- };
109
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
109
- return do_sve2_zzzz_ool(s, a, fns[a->esz], (sel2 << 1) | sel1);
110
rn_ofs, rm_ofs, vec_size, vec_size,
110
-}
111
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
111
+static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
112
return 0;
112
+ NULL, gen_helper_sve2_sqdmlal_zzzw_h,
113
113
+ gen_helper_sve2_sqdmlal_zzzw_s, gen_helper_sve2_sqdmlal_zzzw_d,
114
case NEON_3R_VADD_VSUB:
114
+};
115
+ case NEON_3R_LOGIC:
115
+TRANS_FEAT(SQDMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
116
/* Already handled by decodetree */
116
+ sqdmlal_zzzw_fns[a->esz], a, 0)
117
return 1;
117
+TRANS_FEAT(SQDMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
118
}
118
+ sqdmlal_zzzw_fns[a->esz], a, 3)
119
+TRANS_FEAT(SQDMLALBT, aa64_sve2, gen_gvec_ool_arg_zzzz,
120
+ sqdmlal_zzzw_fns[a->esz], a, 2)
121
122
-static bool do_sqdmlsl_zzzw(DisasContext *s, arg_rrrr_esz *a,
123
- bool sel1, bool sel2)
124
-{
125
- static gen_helper_gvec_4 * const fns[] = {
126
- NULL, gen_helper_sve2_sqdmlsl_zzzw_h,
127
- gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d,
128
- };
129
- return do_sve2_zzzz_ool(s, a, fns[a->esz], (sel2 << 1) | sel1);
130
-}
131
+static gen_helper_gvec_4 * const sqdmlsl_zzzw_fns[] = {
132
+ NULL, gen_helper_sve2_sqdmlsl_zzzw_h,
133
+ gen_helper_sve2_sqdmlsl_zzzw_s, gen_helper_sve2_sqdmlsl_zzzw_d,
134
+};
135
+TRANS_FEAT(SQDMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
136
+ sqdmlsl_zzzw_fns[a->esz], a, 0)
137
+TRANS_FEAT(SQDMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
138
+ sqdmlsl_zzzw_fns[a->esz], a, 3)
139
+TRANS_FEAT(SQDMLSLBT, aa64_sve2, gen_gvec_ool_arg_zzzz,
140
+ sqdmlsl_zzzw_fns[a->esz], a, 2)
141
142
-static bool trans_SQDMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
143
-{
144
- return do_sqdmlal_zzzw(s, a, false, false);
145
-}
146
+static gen_helper_gvec_4 * const sqrdmlah_fns[] = {
147
+ gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h,
148
+ gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d,
149
+};
150
+TRANS_FEAT(SQRDMLAH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz,
151
+ sqrdmlah_fns[a->esz], a, 0)
152
153
-static bool trans_SQDMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
154
-{
155
- return do_sqdmlal_zzzw(s, a, true, true);
156
-}
157
+static gen_helper_gvec_4 * const sqrdmlsh_fns[] = {
158
+ gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h,
159
+ gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d,
160
+};
161
+TRANS_FEAT(SQRDMLSH_zzzz, aa64_sve2, gen_gvec_ool_arg_zzzz,
162
+ sqrdmlsh_fns[a->esz], a, 0)
163
164
-static bool trans_SQDMLALBT(DisasContext *s, arg_rrrr_esz *a)
165
-{
166
- return do_sqdmlal_zzzw(s, a, false, true);
167
-}
168
+static gen_helper_gvec_4 * const smlal_zzzw_fns[] = {
169
+ NULL, gen_helper_sve2_smlal_zzzw_h,
170
+ gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d,
171
+};
172
+TRANS_FEAT(SMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
173
+ smlal_zzzw_fns[a->esz], a, 0)
174
+TRANS_FEAT(SMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
175
+ smlal_zzzw_fns[a->esz], a, 1)
176
177
-static bool trans_SQDMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
178
-{
179
- return do_sqdmlsl_zzzw(s, a, false, false);
180
-}
181
+static gen_helper_gvec_4 * const umlal_zzzw_fns[] = {
182
+ NULL, gen_helper_sve2_umlal_zzzw_h,
183
+ gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d,
184
+};
185
+TRANS_FEAT(UMLALB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
186
+ umlal_zzzw_fns[a->esz], a, 0)
187
+TRANS_FEAT(UMLALT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
188
+ umlal_zzzw_fns[a->esz], a, 1)
189
190
-static bool trans_SQDMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
191
-{
192
- return do_sqdmlsl_zzzw(s, a, true, true);
193
-}
194
+static gen_helper_gvec_4 * const smlsl_zzzw_fns[] = {
195
+ NULL, gen_helper_sve2_smlsl_zzzw_h,
196
+ gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d,
197
+};
198
+TRANS_FEAT(SMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
199
+ smlsl_zzzw_fns[a->esz], a, 0)
200
+TRANS_FEAT(SMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
201
+ smlsl_zzzw_fns[a->esz], a, 1)
202
203
-static bool trans_SQDMLSLBT(DisasContext *s, arg_rrrr_esz *a)
204
-{
205
- return do_sqdmlsl_zzzw(s, a, false, true);
206
-}
207
-
208
-static bool trans_SQRDMLAH_zzzz(DisasContext *s, arg_rrrr_esz *a)
209
-{
210
- static gen_helper_gvec_4 * const fns[] = {
211
- gen_helper_sve2_sqrdmlah_b, gen_helper_sve2_sqrdmlah_h,
212
- gen_helper_sve2_sqrdmlah_s, gen_helper_sve2_sqrdmlah_d,
213
- };
214
- return do_sve2_zzzz_ool(s, a, fns[a->esz], 0);
215
-}
216
-
217
-static bool trans_SQRDMLSH_zzzz(DisasContext *s, arg_rrrr_esz *a)
218
-{
219
- static gen_helper_gvec_4 * const fns[] = {
220
- gen_helper_sve2_sqrdmlsh_b, gen_helper_sve2_sqrdmlsh_h,
221
- gen_helper_sve2_sqrdmlsh_s, gen_helper_sve2_sqrdmlsh_d,
222
- };
223
- return do_sve2_zzzz_ool(s, a, fns[a->esz], 0);
224
-}
225
-
226
-static bool do_smlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
227
-{
228
- static gen_helper_gvec_4 * const fns[] = {
229
- NULL, gen_helper_sve2_smlal_zzzw_h,
230
- gen_helper_sve2_smlal_zzzw_s, gen_helper_sve2_smlal_zzzw_d,
231
- };
232
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
233
-}
234
-
235
-static bool trans_SMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
236
-{
237
- return do_smlal_zzzw(s, a, false);
238
-}
239
-
240
-static bool trans_SMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
241
-{
242
- return do_smlal_zzzw(s, a, true);
243
-}
244
-
245
-static bool do_umlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
246
-{
247
- static gen_helper_gvec_4 * const fns[] = {
248
- NULL, gen_helper_sve2_umlal_zzzw_h,
249
- gen_helper_sve2_umlal_zzzw_s, gen_helper_sve2_umlal_zzzw_d,
250
- };
251
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
252
-}
253
-
254
-static bool trans_UMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
255
-{
256
- return do_umlal_zzzw(s, a, false);
257
-}
258
-
259
-static bool trans_UMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
260
-{
261
- return do_umlal_zzzw(s, a, true);
262
-}
263
-
264
-static bool do_smlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
265
-{
266
- static gen_helper_gvec_4 * const fns[] = {
267
- NULL, gen_helper_sve2_smlsl_zzzw_h,
268
- gen_helper_sve2_smlsl_zzzw_s, gen_helper_sve2_smlsl_zzzw_d,
269
- };
270
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
271
-}
272
-
273
-static bool trans_SMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
274
-{
275
- return do_smlsl_zzzw(s, a, false);
276
-}
277
-
278
-static bool trans_SMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
279
-{
280
- return do_smlsl_zzzw(s, a, true);
281
-}
282
-
283
-static bool do_umlsl_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
284
-{
285
- static gen_helper_gvec_4 * const fns[] = {
286
- NULL, gen_helper_sve2_umlsl_zzzw_h,
287
- gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d,
288
- };
289
- return do_sve2_zzzz_ool(s, a, fns[a->esz], sel);
290
-}
291
-
292
-static bool trans_UMLSLB_zzzw(DisasContext *s, arg_rrrr_esz *a)
293
-{
294
- return do_umlsl_zzzw(s, a, false);
295
-}
296
-
297
-static bool trans_UMLSLT_zzzw(DisasContext *s, arg_rrrr_esz *a)
298
-{
299
- return do_umlsl_zzzw(s, a, true);
300
-}
301
+static gen_helper_gvec_4 * const umlsl_zzzw_fns[] = {
302
+ NULL, gen_helper_sve2_umlsl_zzzw_h,
303
+ gen_helper_sve2_umlsl_zzzw_s, gen_helper_sve2_umlsl_zzzw_d,
304
+};
305
+TRANS_FEAT(UMLSLB_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
306
+ umlsl_zzzw_fns[a->esz], a, 0)
307
+TRANS_FEAT(UMLSLT_zzzw, aa64_sve2, gen_gvec_ool_arg_zzzz,
308
+ umlsl_zzzw_fns[a->esz], a, 1)
309
310
static gen_helper_gvec_4 * const cmla_fns[] = {
311
gen_helper_sve2_cmla_zzzz_b, gen_helper_sve2_cmla_zzzz_h,
119
--
312
--
120
2.20.1
313
2.25.1
121
122
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zzzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-13-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 47 ++++++++------------------------------
12
1 file changed, 10 insertions(+), 37 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_FMLSLT_zzxw(DisasContext *s, arg_rrxr_esz *a)
19
return do_FMLAL_zzxw(s, a, true, true);
20
}
21
22
-static bool do_i8mm_zzzz_ool(DisasContext *s, arg_rrrr_esz *a,
23
- gen_helper_gvec_4 *fn, int data)
24
-{
25
- if (!dc_isar_feature(aa64_sve_i8mm, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zzzz(s, fn, a, data);
29
-}
30
+TRANS_FEAT(SMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
31
+ gen_helper_gvec_smmla_b, a, 0)
32
+TRANS_FEAT(USMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
33
+ gen_helper_gvec_usmmla_b, a, 0)
34
+TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
35
+ gen_helper_gvec_ummla_b, a, 0)
36
37
-static bool trans_SMMLA(DisasContext *s, arg_rrrr_esz *a)
38
-{
39
- return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_smmla_b, 0);
40
-}
41
-
42
-static bool trans_USMMLA(DisasContext *s, arg_rrrr_esz *a)
43
-{
44
- return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_usmmla_b, 0);
45
-}
46
-
47
-static bool trans_UMMLA(DisasContext *s, arg_rrrr_esz *a)
48
-{
49
- return do_i8mm_zzzz_ool(s, a, gen_helper_gvec_ummla_b, 0);
50
-}
51
-
52
-static bool trans_BFDOT_zzzz(DisasContext *s, arg_rrrr_esz *a)
53
-{
54
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
55
- return false;
56
- }
57
- return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfdot, a, 0);
58
-}
59
+TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
60
+ gen_helper_gvec_bfdot, a, 0)
61
62
static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
63
{
64
@@ -XXX,XX +XXX,XX @@ static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
65
a->rd, a->rn, a->rm, a->ra, a->index);
66
}
67
68
-static bool trans_BFMMLA(DisasContext *s, arg_rrrr_esz *a)
69
-{
70
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
71
- return false;
72
- }
73
- return gen_gvec_ool_arg_zzzz(s, gen_helper_gvec_bfmmla, a, 0);
74
-}
75
+TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
76
+ gen_helper_gvec_bfmmla, a, 0)
77
78
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
79
{
80
--
81
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Rename the function to match gen_gvec_ool_arg_zzzz,
4
and move to be adjacent.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-14-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 18 +++++++++---------
12
1 file changed, 9 insertions(+), 9 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
19
return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, data);
20
}
21
22
+static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn,
23
+ arg_rrxr_esz *a)
24
+{
25
+ return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
26
+}
27
+
28
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
29
static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
30
int rd, int rn, int pg, int data)
31
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz,
32
* SVE Multiply - Indexed
33
*/
34
35
-static bool do_zzxz_ool(DisasContext *s, arg_rrxr_esz *a,
36
- gen_helper_gvec_4 *fn)
37
-{
38
- return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
39
-}
40
-
41
#define DO_RRXR(NAME, FUNC) \
42
static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
43
- { return do_zzxz_ool(s, a, FUNC); }
44
+ { return gen_gvec_ool_arg_zzxz(s, FUNC, a); }
45
46
DO_RRXR(trans_SDOT_zzxw_s, gen_helper_gvec_sdot_idx_b)
47
DO_RRXR(trans_SDOT_zzxw_d, gen_helper_gvec_sdot_idx_h)
48
@@ -XXX,XX +XXX,XX @@ static bool trans_SUDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
49
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
50
return false;
51
}
52
- return do_zzxz_ool(s, a, gen_helper_gvec_sudot_idx_b);
53
+ return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_sudot_idx_b, a);
54
}
55
56
static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
57
@@ -XXX,XX +XXX,XX @@ static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
58
if (!dc_isar_feature(aa64_sve_i8mm, s)) {
59
return false;
60
}
61
- return do_zzxz_ool(s, a, gen_helper_gvec_usdot_idx_b);
62
+ return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_usdot_idx_b, a);
63
}
64
65
#undef DO_RRXR
66
--
67
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zzxz to TRANS_FEAT. Also include
5
BFDOT_zzxz, which was using gen_gvec_ool_zzzz.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-15-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/translate-sve.c | 48 +++++++++++---------------------------
13
1 file changed, 14 insertions(+), 34 deletions(-)
14
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-sve.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(DOT_zzzz, aa64_sve, gen_gvec_ool_zzzz,
20
* SVE Multiply - Indexed
21
*/
22
23
-#define DO_RRXR(NAME, FUNC) \
24
- static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
25
- { return gen_gvec_ool_arg_zzxz(s, FUNC, a); }
26
+TRANS_FEAT(SDOT_zzxw_s, aa64_sve, gen_gvec_ool_arg_zzxz,
27
+ gen_helper_gvec_sdot_idx_b, a)
28
+TRANS_FEAT(SDOT_zzxw_d, aa64_sve, gen_gvec_ool_arg_zzxz,
29
+ gen_helper_gvec_sdot_idx_h, a)
30
+TRANS_FEAT(UDOT_zzxw_s, aa64_sve, gen_gvec_ool_arg_zzxz,
31
+ gen_helper_gvec_udot_idx_b, a)
32
+TRANS_FEAT(UDOT_zzxw_d, aa64_sve, gen_gvec_ool_arg_zzxz,
33
+ gen_helper_gvec_udot_idx_h, a)
34
35
-DO_RRXR(trans_SDOT_zzxw_s, gen_helper_gvec_sdot_idx_b)
36
-DO_RRXR(trans_SDOT_zzxw_d, gen_helper_gvec_sdot_idx_h)
37
-DO_RRXR(trans_UDOT_zzxw_s, gen_helper_gvec_udot_idx_b)
38
-DO_RRXR(trans_UDOT_zzxw_d, gen_helper_gvec_udot_idx_h)
39
-
40
-static bool trans_SUDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
41
-{
42
- if (!dc_isar_feature(aa64_sve_i8mm, s)) {
43
- return false;
44
- }
45
- return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_sudot_idx_b, a);
46
-}
47
-
48
-static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
49
-{
50
- if (!dc_isar_feature(aa64_sve_i8mm, s)) {
51
- return false;
52
- }
53
- return gen_gvec_ool_arg_zzxz(s, gen_helper_gvec_usdot_idx_b, a);
54
-}
55
-
56
-#undef DO_RRXR
57
+TRANS_FEAT(SUDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
58
+ gen_helper_gvec_sudot_idx_b, a)
59
+TRANS_FEAT(USDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
60
+ gen_helper_gvec_usdot_idx_b, a)
61
62
static bool do_sve2_zzz_data(DisasContext *s, int rd, int rn, int rm, int data,
63
gen_helper_gvec_3 *fn)
64
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UMMLA, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
65
66
TRANS_FEAT(BFDOT_zzzz, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
67
gen_helper_gvec_bfdot, a, 0)
68
-
69
-static bool trans_BFDOT_zzxz(DisasContext *s, arg_rrxr_esz *a)
70
-{
71
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
72
- return false;
73
- }
74
- return gen_gvec_ool_zzzz(s, gen_helper_gvec_bfdot_idx,
75
- a->rd, a->rn, a->rm, a->ra, a->index);
76
-}
77
+TRANS_FEAT(BFDOT_zzxz, aa64_sve_bf16, gen_gvec_ool_arg_zzxz,
78
+ gen_helper_gvec_bfdot_idx, a)
79
80
TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
81
gen_helper_gvec_bfmmla, a, 0)
82
--
83
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zzz_data
4
to use TRANS_FEAT and gen_gvec_ool_zzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-16-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 69 ++++++++++++++------------------------
12
1 file changed, 25 insertions(+), 44 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SUDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
19
TRANS_FEAT(USDOT_zzxw_s, aa64_sve_i8mm, gen_gvec_ool_arg_zzxz,
20
gen_helper_gvec_usdot_idx_b, a)
21
22
-static bool do_sve2_zzz_data(DisasContext *s, int rd, int rn, int rm, int data,
23
- gen_helper_gvec_3 *fn)
24
-{
25
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- if (sve_access_check(s)) {
29
- unsigned vsz = vec_full_reg_size(s);
30
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
31
- vec_full_reg_offset(s, rn),
32
- vec_full_reg_offset(s, rm),
33
- vsz, vsz, data, fn);
34
- }
35
- return true;
36
-}
37
-
38
#define DO_SVE2_RRX(NAME, FUNC) \
39
- static bool NAME(DisasContext *s, arg_rrx_esz *a) \
40
- { return do_sve2_zzz_data(s, a->rd, a->rn, a->rm, a->index, FUNC); }
41
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \
42
+ a->rd, a->rn, a->rm, a->index)
43
44
-DO_SVE2_RRX(trans_MUL_zzx_h, gen_helper_gvec_mul_idx_h)
45
-DO_SVE2_RRX(trans_MUL_zzx_s, gen_helper_gvec_mul_idx_s)
46
-DO_SVE2_RRX(trans_MUL_zzx_d, gen_helper_gvec_mul_idx_d)
47
+DO_SVE2_RRX(MUL_zzx_h, gen_helper_gvec_mul_idx_h)
48
+DO_SVE2_RRX(MUL_zzx_s, gen_helper_gvec_mul_idx_s)
49
+DO_SVE2_RRX(MUL_zzx_d, gen_helper_gvec_mul_idx_d)
50
51
-DO_SVE2_RRX(trans_SQDMULH_zzx_h, gen_helper_sve2_sqdmulh_idx_h)
52
-DO_SVE2_RRX(trans_SQDMULH_zzx_s, gen_helper_sve2_sqdmulh_idx_s)
53
-DO_SVE2_RRX(trans_SQDMULH_zzx_d, gen_helper_sve2_sqdmulh_idx_d)
54
+DO_SVE2_RRX(SQDMULH_zzx_h, gen_helper_sve2_sqdmulh_idx_h)
55
+DO_SVE2_RRX(SQDMULH_zzx_s, gen_helper_sve2_sqdmulh_idx_s)
56
+DO_SVE2_RRX(SQDMULH_zzx_d, gen_helper_sve2_sqdmulh_idx_d)
57
58
-DO_SVE2_RRX(trans_SQRDMULH_zzx_h, gen_helper_sve2_sqrdmulh_idx_h)
59
-DO_SVE2_RRX(trans_SQRDMULH_zzx_s, gen_helper_sve2_sqrdmulh_idx_s)
60
-DO_SVE2_RRX(trans_SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_idx_d)
61
+DO_SVE2_RRX(SQRDMULH_zzx_h, gen_helper_sve2_sqrdmulh_idx_h)
62
+DO_SVE2_RRX(SQRDMULH_zzx_s, gen_helper_sve2_sqrdmulh_idx_s)
63
+DO_SVE2_RRX(SQRDMULH_zzx_d, gen_helper_sve2_sqrdmulh_idx_d)
64
65
#undef DO_SVE2_RRX
66
67
#define DO_SVE2_RRX_TB(NAME, FUNC, TOP) \
68
- static bool NAME(DisasContext *s, arg_rrx_esz *a) \
69
- { \
70
- return do_sve2_zzz_data(s, a->rd, a->rn, a->rm, \
71
- (a->index << 1) | TOP, FUNC); \
72
- }
73
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_ool_zzz, FUNC, \
74
+ a->rd, a->rn, a->rm, (a->index << 1) | TOP)
75
76
-DO_SVE2_RRX_TB(trans_SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false)
77
-DO_SVE2_RRX_TB(trans_SQDMULLB_zzx_d, gen_helper_sve2_sqdmull_idx_d, false)
78
-DO_SVE2_RRX_TB(trans_SQDMULLT_zzx_s, gen_helper_sve2_sqdmull_idx_s, true)
79
-DO_SVE2_RRX_TB(trans_SQDMULLT_zzx_d, gen_helper_sve2_sqdmull_idx_d, true)
80
+DO_SVE2_RRX_TB(SQDMULLB_zzx_s, gen_helper_sve2_sqdmull_idx_s, false)
81
+DO_SVE2_RRX_TB(SQDMULLB_zzx_d, gen_helper_sve2_sqdmull_idx_d, false)
82
+DO_SVE2_RRX_TB(SQDMULLT_zzx_s, gen_helper_sve2_sqdmull_idx_s, true)
83
+DO_SVE2_RRX_TB(SQDMULLT_zzx_d, gen_helper_sve2_sqdmull_idx_d, true)
84
85
-DO_SVE2_RRX_TB(trans_SMULLB_zzx_s, gen_helper_sve2_smull_idx_s, false)
86
-DO_SVE2_RRX_TB(trans_SMULLB_zzx_d, gen_helper_sve2_smull_idx_d, false)
87
-DO_SVE2_RRX_TB(trans_SMULLT_zzx_s, gen_helper_sve2_smull_idx_s, true)
88
-DO_SVE2_RRX_TB(trans_SMULLT_zzx_d, gen_helper_sve2_smull_idx_d, true)
89
+DO_SVE2_RRX_TB(SMULLB_zzx_s, gen_helper_sve2_smull_idx_s, false)
90
+DO_SVE2_RRX_TB(SMULLB_zzx_d, gen_helper_sve2_smull_idx_d, false)
91
+DO_SVE2_RRX_TB(SMULLT_zzx_s, gen_helper_sve2_smull_idx_s, true)
92
+DO_SVE2_RRX_TB(SMULLT_zzx_d, gen_helper_sve2_smull_idx_d, true)
93
94
-DO_SVE2_RRX_TB(trans_UMULLB_zzx_s, gen_helper_sve2_umull_idx_s, false)
95
-DO_SVE2_RRX_TB(trans_UMULLB_zzx_d, gen_helper_sve2_umull_idx_d, false)
96
-DO_SVE2_RRX_TB(trans_UMULLT_zzx_s, gen_helper_sve2_umull_idx_s, true)
97
-DO_SVE2_RRX_TB(trans_UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true)
98
+DO_SVE2_RRX_TB(UMULLB_zzx_s, gen_helper_sve2_umull_idx_s, false)
99
+DO_SVE2_RRX_TB(UMULLB_zzx_d, gen_helper_sve2_umull_idx_d, false)
100
+DO_SVE2_RRX_TB(UMULLT_zzx_s, gen_helper_sve2_umull_idx_s, true)
101
+DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true)
102
103
#undef DO_SVE2_RRX_TB
104
105
--
106
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zzzz_data
4
to use TRANS_FEAT and gen_gvec_ool_{zzzz,zzxz}.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-17-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 106 ++++++++++++++-----------------------
12
1 file changed, 41 insertions(+), 65 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ DO_SVE2_RRX_TB(UMULLT_zzx_d, gen_helper_sve2_umull_idx_d, true)
19
20
#undef DO_SVE2_RRX_TB
21
22
-static bool do_sve2_zzzz_data(DisasContext *s, int rd, int rn, int rm, int ra,
23
- int data, gen_helper_gvec_4 *fn)
24
-{
25
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- if (sve_access_check(s)) {
29
- unsigned vsz = vec_full_reg_size(s);
30
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
31
- vec_full_reg_offset(s, rn),
32
- vec_full_reg_offset(s, rm),
33
- vec_full_reg_offset(s, ra),
34
- vsz, vsz, data, fn);
35
- }
36
- return true;
37
-}
38
-
39
#define DO_SVE2_RRXR(NAME, FUNC) \
40
- static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
41
- { return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->ra, a->index, FUNC); }
42
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_arg_zzxz, FUNC, a)
43
44
-DO_SVE2_RRXR(trans_MLA_zzxz_h, gen_helper_gvec_mla_idx_h)
45
-DO_SVE2_RRXR(trans_MLA_zzxz_s, gen_helper_gvec_mla_idx_s)
46
-DO_SVE2_RRXR(trans_MLA_zzxz_d, gen_helper_gvec_mla_idx_d)
47
+DO_SVE2_RRXR(MLA_zzxz_h, gen_helper_gvec_mla_idx_h)
48
+DO_SVE2_RRXR(MLA_zzxz_s, gen_helper_gvec_mla_idx_s)
49
+DO_SVE2_RRXR(MLA_zzxz_d, gen_helper_gvec_mla_idx_d)
50
51
-DO_SVE2_RRXR(trans_MLS_zzxz_h, gen_helper_gvec_mls_idx_h)
52
-DO_SVE2_RRXR(trans_MLS_zzxz_s, gen_helper_gvec_mls_idx_s)
53
-DO_SVE2_RRXR(trans_MLS_zzxz_d, gen_helper_gvec_mls_idx_d)
54
+DO_SVE2_RRXR(MLS_zzxz_h, gen_helper_gvec_mls_idx_h)
55
+DO_SVE2_RRXR(MLS_zzxz_s, gen_helper_gvec_mls_idx_s)
56
+DO_SVE2_RRXR(MLS_zzxz_d, gen_helper_gvec_mls_idx_d)
57
58
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h)
59
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s)
60
-DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d)
61
+DO_SVE2_RRXR(SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h)
62
+DO_SVE2_RRXR(SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s)
63
+DO_SVE2_RRXR(SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d)
64
65
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h)
66
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s)
67
-DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d)
68
+DO_SVE2_RRXR(SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h)
69
+DO_SVE2_RRXR(SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s)
70
+DO_SVE2_RRXR(SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d)
71
72
#undef DO_SVE2_RRXR
73
74
#define DO_SVE2_RRXR_TB(NAME, FUNC, TOP) \
75
- static bool NAME(DisasContext *s, arg_rrxr_esz *a) \
76
- { \
77
- return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->rd, \
78
- (a->index << 1) | TOP, FUNC); \
79
- }
80
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \
81
+ a->rd, a->rn, a->rm, a->ra, (a->index << 1) | TOP)
82
83
-DO_SVE2_RRXR_TB(trans_SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false)
84
-DO_SVE2_RRXR_TB(trans_SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false)
85
-DO_SVE2_RRXR_TB(trans_SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true)
86
-DO_SVE2_RRXR_TB(trans_SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true)
87
+DO_SVE2_RRXR_TB(SQDMLALB_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, false)
88
+DO_SVE2_RRXR_TB(SQDMLALB_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, false)
89
+DO_SVE2_RRXR_TB(SQDMLALT_zzxw_s, gen_helper_sve2_sqdmlal_idx_s, true)
90
+DO_SVE2_RRXR_TB(SQDMLALT_zzxw_d, gen_helper_sve2_sqdmlal_idx_d, true)
91
92
-DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false)
93
-DO_SVE2_RRXR_TB(trans_SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false)
94
-DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true)
95
-DO_SVE2_RRXR_TB(trans_SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true)
96
+DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, false)
97
+DO_SVE2_RRXR_TB(SQDMLSLB_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, false)
98
+DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_s, gen_helper_sve2_sqdmlsl_idx_s, true)
99
+DO_SVE2_RRXR_TB(SQDMLSLT_zzxw_d, gen_helper_sve2_sqdmlsl_idx_d, true)
100
101
-DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false)
102
-DO_SVE2_RRXR_TB(trans_SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false)
103
-DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true)
104
-DO_SVE2_RRXR_TB(trans_SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true)
105
+DO_SVE2_RRXR_TB(SMLALB_zzxw_s, gen_helper_sve2_smlal_idx_s, false)
106
+DO_SVE2_RRXR_TB(SMLALB_zzxw_d, gen_helper_sve2_smlal_idx_d, false)
107
+DO_SVE2_RRXR_TB(SMLALT_zzxw_s, gen_helper_sve2_smlal_idx_s, true)
108
+DO_SVE2_RRXR_TB(SMLALT_zzxw_d, gen_helper_sve2_smlal_idx_d, true)
109
110
-DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false)
111
-DO_SVE2_RRXR_TB(trans_UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false)
112
-DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true)
113
-DO_SVE2_RRXR_TB(trans_UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true)
114
+DO_SVE2_RRXR_TB(UMLALB_zzxw_s, gen_helper_sve2_umlal_idx_s, false)
115
+DO_SVE2_RRXR_TB(UMLALB_zzxw_d, gen_helper_sve2_umlal_idx_d, false)
116
+DO_SVE2_RRXR_TB(UMLALT_zzxw_s, gen_helper_sve2_umlal_idx_s, true)
117
+DO_SVE2_RRXR_TB(UMLALT_zzxw_d, gen_helper_sve2_umlal_idx_d, true)
118
119
-DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false)
120
-DO_SVE2_RRXR_TB(trans_SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false)
121
-DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true)
122
-DO_SVE2_RRXR_TB(trans_SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true)
123
+DO_SVE2_RRXR_TB(SMLSLB_zzxw_s, gen_helper_sve2_smlsl_idx_s, false)
124
+DO_SVE2_RRXR_TB(SMLSLB_zzxw_d, gen_helper_sve2_smlsl_idx_d, false)
125
+DO_SVE2_RRXR_TB(SMLSLT_zzxw_s, gen_helper_sve2_smlsl_idx_s, true)
126
+DO_SVE2_RRXR_TB(SMLSLT_zzxw_d, gen_helper_sve2_smlsl_idx_d, true)
127
128
-DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false)
129
-DO_SVE2_RRXR_TB(trans_UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false)
130
-DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true)
131
-DO_SVE2_RRXR_TB(trans_UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true)
132
+DO_SVE2_RRXR_TB(UMLSLB_zzxw_s, gen_helper_sve2_umlsl_idx_s, false)
133
+DO_SVE2_RRXR_TB(UMLSLB_zzxw_d, gen_helper_sve2_umlsl_idx_d, false)
134
+DO_SVE2_RRXR_TB(UMLSLT_zzxw_s, gen_helper_sve2_umlsl_idx_s, true)
135
+DO_SVE2_RRXR_TB(UMLSLT_zzxw_d, gen_helper_sve2_umlsl_idx_d, true)
136
137
#undef DO_SVE2_RRXR_TB
138
139
#define DO_SVE2_RRXR_ROT(NAME, FUNC) \
140
- static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
141
- { \
142
- return do_sve2_zzzz_data(s, a->rd, a->rn, a->rm, a->ra, \
143
- (a->index << 2) | a->rot, FUNC); \
144
- }
145
+ TRANS_FEAT(NAME, aa64_sve2, gen_gvec_ool_zzzz, FUNC, \
146
+ a->rd, a->rn, a->rm, a->ra, (a->index << 2) | a->rot)
147
148
DO_SVE2_RRXR_ROT(CMLA_zzxz_h, gen_helper_sve2_cmla_idx_h)
149
DO_SVE2_RRXR_ROT(CMLA_zzxz_s, gen_helper_sve2_cmla_idx_s)
150
--
151
2.25.1
diff view generated by jsdifflib
1
Add the infrastructure for building and invoking a decodetree decoder
1
From: Richard Henderson <richard.henderson@linaro.org>
2
for the AArch32 Neon encodings. At the moment the new decoder covers
3
nothing, so we always fall back to the existing hand-written decode.
4
2
5
We follow the same pattern we did for the VFP decodetree conversion
3
Convert SVE translation functions using do_sve2_zzw_data
6
(commit 78e138bc1f672c145ef6ace74617d and following): code that deals
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
7
with Neon will be moving gradually out to translate-neon.vfp.inc,
8
which we #include into translate.c.
9
5
10
In order to share the decode files between A32 and T32, we
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
split Neon into 3 parts:
7
Message-id: 20220527181907.189259-18-richard.henderson@linaro.org
12
* data-processing
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
* load-store
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
* 'shared' encodings
10
---
11
target/arm/translate-sve.c | 297 ++++++++++++++++++-------------------
12
1 file changed, 145 insertions(+), 152 deletions(-)
15
13
16
The first two groups of instructions have similar but not identical
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
A32 and T32 encodings, so we need to manually transform the T32
18
encoding into the A32 one before calling the decoder; the third group
19
covers the Neon instructions which are identical in A32 and T32.
20
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-id: 20200430181003.21682-4-peter.maydell@linaro.org
24
---
25
target/arm/neon-dp.decode | 29 ++++++++++++++++++++++++++
26
target/arm/neon-ls.decode | 29 ++++++++++++++++++++++++++
27
target/arm/neon-shared.decode | 27 +++++++++++++++++++++++++
28
target/arm/translate-neon.inc.c | 32 +++++++++++++++++++++++++++++
29
target/arm/translate.c | 36 +++++++++++++++++++++++++++++++--
30
target/arm/Makefile.objs | 18 +++++++++++++++++
31
6 files changed, 169 insertions(+), 2 deletions(-)
32
create mode 100644 target/arm/neon-dp.decode
33
create mode 100644 target/arm/neon-ls.decode
34
create mode 100644 target/arm/neon-shared.decode
35
create mode 100644 target/arm/translate-neon.inc.c
36
37
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
38
new file mode 100644
39
index XXXXXXX..XXXXXXX
40
--- /dev/null
41
+++ b/target/arm/neon-dp.decode
42
@@ -XXX,XX +XXX,XX @@
43
+# AArch32 Neon data-processing instruction descriptions
44
+#
45
+# Copyright (c) 2020 Linaro, Ltd
46
+#
47
+# This library is free software; you can redistribute it and/or
48
+# modify it under the terms of the GNU Lesser General Public
49
+# License as published by the Free Software Foundation; either
50
+# version 2 of the License, or (at your option) any later version.
51
+#
52
+# This library is distributed in the hope that it will be useful,
53
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
54
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
55
+# Lesser General Public License for more details.
56
+#
57
+# You should have received a copy of the GNU Lesser General Public
58
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
59
+
60
+#
61
+# This file is processed by scripts/decodetree.py
62
+#
63
+
64
+# Encodings for Neon data processing instructions where the T32 encoding
65
+# is a simple transformation of the A32 encoding.
66
+# More specifically, this file covers instructions where the A32 encoding is
67
+# 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
68
+# and the T32 encoding is
69
+# 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
70
+# This file works on the A32 encoding only; calling code for T32 has to
71
+# transform the insn into the A32 version first.
72
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
73
new file mode 100644
74
index XXXXXXX..XXXXXXX
75
--- /dev/null
76
+++ b/target/arm/neon-ls.decode
77
@@ -XXX,XX +XXX,XX @@
78
+# AArch32 Neon load/store instruction descriptions
79
+#
80
+# Copyright (c) 2020 Linaro, Ltd
81
+#
82
+# This library is free software; you can redistribute it and/or
83
+# modify it under the terms of the GNU Lesser General Public
84
+# License as published by the Free Software Foundation; either
85
+# version 2 of the License, or (at your option) any later version.
86
+#
87
+# This library is distributed in the hope that it will be useful,
88
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
89
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
90
+# Lesser General Public License for more details.
91
+#
92
+# You should have received a copy of the GNU Lesser General Public
93
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
94
+
95
+#
96
+# This file is processed by scripts/decodetree.py
97
+#
98
+
99
+# Encodings for Neon load/store instructions where the T32 encoding
100
+# is a simple transformation of the A32 encoding.
101
+# More specifically, this file covers instructions where the A32 encoding is
102
+# 0b1111_0100_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
103
+# and the T32 encoding is
104
+# 0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
105
+# This file works on the A32 encoding only; calling code for T32 has to
106
+# transform the insn into the A32 version first.
107
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
108
new file mode 100644
109
index XXXXXXX..XXXXXXX
110
--- /dev/null
111
+++ b/target/arm/neon-shared.decode
112
@@ -XXX,XX +XXX,XX @@
113
+# AArch32 Neon instruction descriptions
114
+#
115
+# Copyright (c) 2020 Linaro, Ltd
116
+#
117
+# This library is free software; you can redistribute it and/or
118
+# modify it under the terms of the GNU Lesser General Public
119
+# License as published by the Free Software Foundation; either
120
+# version 2 of the License, or (at your option) any later version.
121
+#
122
+# This library is distributed in the hope that it will be useful,
123
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
124
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
125
+# Lesser General Public License for more details.
126
+#
127
+# You should have received a copy of the GNU Lesser General Public
128
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
129
+
130
+#
131
+# This file is processed by scripts/decodetree.py
132
+#
133
+
134
+# Encodings for Neon instructions whose encoding is the same for
135
+# both A32 and T32.
136
+
137
+# More specifically, this covers:
138
+# 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
139
+# 3same ext: 0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
140
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
141
new file mode 100644
142
index XXXXXXX..XXXXXXX
143
--- /dev/null
144
+++ b/target/arm/translate-neon.inc.c
145
@@ -XXX,XX +XXX,XX @@
146
+/*
147
+ * ARM translation: AArch32 Neon instructions
148
+ *
149
+ * Copyright (c) 2003 Fabrice Bellard
150
+ * Copyright (c) 2005-2007 CodeSourcery
151
+ * Copyright (c) 2007 OpenedHand, Ltd.
152
+ * Copyright (c) 2020 Linaro, Ltd.
153
+ *
154
+ * This library is free software; you can redistribute it and/or
155
+ * modify it under the terms of the GNU Lesser General Public
156
+ * License as published by the Free Software Foundation; either
157
+ * version 2 of the License, or (at your option) any later version.
158
+ *
159
+ * This library is distributed in the hope that it will be useful,
160
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
161
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
162
+ * Lesser General Public License for more details.
163
+ *
164
+ * You should have received a copy of the GNU Lesser General Public
165
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
166
+ */
167
+
168
+/*
169
+ * This file is intended to be included from translate.c; it uses
170
+ * some macros and definitions provided by that file.
171
+ * It might be possible to convert it to a standalone .c file eventually.
172
+ */
173
+
174
+/* Include the generated Neon decoder */
175
+#include "decode-neon-dp.inc.c"
176
+#include "decode-neon-ls.inc.c"
177
+#include "decode-neon-shared.inc.c"
178
diff --git a/target/arm/translate.c b/target/arm/translate.c
179
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
180
--- a/target/arm/translate.c
16
--- a/target/arm/translate-sve.c
181
+++ b/target/arm/translate.c
17
+++ b/target/arm/translate-sve.c
182
@@ -XXX,XX +XXX,XX @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
18
@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZPZZ(USQADD, usqadd)
183
19
* SVE2 Widening Integer Arithmetic
184
#define ARM_CP_RW_BIT (1 << 20)
20
*/
185
21
186
-/* Include the VFP decoder */
22
-static bool do_sve2_zzw_ool(DisasContext *s, arg_rrr_esz *a,
187
+/* Include the VFP and Neon decoders */
23
- gen_helper_gvec_3 *fn, int data)
188
#include "translate-vfp.inc.c"
24
-{
189
+#include "translate-neon.inc.c"
25
- if (fn == NULL || !dc_isar_feature(aa64_sve2, s)) {
190
26
- return false;
191
static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
27
- }
28
- if (sve_access_check(s)) {
29
- unsigned vsz = vec_full_reg_size(s);
30
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
31
- vec_full_reg_offset(s, a->rn),
32
- vec_full_reg_offset(s, a->rm),
33
- vsz, vsz, data, fn);
34
- }
35
- return true;
36
-}
37
+static gen_helper_gvec_3 * const saddl_fns[4] = {
38
+ NULL, gen_helper_sve2_saddl_h,
39
+ gen_helper_sve2_saddl_s, gen_helper_sve2_saddl_d,
40
+};
41
+TRANS_FEAT(SADDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
42
+ saddl_fns[a->esz], a, 0)
43
+TRANS_FEAT(SADDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
44
+ saddl_fns[a->esz], a, 3)
45
+TRANS_FEAT(SADDLBT, aa64_sve2, gen_gvec_ool_arg_zzz,
46
+ saddl_fns[a->esz], a, 2)
47
48
-#define DO_SVE2_ZZZ_TB(NAME, name, SEL1, SEL2) \
49
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
50
-{ \
51
- static gen_helper_gvec_3 * const fns[4] = { \
52
- NULL, gen_helper_sve2_##name##_h, \
53
- gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
54
- }; \
55
- return do_sve2_zzw_ool(s, a, fns[a->esz], (SEL2 << 1) | SEL1); \
56
-}
57
+static gen_helper_gvec_3 * const ssubl_fns[4] = {
58
+ NULL, gen_helper_sve2_ssubl_h,
59
+ gen_helper_sve2_ssubl_s, gen_helper_sve2_ssubl_d,
60
+};
61
+TRANS_FEAT(SSUBLB, aa64_sve2, gen_gvec_ool_arg_zzz,
62
+ ssubl_fns[a->esz], a, 0)
63
+TRANS_FEAT(SSUBLT, aa64_sve2, gen_gvec_ool_arg_zzz,
64
+ ssubl_fns[a->esz], a, 3)
65
+TRANS_FEAT(SSUBLBT, aa64_sve2, gen_gvec_ool_arg_zzz,
66
+ ssubl_fns[a->esz], a, 2)
67
+TRANS_FEAT(SSUBLTB, aa64_sve2, gen_gvec_ool_arg_zzz,
68
+ ssubl_fns[a->esz], a, 1)
69
70
-DO_SVE2_ZZZ_TB(SADDLB, saddl, false, false)
71
-DO_SVE2_ZZZ_TB(SSUBLB, ssubl, false, false)
72
-DO_SVE2_ZZZ_TB(SABDLB, sabdl, false, false)
73
+static gen_helper_gvec_3 * const sabdl_fns[4] = {
74
+ NULL, gen_helper_sve2_sabdl_h,
75
+ gen_helper_sve2_sabdl_s, gen_helper_sve2_sabdl_d,
76
+};
77
+TRANS_FEAT(SABDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
78
+ sabdl_fns[a->esz], a, 0)
79
+TRANS_FEAT(SABDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
80
+ sabdl_fns[a->esz], a, 3)
81
82
-DO_SVE2_ZZZ_TB(UADDLB, uaddl, false, false)
83
-DO_SVE2_ZZZ_TB(USUBLB, usubl, false, false)
84
-DO_SVE2_ZZZ_TB(UABDLB, uabdl, false, false)
85
+static gen_helper_gvec_3 * const uaddl_fns[4] = {
86
+ NULL, gen_helper_sve2_uaddl_h,
87
+ gen_helper_sve2_uaddl_s, gen_helper_sve2_uaddl_d,
88
+};
89
+TRANS_FEAT(UADDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
90
+ uaddl_fns[a->esz], a, 0)
91
+TRANS_FEAT(UADDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
92
+ uaddl_fns[a->esz], a, 3)
93
94
-DO_SVE2_ZZZ_TB(SADDLT, saddl, true, true)
95
-DO_SVE2_ZZZ_TB(SSUBLT, ssubl, true, true)
96
-DO_SVE2_ZZZ_TB(SABDLT, sabdl, true, true)
97
+static gen_helper_gvec_3 * const usubl_fns[4] = {
98
+ NULL, gen_helper_sve2_usubl_h,
99
+ gen_helper_sve2_usubl_s, gen_helper_sve2_usubl_d,
100
+};
101
+TRANS_FEAT(USUBLB, aa64_sve2, gen_gvec_ool_arg_zzz,
102
+ usubl_fns[a->esz], a, 0)
103
+TRANS_FEAT(USUBLT, aa64_sve2, gen_gvec_ool_arg_zzz,
104
+ usubl_fns[a->esz], a, 3)
105
106
-DO_SVE2_ZZZ_TB(UADDLT, uaddl, true, true)
107
-DO_SVE2_ZZZ_TB(USUBLT, usubl, true, true)
108
-DO_SVE2_ZZZ_TB(UABDLT, uabdl, true, true)
109
+static gen_helper_gvec_3 * const uabdl_fns[4] = {
110
+ NULL, gen_helper_sve2_uabdl_h,
111
+ gen_helper_sve2_uabdl_s, gen_helper_sve2_uabdl_d,
112
+};
113
+TRANS_FEAT(UABDLB, aa64_sve2, gen_gvec_ool_arg_zzz,
114
+ uabdl_fns[a->esz], a, 0)
115
+TRANS_FEAT(UABDLT, aa64_sve2, gen_gvec_ool_arg_zzz,
116
+ uabdl_fns[a->esz], a, 3)
117
118
-DO_SVE2_ZZZ_TB(SADDLBT, saddl, false, true)
119
-DO_SVE2_ZZZ_TB(SSUBLBT, ssubl, false, true)
120
-DO_SVE2_ZZZ_TB(SSUBLTB, ssubl, true, false)
121
+static gen_helper_gvec_3 * const sqdmull_fns[4] = {
122
+ NULL, gen_helper_sve2_sqdmull_zzz_h,
123
+ gen_helper_sve2_sqdmull_zzz_s, gen_helper_sve2_sqdmull_zzz_d,
124
+};
125
+TRANS_FEAT(SQDMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
126
+ sqdmull_fns[a->esz], a, 0)
127
+TRANS_FEAT(SQDMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
128
+ sqdmull_fns[a->esz], a, 3)
129
130
-DO_SVE2_ZZZ_TB(SQDMULLB_zzz, sqdmull_zzz, false, false)
131
-DO_SVE2_ZZZ_TB(SQDMULLT_zzz, sqdmull_zzz, true, true)
132
+static gen_helper_gvec_3 * const smull_fns[4] = {
133
+ NULL, gen_helper_sve2_smull_zzz_h,
134
+ gen_helper_sve2_smull_zzz_s, gen_helper_sve2_smull_zzz_d,
135
+};
136
+TRANS_FEAT(SMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
137
+ smull_fns[a->esz], a, 0)
138
+TRANS_FEAT(SMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
139
+ smull_fns[a->esz], a, 3)
140
141
-DO_SVE2_ZZZ_TB(SMULLB_zzz, smull_zzz, false, false)
142
-DO_SVE2_ZZZ_TB(SMULLT_zzz, smull_zzz, true, true)
143
+static gen_helper_gvec_3 * const umull_fns[4] = {
144
+ NULL, gen_helper_sve2_umull_zzz_h,
145
+ gen_helper_sve2_umull_zzz_s, gen_helper_sve2_umull_zzz_d,
146
+};
147
+TRANS_FEAT(UMULLB_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
148
+ umull_fns[a->esz], a, 0)
149
+TRANS_FEAT(UMULLT_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
150
+ umull_fns[a->esz], a, 3)
151
152
-DO_SVE2_ZZZ_TB(UMULLB_zzz, umull_zzz, false, false)
153
-DO_SVE2_ZZZ_TB(UMULLT_zzz, umull_zzz, true, true)
154
-
155
-static bool do_eor_tb(DisasContext *s, arg_rrr_esz *a, bool sel1)
156
-{
157
- static gen_helper_gvec_3 * const fns[4] = {
158
- gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h,
159
- gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d,
160
- };
161
- return do_sve2_zzw_ool(s, a, fns[a->esz], (!sel1 << 1) | sel1);
162
-}
163
-
164
-static bool trans_EORBT(DisasContext *s, arg_rrr_esz *a)
165
-{
166
- return do_eor_tb(s, a, false);
167
-}
168
-
169
-static bool trans_EORTB(DisasContext *s, arg_rrr_esz *a)
170
-{
171
- return do_eor_tb(s, a, true);
172
-}
173
+static gen_helper_gvec_3 * const eoril_fns[4] = {
174
+ gen_helper_sve2_eoril_b, gen_helper_sve2_eoril_h,
175
+ gen_helper_sve2_eoril_s, gen_helper_sve2_eoril_d,
176
+};
177
+TRANS_FEAT(EORBT, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 2)
178
+TRANS_FEAT(EORTB, aa64_sve2, gen_gvec_ool_arg_zzz, eoril_fns[a->esz], a, 1)
179
180
static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
192
{
181
{
193
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
182
@@ -XXX,XX +XXX,XX @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
194
/* Unconditional instructions. */
183
if (a->esz == 0 && !dc_isar_feature(aa64_sve2_pmull128, s)) {
195
/* TODO: Perhaps merge these into one decodetree output file. */
184
return false;
196
if (disas_a32_uncond(s, insn) ||
197
- disas_vfp_uncond(s, insn)) {
198
+ disas_vfp_uncond(s, insn) ||
199
+ disas_neon_dp(s, insn) ||
200
+ disas_neon_ls(s, insn) ||
201
+ disas_neon_shared(s, insn)) {
202
return;
203
}
204
/* fall back to legacy decoder */
205
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
206
ARCH(6T2);
207
}
185
}
208
186
- return do_sve2_zzw_ool(s, a, fns[a->esz], sel);
209
+ if ((insn & 0xef000000) == 0xef000000) {
187
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
210
+ /*
188
}
211
+ * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
189
212
+ * transform into
190
-static bool trans_PMULLB(DisasContext *s, arg_rrr_esz *a)
213
+ * A32 encodings 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
191
-{
214
+ */
192
- return do_trans_pmull(s, a, false);
215
+ uint32_t a32_insn = (insn & 0xe2ffffff) |
193
-}
216
+ ((insn & (1 << 28)) >> 4) | (1 << 28);
194
+TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false)
217
+
195
+TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true)
218
+ if (disas_neon_dp(s, a32_insn)) {
196
219
+ return;
197
-static bool trans_PMULLT(DisasContext *s, arg_rrr_esz *a)
220
+ }
198
-{
221
+ }
199
- return do_trans_pmull(s, a, true);
222
+
200
-}
223
+ if ((insn & 0xff100000) == 0xf9000000) {
201
+static gen_helper_gvec_3 * const saddw_fns[4] = {
224
+ /*
202
+ NULL, gen_helper_sve2_saddw_h,
225
+ * T32 encodings 0b1111_1001_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
203
+ gen_helper_sve2_saddw_s, gen_helper_sve2_saddw_d,
226
+ * transform into
204
+};
227
+ * A32 encodings 0b1111_0100_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
205
+TRANS_FEAT(SADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 0)
228
+ */
206
+TRANS_FEAT(SADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, saddw_fns[a->esz], a, 1)
229
+ uint32_t a32_insn = (insn & 0x00ffffff) | 0xf4000000;
207
230
+
208
-#define DO_SVE2_ZZZ_WTB(NAME, name, SEL2) \
231
+ if (disas_neon_ls(s, a32_insn)) {
209
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
232
+ return;
210
-{ \
233
+ }
211
- static gen_helper_gvec_3 * const fns[4] = { \
234
+ }
212
- NULL, gen_helper_sve2_##name##_h, \
235
+
213
- gen_helper_sve2_##name##_s, gen_helper_sve2_##name##_d, \
236
/*
214
- }; \
237
* TODO: Perhaps merge these into one decodetree output file.
215
- return do_sve2_zzw_ool(s, a, fns[a->esz], SEL2); \
238
* Note disas_vfp is written for a32 with cond field in the
216
-}
239
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
217
+static gen_helper_gvec_3 * const ssubw_fns[4] = {
240
*/
218
+ NULL, gen_helper_sve2_ssubw_h,
241
if (disas_t32(s, insn) ||
219
+ gen_helper_sve2_ssubw_s, gen_helper_sve2_ssubw_d,
242
disas_vfp_uncond(s, insn) ||
220
+};
243
+ disas_neon_shared(s, insn) ||
221
+TRANS_FEAT(SSUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 0)
244
((insn >> 28) == 0xe && disas_vfp(s, insn))) {
222
+TRANS_FEAT(SSUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, ssubw_fns[a->esz], a, 1)
245
return;
223
246
}
224
-DO_SVE2_ZZZ_WTB(SADDWB, saddw, false)
247
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
225
-DO_SVE2_ZZZ_WTB(SADDWT, saddw, true)
248
index XXXXXXX..XXXXXXX 100644
226
-DO_SVE2_ZZZ_WTB(SSUBWB, ssubw, false)
249
--- a/target/arm/Makefile.objs
227
-DO_SVE2_ZZZ_WTB(SSUBWT, ssubw, true)
250
+++ b/target/arm/Makefile.objs
228
+static gen_helper_gvec_3 * const uaddw_fns[4] = {
251
@@ -XXX,XX +XXX,XX @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
229
+ NULL, gen_helper_sve2_uaddw_h,
252
     $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
230
+ gen_helper_sve2_uaddw_s, gen_helper_sve2_uaddw_d,
253
     "GEN", $(TARGET_DIR)$@)
231
+};
254
232
+TRANS_FEAT(UADDWB, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 0)
255
+target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
233
+TRANS_FEAT(UADDWT, aa64_sve2, gen_gvec_ool_arg_zzz, uaddw_fns[a->esz], a, 1)
256
+    $(call quiet-command,\
234
257
+     $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
235
-DO_SVE2_ZZZ_WTB(UADDWB, uaddw, false)
258
+     "GEN", $(TARGET_DIR)$@)
236
-DO_SVE2_ZZZ_WTB(UADDWT, uaddw, true)
259
+
237
-DO_SVE2_ZZZ_WTB(USUBWB, usubw, false)
260
+target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
238
-DO_SVE2_ZZZ_WTB(USUBWT, usubw, true)
261
+    $(call quiet-command,\
239
+static gen_helper_gvec_3 * const usubw_fns[4] = {
262
+     $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
240
+ NULL, gen_helper_sve2_usubw_h,
263
+     "GEN", $(TARGET_DIR)$@)
241
+ gen_helper_sve2_usubw_s, gen_helper_sve2_usubw_d,
264
+
242
+};
265
+target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
243
+TRANS_FEAT(USUBWB, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 0)
266
+    $(call quiet-command,\
244
+TRANS_FEAT(USUBWT, aa64_sve2, gen_gvec_ool_arg_zzz, usubw_fns[a->esz], a, 1)
267
+     $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
245
268
+     "GEN", $(TARGET_DIR)$@)
246
static void gen_sshll_vec(unsigned vece, TCGv_vec d, TCGv_vec n, int64_t imm)
269
+
247
{
270
target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
248
@@ -XXX,XX +XXX,XX @@ static bool trans_USHLLT(DisasContext *s, arg_rri_esz *a)
271
    $(call quiet-command,\
249
return do_sve2_shll_tb(s, a, true, true);
272
     $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
250
}
273
@@ -XXX,XX +XXX,XX @@ target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
251
274
     "GEN", $(TARGET_DIR)$@)
252
-static bool trans_BEXT(DisasContext *s, arg_rrr_esz *a)
275
253
-{
276
target/arm/translate-sve.o: target/arm/decode-sve.inc.c
254
- static gen_helper_gvec_3 * const fns[4] = {
277
+target/arm/translate.o: target/arm/decode-neon-shared.inc.c
255
- gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
278
+target/arm/translate.o: target/arm/decode-neon-dp.inc.c
256
- gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
279
+target/arm/translate.o: target/arm/decode-neon-ls.inc.c
257
- };
280
target/arm/translate.o: target/arm/decode-vfp.inc.c
258
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
281
target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
259
- return false;
282
target/arm/translate.o: target/arm/decode-a32.inc.c
260
- }
261
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
262
-}
263
+static gen_helper_gvec_3 * const bext_fns[4] = {
264
+ gen_helper_sve2_bext_b, gen_helper_sve2_bext_h,
265
+ gen_helper_sve2_bext_s, gen_helper_sve2_bext_d,
266
+};
267
+TRANS_FEAT(BEXT, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
268
+ bext_fns[a->esz], a, 0)
269
270
-static bool trans_BDEP(DisasContext *s, arg_rrr_esz *a)
271
-{
272
- static gen_helper_gvec_3 * const fns[4] = {
273
- gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
274
- gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
275
- };
276
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
277
- return false;
278
- }
279
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
280
-}
281
+static gen_helper_gvec_3 * const bdep_fns[4] = {
282
+ gen_helper_sve2_bdep_b, gen_helper_sve2_bdep_h,
283
+ gen_helper_sve2_bdep_s, gen_helper_sve2_bdep_d,
284
+};
285
+TRANS_FEAT(BDEP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
286
+ bdep_fns[a->esz], a, 0)
287
288
-static bool trans_BGRP(DisasContext *s, arg_rrr_esz *a)
289
-{
290
- static gen_helper_gvec_3 * const fns[4] = {
291
- gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
292
- gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
293
- };
294
- if (!dc_isar_feature(aa64_sve2_bitperm, s)) {
295
- return false;
296
- }
297
- return do_sve2_zzw_ool(s, a, fns[a->esz], 0);
298
-}
299
+static gen_helper_gvec_3 * const bgrp_fns[4] = {
300
+ gen_helper_sve2_bgrp_b, gen_helper_sve2_bgrp_h,
301
+ gen_helper_sve2_bgrp_s, gen_helper_sve2_bgrp_d,
302
+};
303
+TRANS_FEAT(BGRP, aa64_sve2_bitperm, gen_gvec_ool_arg_zzz,
304
+ bgrp_fns[a->esz], a, 0)
305
306
-static bool do_cadd(DisasContext *s, arg_rrr_esz *a, bool sq, bool rot)
307
-{
308
- static gen_helper_gvec_3 * const fns[2][4] = {
309
- { gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
310
- gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d },
311
- { gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h,
312
- gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d },
313
- };
314
- return do_sve2_zzw_ool(s, a, fns[sq][a->esz], rot);
315
-}
316
+static gen_helper_gvec_3 * const cadd_fns[4] = {
317
+ gen_helper_sve2_cadd_b, gen_helper_sve2_cadd_h,
318
+ gen_helper_sve2_cadd_s, gen_helper_sve2_cadd_d,
319
+};
320
+TRANS_FEAT(CADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz,
321
+ cadd_fns[a->esz], a, 0)
322
+TRANS_FEAT(CADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz,
323
+ cadd_fns[a->esz], a, 1)
324
325
-static bool trans_CADD_rot90(DisasContext *s, arg_rrr_esz *a)
326
-{
327
- return do_cadd(s, a, false, false);
328
-}
329
-
330
-static bool trans_CADD_rot270(DisasContext *s, arg_rrr_esz *a)
331
-{
332
- return do_cadd(s, a, false, true);
333
-}
334
-
335
-static bool trans_SQCADD_rot90(DisasContext *s, arg_rrr_esz *a)
336
-{
337
- return do_cadd(s, a, true, false);
338
-}
339
-
340
-static bool trans_SQCADD_rot270(DisasContext *s, arg_rrr_esz *a)
341
-{
342
- return do_cadd(s, a, true, true);
343
-}
344
+static gen_helper_gvec_3 * const sqcadd_fns[4] = {
345
+ gen_helper_sve2_sqcadd_b, gen_helper_sve2_sqcadd_h,
346
+ gen_helper_sve2_sqcadd_s, gen_helper_sve2_sqcadd_d,
347
+};
348
+TRANS_FEAT(SQCADD_rot90, aa64_sve2, gen_gvec_ool_arg_zzz,
349
+ sqcadd_fns[a->esz], a, 0)
350
+TRANS_FEAT(SQCADD_rot270, aa64_sve2, gen_gvec_ool_arg_zzz,
351
+ sqcadd_fns[a->esz], a, 1)
352
353
static gen_helper_gvec_4 * const sabal_fns[4] = {
354
NULL, gen_helper_sve2_sabal_h,
283
--
355
--
284
2.20.1
356
2.25.1
285
286
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This is the last direct user of tcg_gen_gvec_4_ool.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-19-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 17 ++---------------
11
1 file changed, 2 insertions(+), 15 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_4 * const sqrdcmlah_fns[] = {
18
TRANS_FEAT(SQRDCMLAH_zzzz, aa64_sve2, gen_gvec_ool_zzzz,
19
sqrdcmlah_fns[a->esz], a->rd, a->rn, a->rm, a->ra, a->rot)
20
21
-static bool trans_USDOT_zzzz(DisasContext *s, arg_USDOT_zzzz *a)
22
-{
23
- if (a->esz != 2 || !dc_isar_feature(aa64_sve_i8mm, s)) {
24
- return false;
25
- }
26
- if (sve_access_check(s)) {
27
- unsigned vsz = vec_full_reg_size(s);
28
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
29
- vec_full_reg_offset(s, a->rn),
30
- vec_full_reg_offset(s, a->rm),
31
- vec_full_reg_offset(s, a->ra),
32
- vsz, vsz, 0, gen_helper_gvec_usdot_b);
33
- }
34
- return true;
35
-}
36
+TRANS_FEAT(USDOT_zzzz, aa64_sve_i8mm, gen_gvec_ool_arg_zzzz,
37
+ a->esz == 2 ? gen_helper_gvec_usdot_b : NULL, a, 0)
38
39
TRANS_FEAT(AESMC, aa64_sve2_aes, gen_gvec_ool_zz,
40
gen_helper_crypto_aesmc, a->rd, a->rd, a->decrypt)
41
--
42
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-20-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 37 +++++++++++++++----------------------
9
1 file changed, 15 insertions(+), 22 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
19
-static void gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
20
+static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
21
int rd, int rn, int pg, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- pred_full_reg_offset(s, pg),
27
- vsz, vsz, data, fn);
28
+ if (fn == NULL) {
29
+ return false;
30
+ }
31
+ if (sve_access_check(s)) {
32
+ unsigned vsz = vec_full_reg_size(s);
33
+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
34
+ vec_full_reg_offset(s, rn),
35
+ pred_full_reg_offset(s, pg),
36
+ vsz, vsz, data, fn);
37
+ }
38
+ return true;
39
}
40
41
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
42
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
43
44
static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
45
{
46
- if (fn == NULL) {
47
- return false;
48
- }
49
- if (sve_access_check(s)) {
50
- gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
51
- }
52
- return true;
53
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
54
}
55
56
#define DO_ZPZ(NAME, name) \
57
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
58
gen_helper_sve_movz_b, gen_helper_sve_movz_h,
59
gen_helper_sve_movz_s, gen_helper_sve_movz_d,
60
};
61
-
62
- if (sve_access_check(s)) {
63
- gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
64
- }
65
- return true;
66
+ return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
67
}
68
69
static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
70
gen_helper_gvec_3 *fn)
71
{
72
- if (sve_access_check(s)) {
73
- gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
74
- }
75
- return true;
76
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
77
}
78
79
static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
80
--
81
2.25.1
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add support for the RTC.
3
Use gen_gvec_ool_arg_zpz instead of gen_gvec_ool_zzp
4
when the arguments come from arg_rpr_esz.
5
Replaces do_zpz_ool.
4
6
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20220527181907.189259-21-richard.henderson@linaro.org
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200427181649.26851-12-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
hw/arm/xlnx-versal-virt.c | 22 ++++++++++++++++++++++
12
target/arm/translate-sve.c | 45 +++++++++++++++++++++-----------------
12
1 file changed, 22 insertions(+)
13
1 file changed, 25 insertions(+), 20 deletions(-)
13
14
14
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/xlnx-versal-virt.c
17
--- a/target/arm/translate-sve.c
17
+++ b/hw/arm/xlnx-versal-virt.c
18
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void fdt_add_sd_nodes(VersalVirt *s)
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
19
}
20
return true;
20
}
21
}
21
22
22
+static void fdt_add_rtc_node(VersalVirt *s)
23
+static bool gen_gvec_ool_arg_zpz(DisasContext *s, gen_helper_gvec_3 *fn,
24
+ arg_rpr_esz *a, int data)
23
+{
25
+{
24
+ const char compat[] = "xlnx,zynqmp-rtc";
26
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, data);
25
+ const char interrupt_names[] = "alarm\0sec";
26
+ char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC);
27
+
28
+ qemu_fdt_add_subnode(s->fdt, name);
29
+
30
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
31
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ,
32
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI,
33
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ,
34
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
35
+ qemu_fdt_setprop(s->fdt, name, "interrupt-names",
36
+ interrupt_names, sizeof(interrupt_names));
37
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
38
+ 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE);
39
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
40
+ g_free(name);
41
+}
27
+}
42
+
28
+
43
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
29
+
30
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
31
static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
32
int rd, int rn, int rm, int pg, int data)
33
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
34
*** SVE Integer Arithmetic - Unary Predicated Group
35
*/
36
37
-static bool do_zpz_ool(DisasContext *s, arg_rpr_esz *a, gen_helper_gvec_3 *fn)
38
-{
39
- return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, 0);
40
-}
41
-
42
#define DO_ZPZ(NAME, name) \
43
static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
44
{ \
45
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
46
gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
47
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
48
}; \
49
- return do_zpz_ool(s, a, fns[a->esz]); \
50
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0); \
51
}
52
53
DO_ZPZ(CLS, cls)
54
@@ -XXX,XX +XXX,XX @@ static bool trans_FABS(DisasContext *s, arg_rpr_esz *a)
55
gen_helper_sve_fabs_s,
56
gen_helper_sve_fabs_d
57
};
58
- return do_zpz_ool(s, a, fns[a->esz]);
59
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
60
}
61
62
static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a)
63
@@ -XXX,XX +XXX,XX @@ static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a)
64
gen_helper_sve_fneg_s,
65
gen_helper_sve_fneg_d
66
};
67
- return do_zpz_ool(s, a, fns[a->esz]);
68
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
69
}
70
71
static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a)
72
@@ -XXX,XX +XXX,XX @@ static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a)
73
gen_helper_sve_sxtb_s,
74
gen_helper_sve_sxtb_d
75
};
76
- return do_zpz_ool(s, a, fns[a->esz]);
77
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
78
}
79
80
static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a)
81
@@ -XXX,XX +XXX,XX @@ static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a)
82
gen_helper_sve_uxtb_s,
83
gen_helper_sve_uxtb_d
84
};
85
- return do_zpz_ool(s, a, fns[a->esz]);
86
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
87
}
88
89
static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a)
90
@@ -XXX,XX +XXX,XX @@ static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a)
91
gen_helper_sve_sxth_s,
92
gen_helper_sve_sxth_d
93
};
94
- return do_zpz_ool(s, a, fns[a->esz]);
95
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
96
}
97
98
static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a)
99
@@ -XXX,XX +XXX,XX @@ static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a)
100
gen_helper_sve_uxth_s,
101
gen_helper_sve_uxth_d
102
};
103
- return do_zpz_ool(s, a, fns[a->esz]);
104
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
105
}
106
107
static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a)
44
{
108
{
45
Error *err = NULL;
109
- return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_sxtw_d : NULL);
46
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
110
+ return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_sxtw_d
47
fdt_add_timer_nodes(s);
111
+ : NULL, a, 0);
48
fdt_add_zdma_nodes(s);
112
}
49
fdt_add_sd_nodes(s);
113
50
+ fdt_add_rtc_node(s);
114
static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a)
51
fdt_add_cpu_nodes(s, psci_conduit);
115
{
52
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
116
- return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_uxtw_d : NULL);
53
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
117
+ return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_uxtw_d
118
+ : NULL, a, 0);
119
}
120
121
#undef DO_ZPZ
122
@@ -XXX,XX +XXX,XX @@ static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a)
123
static gen_helper_gvec_3 * const fns[4] = {
124
NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
125
};
126
- return do_zpz_ool(s, a, fns[a->esz]);
127
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
128
}
129
130
/* Call the helper that computes the ARM LastActiveElement pseudocode
131
@@ -XXX,XX +XXX,XX @@ static bool trans_REVB(DisasContext *s, arg_rpr_esz *a)
132
gen_helper_sve_revb_s,
133
gen_helper_sve_revb_d,
134
};
135
- return do_zpz_ool(s, a, fns[a->esz]);
136
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
137
}
138
139
static bool trans_REVH(DisasContext *s, arg_rpr_esz *a)
140
@@ -XXX,XX +XXX,XX @@ static bool trans_REVH(DisasContext *s, arg_rpr_esz *a)
141
gen_helper_sve_revh_s,
142
gen_helper_sve_revh_d,
143
};
144
- return do_zpz_ool(s, a, fns[a->esz]);
145
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
146
}
147
148
static bool trans_REVW(DisasContext *s, arg_rpr_esz *a)
149
{
150
- return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_revw_d : NULL);
151
+ return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_revw_d
152
+ : NULL, a, 0);
153
}
154
155
static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
156
@@ -XXX,XX +XXX,XX @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
157
gen_helper_sve_rbit_s,
158
gen_helper_sve_rbit_d,
159
};
160
- return do_zpz_ool(s, a, fns[a->esz]);
161
+ return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
162
}
163
164
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
165
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zpz_ool(DisasContext *s, arg_rpr_esz *a,
166
if (!dc_isar_feature(aa64_sve2, s)) {
167
return false;
168
}
169
- return do_zpz_ool(s, a, fn);
170
+ return gen_gvec_ool_arg_zpz(s, fn, a, 0);
171
}
172
173
static bool trans_URECPE(DisasContext *s, arg_rpr_esz *a)
54
--
174
--
55
2.20.1
175
2.25.1
56
57
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zpz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-22-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 189 ++++++++++++-------------------------
12
1 file changed, 60 insertions(+), 129 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
19
*** SVE Integer Arithmetic - Unary Predicated Group
20
*/
21
22
-#define DO_ZPZ(NAME, name) \
23
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
24
-{ \
25
- static gen_helper_gvec_3 * const fns[4] = { \
26
- gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
27
- gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
28
+#define DO_ZPZ(NAME, FEAT, name) \
29
+ static gen_helper_gvec_3 * const name##_fns[4] = { \
30
+ gen_helper_##name##_b, gen_helper_##name##_h, \
31
+ gen_helper_##name##_s, gen_helper_##name##_d, \
32
}; \
33
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0); \
34
-}
35
+ TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpz, name##_fns[a->esz], a, 0)
36
37
-DO_ZPZ(CLS, cls)
38
-DO_ZPZ(CLZ, clz)
39
-DO_ZPZ(CNT_zpz, cnt_zpz)
40
-DO_ZPZ(CNOT, cnot)
41
-DO_ZPZ(NOT_zpz, not_zpz)
42
-DO_ZPZ(ABS, abs)
43
-DO_ZPZ(NEG, neg)
44
+DO_ZPZ(CLS, aa64_sve, sve_cls)
45
+DO_ZPZ(CLZ, aa64_sve, sve_clz)
46
+DO_ZPZ(CNT_zpz, aa64_sve, sve_cnt_zpz)
47
+DO_ZPZ(CNOT, aa64_sve, sve_cnot)
48
+DO_ZPZ(NOT_zpz, aa64_sve, sve_not_zpz)
49
+DO_ZPZ(ABS, aa64_sve, sve_abs)
50
+DO_ZPZ(NEG, aa64_sve, sve_neg)
51
+DO_ZPZ(RBIT, aa64_sve, sve_rbit)
52
53
-static bool trans_FABS(DisasContext *s, arg_rpr_esz *a)
54
-{
55
- static gen_helper_gvec_3 * const fns[4] = {
56
- NULL,
57
- gen_helper_sve_fabs_h,
58
- gen_helper_sve_fabs_s,
59
- gen_helper_sve_fabs_d
60
- };
61
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
62
-}
63
+static gen_helper_gvec_3 * const fabs_fns[4] = {
64
+ NULL, gen_helper_sve_fabs_h,
65
+ gen_helper_sve_fabs_s, gen_helper_sve_fabs_d,
66
+};
67
+TRANS_FEAT(FABS, aa64_sve, gen_gvec_ool_arg_zpz, fabs_fns[a->esz], a, 0)
68
69
-static bool trans_FNEG(DisasContext *s, arg_rpr_esz *a)
70
-{
71
- static gen_helper_gvec_3 * const fns[4] = {
72
- NULL,
73
- gen_helper_sve_fneg_h,
74
- gen_helper_sve_fneg_s,
75
- gen_helper_sve_fneg_d
76
- };
77
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
78
-}
79
+static gen_helper_gvec_3 * const fneg_fns[4] = {
80
+ NULL, gen_helper_sve_fneg_h,
81
+ gen_helper_sve_fneg_s, gen_helper_sve_fneg_d,
82
+};
83
+TRANS_FEAT(FNEG, aa64_sve, gen_gvec_ool_arg_zpz, fneg_fns[a->esz], a, 0)
84
85
-static bool trans_SXTB(DisasContext *s, arg_rpr_esz *a)
86
-{
87
- static gen_helper_gvec_3 * const fns[4] = {
88
- NULL,
89
- gen_helper_sve_sxtb_h,
90
- gen_helper_sve_sxtb_s,
91
- gen_helper_sve_sxtb_d
92
- };
93
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
94
-}
95
+static gen_helper_gvec_3 * const sxtb_fns[4] = {
96
+ NULL, gen_helper_sve_sxtb_h,
97
+ gen_helper_sve_sxtb_s, gen_helper_sve_sxtb_d,
98
+};
99
+TRANS_FEAT(SXTB, aa64_sve, gen_gvec_ool_arg_zpz, sxtb_fns[a->esz], a, 0)
100
101
-static bool trans_UXTB(DisasContext *s, arg_rpr_esz *a)
102
-{
103
- static gen_helper_gvec_3 * const fns[4] = {
104
- NULL,
105
- gen_helper_sve_uxtb_h,
106
- gen_helper_sve_uxtb_s,
107
- gen_helper_sve_uxtb_d
108
- };
109
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
110
-}
111
+static gen_helper_gvec_3 * const uxtb_fns[4] = {
112
+ NULL, gen_helper_sve_uxtb_h,
113
+ gen_helper_sve_uxtb_s, gen_helper_sve_uxtb_d,
114
+};
115
+TRANS_FEAT(UXTB, aa64_sve, gen_gvec_ool_arg_zpz, uxtb_fns[a->esz], a, 0)
116
117
-static bool trans_SXTH(DisasContext *s, arg_rpr_esz *a)
118
-{
119
- static gen_helper_gvec_3 * const fns[4] = {
120
- NULL, NULL,
121
- gen_helper_sve_sxth_s,
122
- gen_helper_sve_sxth_d
123
- };
124
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
125
-}
126
+static gen_helper_gvec_3 * const sxth_fns[4] = {
127
+ NULL, NULL, gen_helper_sve_sxth_s, gen_helper_sve_sxth_d
128
+};
129
+TRANS_FEAT(SXTH, aa64_sve, gen_gvec_ool_arg_zpz, sxth_fns[a->esz], a, 0)
130
131
-static bool trans_UXTH(DisasContext *s, arg_rpr_esz *a)
132
-{
133
- static gen_helper_gvec_3 * const fns[4] = {
134
- NULL, NULL,
135
- gen_helper_sve_uxth_s,
136
- gen_helper_sve_uxth_d
137
- };
138
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
139
-}
140
+static gen_helper_gvec_3 * const uxth_fns[4] = {
141
+ NULL, NULL, gen_helper_sve_uxth_s, gen_helper_sve_uxth_d
142
+};
143
+TRANS_FEAT(UXTH, aa64_sve, gen_gvec_ool_arg_zpz, uxth_fns[a->esz], a, 0)
144
145
-static bool trans_SXTW(DisasContext *s, arg_rpr_esz *a)
146
-{
147
- return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_sxtw_d
148
- : NULL, a, 0);
149
-}
150
-
151
-static bool trans_UXTW(DisasContext *s, arg_rpr_esz *a)
152
-{
153
- return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_uxtw_d
154
- : NULL, a, 0);
155
-}
156
-
157
-#undef DO_ZPZ
158
+TRANS_FEAT(SXTW, aa64_sve, gen_gvec_ool_arg_zpz,
159
+ a->esz == 3 ? gen_helper_sve_sxtw_d : NULL, a, 0)
160
+TRANS_FEAT(UXTW, aa64_sve, gen_gvec_ool_arg_zpz,
161
+ a->esz == 3 ? gen_helper_sve_uxtw_d : NULL, a, 0)
162
163
/*
164
*** SVE Integer Reduction Group
165
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(TRN2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
166
*** SVE Permute Vector - Predicated Group
167
*/
168
169
-static bool trans_COMPACT(DisasContext *s, arg_rpr_esz *a)
170
-{
171
- static gen_helper_gvec_3 * const fns[4] = {
172
- NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
173
- };
174
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
175
-}
176
+static gen_helper_gvec_3 * const compact_fns[4] = {
177
+ NULL, NULL, gen_helper_sve_compact_s, gen_helper_sve_compact_d
178
+};
179
+TRANS_FEAT(COMPACT, aa64_sve, gen_gvec_ool_arg_zpz, compact_fns[a->esz], a, 0)
180
181
/* Call the helper that computes the ARM LastActiveElement pseudocode
182
* function, scaled by the element size. This includes the not found
183
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a)
184
return true;
185
}
186
187
-static bool trans_REVB(DisasContext *s, arg_rpr_esz *a)
188
-{
189
- static gen_helper_gvec_3 * const fns[4] = {
190
- NULL,
191
- gen_helper_sve_revb_h,
192
- gen_helper_sve_revb_s,
193
- gen_helper_sve_revb_d,
194
- };
195
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
196
-}
197
+static gen_helper_gvec_3 * const revb_fns[4] = {
198
+ NULL, gen_helper_sve_revb_h,
199
+ gen_helper_sve_revb_s, gen_helper_sve_revb_d,
200
+};
201
+TRANS_FEAT(REVB, aa64_sve, gen_gvec_ool_arg_zpz, revb_fns[a->esz], a, 0)
202
203
-static bool trans_REVH(DisasContext *s, arg_rpr_esz *a)
204
-{
205
- static gen_helper_gvec_3 * const fns[4] = {
206
- NULL,
207
- NULL,
208
- gen_helper_sve_revh_s,
209
- gen_helper_sve_revh_d,
210
- };
211
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
212
-}
213
+static gen_helper_gvec_3 * const revh_fns[4] = {
214
+ NULL, NULL, gen_helper_sve_revh_s, gen_helper_sve_revh_d,
215
+};
216
+TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0)
217
218
-static bool trans_REVW(DisasContext *s, arg_rpr_esz *a)
219
-{
220
- return gen_gvec_ool_arg_zpz(s, a->esz == 3 ? gen_helper_sve_revw_d
221
- : NULL, a, 0);
222
-}
223
-
224
-static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
225
-{
226
- static gen_helper_gvec_3 * const fns[4] = {
227
- gen_helper_sve_rbit_b,
228
- gen_helper_sve_rbit_h,
229
- gen_helper_sve_rbit_s,
230
- gen_helper_sve_rbit_d,
231
- };
232
- return gen_gvec_ool_arg_zpz(s, fns[a->esz], a, 0);
233
-}
234
+TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
235
+ a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0)
236
237
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
238
{
239
--
240
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zpz_data
4
to use TRANS_FEAT and gen_gvec_ool_arg_zpz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-23-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 53 ++++++++++----------------------------
12
1 file changed, 14 insertions(+), 39 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_UADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
19
* SVE2 integer unary operations (predicated)
20
*/
21
22
-static bool do_sve2_zpz_ool(DisasContext *s, arg_rpr_esz *a,
23
- gen_helper_gvec_3 *fn)
24
-{
25
- if (!dc_isar_feature(aa64_sve2, s)) {
26
- return false;
27
- }
28
- return gen_gvec_ool_arg_zpz(s, fn, a, 0);
29
-}
30
+TRANS_FEAT(URECPE, aa64_sve2, gen_gvec_ool_arg_zpz,
31
+ a->esz == 2 ? gen_helper_sve2_urecpe_s : NULL, a, 0)
32
33
-static bool trans_URECPE(DisasContext *s, arg_rpr_esz *a)
34
-{
35
- if (a->esz != 2) {
36
- return false;
37
- }
38
- return do_sve2_zpz_ool(s, a, gen_helper_sve2_urecpe_s);
39
-}
40
+TRANS_FEAT(URSQRTE, aa64_sve2, gen_gvec_ool_arg_zpz,
41
+ a->esz == 2 ? gen_helper_sve2_ursqrte_s : NULL, a, 0)
42
43
-static bool trans_URSQRTE(DisasContext *s, arg_rpr_esz *a)
44
-{
45
- if (a->esz != 2) {
46
- return false;
47
- }
48
- return do_sve2_zpz_ool(s, a, gen_helper_sve2_ursqrte_s);
49
-}
50
+static gen_helper_gvec_3 * const sqabs_fns[4] = {
51
+ gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h,
52
+ gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d,
53
+};
54
+TRANS_FEAT(SQABS, aa64_sve2, gen_gvec_ool_arg_zpz, sqabs_fns[a->esz], a, 0)
55
56
-static bool trans_SQABS(DisasContext *s, arg_rpr_esz *a)
57
-{
58
- static gen_helper_gvec_3 * const fns[4] = {
59
- gen_helper_sve2_sqabs_b, gen_helper_sve2_sqabs_h,
60
- gen_helper_sve2_sqabs_s, gen_helper_sve2_sqabs_d,
61
- };
62
- return do_sve2_zpz_ool(s, a, fns[a->esz]);
63
-}
64
-
65
-static bool trans_SQNEG(DisasContext *s, arg_rpr_esz *a)
66
-{
67
- static gen_helper_gvec_3 * const fns[4] = {
68
- gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h,
69
- gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d,
70
- };
71
- return do_sve2_zpz_ool(s, a, fns[a->esz]);
72
-}
73
+static gen_helper_gvec_3 * const sqneg_fns[4] = {
74
+ gen_helper_sve2_sqneg_b, gen_helper_sve2_sqneg_h,
75
+ gen_helper_sve2_sqneg_s, gen_helper_sve2_sqneg_d,
76
+};
77
+TRANS_FEAT(SQNEG, aa64_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0)
78
79
#define DO_SVE2_ZPZZ(NAME, name) \
80
static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
81
--
82
2.25.1
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add support for SD.
3
Rename the function to match gen_gvec_ool_arg_zpz,
4
and move to be adjacent.
4
5
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20220527181907.189259-24-richard.henderson@linaro.org
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20200427181649.26851-11-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
hw/arm/xlnx-versal-virt.c | 46 +++++++++++++++++++++++++++++++++++++++
11
target/arm/translate-sve.c | 29 ++++++++++++++---------------
12
1 file changed, 46 insertions(+)
12
1 file changed, 14 insertions(+), 15 deletions(-)
13
13
14
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/xlnx-versal-virt.c
16
--- a/target/arm/translate-sve.c
17
+++ b/hw/arm/xlnx-versal-virt.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpz(DisasContext *s, gen_helper_gvec_3 *fn,
19
#include "hw/arm/sysbus-fdt.h"
19
return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, data);
20
#include "hw/arm/fdt.h"
20
}
21
#include "cpu.h"
21
22
+#include "hw/qdev-properties.h"
22
+static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn,
23
#include "hw/arm/xlnx-versal.h"
23
+ arg_rpri_esz *a)
24
24
+{
25
#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
25
+ return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
26
@@ -XXX,XX +XXX,XX @@ static void fdt_add_zdma_nodes(VersalVirt *s)
26
+}
27
28
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
29
static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
30
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
31
return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
32
}
33
34
-static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a,
35
- gen_helper_gvec_3 *fn)
36
-{
37
- return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
38
-}
39
-
40
static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
41
{
42
static gen_helper_gvec_3 * const fns[4] = {
43
@@ -XXX,XX +XXX,XX @@ static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
44
/* Shift by element size is architecturally valid. For
45
arithmetic right-shift, it's the same as by one less. */
46
a->imm = MIN(a->imm, (8 << a->esz) - 1);
47
- return do_zpzi_ool(s, a, fns[a->esz]);
48
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
49
}
50
51
static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
52
@@ -XXX,XX +XXX,XX @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
53
if (a->imm >= (8 << a->esz)) {
54
return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
55
} else {
56
- return do_zpzi_ool(s, a, fns[a->esz]);
57
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
27
}
58
}
28
}
59
}
29
60
30
+static void fdt_add_sd_nodes(VersalVirt *s)
61
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
31
+{
62
if (a->imm >= (8 << a->esz)) {
32
+ const char clocknames[] = "clk_xin\0clk_ahb";
63
return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
33
+ const char compat[] = "arasan,sdhci-8.9a";
64
} else {
34
+ int i;
65
- return do_zpzi_ool(s, a, fns[a->esz]);
35
+
66
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
36
+ for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) {
37
+ uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i;
38
+ char *name = g_strdup_printf("/sdhci@%" PRIx64, addr);
39
+
40
+ qemu_fdt_add_subnode(s->fdt, name);
41
+
42
+ qemu_fdt_setprop_cells(s->fdt, name, "clocks",
43
+ s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
44
+ qemu_fdt_setprop(s->fdt, name, "clock-names",
45
+ clocknames, sizeof(clocknames));
46
+ qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
47
+ GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2,
48
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
49
+ qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
50
+ 2, addr, 2, MM_PMC_SD0_SIZE);
51
+ qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
52
+ g_free(name);
53
+ }
54
+}
55
+
56
static void fdt_nop_memory_nodes(void *fdt, Error **errp)
57
{
58
Error *err = NULL;
59
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
60
}
67
}
61
}
68
}
62
69
63
+static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
70
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
64
+{
71
if (a->imm >= (8 << a->esz)) {
65
+ BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
72
return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
66
+ DeviceState *card;
73
} else {
67
+
74
- return do_zpzi_ool(s, a, fns[a->esz]);
68
+ card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD);
75
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
69
+ object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card),
76
}
70
+ &error_fatal);
77
}
71
+ qdev_prop_set_drive(card, "drive", blk, &error_fatal);
78
72
+ object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
79
@@ -XXX,XX +XXX,XX @@ static bool trans_SQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
73
+}
80
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
74
+
81
return false;
75
static void versal_virt_init(MachineState *machine)
82
}
76
{
83
- return do_zpzi_ool(s, a, fns[a->esz]);
77
VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
84
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
78
int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
85
}
79
+ int i;
86
80
87
static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
81
/*
88
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
82
* If the user provides an Operating System to be loaded, we expect them
89
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
83
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
90
return false;
84
fdt_add_gic_nodes(s);
91
}
85
fdt_add_timer_nodes(s);
92
- return do_zpzi_ool(s, a, fns[a->esz]);
86
fdt_add_zdma_nodes(s);
93
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
87
+ fdt_add_sd_nodes(s);
94
}
88
fdt_add_cpu_nodes(s, psci_conduit);
95
89
fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
96
static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
90
fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
97
@@ -XXX,XX +XXX,XX @@ static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
91
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
98
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
92
memory_region_add_subregion_overlap(get_system_memory(),
99
return false;
93
0, &s->soc.fpd.apu.mr, 0);
100
}
94
101
- return do_zpzi_ool(s, a, fns[a->esz]);
95
+ /* Plugin SD cards. */
102
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
96
+ for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
103
}
97
+ sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
104
98
+ }
105
static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
99
+
106
@@ -XXX,XX +XXX,XX @@ static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
100
s->binfo.ram_size = machine->ram_size;
107
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
101
s->binfo.loader_start = 0x0;
108
return false;
102
s->binfo.get_dtb = versal_virt_get_dtb;
109
}
110
- return do_zpzi_ool(s, a, fns[a->esz]);
111
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
112
}
113
114
static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
115
@@ -XXX,XX +XXX,XX @@ static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
116
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
117
return false;
118
}
119
- return do_zpzi_ool(s, a, fns[a->esz]);
120
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
121
}
122
123
/*
103
--
124
--
104
2.20.1
125
2.25.1
105
106
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Embed the APUs into the SoC type.
3
Convert some SVE translation functions using
4
gen_gvec_ool_arg_zpzi to TRANS_FEAT.
4
5
5
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Message-id: 20220527181907.189259-25-richard.henderson@linaro.org
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
10
Message-id: 20200427181649.26851-8-edgar.iglesias@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
include/hw/arm/xlnx-versal.h | 2 +-
11
target/arm/translate-sve.c | 85 ++++++++++++++------------------------
14
hw/arm/xlnx-versal-virt.c | 4 ++--
12
1 file changed, 30 insertions(+), 55 deletions(-)
15
hw/arm/xlnx-versal.c | 19 +++++--------------
16
3 files changed, 8 insertions(+), 17 deletions(-)
17
13
18
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/xlnx-versal.h
16
--- a/target/arm/translate-sve.c
21
+++ b/include/hw/arm/xlnx-versal.h
17
+++ b/target/arm/translate-sve.c
22
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
18
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
23
struct {
24
struct {
25
MemoryRegion mr;
26
- ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
27
+ ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
28
GICv3State gic;
29
} apu;
30
} fpd;
31
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/xlnx-versal-virt.c
34
+++ b/hw/arm/xlnx-versal-virt.c
35
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
36
s->binfo.get_dtb = versal_virt_get_dtb;
37
s->binfo.modify_dtb = versal_virt_modify_dtb;
38
if (machine->kernel_filename) {
39
- arm_load_kernel(s->soc.fpd.apu.cpu[0], machine, &s->binfo);
40
+ arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo);
41
} else {
42
- AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
43
+ AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0],
44
&s->binfo);
45
/* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
46
* Offset things by 4K. */
47
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/arm/xlnx-versal.c
50
+++ b/hw/arm/xlnx-versal.c
51
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
52
53
for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
54
Object *obj;
55
- char *name;
56
-
57
- obj = object_new(XLNX_VERSAL_ACPU_TYPE);
58
- if (!obj) {
59
- error_report("Unable to create apu.cpu[%d] of type %s",
60
- i, XLNX_VERSAL_ACPU_TYPE);
61
- exit(EXIT_FAILURE);
62
- }
63
-
64
- name = g_strdup_printf("apu-cpu[%d]", i);
65
- object_property_add_child(OBJECT(s), name, obj, &error_fatal);
66
- g_free(name);
67
68
+ object_initialize_child(OBJECT(s), "apu-cpu[*]",
69
+ &s->fpd.apu.cpu[i], sizeof(s->fpd.apu.cpu[i]),
70
+ XLNX_VERSAL_ACPU_TYPE, &error_abort, NULL);
71
+ obj = OBJECT(&s->fpd.apu.cpu[i]);
72
object_property_set_int(obj, s->cfg.psci_conduit,
73
"psci-conduit", &error_abort);
74
if (i) {
75
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
76
object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
77
&error_abort);
78
object_property_set_bool(obj, true, "realized", &error_fatal);
79
- s->fpd.apu.cpu[i] = ARM_CPU(obj);
80
}
19
}
81
}
20
}
82
21
83
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
22
-static bool trans_SQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
84
}
23
-{
85
24
- static gen_helper_gvec_3 * const fns[4] = {
86
for (i = 0; i < nr_apu_cpus; i++) {
25
- gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h,
87
- DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);
26
- gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d,
88
+ DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]);
27
- };
89
int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
28
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
90
qemu_irq maint_irq;
29
- return false;
91
int ti;
30
- }
31
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
32
-}
33
+static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = {
34
+ gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h,
35
+ gen_helper_sve2_sqshl_zpzi_s, gen_helper_sve2_sqshl_zpzi_d,
36
+};
37
+TRANS_FEAT(SQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi,
38
+ a->esz < 0 ? NULL : sqshl_zpzi_fns[a->esz], a)
39
40
-static bool trans_UQSHL_zpzi(DisasContext *s, arg_rpri_esz *a)
41
-{
42
- static gen_helper_gvec_3 * const fns[4] = {
43
- gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h,
44
- gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d,
45
- };
46
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
47
- return false;
48
- }
49
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
50
-}
51
+static gen_helper_gvec_3 * const uqshl_zpzi_fns[4] = {
52
+ gen_helper_sve2_uqshl_zpzi_b, gen_helper_sve2_uqshl_zpzi_h,
53
+ gen_helper_sve2_uqshl_zpzi_s, gen_helper_sve2_uqshl_zpzi_d,
54
+};
55
+TRANS_FEAT(UQSHL_zpzi, aa64_sve2, gen_gvec_ool_arg_zpzi,
56
+ a->esz < 0 ? NULL : uqshl_zpzi_fns[a->esz], a)
57
58
-static bool trans_SRSHR(DisasContext *s, arg_rpri_esz *a)
59
-{
60
- static gen_helper_gvec_3 * const fns[4] = {
61
- gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h,
62
- gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d,
63
- };
64
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
65
- return false;
66
- }
67
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
68
-}
69
+static gen_helper_gvec_3 * const srshr_fns[4] = {
70
+ gen_helper_sve2_srshr_b, gen_helper_sve2_srshr_h,
71
+ gen_helper_sve2_srshr_s, gen_helper_sve2_srshr_d,
72
+};
73
+TRANS_FEAT(SRSHR, aa64_sve2, gen_gvec_ool_arg_zpzi,
74
+ a->esz < 0 ? NULL : srshr_fns[a->esz], a)
75
76
-static bool trans_URSHR(DisasContext *s, arg_rpri_esz *a)
77
-{
78
- static gen_helper_gvec_3 * const fns[4] = {
79
- gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h,
80
- gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d,
81
- };
82
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
83
- return false;
84
- }
85
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
86
-}
87
+static gen_helper_gvec_3 * const urshr_fns[4] = {
88
+ gen_helper_sve2_urshr_b, gen_helper_sve2_urshr_h,
89
+ gen_helper_sve2_urshr_s, gen_helper_sve2_urshr_d,
90
+};
91
+TRANS_FEAT(URSHR, aa64_sve2, gen_gvec_ool_arg_zpzi,
92
+ a->esz < 0 ? NULL : urshr_fns[a->esz], a)
93
94
-static bool trans_SQSHLU(DisasContext *s, arg_rpri_esz *a)
95
-{
96
- static gen_helper_gvec_3 * const fns[4] = {
97
- gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h,
98
- gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d,
99
- };
100
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
101
- return false;
102
- }
103
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
104
-}
105
+static gen_helper_gvec_3 * const sqshlu_fns[4] = {
106
+ gen_helper_sve2_sqshlu_b, gen_helper_sve2_sqshlu_h,
107
+ gen_helper_sve2_sqshlu_s, gen_helper_sve2_sqshlu_d,
108
+};
109
+TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi,
110
+ a->esz < 0 ? NULL : sqshlu_fns[a->esz], a)
111
112
/*
113
*** SVE Bitwise Shift - Predicated Group
92
--
114
--
93
2.20.1
115
2.25.1
94
95
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-26-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 42 ++++++++++++++++----------------------
9
1 file changed, 18 insertions(+), 24 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn,
16
}
17
18
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
19
-static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
20
+static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
21
int rd, int rn, int rm, int pg, int data)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm),
27
- pred_full_reg_offset(s, pg),
28
- vsz, vsz, data, fn);
29
+ if (fn == NULL) {
30
+ return false;
31
+ }
32
+ if (sve_access_check(s)) {
33
+ unsigned vsz = vec_full_reg_size(s);
34
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
35
+ vec_full_reg_offset(s, rn),
36
+ vec_full_reg_offset(s, rm),
37
+ pred_full_reg_offset(s, pg),
38
+ vsz, vsz, data, fn);
39
+ }
40
+ return true;
41
}
42
43
/* Invoke a vector expander on two Zregs. */
44
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
45
46
static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
47
{
48
- if (fn == NULL) {
49
- return false;
50
- }
51
- if (sve_access_check(s)) {
52
- gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
53
- }
54
- return true;
55
+ return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
56
}
57
58
/* Select active elememnts from Zn and inactive elements from Zm,
59
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
60
61
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
62
{
63
- if (sve_access_check(s)) {
64
- gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
65
- a->rd, a->rn, a->rm, a->pg, a->esz);
66
- }
67
- return true;
68
+ return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
69
+ a->rd, a->rn, a->rm, a->pg, a->esz);
70
}
71
72
static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
73
@@ -XXX,XX +XXX,XX @@ static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
74
if (!dc_isar_feature(aa64_sve2, s)) {
75
return false;
76
}
77
- if (sve_access_check(s)) {
78
- gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
79
- a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
80
- }
81
- return true;
82
+ return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
83
+ a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
84
}
85
86
/*
87
--
88
2.25.1
diff view generated by jsdifflib
1
The ARMv8.2-TTS2UXN feature extends the XN field in stage 2
1
From: Richard Henderson <richard.henderson@linaro.org>
2
translation table descriptors from just bit [54] to bits [54:53],
3
allowing stage 2 to control execution permissions separately for EL0
4
and EL1. Implement the new semantics of the XN field and enable
5
the feature for our 'max' CPU.
6
2
3
Use gen_gvec_ool_arg_zpzz instead of gen_gvec_ool_zzzp
4
when the arguments come from arg_rprr_esz.
5
Replaces do_zpzz_ool.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-27-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200330210400.11724-5-peter.maydell@linaro.org
11
---
11
---
12
target/arm/cpu.h | 15 +++++++++++++++
12
target/arm/translate-sve.c | 21 +++++++++++----------
13
target/arm/cpu.c | 1 +
13
1 file changed, 11 insertions(+), 10 deletions(-)
14
target/arm/cpu64.c | 2 ++
15
target/arm/helper.c | 37 +++++++++++++++++++++++++++++++------
16
4 files changed, 49 insertions(+), 6 deletions(-)
17
14
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
19
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
17
--- a/target/arm/translate-sve.c
21
+++ b/target/arm/cpu.h
18
+++ b/target/arm/translate-sve.c
22
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
23
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
20
return true;
24
}
21
}
25
22
26
+static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
23
+static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
24
+ arg_rprr_esz *a, int data)
27
+{
25
+{
28
+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
26
+ return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data);
29
+}
27
+}
30
+
28
+
31
/*
29
/* Invoke a vector expander on two Zregs. */
32
* 64-bit feature tests via id registers.
30
static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
31
int esz, int rd, int rn)
32
@@ -XXX,XX +XXX,XX @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
33
*** SVE Integer Arithmetic - Binary Predicated Group
33
*/
34
*/
34
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
35
35
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
36
-static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4 *fn)
37
-{
38
- return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
39
-}
40
-
41
/* Select active elememnts from Zn and inactive elements from Zm,
42
* storing the result in Zd.
43
*/
44
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a) \
45
gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \
46
gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \
47
}; \
48
- return do_zpzz_ool(s, a, fns[a->esz]); \
49
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
36
}
50
}
37
51
38
+static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
52
DO_ZPZZ(AND, and)
39
+{
53
@@ -XXX,XX +XXX,XX @@ static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
40
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
54
static gen_helper_gvec_4 * const fns[4] = {
41
+}
55
NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
42
+
56
};
43
/*
57
- return do_zpzz_ool(s, a, fns[a->esz]);
44
* Feature tests for "does this exist in either 32-bit or 64-bit?"
58
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
45
*/
46
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
47
return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
48
}
59
}
49
60
50
+static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
61
static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
51
+{
62
@@ -XXX,XX +XXX,XX @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
52
+ return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
63
static gen_helper_gvec_4 * const fns[4] = {
53
+}
64
NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
54
+
65
};
55
/*
66
- return do_zpzz_ool(s, a, fns[a->esz]);
56
* Forward to the above feature tests given an ARMCPU pointer.
67
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
57
*/
68
}
58
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
69
59
index XXXXXXX..XXXXXXX 100644
70
static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
60
--- a/target/arm/cpu.c
71
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a) \
61
+++ b/target/arm/cpu.c
72
if (a->esz < 0 || a->esz >= 3) { \
62
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
73
return false; \
63
t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
74
} \
64
t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
75
- return do_zpzz_ool(s, a, fns[a->esz]); \
65
t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
76
+ return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
66
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
77
}
67
cpu->isar.id_mmfr4 = t;
78
68
}
79
DO_ZPZW(ASR, asr)
69
#endif
80
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zpzz_ool(DisasContext *s, arg_rprr_esz *a,
70
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
81
if (!dc_isar_feature(aa64_sve2, s)) {
71
index XXXXXXX..XXXXXXX 100644
82
return false;
72
--- a/target/arm/cpu64.c
73
+++ b/target/arm/cpu64.c
74
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
75
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
76
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
77
t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
78
+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
79
cpu->isar.id_aa64mmfr1 = t;
80
81
t = cpu->isar.id_aa64mmfr2;
82
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
83
u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
84
u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
85
u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
86
+ u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
87
cpu->isar.id_mmfr4 = u;
88
89
u = cpu->isar.id_aa64dfr0;
90
diff --git a/target/arm/helper.c b/target/arm/helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/helper.c
93
+++ b/target/arm/helper.c
94
@@ -XXX,XX +XXX,XX @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
95
*
96
* @env: CPUARMState
97
* @s2ap: The 2-bit stage2 access permissions (S2AP)
98
- * @xn: XN (execute-never) bit
99
+ * @xn: XN (execute-never) bits
100
+ * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
101
*/
102
-static int get_S2prot(CPUARMState *env, int s2ap, int xn)
103
+static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
104
{
105
int prot = 0;
106
107
@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn)
108
if (s2ap & 2) {
109
prot |= PAGE_WRITE;
110
}
83
}
111
- if (!xn) {
84
- return do_zpzz_ool(s, a, fn);
112
- if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
85
+ return gen_gvec_ool_arg_zpzz(s, fn, a, 0);
113
+
86
}
114
+ if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {
87
115
+ switch (xn) {
88
static bool trans_SADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
116
+ case 0:
117
prot |= PAGE_EXEC;
118
+ break;
119
+ case 1:
120
+ if (s1_is_el0) {
121
+ prot |= PAGE_EXEC;
122
+ }
123
+ break;
124
+ case 2:
125
+ break;
126
+ case 3:
127
+ if (!s1_is_el0) {
128
+ prot |= PAGE_EXEC;
129
+ }
130
+ break;
131
+ default:
132
+ g_assert_not_reached();
133
+ }
134
+ } else {
135
+ if (!extract32(xn, 1, 1)) {
136
+ if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
137
+ prot |= PAGE_EXEC;
138
+ }
139
}
140
}
141
return prot;
142
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
143
}
144
145
ap = extract32(attrs, 4, 2);
146
- xn = extract32(attrs, 12, 1);
147
148
if (mmu_idx == ARMMMUIdx_Stage2) {
149
ns = true;
150
- *prot = get_S2prot(env, ap, xn);
151
+ xn = extract32(attrs, 11, 2);
152
+ *prot = get_S2prot(env, ap, xn, s1_is_el0);
153
} else {
154
ns = extract32(attrs, 3, 1);
155
+ xn = extract32(attrs, 12, 1);
156
pxn = extract32(attrs, 11, 1);
157
*prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
158
}
159
--
89
--
160
2.20.1
90
2.25.1
161
162
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_ool_arg_zpzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-28-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 85 ++++++++++++++++----------------------
12
1 file changed, 36 insertions(+), 49 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
19
gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
20
}
21
22
-#define DO_ZPZZ(NAME, name) \
23
-static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a) \
24
-{ \
25
- static gen_helper_gvec_4 * const fns[4] = { \
26
- gen_helper_sve_##name##_zpzz_b, gen_helper_sve_##name##_zpzz_h, \
27
- gen_helper_sve_##name##_zpzz_s, gen_helper_sve_##name##_zpzz_d, \
28
+#define DO_ZPZZ(NAME, FEAT, name) \
29
+ static gen_helper_gvec_4 * const name##_zpzz_fns[4] = { \
30
+ gen_helper_##name##_zpzz_b, gen_helper_##name##_zpzz_h, \
31
+ gen_helper_##name##_zpzz_s, gen_helper_##name##_zpzz_d, \
32
}; \
33
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
34
-}
35
+ TRANS_FEAT(NAME, FEAT, gen_gvec_ool_arg_zpzz, \
36
+ name##_zpzz_fns[a->esz], a, 0)
37
38
-DO_ZPZZ(AND, and)
39
-DO_ZPZZ(EOR, eor)
40
-DO_ZPZZ(ORR, orr)
41
-DO_ZPZZ(BIC, bic)
42
+DO_ZPZZ(AND_zpzz, aa64_sve, sve_and)
43
+DO_ZPZZ(EOR_zpzz, aa64_sve, sve_eor)
44
+DO_ZPZZ(ORR_zpzz, aa64_sve, sve_orr)
45
+DO_ZPZZ(BIC_zpzz, aa64_sve, sve_bic)
46
47
-DO_ZPZZ(ADD, add)
48
-DO_ZPZZ(SUB, sub)
49
+DO_ZPZZ(ADD_zpzz, aa64_sve, sve_add)
50
+DO_ZPZZ(SUB_zpzz, aa64_sve, sve_sub)
51
52
-DO_ZPZZ(SMAX, smax)
53
-DO_ZPZZ(UMAX, umax)
54
-DO_ZPZZ(SMIN, smin)
55
-DO_ZPZZ(UMIN, umin)
56
-DO_ZPZZ(SABD, sabd)
57
-DO_ZPZZ(UABD, uabd)
58
+DO_ZPZZ(SMAX_zpzz, aa64_sve, sve_smax)
59
+DO_ZPZZ(UMAX_zpzz, aa64_sve, sve_umax)
60
+DO_ZPZZ(SMIN_zpzz, aa64_sve, sve_smin)
61
+DO_ZPZZ(UMIN_zpzz, aa64_sve, sve_umin)
62
+DO_ZPZZ(SABD_zpzz, aa64_sve, sve_sabd)
63
+DO_ZPZZ(UABD_zpzz, aa64_sve, sve_uabd)
64
65
-DO_ZPZZ(MUL, mul)
66
-DO_ZPZZ(SMULH, smulh)
67
-DO_ZPZZ(UMULH, umulh)
68
+DO_ZPZZ(MUL_zpzz, aa64_sve, sve_mul)
69
+DO_ZPZZ(SMULH_zpzz, aa64_sve, sve_smulh)
70
+DO_ZPZZ(UMULH_zpzz, aa64_sve, sve_umulh)
71
72
-DO_ZPZZ(ASR, asr)
73
-DO_ZPZZ(LSR, lsr)
74
-DO_ZPZZ(LSL, lsl)
75
+DO_ZPZZ(ASR_zpzz, aa64_sve, sve_asr)
76
+DO_ZPZZ(LSR_zpzz, aa64_sve, sve_lsr)
77
+DO_ZPZZ(LSL_zpzz, aa64_sve, sve_lsl)
78
79
-static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
80
-{
81
- static gen_helper_gvec_4 * const fns[4] = {
82
- NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
83
- };
84
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
85
-}
86
+static gen_helper_gvec_4 * const sdiv_fns[4] = {
87
+ NULL, NULL, gen_helper_sve_sdiv_zpzz_s, gen_helper_sve_sdiv_zpzz_d
88
+};
89
+TRANS_FEAT(SDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, sdiv_fns[a->esz], a, 0)
90
91
-static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a)
92
-{
93
- static gen_helper_gvec_4 * const fns[4] = {
94
- NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
95
- };
96
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0);
97
-}
98
+static gen_helper_gvec_4 * const udiv_fns[4] = {
99
+ NULL, NULL, gen_helper_sve_udiv_zpzz_s, gen_helper_sve_udiv_zpzz_d
100
+};
101
+TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0)
102
103
static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
104
{
105
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SQSHLU, aa64_sve2, gen_gvec_ool_arg_zpzi,
106
*/
107
108
#define DO_ZPZW(NAME, name) \
109
-static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a) \
110
-{ \
111
- static gen_helper_gvec_4 * const fns[3] = { \
112
+ static gen_helper_gvec_4 * const name##_zpzw_fns[4] = { \
113
gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \
114
- gen_helper_sve_##name##_zpzw_s, \
115
+ gen_helper_sve_##name##_zpzw_s, NULL \
116
}; \
117
- if (a->esz < 0 || a->esz >= 3) { \
118
- return false; \
119
- } \
120
- return gen_gvec_ool_arg_zpzz(s, fns[a->esz], a, 0); \
121
-}
122
+ TRANS_FEAT(NAME##_zpzw, aa64_sve, gen_gvec_ool_arg_zpzz, \
123
+ a->esz < 0 ? NULL : name##_zpzw_fns[a->esz], a, 0)
124
125
DO_ZPZW(ASR, asr)
126
DO_ZPZW(LSR, lsr)
127
--
128
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zpzz_ool
4
to use TRANS_FEAT and gen_gvec_ool_arg_zpzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-29-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 118 +++++++++++++------------------------
12
1 file changed, 40 insertions(+), 78 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
19
return true;
20
}
21
22
-#undef DO_ZPZZ
23
-
24
/*
25
*** SVE Integer Arithmetic - Unary Predicated Group
26
*/
27
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SQRDMULH_zzz, aa64_sve2, gen_gvec_ool_arg_zzz,
28
* SVE2 Integer - Predicated
29
*/
30
31
-static bool do_sve2_zpzz_ool(DisasContext *s, arg_rprr_esz *a,
32
- gen_helper_gvec_4 *fn)
33
-{
34
- if (!dc_isar_feature(aa64_sve2, s)) {
35
- return false;
36
- }
37
- return gen_gvec_ool_arg_zpzz(s, fn, a, 0);
38
-}
39
+static gen_helper_gvec_4 * const sadlp_fns[4] = {
40
+ NULL, gen_helper_sve2_sadalp_zpzz_h,
41
+ gen_helper_sve2_sadalp_zpzz_s, gen_helper_sve2_sadalp_zpzz_d,
42
+};
43
+TRANS_FEAT(SADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz,
44
+ sadlp_fns[a->esz], a, 0)
45
46
-static bool trans_SADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
47
-{
48
- static gen_helper_gvec_4 * const fns[3] = {
49
- gen_helper_sve2_sadalp_zpzz_h,
50
- gen_helper_sve2_sadalp_zpzz_s,
51
- gen_helper_sve2_sadalp_zpzz_d,
52
- };
53
- if (a->esz == 0) {
54
- return false;
55
- }
56
- return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]);
57
-}
58
-
59
-static bool trans_UADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
60
-{
61
- static gen_helper_gvec_4 * const fns[3] = {
62
- gen_helper_sve2_uadalp_zpzz_h,
63
- gen_helper_sve2_uadalp_zpzz_s,
64
- gen_helper_sve2_uadalp_zpzz_d,
65
- };
66
- if (a->esz == 0) {
67
- return false;
68
- }
69
- return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]);
70
-}
71
+static gen_helper_gvec_4 * const uadlp_fns[4] = {
72
+ NULL, gen_helper_sve2_uadalp_zpzz_h,
73
+ gen_helper_sve2_uadalp_zpzz_s, gen_helper_sve2_uadalp_zpzz_d,
74
+};
75
+TRANS_FEAT(UADALP_zpzz, aa64_sve2, gen_gvec_ool_arg_zpzz,
76
+ uadlp_fns[a->esz], a, 0)
77
78
/*
79
* SVE2 integer unary operations (predicated)
80
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3 * const sqneg_fns[4] = {
81
};
82
TRANS_FEAT(SQNEG, aa64_sve2, gen_gvec_ool_arg_zpz, sqneg_fns[a->esz], a, 0)
83
84
-#define DO_SVE2_ZPZZ(NAME, name) \
85
-static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
86
-{ \
87
- static gen_helper_gvec_4 * const fns[4] = { \
88
- gen_helper_sve2_##name##_zpzz_b, gen_helper_sve2_##name##_zpzz_h, \
89
- gen_helper_sve2_##name##_zpzz_s, gen_helper_sve2_##name##_zpzz_d, \
90
- }; \
91
- return do_sve2_zpzz_ool(s, a, fns[a->esz]); \
92
-}
93
+DO_ZPZZ(SQSHL, aa64_sve2, sve2_sqshl)
94
+DO_ZPZZ(SQRSHL, aa64_sve2, sve2_sqrshl)
95
+DO_ZPZZ(SRSHL, aa64_sve2, sve2_srshl)
96
97
-DO_SVE2_ZPZZ(SQSHL, sqshl)
98
-DO_SVE2_ZPZZ(SQRSHL, sqrshl)
99
-DO_SVE2_ZPZZ(SRSHL, srshl)
100
+DO_ZPZZ(UQSHL, aa64_sve2, sve2_uqshl)
101
+DO_ZPZZ(UQRSHL, aa64_sve2, sve2_uqrshl)
102
+DO_ZPZZ(URSHL, aa64_sve2, sve2_urshl)
103
104
-DO_SVE2_ZPZZ(UQSHL, uqshl)
105
-DO_SVE2_ZPZZ(UQRSHL, uqrshl)
106
-DO_SVE2_ZPZZ(URSHL, urshl)
107
+DO_ZPZZ(SHADD, aa64_sve2, sve2_shadd)
108
+DO_ZPZZ(SRHADD, aa64_sve2, sve2_srhadd)
109
+DO_ZPZZ(SHSUB, aa64_sve2, sve2_shsub)
110
111
-DO_SVE2_ZPZZ(SHADD, shadd)
112
-DO_SVE2_ZPZZ(SRHADD, srhadd)
113
-DO_SVE2_ZPZZ(SHSUB, shsub)
114
+DO_ZPZZ(UHADD, aa64_sve2, sve2_uhadd)
115
+DO_ZPZZ(URHADD, aa64_sve2, sve2_urhadd)
116
+DO_ZPZZ(UHSUB, aa64_sve2, sve2_uhsub)
117
118
-DO_SVE2_ZPZZ(UHADD, uhadd)
119
-DO_SVE2_ZPZZ(URHADD, urhadd)
120
-DO_SVE2_ZPZZ(UHSUB, uhsub)
121
+DO_ZPZZ(ADDP, aa64_sve2, sve2_addp)
122
+DO_ZPZZ(SMAXP, aa64_sve2, sve2_smaxp)
123
+DO_ZPZZ(UMAXP, aa64_sve2, sve2_umaxp)
124
+DO_ZPZZ(SMINP, aa64_sve2, sve2_sminp)
125
+DO_ZPZZ(UMINP, aa64_sve2, sve2_uminp)
126
127
-DO_SVE2_ZPZZ(ADDP, addp)
128
-DO_SVE2_ZPZZ(SMAXP, smaxp)
129
-DO_SVE2_ZPZZ(UMAXP, umaxp)
130
-DO_SVE2_ZPZZ(SMINP, sminp)
131
-DO_SVE2_ZPZZ(UMINP, uminp)
132
-
133
-DO_SVE2_ZPZZ(SQADD_zpzz, sqadd)
134
-DO_SVE2_ZPZZ(UQADD_zpzz, uqadd)
135
-DO_SVE2_ZPZZ(SQSUB_zpzz, sqsub)
136
-DO_SVE2_ZPZZ(UQSUB_zpzz, uqsub)
137
-DO_SVE2_ZPZZ(SUQADD, suqadd)
138
-DO_SVE2_ZPZZ(USQADD, usqadd)
139
+DO_ZPZZ(SQADD_zpzz, aa64_sve2, sve2_sqadd)
140
+DO_ZPZZ(UQADD_zpzz, aa64_sve2, sve2_uqadd)
141
+DO_ZPZZ(SQSUB_zpzz, aa64_sve2, sve2_sqsub)
142
+DO_ZPZZ(UQSUB_zpzz, aa64_sve2, sve2_uqsub)
143
+DO_ZPZZ(SUQADD, aa64_sve2, sve2_suqadd)
144
+DO_ZPZZ(USQADD, aa64_sve2, sve2_usqadd)
145
146
/*
147
* SVE2 Widening Integer Arithmetic
148
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
149
DO_SVE2_PPZZ_MATCH(MATCH, match)
150
DO_SVE2_PPZZ_MATCH(NMATCH, nmatch)
151
152
-static bool trans_HISTCNT(DisasContext *s, arg_rprr_esz *a)
153
-{
154
- static gen_helper_gvec_4 * const fns[2] = {
155
- gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
156
- };
157
- if (a->esz < 2) {
158
- return false;
159
- }
160
- return do_sve2_zpzz_ool(s, a, fns[a->esz - 2]);
161
-}
162
+static gen_helper_gvec_4 * const histcnt_fns[4] = {
163
+ NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
164
+};
165
+TRANS_FEAT(HISTCNT, aa64_sve2, gen_gvec_ool_arg_zpzz,
166
+ histcnt_fns[a->esz], a, 0)
167
168
TRANS_FEAT(HISTSEG, aa64_sve2, gen_gvec_ool_arg_zzz,
169
a->esz == 0 ? gen_helper_sve2_histseg : NULL, a, 0)
170
--
171
2.25.1
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Embed the ADMAs into the SoC type.
3
There is only one caller for gen_gvec_fn_zz; inline it.
4
4
5
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Message-id: 20220527181907.189259-30-richard.henderson@linaro.org
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
10
Message-id: 20200427181649.26851-7-edgar.iglesias@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
include/hw/arm/xlnx-versal.h | 3 ++-
10
target/arm/translate-sve.c | 13 +++----------
14
hw/arm/xlnx-versal.c | 14 +++++++-------
11
1 file changed, 3 insertions(+), 10 deletions(-)
15
2 files changed, 9 insertions(+), 8 deletions(-)
16
12
17
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
18
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/xlnx-versal.h
15
--- a/target/arm/translate-sve.c
20
+++ b/include/hw/arm/xlnx-versal.h
16
+++ b/target/arm/translate-sve.c
21
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
22
#include "hw/arm/boot.h"
18
return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data);
23
#include "hw/intc/arm_gicv3.h"
19
}
24
#include "hw/char/pl011.h"
20
25
+#include "hw/dma/xlnx-zdma.h"
21
-/* Invoke a vector expander on two Zregs. */
26
#include "hw/net/cadence_gem.h"
22
-static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
27
23
- int esz, int rd, int rn)
28
#define TYPE_XLNX_VERSAL "xlnx-versal"
24
-{
29
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
25
- unsigned vsz = vec_full_reg_size(s);
30
struct {
26
- gvec_fn(esz, vec_full_reg_offset(s, rd),
31
PL011State uart[XLNX_VERSAL_NR_UARTS];
27
- vec_full_reg_offset(s, rn), vsz, vsz);
32
CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
28
-}
33
- SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
29
-
34
+ XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
30
/* Invoke a vector expander on three Zregs. */
35
} iou;
31
static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
36
} lpd;
32
int esz, int rd, int rn, int rm)
37
33
@@ -XXX,XX +XXX,XX @@ static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
38
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
34
static bool do_mov_z(DisasContext *s, int rd, int rn)
39
index XXXXXXX..XXXXXXX 100644
35
{
40
--- a/hw/arm/xlnx-versal.c
36
if (sve_access_check(s)) {
41
+++ b/hw/arm/xlnx-versal.c
37
- gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
42
@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
38
+ unsigned vsz = vec_full_reg_size(s);
43
DeviceState *dev;
39
+ tcg_gen_gvec_mov(MO_8, vec_full_reg_offset(s, rd),
44
MemoryRegion *mr;
40
+ vec_full_reg_offset(s, rn), vsz, vsz);
45
46
- dev = qdev_create(NULL, "xlnx.zdma");
47
- s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev);
48
- object_property_set_int(OBJECT(s->lpd.iou.adma[i]), 128, "bus-width",
49
- &error_abort);
50
- object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
51
+ sysbus_init_child_obj(OBJECT(s), name,
52
+ &s->lpd.iou.adma[i], sizeof(s->lpd.iou.adma[i]),
53
+ TYPE_XLNX_ZDMA);
54
+ dev = DEVICE(&s->lpd.iou.adma[i]);
55
+ object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort);
56
qdev_init_nofail(dev);
57
58
- mr = sysbus_mmio_get_region(s->lpd.iou.adma[i], 0);
59
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
60
memory_region_add_subregion(&s->mr_ps,
61
MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
62
63
- sysbus_connect_irq(s->lpd.iou.adma[i], 0, pic[VERSAL_ADMA_IRQ_0 + i]);
64
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]);
65
g_free(name);
66
}
41
}
42
return true;
67
}
43
}
68
--
44
--
69
2.20.1
45
2.25.1
70
71
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-31-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 36 +++++++++++++++---------------------
9
1 file changed, 15 insertions(+), 21 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
16
}
17
18
/* Invoke a vector expander on three Zregs. */
19
-static void gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
20
+static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
21
int esz, int rd, int rn, int rm)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- gvec_fn(esz, vec_full_reg_offset(s, rd),
25
- vec_full_reg_offset(s, rn),
26
- vec_full_reg_offset(s, rm), vsz, vsz);
27
+ if (gvec_fn == NULL) {
28
+ return false;
29
+ }
30
+ if (sve_access_check(s)) {
31
+ unsigned vsz = vec_full_reg_size(s);
32
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
33
+ vec_full_reg_offset(s, rn),
34
+ vec_full_reg_offset(s, rm), vsz, vsz);
35
+ }
36
+ return true;
37
}
38
39
/* Invoke a vector expander on four Zregs. */
40
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
41
42
static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
43
{
44
- if (sve_access_check(s)) {
45
- gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
46
- }
47
- return true;
48
+ return gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
49
}
50
51
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
52
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
53
if (!dc_isar_feature(aa64_sve2, s)) {
54
return false;
55
}
56
- if (sve_access_check(s)) {
57
- gen_gvec_fn_zzz(s, tcg_gen_gvec_mul, a->esz, a->rd, a->rn, a->rm);
58
- }
59
- return true;
60
+ return gen_gvec_fn_zzz(s, tcg_gen_gvec_mul, a->esz, a->rd, a->rn, a->rm);
61
}
62
63
static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
64
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_fn_zzz(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn)
65
if (!dc_isar_feature(aa64_sve2, s)) {
66
return false;
67
}
68
- if (sve_access_check(s)) {
69
- gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
70
- }
71
- return true;
72
+ return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
73
}
74
75
static bool trans_SABA(DisasContext *s, arg_rrr_esz *a)
76
@@ -XXX,XX +XXX,XX @@ static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
77
if (!dc_isar_feature(aa64_sve2_sha3, s)) {
78
return false;
79
}
80
- if (sve_access_check(s)) {
81
- gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm);
82
- }
83
- return true;
84
+ return gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm);
85
}
86
87
static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
88
--
89
2.25.1
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Add support for SD.
3
Rename the function to match gen_gvec_fn_zzz,
4
and move to be adjacent.
4
5
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20220527181907.189259-32-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20200427181649.26851-9-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
include/hw/arm/xlnx-versal.h | 12 ++++++++++++
11
target/arm/translate-sve.c | 31 ++++++++++++++++---------------
13
hw/arm/xlnx-versal.c | 31 +++++++++++++++++++++++++++++++
12
1 file changed, 16 insertions(+), 15 deletions(-)
14
2 files changed, 43 insertions(+)
15
13
16
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-versal.h
16
--- a/target/arm/translate-sve.c
19
+++ b/include/hw/arm/xlnx-versal.h
17
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
21
19
return true;
22
#include "hw/sysbus.h"
23
#include "hw/arm/boot.h"
24
+#include "hw/sd/sdhci.h"
25
#include "hw/intc/arm_gicv3.h"
26
#include "hw/char/pl011.h"
27
#include "hw/dma/xlnx-zdma.h"
28
@@ -XXX,XX +XXX,XX @@
29
#define XLNX_VERSAL_NR_UARTS 2
30
#define XLNX_VERSAL_NR_GEMS 2
31
#define XLNX_VERSAL_NR_ADMAS 8
32
+#define XLNX_VERSAL_NR_SDS 2
33
#define XLNX_VERSAL_NR_IRQS 192
34
35
typedef struct Versal {
36
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
37
} iou;
38
} lpd;
39
40
+ /* The Platform Management Controller subsystem. */
41
+ struct {
42
+ struct {
43
+ SDHCIState sd[XLNX_VERSAL_NR_SDS];
44
+ } iou;
45
+ } pmc;
46
+
47
struct {
48
MemoryRegion *mr_ddr;
49
uint32_t psci_conduit;
50
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
51
#define VERSAL_GEM1_IRQ_0 58
52
#define VERSAL_GEM1_WAKE_IRQ_0 59
53
#define VERSAL_ADMA_IRQ_0 60
54
+#define VERSAL_SD0_IRQ_0 126
55
56
/* Architecturally reserved IRQs suitable for virtualization. */
57
#define VERSAL_RSVD_IRQ_FIRST 111
58
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
59
#define MM_FPD_CRF 0xfd1a0000U
60
#define MM_FPD_CRF_SIZE 0x140000
61
62
+#define MM_PMC_SD0 0xf1040000U
63
+#define MM_PMC_SD0_SIZE 0x10000
64
#define MM_PMC_CRP 0xf1260000U
65
#define MM_PMC_CRP_SIZE 0x10000
66
#endif
67
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/hw/arm/xlnx-versal.c
70
+++ b/hw/arm/xlnx-versal.c
71
@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
72
}
73
}
20
}
74
21
75
+#define SDHCI_CAPABILITIES 0x280737ec6481 /* Same as on ZynqMP. */
22
+static bool gen_gvec_fn_arg_zzz(DisasContext *s, GVecGen3Fn *fn,
76
+static void versal_create_sds(Versal *s, qemu_irq *pic)
23
+ arg_rrr_esz *a)
77
+{
24
+{
78
+ int i;
25
+ return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
79
+
80
+ for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) {
81
+ DeviceState *dev;
82
+ MemoryRegion *mr;
83
+
84
+ sysbus_init_child_obj(OBJECT(s), "sd[*]",
85
+ &s->pmc.iou.sd[i], sizeof(s->pmc.iou.sd[i]),
86
+ TYPE_SYSBUS_SDHCI);
87
+ dev = DEVICE(&s->pmc.iou.sd[i]);
88
+
89
+ object_property_set_uint(OBJECT(dev),
90
+ 3, "sd-spec-version", &error_fatal);
91
+ object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg",
92
+ &error_fatal);
93
+ object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal);
94
+ qdev_init_nofail(dev);
95
+
96
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
97
+ memory_region_add_subregion(&s->mr_ps,
98
+ MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr);
99
+
100
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
101
+ pic[VERSAL_SD0_IRQ_0 + i * 2]);
102
+ }
103
+}
26
+}
104
+
27
+
105
/* This takes the board allocated linear DDR memory and creates aliases
28
/* Invoke a vector expander on four Zregs. */
106
* for each split DDR range/aperture on the Versal address map.
29
static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
30
int esz, int rd, int rn, int rm, int ra)
31
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
32
*** SVE Logical - Unpredicated Group
107
*/
33
*/
108
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
34
109
versal_create_uarts(s, pic);
35
-static bool do_zzz_fn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *gvec_fn)
110
versal_create_gems(s, pic);
36
-{
111
versal_create_admas(s, pic);
37
- return gen_gvec_fn_zzz(s, gvec_fn, a->esz, a->rd, a->rn, a->rm);
112
+ versal_create_sds(s, pic);
38
-}
113
versal_map_ddr(s);
39
-
114
versal_unimp(s);
40
static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
115
41
{
42
- return do_zzz_fn(s, a, tcg_gen_gvec_and);
43
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_and, a);
44
}
45
46
static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
47
{
48
- return do_zzz_fn(s, a, tcg_gen_gvec_or);
49
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_or, a);
50
}
51
52
static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
53
{
54
- return do_zzz_fn(s, a, tcg_gen_gvec_xor);
55
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_xor, a);
56
}
57
58
static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
59
{
60
- return do_zzz_fn(s, a, tcg_gen_gvec_andc);
61
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_andc, a);
62
}
63
64
static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh)
65
@@ -XXX,XX +XXX,XX @@ static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
66
67
static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
68
{
69
- return do_zzz_fn(s, a, tcg_gen_gvec_add);
70
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_add, a);
71
}
72
73
static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
74
{
75
- return do_zzz_fn(s, a, tcg_gen_gvec_sub);
76
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sub, a);
77
}
78
79
static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
80
{
81
- return do_zzz_fn(s, a, tcg_gen_gvec_ssadd);
82
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ssadd, a);
83
}
84
85
static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
86
{
87
- return do_zzz_fn(s, a, tcg_gen_gvec_sssub);
88
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sssub, a);
89
}
90
91
static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
92
{
93
- return do_zzz_fn(s, a, tcg_gen_gvec_usadd);
94
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_usadd, a);
95
}
96
97
static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
98
{
99
- return do_zzz_fn(s, a, tcg_gen_gvec_ussub);
100
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ussub, a);
101
}
102
103
/*
116
--
104
--
117
2.20.1
105
2.25.1
118
119
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Two uses of gen_gvec_fn_zzz can pass on arg_rrr_esz instead.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-33-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
18
if (!dc_isar_feature(aa64_sve2, s)) {
19
return false;
20
}
21
- return gen_gvec_fn_zzz(s, tcg_gen_gvec_mul, a->esz, a->rd, a->rn, a->rm);
22
+ return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_mul, a);
23
}
24
25
static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
26
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_fn_zzz(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn)
27
if (!dc_isar_feature(aa64_sve2, s)) {
28
return false;
29
}
30
- return gen_gvec_fn_zzz(s, fn, a->esz, a->rd, a->rn, a->rm);
31
+ return gen_gvec_fn_arg_zzz(s, fn, a);
32
}
33
34
static bool trans_SABA(DisasContext *s, arg_rrr_esz *a)
35
--
36
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions directly using
4
gen_gvec_fn_arg_zzz to TRANS_FEAT.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-34-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 66 +++++++-------------------------------
12
1 file changed, 11 insertions(+), 55 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
19
*** SVE Logical - Unpredicated Group
20
*/
21
22
-static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
23
-{
24
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_and, a);
25
-}
26
-
27
-static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
28
-{
29
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_or, a);
30
-}
31
-
32
-static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
33
-{
34
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_xor, a);
35
-}
36
-
37
-static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a)
38
-{
39
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_andc, a);
40
-}
41
+TRANS_FEAT(AND_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_and, a)
42
+TRANS_FEAT(ORR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_or, a)
43
+TRANS_FEAT(EOR_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_xor, a)
44
+TRANS_FEAT(BIC_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_andc, a)
45
46
static void gen_xar8_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, int64_t sh)
47
{
48
@@ -XXX,XX +XXX,XX @@ static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
49
*** SVE Integer Arithmetic - Unpredicated Group
50
*/
51
52
-static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a)
53
-{
54
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_add, a);
55
-}
56
-
57
-static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a)
58
-{
59
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sub, a);
60
-}
61
-
62
-static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a)
63
-{
64
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ssadd, a);
65
-}
66
-
67
-static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
68
-{
69
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_sssub, a);
70
-}
71
-
72
-static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a)
73
-{
74
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_usadd, a);
75
-}
76
-
77
-static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a)
78
-{
79
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_ussub, a);
80
-}
81
+TRANS_FEAT(ADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_add, a)
82
+TRANS_FEAT(SUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sub, a)
83
+TRANS_FEAT(SQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ssadd, a)
84
+TRANS_FEAT(SQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_sssub, a)
85
+TRANS_FEAT(UQADD_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_usadd, a)
86
+TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a)
87
88
/*
89
*** SVE Integer Arithmetic - Binary Predicated Group
90
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
91
* SVE2 Integer Multiply - Unpredicated
92
*/
93
94
-static bool trans_MUL_zzz(DisasContext *s, arg_rrr_esz *a)
95
-{
96
- if (!dc_isar_feature(aa64_sve2, s)) {
97
- return false;
98
- }
99
- return gen_gvec_fn_arg_zzz(s, tcg_gen_gvec_mul, a);
100
-}
101
+TRANS_FEAT(MUL_zzz, aa64_sve2, gen_gvec_fn_arg_zzz, tcg_gen_gvec_mul, a)
102
103
static gen_helper_gvec_3 * const smulh_zzz_fns[4] = {
104
gen_helper_gvec_smulh_b, gen_helper_gvec_smulh_h,
105
--
106
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_fn_zzz
4
to use TRANS_FEAT and gen_gvec_fn_arg_zzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-35-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 19 ++-----------------
12
1 file changed, 2 insertions(+), 17 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_SLI(DisasContext *s, arg_rri_esz *a)
19
return do_sve2_fn2i(s, a, gen_gvec_sli);
20
}
21
22
-static bool do_sve2_fn_zzz(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn)
23
-{
24
- if (!dc_isar_feature(aa64_sve2, s)) {
25
- return false;
26
- }
27
- return gen_gvec_fn_arg_zzz(s, fn, a);
28
-}
29
-
30
-static bool trans_SABA(DisasContext *s, arg_rrr_esz *a)
31
-{
32
- return do_sve2_fn_zzz(s, a, gen_gvec_saba);
33
-}
34
-
35
-static bool trans_UABA(DisasContext *s, arg_rrr_esz *a)
36
-{
37
- return do_sve2_fn_zzz(s, a, gen_gvec_uaba);
38
-}
39
+TRANS_FEAT(SABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a)
40
+TRANS_FEAT(UABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a)
41
42
static bool do_sve2_narrow_extract(DisasContext *s, arg_rri_esz *a,
43
const GVecGen2 ops[3])
44
--
45
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The decode for RAX1 sets esz to MO_8, because that's what
4
we use by default for "no esz present". We changed that
5
to MO_64 during translation because it is more logical for
6
the operation. However, the esz argument to gen_gvec_rax1
7
is unused and forces MO_64 within that function, so there
8
is no need to do it here as well.
9
10
Simplify to use gen_gvec_fn_arg_zzz and TRANS_FEAT.
11
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20220527181907.189259-36-richard.henderson@linaro.org
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/translate-sve.c | 8 +-------
18
1 file changed, 1 insertion(+), 7 deletions(-)
19
20
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/translate-sve.c
23
+++ b/target/arm/translate-sve.c
24
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
25
TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
26
gen_helper_crypto_sm4ekey, a, 0)
27
28
-static bool trans_RAX1(DisasContext *s, arg_rrr_esz *a)
29
-{
30
- if (!dc_isar_feature(aa64_sve2_sha3, s)) {
31
- return false;
32
- }
33
- return gen_gvec_fn_zzz(s, gen_gvec_rax1, MO_64, a->rd, a->rn, a->rm);
34
-}
35
+TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a)
36
37
static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
38
{
39
--
40
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Merge gen_gvec_fn_zzzz with the sve access check and the
4
dereference of arg_rrrr_esz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-37-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 25 ++++++++++++++-----------
12
1 file changed, 14 insertions(+), 11 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_fn_arg_zzz(DisasContext *s, GVecGen3Fn *fn,
19
}
20
21
/* Invoke a vector expander on four Zregs. */
22
-static void gen_gvec_fn_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
23
- int esz, int rd, int rn, int rm, int ra)
24
+static bool gen_gvec_fn_arg_zzzz(DisasContext *s, GVecGen4Fn *gvec_fn,
25
+ arg_rrrr_esz *a)
26
{
27
- unsigned vsz = vec_full_reg_size(s);
28
- gvec_fn(esz, vec_full_reg_offset(s, rd),
29
- vec_full_reg_offset(s, rn),
30
- vec_full_reg_offset(s, rm),
31
- vec_full_reg_offset(s, ra), vsz, vsz);
32
+ if (gvec_fn == NULL) {
33
+ return false;
34
+ }
35
+ if (sve_access_check(s)) {
36
+ unsigned vsz = vec_full_reg_size(s);
37
+ gvec_fn(a->esz, vec_full_reg_offset(s, a->rd),
38
+ vec_full_reg_offset(s, a->rn),
39
+ vec_full_reg_offset(s, a->rm),
40
+ vec_full_reg_offset(s, a->ra), vsz, vsz);
41
+ }
42
+ return true;
43
}
44
45
/* Invoke a vector move on two Zregs. */
46
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_zzzz_fn(DisasContext *s, arg_rrrr_esz *a, GVecGen4Fn *fn)
47
if (!dc_isar_feature(aa64_sve2, s)) {
48
return false;
49
}
50
- if (sve_access_check(s)) {
51
- gen_gvec_fn_zzzz(s, fn, a->esz, a->rd, a->rn, a->rm, a->ra);
52
- }
53
- return true;
54
+ return gen_gvec_fn_arg_zzzz(s, fn, a);
55
}
56
57
static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
58
--
59
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_zzzz_fn
4
to use TRANS_FEAT and gen_gvec_fn_arg_zzzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-38-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 38 ++++++--------------------------------
12
1 file changed, 6 insertions(+), 32 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool trans_XAR(DisasContext *s, arg_rrri_esz *a)
19
return true;
20
}
21
22
-static bool do_sve2_zzzz_fn(DisasContext *s, arg_rrrr_esz *a, GVecGen4Fn *fn)
23
-{
24
- if (!dc_isar_feature(aa64_sve2, s)) {
25
- return false;
26
- }
27
- return gen_gvec_fn_arg_zzzz(s, fn, a);
28
-}
29
-
30
static void gen_eor3_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
31
{
32
tcg_gen_xor_i64(d, n, m);
33
@@ -XXX,XX +XXX,XX @@ static void gen_eor3(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
34
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
35
}
36
37
-static bool trans_EOR3(DisasContext *s, arg_rrrr_esz *a)
38
-{
39
- return do_sve2_zzzz_fn(s, a, gen_eor3);
40
-}
41
+TRANS_FEAT(EOR3, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_eor3, a)
42
43
static void gen_bcax_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
44
{
45
@@ -XXX,XX +XXX,XX @@ static void gen_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
46
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
47
}
48
49
-static bool trans_BCAX(DisasContext *s, arg_rrrr_esz *a)
50
-{
51
- return do_sve2_zzzz_fn(s, a, gen_bcax);
52
-}
53
+TRANS_FEAT(BCAX, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bcax, a)
54
55
static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
56
uint32_t a, uint32_t oprsz, uint32_t maxsz)
57
@@ -XXX,XX +XXX,XX @@ static void gen_bsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
58
tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz);
59
}
60
61
-static bool trans_BSL(DisasContext *s, arg_rrrr_esz *a)
62
-{
63
- return do_sve2_zzzz_fn(s, a, gen_bsl);
64
-}
65
+TRANS_FEAT(BSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl, a)
66
67
static void gen_bsl1n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
68
{
69
@@ -XXX,XX +XXX,XX @@ static void gen_bsl1n(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
70
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
71
}
72
73
-static bool trans_BSL1N(DisasContext *s, arg_rrrr_esz *a)
74
-{
75
- return do_sve2_zzzz_fn(s, a, gen_bsl1n);
76
-}
77
+TRANS_FEAT(BSL1N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl1n, a)
78
79
static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
80
{
81
@@ -XXX,XX +XXX,XX @@ static void gen_bsl2n(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
82
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
83
}
84
85
-static bool trans_BSL2N(DisasContext *s, arg_rrrr_esz *a)
86
-{
87
- return do_sve2_zzzz_fn(s, a, gen_bsl2n);
88
-}
89
+TRANS_FEAT(BSL2N, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_bsl2n, a)
90
91
static void gen_nbsl_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
92
{
93
@@ -XXX,XX +XXX,XX @@ static void gen_nbsl(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
94
tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
95
}
96
97
-static bool trans_NBSL(DisasContext *s, arg_rrrr_esz *a)
98
-{
99
- return do_sve2_zzzz_fn(s, a, gen_nbsl);
100
-}
101
+TRANS_FEAT(NBSL, aa64_sve2, gen_gvec_fn_arg_zzzz, gen_nbsl, a)
102
103
/*
104
*** SVE Integer Arithmetic - Unpredicated Group
105
--
106
2.25.1
diff view generated by jsdifflib
1
Convert the Neon 3-reg-same VADD and VSUB insns to decodetree.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Note that we don't need the neon_3r_sizes[op] check here because all
3
We have two places that perform this particular operation.
4
size values are OK for VADD and VSUB; we'll add this when we convert
5
the first insn that has size restrictions.
6
4
7
For this we need one of the GVecGen*Fn typedefs currently in
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
translate-a64.h; move them all to translate.h as a block so they
6
Message-id: 20220527181907.189259-39-richard.henderson@linaro.org
9
are visible to the 32-bit decoder.
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 30 +++++++++++++++++-------------
11
1 file changed, 17 insertions(+), 13 deletions(-)
10
12
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20200430181003.21682-15-peter.maydell@linaro.org
14
---
15
target/arm/translate-a64.h | 9 --------
16
target/arm/translate.h | 9 ++++++++
17
target/arm/neon-dp.decode | 17 +++++++++++++++
18
target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++
19
target/arm/translate.c | 14 ++++--------
20
5 files changed, 68 insertions(+), 19 deletions(-)
21
22
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
23
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/translate-a64.h
15
--- a/target/arm/translate-sve.c
25
+++ b/target/arm/translate-a64.h
16
+++ b/target/arm/translate-sve.c
26
@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)
17
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzz(DisasContext *s, gen_helper_gvec_4 *fn,
27
18
return gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, data);
28
bool disas_sve(DisasContext *, uint32_t);
29
30
-/* Note that the gvec expanders operate on offsets + sizes. */
31
-typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
32
-typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
33
- uint32_t, uint32_t);
34
-typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
35
- uint32_t, uint32_t, uint32_t);
36
-typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
37
- uint32_t, uint32_t, uint32_t);
38
-
39
#endif /* TARGET_ARM_TRANSLATE_A64_H */
40
diff --git a/target/arm/translate.h b/target/arm/translate.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/translate.h
43
+++ b/target/arm/translate.h
44
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
45
#define dc_isar_feature(name, ctx) \
46
({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
47
48
+/* Note that the gvec expanders operate on offsets + sizes. */
49
+typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
50
+typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
51
+ uint32_t, uint32_t);
52
+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
53
+ uint32_t, uint32_t, uint32_t);
54
+typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
55
+ uint32_t, uint32_t, uint32_t);
56
+
57
#endif /* TARGET_ARM_TRANSLATE_H */
58
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/neon-dp.decode
61
+++ b/target/arm/neon-dp.decode
62
@@ -XXX,XX +XXX,XX @@
63
#
64
# This file is processed by scripts/decodetree.py
65
#
66
+# VFP/Neon register fields; same as vfp.decode
67
+%vm_dp 5:1 0:4
68
+%vn_dp 7:1 16:4
69
+%vd_dp 22:1 12:4
70
71
# Encodings for Neon data processing instructions where the T32 encoding
72
# is a simple transformation of the A32 encoding.
73
@@ -XXX,XX +XXX,XX @@
74
# 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
75
# This file works on the A32 encoding only; calling code for T32 has to
76
# transform the insn into the A32 version first.
77
+
78
+######################################################################
79
+# 3-reg-same grouping:
80
+# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
81
+######################################################################
82
+
83
+&3same vm vn vd q size
84
+
85
+@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
86
+ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
87
+
88
+VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
89
+VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
90
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/translate-neon.inc.c
93
+++ b/target/arm/translate-neon.inc.c
94
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
95
96
return true;
97
}
19
}
98
+
20
99
+static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
21
+/* Invoke a vector expander on two Zregs and an immediate. */
22
+static bool gen_gvec_fn_zzi(DisasContext *s, GVecGen2iFn *gvec_fn,
23
+ int esz, int rd, int rn, uint64_t imm)
100
+{
24
+{
101
+ int vec_size = a->q ? 16 : 8;
25
+ if (gvec_fn == NULL) {
102
+ int rd_ofs = neon_reg_offset(a->vd, 0);
103
+ int rn_ofs = neon_reg_offset(a->vn, 0);
104
+ int rm_ofs = neon_reg_offset(a->vm, 0);
105
+
106
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
107
+ return false;
26
+ return false;
108
+ }
27
+ }
109
+
28
+ if (sve_access_check(s)) {
110
+ /* UNDEF accesses to D16-D31 if they don't exist. */
29
+ unsigned vsz = vec_full_reg_size(s);
111
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
30
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
112
+ ((a->vd | a->vn | a->vm) & 0x10)) {
31
+ vec_full_reg_offset(s, rn), imm, vsz, vsz);
113
+ return false;
114
+ }
32
+ }
115
+
116
+ if ((a->vn | a->vm | a->vd) & a->q) {
117
+ return false;
118
+ }
119
+
120
+ if (!vfp_access_check(s)) {
121
+ return true;
122
+ }
123
+
124
+ fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
125
+ return true;
33
+ return true;
126
+}
34
+}
127
+
35
+
128
+#define DO_3SAME(INSN, FUNC) \
36
/* Invoke a vector expander on three Zregs. */
129
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
37
static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
130
+ { \
38
int esz, int rd, int rn, int rm)
131
+ return do_3same(s, a, FUNC); \
39
@@ -XXX,XX +XXX,XX @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)
132
+ }
40
extract32(a->dbm, 6, 6))) {
133
+
41
return false;
134
+DO_3SAME(VADD, tcg_gen_gvec_add)
42
}
135
+DO_3SAME(VSUB, tcg_gen_gvec_sub)
43
- if (sve_access_check(s)) {
136
diff --git a/target/arm/translate.c b/target/arm/translate.c
44
- unsigned vsz = vec_full_reg_size(s);
137
index XXXXXXX..XXXXXXX 100644
45
- gvec_fn(MO_64, vec_full_reg_offset(s, a->rd),
138
--- a/target/arm/translate.c
46
- vec_full_reg_offset(s, a->rn), imm, vsz, vsz);
139
+++ b/target/arm/translate.c
47
- }
140
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
48
- return true;
141
}
49
+ return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm);
142
return 0;
50
}
143
51
144
- case NEON_3R_VADD_VSUB:
52
static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a)
145
- if (u) {
53
@@ -XXX,XX +XXX,XX @@ static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
146
- tcg_gen_gvec_sub(size, rd_ofs, rn_ofs, rm_ofs,
54
if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
147
- vec_size, vec_size);
55
return false;
148
- } else {
56
}
149
- tcg_gen_gvec_add(size, rd_ofs, rn_ofs, rm_ofs,
57
- if (sve_access_check(s)) {
150
- vec_size, vec_size);
58
- unsigned vsz = vec_full_reg_size(s);
151
- }
59
- unsigned rd_ofs = vec_full_reg_offset(s, a->rd);
152
- return 0;
60
- unsigned rn_ofs = vec_full_reg_offset(s, a->rn);
153
-
61
- fn(a->esz, rd_ofs, rn_ofs, a->imm, vsz, vsz);
154
case NEON_3R_VQADD:
62
- }
155
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
63
- return true;
156
rn_ofs, rm_ofs, vec_size, vec_size,
64
+ return gen_gvec_fn_zzi(s, fn, a->esz, a->rd, a->rn, a->imm);
157
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
65
}
158
tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
66
159
u ? &ushl_op[size] : &sshl_op[size]);
67
static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
160
return 0;
161
+
162
+ case NEON_3R_VADD_VSUB:
163
+ /* Already handled by decodetree */
164
+ return 1;
165
}
166
167
if (size == 3) {
168
--
68
--
169
2.20.1
69
2.25.1
170
171
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-40-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 +++--------------
9
1 file changed, 3 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zz_dbm(DisasContext *s, arg_rr_dbm *a, GVecGen2iFn *gvec_fn)
16
return gen_gvec_fn_zzi(s, gvec_fn, MO_64, a->rd, a->rn, imm);
17
}
18
19
-static bool trans_AND_zzi(DisasContext *s, arg_rr_dbm *a)
20
-{
21
- return do_zz_dbm(s, a, tcg_gen_gvec_andi);
22
-}
23
-
24
-static bool trans_ORR_zzi(DisasContext *s, arg_rr_dbm *a)
25
-{
26
- return do_zz_dbm(s, a, tcg_gen_gvec_ori);
27
-}
28
-
29
-static bool trans_EOR_zzi(DisasContext *s, arg_rr_dbm *a)
30
-{
31
- return do_zz_dbm(s, a, tcg_gen_gvec_xori);
32
-}
33
+TRANS_FEAT(AND_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_andi)
34
+TRANS_FEAT(ORR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_ori)
35
+TRANS_FEAT(EOR_zzi, aa64_sve, do_zz_dbm, a, tcg_gen_gvec_xori)
36
37
static bool trans_DUPM(DisasContext *s, arg_DUPM *a)
38
{
39
--
40
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The check is already done in gen_gvec_ool_zzzp,
4
which is called by do_sel_z; remove from callers.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-41-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 14 ++++----------
12
1 file changed, 4 insertions(+), 10 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UQSUB_zzz, aa64_sve, gen_gvec_fn_arg_zzz, tcg_gen_gvec_ussub, a)
19
/* Select active elememnts from Zn and inactive elements from Zm,
20
* storing the result in Zd.
21
*/
22
-static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
23
+static bool do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
24
{
25
static gen_helper_gvec_4 * const fns[4] = {
26
gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
27
gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d
28
};
29
- gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
30
+ return gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
31
}
32
33
#define DO_ZPZZ(NAME, FEAT, name) \
34
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0)
35
36
static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
37
{
38
- if (sve_access_check(s)) {
39
- do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
40
- }
41
- return true;
42
+ return do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
43
}
44
45
/*
46
@@ -XXX,XX +XXX,XX @@ static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a)
47
48
static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
49
{
50
- if (sve_access_check(s)) {
51
- do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
52
- }
53
- return true;
54
+ return do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
55
}
56
57
static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
58
--
59
2.25.1
diff view generated by jsdifflib
1
Convert the Neon "load single structure to all lanes" insns to
1
From: Richard Henderson <richard.henderson@linaro.org>
2
decodetree.
3
2
3
We have two places that perform this particular operation.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-42-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200430181003.21682-13-peter.maydell@linaro.org
7
---
9
---
8
target/arm/neon-ls.decode | 5 +++
10
target/arm/translate-sve.c | 21 +++++++++++++--------
9
target/arm/translate-neon.inc.c | 73 +++++++++++++++++++++++++++++++++
11
1 file changed, 13 insertions(+), 8 deletions(-)
10
target/arm/translate.c | 55 +------------------------
11
3 files changed, 80 insertions(+), 53 deletions(-)
12
12
13
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-ls.decode
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/neon-ls.decode
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_fn_zzi(DisasContext *s, GVecGen2iFn *gvec_fn,
18
19
VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
20
vd=%vd_dp
21
+
22
+# Neon load single element to all lanes
23
+
24
+VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
25
+ vd=%vd_dp
26
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/translate-neon.inc.c
29
+++ b/target/arm/translate-neon.inc.c
30
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
31
gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
32
return true;
18
return true;
33
}
19
}
34
+
20
35
+static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
21
+static bool gen_gvec_fn_arg_zzi(DisasContext *s, GVecGen2iFn *gvec_fn,
22
+ arg_rri_esz *a)
36
+{
23
+{
37
+ /* Neon load single structure to all lanes */
24
+ if (a->esz < 0) {
38
+ int reg, stride, vec_size;
25
+ /* Invalid tsz encoding -- see tszimm_esz. */
39
+ int vd = a->vd;
40
+ int size = a->size;
41
+ int nregs = a->n + 1;
42
+ TCGv_i32 addr, tmp;
43
+
44
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
45
+ return false;
26
+ return false;
46
+ }
27
+ }
28
+ return gen_gvec_fn_zzi(s, gvec_fn, a->esz, a->rd, a->rn, a->imm);
29
+}
47
+
30
+
48
+ /* UNDEF accesses to D16-D31 if they don't exist */
31
/* Invoke a vector expander on three Zregs. */
49
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
32
static bool gen_gvec_fn_zzz(DisasContext *s, GVecGen3Fn *gvec_fn,
50
+ return false;
33
int esz, int rd, int rn, int rm)
51
+ }
34
@@ -XXX,XX +XXX,XX @@ static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
52
+
35
if (a->esz == 0 && extract32(s->insn, 13, 1)) {
53
+ if (size == 3) {
36
return false;
54
+ if (nregs != 4 || a->a == 0) {
37
}
55
+ return false;
38
- if (sve_access_check(s)) {
56
+ }
39
- unsigned vsz = vec_full_reg_size(s);
57
+ /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */
40
- tcg_gen_gvec_addi(a->esz, vec_full_reg_offset(s, a->rd),
58
+ size = 2;
41
- vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz);
59
+ }
42
- }
60
+ if (nregs == 1 && a->a == 1 && size == 0) {
43
- return true;
61
+ return false;
44
+ return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
62
+ }
45
}
63
+ if (nregs == 3 && a->a == 1) {
46
64
+ return false;
47
static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a)
65
+ }
48
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true)
66
+
49
67
+ if (!vfp_access_check(s)) {
50
static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
68
+ return true;
51
{
69
+ }
52
- if (a->esz < 0 || !dc_isar_feature(aa64_sve2, s)) {
70
+
53
+ if (!dc_isar_feature(aa64_sve2, s)) {
71
+ /*
54
return false;
72
+ * VLD1 to all lanes: T bit indicates how many Dregs to write.
55
}
73
+ * VLD2/3/4 to all lanes: T bit indicates register stride.
56
- return gen_gvec_fn_zzi(s, fn, a->esz, a->rd, a->rn, a->imm);
74
+ */
57
+ return gen_gvec_fn_arg_zzi(s, fn, a);
75
+ stride = a->t ? 2 : 1;
58
}
76
+ vec_size = nregs == 1 ? stride * 8 : 8;
59
77
+
60
static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
78
+ tmp = tcg_temp_new_i32();
79
+ addr = tcg_temp_new_i32();
80
+ load_reg_var(s, addr, a->rn);
81
+ for (reg = 0; reg < nregs; reg++) {
82
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
83
+ s->be_data | size);
84
+ if ((vd & 1) && vec_size == 16) {
85
+ /*
86
+ * We cannot write 16 bytes at once because the
87
+ * destination is unaligned.
88
+ */
89
+ tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
90
+ 8, 8, tmp);
91
+ tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),
92
+ neon_reg_offset(vd, 0), 8, 8);
93
+ } else {
94
+ tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
95
+ vec_size, vec_size, tmp);
96
+ }
97
+ tcg_gen_addi_i32(addr, addr, 1 << size);
98
+ vd += stride;
99
+ }
100
+ tcg_temp_free_i32(tmp);
101
+ tcg_temp_free_i32(addr);
102
+
103
+ gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << size) * nregs);
104
+
105
+ return true;
106
+}
107
diff --git a/target/arm/translate.c b/target/arm/translate.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/translate.c
110
+++ b/target/arm/translate.c
111
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
112
int size;
113
int reg;
114
int load;
115
- int vec_size;
116
TCGv_i32 addr;
117
TCGv_i32 tmp;
118
119
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
120
} else {
121
size = (insn >> 10) & 3;
122
if (size == 3) {
123
- /* Load single element to all lanes. */
124
- int a = (insn >> 4) & 1;
125
- if (!load) {
126
- return 1;
127
- }
128
- size = (insn >> 6) & 3;
129
- nregs = ((insn >> 8) & 3) + 1;
130
-
131
- if (size == 3) {
132
- if (nregs != 4 || a == 0) {
133
- return 1;
134
- }
135
- /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
136
- size = 2;
137
- }
138
- if (nregs == 1 && a == 1 && size == 0) {
139
- return 1;
140
- }
141
- if (nregs == 3 && a == 1) {
142
- return 1;
143
- }
144
- addr = tcg_temp_new_i32();
145
- load_reg_var(s, addr, rn);
146
-
147
- /* VLD1 to all lanes: bit 5 indicates how many Dregs to write.
148
- * VLD2/3/4 to all lanes: bit 5 indicates register stride.
149
- */
150
- stride = (insn & (1 << 5)) ? 2 : 1;
151
- vec_size = nregs == 1 ? stride * 8 : 8;
152
-
153
- tmp = tcg_temp_new_i32();
154
- for (reg = 0; reg < nregs; reg++) {
155
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
156
- s->be_data | size);
157
- if ((rd & 1) && vec_size == 16) {
158
- /* We cannot write 16 bytes at once because the
159
- * destination is unaligned.
160
- */
161
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0),
162
- 8, 8, tmp);
163
- tcg_gen_gvec_mov(0, neon_reg_offset(rd + 1, 0),
164
- neon_reg_offset(rd, 0), 8, 8);
165
- } else {
166
- tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0),
167
- vec_size, vec_size, tmp);
168
- }
169
- tcg_gen_addi_i32(addr, addr, 1 << size);
170
- rd += stride;
171
- }
172
- tcg_temp_free_i32(tmp);
173
- tcg_temp_free_i32(addr);
174
- stride = (1 << size) * nregs;
175
+ /* Load single element to all lanes -- handled by decodetree */
176
+ return 1;
177
} else {
178
/* Single element. */
179
int idx = (insn >> 4) & 0xf;
180
--
61
--
181
2.20.1
62
2.25.1
182
183
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_sve2_fn2i
4
to use TRANS_FEAT and gen_gvec_fn_arg_zzi.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-43-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 43 ++++++--------------------------------
12
1 file changed, 6 insertions(+), 37 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static bool do_adcl(DisasContext *s, arg_rrrr_esz *a, bool sel)
19
TRANS_FEAT(ADCLB, aa64_sve2, do_adcl, a, false)
20
TRANS_FEAT(ADCLT, aa64_sve2, do_adcl, a, true)
21
22
-static bool do_sve2_fn2i(DisasContext *s, arg_rri_esz *a, GVecGen2iFn *fn)
23
-{
24
- if (!dc_isar_feature(aa64_sve2, s)) {
25
- return false;
26
- }
27
- return gen_gvec_fn_arg_zzi(s, fn, a);
28
-}
29
-
30
-static bool trans_SSRA(DisasContext *s, arg_rri_esz *a)
31
-{
32
- return do_sve2_fn2i(s, a, gen_gvec_ssra);
33
-}
34
-
35
-static bool trans_USRA(DisasContext *s, arg_rri_esz *a)
36
-{
37
- return do_sve2_fn2i(s, a, gen_gvec_usra);
38
-}
39
-
40
-static bool trans_SRSRA(DisasContext *s, arg_rri_esz *a)
41
-{
42
- return do_sve2_fn2i(s, a, gen_gvec_srsra);
43
-}
44
-
45
-static bool trans_URSRA(DisasContext *s, arg_rri_esz *a)
46
-{
47
- return do_sve2_fn2i(s, a, gen_gvec_ursra);
48
-}
49
-
50
-static bool trans_SRI(DisasContext *s, arg_rri_esz *a)
51
-{
52
- return do_sve2_fn2i(s, a, gen_gvec_sri);
53
-}
54
-
55
-static bool trans_SLI(DisasContext *s, arg_rri_esz *a)
56
-{
57
- return do_sve2_fn2i(s, a, gen_gvec_sli);
58
-}
59
+TRANS_FEAT(SSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ssra, a)
60
+TRANS_FEAT(USRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_usra, a)
61
+TRANS_FEAT(SRSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_srsra, a)
62
+TRANS_FEAT(URSRA, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_ursra, a)
63
+TRANS_FEAT(SRI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sri, a)
64
+TRANS_FEAT(SLI, aa64_sve2, gen_gvec_fn_arg_zzi, gen_gvec_sli, a)
65
66
TRANS_FEAT(SABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_saba, a)
67
TRANS_FEAT(UABA, aa64_sve2, gen_gvec_fn_arg_zzz, gen_gvec_uaba, a)
68
--
69
2.25.1
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
hw/arm: versal: Add support for the RTC.
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
4
Message-id: 20220527181907.189259-44-richard.henderson@linaro.org
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20200427181649.26851-10-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
7
---
12
include/hw/arm/xlnx-versal.h | 8 ++++++++
8
target/arm/translate-sve.c | 20 +++++++-------------
13
hw/arm/xlnx-versal.c | 21 +++++++++++++++++++++
9
1 file changed, 7 insertions(+), 13 deletions(-)
14
2 files changed, 29 insertions(+)
15
10
16
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-versal.h
13
--- a/target/arm/translate-sve.c
19
+++ b/include/hw/arm/xlnx-versal.h
14
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
21
#include "hw/char/pl011.h"
22
#include "hw/dma/xlnx-zdma.h"
23
#include "hw/net/cadence_gem.h"
24
+#include "hw/rtc/xlnx-zynqmp-rtc.h"
25
26
#define TYPE_XLNX_VERSAL "xlnx-versal"
27
#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
28
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
29
struct {
30
SDHCIState sd[XLNX_VERSAL_NR_SDS];
31
} iou;
32
+
33
+ XlnxZynqMPRTC rtc;
34
} pmc;
35
36
struct {
37
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
38
#define VERSAL_GEM1_IRQ_0 58
39
#define VERSAL_GEM1_WAKE_IRQ_0 59
40
#define VERSAL_ADMA_IRQ_0 60
41
+#define VERSAL_RTC_APB_ERR_IRQ 121
42
#define VERSAL_SD0_IRQ_0 126
43
+#define VERSAL_RTC_ALARM_IRQ 142
44
+#define VERSAL_RTC_SECONDS_IRQ 143
45
46
/* Architecturally reserved IRQs suitable for virtualization. */
47
#define VERSAL_RSVD_IRQ_FIRST 111
48
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
49
#define MM_PMC_SD0_SIZE 0x10000
50
#define MM_PMC_CRP 0xf1260000U
51
#define MM_PMC_CRP_SIZE 0x10000
52
+#define MM_PMC_RTC 0xf12a0000
53
+#define MM_PMC_RTC_SIZE 0x10000
54
#endif
55
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/hw/arm/xlnx-versal.c
58
+++ b/hw/arm/xlnx-versal.c
59
@@ -XXX,XX +XXX,XX @@ static void versal_create_sds(Versal *s, qemu_irq *pic)
60
}
61
}
16
}
62
17
63
+static void versal_create_rtc(Versal *s, qemu_irq *pic)
18
#define DO_VPZ(NAME, name) \
64
+{
19
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
65
+ SysBusDevice *sbd;
20
-{ \
66
+ MemoryRegion *mr;
21
- static gen_helper_gvec_reduc * const fns[4] = { \
67
+
22
+ static gen_helper_gvec_reduc * const name##_fns[4] = { \
68
+ sysbus_init_child_obj(OBJECT(s), "rtc", &s->pmc.rtc, sizeof(s->pmc.rtc),
23
gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
69
+ TYPE_XLNX_ZYNQMP_RTC);
24
gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
70
+ sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
25
}; \
71
+ qdev_init_nofail(DEVICE(sbd));
26
- return do_vpz_ool(s, a, fns[a->esz]); \
72
+
27
-}
73
+ mr = sysbus_mmio_get_region(sbd, 0);
28
+ TRANS_FEAT(NAME, aa64_sve, do_vpz_ool, a, name##_fns[a->esz])
74
+ memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
29
75
+
30
DO_VPZ(ORV, orv)
76
+ /*
31
DO_VPZ(ANDV, andv)
77
+ * TODO: Connect the ALARM and SECONDS interrupts once our RTC model
32
@@ -XXX,XX +XXX,XX @@ DO_VPZ(UMAXV, umaxv)
78
+ * supports them.
33
DO_VPZ(SMINV, sminv)
79
+ */
34
DO_VPZ(UMINV, uminv)
80
+ sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
35
81
+}
36
-static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a)
82
+
37
-{
83
/* This takes the board allocated linear DDR memory and creates aliases
38
- static gen_helper_gvec_reduc * const fns[4] = {
84
* for each split DDR range/aperture on the Versal address map.
39
- gen_helper_sve_saddv_b, gen_helper_sve_saddv_h,
85
*/
40
- gen_helper_sve_saddv_s, NULL
86
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
41
- };
87
versal_create_gems(s, pic);
42
- return do_vpz_ool(s, a, fns[a->esz]);
88
versal_create_admas(s, pic);
43
-}
89
versal_create_sds(s, pic);
44
+static gen_helper_gvec_reduc * const saddv_fns[4] = {
90
+ versal_create_rtc(s, pic);
45
+ gen_helper_sve_saddv_b, gen_helper_sve_saddv_h,
91
versal_map_ddr(s);
46
+ gen_helper_sve_saddv_s, NULL
92
versal_unimp(s);
47
+};
48
+TRANS_FEAT(SADDV, aa64_sve, do_vpz_ool, a, saddv_fns[a->esz])
49
50
#undef DO_VPZ
93
51
94
--
52
--
95
2.20.1
53
2.25.1
96
97
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-45-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 +++--------------
9
1 file changed, 3 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_shift_imm(DisasContext *s, arg_rri_esz *a, bool asr,
16
return true;
17
}
18
19
-static bool trans_ASR_zzi(DisasContext *s, arg_rri_esz *a)
20
-{
21
- return do_shift_imm(s, a, true, tcg_gen_gvec_sari);
22
-}
23
-
24
-static bool trans_LSR_zzi(DisasContext *s, arg_rri_esz *a)
25
-{
26
- return do_shift_imm(s, a, false, tcg_gen_gvec_shri);
27
-}
28
-
29
-static bool trans_LSL_zzi(DisasContext *s, arg_rri_esz *a)
30
-{
31
- return do_shift_imm(s, a, false, tcg_gen_gvec_shli);
32
-}
33
+TRANS_FEAT(ASR_zzi, aa64_sve, do_shift_imm, a, true, tcg_gen_gvec_sari)
34
+TRANS_FEAT(LSR_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shri)
35
+TRANS_FEAT(LSL_zzi, aa64_sve, do_shift_imm, a, false, tcg_gen_gvec_shli)
36
37
#define DO_ZZW(NAME, name) \
38
static gen_helper_gvec_3 * const name##_zzw_fns[4] = { \
39
--
40
2.25.1
diff view generated by jsdifflib
1
Convert the Neon "load/store multiple structures" insns to decodetree.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Share code between the various shifts using arg_rpri_esz.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-46-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200430181003.21682-12-peter.maydell@linaro.org
6
---
9
---
7
target/arm/neon-ls.decode | 7 ++
10
target/arm/translate-sve.c | 68 +++++++++++++++++---------------------
8
target/arm/translate-neon.inc.c | 124 ++++++++++++++++++++++++++++++++
11
1 file changed, 30 insertions(+), 38 deletions(-)
9
target/arm/translate.c | 91 +----------------------
10
3 files changed, 133 insertions(+), 89 deletions(-)
11
12
12
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/neon-ls.decode
15
--- a/target/arm/translate-sve.c
15
+++ b/target/arm/neon-ls.decode
16
+++ b/target/arm/translate-sve.c
16
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static bool do_movz_zpz(DisasContext *s, int rd, int rn, int pg,
17
# 0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
18
return gen_gvec_ool_zzp(s, fns[esz], rd, rn, pg, invert);
18
# This file works on the A32 encoding only; calling code for T32 has to
19
}
19
# transform the insn into the A32 version first.
20
21
+static bool do_shift_zpzi(DisasContext *s, arg_rpri_esz *a, bool asr,
22
+ gen_helper_gvec_3 * const fns[4])
23
+{
24
+ int max;
20
+
25
+
21
+%vd_dp 22:1 12:4
26
+ if (a->esz < 0) {
22
+
27
+ /* Invalid tsz encoding -- see tszimm_esz. */
23
+# Neon load/store multiple structures
24
+
25
+VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
26
+ vd=%vd_dp
27
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/translate-neon.inc.c
30
+++ b/target/arm/translate-neon.inc.c
31
@@ -XXX,XX +XXX,XX @@ static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
32
gen_helper_gvec_fmlal_idx_a32);
33
return true;
34
}
35
+
36
+static struct {
37
+ int nregs;
38
+ int interleave;
39
+ int spacing;
40
+} const neon_ls_element_type[11] = {
41
+ {1, 4, 1},
42
+ {1, 4, 2},
43
+ {4, 1, 1},
44
+ {2, 2, 2},
45
+ {1, 3, 1},
46
+ {1, 3, 2},
47
+ {3, 1, 1},
48
+ {1, 1, 1},
49
+ {1, 2, 1},
50
+ {1, 2, 2},
51
+ {2, 1, 1}
52
+};
53
+
54
+static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn,
55
+ int stride)
56
+{
57
+ if (rm != 15) {
58
+ TCGv_i32 base;
59
+
60
+ base = load_reg(s, rn);
61
+ if (rm == 13) {
62
+ tcg_gen_addi_i32(base, base, stride);
63
+ } else {
64
+ TCGv_i32 index;
65
+ index = load_reg(s, rm);
66
+ tcg_gen_add_i32(base, base, index);
67
+ tcg_temp_free_i32(index);
68
+ }
69
+ store_reg(s, rn, base);
70
+ }
71
+}
72
+
73
+static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
74
+{
75
+ /* Neon load/store multiple structures */
76
+ int nregs, interleave, spacing, reg, n;
77
+ MemOp endian = s->be_data;
78
+ int mmu_idx = get_mem_index(s);
79
+ int size = a->size;
80
+ TCGv_i64 tmp64;
81
+ TCGv_i32 addr, tmp;
82
+
83
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
84
+ return false;
28
+ return false;
85
+ }
29
+ }
86
+
30
+
87
+ /* UNDEF accesses to D16-D31 if they don't exist */
88
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
89
+ return false;
90
+ }
91
+ if (a->itype > 10) {
92
+ return false;
93
+ }
94
+ /* Catch UNDEF cases for bad values of align field */
95
+ switch (a->itype & 0xc) {
96
+ case 4:
97
+ if (a->align >= 2) {
98
+ return false;
99
+ }
100
+ break;
101
+ case 8:
102
+ if (a->align == 3) {
103
+ return false;
104
+ }
105
+ break;
106
+ default:
107
+ break;
108
+ }
109
+ nregs = neon_ls_element_type[a->itype].nregs;
110
+ interleave = neon_ls_element_type[a->itype].interleave;
111
+ spacing = neon_ls_element_type[a->itype].spacing;
112
+ if (size == 3 && (interleave | spacing) != 1) {
113
+ return false;
114
+ }
115
+
116
+ if (!vfp_access_check(s)) {
117
+ return true;
118
+ }
119
+
120
+ /* For our purposes, bytes are always little-endian. */
121
+ if (size == 0) {
122
+ endian = MO_LE;
123
+ }
124
+ /*
31
+ /*
125
+ * Consecutive little-endian elements from a single register
32
+ * Shift by element size is architecturally valid.
126
+ * can be promoted to a larger little-endian operation.
33
+ * For arithmetic right-shift, it's the same as by one less.
34
+ * For logical shifts and ASRD, it is a zeroing operation.
127
+ */
35
+ */
128
+ if (interleave == 1 && endian == MO_LE) {
36
+ max = 8 << a->esz;
129
+ size = 3;
37
+ if (a->imm >= max) {
130
+ }
38
+ if (asr) {
131
+ tmp64 = tcg_temp_new_i64();
39
+ a->imm = max - 1;
132
+ addr = tcg_temp_new_i32();
40
+ } else {
133
+ tmp = tcg_const_i32(1 << size);
41
+ return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
134
+ load_reg_var(s, addr, a->rn);
135
+ for (reg = 0; reg < nregs; reg++) {
136
+ for (n = 0; n < 8 >> size; n++) {
137
+ int xs;
138
+ for (xs = 0; xs < interleave; xs++) {
139
+ int tt = a->vd + reg + spacing * xs;
140
+
141
+ if (a->l) {
142
+ gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
143
+ neon_store_element64(tt, n, size, tmp64);
144
+ } else {
145
+ neon_load_element64(tmp64, tt, n, size);
146
+ gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
147
+ }
148
+ tcg_gen_add_i32(addr, addr, tmp);
149
+ }
150
+ }
42
+ }
151
+ }
43
+ }
152
+ tcg_temp_free_i32(addr);
44
+ return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
153
+ tcg_temp_free_i32(tmp);
45
+}
154
+ tcg_temp_free_i64(tmp64);
155
+
46
+
156
+ gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
47
static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
157
+ return true;
48
{
158
+}
49
static gen_helper_gvec_3 * const fns[4] = {
159
diff --git a/target/arm/translate.c b/target/arm/translate.c
50
gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h,
160
index XXXXXXX..XXXXXXX 100644
51
gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d,
161
--- a/target/arm/translate.c
52
};
162
+++ b/target/arm/translate.c
53
- if (a->esz < 0) {
163
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
54
- /* Invalid tsz encoding -- see tszimm_esz. */
55
- return false;
56
- }
57
- /* Shift by element size is architecturally valid. For
58
- arithmetic right-shift, it's the same as by one less. */
59
- a->imm = MIN(a->imm, (8 << a->esz) - 1);
60
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
61
+ return do_shift_zpzi(s, a, true, fns);
164
}
62
}
165
63
166
64
static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
167
-static struct {
65
@@ -XXX,XX +XXX,XX @@ static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
168
- int nregs;
66
gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h,
169
- int interleave;
67
gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d,
170
- int spacing;
68
};
171
-} const neon_ls_element_type[11] = {
69
- if (a->esz < 0) {
172
- {1, 4, 1},
70
- return false;
173
- {1, 4, 2},
71
- }
174
- {4, 1, 1},
72
- /* Shift by element size is architecturally valid.
175
- {2, 2, 2},
73
- For logical shifts, it is a zeroing operation. */
176
- {1, 3, 1},
74
- if (a->imm >= (8 << a->esz)) {
177
- {1, 3, 2},
75
- return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
178
- {3, 1, 1},
76
- } else {
179
- {1, 1, 1},
77
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
180
- {1, 2, 1},
78
- }
181
- {1, 2, 2},
79
+ return do_shift_zpzi(s, a, false, fns);
182
- {2, 1, 1}
80
}
183
-};
81
184
-
82
static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
185
/* Translate a NEON load/store element instruction. Return nonzero if the
83
@@ -XXX,XX +XXX,XX @@ static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
186
instruction is invalid. */
84
gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h,
187
static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
85
gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d,
188
{
86
};
189
int rd, rn, rm;
87
- if (a->esz < 0) {
190
- int op;
88
- return false;
191
int nregs;
89
- }
192
- int interleave;
90
- /* Shift by element size is architecturally valid.
193
- int spacing;
91
- For logical shifts, it is a zeroing operation. */
194
int stride;
92
- if (a->imm >= (8 << a->esz)) {
195
int size;
93
- return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
196
int reg;
94
- } else {
197
int load;
95
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
198
- int n;
96
- }
199
int vec_size;
97
+ return do_shift_zpzi(s, a, false, fns);
200
- int mmu_idx;
98
}
201
- MemOp endian;
99
202
TCGv_i32 addr;
100
static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
203
TCGv_i32 tmp;
101
@@ -XXX,XX +XXX,XX @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
204
- TCGv_i32 tmp2;
102
gen_helper_sve_asrd_b, gen_helper_sve_asrd_h,
205
- TCGv_i64 tmp64;
103
gen_helper_sve_asrd_s, gen_helper_sve_asrd_d,
206
104
};
207
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
105
- if (a->esz < 0) {
208
return 1;
106
- return false;
209
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
107
- }
210
rn = (insn >> 16) & 0xf;
108
- /* Shift by element size is architecturally valid. For arithmetic
211
rm = insn & 0xf;
109
- right shift for division, it is a zeroing operation. */
212
load = (insn & (1 << 21)) != 0;
110
- if (a->imm >= (8 << a->esz)) {
213
- endian = s->be_data;
111
- return do_movz_zpz(s, a->rd, a->rd, a->pg, a->esz, true);
214
- mmu_idx = get_mem_index(s);
112
- } else {
215
if ((insn & (1 << 23)) == 0) {
113
- return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
216
- /* Load store all elements. */
114
- }
217
- op = (insn >> 8) & 0xf;
115
+ return do_shift_zpzi(s, a, false, fns);
218
- size = (insn >> 6) & 3;
116
}
219
- if (op > 10)
117
220
- return 1;
118
static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = {
221
- /* Catch UNDEF cases for bad values of align field */
222
- switch (op & 0xc) {
223
- case 4:
224
- if (((insn >> 5) & 1) == 1) {
225
- return 1;
226
- }
227
- break;
228
- case 8:
229
- if (((insn >> 4) & 3) == 3) {
230
- return 1;
231
- }
232
- break;
233
- default:
234
- break;
235
- }
236
- nregs = neon_ls_element_type[op].nregs;
237
- interleave = neon_ls_element_type[op].interleave;
238
- spacing = neon_ls_element_type[op].spacing;
239
- if (size == 3 && (interleave | spacing) != 1) {
240
- return 1;
241
- }
242
- /* For our purposes, bytes are always little-endian. */
243
- if (size == 0) {
244
- endian = MO_LE;
245
- }
246
- /* Consecutive little-endian elements from a single register
247
- * can be promoted to a larger little-endian operation.
248
- */
249
- if (interleave == 1 && endian == MO_LE) {
250
- size = 3;
251
- }
252
- tmp64 = tcg_temp_new_i64();
253
- addr = tcg_temp_new_i32();
254
- tmp2 = tcg_const_i32(1 << size);
255
- load_reg_var(s, addr, rn);
256
- for (reg = 0; reg < nregs; reg++) {
257
- for (n = 0; n < 8 >> size; n++) {
258
- int xs;
259
- for (xs = 0; xs < interleave; xs++) {
260
- int tt = rd + reg + spacing * xs;
261
-
262
- if (load) {
263
- gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
264
- neon_store_element64(tt, n, size, tmp64);
265
- } else {
266
- neon_load_element64(tmp64, tt, n, size);
267
- gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
268
- }
269
- tcg_gen_add_i32(addr, addr, tmp2);
270
- }
271
- }
272
- }
273
- tcg_temp_free_i32(addr);
274
- tcg_temp_free_i32(tmp2);
275
- tcg_temp_free_i64(tmp64);
276
- stride = nregs * interleave * 8;
277
+ /* Load store all elements -- handled already by decodetree */
278
+ return 1;
279
} else {
280
size = (insn >> 10) & 3;
281
if (size == 3) {
282
--
119
--
283
2.20.1
120
2.25.1
284
285
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-47-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 52 +++++++++++++++-----------------------
9
1 file changed, 20 insertions(+), 32 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_shift_zpzi(DisasContext *s, arg_rpri_esz *a, bool asr,
16
return gen_gvec_ool_arg_zpzi(s, fns[a->esz], a);
17
}
18
19
-static bool trans_ASR_zpzi(DisasContext *s, arg_rpri_esz *a)
20
-{
21
- static gen_helper_gvec_3 * const fns[4] = {
22
- gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h,
23
- gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d,
24
- };
25
- return do_shift_zpzi(s, a, true, fns);
26
-}
27
+static gen_helper_gvec_3 * const asr_zpzi_fns[4] = {
28
+ gen_helper_sve_asr_zpzi_b, gen_helper_sve_asr_zpzi_h,
29
+ gen_helper_sve_asr_zpzi_s, gen_helper_sve_asr_zpzi_d,
30
+};
31
+TRANS_FEAT(ASR_zpzi, aa64_sve, do_shift_zpzi, a, true, asr_zpzi_fns)
32
33
-static bool trans_LSR_zpzi(DisasContext *s, arg_rpri_esz *a)
34
-{
35
- static gen_helper_gvec_3 * const fns[4] = {
36
- gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h,
37
- gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d,
38
- };
39
- return do_shift_zpzi(s, a, false, fns);
40
-}
41
+static gen_helper_gvec_3 * const lsr_zpzi_fns[4] = {
42
+ gen_helper_sve_lsr_zpzi_b, gen_helper_sve_lsr_zpzi_h,
43
+ gen_helper_sve_lsr_zpzi_s, gen_helper_sve_lsr_zpzi_d,
44
+};
45
+TRANS_FEAT(LSR_zpzi, aa64_sve, do_shift_zpzi, a, false, lsr_zpzi_fns)
46
47
-static bool trans_LSL_zpzi(DisasContext *s, arg_rpri_esz *a)
48
-{
49
- static gen_helper_gvec_3 * const fns[4] = {
50
- gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h,
51
- gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d,
52
- };
53
- return do_shift_zpzi(s, a, false, fns);
54
-}
55
+static gen_helper_gvec_3 * const lsl_zpzi_fns[4] = {
56
+ gen_helper_sve_lsl_zpzi_b, gen_helper_sve_lsl_zpzi_h,
57
+ gen_helper_sve_lsl_zpzi_s, gen_helper_sve_lsl_zpzi_d,
58
+};
59
+TRANS_FEAT(LSL_zpzi, aa64_sve, do_shift_zpzi, a, false, lsl_zpzi_fns)
60
61
-static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a)
62
-{
63
- static gen_helper_gvec_3 * const fns[4] = {
64
- gen_helper_sve_asrd_b, gen_helper_sve_asrd_h,
65
- gen_helper_sve_asrd_s, gen_helper_sve_asrd_d,
66
- };
67
- return do_shift_zpzi(s, a, false, fns);
68
-}
69
+static gen_helper_gvec_3 * const asrd_fns[4] = {
70
+ gen_helper_sve_asrd_b, gen_helper_sve_asrd_h,
71
+ gen_helper_sve_asrd_s, gen_helper_sve_asrd_d,
72
+};
73
+TRANS_FEAT(ASRD, aa64_sve, do_shift_zpzi, a, false, asrd_fns)
74
75
static gen_helper_gvec_3 * const sqshl_zpzi_fns[4] = {
76
gen_helper_sve2_sqshl_zpzi_b, gen_helper_sve2_sqshl_zpzi_h,
77
--
78
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the DO_ZPZZZ macro, as it had just the two uses.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20220527181907.189259-48-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-sve.c | 23 ++++++++++-------------
11
1 file changed, 10 insertions(+), 13 deletions(-)
12
13
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static bool do_zpzzz_ool(DisasContext *s, arg_rprrr_esz *a,
18
return true;
19
}
20
21
-#define DO_ZPZZZ(NAME, name) \
22
-static bool trans_##NAME(DisasContext *s, arg_rprrr_esz *a) \
23
-{ \
24
- static gen_helper_gvec_5 * const fns[4] = { \
25
- gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
26
- gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
27
- }; \
28
- return do_zpzzz_ool(s, a, fns[a->esz]); \
29
-}
30
+static gen_helper_gvec_5 * const mla_fns[4] = {
31
+ gen_helper_sve_mla_b, gen_helper_sve_mla_h,
32
+ gen_helper_sve_mla_s, gen_helper_sve_mla_d,
33
+};
34
+TRANS_FEAT(MLA, aa64_sve, do_zpzzz_ool, a, mla_fns[a->esz])
35
36
-DO_ZPZZZ(MLA, mla)
37
-DO_ZPZZZ(MLS, mls)
38
-
39
-#undef DO_ZPZZZ
40
+static gen_helper_gvec_5 * const mls_fns[4] = {
41
+ gen_helper_sve_mls_b, gen_helper_sve_mls_h,
42
+ gen_helper_sve_mls_s, gen_helper_sve_mls_d,
43
+};
44
+TRANS_FEAT(MLS, aa64_sve, do_zpzzz_ool, a, mls_fns[a->esz])
45
46
/*
47
*** SVE Index Generation Group
48
--
49
2.25.1
diff view generated by jsdifflib
1
Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
1
From: Richard Henderson <richard.henderson@linaro.org>
2
to decodetree.
3
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-49-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200430181003.21682-10-peter.maydell@linaro.org
7
---
7
---
8
target/arm/neon-shared.decode | 3 +++
8
target/arm/translate-sve.c | 53 ++++++++++++++++++--------------------
9
target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++
9
1 file changed, 25 insertions(+), 28 deletions(-)
10
target/arm/translate.c | 13 +-----------
11
3 files changed, 39 insertions(+), 12 deletions(-)
12
10
13
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-shared.decode
13
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/neon-shared.decode
14
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(MLS, aa64_sve, do_zpzzz_ool, a, mls_fns[a->esz])
18
vn=%vn_dp vd=%vd_dp size=0
16
*** SVE Index Generation Group
19
VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
17
*/
20
vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0
18
19
-static void do_index(DisasContext *s, int esz, int rd,
20
+static bool do_index(DisasContext *s, int esz, int rd,
21
TCGv_i64 start, TCGv_i64 incr)
22
{
23
- unsigned vsz = vec_full_reg_size(s);
24
- TCGv_i32 desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
25
- TCGv_ptr t_zd = tcg_temp_new_ptr();
26
+ unsigned vsz;
27
+ TCGv_i32 desc;
28
+ TCGv_ptr t_zd;
21
+
29
+
22
+VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
30
+ if (!sve_access_check(s)) {
23
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp
24
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/translate-neon.inc.c
27
+++ b/target/arm/translate-neon.inc.c
28
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
29
tcg_temp_free_ptr(fpst);
30
return true;
31
}
32
+
33
+static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
34
+{
35
+ gen_helper_gvec_3 *fn_gvec;
36
+ int opr_sz;
37
+ TCGv_ptr fpst;
38
+
39
+ if (!dc_isar_feature(aa32_dp, s)) {
40
+ return false;
41
+ }
42
+
43
+ /* UNDEF accesses to D16-D31 if they don't exist. */
44
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
45
+ ((a->vd | a->vn) & 0x10)) {
46
+ return false;
47
+ }
48
+
49
+ if ((a->vd | a->vn) & a->q) {
50
+ return false;
51
+ }
52
+
53
+ if (!vfp_access_check(s)) {
54
+ return true;
31
+ return true;
55
+ }
32
+ }
56
+
33
+
57
+ fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
34
+ vsz = vec_full_reg_size(s);
58
+ opr_sz = (1 + a->q) * 8;
35
+ desc = tcg_constant_i32(simd_desc(vsz, vsz, 0));
59
+ fpst = get_fpstatus_ptr(1);
36
+ t_zd = tcg_temp_new_ptr();
60
+ tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
37
61
+ vfp_reg_offset(1, a->vn),
38
tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd));
62
+ vfp_reg_offset(1, a->rm),
39
if (esz == 3) {
63
+ opr_sz, opr_sz, a->index, fn_gvec);
40
@@ -XXX,XX +XXX,XX @@ static void do_index(DisasContext *s, int esz, int rd,
64
+ tcg_temp_free_ptr(fpst);
41
tcg_temp_free_i32(i32);
42
}
43
tcg_temp_free_ptr(t_zd);
65
+ return true;
44
+ return true;
66
+}
45
}
67
diff --git a/target/arm/translate.c b/target/arm/translate.c
46
68
index XXXXXXX..XXXXXXX 100644
47
static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
69
--- a/target/arm/translate.c
48
{
70
+++ b/target/arm/translate.c
49
- if (sve_access_check(s)) {
71
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
50
- TCGv_i64 start = tcg_constant_i64(a->imm1);
72
bool is_long = false, q = extract32(insn, 6, 1);
51
- TCGv_i64 incr = tcg_constant_i64(a->imm2);
73
bool ptr_is_env = false;
52
- do_index(s, a->esz, a->rd, start, incr);
74
53
- }
75
- if ((insn & 0xffb00f00) == 0xfe200d00) {
54
- return true;
76
- /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
55
+ TCGv_i64 start = tcg_constant_i64(a->imm1);
77
- int u = extract32(insn, 4, 1);
56
+ TCGv_i64 incr = tcg_constant_i64(a->imm2);
78
-
57
+ return do_index(s, a->esz, a->rd, start, incr);
79
- if (!dc_isar_feature(aa32_dp, s)) {
58
}
80
- return 1;
59
81
- }
60
static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
82
- fn_gvec = u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
61
{
83
- /* rm is just Vm, and index is M. */
62
- if (sve_access_check(s)) {
84
- data = extract32(insn, 5, 1); /* index */
63
- TCGv_i64 start = tcg_constant_i64(a->imm);
85
- rm = extract32(insn, 0, 4);
64
- TCGv_i64 incr = cpu_reg(s, a->rm);
86
- } else if ((insn & 0xffa00f10) == 0xfe000810) {
65
- do_index(s, a->esz, a->rd, start, incr);
87
+ if ((insn & 0xffa00f10) == 0xfe000810) {
66
- }
88
/* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
67
- return true;
89
int is_s = extract32(insn, 20, 1);
68
+ TCGv_i64 start = tcg_constant_i64(a->imm);
90
int vm20 = extract32(insn, 0, 3);
69
+ TCGv_i64 incr = cpu_reg(s, a->rm);
70
+ return do_index(s, a->esz, a->rd, start, incr);
71
}
72
73
static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
74
{
75
- if (sve_access_check(s)) {
76
- TCGv_i64 start = cpu_reg(s, a->rn);
77
- TCGv_i64 incr = tcg_constant_i64(a->imm);
78
- do_index(s, a->esz, a->rd, start, incr);
79
- }
80
- return true;
81
+ TCGv_i64 start = cpu_reg(s, a->rn);
82
+ TCGv_i64 incr = tcg_constant_i64(a->imm);
83
+ return do_index(s, a->esz, a->rd, start, incr);
84
}
85
86
static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a)
87
{
88
- if (sve_access_check(s)) {
89
- TCGv_i64 start = cpu_reg(s, a->rn);
90
- TCGv_i64 incr = cpu_reg(s, a->rm);
91
- do_index(s, a->esz, a->rd, start, incr);
92
- }
93
- return true;
94
+ TCGv_i64 start = cpu_reg(s, a->rn);
95
+ TCGv_i64 incr = cpu_reg(s, a->rm);
96
+ return do_index(s, a->esz, a->rd, start, incr);
97
}
98
99
/*
91
--
100
--
92
2.20.1
101
2.25.1
93
94
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-50-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 35 ++++++++---------------------------
9
1 file changed, 8 insertions(+), 27 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_index(DisasContext *s, int esz, int rd,
16
return true;
17
}
18
19
-static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a)
20
-{
21
- TCGv_i64 start = tcg_constant_i64(a->imm1);
22
- TCGv_i64 incr = tcg_constant_i64(a->imm2);
23
- return do_index(s, a->esz, a->rd, start, incr);
24
-}
25
-
26
-static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a)
27
-{
28
- TCGv_i64 start = tcg_constant_i64(a->imm);
29
- TCGv_i64 incr = cpu_reg(s, a->rm);
30
- return do_index(s, a->esz, a->rd, start, incr);
31
-}
32
-
33
-static bool trans_INDEX_ri(DisasContext *s, arg_INDEX_ri *a)
34
-{
35
- TCGv_i64 start = cpu_reg(s, a->rn);
36
- TCGv_i64 incr = tcg_constant_i64(a->imm);
37
- return do_index(s, a->esz, a->rd, start, incr);
38
-}
39
-
40
-static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a)
41
-{
42
- TCGv_i64 start = cpu_reg(s, a->rn);
43
- TCGv_i64 incr = cpu_reg(s, a->rm);
44
- return do_index(s, a->esz, a->rd, start, incr);
45
-}
46
+TRANS_FEAT(INDEX_ii, aa64_sve, do_index, a->esz, a->rd,
47
+ tcg_constant_i64(a->imm1), tcg_constant_i64(a->imm2))
48
+TRANS_FEAT(INDEX_ir, aa64_sve, do_index, a->esz, a->rd,
49
+ tcg_constant_i64(a->imm), cpu_reg(s, a->rm))
50
+TRANS_FEAT(INDEX_ri, aa64_sve, do_index, a->esz, a->rd,
51
+ cpu_reg(s, a->rn), tcg_constant_i64(a->imm))
52
+TRANS_FEAT(INDEX_rr, aa64_sve, do_index, a->esz, a->rd,
53
+ cpu_reg(s, a->rn), cpu_reg(s, a->rm))
54
55
/*
56
*** SVE Stack Allocation Group
57
--
58
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-51-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 23 ++++-------------------
9
1 file changed, 4 insertions(+), 19 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
16
return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, a->imm);
17
}
18
19
-static bool trans_ADR_p32(DisasContext *s, arg_rrri *a)
20
-{
21
- return do_adr(s, a, gen_helper_sve_adr_p32);
22
-}
23
-
24
-static bool trans_ADR_p64(DisasContext *s, arg_rrri *a)
25
-{
26
- return do_adr(s, a, gen_helper_sve_adr_p64);
27
-}
28
-
29
-static bool trans_ADR_s32(DisasContext *s, arg_rrri *a)
30
-{
31
- return do_adr(s, a, gen_helper_sve_adr_s32);
32
-}
33
-
34
-static bool trans_ADR_u32(DisasContext *s, arg_rrri *a)
35
-{
36
- return do_adr(s, a, gen_helper_sve_adr_u32);
37
-}
38
+TRANS_FEAT(ADR_p32, aa64_sve, do_adr, a, gen_helper_sve_adr_p32)
39
+TRANS_FEAT(ADR_p64, aa64_sve, do_adr, a, gen_helper_sve_adr_p64)
40
+TRANS_FEAT(ADR_s32, aa64_sve, do_adr, a, gen_helper_sve_adr_s32)
41
+TRANS_FEAT(ADR_u32, aa64_sve, do_adr, a, gen_helper_sve_adr_u32)
42
43
/*
44
*** SVE Integer Misc - Unpredicated Group
45
--
46
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-52-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 19 +++++--------------
9
1 file changed, 5 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_predset(DisasContext *s, int esz, int rd, int pat, bool setflag)
16
return true;
17
}
18
19
-static bool trans_PTRUE(DisasContext *s, arg_PTRUE *a)
20
-{
21
- return do_predset(s, a->esz, a->rd, a->pat, a->s);
22
-}
23
+TRANS_FEAT(PTRUE, aa64_sve, do_predset, a->esz, a->rd, a->pat, a->s)
24
25
-static bool trans_SETFFR(DisasContext *s, arg_SETFFR *a)
26
-{
27
- /* Note pat == 31 is #all, to set all elements. */
28
- return do_predset(s, 0, FFR_PRED_NUM, 31, false);
29
-}
30
+/* Note pat == 31 is #all, to set all elements. */
31
+TRANS_FEAT(SETFFR, aa64_sve, do_predset, 0, FFR_PRED_NUM, 31, false)
32
33
-static bool trans_PFALSE(DisasContext *s, arg_PFALSE *a)
34
-{
35
- /* Note pat == 32 is #unimp, to set no elements. */
36
- return do_predset(s, 0, a->rd, 32, false);
37
-}
38
+/* Note pat == 32 is #unimp, to set no elements. */
39
+TRANS_FEAT(PFALSE, aa64_sve, do_predset, 0, a->rd, 32, false)
40
41
static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a)
42
{
43
--
44
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-53-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_RDFFR_p(DisasContext *s, arg_RDFFR_p *a)
16
return trans_AND_pppp(s, &alt_a);
17
}
18
19
-static bool trans_RDFFR(DisasContext *s, arg_RDFFR *a)
20
-{
21
- return do_mov_p(s, a->rd, FFR_PRED_NUM);
22
-}
23
-
24
-static bool trans_WRFFR(DisasContext *s, arg_WRFFR *a)
25
-{
26
- return do_mov_p(s, FFR_PRED_NUM, a->rn);
27
-}
28
+TRANS_FEAT(RDFFR, aa64_sve, do_mov_p, a->rd, FFR_PRED_NUM)
29
+TRANS_FEAT(WRFFR, aa64_sve, do_mov_p, FFR_PRED_NUM, a->rn)
30
31
static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
32
void (*gen_fn)(TCGv_i32, TCGv_ptr,
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-54-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_esz *a,
16
return true;
17
}
18
19
-static bool trans_PFIRST(DisasContext *s, arg_rr_esz *a)
20
-{
21
- return do_pfirst_pnext(s, a, gen_helper_sve_pfirst);
22
-}
23
-
24
-static bool trans_PNEXT(DisasContext *s, arg_rr_esz *a)
25
-{
26
- return do_pfirst_pnext(s, a, gen_helper_sve_pnext);
27
-}
28
+TRANS_FEAT(PFIRST, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pfirst)
29
+TRANS_FEAT(PNEXT, aa64_sve, do_pfirst_pnext, a, gen_helper_sve_pnext)
30
31
/*
32
*** SVE Element Count Group
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-55-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 14 ++------------
9
1 file changed, 2 insertions(+), 12 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_EXT(DisasContext *s, int rd, int rn, int rm, int imm)
16
return true;
17
}
18
19
-static bool trans_EXT(DisasContext *s, arg_EXT *a)
20
-{
21
- return do_EXT(s, a->rd, a->rn, a->rm, a->imm);
22
-}
23
-
24
-static bool trans_EXT_sve2(DisasContext *s, arg_rri *a)
25
-{
26
- if (!dc_isar_feature(aa64_sve2, s)) {
27
- return false;
28
- }
29
- return do_EXT(s, a->rd, a->rn, (a->rn + 1) % 32, a->imm);
30
-}
31
+TRANS_FEAT(EXT, aa64_sve, do_EXT, a->rd, a->rn, a->rm, a->imm)
32
+TRANS_FEAT(EXT_sve2, aa64_sve2, do_EXT, a->rd, a->rn, (a->rn + 1) % 32, a->imm)
33
34
/*
35
*** SVE Permute - Unpredicated Group
36
--
37
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-56-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 35 ++++++-----------------------------
9
1 file changed, 6 insertions(+), 29 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz *a, bool high_odd,
16
return true;
17
}
18
19
-static bool trans_ZIP1_p(DisasContext *s, arg_rrr_esz *a)
20
-{
21
- return do_perm_pred3(s, a, 0, gen_helper_sve_zip_p);
22
-}
23
-
24
-static bool trans_ZIP2_p(DisasContext *s, arg_rrr_esz *a)
25
-{
26
- return do_perm_pred3(s, a, 1, gen_helper_sve_zip_p);
27
-}
28
-
29
-static bool trans_UZP1_p(DisasContext *s, arg_rrr_esz *a)
30
-{
31
- return do_perm_pred3(s, a, 0, gen_helper_sve_uzp_p);
32
-}
33
-
34
-static bool trans_UZP2_p(DisasContext *s, arg_rrr_esz *a)
35
-{
36
- return do_perm_pred3(s, a, 1, gen_helper_sve_uzp_p);
37
-}
38
-
39
-static bool trans_TRN1_p(DisasContext *s, arg_rrr_esz *a)
40
-{
41
- return do_perm_pred3(s, a, 0, gen_helper_sve_trn_p);
42
-}
43
-
44
-static bool trans_TRN2_p(DisasContext *s, arg_rrr_esz *a)
45
-{
46
- return do_perm_pred3(s, a, 1, gen_helper_sve_trn_p);
47
-}
48
+TRANS_FEAT(ZIP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_zip_p)
49
+TRANS_FEAT(ZIP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_zip_p)
50
+TRANS_FEAT(UZP1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_uzp_p)
51
+TRANS_FEAT(UZP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_uzp_p)
52
+TRANS_FEAT(TRN1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_trn_p)
53
+TRANS_FEAT(TRN2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_trn_p)
54
55
static bool trans_REV_p(DisasContext *s, arg_rr_esz *a)
56
{
57
--
58
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-57-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 +++--------------
9
1 file changed, 3 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(UZP2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_uzp_p)
16
TRANS_FEAT(TRN1_p, aa64_sve, do_perm_pred3, a, 0, gen_helper_sve_trn_p)
17
TRANS_FEAT(TRN2_p, aa64_sve, do_perm_pred3, a, 1, gen_helper_sve_trn_p)
18
19
-static bool trans_REV_p(DisasContext *s, arg_rr_esz *a)
20
-{
21
- return do_perm_pred2(s, a, 0, gen_helper_sve_rev_p);
22
-}
23
-
24
-static bool trans_PUNPKLO(DisasContext *s, arg_PUNPKLO *a)
25
-{
26
- return do_perm_pred2(s, a, 0, gen_helper_sve_punpk_p);
27
-}
28
-
29
-static bool trans_PUNPKHI(DisasContext *s, arg_PUNPKHI *a)
30
-{
31
- return do_perm_pred2(s, a, 1, gen_helper_sve_punpk_p);
32
-}
33
+TRANS_FEAT(REV_p, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_rev_p)
34
+TRANS_FEAT(PUNPKLO, aa64_sve, do_perm_pred2, a, 0, gen_helper_sve_punpk_p)
35
+TRANS_FEAT(PUNPKHI, aa64_sve, do_perm_pred2, a, 1, gen_helper_sve_punpk_p)
36
37
/*
38
*** SVE Permute - Interleaving Group
39
--
40
2.25.1
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Embed the GEMs into the SoC type.
3
This is in line with how we treat uzp, and will
4
eliminate the special case code during translation.
4
5
5
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Message-id: 20220527181907.189259-58-richard.henderson@linaro.org
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
10
Message-id: 20200427181649.26851-6-edgar.iglesias@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
include/hw/arm/xlnx-versal.h | 3 ++-
11
target/arm/sve_helper.c | 6 ++++--
14
hw/arm/xlnx-versal.c | 15 ++++++++-------
12
target/arm/translate-sve.c | 12 ++++++------
15
2 files changed, 10 insertions(+), 8 deletions(-)
13
2 files changed, 10 insertions(+), 8 deletions(-)
16
14
17
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
15
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/xlnx-versal.h
17
--- a/target/arm/sve_helper.c
20
+++ b/include/hw/arm/xlnx-versal.h
18
+++ b/target/arm/sve_helper.c
21
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ void HELPER(sve_punpk_p)(void *vd, void *vn, uint32_t pred_desc)
22
#include "hw/arm/boot.h"
20
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
23
#include "hw/intc/arm_gicv3.h"
21
{ \
24
#include "hw/char/pl011.h"
22
intptr_t oprsz = simd_oprsz(desc); \
25
+#include "hw/net/cadence_gem.h"
23
+ intptr_t odd_ofs = simd_data(desc); \
26
24
intptr_t i, oprsz_2 = oprsz / 2; \
27
#define TYPE_XLNX_VERSAL "xlnx-versal"
25
ARMVectorReg tmp_n, tmp_m; \
28
#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
26
/* We produce output faster than we consume input. \
29
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
27
@@ -XXX,XX +XXX,XX @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
30
28
vm = memcpy(&tmp_m, vm, oprsz_2); \
31
struct {
29
} \
32
PL011State uart[XLNX_VERSAL_NR_UARTS];
30
for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \
33
- SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
31
- *(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + H(i)); \
34
+ CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
32
- *(TYPE *)(vd + H(2 * i + sizeof(TYPE))) = *(TYPE *)(vm + H(i)); \
35
SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
33
+ *(TYPE *)(vd + H(2 * i + 0)) = *(TYPE *)(vn + odd_ofs + H(i)); \
36
} iou;
34
+ *(TYPE *)(vd + H(2 * i + sizeof(TYPE))) = \
37
} lpd;
35
+ *(TYPE *)(vm + odd_ofs + H(i)); \
38
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
36
} \
37
if (sizeof(TYPE) == 16 && unlikely(oprsz & 16)) { \
38
memset(vd + oprsz - 16, 0, 16); \
39
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
39
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/arm/xlnx-versal.c
41
--- a/target/arm/translate-sve.c
41
+++ b/hw/arm/xlnx-versal.c
42
+++ b/target/arm/translate-sve.c
42
@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
43
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
43
DeviceState *dev;
44
unsigned vsz = vec_full_reg_size(s);
44
MemoryRegion *mr;
45
unsigned high_ofs = high ? vsz / 2 : 0;
45
46
tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
46
- dev = qdev_create(NULL, "cadence_gem");
47
- vec_full_reg_offset(s, a->rn) + high_ofs,
47
- s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);
48
- vec_full_reg_offset(s, a->rm) + high_ofs,
48
- object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
49
- vsz, vsz, 0, fns[a->esz]);
49
+ sysbus_init_child_obj(OBJECT(s), name,
50
+ vec_full_reg_offset(s, a->rn),
50
+ &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]),
51
+ vec_full_reg_offset(s, a->rm),
51
+ TYPE_CADENCE_GEM);
52
+ vsz, vsz, high_ofs, fns[a->esz]);
52
+ dev = DEVICE(&s->lpd.iou.gem[i]);
53
if (nd->used) {
54
qemu_check_nic_model(nd, "cadence_gem");
55
qdev_set_nic_properties(dev, nd);
56
}
57
- object_property_set_int(OBJECT(s->lpd.iou.gem[i]),
58
+ object_property_set_int(OBJECT(dev),
59
2, "num-priority-queues",
60
&error_abort);
61
- object_property_set_link(OBJECT(s->lpd.iou.gem[i]),
62
+ object_property_set_link(OBJECT(dev),
63
OBJECT(&s->mr_ps), "dma",
64
&error_abort);
65
qdev_init_nofail(dev);
66
67
- mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);
68
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
69
memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
70
71
- sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);
72
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
73
g_free(name);
74
}
53
}
54
return true;
55
}
56
@@ -XXX,XX +XXX,XX @@ static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high)
57
unsigned vsz = vec_full_reg_size(s);
58
unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
59
tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
60
- vec_full_reg_offset(s, a->rn) + high_ofs,
61
- vec_full_reg_offset(s, a->rm) + high_ofs,
62
- vsz, vsz, 0, gen_helper_sve2_zip_q);
63
+ vec_full_reg_offset(s, a->rn),
64
+ vec_full_reg_offset(s, a->rm),
65
+ vsz, vsz, high_ofs, gen_helper_sve2_zip_q);
66
}
67
return true;
75
}
68
}
76
--
69
--
77
2.20.1
70
2.25.1
78
79
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-59-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 25 +++++++------------------
9
1 file changed, 7 insertions(+), 18 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
16
gen_helper_sve_zip_b, gen_helper_sve_zip_h,
17
gen_helper_sve_zip_s, gen_helper_sve_zip_d,
18
};
19
+ unsigned vsz = vec_full_reg_size(s);
20
+ unsigned high_ofs = high ? vsz / 2 : 0;
21
22
- if (sve_access_check(s)) {
23
- unsigned vsz = vec_full_reg_size(s);
24
- unsigned high_ofs = high ? vsz / 2 : 0;
25
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
26
- vec_full_reg_offset(s, a->rn),
27
- vec_full_reg_offset(s, a->rm),
28
- vsz, vsz, high_ofs, fns[a->esz]);
29
- }
30
- return true;
31
+ return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, high_ofs);
32
}
33
34
static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
35
@@ -XXX,XX +XXX,XX @@ static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a)
36
37
static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high)
38
{
39
+ unsigned vsz = vec_full_reg_size(s);
40
+ unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
41
+
42
if (!dc_isar_feature(aa64_sve_f64mm, s)) {
43
return false;
44
}
45
- if (sve_access_check(s)) {
46
- unsigned vsz = vec_full_reg_size(s);
47
- unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
48
- tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd),
49
- vec_full_reg_offset(s, a->rn),
50
- vec_full_reg_offset(s, a->rm),
51
- vsz, vsz, high_ofs, gen_helper_sve2_zip_q);
52
- }
53
- return true;
54
+ return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_zip_q, a, high_ofs);
55
}
56
57
static bool trans_ZIP1_q(DisasContext *s, arg_rrr_esz *a)
58
--
59
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Convert SVE translation functions using do_zip*
4
to use TRANS_FEAT and gen_gvec_ool_arg_zzz.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-60-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-sve.c | 54 +++++++++-----------------------------
12
1 file changed, 13 insertions(+), 41 deletions(-)
13
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(PUNPKHI, aa64_sve, do_perm_pred2, a, 1, gen_helper_sve_punpk_p)
19
*** SVE Permute - Interleaving Group
20
*/
21
22
-static bool do_zip(DisasContext *s, arg_rrr_esz *a, bool high)
23
-{
24
- static gen_helper_gvec_3 * const fns[4] = {
25
- gen_helper_sve_zip_b, gen_helper_sve_zip_h,
26
- gen_helper_sve_zip_s, gen_helper_sve_zip_d,
27
- };
28
- unsigned vsz = vec_full_reg_size(s);
29
- unsigned high_ofs = high ? vsz / 2 : 0;
30
+static gen_helper_gvec_3 * const zip_fns[4] = {
31
+ gen_helper_sve_zip_b, gen_helper_sve_zip_h,
32
+ gen_helper_sve_zip_s, gen_helper_sve_zip_d,
33
+};
34
+TRANS_FEAT(ZIP1_z, aa64_sve, gen_gvec_ool_arg_zzz,
35
+ zip_fns[a->esz], a, 0)
36
+TRANS_FEAT(ZIP2_z, aa64_sve, gen_gvec_ool_arg_zzz,
37
+ zip_fns[a->esz], a, vec_full_reg_size(s) / 2)
38
39
- return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, high_ofs);
40
-}
41
-
42
-static bool trans_ZIP1_z(DisasContext *s, arg_rrr_esz *a)
43
-{
44
- return do_zip(s, a, false);
45
-}
46
-
47
-static bool trans_ZIP2_z(DisasContext *s, arg_rrr_esz *a)
48
-{
49
- return do_zip(s, a, true);
50
-}
51
-
52
-static bool do_zip_q(DisasContext *s, arg_rrr_esz *a, bool high)
53
-{
54
- unsigned vsz = vec_full_reg_size(s);
55
- unsigned high_ofs = high ? QEMU_ALIGN_DOWN(vsz, 32) / 2 : 0;
56
-
57
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
58
- return false;
59
- }
60
- return gen_gvec_ool_arg_zzz(s, gen_helper_sve2_zip_q, a, high_ofs);
61
-}
62
-
63
-static bool trans_ZIP1_q(DisasContext *s, arg_rrr_esz *a)
64
-{
65
- return do_zip_q(s, a, false);
66
-}
67
-
68
-static bool trans_ZIP2_q(DisasContext *s, arg_rrr_esz *a)
69
-{
70
- return do_zip_q(s, a, true);
71
-}
72
+TRANS_FEAT(ZIP1_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
73
+ gen_helper_sve2_zip_q, a, 0)
74
+TRANS_FEAT(ZIP2_q, aa64_sve_f64mm, gen_gvec_ool_arg_zzz,
75
+ gen_helper_sve2_zip_q, a,
76
+ QEMU_ALIGN_DOWN(vec_full_reg_size(s), 32) / 2)
77
78
static gen_helper_gvec_3 * const uzp_fns[4] = {
79
gen_helper_sve_uzp_b, gen_helper_sve_uzp_h,
80
--
81
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-61-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_clast_vector(DisasContext *s, arg_rprr_esz *a, bool before)
16
return true;
17
}
18
19
-static bool trans_CLASTA_z(DisasContext *s, arg_rprr_esz *a)
20
-{
21
- return do_clast_vector(s, a, false);
22
-}
23
-
24
-static bool trans_CLASTB_z(DisasContext *s, arg_rprr_esz *a)
25
-{
26
- return do_clast_vector(s, a, true);
27
-}
28
+TRANS_FEAT(CLASTA_z, aa64_sve, do_clast_vector, a, false)
29
+TRANS_FEAT(CLASTB_z, aa64_sve, do_clast_vector, a, true)
30
31
/* Compute CLAST for a scalar. */
32
static void do_clast_scalar(DisasContext *s, int esz, int pg, int rm,
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-62-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_clast_fp(DisasContext *s, arg_rpr_esz *a, bool before)
16
return true;
17
}
18
19
-static bool trans_CLASTA_v(DisasContext *s, arg_rpr_esz *a)
20
-{
21
- return do_clast_fp(s, a, false);
22
-}
23
-
24
-static bool trans_CLASTB_v(DisasContext *s, arg_rpr_esz *a)
25
-{
26
- return do_clast_fp(s, a, true);
27
-}
28
+TRANS_FEAT(CLASTA_v, aa64_sve, do_clast_fp, a, false)
29
+TRANS_FEAT(CLASTB_v, aa64_sve, do_clast_fp, a, true)
30
31
/* Compute CLAST for a Xreg. */
32
static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before)
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-63-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_clast_general(DisasContext *s, arg_rpr_esz *a, bool before)
16
return true;
17
}
18
19
-static bool trans_CLASTA_r(DisasContext *s, arg_rpr_esz *a)
20
-{
21
- return do_clast_general(s, a, false);
22
-}
23
-
24
-static bool trans_CLASTB_r(DisasContext *s, arg_rpr_esz *a)
25
-{
26
- return do_clast_general(s, a, true);
27
-}
28
+TRANS_FEAT(CLASTA_r, aa64_sve, do_clast_general, a, false)
29
+TRANS_FEAT(CLASTB_r, aa64_sve, do_clast_general, a, true)
30
31
/* Compute LAST for a scalar. */
32
static TCGv_i64 do_last_scalar(DisasContext *s, int esz,
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-64-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_last_fp(DisasContext *s, arg_rpr_esz *a, bool before)
16
return true;
17
}
18
19
-static bool trans_LASTA_v(DisasContext *s, arg_rpr_esz *a)
20
-{
21
- return do_last_fp(s, a, false);
22
-}
23
-
24
-static bool trans_LASTB_v(DisasContext *s, arg_rpr_esz *a)
25
-{
26
- return do_last_fp(s, a, true);
27
-}
28
+TRANS_FEAT(LASTA_v, aa64_sve, do_last_fp, a, false)
29
+TRANS_FEAT(LASTB_v, aa64_sve, do_last_fp, a, true)
30
31
/* Compute LAST for a Xreg. */
32
static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before)
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-65-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_last_general(DisasContext *s, arg_rpr_esz *a, bool before)
16
return true;
17
}
18
19
-static bool trans_LASTA_r(DisasContext *s, arg_rpr_esz *a)
20
-{
21
- return do_last_general(s, a, false);
22
-}
23
-
24
-static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a)
25
-{
26
- return do_last_general(s, a, true);
27
-}
28
+TRANS_FEAT(LASTA_r, aa64_sve, do_last_general, a, false)
29
+TRANS_FEAT(LASTB_r, aa64_sve, do_last_general, a, true)
30
31
static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a)
32
{
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-66-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 ++++-------------
9
1 file changed, 4 insertions(+), 13 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(REVH, aa64_sve, gen_gvec_ool_arg_zpz, revh_fns[a->esz], a, 0)
16
TRANS_FEAT(REVW, aa64_sve, gen_gvec_ool_arg_zpz,
17
a->esz == 3 ? gen_helper_sve_revw_d : NULL, a, 0)
18
19
-static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
20
-{
21
- return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
22
- a->rd, a->rn, a->rm, a->pg, a->esz);
23
-}
24
+TRANS_FEAT(SPLICE, aa64_sve, gen_gvec_ool_arg_zpzz,
25
+ gen_helper_sve_splice, a, a->esz)
26
27
-static bool trans_SPLICE_sve2(DisasContext *s, arg_rpr_esz *a)
28
-{
29
- if (!dc_isar_feature(aa64_sve2, s)) {
30
- return false;
31
- }
32
- return gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
33
- a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz);
34
-}
35
+TRANS_FEAT(SPLICE_sve2, aa64_sve2, gen_gvec_ool_zzzp, gen_helper_sve_splice,
36
+ a->rd, a->rn, (a->rn + 1) % 32, a->pg, a->esz)
37
38
/*
39
*** SVE Integer Compare - Vectors Group
40
--
41
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-67-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 28 ++++++++++++----------------
9
1 file changed, 12 insertions(+), 16 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
16
}
17
18
#define DO_PPZZ(NAME, name) \
19
-static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a) \
20
-{ \
21
- static gen_helper_gvec_flags_4 * const fns[4] = { \
22
- gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \
23
- gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \
24
- }; \
25
- return do_ppzz_flags(s, a, fns[a->esz]); \
26
-}
27
+ static gen_helper_gvec_flags_4 * const name##_ppzz_fns[4] = { \
28
+ gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \
29
+ gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \
30
+ }; \
31
+ TRANS_FEAT(NAME##_ppzz, aa64_sve, do_ppzz_flags, \
32
+ a, name##_ppzz_fns[a->esz])
33
34
DO_PPZZ(CMPEQ, cmpeq)
35
DO_PPZZ(CMPNE, cmpne)
36
@@ -XXX,XX +XXX,XX @@ DO_PPZZ(CMPHS, cmphs)
37
#undef DO_PPZZ
38
39
#define DO_PPZW(NAME, name) \
40
-static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a) \
41
-{ \
42
- static gen_helper_gvec_flags_4 * const fns[4] = { \
43
- gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \
44
- gen_helper_sve_##name##_ppzw_s, NULL \
45
- }; \
46
- return do_ppzz_flags(s, a, fns[a->esz]); \
47
-}
48
+ static gen_helper_gvec_flags_4 * const name##_ppzw_fns[4] = { \
49
+ gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \
50
+ gen_helper_sve_##name##_ppzw_s, NULL \
51
+ }; \
52
+ TRANS_FEAT(NAME##_ppzw, aa64_sve, do_ppzz_flags, \
53
+ a, name##_ppzw_fns[a->esz])
54
55
DO_PPZW(CMPEQ, cmpeq)
56
DO_PPZW(CMPNE, cmpne)
57
--
58
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-68-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 28 ++++++++--------------------
9
1 file changed, 8 insertions(+), 20 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZZZ_NARROW(SUBHNT, subhnt)
16
DO_SVE2_ZZZ_NARROW(RSUBHNB, rsubhnb)
17
DO_SVE2_ZZZ_NARROW(RSUBHNT, rsubhnt)
18
19
-static bool do_sve2_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
20
- gen_helper_gvec_flags_4 *fn)
21
-{
22
- if (!dc_isar_feature(aa64_sve2, s)) {
23
- return false;
24
- }
25
- return do_ppzz_flags(s, a, fn);
26
-}
27
+static gen_helper_gvec_flags_4 * const match_fns[4] = {
28
+ gen_helper_sve2_match_ppzz_b, gen_helper_sve2_match_ppzz_h, NULL, NULL
29
+};
30
+TRANS_FEAT(MATCH, aa64_sve2, do_ppzz_flags, a, match_fns[a->esz])
31
32
-#define DO_SVE2_PPZZ_MATCH(NAME, name) \
33
-static bool trans_##NAME(DisasContext *s, arg_rprr_esz *a) \
34
-{ \
35
- static gen_helper_gvec_flags_4 * const fns[4] = { \
36
- gen_helper_sve2_##name##_ppzz_b, gen_helper_sve2_##name##_ppzz_h, \
37
- NULL, NULL \
38
- }; \
39
- return do_sve2_ppzz_flags(s, a, fns[a->esz]); \
40
-}
41
-
42
-DO_SVE2_PPZZ_MATCH(MATCH, match)
43
-DO_SVE2_PPZZ_MATCH(NMATCH, nmatch)
44
+static gen_helper_gvec_flags_4 * const nmatch_fns[4] = {
45
+ gen_helper_sve2_nmatch_ppzz_b, gen_helper_sve2_nmatch_ppzz_h, NULL, NULL
46
+};
47
+TRANS_FEAT(NMATCH, aa64_sve2, do_ppzz_flags, a, nmatch_fns[a->esz])
48
49
static gen_helper_gvec_4 * const histcnt_fns[4] = {
50
NULL, NULL, gen_helper_sve2_histcnt_s, gen_helper_sve2_histcnt_d
51
--
52
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-69-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 8 +++-----
9
1 file changed, 3 insertions(+), 5 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_esz *a,
16
}
17
18
#define DO_PPZI(NAME, name) \
19
-static bool trans_##NAME##_ppzi(DisasContext *s, arg_rpri_esz *a) \
20
-{ \
21
- static gen_helper_gvec_flags_3 * const fns[4] = { \
22
+ static gen_helper_gvec_flags_3 * const name##_ppzi_fns[4] = { \
23
gen_helper_sve_##name##_ppzi_b, gen_helper_sve_##name##_ppzi_h, \
24
gen_helper_sve_##name##_ppzi_s, gen_helper_sve_##name##_ppzi_d, \
25
}; \
26
- return do_ppzi_flags(s, a, fns[a->esz]); \
27
-}
28
+ TRANS_FEAT(NAME##_ppzi, aa64_sve, do_ppzi_flags, a, \
29
+ name##_ppzi_fns[a->esz])
30
31
DO_PPZI(CMPEQ, cmpeq)
32
DO_PPZI(CMPNE, cmpne)
33
--
34
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-70-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 45 ++++++++++++--------------------------
9
1 file changed, 14 insertions(+), 31 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a,
16
return true;
17
}
18
19
-static bool trans_BRKPA(DisasContext *s, arg_rprr_s *a)
20
-{
21
- return do_brk3(s, a, gen_helper_sve_brkpa, gen_helper_sve_brkpas);
22
-}
23
+TRANS_FEAT(BRKPA, aa64_sve, do_brk3, a,
24
+ gen_helper_sve_brkpa, gen_helper_sve_brkpas)
25
+TRANS_FEAT(BRKPB, aa64_sve, do_brk3, a,
26
+ gen_helper_sve_brkpb, gen_helper_sve_brkpbs)
27
28
-static bool trans_BRKPB(DisasContext *s, arg_rprr_s *a)
29
-{
30
- return do_brk3(s, a, gen_helper_sve_brkpb, gen_helper_sve_brkpbs);
31
-}
32
+TRANS_FEAT(BRKA_m, aa64_sve, do_brk2, a,
33
+ gen_helper_sve_brka_m, gen_helper_sve_brkas_m)
34
+TRANS_FEAT(BRKB_m, aa64_sve, do_brk2, a,
35
+ gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m)
36
37
-static bool trans_BRKA_m(DisasContext *s, arg_rpr_s *a)
38
-{
39
- return do_brk2(s, a, gen_helper_sve_brka_m, gen_helper_sve_brkas_m);
40
-}
41
+TRANS_FEAT(BRKA_z, aa64_sve, do_brk2, a,
42
+ gen_helper_sve_brka_z, gen_helper_sve_brkas_z)
43
+TRANS_FEAT(BRKB_z, aa64_sve, do_brk2, a,
44
+ gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z)
45
46
-static bool trans_BRKB_m(DisasContext *s, arg_rpr_s *a)
47
-{
48
- return do_brk2(s, a, gen_helper_sve_brkb_m, gen_helper_sve_brkbs_m);
49
-}
50
-
51
-static bool trans_BRKA_z(DisasContext *s, arg_rpr_s *a)
52
-{
53
- return do_brk2(s, a, gen_helper_sve_brka_z, gen_helper_sve_brkas_z);
54
-}
55
-
56
-static bool trans_BRKB_z(DisasContext *s, arg_rpr_s *a)
57
-{
58
- return do_brk2(s, a, gen_helper_sve_brkb_z, gen_helper_sve_brkbs_z);
59
-}
60
-
61
-static bool trans_BRKN(DisasContext *s, arg_rpr_s *a)
62
-{
63
- return do_brk2(s, a, gen_helper_sve_brkn, gen_helper_sve_brkns);
64
-}
65
+TRANS_FEAT(BRKN, aa64_sve, do_brk2, a,
66
+ gen_helper_sve_brkn, gen_helper_sve_brkns)
67
68
/*
69
*** SVE Predicate Count Group
70
--
71
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-71-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 10 +---------
9
1 file changed, 1 insertion(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
16
return true;
17
}
18
19
-static bool trans_MUL_zzi(DisasContext *s, arg_rri_esz *a)
20
-{
21
- if (sve_access_check(s)) {
22
- unsigned vsz = vec_full_reg_size(s);
23
- tcg_gen_gvec_muli(a->esz, vec_full_reg_offset(s, a->rd),
24
- vec_full_reg_offset(s, a->rn), a->imm, vsz, vsz);
25
- }
26
- return true;
27
-}
28
+TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a)
29
30
static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
31
{
32
--
33
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the unparsed extraction in trans_DUP_i,
4
which is intended to reject an 8-bit shift of
5
an 8-bit constant for 8-bit element.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-72-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/sve.decode | 5 ++++-
13
target/arm/translate-sve.c | 10 ++++++----
14
2 files changed, 10 insertions(+), 5 deletions(-)
15
16
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve.decode
19
+++ b/target/arm/sve.decode
20
@@ -XXX,XX +XXX,XX @@ WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4
21
FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
22
23
# SVE broadcast integer immediate (unpredicated)
24
-DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
25
+{
26
+ INVALID 00100101 00 111 00 011 1 -------- -----
27
+ DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
28
+}
29
30
# SVE integer add/subtract immediate (unpredicated)
31
ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
32
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/translate-sve.c
35
+++ b/target/arm/translate-sve.c
36
@@ -XXX,XX +XXX,XX @@ const uint64_t pred_esz_masks[4] = {
37
0x1111111111111111ull, 0x0101010101010101ull
38
};
39
40
+static bool trans_INVALID(DisasContext *s, arg_INVALID *a)
41
+{
42
+ unallocated_encoding(s);
43
+ return true;
44
+}
45
+
46
/*
47
*** SVE Logical - Unpredicated Group
48
*/
49
@@ -XXX,XX +XXX,XX @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a)
50
51
static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
52
{
53
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
54
- return false;
55
- }
56
if (sve_access_check(s)) {
57
unsigned vsz = vec_full_reg_size(s);
58
int dofs = vec_full_reg_offset(s, a->rd);
59
-
60
tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm);
61
}
62
return true;
63
--
64
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the unparsed extractions in trans_ADD_zzi, trans_SUBR_zzi,
4
and do_zzi_sat which are intended to reject an 8-bit shift of an
5
8-bit constant for 8-bit element.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-73-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/sve.decode | 35 ++++++++++++++++++++++++++++-------
13
target/arm/translate-sve.c | 9 ---------
14
2 files changed, 28 insertions(+), 16 deletions(-)
15
16
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/sve.decode
19
+++ b/target/arm/sve.decode
20
@@ -XXX,XX +XXX,XX @@ FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
21
}
22
23
# SVE integer add/subtract immediate (unpredicated)
24
-ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
25
-SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
26
-SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
27
-SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
28
-UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
29
-SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
30
-UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
31
+{
32
+ INVALID 00100101 00 100 000 11 1 -------- -----
33
+ ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
34
+}
35
+{
36
+ INVALID 00100101 00 100 001 11 1 -------- -----
37
+ SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
38
+}
39
+{
40
+ INVALID 00100101 00 100 011 11 1 -------- -----
41
+ SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
42
+}
43
+{
44
+ INVALID 00100101 00 100 100 11 1 -------- -----
45
+ SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
46
+}
47
+{
48
+ INVALID 00100101 00 100 101 11 1 -------- -----
49
+ UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
50
+}
51
+{
52
+ INVALID 00100101 00 100 110 11 1 -------- -----
53
+ SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
54
+}
55
+{
56
+ INVALID 00100101 00 100 111 11 1 -------- -----
57
+ UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
58
+}
59
60
# SVE integer min/max immediate (unpredicated)
61
SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
62
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
63
index XXXXXXX..XXXXXXX 100644
64
--- a/target/arm/translate-sve.c
65
+++ b/target/arm/translate-sve.c
66
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
67
68
static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
69
{
70
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
71
- return false;
72
- }
73
return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
74
}
75
76
@@ -XXX,XX +XXX,XX @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz *a)
77
.scalar_first = true }
78
};
79
80
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
81
- return false;
82
- }
83
if (sve_access_check(s)) {
84
unsigned vsz = vec_full_reg_size(s);
85
tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd),
86
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_muli, a)
87
88
static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
89
{
90
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
91
- return false;
92
- }
93
if (sve_access_check(s)) {
94
do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
95
tcg_constant_i64(a->imm), u, d);
96
--
97
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Remove the unparsed extractions in trans_CPY_{m,z}_i which are intended
4
to reject an 8-bit shift of an 8-bit constant for 8-bit element.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-74-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/sve.decode | 10 ++++++++--
12
target/arm/translate-sve.c | 6 ------
13
2 files changed, 8 insertions(+), 8 deletions(-)
14
15
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/sve.decode
18
+++ b/target/arm/sve.decode
19
@@ -XXX,XX +XXX,XX @@ DUPM 00000101 11 0000 dbm:13 rd:5
20
FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
21
22
# SVE copy integer immediate (predicated)
23
-CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
24
-CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
25
+{
26
+ INVALID 00000101 00 01 ---- 01 1 -------- -----
27
+ CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
28
+}
29
+{
30
+ INVALID 00000101 00 01 ---- 00 1 -------- -----
31
+ CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
32
+}
33
34
### SVE Permute - Extract Group
35
36
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/translate-sve.c
39
+++ b/target/arm/translate-sve.c
40
@@ -XXX,XX +XXX,XX @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a)
41
42
static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a)
43
{
44
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
45
- return false;
46
- }
47
if (sve_access_check(s)) {
48
do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm));
49
}
50
@@ -XXX,XX +XXX,XX @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a)
51
gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d,
52
};
53
54
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
55
- return false;
56
- }
57
if (sve_access_check(s)) {
58
unsigned vsz = vec_full_reg_size(s);
59
tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd),
60
--
61
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-75-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 5 +----
9
1 file changed, 1 insertion(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
16
return true;
17
}
18
19
-static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
20
-{
21
- return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
22
-}
23
+TRANS_FEAT(ADD_zzi, aa64_sve, gen_gvec_fn_arg_zzi, tcg_gen_gvec_addi, a)
24
25
static bool trans_SUB_zzi(DisasContext *s, arg_rri_esz *a)
26
{
27
--
28
2.25.1
diff view generated by jsdifflib
1
We were accidentally permitting decode of Thumb Neon insns even if
1
From: Richard Henderson <richard.henderson@linaro.org>
2
the CPU didn't have the FEATURE_NEON bit set, because the feature
3
check was being done before the call to disas_neon_data_insn() and
4
disas_neon_ls_insn() in the Arm decoder but was omitted from the
5
Thumb decoder. Push the feature bit check down into the called
6
functions so it is done for both Arm and Thumb encodings.
7
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-76-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20200430181003.21682-3-peter.maydell@linaro.org
12
---
7
---
13
target/arm/translate.c | 16 ++++++++--------
8
target/arm/translate-sve.c | 23 ++++-------------------
14
1 file changed, 8 insertions(+), 8 deletions(-)
9
1 file changed, 4 insertions(+), 19 deletions(-)
15
10
16
diff --git a/target/arm/translate.c b/target/arm/translate.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate.c
13
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/translate.c
14
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
15
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
21
TCGv_i32 tmp2;
16
return true;
22
TCGv_i64 tmp64;
17
}
23
18
24
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
19
-static bool trans_SQADD_zzi(DisasContext *s, arg_rri_esz *a)
25
+ return 1;
20
-{
26
+ }
21
- return do_zzi_sat(s, a, false, false);
27
+
22
-}
28
/* FIXME: this access check should not take precedence over UNDEF
29
* for invalid encodings; we will generate incorrect syndrome information
30
* for attempts to execute invalid vfp/neon encodings with FP disabled.
31
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
32
TCGv_ptr ptr1, ptr2, ptr3;
33
TCGv_i64 tmp64;
34
35
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
36
+ return 1;
37
+ }
38
+
39
/* FIXME: this access check should not take precedence over UNDEF
40
* for invalid encodings; we will generate incorrect syndrome information
41
* for attempts to execute invalid vfp/neon encodings with FP disabled.
42
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
43
44
if (((insn >> 25) & 7) == 1) {
45
/* NEON Data processing. */
46
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
47
- goto illegal_op;
48
- }
49
-
23
-
50
if (disas_neon_data_insn(s, insn)) {
24
-static bool trans_UQADD_zzi(DisasContext *s, arg_rri_esz *a)
51
goto illegal_op;
25
-{
52
}
26
- return do_zzi_sat(s, a, true, false);
53
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
27
-}
54
}
55
if ((insn & 0x0f100000) == 0x04000000) {
56
/* NEON load/store. */
57
- if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
58
- goto illegal_op;
59
- }
60
-
28
-
61
if (disas_neon_ls_insn(s, insn)) {
29
-static bool trans_SQSUB_zzi(DisasContext *s, arg_rri_esz *a)
62
goto illegal_op;
30
-{
63
}
31
- return do_zzi_sat(s, a, false, true);
32
-}
33
-
34
-static bool trans_UQSUB_zzi(DisasContext *s, arg_rri_esz *a)
35
-{
36
- return do_zzi_sat(s, a, true, true);
37
-}
38
+TRANS_FEAT(SQADD_zzi, aa64_sve, do_zzi_sat, a, false, false)
39
+TRANS_FEAT(UQADD_zzi, aa64_sve, do_zzi_sat, a, true, false)
40
+TRANS_FEAT(SQSUB_zzi, aa64_sve, do_zzi_sat, a, false, true)
41
+TRANS_FEAT(UQSUB_zzi, aa64_sve, do_zzi_sat, a, true, true)
42
43
static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
44
{
64
--
45
--
65
2.20.1
46
2.25.1
66
67
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-77-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 7 ++-----
9
1 file changed, 2 insertions(+), 5 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz *a, gen_helper_gvec_2i *fn)
16
}
17
18
#define DO_ZZI(NAME, name) \
19
-static bool trans_##NAME##_zzi(DisasContext *s, arg_rri_esz *a) \
20
-{ \
21
- static gen_helper_gvec_2i * const fns[4] = { \
22
+ static gen_helper_gvec_2i * const name##i_fns[4] = { \
23
gen_helper_sve_##name##i_b, gen_helper_sve_##name##i_h, \
24
gen_helper_sve_##name##i_s, gen_helper_sve_##name##i_d, \
25
}; \
26
- return do_zzi_ool(s, a, fns[a->esz]); \
27
-}
28
+ TRANS_FEAT(NAME##_zzi, aa64_sve, do_zzi_ool, a, name##i_fns[a->esz])
29
30
DO_ZZI(SMAX, smax)
31
DO_ZZI(UMAX, umax)
32
--
33
2.25.1
diff view generated by jsdifflib
1
Convert the V[US]DOT (vector) insns to decodetree.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use these for the several varieties of floating-point
4
multiply-add instructions.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-78-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200430181003.21682-7-peter.maydell@linaro.org
6
---
10
---
7
target/arm/neon-shared.decode | 4 ++++
11
target/arm/translate-sve.c | 140 ++++++++++++++-----------------------
8
target/arm/translate-neon.inc.c | 32 ++++++++++++++++++++++++++++++++
12
1 file changed, 53 insertions(+), 87 deletions(-)
9
target/arm/translate.c | 9 +--------
10
3 files changed, 37 insertions(+), 8 deletions(-)
11
13
12
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/neon-shared.decode
16
--- a/target/arm/translate-sve.c
15
+++ b/target/arm/neon-shared.decode
17
+++ b/target/arm/translate-sve.c
16
@@ -XXX,XX +XXX,XX @@ VCMLA 1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzxz(DisasContext *s, gen_helper_gvec_4 *fn,
17
19
return gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->index);
18
VCADD 1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
20
}
19
vm=%vm_dp vn=%vn_dp vd=%vd_dp
21
20
+
22
+/* Invoke an out-of-line helper on 4 Zregs, plus a pointer. */
21
+# VUDOT and VSDOT
23
+static bool gen_gvec_ptr_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn,
22
+VDOT 1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
24
+ int rd, int rn, int rm, int ra,
23
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp
25
+ int data, TCGv_ptr ptr)
24
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/target/arm/translate-neon.inc.c
27
+++ b/target/arm/translate-neon.inc.c
28
@@ -XXX,XX +XXX,XX @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
29
tcg_temp_free_ptr(fpst);
30
return true;
31
}
32
+
33
+static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
34
+{
26
+{
35
+ int opr_sz;
27
+ if (fn == NULL) {
36
+ gen_helper_gvec_3 *fn_gvec;
37
+
38
+ if (!dc_isar_feature(aa32_dp, s)) {
39
+ return false;
28
+ return false;
40
+ }
29
+ }
41
+
30
+ if (sve_access_check(s)) {
42
+ /* UNDEF accesses to D16-D31 if they don't exist. */
31
+ unsigned vsz = vec_full_reg_size(s);
43
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
32
+ tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, rd),
44
+ ((a->vd | a->vn | a->vm) & 0x10)) {
33
+ vec_full_reg_offset(s, rn),
45
+ return false;
34
+ vec_full_reg_offset(s, rm),
35
+ vec_full_reg_offset(s, ra),
36
+ ptr, vsz, vsz, data, fn);
46
+ }
37
+ }
47
+
48
+ if ((a->vn | a->vm | a->vd) & a->q) {
49
+ return false;
50
+ }
51
+
52
+ if (!vfp_access_check(s)) {
53
+ return true;
54
+ }
55
+
56
+ opr_sz = (1 + a->q) * 8;
57
+ fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
58
+ tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
59
+ vfp_reg_offset(1, a->vn),
60
+ vfp_reg_offset(1, a->vm),
61
+ opr_sz, opr_sz, 0, fn_gvec);
62
+ return true;
38
+ return true;
63
+}
39
+}
64
diff --git a/target/arm/translate.c b/target/arm/translate.c
40
+
65
index XXXXXXX..XXXXXXX 100644
41
+static bool gen_gvec_fpst_zzzz(DisasContext *s, gen_helper_gvec_4_ptr *fn,
66
--- a/target/arm/translate.c
42
+ int rd, int rn, int rm, int ra,
67
+++ b/target/arm/translate.c
43
+ int data, ARMFPStatusFlavour flavour)
68
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
44
+{
69
bool is_long = false, q = extract32(insn, 6, 1);
45
+ TCGv_ptr status = fpstatus_ptr(flavour);
70
bool ptr_is_env = false;
46
+ bool ret = gen_gvec_ptr_zzzz(s, fn, rd, rn, rm, ra, data, status);
71
47
+ tcg_temp_free_ptr(status);
72
- if ((insn & 0xfeb00f00) == 0xfc200d00) {
48
+ return ret;
73
- /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
49
+}
74
- bool u = extract32(insn, 4, 1);
50
+
75
- if (!dc_isar_feature(aa32_dp, s)) {
51
/* Invoke an out-of-line helper on 2 Zregs and a predicate. */
76
- return 1;
52
static bool gen_gvec_ool_zzp(DisasContext *s, gen_helper_gvec_3 *fn,
77
- }
53
int rd, int rn, int pg, int data)
78
- fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
54
@@ -XXX,XX +XXX,XX @@ DO_SVE2_RRXR_ROT(CDOT_zzxw_d, gen_helper_sve2_cdot_idx_d)
79
- } else if ((insn & 0xff300f10) == 0xfc200810) {
55
80
+ if ((insn & 0xff300f10) == 0xfc200810) {
56
static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub)
81
/* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
57
{
82
int is_s = extract32(insn, 23, 1);
58
- static gen_helper_gvec_4_ptr * const fns[3] = {
83
if (!dc_isar_feature(aa32_fhm, s)) {
59
+ static gen_helper_gvec_4_ptr * const fns[4] = {
60
+ NULL,
61
gen_helper_gvec_fmla_idx_h,
62
gen_helper_gvec_fmla_idx_s,
63
gen_helper_gvec_fmla_idx_d,
64
};
65
-
66
- if (sve_access_check(s)) {
67
- unsigned vsz = vec_full_reg_size(s);
68
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
69
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
70
- vec_full_reg_offset(s, a->rn),
71
- vec_full_reg_offset(s, a->rm),
72
- vec_full_reg_offset(s, a->ra),
73
- status, vsz, vsz, (a->index << 1) | sub,
74
- fns[a->esz - 1]);
75
- tcg_temp_free_ptr(status);
76
- }
77
- return true;
78
+ return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
79
+ (a->index << 1) | sub,
80
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
81
}
82
83
static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a)
84
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zpzzz(DisasContext *s, arg_FCMLA_zpzzz *a)
85
86
static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)
87
{
88
- static gen_helper_gvec_4_ptr * const fns[2] = {
89
+ static gen_helper_gvec_4_ptr * const fns[4] = {
90
+ NULL,
91
gen_helper_gvec_fcmlah_idx,
92
gen_helper_gvec_fcmlas_idx,
93
+ NULL,
94
};
95
96
- tcg_debug_assert(a->esz == 1 || a->esz == 2);
97
tcg_debug_assert(a->rd == a->ra);
98
- if (sve_access_check(s)) {
99
- unsigned vsz = vec_full_reg_size(s);
100
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
101
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
102
- vec_full_reg_offset(s, a->rn),
103
- vec_full_reg_offset(s, a->rm),
104
- vec_full_reg_offset(s, a->ra),
105
- status, vsz, vsz,
106
- a->index * 4 + a->rot,
107
- fns[a->esz - 1]);
108
- tcg_temp_free_ptr(status);
109
- }
110
- return true;
111
+
112
+ return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
113
+ a->index * 4 + a->rot,
114
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
115
}
116
117
/*
118
@@ -XXX,XX +XXX,XX @@ static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a)
119
return false;
120
}
121
122
- if (sve_access_check(s)) {
123
- unsigned vsz = vec_full_reg_size(s);
124
- TCGv_ptr status = fpstatus_ptr(FPST_FPCR);
125
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
126
- vec_full_reg_offset(s, a->rn),
127
- vec_full_reg_offset(s, a->rm),
128
- vec_full_reg_offset(s, a->ra),
129
- status, vsz, vsz, 0, fn);
130
- tcg_temp_free_ptr(status);
131
- }
132
- return true;
133
+ return gen_gvec_fpst_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR);
134
}
135
136
static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
137
@@ -XXX,XX +XXX,XX @@ static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
138
if (!dc_isar_feature(aa64_sve2, s)) {
139
return false;
140
}
141
- if (sve_access_check(s)) {
142
- unsigned vsz = vec_full_reg_size(s);
143
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
144
- vec_full_reg_offset(s, a->rn),
145
- vec_full_reg_offset(s, a->rm),
146
- vec_full_reg_offset(s, a->ra),
147
- cpu_env, vsz, vsz, (sel << 1) | sub,
148
- gen_helper_sve2_fmlal_zzzw_s);
149
- }
150
- return true;
151
+ return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzzw_s,
152
+ a->rd, a->rn, a->rm, a->ra,
153
+ (sel << 1) | sub, cpu_env);
154
}
155
156
static bool trans_FMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
157
@@ -XXX,XX +XXX,XX @@ static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sub, bool sel)
158
if (!dc_isar_feature(aa64_sve2, s)) {
159
return false;
160
}
161
- if (sve_access_check(s)) {
162
- unsigned vsz = vec_full_reg_size(s);
163
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
164
- vec_full_reg_offset(s, a->rn),
165
- vec_full_reg_offset(s, a->rm),
166
- vec_full_reg_offset(s, a->ra),
167
- cpu_env, vsz, vsz,
168
- (a->index << 2) | (sel << 1) | sub,
169
- gen_helper_sve2_fmlal_zzxw_s);
170
- }
171
- return true;
172
+ return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzxw_s,
173
+ a->rd, a->rn, a->rm, a->ra,
174
+ (a->index << 2) | (sel << 1) | sub, cpu_env);
175
}
176
177
static bool trans_FMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a)
178
@@ -XXX,XX +XXX,XX @@ static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
179
if (!dc_isar_feature(aa64_sve_bf16, s)) {
180
return false;
181
}
182
- if (sve_access_check(s)) {
183
- TCGv_ptr status = fpstatus_ptr(FPST_FPCR);
184
- unsigned vsz = vec_full_reg_size(s);
185
-
186
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
187
- vec_full_reg_offset(s, a->rn),
188
- vec_full_reg_offset(s, a->rm),
189
- vec_full_reg_offset(s, a->ra),
190
- status, vsz, vsz, sel,
191
- gen_helper_gvec_bfmlal);
192
- tcg_temp_free_ptr(status);
193
- }
194
- return true;
195
+ return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal,
196
+ a->rd, a->rn, a->rm, a->ra, sel, FPST_FPCR);
197
}
198
199
static bool trans_BFMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
200
@@ -XXX,XX +XXX,XX @@ static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
201
if (!dc_isar_feature(aa64_sve_bf16, s)) {
202
return false;
203
}
204
- if (sve_access_check(s)) {
205
- TCGv_ptr status = fpstatus_ptr(FPST_FPCR);
206
- unsigned vsz = vec_full_reg_size(s);
207
-
208
- tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd),
209
- vec_full_reg_offset(s, a->rn),
210
- vec_full_reg_offset(s, a->rm),
211
- vec_full_reg_offset(s, a->ra),
212
- status, vsz, vsz, (a->index << 1) | sel,
213
- gen_helper_gvec_bfmlal_idx);
214
- tcg_temp_free_ptr(status);
215
- }
216
- return true;
217
+ return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx,
218
+ a->rd, a->rn, a->rm, a->ra,
219
+ (a->index << 1) | sel, FPST_FPCR);
220
}
221
222
static bool trans_BFMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a)
84
--
223
--
85
2.20.1
224
2.25.1
86
87
diff view generated by jsdifflib
1
Somewhere along theline we accidentally added a duplicate
1
From: Richard Henderson <richard.henderson@linaro.org>
2
"using D16-D31 when they don't exist" check to do_vfm_dp()
3
(probably an artifact of a patchseries rebase). Remove it.
4
2
3
Being able to specify the feature predicate in TRANS_FEAT
4
makes it easier to split trans_FMMLA by element size,
5
which also happens to simplify the decode.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-79-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200430181003.21682-2-peter.maydell@linaro.org
9
---
11
---
10
target/arm/translate-vfp.inc.c | 6 ------
12
target/arm/sve.decode | 7 +++----
11
1 file changed, 6 deletions(-)
13
target/arm/translate-sve.c | 27 ++++-----------------------
14
2 files changed, 7 insertions(+), 27 deletions(-)
12
15
13
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
16
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-vfp.inc.c
18
--- a/target/arm/sve.decode
16
+++ b/target/arm/translate-vfp.inc.c
19
+++ b/target/arm/sve.decode
17
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
20
@@ -XXX,XX +XXX,XX @@ SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx
18
return false;
21
USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm
19
}
22
20
23
### SVE2 floating point matrix multiply accumulate
21
- /* UNDEF accesses to D16-D31 if they don't exist. */
24
-{
22
- if (!dc_isar_feature(aa32_simd_r32, s) &&
25
- BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
23
- ((a->vd | a->vn | a->vm) & 0x10)) {
26
- FMMLA 01100100 .. 1 ..... 111 001 ..... ..... @rda_rn_rm
27
-}
28
+BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
29
+FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
30
+FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_e0
31
32
### SVE2 Memory Gather Load Group
33
34
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/translate-sve.c
37
+++ b/target/arm/translate-sve.c
38
@@ -XXX,XX +XXX,XX @@ DO_SVE2_ZPZZ_FP(FMINP, fminp)
39
* SVE Integer Multiply-Add (unpredicated)
40
*/
41
42
-static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a)
43
-{
44
- gen_helper_gvec_4_ptr *fn;
45
-
46
- switch (a->esz) {
47
- case MO_32:
48
- if (!dc_isar_feature(aa64_sve_f32mm, s)) {
49
- return false;
50
- }
51
- fn = gen_helper_fmmla_s;
52
- break;
53
- case MO_64:
54
- if (!dc_isar_feature(aa64_sve_f64mm, s)) {
55
- return false;
56
- }
57
- fn = gen_helper_fmmla_d;
58
- break;
59
- default:
24
- return false;
60
- return false;
25
- }
61
- }
26
-
62
-
27
if (!vfp_access_check(s)) {
63
- return gen_gvec_fpst_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR);
28
return true;
64
-}
29
}
65
+TRANS_FEAT(FMMLA_s, aa64_sve_f32mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_s,
66
+ a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
67
+TRANS_FEAT(FMMLA_d, aa64_sve_f64mm, gen_gvec_fpst_zzzz, gen_helper_fmmla_d,
68
+ a->rd, a->rn, a->rm, a->ra, 0, FPST_FPCR)
69
70
static gen_helper_gvec_4 * const sqdmlal_zzzw_fns[] = {
71
NULL, gen_helper_sve2_sqdmlal_zzzw_h,
30
--
72
--
31
2.20.1
73
2.25.1
32
33
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Embed the UARTs into the SoC type.
3
Combined with the check already present in gen_mov_p,
4
we can simplify some special cases in trans_AND_pppp
5
and trans_BIC_pppp.
4
6
5
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Message-id: 20220527181907.189259-80-richard.henderson@linaro.org
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
10
Message-id: 20200427181649.26851-5-edgar.iglesias@gmail.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
include/hw/arm/xlnx-versal.h | 3 ++-
12
target/arm/translate-sve.c | 30 ++++++++++++------------------
14
hw/arm/xlnx-versal.c | 12 ++++++------
13
1 file changed, 12 insertions(+), 18 deletions(-)
15
2 files changed, 8 insertions(+), 7 deletions(-)
16
14
17
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/xlnx-versal.h
17
--- a/target/arm/translate-sve.c
20
+++ b/include/hw/arm/xlnx-versal.h
18
+++ b/target/arm/translate-sve.c
21
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word)
22
#include "hw/sysbus.h"
20
}
23
#include "hw/arm/boot.h"
21
24
#include "hw/intc/arm_gicv3.h"
22
/* Invoke a vector expander on three Pregs. */
25
+#include "hw/char/pl011.h"
23
-static void gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
26
24
+static bool gen_gvec_fn_ppp(DisasContext *s, GVecGen3Fn *gvec_fn,
27
#define TYPE_XLNX_VERSAL "xlnx-versal"
25
int rd, int rn, int rm)
28
#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
26
{
29
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
27
- unsigned psz = pred_gvec_reg_size(s);
30
MemoryRegion mr_ocm;
28
- gvec_fn(MO_64, pred_full_reg_offset(s, rd),
31
29
- pred_full_reg_offset(s, rn),
32
struct {
30
- pred_full_reg_offset(s, rm), psz, psz);
33
- SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
31
+ if (sve_access_check(s)) {
34
+ PL011State uart[XLNX_VERSAL_NR_UARTS];
32
+ unsigned psz = pred_gvec_reg_size(s);
35
SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
33
+ gvec_fn(MO_64, pred_full_reg_offset(s, rd),
36
SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
34
+ pred_full_reg_offset(s, rn),
37
} iou;
35
+ pred_full_reg_offset(s, rm), psz, psz);
38
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
36
+ }
39
index XXXXXXX..XXXXXXX 100644
37
+ return true;
40
--- a/hw/arm/xlnx-versal.c
38
}
41
+++ b/hw/arm/xlnx-versal.c
39
42
@@ -XXX,XX +XXX,XX @@
40
/* Invoke a vector move on two Pregs. */
43
#include "kvm_arm.h"
41
@@ -XXX,XX +XXX,XX @@ static bool trans_AND_pppp(DisasContext *s, arg_rprr_s *a)
44
#include "hw/misc/unimp.h"
42
};
45
#include "hw/arm/xlnx-versal.h"
43
46
-#include "hw/char/pl011.h"
44
if (!a->s) {
47
45
- if (!sve_access_check(s)) {
48
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
46
- return true;
49
#define GEM_REVISION 0x40070106
47
- }
50
@@ -XXX,XX +XXX,XX @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
48
if (a->rn == a->rm) {
51
DeviceState *dev;
49
if (a->pg == a->rn) {
52
MemoryRegion *mr;
50
- do_mov_p(s, a->rd, a->rn);
53
51
- } else {
54
- dev = qdev_create(NULL, TYPE_PL011);
52
- gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
55
- s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);
53
+ return do_mov_p(s, a->rd, a->rn);
56
+ sysbus_init_child_obj(OBJECT(s), name,
54
}
57
+ &s->lpd.iou.uart[i], sizeof(s->lpd.iou.uart[i]),
55
- return true;
58
+ TYPE_PL011);
56
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->pg);
59
+ dev = DEVICE(&s->lpd.iou.uart[i]);
57
} else if (a->pg == a->rn || a->pg == a->rm) {
60
qdev_prop_set_chr(dev, "chardev", serial_hd(i));
58
- gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
61
- object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
59
- return true;
62
qdev_init_nofail(dev);
60
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_and, a->rd, a->rn, a->rm);
63
61
}
64
- mr = sysbus_mmio_get_region(s->lpd.iou.uart[i], 0);
65
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
66
memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
67
68
- sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]);
69
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
70
g_free(name);
71
}
62
}
63
return do_pppp_flags(s, a, &op);
64
@@ -XXX,XX +XXX,XX @@ static bool trans_BIC_pppp(DisasContext *s, arg_rprr_s *a)
65
};
66
67
if (!a->s && a->pg == a->rn) {
68
- if (sve_access_check(s)) {
69
- gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
70
- }
71
- return true;
72
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->rn, a->rm);
73
}
74
return do_pppp_flags(s, a, &op);
72
}
75
}
73
--
76
--
74
2.20.1
77
2.25.1
75
76
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Remove inclusion of arm_gicv3_common.h, this already gets
3
This alias is defined on EOR (prediates). While the
4
included via xlnx-versal.h.
4
same operation could be performed with NAND or NOR,
5
only bother with the official alias.
5
6
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20220527181907.189259-81-richard.henderson@linaro.org
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20200427181649.26851-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
hw/arm/xlnx-versal.c | 1 -
12
target/arm/translate-sve.c | 5 +++++
13
1 file changed, 1 deletion(-)
13
1 file changed, 5 insertions(+)
14
14
15
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-versal.c
17
--- a/target/arm/translate-sve.c
18
+++ b/hw/arm/xlnx-versal.c
18
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a)
20
#include "hw/arm/boot.h"
20
.fno = gen_helper_sve_eor_pppp,
21
#include "kvm_arm.h"
21
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
22
#include "hw/misc/unimp.h"
22
};
23
-#include "hw/intc/arm_gicv3_common.h"
23
+
24
#include "hw/arm/xlnx-versal.h"
24
+ /* Alias NOT (predicate) is EOR Pd.B, Pg/Z, Pn.B, Pg.B */
25
#include "hw/char/pl011.h"
25
+ if (!a->s && a->pg == a->rm) {
26
+ return gen_gvec_fn_ppp(s, tcg_gen_gvec_andc, a->rd, a->pg, a->rn);
27
+ }
28
return do_pppp_flags(s, a, &op);
29
}
26
30
27
--
31
--
28
2.20.1
32
2.25.1
29
30
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-82-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 5 +----
9
1 file changed, 1 insertion(+), 4 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_4 * const udiv_fns[4] = {
16
};
17
TRANS_FEAT(UDIV_zpzz, aa64_sve, gen_gvec_ool_arg_zpzz, udiv_fns[a->esz], a, 0)
18
19
-static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a)
20
-{
21
- return do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
22
-}
23
+TRANS_FEAT(SEL_zpzz, aa64_sve, do_sel_z, a->rd, a->rn, a->rm, a->pg, a->esz)
24
25
/*
26
*** SVE Integer Arithmetic - Unary Predicated Group
27
--
28
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-83-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 17 +++--------------
9
1 file changed, 3 insertions(+), 14 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a)
16
* In the meantime, just emit the moves.
17
*/
18
19
-static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a)
20
-{
21
- return do_mov_z(s, a->rd, a->rn);
22
-}
23
-
24
-static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a)
25
-{
26
- return do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
27
-}
28
-
29
-static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a)
30
-{
31
- return do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz, false);
32
-}
33
+TRANS_FEAT(MOVPRFX, aa64_sve, do_mov_z, a->rd, a->rn)
34
+TRANS_FEAT(MOVPRFX_m, aa64_sve, do_sel_z, a->rd, a->rn, a->rd, a->pg, a->esz)
35
+TRANS_FEAT(MOVPRFX_z, aa64_sve, do_movz_zpz, a->rd, a->rn, a->pg, a->esz, false)
36
37
/*
38
* SVE2 Integer Multiply - Unpredicated
39
--
40
2.25.1
diff view generated by jsdifflib
New patch
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-84-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 11 ++---------
9
1 file changed, 2 insertions(+), 9 deletions(-)
10
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-sve.c
14
+++ b/target/arm/translate-sve.c
15
@@ -XXX,XX +XXX,XX @@ static bool do_FMLA_zzxz(DisasContext *s, arg_rrxr_esz *a, bool sub)
16
a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
17
}
18
19
-static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a)
20
-{
21
- return do_FMLA_zzxz(s, a, false);
22
-}
23
-
24
-static bool trans_FMLS_zzxz(DisasContext *s, arg_FMLA_zzxz *a)
25
-{
26
- return do_FMLA_zzxz(s, a, true);
27
-}
28
+TRANS_FEAT(FMLA_zzxz, aa64_sve, do_FMLA_zzxz, a, false)
29
+TRANS_FEAT(FMLS_zzxz, aa64_sve, do_FMLA_zzxz, a, true)
30
31
/*
32
*** SVE Floating Point Multiply Indexed Group
33
--
34
2.25.1
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Fix typo xlnx-ve -> xlnx-versal.
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
4
Message-id: 20220527181907.189259-85-richard.henderson@linaro.org
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20200427181649.26851-4-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
7
---
12
hw/arm/xlnx-versal-virt.c | 2 +-
8
target/arm/translate-sve.c | 28 ++++------------------------
13
1 file changed, 1 insertion(+), 1 deletion(-)
9
1 file changed, 4 insertions(+), 24 deletions(-)
14
10
15
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-versal-virt.c
13
--- a/target/arm/translate-sve.c
18
+++ b/hw/arm/xlnx-versal-virt.c
14
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(BFMMLA, aa64_sve_bf16, gen_gvec_ool_arg_zzzz,
20
psci_conduit = QEMU_PSCI_CONDUIT_SMC;
16
21
}
17
static bool do_BFMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel)
22
18
{
23
- sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
19
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
24
+ sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc,
20
- return false;
25
sizeof(s->soc), TYPE_XLNX_VERSAL);
21
- }
26
object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
22
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal,
27
"ddr", &error_abort);
23
a->rd, a->rn, a->rm, a->ra, sel, FPST_FPCR);
24
}
25
26
-static bool trans_BFMLALB_zzzw(DisasContext *s, arg_rrrr_esz *a)
27
-{
28
- return do_BFMLAL_zzzw(s, a, false);
29
-}
30
-
31
-static bool trans_BFMLALT_zzzw(DisasContext *s, arg_rrrr_esz *a)
32
-{
33
- return do_BFMLAL_zzzw(s, a, true);
34
-}
35
+TRANS_FEAT(BFMLALB_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, false)
36
+TRANS_FEAT(BFMLALT_zzzw, aa64_sve_bf16, do_BFMLAL_zzzw, a, true)
37
38
static bool do_BFMLAL_zzxw(DisasContext *s, arg_rrxr_esz *a, bool sel)
39
{
40
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
41
- return false;
42
- }
43
return gen_gvec_fpst_zzzz(s, gen_helper_gvec_bfmlal_idx,
44
a->rd, a->rn, a->rm, a->ra,
45
(a->index << 1) | sel, FPST_FPCR);
46
}
47
48
-static bool trans_BFMLALB_zzxw(DisasContext *s, arg_rrxr_esz *a)
49
-{
50
- return do_BFMLAL_zzxw(s, a, false);
51
-}
52
-
53
-static bool trans_BFMLALT_zzxw(DisasContext *s, arg_rrxr_esz *a)
54
-{
55
- return do_BFMLAL_zzxw(s, a, true);
56
-}
57
+TRANS_FEAT(BFMLALB_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, false)
58
+TRANS_FEAT(BFMLALT_zzxw, aa64_sve_bf16, do_BFMLAL_zzxw, a, true)
28
--
59
--
29
2.20.1
60
2.25.1
30
31
diff view generated by jsdifflib
1
Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
1
From: Richard Henderson <richard.henderson@linaro.org>
2
3-reg-same grouping to decodetree.
3
2
3
Rename the function to match gen_gvec_ool_arg_zzz,
4
and move to be adjacent. Split out gen_gvec_fpst_zzz
5
as a helper while we're at it.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-86-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200430181003.21682-20-peter.maydell@linaro.org
7
---
11
---
8
target/arm/neon-dp.decode | 9 +++++++
12
target/arm/translate-sve.c | 50 +++++++++++++++++++++++---------------
9
target/arm/translate-neon.inc.c | 44 +++++++++++++++++++++++++++++++++
13
1 file changed, 30 insertions(+), 20 deletions(-)
10
target/arm/translate.c | 28 +++------------------
11
3 files changed, 56 insertions(+), 25 deletions(-)
12
14
13
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-dp.decode
17
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/neon-dp.decode
18
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
18
VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
20
return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data);
19
VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
21
}
20
22
21
+VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same
23
+/* Invoke an out-of-line helper on 3 Zregs, plus float_status. */
22
+VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same
24
+static bool gen_gvec_fpst_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
25
+ int rd, int rn, int rm,
26
+ int data, ARMFPStatusFlavour flavour)
27
+{
28
+ if (fn == NULL) {
29
+ return false;
30
+ }
31
+ if (sve_access_check(s)) {
32
+ unsigned vsz = vec_full_reg_size(s);
33
+ TCGv_ptr status = fpstatus_ptr(flavour);
23
+
34
+
24
VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
35
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
25
VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
36
+ vec_full_reg_offset(s, rn),
26
VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
37
+ vec_full_reg_offset(s, rm),
27
@@ -XXX,XX +XXX,XX @@ VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
38
+ status, vsz, vsz, data, fn);
28
29
VTST_3s 1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
30
VCEQ_3s 1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
31
+
39
+
32
+VMLA_3s 1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
40
+ tcg_temp_free_ptr(status);
33
+VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
41
+ }
34
+
42
+ return true;
35
+VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
36
+VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
37
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate-neon.inc.c
40
+++ b/target/arm/translate-neon.inc.c
41
@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
42
DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
43
DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
44
DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
45
+DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul)
46
47
#define DO_3SAME_CMP(INSN, COND) \
48
static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
49
@@ -XXX,XX +XXX,XX @@ DO_3SAME_GVEC4(VQADD_S, sqadd_op)
50
DO_3SAME_GVEC4(VQADD_U, uqadd_op)
51
DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
52
DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
53
+
54
+static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
55
+ uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
56
+{
57
+ tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
58
+ 0, gen_helper_gvec_pmul_b);
59
+}
43
+}
60
+
44
+
61
+static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
45
+static bool gen_gvec_fpst_arg_zzz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
46
+ arg_rrr_esz *a, int data)
62
+{
47
+{
63
+ if (a->size != 0) {
48
+ return gen_gvec_fpst_zzz(s, fn, a->rd, a->rn, a->rm, data,
64
+ return false;
49
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
65
+ }
66
+ return do_3same(s, a, gen_VMUL_p_3s);
67
+}
50
+}
68
+
51
+
69
+#define DO_3SAME_GVEC3_NO_SZ_3(INSN, OPARRAY) \
52
/* Invoke an out-of-line helper on 4 Zregs. */
70
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
53
static bool gen_gvec_ool_zzzz(DisasContext *s, gen_helper_gvec_4 *fn,
71
+ uint32_t rn_ofs, uint32_t rm_ofs, \
54
int rd, int rn, int rm, int ra, int data)
72
+ uint32_t oprsz, uint32_t maxsz) \
55
@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
73
+ { \
56
*** SVE Floating Point Arithmetic - Unpredicated Group
74
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, \
57
*/
75
+ oprsz, maxsz, &OPARRAY[vece]); \
58
76
+ } \
59
-static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a,
77
+ DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
60
- gen_helper_gvec_3_ptr *fn)
78
+
61
-{
79
+
62
- if (fn == NULL) {
80
+DO_3SAME_GVEC3_NO_SZ_3(VMLA, mla_op)
63
- return false;
81
+DO_3SAME_GVEC3_NO_SZ_3(VMLS, mls_op)
64
- }
82
+
65
- if (sve_access_check(s)) {
83
+#define DO_3SAME_GVEC3_SHIFT(INSN, OPARRAY) \
66
- unsigned vsz = vec_full_reg_size(s);
84
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
67
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
85
+ uint32_t rn_ofs, uint32_t rm_ofs, \
68
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
86
+ uint32_t oprsz, uint32_t maxsz) \
69
- vec_full_reg_offset(s, a->rn),
87
+ { \
70
- vec_full_reg_offset(s, a->rm),
88
+ /* Note the operation is vshl vd,vm,vn */ \
71
- status, vsz, vsz, 0, fn);
89
+ tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, \
72
- tcg_temp_free_ptr(status);
90
+ oprsz, maxsz, &OPARRAY[vece]); \
73
- }
91
+ } \
74
- return true;
92
+ DO_3SAME(INSN, gen_##INSN##_3s)
75
-}
93
+
94
+DO_3SAME_GVEC3_SHIFT(VSHL_S, sshl_op)
95
+DO_3SAME_GVEC3_SHIFT(VSHL_U, ushl_op)
96
diff --git a/target/arm/translate.c b/target/arm/translate.c
97
index XXXXXXX..XXXXXXX 100644
98
--- a/target/arm/translate.c
99
+++ b/target/arm/translate.c
100
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
101
}
102
return 1;
103
104
- case NEON_3R_VMUL: /* VMUL */
105
- if (u) {
106
- /* Polynomial case allows only P8. */
107
- if (size != 0) {
108
- return 1;
109
- }
110
- tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
111
- 0, gen_helper_gvec_pmul_b);
112
- } else {
113
- tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs,
114
- vec_size, vec_size);
115
- }
116
- return 0;
117
-
76
-
118
- case NEON_3R_VML: /* VMLA, VMLS */
119
- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
120
- u ? &mls_op[size] : &mla_op[size]);
121
- return 0;
122
-
77
-
123
- case NEON_3R_VSHL:
78
#define DO_FP3(NAME, name) \
124
- /* Note the operation is vshl vd,vm,vn */
79
static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
125
- tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
80
{ \
126
- u ? &ushl_op[size] : &sshl_op[size]);
81
@@ -XXX,XX +XXX,XX @@ static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
127
- return 0;
82
NULL, gen_helper_gvec_##name##_h, \
128
-
83
gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \
129
case NEON_3R_VADD_VSUB:
84
}; \
130
case NEON_3R_LOGIC:
85
- return do_zzz_fp(s, a, fns[a->esz]); \
131
case NEON_3R_VMAX:
86
+ return gen_gvec_fpst_arg_zzz(s, fns[a->esz], a, 0); \
132
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
87
}
133
case NEON_3R_VCGE:
88
134
case NEON_3R_VQADD:
89
DO_FP3(FADD_zzz, fadd)
135
case NEON_3R_VQSUB:
136
+ case NEON_3R_VMUL:
137
+ case NEON_3R_VML:
138
+ case NEON_3R_VSHL:
139
/* Already handled by decodetree */
140
return 1;
141
}
142
--
90
--
143
2.20.1
91
2.25.1
144
145
diff view generated by jsdifflib
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Move misplaced comment.
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
4
Message-id: 20220527181907.189259-87-richard.henderson@linaro.org
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Message-id: 20200427181649.26851-3-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
7
---
12
hw/arm/xlnx-versal.c | 2 +-
8
target/arm/translate-sve.c | 7 ++-----
13
1 file changed, 1 insertion(+), 1 deletion(-)
9
1 file changed, 2 insertions(+), 5 deletions(-)
14
10
15
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-versal.c
13
--- a/target/arm/translate-sve.c
18
+++ b/hw/arm/xlnx-versal.c
14
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
15
@@ -XXX,XX +XXX,XX @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a)
20
16
*/
21
obj = object_new(XLNX_VERSAL_ACPU_TYPE);
17
22
if (!obj) {
18
#define DO_FP3(NAME, name) \
23
- /* Secondary CPUs start in PSCI powered-down state */
19
-static bool trans_##NAME(DisasContext *s, arg_rrr_esz *a) \
24
error_report("Unable to create apu.cpu[%d] of type %s",
20
-{ \
25
i, XLNX_VERSAL_ACPU_TYPE);
21
- static gen_helper_gvec_3_ptr * const fns[4] = { \
26
exit(EXIT_FAILURE);
22
+ static gen_helper_gvec_3_ptr * const name##_fns[4] = { \
27
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
23
NULL, gen_helper_gvec_##name##_h, \
28
object_property_set_int(obj, s->cfg.psci_conduit,
24
gen_helper_gvec_##name##_s, gen_helper_gvec_##name##_d \
29
"psci-conduit", &error_abort);
25
}; \
30
if (i) {
26
- return gen_gvec_fpst_arg_zzz(s, fns[a->esz], a, 0); \
31
+ /* Secondary CPUs start in PSCI powered-down state */
27
-}
32
object_property_set_bool(obj, true,
28
+ TRANS_FEAT(NAME, aa64_sve, gen_gvec_fpst_arg_zzz, name##_fns[a->esz], a, 0)
33
"start-powered-off", &error_abort);
29
34
}
30
DO_FP3(FADD_zzz, fadd)
31
DO_FP3(FSUB_zzz, fsub)
35
--
32
--
36
2.20.1
33
2.25.1
37
38
diff view generated by jsdifflib
1
In aarch64_max_initfn() we update both 32-bit and 64-bit ID
1
From: Richard Henderson <richard.henderson@linaro.org>
2
registers. The intended pattern is that for 64-bit ID registers we
3
use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
4
registers use FIELD_DP32 and the uint32_t 'u' register. For
5
ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of
6
this 64-bit ID register would end up always zero. Luckily at the
7
moment that's what they should be anyway, so this bug has no visible
8
effects.
9
2
10
Use the right-sized variable.
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-88-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 26 +++++++-------------------
9
1 file changed, 7 insertions(+), 19 deletions(-)
11
10
12
Fixes: 3bec78447a958d481991
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
16
Message-id: 20200423110915.10527-1-peter.maydell@linaro.org
17
---
18
target/arm/cpu64.c | 6 +++---
19
1 file changed, 3 insertions(+), 3 deletions(-)
20
21
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
22
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu64.c
13
--- a/target/arm/translate-sve.c
24
+++ b/target/arm/cpu64.c
14
+++ b/target/arm/translate-sve.c
25
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FMLS_zzxz, aa64_sve, do_FMLA_zzxz, a, true)
26
u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
16
*** SVE Floating Point Multiply Indexed Group
27
cpu->isar.id_mmfr4 = u;
17
*/
28
18
29
- u = cpu->isar.id_aa64dfr0;
19
-static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a)
30
- u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
20
-{
31
- cpu->isar.id_aa64dfr0 = u;
21
- static gen_helper_gvec_3_ptr * const fns[3] = {
32
+ t = cpu->isar.id_aa64dfr0;
22
- gen_helper_gvec_fmul_idx_h,
33
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
23
- gen_helper_gvec_fmul_idx_s,
34
+ cpu->isar.id_aa64dfr0 = t;
24
- gen_helper_gvec_fmul_idx_d,
35
25
- };
36
u = cpu->isar.id_dfr0;
26
-
37
u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
27
- if (sve_access_check(s)) {
28
- unsigned vsz = vec_full_reg_size(s);
29
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
30
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
31
- vec_full_reg_offset(s, a->rn),
32
- vec_full_reg_offset(s, a->rm),
33
- status, vsz, vsz, a->index, fns[a->esz - 1]);
34
- tcg_temp_free_ptr(status);
35
- }
36
- return true;
37
-}
38
+static gen_helper_gvec_3_ptr * const fmul_idx_fns[4] = {
39
+ NULL, gen_helper_gvec_fmul_idx_h,
40
+ gen_helper_gvec_fmul_idx_s, gen_helper_gvec_fmul_idx_d,
41
+};
42
+TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
43
+ fmul_idx_fns[a->esz], a->rd, a->rn, a->rm, a->index,
44
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
45
46
/*
47
*** SVE Floating Point Fast Reduction Group
38
--
48
--
39
2.20.1
49
2.25.1
40
41
diff view generated by jsdifflib
1
The access_type argument to get_phys_addr_lpae() is an MMUAccessType;
1
From: Richard Henderson <richard.henderson@linaro.org>
2
use the enum constant MMU_DATA_LOAD rather than a literal 0 when we
3
call it in S1_ptw_translate().
4
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-89-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200330210400.11724-3-peter.maydell@linaro.org
9
---
7
---
10
target/arm/helper.c | 5 +++--
8
target/arm/translate-sve.c | 29 +++++++----------------------
11
1 file changed, 3 insertions(+), 2 deletions(-)
9
1 file changed, 7 insertions(+), 22 deletions(-)
12
10
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
13
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/helper.c
14
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
15
@@ -XXX,XX +XXX,XX @@ DO_PPZ(FCMNE_ppz0, fcmne0)
18
pcacheattrs = &cacheattrs;
16
*** SVE floating-point trig multiply-add coefficient
19
}
17
*/
20
18
21
- ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa,
19
-static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a)
22
- &txattrs, &s2prot, &s2size, fi, pcacheattrs);
20
-{
23
+ ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
21
- static gen_helper_gvec_3_ptr * const fns[3] = {
24
+ &s2pa, &txattrs, &s2prot, &s2size, fi,
22
- gen_helper_sve_ftmad_h,
25
+ pcacheattrs);
23
- gen_helper_sve_ftmad_s,
26
if (ret) {
24
- gen_helper_sve_ftmad_d,
27
assert(fi->type != ARMFault_None);
25
- };
28
fi->s2addr = addr;
26
-
27
- if (a->esz == 0) {
28
- return false;
29
- }
30
- if (sve_access_check(s)) {
31
- unsigned vsz = vec_full_reg_size(s);
32
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
33
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
34
- vec_full_reg_offset(s, a->rn),
35
- vec_full_reg_offset(s, a->rm),
36
- status, vsz, vsz, a->imm, fns[a->esz - 1]);
37
- tcg_temp_free_ptr(status);
38
- }
39
- return true;
40
-}
41
+static gen_helper_gvec_3_ptr * const ftmad_fns[4] = {
42
+ NULL, gen_helper_sve_ftmad_h,
43
+ gen_helper_sve_ftmad_s, gen_helper_sve_ftmad_d,
44
+};
45
+TRANS_FEAT(FTMAD, aa64_sve, gen_gvec_fpst_zzz,
46
+ ftmad_fns[a->esz], a->rd, a->rn, a->rm, a->imm,
47
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
48
49
/*
50
*** SVE Floating Point Accumulating Reduction Group
29
--
51
--
30
2.20.1
52
2.25.1
31
32
diff view generated by jsdifflib
1
Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
1
From: Richard Henderson <richard.henderson@linaro.org>
2
to decodetree. These are the last ones in the group so we can remove
3
all the legacy decode for the group.
4
2
5
Note that in disas_thumb2_insn() the parts of this encoding space
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
where the decodetree decoder returns false will correctly be directed
4
Message-id: 20220527181907.189259-90-richard.henderson@linaro.org
7
to illegal_op by the "(insn & (1 << 28))" check so they won't fall
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
into disas_coproc_insn() by mistake.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 30 +++++++++++++++++-------------
9
1 file changed, 17 insertions(+), 13 deletions(-)
9
10
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20200430181003.21682-11-peter.maydell@linaro.org
13
---
14
target/arm/neon-shared.decode | 7 +++
15
target/arm/translate-neon.inc.c | 32 ++++++++++
16
target/arm/translate.c | 107 +-------------------------------
17
3 files changed, 40 insertions(+), 106 deletions(-)
18
19
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
20
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/neon-shared.decode
13
--- a/target/arm/translate-sve.c
22
+++ b/target/arm/neon-shared.decode
14
+++ b/target/arm/translate-sve.c
23
@@ -XXX,XX +XXX,XX @@ VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FMUL_zzx, aa64_sve, gen_gvec_fpst_zzz,
24
16
typedef void gen_helper_fp_reduce(TCGv_i64, TCGv_ptr, TCGv_ptr,
25
VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
17
TCGv_ptr, TCGv_i32);
26
vm=%vm_dp vn=%vn_dp vd=%vd_dp
18
27
+
19
-static void do_reduce(DisasContext *s, arg_rpr_esz *a,
28
+%vfml_scalar_q0_rm 0:3 5:1
20
+static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
29
+%vfml_scalar_q1_index 5:1 3:1
21
gen_helper_fp_reduce *fn)
30
+VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1 index:1 ... \
22
{
31
+ rm=%vfml_scalar_q0_rm vn=%vn_sp vd=%vd_dp q=0
23
- unsigned vsz = vec_full_reg_size(s);
32
+VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \
24
- unsigned p2vsz = pow2ceil(vsz);
33
+ index=%vfml_scalar_q1_index vn=%vn_dp vd=%vd_dp q=1
25
- TCGv_i32 t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz));
34
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
26
+ unsigned vsz, p2vsz;
35
index XXXXXXX..XXXXXXX 100644
27
+ TCGv_i32 t_desc;
36
--- a/target/arm/translate-neon.inc.c
28
TCGv_ptr t_zn, t_pg, status;
37
+++ b/target/arm/translate-neon.inc.c
29
TCGv_i64 temp;
38
@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
30
39
tcg_temp_free_ptr(fpst);
31
+ if (fn == NULL) {
40
return true;
41
}
42
+
43
+static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
44
+{
45
+ int opr_sz;
46
+
47
+ if (!dc_isar_feature(aa32_fhm, s)) {
48
+ return false;
32
+ return false;
49
+ }
33
+ }
50
+
34
+ if (!sve_access_check(s)) {
51
+ /* UNDEF accesses to D16-D31 if they don't exist. */
52
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
53
+ ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) {
54
+ return false;
55
+ }
56
+
57
+ if (a->vd & a->q) {
58
+ return false;
59
+ }
60
+
61
+ if (!vfp_access_check(s)) {
62
+ return true;
35
+ return true;
63
+ }
36
+ }
64
+
37
+
65
+ opr_sz = (1 + a->q) * 8;
38
+ vsz = vec_full_reg_size(s);
66
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
39
+ p2vsz = pow2ceil(vsz);
67
+ vfp_reg_offset(a->q, a->vn),
40
+ t_desc = tcg_constant_i32(simd_desc(vsz, vsz, p2vsz));
68
+ vfp_reg_offset(a->q, a->rm),
41
temp = tcg_temp_new_i64();
69
+ cpu_env, opr_sz, opr_sz,
42
t_zn = tcg_temp_new_ptr();
70
+ (a->index << 2) | a->s, /* is_2 == 0 */
43
t_pg = tcg_temp_new_ptr();
71
+ gen_helper_gvec_fmlal_idx_a32);
44
@@ -XXX,XX +XXX,XX @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
45
46
write_fp_dreg(s, a->rd, temp);
47
tcg_temp_free_i64(temp);
72
+ return true;
48
+ return true;
73
+}
74
diff --git a/target/arm/translate.c b/target/arm/translate.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/arm/translate.c
77
+++ b/target/arm/translate.c
78
@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
79
}
49
}
80
50
81
#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
51
#define DO_VPZ(NAME, name) \
82
-#define VFP_SREG(insn, bigbit, smallbit) \
52
static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
83
- ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
53
{ \
84
#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
54
- static gen_helper_fp_reduce * const fns[3] = { \
85
if (dc_isar_feature(aa32_simd_r32, s)) { \
55
- gen_helper_sve_##name##_h, \
86
reg = (((insn) >> (bigbit)) & 0x0f) \
56
+ static gen_helper_fp_reduce * const fns[4] = { \
87
@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
57
+ NULL, gen_helper_sve_##name##_h, \
88
reg = ((insn) >> (bigbit)) & 0x0f; \
58
gen_helper_sve_##name##_s, \
89
}} while (0)
59
gen_helper_sve_##name##_d, \
90
60
}; \
91
-#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
61
- if (a->esz == 0) { \
92
#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
62
- return false; \
93
-#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
63
- } \
94
#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
64
- if (sve_access_check(s)) { \
95
-#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
65
- do_reduce(s, a, fns[a->esz - 1]); \
96
#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
66
- } \
97
67
- return true; \
98
static void gen_neon_dup_low16(TCGv_i32 var)
68
+ return do_reduce(s, a, fns[a->esz]); \
99
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
100
return 0;
101
}
69
}
102
70
103
-/* Advanced SIMD two registers and a scalar extension.
71
DO_VPZ(FADDV, faddv)
104
- * 31 24 23 22 20 16 12 11 10 9 8 3 0
105
- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
106
- * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
107
- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
108
- *
109
- */
110
-
111
-static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
112
-{
113
- gen_helper_gvec_3 *fn_gvec = NULL;
114
- gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
115
- int rd, rn, rm, opr_sz, data;
116
- int off_rn, off_rm;
117
- bool is_long = false, q = extract32(insn, 6, 1);
118
- bool ptr_is_env = false;
119
-
120
- if ((insn & 0xffa00f10) == 0xfe000810) {
121
- /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
122
- int is_s = extract32(insn, 20, 1);
123
- int vm20 = extract32(insn, 0, 3);
124
- int vm3 = extract32(insn, 3, 1);
125
- int m = extract32(insn, 5, 1);
126
- int index;
127
-
128
- if (!dc_isar_feature(aa32_fhm, s)) {
129
- return 1;
130
- }
131
- if (q) {
132
- rm = vm20;
133
- index = m * 2 + vm3;
134
- } else {
135
- rm = vm20 * 2 + m;
136
- index = vm3;
137
- }
138
- is_long = true;
139
- data = (index << 2) | is_s; /* is_2 == 0 */
140
- fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
141
- ptr_is_env = true;
142
- } else {
143
- return 1;
144
- }
145
-
146
- VFP_DREG_D(rd, insn);
147
- if (rd & q) {
148
- return 1;
149
- }
150
- if (q || !is_long) {
151
- VFP_DREG_N(rn, insn);
152
- if (rn & q & !is_long) {
153
- return 1;
154
- }
155
- off_rn = vfp_reg_offset(1, rn);
156
- off_rm = vfp_reg_offset(1, rm);
157
- } else {
158
- rn = VFP_SREG_N(insn);
159
- off_rn = vfp_reg_offset(0, rn);
160
- off_rm = vfp_reg_offset(0, rm);
161
- }
162
- if (s->fp_excp_el) {
163
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
164
- syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
165
- return 0;
166
- }
167
- if (!s->vfp_enabled) {
168
- return 1;
169
- }
170
-
171
- opr_sz = (1 + q) * 8;
172
- if (fn_gvec_ptr) {
173
- TCGv_ptr ptr;
174
- if (ptr_is_env) {
175
- ptr = cpu_env;
176
- } else {
177
- ptr = get_fpstatus_ptr(1);
178
- }
179
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
180
- opr_sz, opr_sz, data, fn_gvec_ptr);
181
- if (!ptr_is_env) {
182
- tcg_temp_free_ptr(ptr);
183
- }
184
- } else {
185
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
186
- opr_sz, opr_sz, data, fn_gvec);
187
- }
188
- return 0;
189
-}
190
-
191
static int disas_coproc_insn(DisasContext *s, uint32_t insn)
192
{
193
int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
194
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
195
}
196
}
197
}
198
- } else if ((insn & 0x0f000a00) == 0x0e000800
199
- && arm_dc_feature(s, ARM_FEATURE_V8)) {
200
- if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
201
- goto illegal_op;
202
- }
203
- return;
204
}
205
goto illegal_op;
206
}
207
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
208
}
209
break;
210
}
211
- if ((insn & 0xff000a00) == 0xfe000800
212
- && arm_dc_feature(s, ARM_FEATURE_V8)) {
213
- /* The Thumb2 and ARM encodings are identical. */
214
- if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
215
- goto illegal_op;
216
- }
217
- } else if (((insn >> 24) & 3) == 3) {
218
+ if (((insn >> 24) & 3) == 3) {
219
/* Translate into the equivalent ARM encoding. */
220
insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
221
if (disas_neon_data_insn(s, insn)) {
222
--
72
--
223
2.20.1
73
2.25.1
224
225
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
By using the TYPE_* definitions for devices, we can:
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
- quickly find where devices are used with 'git-grep'
4
Message-id: 20220527181907.189259-91-richard.henderson@linaro.org
5
- easily rename a device (one-line change).
6
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200428154650.21991-1-f4bug@amsat.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
7
---
12
hw/arm/mps2-tz.c | 2 +-
8
target/arm/translate-sve.c | 14 ++++++--------
13
1 file changed, 1 insertion(+), 1 deletion(-)
9
1 file changed, 6 insertions(+), 8 deletions(-)
14
10
15
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
16
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/mps2-tz.c
13
--- a/target/arm/translate-sve.c
18
+++ b/hw/arm/mps2-tz.c
14
+++ b/target/arm/translate-sve.c
19
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
15
@@ -XXX,XX +XXX,XX @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a,
20
exit(EXIT_FAILURE);
16
}
21
}
17
22
18
#define DO_VPZ(NAME, name) \
23
- sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
19
-static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a) \
24
+ sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
20
-{ \
25
sizeof(mms->iotkit), mmc->armsse_type);
21
- static gen_helper_fp_reduce * const fns[4] = { \
26
iotkitdev = DEVICE(&mms->iotkit);
22
- NULL, gen_helper_sve_##name##_h, \
27
object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
23
- gen_helper_sve_##name##_s, \
24
- gen_helper_sve_##name##_d, \
25
+ static gen_helper_fp_reduce * const name##_fns[4] = { \
26
+ NULL, gen_helper_sve_##name##_h, \
27
+ gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
28
}; \
29
- return do_reduce(s, a, fns[a->esz]); \
30
-}
31
+ TRANS_FEAT(NAME, aa64_sve, do_reduce, a, name##_fns[a->esz])
32
33
DO_VPZ(FADDV, faddv)
34
DO_VPZ(FMINNMV, fminnmv)
35
@@ -XXX,XX +XXX,XX @@ DO_VPZ(FMAXNMV, fmaxnmv)
36
DO_VPZ(FMINV, fminv)
37
DO_VPZ(FMAXV, fmaxv)
38
39
+#undef DO_VPZ
40
+
41
/*
42
*** SVE Floating Point Unary Operations - Unpredicated Group
43
*/
28
--
44
--
29
2.20.1
45
2.25.1
30
31
diff view generated by jsdifflib
1
Convert the VCADD (vector) insns to decodetree.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Rename do_zz_fp to gen_gvec_fpst_arg_zz, and move up.
4
Split out gen_gvec_fpst_zz as a helper while we're at it.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-92-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200430181003.21682-6-peter.maydell@linaro.org
6
---
10
---
7
target/arm/neon-shared.decode | 3 +++
11
target/arm/translate-sve.c | 77 ++++++++++++++++++--------------------
8
target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
12
1 file changed, 36 insertions(+), 41 deletions(-)
9
target/arm/translate.c | 11 +---------
10
3 files changed, 41 insertions(+), 10 deletions(-)
11
13
12
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/neon-shared.decode
16
--- a/target/arm/translate-sve.c
15
+++ b/target/arm/neon-shared.decode
17
+++ b/target/arm/translate-sve.c
16
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_zz(DisasContext *s, gen_helper_gvec_2 *fn,
17
18
VCMLA 1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
19
vm=%vm_dp vn=%vn_dp vd=%vd_dp
20
+
21
+VCADD 1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
22
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp
23
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/translate-neon.inc.c
26
+++ b/target/arm/translate-neon.inc.c
27
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
28
tcg_temp_free_ptr(fpst);
29
return true;
19
return true;
30
}
20
}
31
+
21
32
+static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
22
+static bool gen_gvec_fpst_zz(DisasContext *s, gen_helper_gvec_2_ptr *fn,
23
+ int rd, int rn, int data,
24
+ ARMFPStatusFlavour flavour)
33
+{
25
+{
34
+ int opr_sz;
26
+ if (fn == NULL) {
35
+ TCGv_ptr fpst;
36
+ gen_helper_gvec_3_ptr *fn_gvec_ptr;
37
+
38
+ if (!dc_isar_feature(aa32_vcma, s)
39
+ || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
40
+ return false;
27
+ return false;
41
+ }
28
+ }
29
+ if (sve_access_check(s)) {
30
+ unsigned vsz = vec_full_reg_size(s);
31
+ TCGv_ptr status = fpstatus_ptr(flavour);
42
+
32
+
43
+ /* UNDEF accesses to D16-D31 if they don't exist. */
33
+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd),
44
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
34
+ vec_full_reg_offset(s, rn),
45
+ ((a->vd | a->vn | a->vm) & 0x10)) {
35
+ status, vsz, vsz, data, fn);
46
+ return false;
36
+ tcg_temp_free_ptr(status);
47
+ }
37
+ }
48
+
49
+ if ((a->vn | a->vm | a->vd) & a->q) {
50
+ return false;
51
+ }
52
+
53
+ if (!vfp_access_check(s)) {
54
+ return true;
55
+ }
56
+
57
+ opr_sz = (1 + a->q) * 8;
58
+ fpst = get_fpstatus_ptr(1);
59
+ fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
60
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
61
+ vfp_reg_offset(1, a->vn),
62
+ vfp_reg_offset(1, a->vm),
63
+ fpst, opr_sz, opr_sz, a->rot,
64
+ fn_gvec_ptr);
65
+ tcg_temp_free_ptr(fpst);
66
+ return true;
38
+ return true;
67
+}
39
+}
68
diff --git a/target/arm/translate.c b/target/arm/translate.c
40
+
69
index XXXXXXX..XXXXXXX 100644
41
+static bool gen_gvec_fpst_arg_zz(DisasContext *s, gen_helper_gvec_2_ptr *fn,
70
--- a/target/arm/translate.c
42
+ arg_rr_esz *a, int data)
71
+++ b/target/arm/translate.c
43
+{
72
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
44
+ return gen_gvec_fpst_zz(s, fn, a->rd, a->rn, data,
73
bool is_long = false, q = extract32(insn, 6, 1);
45
+ a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
74
bool ptr_is_env = false;
46
+}
75
47
+
76
- if ((insn & 0xfea00f10) == 0xfc800800) {
48
/* Invoke an out-of-line helper on 3 Zregs. */
77
- /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
49
static bool gen_gvec_ool_zzz(DisasContext *s, gen_helper_gvec_3 *fn,
78
- int size = extract32(insn, 20, 1);
50
int rd, int rn, int rm, int data)
79
- data = extract32(insn, 24, 1); /* rot */
51
@@ -XXX,XX +XXX,XX @@ DO_VPZ(FMAXV, fmaxv)
80
- if (!dc_isar_feature(aa32_vcma, s)
52
*** SVE Floating Point Unary Operations - Unpredicated Group
81
- || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
53
*/
82
- return 1;
54
83
- }
55
-static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn)
84
- fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
56
-{
85
- } else if ((insn & 0xfeb00f00) == 0xfc200d00) {
57
- unsigned vsz = vec_full_reg_size(s);
86
+ if ((insn & 0xfeb00f00) == 0xfc200d00) {
58
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
87
/* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
59
+static gen_helper_gvec_2_ptr * const frecpe_fns[] = {
88
bool u = extract32(insn, 4, 1);
60
+ NULL, gen_helper_gvec_frecpe_h,
89
if (!dc_isar_feature(aa32_dp, s)) {
61
+ gen_helper_gvec_frecpe_s, gen_helper_gvec_frecpe_d,
62
+};
63
+TRANS_FEAT(FRECPE, aa64_sve, gen_gvec_fpst_arg_zz, frecpe_fns[a->esz], a, 0)
64
65
- tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd),
66
- vec_full_reg_offset(s, a->rn),
67
- status, vsz, vsz, 0, fn);
68
- tcg_temp_free_ptr(status);
69
-}
70
-
71
-static bool trans_FRECPE(DisasContext *s, arg_rr_esz *a)
72
-{
73
- static gen_helper_gvec_2_ptr * const fns[3] = {
74
- gen_helper_gvec_frecpe_h,
75
- gen_helper_gvec_frecpe_s,
76
- gen_helper_gvec_frecpe_d,
77
- };
78
- if (a->esz == 0) {
79
- return false;
80
- }
81
- if (sve_access_check(s)) {
82
- do_zz_fp(s, a, fns[a->esz - 1]);
83
- }
84
- return true;
85
-}
86
-
87
-static bool trans_FRSQRTE(DisasContext *s, arg_rr_esz *a)
88
-{
89
- static gen_helper_gvec_2_ptr * const fns[3] = {
90
- gen_helper_gvec_frsqrte_h,
91
- gen_helper_gvec_frsqrte_s,
92
- gen_helper_gvec_frsqrte_d,
93
- };
94
- if (a->esz == 0) {
95
- return false;
96
- }
97
- if (sve_access_check(s)) {
98
- do_zz_fp(s, a, fns[a->esz - 1]);
99
- }
100
- return true;
101
-}
102
+static gen_helper_gvec_2_ptr * const frsqrte_fns[] = {
103
+ NULL, gen_helper_gvec_frsqrte_h,
104
+ gen_helper_gvec_frsqrte_s, gen_helper_gvec_frsqrte_d,
105
+};
106
+TRANS_FEAT(FRSQRTE, aa64_sve, gen_gvec_fpst_arg_zz, frsqrte_fns[a->esz], a, 0)
107
108
/*
109
*** SVE Floating Point Compare with Zero Group
90
--
110
--
91
2.20.1
111
2.25.1
92
93
diff view generated by jsdifflib
1
For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know
1
From: Richard Henderson <richard.henderson@linaro.org>
2
whether the stage 1 access is for EL0 or not, because whether
3
exec permission is given can depend on whether this is an EL0
4
or EL1 access. Add a new argument to get_phys_addr_lpae() so
5
the call sites can pass this information in.
6
2
7
Since get_phys_addr_lpae() doesn't already have a doc comment,
3
Simplify indexing of this array. This will allow folding
8
add one so we have a place to put the documentation of the
4
of the illegal esz == 0 into the normal fn == NULL check.
9
semantics of the new s1_is_el0 argument.
10
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220527181907.189259-93-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20200330210400.11724-4-peter.maydell@linaro.org
15
---
10
---
16
target/arm/helper.c | 29 ++++++++++++++++++++++++++++-
11
target/arm/translate-sve.c | 15 ++++++++-------
17
1 file changed, 28 insertions(+), 1 deletion(-)
12
1 file changed, 8 insertions(+), 7 deletions(-)
18
13
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
20
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
16
--- a/target/arm/translate-sve.c
22
+++ b/target/arm/helper.c
17
+++ b/target/arm/translate-sve.c
23
@@ -XXX,XX +XXX,XX @@
18
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a)
24
19
return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd);
25
static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
26
MMUAccessType access_type, ARMMMUIdx mmu_idx,
27
+ bool s1_is_el0,
28
hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
29
target_ulong *page_size_ptr,
30
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
31
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
32
}
33
34
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
35
+ false,
36
&s2pa, &txattrs, &s2prot, &s2size, fi,
37
pcacheattrs);
38
if (ret) {
39
@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
40
};
41
}
20
}
42
21
43
+/**
22
-static gen_helper_gvec_3_ptr * const frint_fns[3] = {
44
+ * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
23
+static gen_helper_gvec_3_ptr * const frint_fns[] = {
45
+ *
24
+ NULL,
46
+ * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
25
gen_helper_sve_frint_h,
47
+ * prot and page_size may not be filled in, and the populated fsr value provides
26
gen_helper_sve_frint_s,
48
+ * information on why the translation aborted, in the format of a long-format
27
gen_helper_sve_frint_d
49
+ * DFSR/IFSR fault register, with the following caveats:
28
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a)
50
+ * * the WnR bit is never set (the caller must do this).
29
return false;
51
+ *
52
+ * @env: CPUARMState
53
+ * @address: virtual address to get physical address for
54
+ * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
55
+ * @mmu_idx: MMU index indicating required translation regime
56
+ * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
57
+ * walk), must be true if this is stage 2 of a stage 1+2 walk for an
58
+ * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
59
+ * @phys_ptr: set to the physical address corresponding to the virtual address
60
+ * @attrs: set to the memory transaction attributes to use
61
+ * @prot: set to the permissions for the page containing phys_ptr
62
+ * @page_size_ptr: set to the size of the page containing phys_ptr
63
+ * @fi: set to fault info if the translation fails
64
+ * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
65
+ */
66
static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
67
MMUAccessType access_type, ARMMMUIdx mmu_idx,
68
+ bool s1_is_el0,
69
hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
70
target_ulong *page_size_ptr,
71
ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
72
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
73
74
/* S1 is done. Now do S2 translation. */
75
ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,
76
+ mmu_idx == ARMMMUIdx_E10_0,
77
phys_ptr, attrs, &s2_prot,
78
page_size, fi,
79
cacheattrs != NULL ? &cacheattrs2 : NULL);
80
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
81
}
30
}
82
31
return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16,
83
if (regime_using_lpae_format(env, mmu_idx)) {
32
- frint_fns[a->esz - 1]);
84
- return get_phys_addr_lpae(env, address, access_type, mmu_idx,
33
+ frint_fns[a->esz]);
85
+ return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
34
}
86
phys_ptr, attrs, prot, page_size,
35
87
fi, cacheattrs);
36
static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a)
88
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
37
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
38
if (a->esz == 0) {
39
return false;
40
}
41
- return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz - 1]);
42
+ return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz]);
43
}
44
45
static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
46
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
47
if (a->esz == 0) {
48
return false;
49
}
50
- return do_frint_mode(s, a, float_round_up, frint_fns[a->esz - 1]);
51
+ return do_frint_mode(s, a, float_round_up, frint_fns[a->esz]);
52
}
53
54
static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
55
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
56
if (a->esz == 0) {
57
return false;
58
}
59
- return do_frint_mode(s, a, float_round_down, frint_fns[a->esz - 1]);
60
+ return do_frint_mode(s, a, float_round_down, frint_fns[a->esz]);
61
}
62
63
static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
64
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
65
if (a->esz == 0) {
66
return false;
67
}
68
- return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz - 1]);
69
+ return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz]);
70
}
71
72
static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
73
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
74
if (a->esz == 0) {
75
return false;
76
}
77
- return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz - 1]);
78
+ return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
79
}
80
81
static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a)
89
--
82
--
90
2.20.1
83
2.25.1
91
92
diff view generated by jsdifflib
1
Convert the VCMLA (vector) insns in the 3same extension group to
1
From: Richard Henderson <richard.henderson@linaro.org>
2
decodetree.
3
2
3
Rename the function to match other expansion function and
4
move to be adjacent. Split out gen_gvec_fpst_zzp as a
5
helper while we're at it.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220527181907.189259-94-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200430181003.21682-5-peter.maydell@linaro.org
7
---
11
---
8
target/arm/neon-shared.decode | 11 ++++++++++
12
target/arm/translate-sve.c | 392 ++++++++++++-------------------------
9
target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
13
1 file changed, 129 insertions(+), 263 deletions(-)
10
target/arm/translate.c | 11 +---------
11
3 files changed, 49 insertions(+), 10 deletions(-)
12
14
13
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
15
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/neon-shared.decode
17
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/neon-shared.decode
18
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@ static bool gen_gvec_ool_arg_zpzi(DisasContext *s, gen_helper_gvec_3 *fn,
18
# More specifically, this covers:
20
return gen_gvec_ool_zzp(s, fn, a->rd, a->rn, a->pg, a->imm);
19
# 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
21
}
20
# 3same ext: 0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
22
21
+
23
+static bool gen_gvec_fpst_zzp(DisasContext *s, gen_helper_gvec_3_ptr *fn,
22
+# VFP/Neon register fields; same as vfp.decode
24
+ int rd, int rn, int pg, int data,
23
+%vm_dp 5:1 0:4
25
+ ARMFPStatusFlavour flavour)
24
+%vm_sp 0:4 5:1
25
+%vn_dp 7:1 16:4
26
+%vn_sp 16:4 7:1
27
+%vd_dp 22:1 12:4
28
+%vd_sp 12:4 22:1
29
+
30
+VCMLA 1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
31
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp
32
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/translate-neon.inc.c
35
+++ b/target/arm/translate-neon.inc.c
36
@@ -XXX,XX +XXX,XX @@
37
#include "decode-neon-dp.inc.c"
38
#include "decode-neon-ls.inc.c"
39
#include "decode-neon-shared.inc.c"
40
+
41
+static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
42
+{
26
+{
43
+ int opr_sz;
27
+ if (fn == NULL) {
44
+ TCGv_ptr fpst;
45
+ gen_helper_gvec_3_ptr *fn_gvec_ptr;
46
+
47
+ if (!dc_isar_feature(aa32_vcma, s)
48
+ || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
49
+ return false;
28
+ return false;
50
+ }
29
+ }
30
+ if (sve_access_check(s)) {
31
+ unsigned vsz = vec_full_reg_size(s);
32
+ TCGv_ptr status = fpstatus_ptr(flavour);
51
+
33
+
52
+ /* UNDEF accesses to D16-D31 if they don't exist. */
34
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
53
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
35
+ vec_full_reg_offset(s, rn),
54
+ ((a->vd | a->vn | a->vm) & 0x10)) {
36
+ pred_full_reg_offset(s, pg),
55
+ return false;
37
+ status, vsz, vsz, data, fn);
38
+ tcg_temp_free_ptr(status);
56
+ }
39
+ }
57
+
58
+ if ((a->vn | a->vm | a->vd) & a->q) {
59
+ return false;
60
+ }
61
+
62
+ if (!vfp_access_check(s)) {
63
+ return true;
64
+ }
65
+
66
+ opr_sz = (1 + a->q) * 8;
67
+ fpst = get_fpstatus_ptr(1);
68
+ fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
69
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
70
+ vfp_reg_offset(1, a->vn),
71
+ vfp_reg_offset(1, a->vm),
72
+ fpst, opr_sz, opr_sz, a->rot,
73
+ fn_gvec_ptr);
74
+ tcg_temp_free_ptr(fpst);
75
+ return true;
40
+ return true;
76
+}
41
+}
77
diff --git a/target/arm/translate.c b/target/arm/translate.c
42
+
78
index XXXXXXX..XXXXXXX 100644
43
+static bool gen_gvec_fpst_arg_zpz(DisasContext *s, gen_helper_gvec_3_ptr *fn,
79
--- a/target/arm/translate.c
44
+ arg_rpr_esz *a, int data,
80
+++ b/target/arm/translate.c
45
+ ARMFPStatusFlavour flavour)
81
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
46
+{
82
bool is_long = false, q = extract32(insn, 6, 1);
47
+ return gen_gvec_fpst_zzp(s, fn, a->rd, a->rn, a->pg, data, flavour);
83
bool ptr_is_env = false;
48
+}
84
49
+
85
- if ((insn & 0xfe200f10) == 0xfc200800) {
50
/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
86
- /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
51
static bool gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
87
- int size = extract32(insn, 20, 1);
52
int rd, int rn, int rm, int pg, int data)
88
- data = extract32(insn, 23, 2); /* rot */
53
@@ -XXX,XX +XXX,XX @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)
89
- if (!dc_isar_feature(aa32_vcma, s)
54
*** SVE Floating Point Unary Operations Predicated Group
90
- || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
55
*/
91
- return 1;
56
92
- }
57
-static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
93
- fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
58
- bool is_fp16, gen_helper_gvec_3_ptr *fn)
94
- } else if ((insn & 0xfea00f10) == 0xfc800800) {
59
-{
95
+ if ((insn & 0xfea00f10) == 0xfc800800) {
60
- if (sve_access_check(s)) {
96
/* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
61
- unsigned vsz = vec_full_reg_size(s);
97
int size = extract32(insn, 20, 1);
62
- TCGv_ptr status = fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR);
98
data = extract32(insn, 24, 1); /* rot */
63
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
64
- vec_full_reg_offset(s, rn),
65
- pred_full_reg_offset(s, pg),
66
- status, vsz, vsz, 0, fn);
67
- tcg_temp_free_ptr(status);
68
- }
69
- return true;
70
-}
71
+TRANS_FEAT(FCVT_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
72
+ gen_helper_sve_fcvt_sh, a, 0, FPST_FPCR)
73
+TRANS_FEAT(FCVT_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
74
+ gen_helper_sve_fcvt_hs, a, 0, FPST_FPCR)
75
76
-static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a)
77
-{
78
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
79
-}
80
+TRANS_FEAT(BFCVT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
81
+ gen_helper_sve_bfcvt, a, 0, FPST_FPCR)
82
83
-static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a)
84
-{
85
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hs);
86
-}
87
+TRANS_FEAT(FCVT_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
88
+ gen_helper_sve_fcvt_dh, a, 0, FPST_FPCR)
89
+TRANS_FEAT(FCVT_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
90
+ gen_helper_sve_fcvt_hd, a, 0, FPST_FPCR)
91
+TRANS_FEAT(FCVT_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
92
+ gen_helper_sve_fcvt_ds, a, 0, FPST_FPCR)
93
+TRANS_FEAT(FCVT_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
94
+ gen_helper_sve_fcvt_sd, a, 0, FPST_FPCR)
95
96
-static bool trans_BFCVT(DisasContext *s, arg_rpr_esz *a)
97
-{
98
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
99
- return false;
100
- }
101
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvt);
102
-}
103
+TRANS_FEAT(FCVTZS_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
104
+ gen_helper_sve_fcvtzs_hh, a, 0, FPST_FPCR_F16)
105
+TRANS_FEAT(FCVTZU_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
106
+ gen_helper_sve_fcvtzu_hh, a, 0, FPST_FPCR_F16)
107
+TRANS_FEAT(FCVTZS_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
108
+ gen_helper_sve_fcvtzs_hs, a, 0, FPST_FPCR_F16)
109
+TRANS_FEAT(FCVTZU_hs, aa64_sve, gen_gvec_fpst_arg_zpz,
110
+ gen_helper_sve_fcvtzu_hs, a, 0, FPST_FPCR_F16)
111
+TRANS_FEAT(FCVTZS_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
112
+ gen_helper_sve_fcvtzs_hd, a, 0, FPST_FPCR_F16)
113
+TRANS_FEAT(FCVTZU_hd, aa64_sve, gen_gvec_fpst_arg_zpz,
114
+ gen_helper_sve_fcvtzu_hd, a, 0, FPST_FPCR_F16)
115
116
-static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a)
117
-{
118
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
119
-}
120
+TRANS_FEAT(FCVTZS_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
121
+ gen_helper_sve_fcvtzs_ss, a, 0, FPST_FPCR)
122
+TRANS_FEAT(FCVTZU_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
123
+ gen_helper_sve_fcvtzu_ss, a, 0, FPST_FPCR)
124
+TRANS_FEAT(FCVTZS_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
125
+ gen_helper_sve_fcvtzs_sd, a, 0, FPST_FPCR)
126
+TRANS_FEAT(FCVTZU_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
127
+ gen_helper_sve_fcvtzu_sd, a, 0, FPST_FPCR)
128
+TRANS_FEAT(FCVTZS_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
129
+ gen_helper_sve_fcvtzs_ds, a, 0, FPST_FPCR)
130
+TRANS_FEAT(FCVTZU_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
131
+ gen_helper_sve_fcvtzu_ds, a, 0, FPST_FPCR)
132
133
-static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a)
134
-{
135
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_hd);
136
-}
137
-
138
-static bool trans_FCVT_ds(DisasContext *s, arg_rpr_esz *a)
139
-{
140
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_ds);
141
-}
142
-
143
-static bool trans_FCVT_sd(DisasContext *s, arg_rpr_esz *a)
144
-{
145
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sd);
146
-}
147
-
148
-static bool trans_FCVTZS_hh(DisasContext *s, arg_rpr_esz *a)
149
-{
150
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hh);
151
-}
152
-
153
-static bool trans_FCVTZU_hh(DisasContext *s, arg_rpr_esz *a)
154
-{
155
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hh);
156
-}
157
-
158
-static bool trans_FCVTZS_hs(DisasContext *s, arg_rpr_esz *a)
159
-{
160
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hs);
161
-}
162
-
163
-static bool trans_FCVTZU_hs(DisasContext *s, arg_rpr_esz *a)
164
-{
165
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hs);
166
-}
167
-
168
-static bool trans_FCVTZS_hd(DisasContext *s, arg_rpr_esz *a)
169
-{
170
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzs_hd);
171
-}
172
-
173
-static bool trans_FCVTZU_hd(DisasContext *s, arg_rpr_esz *a)
174
-{
175
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvtzu_hd);
176
-}
177
-
178
-static bool trans_FCVTZS_ss(DisasContext *s, arg_rpr_esz *a)
179
-{
180
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ss);
181
-}
182
-
183
-static bool trans_FCVTZU_ss(DisasContext *s, arg_rpr_esz *a)
184
-{
185
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ss);
186
-}
187
-
188
-static bool trans_FCVTZS_sd(DisasContext *s, arg_rpr_esz *a)
189
-{
190
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_sd);
191
-}
192
-
193
-static bool trans_FCVTZU_sd(DisasContext *s, arg_rpr_esz *a)
194
-{
195
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_sd);
196
-}
197
-
198
-static bool trans_FCVTZS_ds(DisasContext *s, arg_rpr_esz *a)
199
-{
200
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_ds);
201
-}
202
-
203
-static bool trans_FCVTZU_ds(DisasContext *s, arg_rpr_esz *a)
204
-{
205
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_ds);
206
-}
207
-
208
-static bool trans_FCVTZS_dd(DisasContext *s, arg_rpr_esz *a)
209
-{
210
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzs_dd);
211
-}
212
-
213
-static bool trans_FCVTZU_dd(DisasContext *s, arg_rpr_esz *a)
214
-{
215
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvtzu_dd);
216
-}
217
+TRANS_FEAT(FCVTZS_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
218
+ gen_helper_sve_fcvtzs_dd, a, 0, FPST_FPCR)
219
+TRANS_FEAT(FCVTZU_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
220
+ gen_helper_sve_fcvtzu_dd, a, 0, FPST_FPCR)
221
222
static gen_helper_gvec_3_ptr * const frint_fns[] = {
223
NULL,
224
@@ -XXX,XX +XXX,XX @@ static gen_helper_gvec_3_ptr * const frint_fns[] = {
225
gen_helper_sve_frint_s,
226
gen_helper_sve_frint_d
227
};
228
+TRANS_FEAT(FRINTI, aa64_sve, gen_gvec_fpst_arg_zpz, frint_fns[a->esz],
229
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
230
231
-static bool trans_FRINTI(DisasContext *s, arg_rpr_esz *a)
232
-{
233
- if (a->esz == 0) {
234
- return false;
235
- }
236
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16,
237
- frint_fns[a->esz]);
238
-}
239
-
240
-static bool trans_FRINTX(DisasContext *s, arg_rpr_esz *a)
241
-{
242
- static gen_helper_gvec_3_ptr * const fns[3] = {
243
- gen_helper_sve_frintx_h,
244
- gen_helper_sve_frintx_s,
245
- gen_helper_sve_frintx_d
246
- };
247
- if (a->esz == 0) {
248
- return false;
249
- }
250
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
251
-}
252
+static gen_helper_gvec_3_ptr * const frintx_fns[] = {
253
+ NULL,
254
+ gen_helper_sve_frintx_h,
255
+ gen_helper_sve_frintx_s,
256
+ gen_helper_sve_frintx_d
257
+};
258
+TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
259
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
260
261
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
262
int mode, gen_helper_gvec_3_ptr *fn)
263
@@ -XXX,XX +XXX,XX @@ static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
264
return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
265
}
266
267
-static bool trans_FRECPX(DisasContext *s, arg_rpr_esz *a)
268
-{
269
- static gen_helper_gvec_3_ptr * const fns[3] = {
270
- gen_helper_sve_frecpx_h,
271
- gen_helper_sve_frecpx_s,
272
- gen_helper_sve_frecpx_d
273
- };
274
- if (a->esz == 0) {
275
- return false;
276
- }
277
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
278
-}
279
+static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
280
+ NULL, gen_helper_sve_frecpx_h,
281
+ gen_helper_sve_frecpx_s, gen_helper_sve_frecpx_d,
282
+};
283
+TRANS_FEAT(FRECPX, aa64_sve, gen_gvec_fpst_arg_zpz, frecpx_fns[a->esz],
284
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
285
286
-static bool trans_FSQRT(DisasContext *s, arg_rpr_esz *a)
287
-{
288
- static gen_helper_gvec_3_ptr * const fns[3] = {
289
- gen_helper_sve_fsqrt_h,
290
- gen_helper_sve_fsqrt_s,
291
- gen_helper_sve_fsqrt_d
292
- };
293
- if (a->esz == 0) {
294
- return false;
295
- }
296
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, a->esz == MO_16, fns[a->esz - 1]);
297
-}
298
+static gen_helper_gvec_3_ptr * const fsqrt_fns[] = {
299
+ NULL, gen_helper_sve_fsqrt_h,
300
+ gen_helper_sve_fsqrt_s, gen_helper_sve_fsqrt_d,
301
+};
302
+TRANS_FEAT(FSQRT, aa64_sve, gen_gvec_fpst_arg_zpz, fsqrt_fns[a->esz],
303
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
304
305
-static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a)
306
-{
307
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh);
308
-}
309
+TRANS_FEAT(SCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
310
+ gen_helper_sve_scvt_hh, a, 0, FPST_FPCR_F16)
311
+TRANS_FEAT(SCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
312
+ gen_helper_sve_scvt_sh, a, 0, FPST_FPCR_F16)
313
+TRANS_FEAT(SCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
314
+ gen_helper_sve_scvt_dh, a, 0, FPST_FPCR_F16)
315
316
-static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a)
317
-{
318
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_sh);
319
-}
320
+TRANS_FEAT(SCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
321
+ gen_helper_sve_scvt_ss, a, 0, FPST_FPCR)
322
+TRANS_FEAT(SCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
323
+ gen_helper_sve_scvt_ds, a, 0, FPST_FPCR)
324
325
-static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a)
326
-{
327
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_dh);
328
-}
329
+TRANS_FEAT(SCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
330
+ gen_helper_sve_scvt_sd, a, 0, FPST_FPCR)
331
+TRANS_FEAT(SCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
332
+ gen_helper_sve_scvt_dd, a, 0, FPST_FPCR)
333
334
-static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a)
335
-{
336
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ss);
337
-}
338
+TRANS_FEAT(UCVTF_hh, aa64_sve, gen_gvec_fpst_arg_zpz,
339
+ gen_helper_sve_ucvt_hh, a, 0, FPST_FPCR_F16)
340
+TRANS_FEAT(UCVTF_sh, aa64_sve, gen_gvec_fpst_arg_zpz,
341
+ gen_helper_sve_ucvt_sh, a, 0, FPST_FPCR_F16)
342
+TRANS_FEAT(UCVTF_dh, aa64_sve, gen_gvec_fpst_arg_zpz,
343
+ gen_helper_sve_ucvt_dh, a, 0, FPST_FPCR_F16)
344
345
-static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a)
346
-{
347
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ds);
348
-}
349
+TRANS_FEAT(UCVTF_ss, aa64_sve, gen_gvec_fpst_arg_zpz,
350
+ gen_helper_sve_ucvt_ss, a, 0, FPST_FPCR)
351
+TRANS_FEAT(UCVTF_ds, aa64_sve, gen_gvec_fpst_arg_zpz,
352
+ gen_helper_sve_ucvt_ds, a, 0, FPST_FPCR)
353
+TRANS_FEAT(UCVTF_sd, aa64_sve, gen_gvec_fpst_arg_zpz,
354
+ gen_helper_sve_ucvt_sd, a, 0, FPST_FPCR)
355
356
-static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a)
357
-{
358
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_sd);
359
-}
360
-
361
-static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a)
362
-{
363
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_dd);
364
-}
365
-
366
-static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a)
367
-{
368
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_hh);
369
-}
370
-
371
-static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a)
372
-{
373
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_sh);
374
-}
375
-
376
-static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a)
377
-{
378
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_dh);
379
-}
380
-
381
-static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a)
382
-{
383
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ss);
384
-}
385
-
386
-static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a)
387
-{
388
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ds);
389
-}
390
-
391
-static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a)
392
-{
393
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_sd);
394
-}
395
-
396
-static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a)
397
-{
398
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_dd);
399
-}
400
+TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz,
401
+ gen_helper_sve_ucvt_dd, a, 0, FPST_FPCR)
402
403
/*
404
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
405
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
406
407
TRANS_FEAT(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz, gen_gvec_rax1, a)
408
409
-static bool trans_FCVTNT_sh(DisasContext *s, arg_rpr_esz *a)
410
-{
411
- if (!dc_isar_feature(aa64_sve2, s)) {
412
- return false;
413
- }
414
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_sh);
415
-}
416
+TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz,
417
+ gen_helper_sve2_fcvtnt_sh, a, 0, FPST_FPCR)
418
+TRANS_FEAT(FCVTNT_ds, aa64_sve2, gen_gvec_fpst_arg_zpz,
419
+ gen_helper_sve2_fcvtnt_ds, a, 0, FPST_FPCR)
420
421
-static bool trans_BFCVTNT(DisasContext *s, arg_rpr_esz *a)
422
-{
423
- if (!dc_isar_feature(aa64_sve_bf16, s)) {
424
- return false;
425
- }
426
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_bfcvtnt);
427
-}
428
+TRANS_FEAT(BFCVTNT, aa64_sve_bf16, gen_gvec_fpst_arg_zpz,
429
+ gen_helper_sve_bfcvtnt, a, 0, FPST_FPCR)
430
431
-static bool trans_FCVTNT_ds(DisasContext *s, arg_rpr_esz *a)
432
-{
433
- if (!dc_isar_feature(aa64_sve2, s)) {
434
- return false;
435
- }
436
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtnt_ds);
437
-}
438
-
439
-static bool trans_FCVTLT_hs(DisasContext *s, arg_rpr_esz *a)
440
-{
441
- if (!dc_isar_feature(aa64_sve2, s)) {
442
- return false;
443
- }
444
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_hs);
445
-}
446
-
447
-static bool trans_FCVTLT_sd(DisasContext *s, arg_rpr_esz *a)
448
-{
449
- if (!dc_isar_feature(aa64_sve2, s)) {
450
- return false;
451
- }
452
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve2_fcvtlt_sd);
453
-}
454
+TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz,
455
+ gen_helper_sve2_fcvtlt_hs, a, 0, FPST_FPCR)
456
+TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
457
+ gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
458
459
static bool trans_FCVTX_ds(DisasContext *s, arg_rpr_esz *a)
460
{
99
--
461
--
100
2.20.1
462
2.25.1
101
102
diff view generated by jsdifflib
1
Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Message-id: 20220527181907.189259-95-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20200430181003.21682-9-peter.maydell@linaro.org
6
---
7
---
7
target/arm/neon-shared.decode | 5 +++++
8
target/arm/translate-sve.c | 52 +++++++++++++++++---------------------
8
target/arm/translate-neon.inc.c | 40 +++++++++++++++++++++++++++++++++
9
1 file changed, 23 insertions(+), 29 deletions(-)
9
target/arm/translate.c | 26 +--------------------
10
3 files changed, 46 insertions(+), 25 deletions(-)
11
10
12
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
13
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/neon-shared.decode
13
--- a/target/arm/translate-sve.c
15
+++ b/target/arm/neon-shared.decode
14
+++ b/target/arm/translate-sve.c
16
@@ -XXX,XX +XXX,XX @@ VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
17
vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0
16
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
18
VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
17
int mode, gen_helper_gvec_3_ptr *fn)
19
vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
18
{
20
+
19
- if (sve_access_check(s)) {
21
+VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
20
- unsigned vsz = vec_full_reg_size(s);
22
+ vn=%vn_dp vd=%vd_dp size=0
21
- TCGv_i32 tmode = tcg_const_i32(mode);
23
+VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
22
- TCGv_ptr status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
24
+ vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0
23
+ unsigned vsz;
25
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
24
+ TCGv_i32 tmode;
26
index XXXXXXX..XXXXXXX 100644
25
+ TCGv_ptr status;
27
--- a/target/arm/translate-neon.inc.c
26
28
+++ b/target/arm/translate-neon.inc.c
27
- gen_helper_set_rmode(tmode, tmode, status);
29
@@ -XXX,XX +XXX,XX @@ static bool trans_VFML(DisasContext *s, arg_VFML *a)
28
-
30
gen_helper_gvec_fmlal_a32);
29
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
31
return true;
30
- vec_full_reg_offset(s, a->rn),
32
}
31
- pred_full_reg_offset(s, a->pg),
33
+
32
- status, vsz, vsz, 0, fn);
34
+static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
33
-
35
+{
34
- gen_helper_set_rmode(tmode, tmode, status);
36
+ gen_helper_gvec_3_ptr *fn_gvec_ptr;
35
- tcg_temp_free_i32(tmode);
37
+ int opr_sz;
36
- tcg_temp_free_ptr(status);
38
+ TCGv_ptr fpst;
37
+ if (fn == NULL) {
39
+
40
+ if (!dc_isar_feature(aa32_vcma, s)) {
41
+ return false;
38
+ return false;
42
+ }
39
}
43
+ if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {
40
+ if (!sve_access_check(s)) {
44
+ return false;
45
+ }
46
+
47
+ /* UNDEF accesses to D16-D31 if they don't exist. */
48
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
49
+ ((a->vd | a->vn | a->vm) & 0x10)) {
50
+ return false;
51
+ }
52
+
53
+ if ((a->vd | a->vn) & a->q) {
54
+ return false;
55
+ }
56
+
57
+ if (!vfp_access_check(s)) {
58
+ return true;
41
+ return true;
59
+ }
42
+ }
60
+
43
+
61
+ fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx
44
+ vsz = vec_full_reg_size(s);
62
+ : gen_helper_gvec_fcmlah_idx);
45
+ tmode = tcg_const_i32(mode);
63
+ opr_sz = (1 + a->q) * 8;
46
+ status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
64
+ fpst = get_fpstatus_ptr(1);
47
+
65
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
48
+ gen_helper_set_rmode(tmode, tmode, status);
66
+ vfp_reg_offset(1, a->vn),
49
+
67
+ vfp_reg_offset(1, a->vm),
50
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
68
+ fpst, opr_sz, opr_sz,
51
+ vec_full_reg_offset(s, a->rn),
69
+ (a->index << 2) | a->rot, fn_gvec_ptr);
52
+ pred_full_reg_offset(s, a->pg),
70
+ tcg_temp_free_ptr(fpst);
53
+ status, vsz, vsz, 0, fn);
71
+ return true;
54
+
72
+}
55
+ gen_helper_set_rmode(tmode, tmode, status);
73
diff --git a/target/arm/translate.c b/target/arm/translate.c
56
+ tcg_temp_free_i32(tmode);
74
index XXXXXXX..XXXXXXX 100644
57
+ tcg_temp_free_ptr(status);
75
--- a/target/arm/translate.c
58
return true;
76
+++ b/target/arm/translate.c
59
}
77
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
60
78
bool is_long = false, q = extract32(insn, 6, 1);
61
static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
79
bool ptr_is_env = false;
62
{
80
63
- if (a->esz == 0) {
81
- if ((insn & 0xff000f10) == 0xfe000800) {
64
- return false;
82
- /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
65
- }
83
- int rot = extract32(insn, 20, 2);
66
return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz]);
84
- int size = extract32(insn, 23, 1);
67
}
85
- int index;
68
86
-
69
static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
87
- if (!dc_isar_feature(aa32_vcma, s)) {
70
{
88
- return 1;
71
- if (a->esz == 0) {
89
- }
72
- return false;
90
- if (size == 0) {
73
- }
91
- if (!dc_isar_feature(aa32_fp16_arith, s)) {
74
return do_frint_mode(s, a, float_round_up, frint_fns[a->esz]);
92
- return 1;
75
}
93
- }
76
94
- /* For fp16, rm is just Vm, and index is M. */
77
static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
95
- rm = extract32(insn, 0, 4);
78
{
96
- index = extract32(insn, 5, 1);
79
- if (a->esz == 0) {
97
- } else {
80
- return false;
98
- /* For fp32, rm is the usual M:Vm, and index is 0. */
81
- }
99
- VFP_DREG_M(rm, insn);
82
return do_frint_mode(s, a, float_round_down, frint_fns[a->esz]);
100
- index = 0;
83
}
101
- }
84
102
- data = (index << 2) | rot;
85
static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
103
- fn_gvec_ptr = (size ? gen_helper_gvec_fcmlas_idx
86
{
104
- : gen_helper_gvec_fcmlah_idx);
87
- if (a->esz == 0) {
105
- } else if ((insn & 0xffb00f00) == 0xfe200d00) {
88
- return false;
106
+ if ((insn & 0xffb00f00) == 0xfe200d00) {
89
- }
107
/* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
90
return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz]);
108
int u = extract32(insn, 4, 1);
91
}
92
93
static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
94
{
95
- if (a->esz == 0) {
96
- return false;
97
- }
98
return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
99
}
109
100
110
--
101
--
111
2.20.1
102
2.25.1
112
113
diff view generated by jsdifflib
1
We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU
1
From: Richard Henderson <richard.henderson@linaro.org>
2
TLB. However we never actually use the TLB -- all stage 2 lookups
3
are done by direct calls to get_phys_addr_lpae() followed by a
4
physical address load via address_space_ld*().
5
2
6
Remove Stage2 from the list of ARM MMU indexes which correspond to
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
real core MMU indexes, and instead put it in the set of "NOTLB" ARM
4
Message-id: 20220527181907.189259-96-richard.henderson@linaro.org
8
MMU indexes.
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/translate-sve.c | 53 ++++++++++----------------------------
9
1 file changed, 14 insertions(+), 39 deletions(-)
9
10
10
This allows us to drop NB_MMU_MODES to 11. It also means we can
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
11
safely add support for the ARMv8.3-TTS2UXN extension, which adds
12
permission bits to the stage 2 descriptors which define execute
13
permission separatel for EL0 and EL1; supporting that while keeping
14
Stage2 in a QEMU TLB would require us to use separate TLBs for
15
"Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a
16
lot of extra complication given we aren't even using the QEMU TLB.
17
18
In the process of updating the comment on our MMU index use,
19
fix a couple of other minor errors:
20
* NS EL2 EL2&0 was missing from the list in the comment
21
* some text hadn't been updated from when we bumped NB_MMU_MODES
22
above 8
23
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
26
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Message-id: 20200330210400.11724-2-peter.maydell@linaro.org
28
---
29
target/arm/cpu-param.h | 2 +-
30
target/arm/cpu.h | 21 +++++---
31
target/arm/helper.c | 112 ++++-------------------------------------
32
3 files changed, 27 insertions(+), 108 deletions(-)
33
34
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
35
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/cpu-param.h
13
--- a/target/arm/translate-sve.c
37
+++ b/target/arm/cpu-param.h
14
+++ b/target/arm/translate-sve.c
38
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
39
# define TARGET_PAGE_BITS_MIN 10
16
return true;
40
#endif
41
42
-#define NB_MMU_MODES 12
43
+#define NB_MMU_MODES 11
44
45
#endif
46
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/cpu.h
49
+++ b/target/arm/cpu.h
50
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
51
* handling via the TLB. The only way to do a stage 1 translation without
52
* the immediate stage 2 translation is via the ATS or AT system insns,
53
* which can be slow-pathed and always do a page table walk.
54
+ * The only use of stage 2 translations is either as part of an s1+2
55
+ * lookup or when loading the descriptors during a stage 1 page table walk,
56
+ * and in both those cases we don't use the TLB.
57
* 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
58
* translation regimes, because they map reasonably well to each other
59
* and they can't both be active at the same time.
60
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
61
* NS EL1 EL1&0 stage 1+2 (aka NS PL1)
62
* NS EL1 EL1&0 stage 1+2 +PAN
63
* NS EL0 EL2&0
64
+ * NS EL2 EL2&0
65
* NS EL2 EL2&0 +PAN
66
* NS EL2 (aka NS PL2)
67
* S EL0 EL1&0 (aka S PL0)
68
* S EL1 EL1&0 (not used if EL3 is 32 bit)
69
* S EL1 EL1&0 +PAN
70
* S EL3 (aka S PL1)
71
- * NS EL1&0 stage 2
72
*
73
- * for a total of 12 different mmu_idx.
74
+ * for a total of 11 different mmu_idx.
75
*
76
* R profile CPUs have an MPU, but can use the same set of MMU indexes
77
* as A profile. They only need to distinguish NS EL0 and NS EL1 (and
78
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
79
* are not quite the same -- different CPU types (most notably M profile
80
* vs A/R profile) would like to use MMU indexes with different semantics,
81
* but since we don't ever need to use all of those in a single CPU we
82
- * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
83
+ * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
84
+ * modes + total number of M profile MMU modes". The lower bits of
85
* ARMMMUIdx are the core TLB mmu index, and the higher bits are always
86
* the same for any particular CPU.
87
* Variables of type ARMMUIdx are always full values, and the core
88
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
89
ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
90
ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A,
91
92
- ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A,
93
-
94
/*
95
* These are not allocated TLBs and are used only for AT system
96
* instructions or for the first stage of an S12 page table walk.
97
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
98
ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
99
ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
100
ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
101
+ /*
102
+ * Not allocated a TLB: used only for second stage of an S12 page
103
+ * table walk, or for descriptor loads during first stage of an S1
104
+ * page table walk. Note that if we ever want to have a TLB for this
105
+ * then various TLB flush insns which currently are no-ops or flush
106
+ * only stage 1 MMU indexes will need to change to flush stage 2.
107
+ */
108
+ ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB,
109
110
/*
111
* M-profile.
112
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
113
TO_CORE_BIT(SE10_1),
114
TO_CORE_BIT(SE10_1_PAN),
115
TO_CORE_BIT(SE3),
116
- TO_CORE_BIT(Stage2),
117
118
TO_CORE_BIT(MUser),
119
TO_CORE_BIT(MPriv),
120
diff --git a/target/arm/helper.c b/target/arm/helper.c
121
index XXXXXXX..XXXXXXX 100644
122
--- a/target/arm/helper.c
123
+++ b/target/arm/helper.c
124
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
125
tlb_flush_by_mmuidx(cs,
126
ARMMMUIdxBit_E10_1 |
127
ARMMMUIdxBit_E10_1_PAN |
128
- ARMMMUIdxBit_E10_0 |
129
- ARMMMUIdxBit_Stage2);
130
+ ARMMMUIdxBit_E10_0);
131
}
17
}
132
18
133
static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
19
-static bool trans_FRINTN(DisasContext *s, arg_rpr_esz *a)
134
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
135
tlb_flush_by_mmuidx_all_cpus_synced(cs,
136
ARMMMUIdxBit_E10_1 |
137
ARMMMUIdxBit_E10_1_PAN |
138
- ARMMMUIdxBit_E10_0 |
139
- ARMMMUIdxBit_Stage2);
140
+ ARMMMUIdxBit_E10_0);
141
}
142
143
-static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
144
- uint64_t value)
145
-{
20
-{
146
- /* Invalidate by IPA. This has to invalidate any structures that
21
- return do_frint_mode(s, a, float_round_nearest_even, frint_fns[a->esz]);
147
- * contain only stage 2 translation information, but does not need
148
- * to apply to structures that contain combined stage 1 and stage 2
149
- * translation information.
150
- * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
151
- */
152
- CPUState *cs = env_cpu(env);
153
- uint64_t pageaddr;
154
-
155
- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
156
- return;
157
- }
158
-
159
- pageaddr = sextract64(value << 12, 0, 40);
160
-
161
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
162
-}
22
-}
163
-
23
-
164
-static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
24
-static bool trans_FRINTP(DisasContext *s, arg_rpr_esz *a)
165
- uint64_t value)
166
-{
25
-{
167
- CPUState *cs = env_cpu(env);
26
- return do_frint_mode(s, a, float_round_up, frint_fns[a->esz]);
168
- uint64_t pageaddr;
169
-
170
- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
171
- return;
172
- }
173
-
174
- pageaddr = sextract64(value << 12, 0, 40);
175
-
176
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
177
- ARMMMUIdxBit_Stage2);
178
-}
179
180
static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
181
uint64_t value)
182
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
183
tlb_flush_by_mmuidx(cs,
184
ARMMMUIdxBit_E10_1 |
185
ARMMMUIdxBit_E10_1_PAN |
186
- ARMMMUIdxBit_E10_0 |
187
- ARMMMUIdxBit_Stage2);
188
+ ARMMMUIdxBit_E10_0);
189
raw_write(env, ri, value);
190
}
191
}
192
@@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env)
193
return ARMMMUIdxBit_SE10_1 |
194
ARMMMUIdxBit_SE10_1_PAN |
195
ARMMMUIdxBit_SE10_0;
196
- } else if (arm_feature(env, ARM_FEATURE_EL2)) {
197
- return ARMMMUIdxBit_E10_1 |
198
- ARMMMUIdxBit_E10_1_PAN |
199
- ARMMMUIdxBit_E10_0 |
200
- ARMMMUIdxBit_Stage2;
201
} else {
202
return ARMMMUIdxBit_E10_1 |
203
ARMMMUIdxBit_E10_1_PAN |
204
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
205
ARMMMUIdxBit_SE3);
206
}
207
208
-static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
209
- uint64_t value)
210
-{
211
- /* Invalidate by IPA. This has to invalidate any structures that
212
- * contain only stage 2 translation information, but does not need
213
- * to apply to structures that contain combined stage 1 and stage 2
214
- * translation information.
215
- * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
216
- */
217
- ARMCPU *cpu = env_archcpu(env);
218
- CPUState *cs = CPU(cpu);
219
- uint64_t pageaddr;
220
-
221
- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
222
- return;
223
- }
224
-
225
- pageaddr = sextract64(value << 12, 0, 48);
226
-
227
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
228
-}
27
-}
229
-
28
-
230
-static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
29
-static bool trans_FRINTM(DisasContext *s, arg_rpr_esz *a)
231
- uint64_t value)
232
-{
30
-{
233
- CPUState *cs = env_cpu(env);
31
- return do_frint_mode(s, a, float_round_down, frint_fns[a->esz]);
234
- uint64_t pageaddr;
235
-
236
- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
237
- return;
238
- }
239
-
240
- pageaddr = sextract64(value << 12, 0, 48);
241
-
242
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
243
- ARMMMUIdxBit_Stage2);
244
-}
32
-}
245
-
33
-
246
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
34
-static bool trans_FRINTZ(DisasContext *s, arg_rpr_esz *a)
247
bool isread)
35
-{
36
- return do_frint_mode(s, a, float_round_to_zero, frint_fns[a->esz]);
37
-}
38
-
39
-static bool trans_FRINTA(DisasContext *s, arg_rpr_esz *a)
40
-{
41
- return do_frint_mode(s, a, float_round_ties_away, frint_fns[a->esz]);
42
-}
43
+TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a,
44
+ float_round_nearest_even, frint_fns[a->esz])
45
+TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a,
46
+ float_round_up, frint_fns[a->esz])
47
+TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a,
48
+ float_round_down, frint_fns[a->esz])
49
+TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a,
50
+ float_round_to_zero, frint_fns[a->esz])
51
+TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a,
52
+ float_round_ties_away, frint_fns[a->esz])
53
54
static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
55
NULL, gen_helper_sve_frecpx_h,
56
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FCVTLT_hs, aa64_sve2, gen_gvec_fpst_arg_zpz,
57
TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
58
gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
59
60
-static bool trans_FCVTX_ds(DisasContext *s, arg_rpr_esz *a)
61
-{
62
- if (!dc_isar_feature(aa64_sve2, s)) {
63
- return false;
64
- }
65
- return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve_fcvt_ds);
66
-}
67
-
68
-static bool trans_FCVTXNT_ds(DisasContext *s, arg_rpr_esz *a)
69
-{
70
- if (!dc_isar_feature(aa64_sve2, s)) {
71
- return false;
72
- }
73
- return do_frint_mode(s, a, float_round_to_odd, gen_helper_sve2_fcvtnt_ds);
74
-}
75
+TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
76
+ float_round_to_odd, gen_helper_sve_fcvt_ds)
77
+TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
78
+ float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
79
80
static bool trans_FLOGB(DisasContext *s, arg_rpr_esz *a)
248
{
81
{
249
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
250
.writefn = tlbi_aa64_vae1_write },
251
{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
252
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
253
- .access = PL2_W, .type = ARM_CP_NO_RAW,
254
- .writefn = tlbi_aa64_ipas2e1is_write },
255
+ .access = PL2_W, .type = ARM_CP_NOP },
256
{ .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
257
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
258
- .access = PL2_W, .type = ARM_CP_NO_RAW,
259
- .writefn = tlbi_aa64_ipas2e1is_write },
260
+ .access = PL2_W, .type = ARM_CP_NOP },
261
{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
262
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
263
.access = PL2_W, .type = ARM_CP_NO_RAW,
264
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
265
.writefn = tlbi_aa64_alle1is_write },
266
{ .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
267
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
268
- .access = PL2_W, .type = ARM_CP_NO_RAW,
269
- .writefn = tlbi_aa64_ipas2e1_write },
270
+ .access = PL2_W, .type = ARM_CP_NOP },
271
{ .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
272
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
273
- .access = PL2_W, .type = ARM_CP_NO_RAW,
274
- .writefn = tlbi_aa64_ipas2e1_write },
275
+ .access = PL2_W, .type = ARM_CP_NOP },
276
{ .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
277
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
278
.access = PL2_W, .type = ARM_CP_NO_RAW,
279
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
280
.writefn = tlbimva_hyp_is_write },
281
{ .name = "TLBIIPAS2",
282
.cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
283
- .type = ARM_CP_NO_RAW, .access = PL2_W,
284
- .writefn = tlbiipas2_write },
285
+ .type = ARM_CP_NOP, .access = PL2_W },
286
{ .name = "TLBIIPAS2IS",
287
.cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
288
- .type = ARM_CP_NO_RAW, .access = PL2_W,
289
- .writefn = tlbiipas2_is_write },
290
+ .type = ARM_CP_NOP, .access = PL2_W },
291
{ .name = "TLBIIPAS2L",
292
.cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
293
- .type = ARM_CP_NO_RAW, .access = PL2_W,
294
- .writefn = tlbiipas2_write },
295
+ .type = ARM_CP_NOP, .access = PL2_W },
296
{ .name = "TLBIIPAS2LIS",
297
.cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
298
- .type = ARM_CP_NO_RAW, .access = PL2_W,
299
- .writefn = tlbiipas2_is_write },
300
+ .type = ARM_CP_NOP, .access = PL2_W },
301
/* 32 bit cache operations */
302
{ .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
303
.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
304
--
82
--
305
2.20.1
83
2.25.1
306
307
diff view generated by jsdifflib
1
From: Fredrik Strupe <fredrik@strupe.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
According to Arm ARM, VQDMULL is only valid when U=0, while having
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
U=1 is unallocated.
4
Message-id: 20220527181907.189259-97-richard.henderson@linaro.org
5
6
Signed-off-by: Fredrik Strupe <fredrik@strupe.net>
7
Fixes: 695272dcb976 ("target-arm: Handle UNDEF cases for Neon 3-regs-different-widths")
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
7
---
11
target/arm/translate.c | 2 +-
8
target/arm/translate-sve.c | 29 ++++++-----------------------
12
1 file changed, 1 insertion(+), 1 deletion(-)
9
1 file changed, 6 insertions(+), 23 deletions(-)
13
10
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
11
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate.c
13
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate.c
14
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
15
@@ -XXX,XX +XXX,XX @@ TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
19
{0, 0, 0, 0}, /* VMLSL */
16
TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
20
{0, 0, 0, 9}, /* VQDMLSL */
17
float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
21
{0, 0, 0, 0}, /* Integer VMULL */
18
22
- {0, 0, 0, 1}, /* VQDMULL */
19
-static bool trans_FLOGB(DisasContext *s, arg_rpr_esz *a)
23
+ {0, 0, 0, 9}, /* VQDMULL */
20
-{
24
{0, 0, 0, 0xa}, /* Polynomial VMULL */
21
- static gen_helper_gvec_3_ptr * const fns[] = {
25
{0, 0, 0, 7}, /* Reserved: always UNDEF */
22
- NULL, gen_helper_flogb_h,
26
};
23
- gen_helper_flogb_s, gen_helper_flogb_d
24
- };
25
-
26
- if (!dc_isar_feature(aa64_sve2, s) || fns[a->esz] == NULL) {
27
- return false;
28
- }
29
- if (sve_access_check(s)) {
30
- TCGv_ptr status =
31
- fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
32
- unsigned vsz = vec_full_reg_size(s);
33
-
34
- tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
35
- vec_full_reg_offset(s, a->rn),
36
- pred_full_reg_offset(s, a->pg),
37
- status, vsz, vsz, 0, fns[a->esz]);
38
- tcg_temp_free_ptr(status);
39
- }
40
- return true;
41
-}
42
+static gen_helper_gvec_3_ptr * const flogb_fns[] = {
43
+ NULL, gen_helper_flogb_h,
44
+ gen_helper_flogb_s, gen_helper_flogb_d
45
+};
46
+TRANS_FEAT(FLOGB, aa64_sve2, gen_gvec_fpst_arg_zpz, flogb_fns[a->esz],
47
+ a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR)
48
49
static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sub, bool sel)
50
{
27
--
51
--
28
2.20.1
52
2.25.1
29
30
diff view generated by jsdifflib