Series comparison

-[PULL 00/39] target-arm queue
+[PULL 00/17] target-arm queue
-Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups.
+Arm changes for before softfreeze: mostly my PL061/GPIO patches,
 but also a new M-profile board and various other things.
 thanks
 -- PMM
+The following changes since commit 05de778b5b8ab0b402996769117b88c7ea5c7c61:
-The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835:
+  Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-07-09 14:30:01 +0100)
   Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210709
-for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:
+for you to fetch changes up to 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646:
-  target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100)
+  hw/intc: Improve formatting of MEMTX_ERROR guest error message (2021-07-09 16:09:12 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * Start of conversion of Neon insns to decodetree
+ * New machine type: stm32vldiscovery
- * versal board: support SD and RTC
+ * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
- * Implement ARMv8.2-TTS2UXN
+ * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
- * Make VQDMULL undefined when U=1
+ * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
- * Some minor code cleanups
+ * Correct the encoding of MDCCSR_EL0 and DBGDSCRint
  * hw/intc: Improve formatting of MEMTX_ERROR guest error message
 ----------------------------------------------------------------
-Edgar E. Iglesias (11):
+Alexandre Iooss (4):
-      hw/arm: versal: Remove inclusion of arm_gicv3_common.h
+      stm32f100: Add the stm32f100 SoC
-      hw/arm: versal: Move misplaced comment
+      stm32vldiscovery: Add the STM32VLDISCOVERY Machine
-      hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal
+      docs/system: arm: Add stm32 boards description
-      hw/arm: versal: Embed the UARTs into the SoC type
+      tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
       hw/arm: versal: Embed the GEMs into the SoC type
       hw/arm: versal: Embed the ADMAs into the SoC type
       hw/arm: versal: Embed the APUs into the SoC type
       hw/arm: versal: Add support for SD
       hw/arm: versal: Add support for the RTC
       hw/arm: versal-virt: Add support for SD
       hw/arm: versal-virt: Add support for the RTC
-Fredrik Strupe (1):
+Peter Maydell (10):
-      target/arm: Make VQDMULL undefined when U=1
+      hw/gpio/pl061: Convert DPRINTF to tracepoints
       hw/gpio/pl061: Clean up read/write offset handling logic
       hw/gpio/pl061: Add tracepoints for register read and write
       hw/gpio/pl061: Document the interface of this device
       hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
       hw/gpio/pl061: Make pullup/pulldown of outputs configurable
       hw/arm/virt: Make PL061 GPIO lines pulled low, not high
       hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
       hw/gpio/pl061: Document a shortcoming in our implementation
       hw/arm/stellaris: Expand comment about handling of OLED chipselect
-Peter Maydell (25):
+Rebecca Cran (1):
-      target/arm: Don't use a TLB for ARMMMUIdx_Stage2
+      hw/intc: Improve formatting of MEMTX_ERROR guest error message
       target/arm: Use enum constant in get_phys_addr_lpae() call
       target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()
       target/arm: Implement ARMv8.2-TTS2UXN
       target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0
       target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
       target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
       target/arm: Add stubs for AArch32 Neon decodetree
       target/arm: Convert VCMLA (vector) to decodetree
       target/arm: Convert VCADD (vector) to decodetree
       target/arm: Convert V[US]DOT (vector) to decodetree
       target/arm: Convert VFM[AS]L (vector) to decodetree
       target/arm: Convert VCMLA (scalar) to decodetree
       target/arm: Convert V[US]DOT (scalar) to decodetree
       target/arm: Convert VFM[AS]L (scalar) to decodetree
       target/arm: Convert Neon load/store multiple structures to decodetree
       target/arm: Convert Neon 'load single structure to all lanes' to decodetree
       target/arm: Convert Neon 'load/store single structure' to decodetree
       target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
       target/arm: Convert Neon 3-reg-same logic ops to decodetree
       target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
       target/arm: Convert Neon 3-reg-same comparisons to decodetree
       target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
       target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
       target/arm: Move gen_ function typedefs to translate.h
-Philippe Mathieu-Daudé (2):
+Ricardo Koller (1):
-      hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string
+      hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
       target/arm: Use uint64_t for midr field in CPU state struct
- include/hw/arm/xlnx-versal.h    |  31 +-
+hnick@vmware.com (1):
- target/arm/cpu-param.h          |   2 +-
+      target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
  target/arm/cpu.h                |  38 ++-
  target/arm/translate-a64.h      |   9 -
  target/arm/translate.h          |  26 ++
  target/arm/neon-dp.decode       |  86 +++++
  target/arm/neon-ls.decode       |  52 +++
  target/arm/neon-shared.decode   |  66 ++++
  hw/arm/mps2-tz.c                |   2 +-
  hw/arm/xlnx-versal-virt.c       |  74 ++++-
  hw/arm/xlnx-versal.c            | 115 +++++--
  target/arm/cpu.c                |   3 +-
  target/arm/cpu64.c              |   8 +-
  target/arm/helper.c             | 183 ++++------
  target/arm/translate-a64.c      |  17 -
  target/arm/translate-neon.inc.c | 714 +++++++++++++++++++++++++++++++++++++++
  target/arm/translate-vfp.inc.c  |   6 -
  target/arm/translate.c          | 716 +++-------------------------------------
  target/arm/Makefile.objs        |  18 +
 files changed, 1302 insertions(+), 864 deletions(-)
  create mode 100644 target/arm/neon-dp.decode
  create mode 100644 target/arm/neon-ls.decode
  create mode 100644 target/arm/neon-shared.decode
  create mode 100644 target/arm/translate-neon.inc.c
+ docs/system/arm/stm32.rst               |  66 +++++++
+ docs/system/target-arm.rst              |   1 +
+ default-configs/devices/arm-softmmu.mak |   1 +
+ include/hw/arm/stm32f100_soc.h          |  57 ++++++
+ hw/arm/stellaris.c                      |  56 +++++-
+ hw/arm/stm32f100_soc.c                  | 182 +++++++++++++++++
+ hw/arm/stm32vldiscovery.c               |  66 +++++++
+ hw/arm/virt.c                           |   3 +
+ hw/gpio/pl061.c                         | 341 +++++++++++++++++++++++++-------
+ hw/intc/arm_gicv3_cpuif.c               |   4 +-
+ hw/intc/arm_gicv3_redist.c              |   4 +-
+ target/arm/helper.c                     |  16 +-
+ tests/qtest/boot-serial-test.c          |  37 ++++
+ MAINTAINERS                             |  13 ++
+ hw/arm/Kconfig                          |  10 +
+ hw/arm/meson.build                      |   2 +
+ hw/gpio/trace-events                    |   9 +
+files changed, 790 insertions(+), 78 deletions(-)
+ create mode 100644 docs/system/arm/stm32.rst
+ create mode 100644 include/hw/arm/stm32f100_soc.h
+ create mode 100644 hw/arm/stm32f100_soc.c
+ create mode 100644 hw/arm/stm32vldiscovery.c

-[PULL 22/39] target/arm: Add stubs for AArch32 Neon decodetree
+[PULL 01/17] stm32f100: Add the stm32f100 SoC
-Add the infrastructure for building and invoking a decodetree decoder
+From: Alexandre Iooss <erdnaxe@crans.org>
-for the AArch32 Neon encodings.  At the moment the new decoder covers
-nothing, so we always fall back to the existing hand-written decode.
+This SoC is similar to stm32f205 SoC.
+This will be used by the STM32VLDISCOVERY to create a machine.
-We follow the same pattern we did for the VFP decodetree conversion
-(commit 78e138bc1f672c145ef6ace74617d and following): code that deals
+Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
-with Neon will be moving gradually out to translate-neon.vfp.inc,
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-which we #include into translate.c.
+Message-id: 20210617165647.2575955-2-erdnaxe@crans.org
 In order to share the decode files between A32 and T32, we
 split Neon into 3 parts:
  * data-processing
  * load-store
  * 'shared' encodings
 The first two groups of instructions have similar but not identical
 A32 and T32 encodings, so we need to manually transform the T32
 encoding into the A32 one before calling the decoder; the third group
 covers the Neon instructions which are identical in A32 and T32.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-4-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       | 29 ++++++++++++++++++++++++++
+ include/hw/arm/stm32f100_soc.h |  57 +++++++++++
- target/arm/neon-ls.decode       | 29 ++++++++++++++++++++++++++
+ hw/arm/stm32f100_soc.c         | 182 +++++++++++++++++++++++++++++++++
- target/arm/neon-shared.decode   | 27 +++++++++++++++++++++++++
+ MAINTAINERS                    |   6 ++
- target/arm/translate-neon.inc.c | 32 +++++++++++++++++++++++++++++
+ hw/arm/Kconfig                 |   6 ++
- target/arm/translate.c          | 36 +++++++++++++++++++++++++++++++--
+ hw/arm/meson.build             |   1 +
- target/arm/Makefile.objs        | 18 +++++++++++++++++
+files changed, 252 insertions(+)
-files changed, 169 insertions(+), 2 deletions(-)
+ create mode 100644 include/hw/arm/stm32f100_soc.h
- create mode 100644 target/arm/neon-dp.decode
+ create mode 100644 hw/arm/stm32f100_soc.c
- create mode 100644 target/arm/neon-ls.decode
- create mode 100644 target/arm/neon-shared.decode
+diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
  create mode 100644 target/arm/translate-neon.inc.c
 diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/target/arm/neon-dp.decode
++++ b/include/hw/arm/stm32f100_soc.h
 @@ -XXX,XX +XXX,XX @@
-+# AArch32 Neon data-processing instruction descriptions
++/*
-+#
++ * STM32F100 SoC
-+#  Copyright (c) 2020 Linaro, Ltd
++ *
-+#
++ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
-+# This library is free software; you can redistribute it and/or
++ *
-+# modify it under the terms of the GNU Lesser General Public
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
-+# License as published by the Free Software Foundation; either
++ * of this software and associated documentation files (the "Software"), to deal
-+# version 2 of the License, or (at your option) any later version.
++ * in the Software without restriction, including without limitation the rights
-+#
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-+# This library is distributed in the hope that it will be useful,
++ * copies of the Software, and to permit persons to whom the Software is
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * furnished to do so, subject to the following conditions:
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ *
-+# Lesser General Public License for more details.
++ * The above copyright notice and this permission notice shall be included in
-+#
++ * all copies or substantial portions of the Software.
-+# You should have received a copy of the GNU Lesser General Public
++ *
-+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+#
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+# This file is processed by scripts/decodetree.py
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-+#
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-+
++ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-+# Encodings for Neon data processing instructions where the T32 encoding
++ * THE SOFTWARE.
-+# is a simple transformation of the A32 encoding.
++ */
-+# More specifically, this file covers instructions where the A32 encoding is
++
-+#   0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
++#ifndef HW_ARM_STM32F100_SOC_H
-+# and the T32 encoding is
++#define HW_ARM_STM32F100_SOC_H
-+#   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
++
-+# This file works on the A32 encoding only; calling code for T32 has to
++#include "hw/char/stm32f2xx_usart.h"
-+# transform the insn into the A32 version first.
++#include "hw/ssi/stm32f2xx_spi.h"
-diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
++#include "hw/arm/armv7m.h"
 +#include "qom/object.h"
 +
 +#define TYPE_STM32F100_SOC "stm32f100-soc"
 +OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
 +
 +#define STM_NUM_USARTS 3
 +#define STM_NUM_SPIS 2
 +
 +#define FLASH_BASE_ADDRESS 0x08000000
 +#define FLASH_SIZE (128 * 1024)
 +#define SRAM_BASE_ADDRESS 0x20000000
 +#define SRAM_SIZE (8 * 1024)
 +
 +struct STM32F100State {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
 +
 +    /*< public >*/
 +    char *cpu_type;
 +
 +    ARMv7MState armv7m;
 +
 +    STM32F2XXUsartState usart[STM_NUM_USARTS];
 +    STM32F2XXSPIState spi[STM_NUM_SPIS];
 +};
 +
 +#endif
 diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/target/arm/neon-ls.decode
++++ b/hw/arm/stm32f100_soc.c
@@ -XXX,XX +XXX,XX @@
 +# AArch32 Neon load/store instruction descriptions
 +#
 +#  Copyright (c) 2020 Linaro, Ltd
 +#
 +# This library is free software; you can redistribute it and/or
 +# modify it under the terms of the GNU Lesser General Public
 +# License as published by the Free Software Foundation; either
 +# version 2 of the License, or (at your option) any later version.
 +#
 +# This library is distributed in the hope that it will be useful,
 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 +# Lesser General Public License for more details.
 +#
 +# You should have received a copy of the GNU Lesser General Public
 +# License along with this library; if not, see <http://www.gnu.org/licenses/>.
 +
 +#
 +# This file is processed by scripts/decodetree.py
 +#
 +
 +# Encodings for Neon load/store instructions where the T32 encoding
 +# is a simple transformation of the A32 encoding.
 +# More specifically, this file covers instructions where the A32 encoding is
 +#   0b1111_0100_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
 +# and the T32 encoding is
 +#   0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
 +# This file works on the A32 encoding only; calling code for T32 has to
 +# transform the insn into the A32 version first.
 diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@
 +# AArch32 Neon instruction descriptions
 +#
 +#  Copyright (c) 2020 Linaro, Ltd
 +#
 +# This library is free software; you can redistribute it and/or
 +# modify it under the terms of the GNU Lesser General Public
 +# License as published by the Free Software Foundation; either
 +# version 2 of the License, or (at your option) any later version.
 +#
 +# This library is distributed in the hope that it will be useful,
 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 +# Lesser General Public License for more details.
 +#
 +# You should have received a copy of the GNU Lesser General Public
 +# License along with this library; if not, see <http://www.gnu.org/licenses/>.
 +
 +#
 +# This file is processed by scripts/decodetree.py
 +#
 +
 +# Encodings for Neon instructions whose encoding is the same for
 +# both A32 and T32.
 +
 +# More specifically, this covers:
 +# 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
 +# 3same ext:       0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/target/arm/translate-neon.inc.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ *  ARM translation: AArch32 Neon instructions
++ * STM32F100 SoC
 + *
-+ *  Copyright (c) 2003 Fabrice Bellard
++ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
-+ *  Copyright (c) 2005-2007 CodeSourcery
++ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
-+ *  Copyright (c) 2007 OpenedHand, Ltd.
++ *
-+ *  Copyright (c) 2020 Linaro, Ltd.
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
-+ *
++ * of this software and associated documentation files (the "Software"), to deal
-+ * This library is free software; you can redistribute it and/or
++ * in the Software without restriction, including without limitation the rights
-+ * modify it under the terms of the GNU Lesser General Public
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-+ * License as published by the Free Software Foundation; either
++ * copies of the Software, and to permit persons to whom the Software is
-+ * version 2 of the License, or (at your option) any later version.
++ * furnished to do so, subject to the following conditions:
 + *
-+ * This library is distributed in the hope that it will be useful,
++ * The above copyright notice and this permission notice shall be included in
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * all copies or substantial portions of the Software.
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
++ *
-+ * Lesser General Public License for more details.
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-+ *
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-+ * You should have received a copy of the GNU Lesser General Public
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
-+/*
++#include "qemu/osdep.h"
-+ * This file is intended to be included from translate.c; it uses
++#include "qapi/error.h"
-+ * some macros and definitions provided by that file.
++#include "qemu/module.h"
-+ * It might be possible to convert it to a standalone .c file eventually.
++#include "hw/arm/boot.h"
-+ */
++#include "exec/address-spaces.h"
-+
++#include "hw/arm/stm32f100_soc.h"
-+/* Include the generated Neon decoder */
++#include "hw/qdev-properties.h"
-+#include "decode-neon-dp.inc.c"
++#include "hw/misc/unimp.h"
-+#include "decode-neon-ls.inc.c"
++#include "sysemu/sysemu.h"
-+#include "decode-neon-shared.inc.c"
++
-diff --git a/target/arm/translate.c b/target/arm/translate.c
++/* stm32f100_soc implementation is derived from stm32f205_soc */
-index XXXXXXX..XXXXXXX 100644
++
---- a/target/arm/translate.c
++static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
-+++ b/target/arm/translate.c
++    0x40004800 };
-@@ -XXX,XX +XXX,XX @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
++static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
++
- #define ARM_CP_RW_BIT   (1 << 20)
++static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
++static const int spi_irq[STM_NUM_SPIS] = {35, 36};
--/* Include the VFP decoder */
++
-+/* Include the VFP and Neon decoders */
++static void stm32f100_soc_initfn(Object *obj)
- #include "translate-vfp.inc.c"
++{
-+#include "translate-neon.inc.c"
++    STM32F100State *s = STM32F100_SOC(obj);
++    int i;
- static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
++
- {
++    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
++
-         /* Unconditional instructions.  */
++    for (i = 0; i < STM_NUM_USARTS; i++) {
-         /* TODO: Perhaps merge these into one decodetree output file.  */
++        object_initialize_child(obj, "usart[*]", &s->usart[i],
-         if (disas_a32_uncond(s, insn) ||
++                                TYPE_STM32F2XX_USART);
--            disas_vfp_uncond(s, insn)) {
++    }
-+            disas_vfp_uncond(s, insn) ||
++
-+            disas_neon_dp(s, insn) ||
++    for (i = 0; i < STM_NUM_SPIS; i++) {
-+            disas_neon_ls(s, insn) ||
++        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
-+            disas_neon_shared(s, insn)) {
++    }
-             return;
++}
-         }
++
-         /* fall back to legacy decoder */
++static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
++{
-         ARCH(6T2);
++    STM32F100State *s = STM32F100_SOC(dev_soc);
-     }
++    DeviceState *dev, *armv7m;
++    SysBusDevice *busdev;
-+    if ((insn & 0xef000000) == 0xef000000) {
++    int i;
-+        /*
++
-+         * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
++    MemoryRegion *system_memory = get_system_memory();
-+         * transform into
++    MemoryRegion *sram = g_new(MemoryRegion, 1);
-+         * A32 encodings 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
++    MemoryRegion *flash = g_new(MemoryRegion, 1);
-+         */
++    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
-+        uint32_t a32_insn = (insn & 0xe2ffffff) |
++
-+            ((insn & (1 << 28)) >> 4) | (1 << 28);
++    /*
-+
++     * Init flash region
-+        if (disas_neon_dp(s, a32_insn)) {
++     * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
 +     */
 +    memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
 +                           FLASH_SIZE, &error_fatal);
 +    memory_region_init_alias(flash_alias, OBJECT(dev_soc),
 +                             "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
 +    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
 +    memory_region_add_subregion(system_memory, 0, flash_alias);
 +
 +    /* Init SRAM region */
 +    memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
 +                           &error_fatal);
 +    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 +
 +    /* Init ARMv7m */
 +    armv7m = DEVICE(&s->armv7m);
 +    qdev_prop_set_uint32(armv7m, "num-irq", 61);
 +    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
 +    qdev_prop_set_bit(armv7m, "enable-bitband", true);
 +    object_property_set_link(OBJECT(&s->armv7m), "memory",
 +                             OBJECT(get_system_memory()), &error_abort);
 +    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
 +        return;
 +    }
 +
 +    /* Attach UART (uses USART registers) and USART controllers */
 +    for (i = 0; i < STM_NUM_USARTS; i++) {
 +        dev = DEVICE(&(s->usart[i]));
 +        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 +        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
 +            return;
 +        }
-+    }
++        busdev = SYS_BUS_DEVICE(dev);
-+
++        sysbus_mmio_map(busdev, 0, usart_addr[i]);
-+    if ((insn & 0xff100000) == 0xf9000000) {
++        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
-+        /*
++    }
-+         * T32 encodings 0b1111_1001_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
++
-+         * transform into
++    /* SPI 1 and 2 */
-+         * A32 encodings 0b1111_0100_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
++    for (i = 0; i < STM_NUM_SPIS; i++) {
-+         */
++        dev = DEVICE(&(s->spi[i]));
-+        uint32_t a32_insn = (insn & 0x00ffffff) | 0xf4000000;
++        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
 +
 +        if (disas_neon_ls(s, a32_insn)) {
 +            return;
 +        }
-+    }
++        busdev = SYS_BUS_DEVICE(dev);
-+
++        sysbus_mmio_map(busdev, 0, spi_addr[i]);
-     /*
++        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
-      * TODO: Perhaps merge these into one decodetree output file.
++    }
-      * Note disas_vfp is written for a32 with cond field in the
++
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
++    create_unimplemented_device("timer[2]",  0x40000000, 0x400);
-      */
++    create_unimplemented_device("timer[3]",  0x40000400, 0x400);
-     if (disas_t32(s, insn) ||
++    create_unimplemented_device("timer[4]",  0x40000800, 0x400);
-         disas_vfp_uncond(s, insn) ||
++    create_unimplemented_device("timer[6]",  0x40001000, 0x400);
-+        disas_neon_shared(s, insn) ||
++    create_unimplemented_device("timer[7]",  0x40001400, 0x400);
-         ((insn >> 28) == 0xe && disas_vfp(s, insn))) {
++    create_unimplemented_device("RTC",       0x40002800, 0x400);
-         return;
++    create_unimplemented_device("WWDG",      0x40002C00, 0x400);
-     }
++    create_unimplemented_device("IWDG",      0x40003000, 0x400);
-diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
++    create_unimplemented_device("I2C1",      0x40005400, 0x400);
 +    create_unimplemented_device("I2C2",      0x40005800, 0x400);
 +    create_unimplemented_device("BKP",       0x40006C00, 0x400);
 +    create_unimplemented_device("PWR",       0x40007000, 0x400);
 +    create_unimplemented_device("DAC",       0x40007400, 0x400);
 +    create_unimplemented_device("CEC",       0x40007800, 0x400);
 +    create_unimplemented_device("AFIO",      0x40010000, 0x400);
 +    create_unimplemented_device("EXTI",      0x40010400, 0x400);
 +    create_unimplemented_device("GPIOA",     0x40010800, 0x400);
 +    create_unimplemented_device("GPIOB",     0x40010C00, 0x400);
 +    create_unimplemented_device("GPIOC",     0x40011000, 0x400);
 +    create_unimplemented_device("GPIOD",     0x40011400, 0x400);
 +    create_unimplemented_device("GPIOE",     0x40011800, 0x400);
 +    create_unimplemented_device("ADC1",      0x40012400, 0x400);
 +    create_unimplemented_device("timer[1]",  0x40012C00, 0x400);
 +    create_unimplemented_device("timer[15]", 0x40014000, 0x400);
 +    create_unimplemented_device("timer[16]", 0x40014400, 0x400);
 +    create_unimplemented_device("timer[17]", 0x40014800, 0x400);
 +    create_unimplemented_device("DMA",       0x40020000, 0x400);
 +    create_unimplemented_device("RCC",       0x40021000, 0x400);
 +    create_unimplemented_device("Flash Int", 0x40022000, 0x400);
 +    create_unimplemented_device("CRC",       0x40023000, 0x400);
 +}
 +
 +static Property stm32f100_soc_properties[] = {
 +    DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
 +    DEFINE_PROP_END_OF_LIST(),
 +};
 +
 +static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = stm32f100_soc_realize;
 +    device_class_set_props(dc, stm32f100_soc_properties);
 +}
 +
 +static const TypeInfo stm32f100_soc_info = {
 +    .name          = TYPE_STM32F100_SOC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(STM32F100State),
 +    .instance_init = stm32f100_soc_initfn,
 +    .class_init    = stm32f100_soc_class_init,
 +};
 +
 +static void stm32f100_soc_types(void)
 +{
 +    type_register_static(&stm32f100_soc_info);
 +}
 +
 +type_init(stm32f100_soc_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/Makefile.objs
+--- a/MAINTAINERS
-+++ b/target/arm/Makefile.objs
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
+@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
-       $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
+ S: Maintained
-       "GEN", $(TARGET_DIR)$@)
+ F: hw/arm/virt-acpi-build.c
-+target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
++STM32F100
-+    $(call quiet-command,\
++M: Alexandre Iooss <erdnaxe@crans.org>
-+      $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
++L: qemu-arm@nongnu.org
-+      "GEN", $(TARGET_DIR)$@)
++S: Maintained
-+
++F: hw/arm/stm32f100_soc.c
-+target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
++
-+    $(call quiet-command,\
+ STM32F205
-+      $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
+ M: Alistair Francis <alistair@alistair23.me>
-+      "GEN", $(TARGET_DIR)$@)
+ M: Peter Maydell <peter.maydell@linaro.org>
-+
+diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
-+target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
+index XXXXXXX..XXXXXXX 100644
-+    $(call quiet-command,\
+--- a/hw/arm/Kconfig
-+      $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
++++ b/hw/arm/Kconfig
-+      "GEN", $(TARGET_DIR)$@)
+@@ -XXX,XX +XXX,XX @@ config RASPI
-+
+     select SDHCI
- target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
+     select USB_DWC2
-     $(call quiet-command,\
-       $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
++config STM32F100_SOC
-@@ -XXX,XX +XXX,XX @@ target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
++    bool
-       "GEN", $(TARGET_DIR)$@)
++    select ARM_V7M
++    select STM32F2XX_USART
- target/arm/translate-sve.o: target/arm/decode-sve.inc.c
++    select STM32F2XX_SPI
-+target/arm/translate.o: target/arm/decode-neon-shared.inc.c
++
-+target/arm/translate.o: target/arm/decode-neon-dp.inc.c
+ config STM32F205_SOC
-+target/arm/translate.o: target/arm/decode-neon-ls.inc.c
+     bool
- target/arm/translate.o: target/arm/decode-vfp.inc.c
+     select ARM_V7M
- target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
+diff --git a/hw/arm/meson.build b/hw/arm/meson.build
- target/arm/translate.o: target/arm/decode-a32.inc.c
+index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
  arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
  arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
  arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
 +arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
  arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
  arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
  arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
 --
 .20.1

-[PULL 17/39] hw/arm: versal: Add support for the RTC
+[PULL 02/17] stm32vldiscovery: Add the STM32VLDISCOVERY Machine
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Alexandre Iooss <erdnaxe@crans.org>
-hw/arm: versal: Add support for the RTC.
+This is a Cortex-M3 based machine. Information can be found at:
 https://www.st.com/en/evaluation-tools/stm32vldiscovery.html
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
+Message-id: 20210617165647.2575955-3-erdnaxe@crans.org
 Message-id: 20200427181649.26851-10-edgar.iglesias@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/xlnx-versal.h |  8 ++++++++
+ default-configs/devices/arm-softmmu.mak |  1 +
- hw/arm/xlnx-versal.c         | 21 +++++++++++++++++++++
+ hw/arm/stm32vldiscovery.c               | 66 +++++++++++++++++++++++++
-files changed, 29 insertions(+)
+ MAINTAINERS                             |  6 +++
  hw/arm/Kconfig                          |  4 ++
  hw/arm/meson.build                      |  1 +
 files changed, 78 insertions(+)
  create mode 100644 hw/arm/stm32vldiscovery.c
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
+--- a/default-configs/devices/arm-softmmu.mak
-+++ b/include/hw/arm/xlnx-versal.h
++++ b/default-configs/devices/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_CHEETAH=y
  CONFIG_SX1=y
  CONFIG_NSERIES=y
  CONFIG_STELLARIS=y
 +CONFIG_STM32VLDISCOVERY=y
  CONFIG_REALVIEW=y
  CONFIG_VERSATILE=y
  CONFIG_VEXPRESS=y
 diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/arm/stm32vldiscovery.c
 @@ -XXX,XX +XXX,XX @@
- #include "hw/char/pl011.h"
++/*
- #include "hw/dma/xlnx-zdma.h"
++ * ST STM32VLDISCOVERY machine
- #include "hw/net/cadence_gem.h"
++ *
-+#include "hw/rtc/xlnx-zynqmp-rtc.h"
++ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
++ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
- #define TYPE_XLNX_VERSAL "xlnx-versal"
++ *
- #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
++ * Permission is hereby granted, free of charge, to any person obtaining a copy
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
++ * of this software and associated documentation files (the "Software"), to deal
-         struct {
++ * in the Software without restriction, including without limitation the rights
-             SDHCIState sd[XLNX_VERSAL_NR_SDS];
++ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-         } iou;
++ * copies of the Software, and to permit persons to whom the Software is
 + * furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice shall be included in
 + * all copies or substantial portions of the Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 + * THE SOFTWARE.
 + */
 +
-+        XlnxZynqMPRTC rtc;
++#include "qemu/osdep.h"
-     } pmc;
++#include "qapi/error.h"
++#include "hw/boards.h"
-     struct {
++#include "hw/qdev-properties.h"
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
++#include "qemu/error-report.h"
- #define VERSAL_GEM1_IRQ_0          58
++#include "hw/arm/stm32f100_soc.h"
- #define VERSAL_GEM1_WAKE_IRQ_0     59
++#include "hw/arm/boot.h"
- #define VERSAL_ADMA_IRQ_0          60
++
-+#define VERSAL_RTC_APB_ERR_IRQ     121
++/* stm32vldiscovery implementation is derived from netduinoplus2 */
- #define VERSAL_SD0_IRQ_0           126
++
-+#define VERSAL_RTC_ALARM_IRQ       142
++/* Main SYSCLK frequency in Hz (24MHz) */
-+#define VERSAL_RTC_SECONDS_IRQ     143
++#define SYSCLK_FRQ 24000000ULL
++
- /* Architecturally reserved IRQs suitable for virtualization.  */
++static void stm32vldiscovery_init(MachineState *machine)
  #define VERSAL_RSVD_IRQ_FIRST 111
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
  #define MM_PMC_SD0_SIZE             0x10000
  #define MM_PMC_CRP                  0xf1260000U
  #define MM_PMC_CRP_SIZE             0x10000
 +#define MM_PMC_RTC                  0xf12a0000
 +#define MM_PMC_RTC_SIZE             0x10000
  #endif
 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal.c
 +++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_sds(Versal *s, qemu_irq *pic)
      }
  }
 +static void versal_create_rtc(Versal *s, qemu_irq *pic)
 +{
-+    SysBusDevice *sbd;
++    DeviceState *dev;
 +    MemoryRegion *mr;
 +
 +    sysbus_init_child_obj(OBJECT(s), "rtc", &s->pmc.rtc, sizeof(s->pmc.rtc),
 +                          TYPE_XLNX_ZYNQMP_RTC);
 +    sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
 +    qdev_init_nofail(DEVICE(sbd));
 +
 +    mr = sysbus_mmio_get_region(sbd, 0);
 +    memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
 +
 +    /*
-+     * TODO: Connect the ALARM and SECONDS interrupts once our RTC model
++     * TODO: ideally we would model the SoC RCC and let it handle
-+     * supports them.
++     * system_clock_scale, including its ability to define different
 +     * possible SYSCLK sources.
 +     */
-+    sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
++    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
 +
 +    dev = qdev_new(TYPE_STM32F100_SOC);
 +    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
 +    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 +
 +    armv7m_load_kernel(ARM_CPU(first_cpu),
 +                       machine->kernel_filename,
 +                       FLASH_SIZE);
 +}
 +
- /* This takes the board allocated linear DDR memory and creates aliases
++static void stm32vldiscovery_machine_init(MachineClass *mc)
-  * for each split DDR range/aperture on the Versal address map.
++{
-  */
++    mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)";
-@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
++    mc->init = stm32vldiscovery_init;
-     versal_create_gems(s, pic);
++}
-     versal_create_admas(s, pic);
++
-     versal_create_sds(s, pic);
++DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
-+    versal_create_rtc(s, pic);
++
-     versal_map_ddr(s);
+diff --git a/MAINTAINERS b/MAINTAINERS
-     versal_unimp(s);
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/*/stellaris*
  F: include/hw/input/gamepad.h
  F: docs/system/arm/stellaris.rst
 +STM32VLDISCOVERY
 +M: Alexandre Iooss <erdnaxe@crans.org>
 +L: qemu-arm@nongnu.org
 +S: Maintained
 +F: hw/arm/stm32vldiscovery.c
 +
  Versatile Express
  M: Peter Maydell <peter.maydell@linaro.org>
  L: qemu-arm@nongnu.org
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config STELLARIS
      select STELLARIS_ENET # ethernet
      select UNIMP
 +config STM32VLDISCOVERY
 +    bool
 +    select STM32F100_SOC
 +
  config STRONGARM
      bool
      select PXA2XX
 diff --git a/hw/arm/meson.build b/hw/arm/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/meson.build
 +++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
  arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
  arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
  arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
 +arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
  arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
  arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
  arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
 --
 .20.1

-[PULL 09/39] hw/arm: versal: Remove inclusion of arm_gicv3_common.h
+[PULL 03/17] docs/system: arm: Add stm32 boards description
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Alexandre Iooss <erdnaxe@crans.org>
-Remove inclusion of arm_gicv3_common.h, this already gets
+This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY.
 included via xlnx-versal.h.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
+Message-id: 20210617165647.2575955-4-erdnaxe@crans.org
 Message-id: 20200427181649.26851-2-edgar.iglesias@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/xlnx-versal.c | 1 -
+ docs/system/arm/stm32.rst  | 66 ++++++++++++++++++++++++++++++++++++++
-file changed, 1 deletion(-)
+ docs/system/target-arm.rst |  1 +
  MAINTAINERS                |  1 +
 files changed, 68 insertions(+)
  create mode 100644 docs/system/arm/stm32.rst
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
+diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/docs/system/arm/stm32.rst
@@ -XXX,XX +XXX,XX @@
 +STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``)
 +========================================================================================
 +
 +The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
 +STMicroelectronics.
 +
 +.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
 +
 +The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
 +based on this chip :
 +
 +- ``stm32vldiscovery``  STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
 +
 +The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
 +based on this chip :
 +
 +- ``netduino2``         Netduino 2 board with STM32F205RFT6 microcontroller
 +
 +The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
 +compatible with STM32F2 series. The following machines are based on this chip :
 +
 +- ``netduinoplus2``     Netduino Plus 2 board with STM32F405RGT6 microcontroller
 +
 +There are many other STM32 series that are currently not supported by QEMU.
 +
 +Supported devices
 +-----------------
 +
 + * ARM Cortex-M3, Cortex M4F
 + * Analog to Digital Converter (ADC)
 + * EXTI interrupt
 + * Serial ports (USART)
 + * SPI controller
 + * System configuration (SYSCFG)
 + * Timer controller (TIMER)
 +
 +Missing devices
 +---------------
 +
 + * Camera interface (DCMI)
 + * Controller Area Network (CAN)
 + * Cycle Redundancy Check (CRC) calculation unit
 + * Digital to Analog Converter (DAC)
 + * DMA controller
 + * Ethernet controller
 + * Flash Interface Unit
 + * GPIO controller
 + * I2C controller
 + * Inter-Integrated Sound (I2S) controller
 + * Power supply configuration (PWR)
 + * Random Number Generator (RNG)
 + * Real-Time Clock (RTC) controller
 + * Reset and Clock Controller (RCC)
 + * Secure Digital Input/Output (SDIO) interface
 + * USB OTG
 + * Watchdog controller (IWDG, WWDG)
 +
 +Boot options
 +------------
 +
 +The STM32 machines can be started using the ``-kernel`` option to load a
 +firmware. Example:
 +
 +.. code-block:: bash
 +
 +  $ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin
 diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal.c
+--- a/docs/system/target-arm.rst
-+++ b/hw/arm/xlnx-versal.c
++++ b/docs/system/target-arm.rst
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
- #include "hw/arm/boot.h"
+    arm/collie
- #include "kvm_arm.h"
+    arm/sx1
- #include "hw/misc/unimp.h"
+    arm/stellaris
--#include "hw/intc/arm_gicv3_common.h"
++   arm/stm32
- #include "hw/arm/xlnx-versal.h"
+    arm/virt
- #include "hw/char/pl011.h"
+    arm/xlnx-versal-virt
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Alexandre Iooss <erdnaxe@crans.org>
  L: qemu-arm@nongnu.org
  S: Maintained
  F: hw/arm/stm32vldiscovery.c
 +F: docs/system/arm/stm32.rst
  Versatile Express
  M: Peter Maydell <peter.maydell@linaro.org>
 --
 .20.1

-[PULL 01/39] target/arm: Make VQDMULL undefined when U=1
+[PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase
-From: Fredrik Strupe <fredrik@strupe.net>
+From: Alexandre Iooss <erdnaxe@crans.org>
-According to Arm ARM, VQDMULL is only valid when U=0, while having
+New mini-kernel test for STM32VLDISCOVERY USART1.
 U=1 is unallocated.
-Signed-off-by: Fredrik Strupe <fredrik@strupe.net>
+Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
-Fixes: 695272dcb976 ("target-arm: Handle UNDEF cases for Neon 3-regs-different-widths")
+Acked-by: Thomas Huth <thuth@redhat.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Acked-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20210617165647.2575955-5-erdnaxe@crans.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.c | 2 +-
+ tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 37 insertions(+)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/tests/qtest/boot-serial-test.c
-+++ b/target/arm/translate.c
++++ b/tests/qtest/boot-serial-test.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_nrf51[] = {
-                     {0, 0, 0, 0}, /* VMLSL */
+x1c, 0x25, 0x00, 0x40                  /* 0x4000251c = UART TXD */
-                     {0, 0, 0, 9}, /* VQDMLSL */
+ };
-                     {0, 0, 0, 0}, /* Integer VMULL */
--                    {0, 0, 0, 1}, /* VQDMULL */
++static const uint8_t kernel_stm32vldiscovery[] = {
-+                    {0, 0, 0, 9}, /* VQDMULL */
++    0x00, 0x00, 0x00, 0x00,                 /* Stack top address */
-                     {0, 0, 0, 0xa}, /* Polynomial VMULL */
++    0x1d, 0x00, 0x00, 0x00,                 /* Reset handler address */
-                     {0, 0, 0, 7}, /* Reserved: always UNDEF */
++    0x00, 0x00, 0x00, 0x00,                 /* NMI */
-                 };
++    0x00, 0x00, 0x00, 0x00,                 /* Hard fault */
 +    0x00, 0x00, 0x00, 0x00,                 /* Memory management fault */
 +    0x00, 0x00, 0x00, 0x00,                 /* Bus fault */
 +    0x00, 0x00, 0x00, 0x00,                 /* Usage fault */
 +    0x0b, 0x4b,                             /* ldr  r3, [pc, #44] Get RCC */
 +    0x44, 0xf2, 0x04, 0x02,                 /* movw r2, #16388 */
 +    0x1a, 0x60,                             /* str  r2, [r3] */
 +    0x0a, 0x4b,                             /* ldr  r3, [pc, #40] Get GPIOA */
 +    0x1a, 0x68,                             /* ldr  r2, [r3] */
 +    0x22, 0xf0, 0xf0, 0x02,                 /* bic  r2, r2, #240 */
 +    0x1a, 0x60,                             /* str  r2, [r3] */
 +    0x1a, 0x68,                             /* ldr  r2, [r3] */
 +    0x42, 0xf0, 0xb0, 0x02,                 /* orr  r2, r2, #176 */
 +    0x1a, 0x60,                             /* str  r2, [r3] */
 +    0x07, 0x4b,                             /* ldr  r3, [pc, #26] Get BAUD */
 +    0x45, 0x22,                             /* movs r2, #69 */
 +    0x1a, 0x60,                             /* str  r2, [r3] */
 +    0x06, 0x4b,                             /* ldr  r3, [pc, #24] Get ENABLE */
 +    0x42, 0xf2, 0x08, 0x02,                 /* movw r2, #8200 */
 +    0x1a, 0x60,                             /* str  r2, [r3] */
 +    0x05, 0x4b,                             /* ldr  r3, [pc, #20] Get TXD */
 +    0x54, 0x22,                             /* movs r2, 'T' */
 +    0x1a, 0x60,                             /* str  r2, [r3] */
 +    0xfe, 0xe7,                             /* b    . */
 +    0x18, 0x10, 0x02, 0x40,                 /* 0x40021018 = RCC */
 +    0x04, 0x08, 0x01, 0x40,                 /* 0x40010804 = GPIOA */
 +    0x08, 0x38, 0x01, 0x40,                 /* 0x40013808 = USART1 BAUD */
 +    0x0c, 0x38, 0x01, 0x40,                 /* 0x4001380c = USART1 ENABLE */
 +    0x04, 0x38, 0x01, 0x40                  /* 0x40013804 = USART1 TXD */
 +};
 +
  typedef struct testdef {
      const char *arch;       /* Target architecture */
      const char *machine;    /* Name of the machine */
@@ -XXX,XX +XXX,XX @@ static testdef_t tests[] = {
      { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
        kernel_aarch64 },
      { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
 +    { "arm", "stm32vldiscovery", "", "T",
 +      sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
      { NULL }
  };
 --
 .20.1

-[PULL 08/39] target/arm: Use uint64_t for midr field in CPU state struct
+[PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Ricardo Koller <ricarkol@google.com>
-MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.
+icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers
-Represent it in QEMU's ARMCPU struct with a uint64_t, not a
+(like LPIs).  The issue is that these functions check against the number
-uint32_t.
+of implemented IRQs (QEMU's default is num_irq=288) which can be lower
 than the maximum virtual IRQ number (1020 - 1).  The consequence is that
 if a hypervisor creates an LR for an IRQ between 288 and 1020, then the
 guest is unable to deactivate the resulting IRQ. Note that other
 functions that deal with large IRQ numbers, like icv_iar_read, check
 against 1020 and not against num_irq.
-This fixes an error when compiling with -Werror=conversion
+Fix the checks by using GICV3_MAXIRQ (1020) instead of the number of
-because we were manipulating the register value using a
+implemented IRQs.
 local uint64_t variable:
-  target/arm/cpu64.c: In function ‘aarch64_max_initfn’:
+Signed-off-by: Ricardo Koller <ricarkol@google.com>
-  target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]
+Message-id: 20210702233701.3369-1-ricarkol@google.com
 |         cpu->midr = t;
         |                     ^
 and future-proofs us against a possible future architecture
 change using some of the top 32 bits.
 Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Suggested-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20200428172634.29707-1-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h | 2 +-
+ hw/intc/arm_gicv3_cpuif.c | 4 ++--
- target/arm/cpu.c | 2 +-
+file changed, 2 insertions(+), 2 deletions(-)
 files changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/target/arm/cpu.h
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
+@@ -XXX,XX +XXX,XX @@ static void icv_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
-         uint64_t id_aa64dfr0;
-         uint64_t id_aa64dfr1;
+     trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value);
-     } isar;
--    uint32_t midr;
+-    if (irq >= cs->gic->num_irq) {
-+    uint64_t midr;
++    if (irq >= GICV3_MAXIRQ) {
-     uint32_t revidr;
+         /* Also catches special interrupt numbers and LPIs */
-     uint32_t reset_fpsid;
+         return;
-     uint32_t ctr;
+     }
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
-index XXXXXXX..XXXXXXX 100644
+     trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
---- a/target/arm/cpu.c
+                                gicv3_redist_affid(cs), value);
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
+-    if (irq >= cs->gic->num_irq) {
- static Property arm_cpu_properties[] = {
++    if (irq >= GICV3_MAXIRQ) {
-     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
+         /* Also catches special interrupt numbers and LPIs */
-     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
+         return;
--    DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
+     }
 +    DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
      DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
                          mp_affinity, ARM64_AFFINITY_INVALID),
      DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
 --
 .20.1

-[PULL 39/39] target/arm: Move gen_ function typedefs to translate.h
+[PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints
-We're going to want at least some of the NeonGen* typedefs
+Convert the use of the DPRINTF debug macro in the PL061 model to
-for the refactored 32-bit Neon decoder, so move them all
+use tracepoints.
 to translate.h since it makes more sense to keep them in
 one group.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-23-peter.maydell@linaro.org
 ---
- target/arm/translate.h     | 17 +++++++++++++++++
+ hw/gpio/pl061.c      | 27 +++++++++------------------
- target/arm/translate-a64.c | 17 -----------------
+ hw/gpio/trace-events |  6 ++++++
-files changed, 17 insertions(+), 17 deletions(-)
+files changed, 15 insertions(+), 18 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/hw/gpio/pl061.c
-+++ b/target/arm/translate.h
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@ typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+@@ -XXX,XX +XXX,XX @@
- typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
+ #include "qemu/log.h"
-                         uint32_t, uint32_t, uint32_t);
+ #include "qemu/module.h"
+ #include "qom/object.h"
-+/* Function prototype for gen_ functions for calling Neon helpers */
+-
-+typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
+-//#define DEBUG_PL061 1
-+typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
+-
-+typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
+-#ifdef DEBUG_PL061
-+typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
+-#define DPRINTF(fmt, ...) \
-+typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
+-do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
-+typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
+-#define BADF(fmt, ...) \
-+typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
+-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
-+typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
+-#else
-+typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
+-#define DPRINTF(fmt, ...) do {} while(0)
-+typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
+-#define BADF(fmt, ...) \
-+typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
+-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
-+typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
+-#endif
-+typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
++#include "trace.h"
-+typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
-+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
+ static const uint8_t pl061_id[12] =
    { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
      uint8_t out;
      int i;
 -    DPRINTF("dir = %d, data = %d\n", s->dir, s->data);
 +    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
      /* Outputs float high.  */
      /* FIXME: This is board dependent.  */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
          for (i = 0; i < N_GPIOS; i++) {
              mask = 1 << i;
              if (changed & mask) {
 -                DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
 -                qemu_set_irq(s->out[i], (out & mask) != 0);
 +                int level = (out & mask) != 0;
 +                trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
 +                qemu_set_irq(s->out[i], level);
              }
          }
      }
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
          for (i = 0; i < N_GPIOS; i++) {
              mask = 1 << i;
              if (changed & mask) {
 -                DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
 +                trace_pl061_input_change(DEVICE(s)->canonical_path, i,
 +                                         (s->data & mask) != 0);
                  if (!(s->isense & mask)) {
                      /* Edge interrupt */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
      /* Level interrupt */
      s->istate |= ~(s->data ^ s->iev) & s->isense;
 -    DPRINTF("istate = %02X\n", s->istate);
 +    trace_pl061_update_istate(DEVICE(s)->canonical_path,
 +                              s->istate, s->im, (s->istate & s->im) != 0);
      qemu_set_irq(s->irq, (s->istate & s->im) != 0);
  }
 diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/gpio/trace-events
 +++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x
  nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
  nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 +# pl061.c
 +pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
 +pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
 +pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
 +pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 +
- #endif /* TARGET_ARM_TRANSLATE_H */
+ # sifive_gpio.c
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+ sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-index XXXXXXX..XXXXXXX 100644
+ sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ typedef struct AArch64DecodeTable {
      AArch64DecodeFn *disas_fn;
  } AArch64DecodeTable;
 -/* Function prototype for gen_ functions for calling Neon helpers */
 -typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
 -typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
 -typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
 -typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
 -typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
 -typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
 -typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
 -typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
 -typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
 -typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
 -typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
 -typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
 -typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 -typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 -typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 -
  /* initialize TCG globals.  */
  void a64_translate_init(void)
  {
 --
 .20.1

-[PULL 29/39] target/arm: Convert VFM[AS]L (scalar) to decodetree
+[PULL 07/17] hw/gpio/pl061: Clean up read/write offset handling logic
-Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
+Currently the pl061_read() and pl061_write() functions handle offsets
-to decodetree. These are the last ones in the group so we can remove
+using a combination of three if() statements and a switch().  Clean
-all the legacy decode for the group.
+this up to use just a switch, using case ranges.
-Note that in disas_thumb2_insn() the parts of this encoding space
+This requires that instead of catching accesses to the luminary-only
-where the decodetree decoder returns false will correctly be directed
+registers on a stock PL061 via a check on s->rsvd_start we use
-to illegal_op by the "(insn & (1 << 28))" check so they won't fall
+an "is this luminary?" check in the cases for each luminary-only
-into disas_coproc_insn() by mistake.
+register.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-11-peter.maydell@linaro.org
 ---
- target/arm/neon-shared.decode   |   7 +++
+ hw/gpio/pl061.c | 104 ++++++++++++++++++++++++++++++++++++------------
- target/arm/translate-neon.inc.c |  32 ++++++++++
+file changed, 79 insertions(+), 25 deletions(-)
- target/arm/translate.c          | 107 +-------------------------------
-files changed, 40 insertions(+), 106 deletions(-)
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
+--- a/hw/gpio/pl061.c
-+++ b/target/arm/neon-shared.decode
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@ VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
+@@ -XXX,XX +XXX,XX @@ struct PL061State {
+     qemu_irq irq;
- VDOT_scalar    1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
+     qemu_irq out[N_GPIOS];
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp
+     const unsigned char *id;
-+
+-    uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
-+%vfml_scalar_q0_rm 0:3 5:1
+ };
-+%vfml_scalar_q1_index 5:1 3:1
-+VFML_scalar    1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1 index:1 ... \
+ static const VMStateDescription vmstate_pl061 = {
-+               rm=%vfml_scalar_q0_rm vn=%vn_sp vd=%vd_dp q=0
+@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
-+VFML_scalar    1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \
+ {
-+               index=%vfml_scalar_q1_index vn=%vn_dp vd=%vd_dp q=1
+     PL061State *s = (PL061State *)opaque;
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
+-    if (offset < 0x400) {
---- a/target/arm/translate-neon.inc.c
+-        return s->data & (offset >> 2);
-+++ b/target/arm/translate-neon.inc.c
+-    }
-@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
+-    if (offset >= s->rsvd_start && offset <= 0xfcc) {
-     tcg_temp_free_ptr(fpst);
+-        goto err_out;
-     return true;
+-    }
- }
+-    if (offset >= 0xfd0 && offset < 0x1000) {
-+
+-        return s->id[(offset - 0xfd0) >> 2];
-+static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
+-    }
-+{
+     switch (offset) {
-+    int opr_sz;
++    case 0x0 ... 0x3ff: /* Data */
-+
++        return s->data & (offset >> 2);
-+    if (!dc_isar_feature(aa32_fhm, s)) {
+     case 0x400: /* Direction */
-+        return false;
+         return s->dir;
-+    }
+     case 0x404: /* Interrupt sense */
-+
+@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
+     case 0x420: /* Alternate function select */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+         return s->afsel;
-+        ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) {
+     case 0x500: /* 2mA drive */
-+        return false;
++        if (s->id != pl061_id_luminary) {
-+    }
++            goto bad_offset;
-+
++        }
-+    if (a->vd & a->q) {
+         return s->dr2r;
-+        return false;
+     case 0x504: /* 4mA drive */
-+    }
++        if (s->id != pl061_id_luminary) {
-+
++            goto bad_offset;
-+    if (!vfp_access_check(s)) {
++        }
-+        return true;
+         return s->dr4r;
-+    }
+     case 0x508: /* 8mA drive */
-+
++        if (s->id != pl061_id_luminary) {
-+    opr_sz = (1 + a->q) * 8;
++            goto bad_offset;
-+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
++        }
-+                       vfp_reg_offset(a->q, a->vn),
+         return s->dr8r;
-+                       vfp_reg_offset(a->q, a->rm),
+     case 0x50c: /* Open drain */
-+                       cpu_env, opr_sz, opr_sz,
++        if (s->id != pl061_id_luminary) {
-+                       (a->index << 2) | a->s, /* is_2 == 0 */
++            goto bad_offset;
-+                       gen_helper_gvec_fmlal_idx_a32);
++        }
-+    return true;
+         return s->odr;
-+}
+     case 0x510: /* Pull-up */
-diff --git a/target/arm/translate.c b/target/arm/translate.c
++        if (s->id != pl061_id_luminary) {
-index XXXXXXX..XXXXXXX 100644
++            goto bad_offset;
---- a/target/arm/translate.c
++        }
-+++ b/target/arm/translate.c
+         return s->pur;
-@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
+     case 0x514: /* Pull-down */
- }
++        if (s->id != pl061_id_luminary) {
++            goto bad_offset;
- #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
++        }
--#define VFP_SREG(insn, bigbit, smallbit) \
+         return s->pdr;
--  ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
+     case 0x518: /* Slew rate control */
- #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
++        if (s->id != pl061_id_luminary) {
-     if (dc_isar_feature(aa32_simd_r32, s)) { \
++            goto bad_offset;
-         reg = (((insn) >> (bigbit)) & 0x0f) \
++        }
-@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
+         return s->slr;
-         reg = ((insn) >> (bigbit)) & 0x0f; \
+     case 0x51c: /* Digital enable */
-     }} while (0)
++        if (s->id != pl061_id_luminary) {
++            goto bad_offset;
--#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
++        }
- #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
+         return s->den;
--#define VFP_SREG_N(insn) VFP_SREG(insn, 16,  7)
+     case 0x520: /* Lock */
- #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16,  7)
++        if (s->id != pl061_id_luminary) {
--#define VFP_SREG_M(insn) VFP_SREG(insn,  0,  5)
++            goto bad_offset;
- #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn,  0,  5)
++        }
+         return s->locked;
- static void gen_neon_dup_low16(TCGv_i32 var)
+     case 0x524: /* Commit */
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
++        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->cr;
      case 0x528: /* Analog mode select */
 +        if (s->id != pl061_id_luminary) {
 +            goto bad_offset;
 +        }
          return s->amsel;
 +    case 0xfd0 ... 0xfff: /* ID registers */
 +        return s->id[(offset - 0xfd0) >> 2];
      default:
 +    bad_offset:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "pl061_read: Bad offset %x\n", (int)offset);
          break;
      }
 -err_out:
 -    qemu_log_mask(LOG_GUEST_ERROR,
 -                  "pl061_read: Bad offset %x\n", (int)offset);
      return 0;
  }
--/* Advanced SIMD two registers and a scalar extension.
+@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
-- *  31             24   23  22   20   16   12  11   10   9    8        3     0
+     PL061State *s = (PL061State *)opaque;
-- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
+     uint8_t mask;
-- * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
-- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
+-    if (offset < 0x400) {
-- *
++    switch (offset) {
-- */
++    case 0 ... 0x3ff:
--
+         mask = (offset >> 2) & s->dir;
--static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
+         s->data = (s->data & ~mask) | (value & mask);
--{
+         pl061_update(s);
--    gen_helper_gvec_3 *fn_gvec = NULL;
+         return;
--    gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
+-    }
--    int rd, rn, rm, opr_sz, data;
+-    if (offset >= s->rsvd_start) {
--    int off_rn, off_rm;
+-        goto err_out;
--    bool is_long = false, q = extract32(insn, 6, 1);
+-    }
--    bool ptr_is_env = false;
+-    switch (offset) {
--
+     case 0x400: /* Direction */
--    if ((insn & 0xffa00f10) == 0xfe000810) {
+         s->dir = value & 0xff;
--        /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
+         break;
--        int is_s = extract32(insn, 20, 1);
+@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
--        int vm20 = extract32(insn, 0, 3);
+         s->afsel = (s->afsel & ~mask) | (value & mask);
--        int vm3 = extract32(insn, 3, 1);
+         break;
--        int m = extract32(insn, 5, 1);
+     case 0x500: /* 2mA drive */
--        int index;
++        if (s->id != pl061_id_luminary) {
--
++            goto bad_offset;
--        if (!dc_isar_feature(aa32_fhm, s)) {
++        }
--            return 1;
+         s->dr2r = value & 0xff;
--        }
+         break;
--        if (q) {
+     case 0x504: /* 4mA drive */
--            rm = vm20;
++        if (s->id != pl061_id_luminary) {
--            index = m * 2 + vm3;
++            goto bad_offset;
--        } else {
++        }
--            rm = vm20 * 2 + m;
+         s->dr4r = value & 0xff;
--            index = vm3;
+         break;
--        }
+     case 0x508: /* 8mA drive */
--        is_long = true;
++        if (s->id != pl061_id_luminary) {
--        data = (index << 2) | is_s; /* is_2 == 0 */
++            goto bad_offset;
--        fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
++        }
--        ptr_is_env = true;
+         s->dr8r = value & 0xff;
--    } else {
+         break;
--        return 1;
+     case 0x50c: /* Open drain */
--    }
++        if (s->id != pl061_id_luminary) {
--
++            goto bad_offset;
--    VFP_DREG_D(rd, insn);
++        }
--    if (rd & q) {
+         s->odr = value & 0xff;
--        return 1;
+         break;
--    }
+     case 0x510: /* Pull-up */
--    if (q || !is_long) {
++        if (s->id != pl061_id_luminary) {
--        VFP_DREG_N(rn, insn);
++            goto bad_offset;
--        if (rn & q & !is_long) {
++        }
--            return 1;
+         s->pur = value & 0xff;
--        }
+         break;
--        off_rn = vfp_reg_offset(1, rn);
+     case 0x514: /* Pull-down */
--        off_rm = vfp_reg_offset(1, rm);
++        if (s->id != pl061_id_luminary) {
--    } else {
++            goto bad_offset;
--        rn = VFP_SREG_N(insn);
++        }
--        off_rn = vfp_reg_offset(0, rn);
+         s->pdr = value & 0xff;
--        off_rm = vfp_reg_offset(0, rm);
+         break;
--    }
+     case 0x518: /* Slew rate control */
--    if (s->fp_excp_el) {
++        if (s->id != pl061_id_luminary) {
--        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
++            goto bad_offset;
--                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
++        }
--        return 0;
+         s->slr = value & 0xff;
--    }
+         break;
--    if (!s->vfp_enabled) {
+     case 0x51c: /* Digital enable */
--        return 1;
++        if (s->id != pl061_id_luminary) {
--    }
++            goto bad_offset;
--
++        }
--    opr_sz = (1 + q) * 8;
+         s->den = value & 0xff;
--    if (fn_gvec_ptr) {
+         break;
--        TCGv_ptr ptr;
+     case 0x520: /* Lock */
--        if (ptr_is_env) {
++        if (s->id != pl061_id_luminary) {
--            ptr = cpu_env;
++            goto bad_offset;
--        } else {
++        }
--            ptr = get_fpstatus_ptr(1);
+         s->locked = (value != 0xacce551);
--        }
+         break;
--        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
+     case 0x524: /* Commit */
--                           opr_sz, opr_sz, data, fn_gvec_ptr);
++        if (s->id != pl061_id_luminary) {
--        if (!ptr_is_env) {
++            goto bad_offset;
--            tcg_temp_free_ptr(ptr);
++        }
--        }
+         if (!s->locked)
--    } else {
+             s->cr = value & 0xff;
--        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
+         break;
--                           opr_sz, opr_sz, data, fn_gvec);
+     case 0x528:
--    }
++        if (s->id != pl061_id_luminary) {
--    return 0;
++            goto bad_offset;
--}
++        }
--
+         s->amsel = value & 0xff;
- static int disas_coproc_insn(DisasContext *s, uint32_t insn)
+         break;
- {
+     default:
-     int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
+-        goto err_out;
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
++    bad_offset:
-                     }
++        qemu_log_mask(LOG_GUEST_ERROR,
-                 }
++                      "pl061_write: Bad offset %x\n", (int)offset);
-             }
++        return;
 -        } else if ((insn & 0x0f000a00) == 0x0e000800
 -                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
 -            if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
 -                goto illegal_op;
 -            }
 -            return;
          }
          goto illegal_op;
      }
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
+     pl061_update(s);
-             }
+     return;
-             break;
+-err_out:
-         }
+-    qemu_log_mask(LOG_GUEST_ERROR,
--        if ((insn & 0xff000a00) == 0xfe000800
+-                  "pl061_write: Bad offset %x\n", (int)offset);
--            && arm_dc_feature(s, ARM_FEATURE_V8)) {
+ }
--            /* The Thumb2 and ARM encodings are identical.  */
--            if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
+ static void pl061_reset(DeviceState *dev)
--                goto illegal_op;
+@@ -XXX,XX +XXX,XX @@ static void pl061_luminary_init(Object *obj)
--            }
+     PL061State *s = PL061(obj);
--        } else if (((insn >> 24) & 3) == 3) {
-+        if (((insn >> 24) & 3) == 3) {
+     s->id = pl061_id_luminary;
-             /* Translate into the equivalent ARM encoding.  */
+-    s->rsvd_start = 0x52c;
-             insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
+ }
-             if (disas_neon_data_insn(s, insn)) {
  static void pl061_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
      SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
      s->id = pl061_id;
 -    s->rsvd_start = 0x424;
      memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
      sysbus_init_mmio(sbd, &s->iomem);
 --
 .20.1

-[PULL 05/39] target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()
+[PULL 08/17] hw/gpio/pl061: Add tracepoints for register read and write
-For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know
+Add tracepoints for reads and writes to the PL061 registers. This requires
-whether the stage 1 access is for EL0 or not, because whether
+restructuring pl061_read() to only return after the tracepoint, rather
-exec permission is given can depend on whether this is an EL0
+than having lots of early-returns.
 or EL1 access. Add a new argument to get_phys_addr_lpae() so
 the call sites can pass this information in.
 Since get_phys_addr_lpae() doesn't already have a doc comment,
 add one so we have a place to put the documentation of the
 semantics of the new s1_is_el0 argument.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200330210400.11724-4-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 29 ++++++++++++++++++++++++++++-
+ hw/gpio/pl061.c      | 70 ++++++++++++++++++++++++++++++--------------
-file changed, 28 insertions(+), 1 deletion(-)
+ hw/gpio/trace-events |  2 ++
 files changed, 50 insertions(+), 22 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/gpio/pl061.c
-+++ b/target/arm/helper.c
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
+                            unsigned size)
- static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
+ {
-                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
+     PL061State *s = (PL061State *)opaque;
-+                               bool s1_is_el0,
++    uint64_t r = 0;
-                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
-                                target_ulong *page_size_ptr,
+     switch (offset) {
-                                ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
+     case 0x0 ... 0x3ff: /* Data */
-@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
+-        return s->data & (offset >> 2);
 +        r = s->data & (offset >> 2);
 +        break;
      case 0x400: /* Direction */
 -        return s->dir;
 +        r = s->dir;
 +        break;
      case 0x404: /* Interrupt sense */
 -        return s->isense;
 +        r = s->isense;
 +        break;
      case 0x408: /* Interrupt both edges */
 -        return s->ibe;
 +        r = s->ibe;
 +        break;
      case 0x40c: /* Interrupt event */
 -        return s->iev;
 +        r = s->iev;
 +        break;
      case 0x410: /* Interrupt mask */
 -        return s->im;
 +        r = s->im;
 +        break;
      case 0x414: /* Raw interrupt status */
 -        return s->istate;
 +        r = s->istate;
 +        break;
      case 0x418: /* Masked interrupt status */
 -        return s->istate & s->im;
 +        r = s->istate & s->im;
 +        break;
      case 0x420: /* Alternate function select */
 -        return s->afsel;
 +        r = s->afsel;
 +        break;
      case 0x500: /* 2mA drive */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
+-        return s->dr2r;
-         ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
++        r = s->dr2r;
-+                                 false,
++        break;
-                                  &s2pa, &txattrs, &s2prot, &s2size, fi,
+     case 0x504: /* 4mA drive */
-                                  pcacheattrs);
+         if (s->id != pl061_id_luminary) {
-         if (ret) {
+             goto bad_offset;
-@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
+         }
-     };
+-        return s->dr4r;
 +        r = s->dr4r;
 +        break;
      case 0x508: /* 8mA drive */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->dr8r;
 +        r = s->dr8r;
 +        break;
      case 0x50c: /* Open drain */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->odr;
 +        r = s->odr;
 +        break;
      case 0x510: /* Pull-up */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->pur;
 +        r = s->pur;
 +        break;
      case 0x514: /* Pull-down */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->pdr;
 +        r = s->pdr;
 +        break;
      case 0x518: /* Slew rate control */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->slr;
 +        r = s->slr;
 +        break;
      case 0x51c: /* Digital enable */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->den;
 +        r = s->den;
 +        break;
      case 0x520: /* Lock */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->locked;
 +        r = s->locked;
 +        break;
      case 0x524: /* Commit */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->cr;
 +        r = s->cr;
 +        break;
      case 0x528: /* Analog mode select */
          if (s->id != pl061_id_luminary) {
              goto bad_offset;
          }
 -        return s->amsel;
 +        r = s->amsel;
 +        break;
      case 0xfd0 ... 0xfff: /* ID registers */
 -        return s->id[(offset - 0xfd0) >> 2];
 +        r = s->id[(offset - 0xfd0) >> 2];
 +        break;
      default:
      bad_offset:
          qemu_log_mask(LOG_GUEST_ERROR,
                        "pl061_read: Bad offset %x\n", (int)offset);
          break;
      }
 -    return 0;
 +
 +    trace_pl061_read(DEVICE(s)->canonical_path, offset, r);
 +    return r;
  }
-+/**
+ static void pl061_write(void *opaque, hwaddr offset,
-+ * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
+@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
-+ *
+     PL061State *s = (PL061State *)opaque;
-+ * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
+     uint8_t mask;
-+ * prot and page_size may not be filled in, and the populated fsr value provides
-+ * information on why the translation aborted, in the format of a long-format
++    trace_pl061_write(DEVICE(s)->canonical_path, offset, value);
-+ * DFSR/IFSR fault register, with the following caveats:
++
-+ *  * the WnR bit is never set (the caller must do this).
+     switch (offset) {
-+ *
+     case 0 ... 0x3ff:
-+ * @env: CPUARMState
+         mask = (offset >> 2) & s->dir;
-+ * @address: virtual address to get physical address for
+diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
-+ * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
+index XXXXXXX..XXXXXXX 100644
-+ * @mmu_idx: MMU index indicating required translation regime
+--- a/hw/gpio/trace-events
-+ * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
++++ b/hw/gpio/trace-events
-+ *             walk), must be true if this is stage 2 of a stage 1+2 walk for an
+@@ -XXX,XX +XXX,XX @@ pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIOD
-+ *             EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
+ pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
-+ * @phys_ptr: set to the physical address corresponding to the virtual address
+ pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
-+ * @attrs: set to the memory transaction attributes to use
+ pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
-+ * @prot: set to the permissions for the page containing phys_ptr
++pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
-+ * @page_size_ptr: set to the size of the page containing phys_ptr
++pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
-+ * @fi: set to fault info if the translation fails
-+ * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
+ # sifive_gpio.c
-+ */
+ sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
  static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
                                 MMUAccessType access_type, ARMMMUIdx mmu_idx,
 +                               bool s1_is_el0,
                                 hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
                                 target_ulong *page_size_ptr,
                                 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
              /* S1 is done. Now do S2 translation.  */
              ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,
 +                                     mmu_idx == ARMMMUIdx_E10_0,
                                       phys_ptr, attrs, &s2_prot,
                                       page_size, fi,
                                       cacheattrs != NULL ? &cacheattrs2 : NULL);
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
      }
      if (regime_using_lpae_format(env, mmu_idx)) {
 -        return get_phys_addr_lpae(env, address, access_type, mmu_idx,
 +        return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
                                    phys_ptr, attrs, prot, page_size,
                                    fi, cacheattrs);
      } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
 --
 .20.1

-[PULL 32/39] target/arm: Convert Neon 'load/store single structure' to decodetree
+[PULL 09/17] hw/gpio/pl061: Document the interface of this device
-Convert the Neon "load/store single structure to one lane" insns to
+Add a comment documenting the "QEMU interface" of this device:
-decodetree.
+which MMIO regions, IRQ lines, GPIO lines, etc it exposes.
 As this is the last set of insns in the neon load/store group,
 we can remove the whole disas_neon_ls_insn() function.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-14-peter.maydell@linaro.org
 ---
- target/arm/neon-ls.decode       |  11 +++
+ hw/gpio/pl061.c | 7 +++++++
- target/arm/translate-neon.inc.c |  89 +++++++++++++++++++
+file changed, 7 insertions(+)
  target/arm/translate.c          | 147 --------------------------------
 files changed, 100 insertions(+), 147 deletions(-)
-diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-ls.decode
+--- a/hw/gpio/pl061.c
-+++ b/target/arm/neon-ls.decode
++++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
  VLD_all_lanes  1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
                 vd=%vd_dp
 +
 +# Neon load/store single structure to one lane
 +%imm1_5_p1 5:1 !function=plus1
 +%imm1_6_p1 6:1 !function=plus1
 +
 +VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
 +               vd=%vd_dp size=0 stride=1
 +VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \
 +               vd=%vd_dp size=1 stride=%imm1_5_p1
 +VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \
 +               vd=%vd_dp size=2 stride=%imm1_6_p1
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
 @@ -XXX,XX +XXX,XX @@
-  * It might be possible to convert it to a standalone .c file eventually.
+  * Written by Paul Brook
   *
   * This code is licensed under the GPL.
 + *
 + * QEMU interface:
 + *  + sysbus MMIO region 0: the device registers
 + *  + sysbus IRQ: the GPIOINTR interrupt line
 + *  + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines
 + *  + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as
 + *    outputs
   */
-+static inline int plus1(DisasContext *s, int x)
+ #include "qemu/osdep.h"
 +{
 +    return x + 1;
 +}
 +
  /* Include the generated Neon decoder */
  #include "decode-neon-dp.inc.c"
  #include "decode-neon-ls.inc.c"
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
      return true;
  }
 +
 +static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
 +{
 +    /* Neon load/store single structure to one lane */
 +    int reg;
 +    int nregs = a->n + 1;
 +    int vd = a->vd;
 +    TCGv_i32 addr, tmp;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 +
 +    /* UNDEF accesses to D16-D31 if they don't exist */
 +    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
 +        return false;
 +    }
 +
 +    /* Catch the UNDEF cases. This is unavoidably a bit messy. */
 +    switch (nregs) {
 +    case 1:
 +        if (((a->align & (1 << a->size)) != 0) ||
 +            (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
 +            return false;
 +        }
 +        break;
 +    case 3:
 +        if ((a->align & 1) != 0) {
 +            return false;
 +        }
 +        /* fall through */
 +    case 2:
 +        if (a->size == 2 && (a->align & 2) != 0) {
 +            return false;
 +        }
 +        break;
 +    case 4:
 +        if ((a->size == 2) && ((a->align & 3) == 3)) {
 +            return false;
 +        }
 +        break;
 +    default:
 +        abort();
 +    }
 +    if ((vd + a->stride * (nregs - 1)) > 31) {
 +        /*
 +         * Attempts to write off the end of the register file are
 +         * UNPREDICTABLE; we choose to UNDEF because otherwise we would
 +         * access off the end of the array that holds the register data.
 +         */
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    tmp = tcg_temp_new_i32();
 +    addr = tcg_temp_new_i32();
 +    load_reg_var(s, addr, a->rn);
 +    /*
 +     * TODO: if we implemented alignment exceptions, we should check
 +     * addr against the alignment encoded in a->align here.
 +     */
 +    for (reg = 0; reg < nregs; reg++) {
 +        if (a->l) {
 +            gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
 +                            s->be_data | a->size);
 +            neon_store_element(vd, a->reg_idx, a->size, tmp);
 +        } else { /* Store */
 +            neon_load_element(tmp, vd, a->reg_idx, a->size);
 +            gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
 +                            s->be_data | a->size);
 +        }
 +        vd += a->stride;
 +        tcg_gen_addi_i32(addr, addr, 1 << a->size);
 +    }
 +    tcg_temp_free_i32(addr);
 +    tcg_temp_free_i32(tmp);
 +
 +    gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs);
 +
 +    return true;
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
      tcg_temp_free_i32(rd);
  }
 -
 -/* Translate a NEON load/store element instruction.  Return nonzero if the
 -   instruction is invalid.  */
 -static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
 -{
 -    int rd, rn, rm;
 -    int nregs;
 -    int stride;
 -    int size;
 -    int reg;
 -    int load;
 -    TCGv_i32 addr;
 -    TCGv_i32 tmp;
 -
 -    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 -        return 1;
 -    }
 -
 -    /* FIXME: this access check should not take precedence over UNDEF
 -     * for invalid encodings; we will generate incorrect syndrome information
 -     * for attempts to execute invalid vfp/neon encodings with FP disabled.
 -     */
 -    if (s->fp_excp_el) {
 -        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
 -                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
 -        return 0;
 -    }
 -
 -    if (!s->vfp_enabled)
 -      return 1;
 -    VFP_DREG_D(rd, insn);
 -    rn = (insn >> 16) & 0xf;
 -    rm = insn & 0xf;
 -    load = (insn & (1 << 21)) != 0;
 -    if ((insn & (1 << 23)) == 0) {
 -        /* Load store all elements -- handled already by decodetree */
 -        return 1;
 -    } else {
 -        size = (insn >> 10) & 3;
 -        if (size == 3) {
 -            /* Load single element to all lanes -- handled by decodetree  */
 -            return 1;
 -        } else {
 -            /* Single element.  */
 -            int idx = (insn >> 4) & 0xf;
 -            int reg_idx;
 -            switch (size) {
 -            case 0:
 -                reg_idx = (insn >> 5) & 7;
 -                stride = 1;
 -                break;
 -            case 1:
 -                reg_idx = (insn >> 6) & 3;
 -                stride = (insn & (1 << 5)) ? 2 : 1;
 -                break;
 -            case 2:
 -                reg_idx = (insn >> 7) & 1;
 -                stride = (insn & (1 << 6)) ? 2 : 1;
 -                break;
 -            default:
 -                abort();
 -            }
 -            nregs = ((insn >> 8) & 3) + 1;
 -            /* Catch the UNDEF cases. This is unavoidably a bit messy. */
 -            switch (nregs) {
 -            case 1:
 -                if (((idx & (1 << size)) != 0) ||
 -                    (size == 2 && ((idx & 3) == 1 || (idx & 3) == 2))) {
 -                    return 1;
 -                }
 -                break;
 -            case 3:
 -                if ((idx & 1) != 0) {
 -                    return 1;
 -                }
 -                /* fall through */
 -            case 2:
 -                if (size == 2 && (idx & 2) != 0) {
 -                    return 1;
 -                }
 -                break;
 -            case 4:
 -                if ((size == 2) && ((idx & 3) == 3)) {
 -                    return 1;
 -                }
 -                break;
 -            default:
 -                abort();
 -            }
 -            if ((rd + stride * (nregs - 1)) > 31) {
 -                /* Attempts to write off the end of the register file
 -                 * are UNPREDICTABLE; we choose to UNDEF because otherwise
 -                 * the neon_load_reg() would write off the end of the array.
 -                 */
 -                return 1;
 -            }
 -            tmp = tcg_temp_new_i32();
 -            addr = tcg_temp_new_i32();
 -            load_reg_var(s, addr, rn);
 -            for (reg = 0; reg < nregs; reg++) {
 -                if (load) {
 -                    gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
 -                                    s->be_data | size);
 -                    neon_store_element(rd, reg_idx, size, tmp);
 -                } else { /* Store */
 -                    neon_load_element(tmp, rd, reg_idx, size);
 -                    gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
 -                                    s->be_data | size);
 -                }
 -                rd += stride;
 -                tcg_gen_addi_i32(addr, addr, 1 << size);
 -            }
 -            tcg_temp_free_i32(addr);
 -            tcg_temp_free_i32(tmp);
 -            stride = nregs * (1 << size);
 -        }
 -    }
 -    if (rm != 15) {
 -        TCGv_i32 base;
 -
 -        base = load_reg(s, rn);
 -        if (rm == 13) {
 -            tcg_gen_addi_i32(base, base, stride);
 -        } else {
 -            TCGv_i32 index;
 -            index = load_reg(s, rm);
 -            tcg_gen_add_i32(base, base, index);
 -            tcg_temp_free_i32(index);
 -        }
 -        store_reg(s, rn, base);
 -    }
 -    return 0;
 -}
 -
  static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
  {
      switch (size) {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
              }
              return;
          }
 -        if ((insn & 0x0f100000) == 0x04000000) {
 -            /* NEON load/store.  */
 -            if (disas_neon_ls_insn(s, insn)) {
 -                goto illegal_op;
 -            }
 -            return;
 -        }
          if ((insn & 0x0e000f00) == 0x0c000100) {
              if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
                  /* iWMMXt register transfer.  */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
          }
          break;
      case 12:
 -        if ((insn & 0x01100000) == 0x01000000) {
 -            if (disas_neon_ls_insn(s, insn)) {
 -                goto illegal_op;
 -            }
 -            break;
 -        }
          goto illegal_op;
      default:
      illegal_op:
 --
 .20.1

-[PULL 38/39] target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
+[PULL 10/17] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
-Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
+The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR
--reg-same grouping to decodetree.
+which lets the guest configure whether the GPIO lines are pull-up,
 pull-down, or truly floating. Instead of assuming all lines are pulled
 high, honour the PUR and PDR registers.
 For the plain PL061, continue to assume that lines have an external
 pull-up resistor, as we did before.
 The stellaris board actually relies on this behaviour -- the CD line
 of the ssd0323 display device is connected to GPIO output C7, and it
 is only because of a different bug which we're about to fix that we
 weren't incorrectly driving this line high on reset and putting the
 ssd0323 into data mode.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-20-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |  9 +++++++
+ hw/gpio/pl061.c      | 58 +++++++++++++++++++++++++++++++++++++++++---
- target/arm/translate-neon.inc.c | 44 +++++++++++++++++++++++++++++++++
+ hw/gpio/trace-events |  2 +-
- target/arm/translate.c          | 28 +++------------------
+files changed, 55 insertions(+), 5 deletions(-)
 files changed, 56 insertions(+), 25 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+--- a/hw/gpio/pl061.c
-+++ b/target/arm/neon-dp.decode
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@ VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl061 = {
- VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
+     }
- VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
+ };
-+VSHL_S_3s        1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same
++static uint8_t pl061_floating(PL061State *s)
-+VSHL_U_3s        1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same
++{
 +    /*
 +     * Return mask of bits which correspond to pins configured as inputs
 +     * and which are floating (neither pulled up to 1 nor down to 0).
 +     */
 +    uint8_t floating;
 +
- VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
++    if (s->id == pl061_id_luminary) {
- VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
++        /*
- VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
++         * If both PUR and PDR bits are clear, there is neither a pullup
-@@ -XXX,XX +XXX,XX @@ VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
++         * nor a pulldown in place, and the output truly floats.
++         */
- VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
++        floating = ~(s->pur | s->pdr);
- VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
++    } else {
-+
++        /* Assume outputs are pulled high. FIXME: this is board dependent. */
-+VMLA_3s          1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
++        floating = 0;
-+VMLS_3s          1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
++    }
-+
++    return floating & ~s->dir;
 +VMUL_3s          1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
 +VMUL_p_3s        1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
  DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
  DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
  DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
 +DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul)
  #define DO_3SAME_CMP(INSN, COND)                                        \
      static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
@@ -XXX,XX +XXX,XX @@ DO_3SAME_GVEC4(VQADD_S, sqadd_op)
  DO_3SAME_GVEC4(VQADD_U, uqadd_op)
  DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
  DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
 +
 +static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 +                           uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
 +{
 +    tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
 +                       0, gen_helper_gvec_pmul_b);
 +}
 +
-+static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
++static uint8_t pl061_pullups(PL061State *s)
 +{
-+    if (a->size != 0) {
++    /*
-+        return false;
++     * Return mask of bits which correspond to pins configured as inputs
 +     * and which are pulled up to 1.
 +     */
 +    uint8_t pullups;
 +
 +    if (s->id == pl061_id_luminary) {
 +        /*
 +         * The Luminary variant of the PL061 has an extra registers which
 +         * the guest can use to configure whether lines should be pullup
 +         * or pulldown.
 +         */
 +        pullups = s->pur;
 +    } else {
 +        /* Assume outputs are pulled high. FIXME: this is board dependent. */
 +        pullups = 0xff;
 +    }
-+    return do_3same(s, a, gen_VMUL_p_3s);
++    return pullups & ~s->dir;
 +}
 +
-+#define DO_3SAME_GVEC3_NO_SZ_3(INSN, OPARRAY)                           \
+ static void pl061_update(PL061State *s)
-+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+ {
-+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+     uint8_t changed;
-+                                uint32_t oprsz, uint32_t maxsz)         \
+     uint8_t mask;
-+    {                                                                   \
+     uint8_t out;
-+        tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,                          \
+     int i;
-+                       oprsz, maxsz, &OPARRAY[vece]);                   \
++    uint8_t pullups = pl061_pullups(s);
-+    }                                                                   \
++    uint8_t floating = pl061_floating(s);
-+    DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
-+
+-    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
-+
++    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data,
-+DO_3SAME_GVEC3_NO_SZ_3(VMLA, mla_op)
++                       pullups, floating);
-+DO_3SAME_GVEC3_NO_SZ_3(VMLS, mls_op)
-+
+-    /* Outputs float high.  */
-+#define DO_3SAME_GVEC3_SHIFT(INSN, OPARRAY)                             \
+-    /* FIXME: This is board dependent.  */
-+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+-    out = (s->data & s->dir) | ~s->dir;
-+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
++    /*
-+                                uint32_t oprsz, uint32_t maxsz)         \
++     * Pins configured as output are driven from the data register;
-+    {                                                                   \
++     * otherwise if they're pulled up they're 1, and if they're floating
-+        /* Note the operation is vshl vd,vm,vn */                       \
++     * then we give them the same value they had previously, so we don't
-+        tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs,                          \
++     * report any change to the other end.
-+                       oprsz, maxsz, &OPARRAY[vece]);                   \
++     */
-+    }                                                                   \
++    out = (s->data & s->dir) | pullups | (s->old_out_data & floating);
-+    DO_3SAME(INSN, gen_##INSN##_3s)
+     changed = s->old_out_data ^ out;
-+
+     if (changed) {
-+DO_3SAME_GVEC3_SHIFT(VSHL_S, sshl_op)
+         s->old_out_data = out;
-+DO_3SAME_GVEC3_SHIFT(VSHL_U, ushl_op)
+diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/hw/gpio/trace-events
-+++ b/target/arm/translate.c
++++ b/hw/gpio/trace-events
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
-             }
+ nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
-             return 1;
+ # pl061.c
--        case NEON_3R_VMUL: /* VMUL */
+-pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
--            if (u) {
++pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x"
--                /* Polynomial case allows only P8.  */
+ pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
--                if (size != 0) {
+ pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
--                    return 1;
+ pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 -                }
 -                tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
 -                                   0, gen_helper_gvec_pmul_b);
 -            } else {
 -                tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs,
 -                                 vec_size, vec_size);
 -            }
 -            return 0;
 -
 -        case NEON_3R_VML: /* VMLA, VMLS */
 -            tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
 -                           u ? &mls_op[size] : &mla_op[size]);
 -            return 0;
 -
 -        case NEON_3R_VSHL:
 -            /* Note the operation is vshl vd,vm,vn */
 -            tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
 -                           u ? &ushl_op[size] : &sshl_op[size]);
 -            return 0;
 -
          case NEON_3R_VADD_VSUB:
          case NEON_3R_LOGIC:
          case NEON_3R_VMAX:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
          case NEON_3R_VCGE:
          case NEON_3R_VQADD:
          case NEON_3R_VQSUB:
 +        case NEON_3R_VMUL:
 +        case NEON_3R_VML:
 +        case NEON_3R_VSHL:
              /* Already handled by decodetree */
              return 1;
          }
 --
 .20.1

-[PULL 30/39] target/arm: Convert Neon load/store multiple structures to decodetree
+[PULL 11/17] hw/gpio/pl061: Make pullup/pulldown of outputs configurable
-Convert the Neon "load/store multiple structures" insns to decodetree.
+The PL061 GPIO does not itself include pullup or pulldown resistors
 to set the value of a GPIO line treated as an output when it is
 configured as an input (ie when the PL061 itself is not driving it).
 In real hardware it is up to the board to add suitable pullups or
 pulldowns.  Currently our implementation hardwires this to "outputs
 pulled high", which is correct for some boards (eg the realview ones:
 see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S
 User Guide" DUI0224I), but wrong for others.
 In particular, the wiring in the 'virt' board and the gpio-pwr device
 assumes that wires should be pulled low, because otherwise the
 pull-to-high will trigger a shutdown or reset action.  (The only
 reason this doesn't happen immediately on startup is due to another
 bug in the PL061, where we don't assert the GPIOs to the correct
 value on reset, but will do so as soon as the guest touches a
 register and pl061_update() gets called.)
 Add properties to the pl061 so the board can configure whether it
 wants GPIO lines to have pullup, pulldown, or neither.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-12-peter.maydell@linaro.org
 ---
- target/arm/neon-ls.decode       |   7 ++
+ hw/gpio/pl061.c | 51 +++++++++++++++++++++++++++++++++++++++++++++----
- target/arm/translate-neon.inc.c | 124 ++++++++++++++++++++++++++++++++
+file changed, 47 insertions(+), 4 deletions(-)
  target/arm/translate.c          |  91 +----------------------
 files changed, 133 insertions(+), 89 deletions(-)
-diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-ls.decode
+--- a/hw/gpio/pl061.c
-+++ b/target/arm/neon-ls.decode
++++ b/hw/gpio/pl061.c
 @@ -XXX,XX +XXX,XX @@
- #   0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
+  *  + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines
- # This file works on the A32 encoding only; calling code for T32 has to
+  *  + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as
- # transform the insn into the A32 version first.
+  *    outputs
 + *  + QOM property "pullups": an integer defining whether non-floating lines
 + *    configured as inputs should be pulled up to logical 1 (ie whether in
 + *    real hardware they have a pullup resistor on the line out of the PL061).
 + *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
 + *    be pulled high, bit 1 configures line 1, and so on. The default is 0xff,
 + *    indicating that all GPIO lines are pulled up to logical 1.
 + *  + QOM property "pulldowns": an integer defining whether non-floating lines
 + *    configured as inputs should be pulled down to logical 0 (ie whether in
 + *    real hardware they have a pulldown resistor on the line out of the PL061).
 + *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
 + *    be pulled low, bit 1 configures line 1, and so on. The default is 0x0.
 + *    It is an error to set a bit in both "pullups" and "pulldowns". If a bit
 + *    is 0 in both, then the line is considered to be floating, and it will
 + *    not have qemu_set_irq() called on it when it is configured as an input.
   */
  #include "qemu/osdep.h"
  #include "hw/irq.h"
  #include "hw/sysbus.h"
 +#include "hw/qdev-properties.h"
  #include "migration/vmstate.h"
 +#include "qapi/error.h"
  #include "qemu/log.h"
  #include "qemu/module.h"
  #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct PL061State {
      qemu_irq irq;
      qemu_irq out[N_GPIOS];
      const unsigned char *id;
 +    /* Properties, for non-Luminary PL061 */
 +    uint32_t pullups;
 +    uint32_t pulldowns;
  };
  static const VMStateDescription vmstate_pl061 = {
@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_floating(PL061State *s)
           */
          floating = ~(s->pur | s->pdr);
      } else {
 -        /* Assume outputs are pulled high. FIXME: this is board dependent. */
 -        floating = 0;
 +        floating = ~(s->pullups | s->pulldowns);
      }
      return floating & ~s->dir;
  }
@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_pullups(PL061State *s)
           */
          pullups = s->pur;
      } else {
 -        /* Assume outputs are pulled high. FIXME: this is board dependent. */
 -        pullups = 0xff;
 +        pullups = s->pullups;
      }
      return pullups & ~s->dir;
  }
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
      qdev_init_gpio_out(dev, s->out, N_GPIOS);
  }
 +static void pl061_realize(DeviceState *dev, Error **errp)
 +{
 +    PL061State *s = PL061(dev);
 +
-+%vd_dp  22:1 12:4
++    if (s->pullups > 0xff) {
-+
++        error_setg(errp, "pullups property must be between 0 and 0xff");
-+# Neon load/store multiple structures
++        return;
-+
++    }
-+VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
++    if (s->pulldowns > 0xff) {
-+               vd=%vd_dp
++        error_setg(errp, "pulldowns property must be between 0 and 0xff");
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
++        return;
-index XXXXXXX..XXXXXXX 100644
++    }
---- a/target/arm/translate-neon.inc.c
++    if (s->pullups & s->pulldowns) {
-+++ b/target/arm/translate-neon.inc.c
++        error_setg(errp, "no bit may be set both in pullups and pulldowns");
-@@ -XXX,XX +XXX,XX @@ static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
++        return;
                         gen_helper_gvec_fmlal_idx_a32);
      return true;
  }
 +
 +static struct {
 +    int nregs;
 +    int interleave;
 +    int spacing;
 +} const neon_ls_element_type[11] = {
 +    {1, 4, 1},
 +    {1, 4, 2},
 +    {4, 1, 1},
 +    {2, 2, 2},
 +    {1, 3, 1},
 +    {1, 3, 2},
 +    {3, 1, 1},
 +    {1, 1, 1},
 +    {1, 2, 1},
 +    {1, 2, 2},
 +    {2, 1, 1}
 +};
 +
 +static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn,
 +                                      int stride)
 +{
 +    if (rm != 15) {
 +        TCGv_i32 base;
 +
 +        base = load_reg(s, rn);
 +        if (rm == 13) {
 +            tcg_gen_addi_i32(base, base, stride);
 +        } else {
 +            TCGv_i32 index;
 +            index = load_reg(s, rm);
 +            tcg_gen_add_i32(base, base, index);
 +            tcg_temp_free_i32(index);
 +        }
 +        store_reg(s, rn, base);
 +    }
 +}
 +
-+static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
++static Property pl061_props[] = {
-+{
++    DEFINE_PROP_UINT32("pullups", PL061State, pullups, 0xff),
-+    /* Neon load/store multiple structures */
++    DEFINE_PROP_UINT32("pulldowns", PL061State, pulldowns, 0x0),
-+    int nregs, interleave, spacing, reg, n;
++    DEFINE_PROP_END_OF_LIST()
-+    MemOp endian = s->be_data;
++};
 +    int mmu_idx = get_mem_index(s);
 +    int size = a->size;
 +    TCGv_i64 tmp64;
 +    TCGv_i32 addr, tmp;
 +
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ static void pl061_class_init(ObjectClass *klass, void *data)
-+        return false;
+ {
-+    }
+     DeviceClass *dc = DEVICE_CLASS(klass);
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist */
+     dc->vmsd = &vmstate_pl061;
-+    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+     dc->reset = &pl061_reset;
-+        return false;
++    dc->realize = pl061_realize;
-+    }
++    device_class_set_props(dc, pl061_props);
 +    if (a->itype > 10) {
 +        return false;
 +    }
 +    /* Catch UNDEF cases for bad values of align field */
 +    switch (a->itype & 0xc) {
 +    case 4:
 +        if (a->align >= 2) {
 +            return false;
 +        }
 +        break;
 +    case 8:
 +        if (a->align == 3) {
 +            return false;
 +        }
 +        break;
 +    default:
 +        break;
 +    }
 +    nregs = neon_ls_element_type[a->itype].nregs;
 +    interleave = neon_ls_element_type[a->itype].interleave;
 +    spacing = neon_ls_element_type[a->itype].spacing;
 +    if (size == 3 && (interleave | spacing) != 1) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /* For our purposes, bytes are always little-endian.  */
 +    if (size == 0) {
 +        endian = MO_LE;
 +    }
 +    /*
 +     * Consecutive little-endian elements from a single register
 +     * can be promoted to a larger little-endian operation.
 +     */
 +    if (interleave == 1 && endian == MO_LE) {
 +        size = 3;
 +    }
 +    tmp64 = tcg_temp_new_i64();
 +    addr = tcg_temp_new_i32();
 +    tmp = tcg_const_i32(1 << size);
 +    load_reg_var(s, addr, a->rn);
 +    for (reg = 0; reg < nregs; reg++) {
 +        for (n = 0; n < 8 >> size; n++) {
 +            int xs;
 +            for (xs = 0; xs < interleave; xs++) {
 +                int tt = a->vd + reg + spacing * xs;
 +
 +                if (a->l) {
 +                    gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
 +                    neon_store_element64(tt, n, size, tmp64);
 +                } else {
 +                    neon_load_element64(tmp64, tt, n, size);
 +                    gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
 +                }
 +                tcg_gen_add_i32(addr, addr, tmp);
 +            }
 +        }
 +    }
 +    tcg_temp_free_i32(addr);
 +    tcg_temp_free_i32(tmp);
 +    tcg_temp_free_i64(tmp64);
 +
 +    gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
 +    return true;
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
  }
+ static const TypeInfo pl061_info = {
 -static struct {
 -    int nregs;
 -    int interleave;
 -    int spacing;
 -} const neon_ls_element_type[11] = {
 -    {1, 4, 1},
 -    {1, 4, 2},
 -    {4, 1, 1},
 -    {2, 2, 2},
 -    {1, 3, 1},
 -    {1, 3, 2},
 -    {3, 1, 1},
 -    {1, 1, 1},
 -    {1, 2, 1},
 -    {1, 2, 2},
 -    {2, 1, 1}
 -};
 -
  /* Translate a NEON load/store element instruction.  Return nonzero if the
     instruction is invalid.  */
  static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
  {
      int rd, rn, rm;
 -    int op;
      int nregs;
 -    int interleave;
 -    int spacing;
      int stride;
      int size;
      int reg;
      int load;
 -    int n;
      int vec_size;
 -    int mmu_idx;
 -    MemOp endian;
      TCGv_i32 addr;
      TCGv_i32 tmp;
 -    TCGv_i32 tmp2;
 -    TCGv_i64 tmp64;
      if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
          return 1;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
      rn = (insn >> 16) & 0xf;
      rm = insn & 0xf;
      load = (insn & (1 << 21)) != 0;
 -    endian = s->be_data;
 -    mmu_idx = get_mem_index(s);
      if ((insn & (1 << 23)) == 0) {
 -        /* Load store all elements.  */
 -        op = (insn >> 8) & 0xf;
 -        size = (insn >> 6) & 3;
 -        if (op > 10)
 -            return 1;
 -        /* Catch UNDEF cases for bad values of align field */
 -        switch (op & 0xc) {
 -        case 4:
 -            if (((insn >> 5) & 1) == 1) {
 -                return 1;
 -            }
 -            break;
 -        case 8:
 -            if (((insn >> 4) & 3) == 3) {
 -                return 1;
 -            }
 -            break;
 -        default:
 -            break;
 -        }
 -        nregs = neon_ls_element_type[op].nregs;
 -        interleave = neon_ls_element_type[op].interleave;
 -        spacing = neon_ls_element_type[op].spacing;
 -        if (size == 3 && (interleave | spacing) != 1) {
 -            return 1;
 -        }
 -        /* For our purposes, bytes are always little-endian.  */
 -        if (size == 0) {
 -            endian = MO_LE;
 -        }
 -        /* Consecutive little-endian elements from a single register
 -         * can be promoted to a larger little-endian operation.
 -         */
 -        if (interleave == 1 && endian == MO_LE) {
 -            size = 3;
 -        }
 -        tmp64 = tcg_temp_new_i64();
 -        addr = tcg_temp_new_i32();
 -        tmp2 = tcg_const_i32(1 << size);
 -        load_reg_var(s, addr, rn);
 -        for (reg = 0; reg < nregs; reg++) {
 -            for (n = 0; n < 8 >> size; n++) {
 -                int xs;
 -                for (xs = 0; xs < interleave; xs++) {
 -                    int tt = rd + reg + spacing * xs;
 -
 -                    if (load) {
 -                        gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
 -                        neon_store_element64(tt, n, size, tmp64);
 -                    } else {
 -                        neon_load_element64(tmp64, tt, n, size);
 -                        gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
 -                    }
 -                    tcg_gen_add_i32(addr, addr, tmp2);
 -                }
 -            }
 -        }
 -        tcg_temp_free_i32(addr);
 -        tcg_temp_free_i32(tmp2);
 -        tcg_temp_free_i64(tmp64);
 -        stride = nregs * interleave * 8;
 +        /* Load store all elements -- handled already by decodetree */
 +        return 1;
      } else {
          size = (insn >> 10) & 3;
          if (size == 3) {
 --
 .20.1

-[PULL 37/39] target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
+[PULL 12/17] hw/arm/virt: Make PL061 GPIO lines pulled low, not high
-Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping
+For the virt board we have two PL061 devices -- one for NonSecure which
-to decodetree.
+is inputs only, and one for Secure which is outputs only. For the former,
 we don't care whether its outputs are pulled low or high when the line is
 configured as an input, because we don't connect them. For the latter,
 we do care, because we wire the lines up to the gpio-pwr device, which
 assumes that level 1 means "do the action" and 1 means "do nothing".
 For consistency in case we add more outputs in future, configure both
 PL061s to pull GPIO lines down to 0.
+Reported-by: Maxim Uvarov <maxim.uvarov@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-19-peter.maydell@linaro.org
 ---
- target/arm/neon-dp.decode       |  6 ++++++
+ hw/arm/virt.c | 3 +++
- target/arm/translate-neon.inc.c | 15 +++++++++++++++
+file changed, 3 insertions(+)
  target/arm/translate.c          | 14 ++------------
 files changed, 23 insertions(+), 12 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
+--- a/hw/arm/virt.c
-+++ b/target/arm/neon-dp.decode
++++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio,
- @3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
+     MachineState *ms = MACHINE(vms);
-                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
+     pl061_dev = qdev_new("pl061");
-+VQADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
++    /* Pull lines down to 0 if not driven by the PL061 */
-+VQADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
++    qdev_prop_set_uint32(pl061_dev, "pullups", 0);
-+
++    qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
- @3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
+     s = SYS_BUS_DEVICE(pl061_dev);
-                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
+     sysbus_realize_and_unref(s, &error_fatal);
+     memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
@@ -XXX,XX +XXX,XX @@ VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
  VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
  VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
 +VQSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
 +VQSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
 +
  VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
  VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
  VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
      tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);
  }
  DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)
 +
 +#define DO_3SAME_GVEC4(INSN, OPARRAY)                                   \
 +    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
 +                                uint32_t rn_ofs, uint32_t rm_ofs,       \
 +                                uint32_t oprsz, uint32_t maxsz)         \
 +    {                                                                   \
 +        tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),           \
 +                       rn_ofs, rm_ofs, oprsz, maxsz, &OPARRAY[vece]);   \
 +    }                                                                   \
 +    DO_3SAME(INSN, gen_##INSN##_3s)
 +
 +DO_3SAME_GVEC4(VQADD_S, sqadd_op)
 +DO_3SAME_GVEC4(VQADD_U, uqadd_op)
 +DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
 +DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
              }
              return 1;
 -        case NEON_3R_VQADD:
 -            tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
 -                           rn_ofs, rm_ofs, vec_size, vec_size,
 -                           (u ? uqadd_op : sqadd_op) + size);
 -            return 0;
 -
 -        case NEON_3R_VQSUB:
 -            tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
 -                           rn_ofs, rm_ofs, vec_size, vec_size,
 -                           (u ? uqsub_op : sqsub_op) + size);
 -            return 0;
 -
          case NEON_3R_VMUL: /* VMUL */
              if (u) {
                  /* Polynomial case allows only P8.  */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
          case NEON_3R_VTST_VCEQ:
          case NEON_3R_VCGT:
          case NEON_3R_VCGE:
 +        case NEON_3R_VQADD:
 +        case NEON_3R_VQSUB:
              /* Already handled by decodetree */
              return 1;
          }
 --
 .20.1

-[PULL 06/39] target/arm: Implement ARMv8.2-TTS2UXN
+[PULL 13/17] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
-The ARMv8.2-TTS2UXN feature extends the XN field in stage 2
+The PL061 comes out of reset with all its lines configured as input,
-translation table descriptors from just bit [54] to bits [54:53],
+which means they might need to be pulled to 0 or 1 depending on the
-allowing stage 2 to control execution permissions separately for EL0
+'pullups' and 'pulldowns' properties.  Currently we do not assert
-and EL1. Implement the new semantics of the XN field and enable
+these lines on reset; they will only be set whenever the guest first
-the feature for our 'max' CPU.
+touches a register that triggers a call to pl061_update().
 Convert the device to three-phase reset so we have a place where we
 can safely call qemu_set_irq() to set the floating lines to their
 correct values.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200330210400.11724-5-peter.maydell@linaro.org
 ---
- target/arm/cpu.h    | 15 +++++++++++++++
+ hw/gpio/pl061.c      | 29 +++++++++++++++++++++++++----
- target/arm/cpu.c    |  1 +
+ hw/gpio/trace-events |  1 +
- target/arm/cpu64.c  |  2 ++
+files changed, 26 insertions(+), 4 deletions(-)
  target/arm/helper.c | 37 +++++++++++++++++++++++++++++++------
 files changed, 49 insertions(+), 6 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/gpio/pl061.c
-+++ b/target/arm/cpu.h
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
-     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
+     return;
  }
-+static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
+-static void pl061_reset(DeviceState *dev)
 +static void pl061_enter_reset(Object *obj, ResetType type)
  {
 -    PL061State *s = PL061(dev);
 +    PL061State *s = PL061(obj);
 +
 +    trace_pl061_reset(DEVICE(s)->canonical_path);
      /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
      s->data = 0;
 -    s->old_out_data = 0;
      s->old_in_data = 0;
      s->dir = 0;
      s->isense = 0;
@@ -XXX,XX +XXX,XX @@ static void pl061_reset(DeviceState *dev)
      s->amsel = 0;
  }
 +static void pl061_hold_reset(Object *obj)
 +{
-+    return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
++    PL061State *s = PL061(obj);
 +    int i, level;
 +    uint8_t floating = pl061_floating(s);
 +    uint8_t pullups = pl061_pullups(s);
 +
 +    for (i = 0; i < N_GPIOS; i++) {
 +        if (extract32(floating, i, 1)) {
 +            continue;
 +        }
 +        level = extract32(pullups, i, 1);
 +        trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
 +        qemu_set_irq(s->out[i], level);
 +    }
 +    s->old_out_data = pullups;
 +}
 +
- /*
+ static void pl061_set_irq(void * opaque, int irq, int level)
-  * 64-bit feature tests via id registers.
+ {
-  */
+     PL061State *s = (PL061State *)opaque;
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ static Property pl061_props[] = {
-     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
+ static void pl061_class_init(ObjectClass *klass, void *data)
  {
      DeviceClass *dc = DEVICE_CLASS(klass);
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
      dc->vmsd = &vmstate_pl061;
 -    dc->reset = &pl061_reset;
      dc->realize = pl061_realize;
      device_class_set_props(dc, pl061_props);
 +    rc->phases.enter = pl061_enter_reset;
 +    rc->phases.hold = pl061_hold_reset;
  }
-+static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
+ static const TypeInfo pl061_info = {
-+{
+diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
 +    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
 +}
 +
  /*
   * Feature tests for "does this exist in either 32-bit or 64-bit?"
   */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
      return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
  }
 +static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
 +{
 +    return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
 +}
 +
  /*
   * Forward to the above feature tests given an ARMCPU pointer.
   */
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/hw/gpio/trace-events
-+++ b/target/arm/cpu.c
++++ b/hw/gpio/trace-events
-@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to
-             t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+ pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
-             t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+ pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
-             t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+ pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
-+            t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
++pl061_reset(const char *id) "%s reset"
-             cpu->isar.id_mmfr4 = t;
-         }
+ # sifive_gpio.c
- #endif
+ sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
          t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
          t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
          t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
 +        t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
          cpu->isar.id_aa64mmfr1 = t;
          t = cpu->isar.id_aa64mmfr2;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
          u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
          u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
          u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
 +        u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
          cpu->isar.id_mmfr4 = u;
          u = cpu->isar.id_aa64dfr0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
   *
   * @env:     CPUARMState
   * @s2ap:    The 2-bit stage2 access permissions (S2AP)
 - * @xn:      XN (execute-never) bit
 + * @xn:      XN (execute-never) bits
 + * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
   */
 -static int get_S2prot(CPUARMState *env, int s2ap, int xn)
 +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
  {
      int prot = 0;
@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn)
      if (s2ap & 2) {
          prot |= PAGE_WRITE;
      }
 -    if (!xn) {
 -        if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
 +
 +    if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {
 +        switch (xn) {
 +        case 0:
              prot |= PAGE_EXEC;
 +            break;
 +        case 1:
 +            if (s1_is_el0) {
 +                prot |= PAGE_EXEC;
 +            }
 +            break;
 +        case 2:
 +            break;
 +        case 3:
 +            if (!s1_is_el0) {
 +                prot |= PAGE_EXEC;
 +            }
 +            break;
 +        default:
 +            g_assert_not_reached();
 +        }
 +    } else {
 +        if (!extract32(xn, 1, 1)) {
 +            if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
 +                prot |= PAGE_EXEC;
 +            }
          }
      }
      return prot;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
      }
      ap = extract32(attrs, 4, 2);
 -    xn = extract32(attrs, 12, 1);
      if (mmu_idx == ARMMMUIdx_Stage2) {
          ns = true;
 -        *prot = get_S2prot(env, ap, xn);
 +        xn = extract32(attrs, 11, 2);
 +        *prot = get_S2prot(env, ap, xn, s1_is_el0);
      } else {
          ns = extract32(attrs, 3, 1);
 +        xn = extract32(attrs, 12, 1);
          pxn = extract32(attrs, 11, 1);
          *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
      }
 --
 .20.1

-[PULL 31/39] target/arm: Convert Neon 'load single structure to all lanes' to decodetree
+[PULL 14/17] hw/gpio/pl061: Document a shortcoming in our implementation
-Convert the Neon "load single structure to all lanes" insns to
+The Luminary PL061s in the Stellaris LM3S9695 don't all have the same
-decodetree.
+reset value for GPIOPUR.  We can get away with not letting the board
 configure the PUR reset value because we don't actually wire anything
 up to the lines which should reset to pull-up.  Add a comment noting
 this omission.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200430181003.21682-13-peter.maydell@linaro.org
 ---
- target/arm/neon-ls.decode       |  5 +++
+ hw/gpio/pl061.c | 9 +++++++++
- target/arm/translate-neon.inc.c | 73 +++++++++++++++++++++++++++++++++
+file changed, 9 insertions(+)
  target/arm/translate.c          | 55 +------------------------
 files changed, 80 insertions(+), 53 deletions(-)
-diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
+diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-ls.decode
+--- a/hw/gpio/pl061.c
-+++ b/target/arm/neon-ls.decode
++++ b/hw/gpio/pl061.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void pl061_enter_reset(Object *obj, ResetType type)
+     trace_pl061_reset(DEVICE(s)->canonical_path);
- VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
-                vd=%vd_dp
+     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
 +
 +# Neon load single element to all lanes
 +
 +VLD_all_lanes  1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
 +               vd=%vd_dp
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
      gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
      return true;
  }
 +
 +static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
 +{
 +    /* Neon load single structure to all lanes */
 +    int reg, stride, vec_size;
 +    int vd = a->vd;
 +    int size = a->size;
 +    int nregs = a->n + 1;
 +    TCGv_i32 addr, tmp;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 +
 +    /* UNDEF accesses to D16-D31 if they don't exist */
 +    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
 +        return false;
 +    }
 +
 +    if (size == 3) {
 +        if (nregs != 4 || a->a == 0) {
 +            return false;
 +        }
 +        /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */
 +        size = 2;
 +    }
 +    if (nregs == 1 && a->a == 1 && size == 0) {
 +        return false;
 +    }
 +    if (nregs == 3 && a->a == 1) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
-+     * VLD1 to all lanes: T bit indicates how many Dregs to write.
++     * FIXME: For the LM3S6965, not all of the PL061 instances have the
-+     * VLD2/3/4 to all lanes: T bit indicates register stride.
++     * same reset values for GPIOPUR, GPIOAFSEL and GPIODEN, so in theory
 +     * we should allow the board to configure these via properties.
 +     * In practice, we don't wire anything up to the affected GPIO lines
 +     * (PB7, PC0, PC1, PC2, PC3 -- they're used for JTAG), so we can
 +     * get away with this inaccuracy.
 +     */
-+    stride = a->t ? 2 : 1;
+     s->data = 0;
-+    vec_size = nregs == 1 ? stride * 8 : 8;
+     s->old_in_data = 0;
-+
+     s->dir = 0;
 +    tmp = tcg_temp_new_i32();
 +    addr = tcg_temp_new_i32();
 +    load_reg_var(s, addr, a->rn);
 +    for (reg = 0; reg < nregs; reg++) {
 +        gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
 +                        s->be_data | size);
 +        if ((vd & 1) && vec_size == 16) {
 +            /*
 +             * We cannot write 16 bytes at once because the
 +             * destination is unaligned.
 +             */
 +            tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
 +                                 8, 8, tmp);
 +            tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),
 +                             neon_reg_offset(vd, 0), 8, 8);
 +        } else {
 +            tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
 +                                 vec_size, vec_size, tmp);
 +        }
 +        tcg_gen_addi_i32(addr, addr, 1 << size);
 +        vd += stride;
 +    }
 +    tcg_temp_free_i32(tmp);
 +    tcg_temp_free_i32(addr);
 +
 +    gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << size) * nregs);
 +
 +    return true;
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
      int size;
      int reg;
      int load;
 -    int vec_size;
      TCGv_i32 addr;
      TCGv_i32 tmp;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
      } else {
          size = (insn >> 10) & 3;
          if (size == 3) {
 -            /* Load single element to all lanes.  */
 -            int a = (insn >> 4) & 1;
 -            if (!load) {
 -                return 1;
 -            }
 -            size = (insn >> 6) & 3;
 -            nregs = ((insn >> 8) & 3) + 1;
 -
 -            if (size == 3) {
 -                if (nregs != 4 || a == 0) {
 -                    return 1;
 -                }
 -                /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
 -                size = 2;
 -            }
 -            if (nregs == 1 && a == 1 && size == 0) {
 -                return 1;
 -            }
 -            if (nregs == 3 && a == 1) {
 -                return 1;
 -            }
 -            addr = tcg_temp_new_i32();
 -            load_reg_var(s, addr, rn);
 -
 -            /* VLD1 to all lanes: bit 5 indicates how many Dregs to write.
 -             * VLD2/3/4 to all lanes: bit 5 indicates register stride.
 -             */
 -            stride = (insn & (1 << 5)) ? 2 : 1;
 -            vec_size = nregs == 1 ? stride * 8 : 8;
 -
 -            tmp = tcg_temp_new_i32();
 -            for (reg = 0; reg < nregs; reg++) {
 -                gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
 -                                s->be_data | size);
 -                if ((rd & 1) && vec_size == 16) {
 -                    /* We cannot write 16 bytes at once because the
 -                     * destination is unaligned.
 -                     */
 -                    tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0),
 -                                         8, 8, tmp);
 -                    tcg_gen_gvec_mov(0, neon_reg_offset(rd + 1, 0),
 -                                     neon_reg_offset(rd, 0), 8, 8);
 -                } else {
 -                    tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0),
 -                                         vec_size, vec_size, tmp);
 -                }
 -                tcg_gen_addi_i32(addr, addr, 1 << size);
 -                rd += stride;
 -            }
 -            tcg_temp_free_i32(tmp);
 -            tcg_temp_free_i32(addr);
 -            stride = (1 << size) * nregs;
 +            /* Load single element to all lanes -- handled by decodetree  */
 +            return 1;
          } else {
              /* Single element.  */
              int idx = (insn >> 4) & 0xf;
 --
 .20.1

-[PULL 27/39] target/arm: Convert VCMLA (scalar) to decodetree
+[PULL 15/17] hw/arm/stellaris: Expand comment about handling of OLED chipselect
-Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.
+The stellaris board doesn't emulate the handling of the OLED
 chipselect line correctly.  Expand the comment describing this,
 including a sketch of the theoretical correct way to do it.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-9-peter.maydell@linaro.org
 ---
- target/arm/neon-shared.decode   |  5 +++++
+ hw/arm/stellaris.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
- target/arm/translate-neon.inc.c | 40 +++++++++++++++++++++++++++++++++
+file changed, 55 insertions(+), 1 deletion(-)
  target/arm/translate.c          | 26 +--------------------
 files changed, 46 insertions(+), 25 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
+--- a/hw/arm/stellaris.c
-+++ b/target/arm/neon-shared.decode
++++ b/hw/arm/stellaris.c
-@@ -XXX,XX +XXX,XX @@ VFML           1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
-                vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0
+             DeviceState *sddev;
- VFML           1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
+             DeviceState *ssddev;
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
-+
+-            /* Some boards have both an OLED controller and SD card connected to
-+VCMLA_scalar   1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
++            /*
-+               vn=%vn_dp vd=%vd_dp size=0
++             * Some boards have both an OLED controller and SD card connected to
-+VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
+              * the same SSI port, with the SD card chip select connected to a
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0
+              * GPIO pin.  Technically the OLED chip select is connected to the
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
+              * SSI Fss pin.  We do not bother emulating that as both devices
-index XXXXXXX..XXXXXXX 100644
+              * should never be selected simultaneously, and our OLED controller
---- a/target/arm/translate-neon.inc.c
+              * ignores stray 0xff commands that occur when deselecting the SD
-+++ b/target/arm/translate-neon.inc.c
+              * card.
-@@ -XXX,XX +XXX,XX @@ static bool trans_VFML(DisasContext *s, arg_VFML *a)
++             *
-                        gen_helper_gvec_fmlal_a32);
++             * The h/w wiring is:
-     return true;
++             *  - GPIO pin D0 is wired to the active-low SD card chip select
- }
++             *  - GPIO pin A3 is wired to the active-low OLED chip select
-+
++             *  - The SoC wiring of the PL061 "auxiliary function" for A3 is
-+static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
++             *    SSI0Fss ("frame signal"), which is an output from the SoC's
-+{
++             *    SSI controller. The SSI controller takes SSI0Fss low when it
-+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
++             *    transmits a frame, so it can work as a chip-select signal.
-+    int opr_sz;
++             *  - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
-+    TCGv_ptr fpst;
++             *    (the OLED never sends data to the CPU, so no wiring needed)
-+
++             *  - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
-+    if (!dc_isar_feature(aa32_vcma, s)) {
++             *    and the OLED display-data-in
-+        return false;
++             *  - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
-+    }
++             *    serial-clock input
-+    if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {
++             * So a guest that wants to use the OLED can configure the PL061
-+        return false;
++             * to make pins A2, A3, A5 aux-function, so they are connected
-+    }
++             * directly to the SSI controller. When the SSI controller sends
-+
++             * data it asserts SSI0Fss which selects the OLED.
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
++             * A guest that wants to use the SD card configures A2, A4 and A5
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
++             * as aux-function, but leaves A3 as a software-controlled GPIO
-+        ((a->vd | a->vn | a->vm) & 0x10)) {
++             * line. It asserts the SD card chip-select by using the PL061
-+        return false;
++             * to control pin D0, and lets the SSI controller handle Clk, Tx
-+    }
++             * and Rx. (The SSI controller asserts Fss during tx cycles as
-+
++             * usual, but because A3 is not set to aux-function this is not
-+    if ((a->vd | a->vn) & a->q) {
++             * forwarded to the OLED, and so the OLED stays unselected.)
-+        return false;
++             *
-+    }
++             * The QEMU implementation instead is:
-+
++             *  - GPIO pin D0 is wired to the active-low SD card chip select,
-+    if (!vfp_access_check(s)) {
++             *    and also to the OLED chip-select which is implemented
-+        return true;
++             *    as *active-high*
-+    }
++             *  - SSI controller signals go to the devices regardless of
-+
++             *    whether the guest programs A2, A4, A5 as aux-function or not
-+    fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx
++             *
-+                   : gen_helper_gvec_fcmlah_idx);
++             * The problem with this implementation is if the guest doesn't
-+    opr_sz = (1 + a->q) * 8;
++             * care about the SD card and only uses the OLED. In that case it
-+    fpst = get_fpstatus_ptr(1);
++             * may choose never to do anything with D0 (leaving it in its
-+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
++             * default floating state, which reliably leaves the card disabled
-+                       vfp_reg_offset(1, a->vn),
++             * because an SD card has a pullup on CS within the card itself),
-+                       vfp_reg_offset(1, a->vm),
++             * and only set up A2, A3, A5. This for us would mean the OLED
-+                       fpst, opr_sz, opr_sz,
++             * never gets the chip-select assert it needs. We work around
-+                       (a->index << 2) | a->rot, fn_gvec_ptr);
++             * this with a manual raise of D0 here (despite board creation
-+    tcg_temp_free_ptr(fpst);
++             * code being the wrong place to raise IRQ lines) to put the OLED
-+    return true;
++             * into an initially selected state.
-+}
++             *
-diff --git a/target/arm/translate.c b/target/arm/translate.c
++             * In theory the right way to model this would be:
-index XXXXXXX..XXXXXXX 100644
++             *  - Implement aux-function support in the PL061, with an
---- a/target/arm/translate.c
++             *    extra set of AFIN and AFOUT GPIO lines (set up so that
-+++ b/target/arm/translate.c
++             *    if a GPIO line is in auxfn mode the main GPIO in and out
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
++             *    track the AFIN and AFOUT lines)
-     bool is_long = false, q = extract32(insn, 6, 1);
++             *  - Wire the AFOUT for D0 up to either a line from the
-     bool ptr_is_env = false;
++             *    SSI controller that's pulled low around every transmit,
++             *    or at least to an always-0 line here on the board
--    if ((insn & 0xff000f10) == 0xfe000800) {
++             *  - Make the ssd0323 OLED controller chipselect active-low
--        /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
+              */
--        int rot = extract32(insn, 20, 2);
+             bus = qdev_get_child_bus(dev, "ssi");
 -        int size = extract32(insn, 23, 1);
 -        int index;
 -
 -        if (!dc_isar_feature(aa32_vcma, s)) {
 -            return 1;
 -        }
 -        if (size == 0) {
 -            if (!dc_isar_feature(aa32_fp16_arith, s)) {
 -                return 1;
 -            }
 -            /* For fp16, rm is just Vm, and index is M.  */
 -            rm = extract32(insn, 0, 4);
 -            index = extract32(insn, 5, 1);
 -        } else {
 -            /* For fp32, rm is the usual M:Vm, and index is 0.  */
 -            VFP_DREG_M(rm, insn);
 -            index = 0;
 -        }
 -        data = (index << 2) | rot;
 -        fn_gvec_ptr = (size ? gen_helper_gvec_fcmlas_idx
 -                       : gen_helper_gvec_fcmlah_idx);
 -    } else if ((insn & 0xffb00f00) == 0xfe200d00) {
 +    if ((insn & 0xffb00f00) == 0xfe200d00) {
          /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
          int u = extract32(insn, 4, 1);
 --
 .20.1

-[PULL 04/39] target/arm: Use enum constant in get_phys_addr_lpae() call
+[PULL 16/17] target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint
-The access_type argument to get_phys_addr_lpae() is an MMUAccessType;
+From: "hnick@vmware.com" <hnick@vmware.com>
 use the enum constant MMU_DATA_LOAD rather than a literal 0 when we
 call it in S1_ptw_translate().
+Signed-off-by: Nick Hudson <hnick@vmware.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200330210400.11724-3-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 5 +++--
+ target/arm/helper.c | 16 +++++++++++++---
-file changed, 3 insertions(+), 2 deletions(-)
+file changed, 13 insertions(+), 3 deletions(-)
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
-             pcacheattrs = &cacheattrs;
+       .access = PL1_RW, .accessfn = access_tda,
-         }
+       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
+       .resetvalue = 0 },
--        ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa,
+-    /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
--                                 &txattrs, &s2prot, &s2size, fi, pcacheattrs);
++    /*
-+        ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
++     * MDCCSR_EL0[30:29] map to EDSCR[30:29].  Simply RAZ as the external
-+                                 &s2pa, &txattrs, &s2prot, &s2size, fi,
++     * Debug Communication Channel is not implemented.
-+                                 pcacheattrs);
++     */
-         if (ret) {
++    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
-             assert(fi->type != ARMFault_None);
++      .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
-             fi->s2addr = addr;
++      .access = PL0_R, .accessfn = access_tda,
 +      .type = ARM_CP_CONST, .resetvalue = 0 },
 +    /*
 +     * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2].  Map all bits as
 +     * it is unlikely a guest will care.
       * We don't implement the configurable EL0 access.
       */
 -    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
 -      .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
 +    { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
 +      .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
        .type = ARM_CP_ALIAS,
        .access = PL1_R, .accessfn = access_tda,
        .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
 --
 .20.1

-[PULL 02/39] hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string
+[PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error message
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+From: Rebecca Cran <rebecca@nuviainc.com>
-By using the TYPE_* definitions for devices, we can:
+Add a space in the message printed when gicr_read*/gicr_write* returns
- - quickly find where devices are used with 'git-grep'
+MEMTX_ERROR in arm_gicv3_redist.c.
  - easily rename a device (one-line change).
-Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
-Message-id: 20200428154650.21991-1-f4bug@amsat.org
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20210706211432.31902-1-rebecca@nuviainc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2-tz.c | 2 +-
+ hw/intc/arm_gicv3_redist.c | 4 ++--
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
+diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2-tz.c
+--- a/hw/intc/arm_gicv3_redist.c
-+++ b/hw/arm/mps2-tz.c
++++ b/hw/intc/arm_gicv3_redist.c
-@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
-         exit(EXIT_FAILURE);
+     if (r == MEMTX_ERROR) {
-     }
+         qemu_log_mask(LOG_GUEST_ERROR,
+                       "%s: invalid guest read at offset " TARGET_FMT_plx
--    sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
+-                      "size %u\n", __func__, offset, size);
-+    sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
++                      " size %u\n", __func__, offset, size);
-                           sizeof(mms->iotkit), mmc->armsse_type);
+         trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
-     iotkitdev = DEVICE(&mms->iotkit);
+                                    size, attrs.secure);
-     object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
+         /* The spec requires that reserved registers are RAZ/WI;
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
      if (r == MEMTX_ERROR) {
          qemu_log_mask(LOG_GUEST_ERROR,
                        "%s: invalid guest write at offset " TARGET_FMT_plx
 -                      "size %u\n", __func__, offset, size);
 +                      " size %u\n", __func__, offset, size);
          trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
                                      size, attrs.secure);
          /* The spec requires that reserved registers are RAZ/WI;
 --
 .20.1

-[PULL 03/39] target/arm: Don't use a TLB for ARMMMUIdx_Stage2
+Deleted patch
-We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU
-TLB.  However we never actually use the TLB -- all stage 2 lookups
-are done by direct calls to get_phys_addr_lpae() followed by a
-physical address load via address_space_ld*().
-Remove Stage2 from the list of ARM MMU indexes which correspond to
-real core MMU indexes, and instead put it in the set of "NOTLB" ARM
-MMU indexes.
-This allows us to drop NB_MMU_MODES to 11.  It also means we can
-safely add support for the ARMv8.3-TTS2UXN extension, which adds
-permission bits to the stage 2 descriptors which define execute
-permission separatel for EL0 and EL1; supporting that while keeping
-Stage2 in a QEMU TLB would require us to use separate TLBs for
-"Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a
-lot of extra complication given we aren't even using the QEMU TLB.
-In the process of updating the comment on our MMU index use,
-fix a couple of other minor errors:
- * NS EL2 EL2&0 was missing from the list in the comment
- * some text hadn't been updated from when we bumped NB_MMU_MODES
-   above 8
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200330210400.11724-2-peter.maydell@linaro.org
----
- target/arm/cpu-param.h |   2 +-
- target/arm/cpu.h       |  21 +++++---
- target/arm/helper.c    | 112 ++++-------------------------------------
-files changed, 27 insertions(+), 108 deletions(-)
-diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu-param.h
-+++ b/target/arm/cpu-param.h
-@@ -XXX,XX +XXX,XX @@
- # define TARGET_PAGE_BITS_MIN  10
- #endif
--#define NB_MMU_MODES 12
-+#define NB_MMU_MODES 11
- #endif
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
-  *     handling via the TLB. The only way to do a stage 1 translation without
-  *     the immediate stage 2 translation is via the ATS or AT system insns,
-  *     which can be slow-pathed and always do a page table walk.
-+ *     The only use of stage 2 translations is either as part of an s1+2
-+ *     lookup or when loading the descriptors during a stage 1 page table walk,
-+ *     and in both those cases we don't use the TLB.
-  *  4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
-  *     translation regimes, because they map reasonably well to each other
-  *     and they can't both be active at the same time.
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
-  * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
-  * NS EL1 EL1&0 stage 1+2 +PAN
-  * NS EL0 EL2&0
-+ * NS EL2 EL2&0
-  * NS EL2 EL2&0 +PAN
-  * NS EL2 (aka NS PL2)
-  * S EL0 EL1&0 (aka S PL0)
-  * S EL1 EL1&0 (not used if EL3 is 32 bit)
-  * S EL1 EL1&0 +PAN
-  * S EL3 (aka S PL1)
-- * NS EL1&0 stage 2
-  *
-- * for a total of 12 different mmu_idx.
-+ * for a total of 11 different mmu_idx.
-  *
-  * R profile CPUs have an MPU, but can use the same set of MMU indexes
-  * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
-  * are not quite the same -- different CPU types (most notably M profile
-  * vs A/R profile) would like to use MMU indexes with different semantics,
-  * but since we don't ever need to use all of those in a single CPU we
-- * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
-+ * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
-+ * modes + total number of M profile MMU modes". The lower bits of
-  * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
-  * the same for any particular CPU.
-  * Variables of type ARMMUIdx are always full values, and the core
-@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
-     ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
-     ARMMMUIdx_SE3        = 10 | ARM_MMU_IDX_A,
--    ARMMMUIdx_Stage2     = 11 | ARM_MMU_IDX_A,
--
-     /*
-      * These are not allocated TLBs and are used only for AT system
-      * instructions or for the first stage of an S12 page table walk.
-@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
-     ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
-     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
-     ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
-+    /*
-+     * Not allocated a TLB: used only for second stage of an S12 page
-+     * table walk, or for descriptor loads during first stage of an S1
-+     * page table walk. Note that if we ever want to have a TLB for this
-+     * then various TLB flush insns which currently are no-ops or flush
-+     * only stage 1 MMU indexes will need to change to flush stage 2.
-+     */
-+    ARMMMUIdx_Stage2     = 3 | ARM_MMU_IDX_NOTLB,
-     /*
-      * M-profile.
-@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
-     TO_CORE_BIT(SE10_1),
-     TO_CORE_BIT(SE10_1_PAN),
-     TO_CORE_BIT(SE3),
--    TO_CORE_BIT(Stage2),
-     TO_CORE_BIT(MUser),
-     TO_CORE_BIT(MPriv),
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     tlb_flush_by_mmuidx(cs,
-                         ARMMMUIdxBit_E10_1 |
-                         ARMMMUIdxBit_E10_1_PAN |
--                        ARMMMUIdxBit_E10_0 |
--                        ARMMMUIdxBit_Stage2);
-+                        ARMMMUIdxBit_E10_0);
- }
- static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     tlb_flush_by_mmuidx_all_cpus_synced(cs,
-                                         ARMMMUIdxBit_E10_1 |
-                                         ARMMMUIdxBit_E10_1_PAN |
--                                        ARMMMUIdxBit_E10_0 |
--                                        ARMMMUIdxBit_Stage2);
-+                                        ARMMMUIdxBit_E10_0);
- }
--static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
--                            uint64_t value)
--{
--    /* Invalidate by IPA. This has to invalidate any structures that
--     * contain only stage 2 translation information, but does not need
--     * to apply to structures that contain combined stage 1 and stage 2
--     * translation information.
--     * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
--     */
--    CPUState *cs = env_cpu(env);
--    uint64_t pageaddr;
--
--    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
--        return;
--    }
--
--    pageaddr = sextract64(value << 12, 0, 40);
--
--    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
--}
--
--static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
--                               uint64_t value)
--{
--    CPUState *cs = env_cpu(env);
--    uint64_t pageaddr;
--
--    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
--        return;
--    }
--
--    pageaddr = sextract64(value << 12, 0, 40);
--
--    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
--                                             ARMMMUIdxBit_Stage2);
--}
- static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                               uint64_t value)
-@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
-         tlb_flush_by_mmuidx(cs,
-                             ARMMMUIdxBit_E10_1 |
-                             ARMMMUIdxBit_E10_1_PAN |
--                            ARMMMUIdxBit_E10_0 |
--                            ARMMMUIdxBit_Stage2);
-+                            ARMMMUIdxBit_E10_0);
-         raw_write(env, ri, value);
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env)
-         return ARMMMUIdxBit_SE10_1 |
-                ARMMMUIdxBit_SE10_1_PAN |
-                ARMMMUIdxBit_SE10_0;
--    } else if (arm_feature(env, ARM_FEATURE_EL2)) {
--        return ARMMMUIdxBit_E10_1 |
--               ARMMMUIdxBit_E10_1_PAN |
--               ARMMMUIdxBit_E10_0 |
--               ARMMMUIdxBit_Stage2;
-     } else {
-         return ARMMMUIdxBit_E10_1 |
-                ARMMMUIdxBit_E10_1_PAN |
-@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                              ARMMMUIdxBit_SE3);
- }
--static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
--                                    uint64_t value)
--{
--    /* Invalidate by IPA. This has to invalidate any structures that
--     * contain only stage 2 translation information, but does not need
--     * to apply to structures that contain combined stage 1 and stage 2
--     * translation information.
--     * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
--     */
--    ARMCPU *cpu = env_archcpu(env);
--    CPUState *cs = CPU(cpu);
--    uint64_t pageaddr;
--
--    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
--        return;
--    }
--
--    pageaddr = sextract64(value << 12, 0, 48);
--
--    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
--}
--
--static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
--                                      uint64_t value)
--{
--    CPUState *cs = env_cpu(env);
--    uint64_t pageaddr;
--
--    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
--        return;
--    }
--
--    pageaddr = sextract64(value << 12, 0, 48);
--
--    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
--                                             ARMMMUIdxBit_Stage2);
--}
--
- static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
-                                       bool isread)
- {
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-       .writefn = tlbi_aa64_vae1_write },
-     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
--      .writefn = tlbi_aa64_ipas2e1is_write },
-+      .access = PL2_W, .type = ARM_CP_NOP },
-     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
--      .writefn = tlbi_aa64_ipas2e1is_write },
-+      .access = PL2_W, .type = ARM_CP_NOP },
-     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
-       .access = PL2_W, .type = ARM_CP_NO_RAW,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-       .writefn = tlbi_aa64_alle1is_write },
-     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
--      .writefn = tlbi_aa64_ipas2e1_write },
-+      .access = PL2_W, .type = ARM_CP_NOP },
-     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
--      .access = PL2_W, .type = ARM_CP_NO_RAW,
--      .writefn = tlbi_aa64_ipas2e1_write },
-+      .access = PL2_W, .type = ARM_CP_NOP },
-     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
-       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
-       .access = PL2_W, .type = ARM_CP_NO_RAW,
-@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
-       .writefn = tlbimva_hyp_is_write },
-     { .name = "TLBIIPAS2",
-       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
--      .type = ARM_CP_NO_RAW, .access = PL2_W,
--      .writefn = tlbiipas2_write },
-+      .type = ARM_CP_NOP, .access = PL2_W },
-     { .name = "TLBIIPAS2IS",
-       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
--      .type = ARM_CP_NO_RAW, .access = PL2_W,
--      .writefn = tlbiipas2_is_write },
-+      .type = ARM_CP_NOP, .access = PL2_W },
-     { .name = "TLBIIPAS2L",
-       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
--      .type = ARM_CP_NO_RAW, .access = PL2_W,
--      .writefn = tlbiipas2_write },
-+      .type = ARM_CP_NOP, .access = PL2_W },
-     { .name = "TLBIIPAS2LIS",
-       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
--      .type = ARM_CP_NO_RAW, .access = PL2_W,
--      .writefn = tlbiipas2_is_write },
-+      .type = ARM_CP_NOP, .access = PL2_W },
-     /* 32 bit cache operations */
-     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
-       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
---
-.20.1

-[PULL 07/39] target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0
+Deleted patch
-In aarch64_max_initfn() we update both 32-bit and 64-bit ID
-registers.  The intended pattern is that for 64-bit ID registers we
-use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
-registers use FIELD_DP32 and the uint32_t 'u' register.  For
-ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of
-this 64-bit ID register would end up always zero.  Luckily at the
-moment that's what they should be anyway, so this bug has no visible
-effects.
-Use the right-sized variable.
-Fixes: 3bec78447a958d481991
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200423110915.10527-1-peter.maydell@linaro.org
----
- target/arm/cpu64.c | 6 +++---
-file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-         u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
-         cpu->isar.id_mmfr4 = u;
--        u = cpu->isar.id_aa64dfr0;
--        u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
--        cpu->isar.id_aa64dfr0 = u;
-+        t = cpu->isar.id_aa64dfr0;
-+        t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
-+        cpu->isar.id_aa64dfr0 = t;
-         u = cpu->isar.id_dfr0;
-         u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
---
-.20.1

-[PULL 10/39] hw/arm: versal: Move misplaced comment
+Deleted patch
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Move misplaced comment.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-3-edgar.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/xlnx-versal.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal.c
-+++ b/hw/arm/xlnx-versal.c
-@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
-         obj = object_new(XLNX_VERSAL_ACPU_TYPE);
-         if (!obj) {
--            /* Secondary CPUs start in PSCI powered-down state */
-             error_report("Unable to create apu.cpu[%d] of type %s",
-                          i, XLNX_VERSAL_ACPU_TYPE);
-             exit(EXIT_FAILURE);
-@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
-         object_property_set_int(obj, s->cfg.psci_conduit,
-                                 "psci-conduit", &error_abort);
-         if (i) {
-+            /* Secondary CPUs start in PSCI powered-down state */
-             object_property_set_bool(obj, true,
-                                      "start-powered-off", &error_abort);
-         }
---
-.20.1

-[PULL 11/39] hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal
+Deleted patch
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Fix typo xlnx-ve -> xlnx-versal.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-4-edgar.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/xlnx-versal-virt.c | 2 +-
-file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal-virt.c
-+++ b/hw/arm/xlnx-versal-virt.c
-@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
-         psci_conduit = QEMU_PSCI_CONDUIT_SMC;
-     }
--    sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
-+    sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc,
-                           sizeof(s->soc), TYPE_XLNX_VERSAL);
-     object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
-                              "ddr", &error_abort);
---
-.20.1

-[PULL 12/39] hw/arm: versal: Embed the UARTs into the SoC type
+Deleted patch
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Embed the UARTs into the SoC type.
-Suggested-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-5-edgar.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/arm/xlnx-versal.h |  3 ++-
- hw/arm/xlnx-versal.c         | 12 ++++++------
-files changed, 8 insertions(+), 7 deletions(-)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
-+++ b/include/hw/arm/xlnx-versal.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/sysbus.h"
- #include "hw/arm/boot.h"
- #include "hw/intc/arm_gicv3.h"
-+#include "hw/char/pl011.h"
- #define TYPE_XLNX_VERSAL "xlnx-versal"
- #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
-         MemoryRegion mr_ocm;
-         struct {
--            SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
-+            PL011State uart[XLNX_VERSAL_NR_UARTS];
-             SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
-             SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
-         } iou;
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal.c
-+++ b/hw/arm/xlnx-versal.c
-@@ -XXX,XX +XXX,XX @@
- #include "kvm_arm.h"
- #include "hw/misc/unimp.h"
- #include "hw/arm/xlnx-versal.h"
--#include "hw/char/pl011.h"
- #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
- #define GEM_REVISION        0x40070106
-@@ -XXX,XX +XXX,XX @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
-         DeviceState *dev;
-         MemoryRegion *mr;
--        dev = qdev_create(NULL, TYPE_PL011);
--        s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);
-+        sysbus_init_child_obj(OBJECT(s), name,
-+                              &s->lpd.iou.uart[i], sizeof(s->lpd.iou.uart[i]),
-+                              TYPE_PL011);
-+        dev = DEVICE(&s->lpd.iou.uart[i]);
-         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
--        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
-         qdev_init_nofail(dev);
--        mr = sysbus_mmio_get_region(s->lpd.iou.uart[i], 0);
-+        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
-         memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
--        sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]);
-+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
-         g_free(name);
-     }
- }
---
-.20.1

-[PULL 13/39] hw/arm: versal: Embed the GEMs into the SoC type
+Deleted patch
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Embed the GEMs into the SoC type.
-Suggested-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-6-edgar.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/arm/xlnx-versal.h |  3 ++-
- hw/arm/xlnx-versal.c         | 15 ++++++++-------
-files changed, 10 insertions(+), 8 deletions(-)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
-+++ b/include/hw/arm/xlnx-versal.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/arm/boot.h"
- #include "hw/intc/arm_gicv3.h"
- #include "hw/char/pl011.h"
-+#include "hw/net/cadence_gem.h"
- #define TYPE_XLNX_VERSAL "xlnx-versal"
- #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
-         struct {
-             PL011State uart[XLNX_VERSAL_NR_UARTS];
--            SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
-+            CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
-             SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
-         } iou;
-     } lpd;
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal.c
-+++ b/hw/arm/xlnx-versal.c
-@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
-         DeviceState *dev;
-         MemoryRegion *mr;
--        dev = qdev_create(NULL, "cadence_gem");
--        s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);
--        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
-+        sysbus_init_child_obj(OBJECT(s), name,
-+                              &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]),
-+                              TYPE_CADENCE_GEM);
-+        dev = DEVICE(&s->lpd.iou.gem[i]);
-         if (nd->used) {
-             qemu_check_nic_model(nd, "cadence_gem");
-             qdev_set_nic_properties(dev, nd);
-         }
--        object_property_set_int(OBJECT(s->lpd.iou.gem[i]),
-+        object_property_set_int(OBJECT(dev),
-, "num-priority-queues",
-                                 &error_abort);
--        object_property_set_link(OBJECT(s->lpd.iou.gem[i]),
-+        object_property_set_link(OBJECT(dev),
-                                  OBJECT(&s->mr_ps), "dma",
-                                  &error_abort);
-         qdev_init_nofail(dev);
--        mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);
-+        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
-         memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
--        sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);
-+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
-         g_free(name);
-     }
- }
---
-.20.1

-[PULL 14/39] hw/arm: versal: Embed the ADMAs into the SoC type
+Deleted patch
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Embed the ADMAs into the SoC type.
-Suggested-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-7-edgar.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/arm/xlnx-versal.h |  3 ++-
- hw/arm/xlnx-versal.c         | 14 +++++++-------
-files changed, 9 insertions(+), 8 deletions(-)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
-+++ b/include/hw/arm/xlnx-versal.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/arm/boot.h"
- #include "hw/intc/arm_gicv3.h"
- #include "hw/char/pl011.h"
-+#include "hw/dma/xlnx-zdma.h"
- #include "hw/net/cadence_gem.h"
- #define TYPE_XLNX_VERSAL "xlnx-versal"
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
-         struct {
-             PL011State uart[XLNX_VERSAL_NR_UARTS];
-             CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
--            SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
-+            XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
-         } iou;
-     } lpd;
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal.c
-+++ b/hw/arm/xlnx-versal.c
-@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
-         DeviceState *dev;
-         MemoryRegion *mr;
--        dev = qdev_create(NULL, "xlnx.zdma");
--        s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev);
--        object_property_set_int(OBJECT(s->lpd.iou.adma[i]), 128, "bus-width",
--                                &error_abort);
--        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
-+        sysbus_init_child_obj(OBJECT(s), name,
-+                              &s->lpd.iou.adma[i], sizeof(s->lpd.iou.adma[i]),
-+                              TYPE_XLNX_ZDMA);
-+        dev = DEVICE(&s->lpd.iou.adma[i]);
-+        object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort);
-         qdev_init_nofail(dev);
--        mr = sysbus_mmio_get_region(s->lpd.iou.adma[i], 0);
-+        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
-         memory_region_add_subregion(&s->mr_ps,
-                                     MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
--        sysbus_connect_irq(s->lpd.iou.adma[i], 0, pic[VERSAL_ADMA_IRQ_0 + i]);
-+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]);
-         g_free(name);
-     }
- }
---
-.20.1

-[PULL 15/39] hw/arm: versal: Embed the APUs into the SoC type
+Deleted patch
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Embed the APUs into the SoC type.
-Suggested-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-8-edgar.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/arm/xlnx-versal.h |  2 +-
- hw/arm/xlnx-versal-virt.c    |  4 ++--
- hw/arm/xlnx-versal.c         | 19 +++++--------------
-files changed, 8 insertions(+), 17 deletions(-)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
-+++ b/include/hw/arm/xlnx-versal.h
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
-     struct {
-         struct {
-             MemoryRegion mr;
--            ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
-+            ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
-             GICv3State gic;
-         } apu;
-     } fpd;
-diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal-virt.c
-+++ b/hw/arm/xlnx-versal-virt.c
-@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
-     s->binfo.get_dtb = versal_virt_get_dtb;
-     s->binfo.modify_dtb = versal_virt_modify_dtb;
-     if (machine->kernel_filename) {
--        arm_load_kernel(s->soc.fpd.apu.cpu[0], machine, &s->binfo);
-+        arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo);
-     } else {
--        AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
-+        AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0],
-                                                   &s->binfo);
-         /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
-          * Offset things by 4K.  */
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal.c
-+++ b/hw/arm/xlnx-versal.c
-@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
-     for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
-         Object *obj;
--        char *name;
--
--        obj = object_new(XLNX_VERSAL_ACPU_TYPE);
--        if (!obj) {
--            error_report("Unable to create apu.cpu[%d] of type %s",
--                         i, XLNX_VERSAL_ACPU_TYPE);
--            exit(EXIT_FAILURE);
--        }
--
--        name = g_strdup_printf("apu-cpu[%d]", i);
--        object_property_add_child(OBJECT(s), name, obj, &error_fatal);
--        g_free(name);
-+        object_initialize_child(OBJECT(s), "apu-cpu[*]",
-+                                &s->fpd.apu.cpu[i], sizeof(s->fpd.apu.cpu[i]),
-+                                XLNX_VERSAL_ACPU_TYPE, &error_abort, NULL);
-+        obj = OBJECT(&s->fpd.apu.cpu[i]);
-         object_property_set_int(obj, s->cfg.psci_conduit,
-                                 "psci-conduit", &error_abort);
-         if (i) {
-@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
-         object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
-                                  &error_abort);
-         object_property_set_bool(obj, true, "realized", &error_fatal);
--        s->fpd.apu.cpu[i] = ARM_CPU(obj);
-     }
- }
-@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
-     }
-     for (i = 0; i < nr_apu_cpus; i++) {
--        DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);
-+        DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]);
-         int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
-         qemu_irq maint_irq;
-         int ti;
---
-.20.1

-[PULL 16/39] hw/arm: versal: Add support for SD
+Deleted patch
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Add support for SD.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-9-edgar.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/arm/xlnx-versal.h | 12 ++++++++++++
- hw/arm/xlnx-versal.c         | 31 +++++++++++++++++++++++++++++++
-files changed, 43 insertions(+)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
-+++ b/include/hw/arm/xlnx-versal.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/sysbus.h"
- #include "hw/arm/boot.h"
-+#include "hw/sd/sdhci.h"
- #include "hw/intc/arm_gicv3.h"
- #include "hw/char/pl011.h"
- #include "hw/dma/xlnx-zdma.h"
-@@ -XXX,XX +XXX,XX @@
- #define XLNX_VERSAL_NR_UARTS   2
- #define XLNX_VERSAL_NR_GEMS    2
- #define XLNX_VERSAL_NR_ADMAS   8
-+#define XLNX_VERSAL_NR_SDS     2
- #define XLNX_VERSAL_NR_IRQS    192
- typedef struct Versal {
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
-         } iou;
-     } lpd;
-+    /* The Platform Management Controller subsystem.  */
-+    struct {
-+        struct {
-+            SDHCIState sd[XLNX_VERSAL_NR_SDS];
-+        } iou;
-+    } pmc;
-+
-     struct {
-         MemoryRegion *mr_ddr;
-         uint32_t psci_conduit;
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
- #define VERSAL_GEM1_IRQ_0          58
- #define VERSAL_GEM1_WAKE_IRQ_0     59
- #define VERSAL_ADMA_IRQ_0          60
-+#define VERSAL_SD0_IRQ_0           126
- /* Architecturally reserved IRQs suitable for virtualization.  */
- #define VERSAL_RSVD_IRQ_FIRST 111
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
- #define MM_FPD_CRF                  0xfd1a0000U
- #define MM_FPD_CRF_SIZE             0x140000
-+#define MM_PMC_SD0                  0xf1040000U
-+#define MM_PMC_SD0_SIZE             0x10000
- #define MM_PMC_CRP                  0xf1260000U
- #define MM_PMC_CRP_SIZE             0x10000
- #endif
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal.c
-+++ b/hw/arm/xlnx-versal.c
-@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
-     }
- }
-+#define SDHCI_CAPABILITIES  0x280737ec6481 /* Same as on ZynqMP.  */
-+static void versal_create_sds(Versal *s, qemu_irq *pic)
-+{
-+    int i;
-+
-+    for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) {
-+        DeviceState *dev;
-+        MemoryRegion *mr;
-+
-+        sysbus_init_child_obj(OBJECT(s), "sd[*]",
-+                              &s->pmc.iou.sd[i], sizeof(s->pmc.iou.sd[i]),
-+                              TYPE_SYSBUS_SDHCI);
-+        dev = DEVICE(&s->pmc.iou.sd[i]);
-+
-+        object_property_set_uint(OBJECT(dev),
-+                                 3, "sd-spec-version", &error_fatal);
-+        object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg",
-+                                 &error_fatal);
-+        object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal);
-+        qdev_init_nofail(dev);
-+
-+        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
-+        memory_region_add_subregion(&s->mr_ps,
-+                                    MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr);
-+
-+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
-+                           pic[VERSAL_SD0_IRQ_0 + i * 2]);
-+    }
-+}
-+
- /* This takes the board allocated linear DDR memory and creates aliases
-  * for each split DDR range/aperture on the Versal address map.
-  */
-@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
-     versal_create_uarts(s, pic);
-     versal_create_gems(s, pic);
-     versal_create_admas(s, pic);
-+    versal_create_sds(s, pic);
-     versal_map_ddr(s);
-     versal_unimp(s);
---
-.20.1

-[PULL 18/39] hw/arm: versal-virt: Add support for SD
+Deleted patch
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Add support for SD.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-11-edgar.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/xlnx-versal-virt.c | 46 +++++++++++++++++++++++++++++++++++++++
-file changed, 46 insertions(+)
-diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal-virt.c
-+++ b/hw/arm/xlnx-versal-virt.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/arm/sysbus-fdt.h"
- #include "hw/arm/fdt.h"
- #include "cpu.h"
-+#include "hw/qdev-properties.h"
- #include "hw/arm/xlnx-versal.h"
- #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_zdma_nodes(VersalVirt *s)
-     }
- }
-+static void fdt_add_sd_nodes(VersalVirt *s)
-+{
-+    const char clocknames[] = "clk_xin\0clk_ahb";
-+    const char compat[] = "arasan,sdhci-8.9a";
-+    int i;
-+
-+    for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) {
-+        uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i;
-+        char *name = g_strdup_printf("/sdhci@%" PRIx64, addr);
-+
-+        qemu_fdt_add_subnode(s->fdt, name);
-+
-+        qemu_fdt_setprop_cells(s->fdt, name, "clocks",
-+                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
-+        qemu_fdt_setprop(s->fdt, name, "clock-names",
-+                         clocknames, sizeof(clocknames));
-+        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
-+                               GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2,
-+                               GIC_FDT_IRQ_FLAGS_LEVEL_HI);
-+        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
-+                                     2, addr, 2, MM_PMC_SD0_SIZE);
-+        qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
-+        g_free(name);
-+    }
-+}
-+
- static void fdt_nop_memory_nodes(void *fdt, Error **errp)
- {
-     Error *err = NULL;
-@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
-     }
- }
-+static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
-+{
-+    BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
-+    DeviceState *card;
-+
-+    card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD);
-+    object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card),
-+                              &error_fatal);
-+    qdev_prop_set_drive(card, "drive", blk, &error_fatal);
-+    object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
-+}
-+
- static void versal_virt_init(MachineState *machine)
- {
-     VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
-     int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
-+    int i;
-     /*
-      * If the user provides an Operating System to be loaded, we expect them
-@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
-     fdt_add_gic_nodes(s);
-     fdt_add_timer_nodes(s);
-     fdt_add_zdma_nodes(s);
-+    fdt_add_sd_nodes(s);
-     fdt_add_cpu_nodes(s, psci_conduit);
-     fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
-     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
-@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
-     memory_region_add_subregion_overlap(get_system_memory(),
-, &s->soc.fpd.apu.mr, 0);
-+    /* Plugin SD cards.  */
-+    for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
-+        sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
-+    }
-+
-     s->binfo.ram_size = machine->ram_size;
-     s->binfo.loader_start = 0x0;
-     s->binfo.get_dtb = versal_virt_get_dtb;
---
-.20.1

-[PULL 19/39] hw/arm: versal-virt: Add support for the RTC
+Deleted patch
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-Add support for the RTC.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-12-edgar.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- hw/arm/xlnx-versal-virt.c | 22 ++++++++++++++++++++++
-file changed, 22 insertions(+)
-diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal-virt.c
-+++ b/hw/arm/xlnx-versal-virt.c
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_sd_nodes(VersalVirt *s)
-     }
- }
-+static void fdt_add_rtc_node(VersalVirt *s)
-+{
-+    const char compat[] = "xlnx,zynqmp-rtc";
-+    const char interrupt_names[] = "alarm\0sec";
-+    char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC);
-+
-+    qemu_fdt_add_subnode(s->fdt, name);
-+
-+    qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
-+                           GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ,
-+                           GIC_FDT_IRQ_FLAGS_LEVEL_HI,
-+                           GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ,
-+                           GIC_FDT_IRQ_FLAGS_LEVEL_HI);
-+    qemu_fdt_setprop(s->fdt, name, "interrupt-names",
-+                     interrupt_names, sizeof(interrupt_names));
-+    qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
-+                                 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE);
-+    qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
-+    g_free(name);
-+}
-+
- static void fdt_nop_memory_nodes(void *fdt, Error **errp)
- {
-     Error *err = NULL;
-@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
-     fdt_add_timer_nodes(s);
-     fdt_add_zdma_nodes(s);
-     fdt_add_sd_nodes(s);
-+    fdt_add_rtc_node(s);
-     fdt_add_cpu_nodes(s, psci_conduit);
-     fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
-     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
---
-.20.1

-[PULL 20/39] target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
+Deleted patch
-Somewhere along theline we accidentally added a duplicate
-"using D16-D31 when they don't exist" check to do_vfm_dp()
-(probably an artifact of a patchseries rebase). Remove it.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200430181003.21682-2-peter.maydell@linaro.org
----
- target/arm/translate-vfp.inc.c | 6 ------
-file changed, 6 deletions(-)
-diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-vfp.inc.c
-+++ b/target/arm/translate-vfp.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
-         return false;
-     }
--    /* UNDEF accesses to D16-D31 if they don't exist. */
--    if (!dc_isar_feature(aa32_simd_r32, s) &&
--        ((a->vd | a->vn | a->vm) & 0x10)) {
--        return false;
--    }
--
-     if (!vfp_access_check(s)) {
-         return true;
-     }
---
-.20.1

-[PULL 21/39] target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
+Deleted patch
-We were accidentally permitting decode of Thumb Neon insns even if
-the CPU didn't have the FEATURE_NEON bit set, because the feature
-check was being done before the call to disas_neon_data_insn() and
-disas_neon_ls_insn() in the Arm decoder but was omitted from the
-Thumb decoder.  Push the feature bit check down into the called
-functions so it is done for both Arm and Thumb encodings.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200430181003.21682-3-peter.maydell@linaro.org
----
- target/arm/translate.c | 16 ++++++++--------
-file changed, 8 insertions(+), 8 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
-     TCGv_i32 tmp2;
-     TCGv_i64 tmp64;
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-+        return 1;
-+    }
-+
-     /* FIXME: this access check should not take precedence over UNDEF
-      * for invalid encodings; we will generate incorrect syndrome information
-      * for attempts to execute invalid vfp/neon encodings with FP disabled.
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     TCGv_ptr ptr1, ptr2, ptr3;
-     TCGv_i64 tmp64;
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-+        return 1;
-+    }
-+
-     /* FIXME: this access check should not take precedence over UNDEF
-      * for invalid encodings; we will generate incorrect syndrome information
-      * for attempts to execute invalid vfp/neon encodings with FP disabled.
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
-         if (((insn >> 25) & 7) == 1) {
-             /* NEON Data processing.  */
--            if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
--                goto illegal_op;
--            }
--
-             if (disas_neon_data_insn(s, insn)) {
-                 goto illegal_op;
-             }
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
-         }
-         if ((insn & 0x0f100000) == 0x04000000) {
-             /* NEON load/store.  */
--            if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
--                goto illegal_op;
--            }
--
-             if (disas_neon_ls_insn(s, insn)) {
-                 goto illegal_op;
-             }
---
-.20.1

-[PULL 23/39] target/arm: Convert VCMLA (vector) to decodetree
+Deleted patch
-Convert the VCMLA (vector) insns in the 3same extension group to
-decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-5-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   | 11 ++++++++++
- target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 11 +---------
-files changed, 49 insertions(+), 10 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@
- # More specifically, this covers:
- # 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
- # 3same ext:       0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
-+
-+# VFP/Neon register fields; same as vfp.decode
-+%vm_dp  5:1 0:4
-+%vm_sp  0:4 5:1
-+%vn_dp  7:1 16:4
-+%vn_sp  16:4 7:1
-+%vd_dp  22:1 12:4
-+%vd_sp  12:4 22:1
-+
-+VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@
- #include "decode-neon-dp.inc.c"
- #include "decode-neon-ls.inc.c"
- #include "decode-neon-shared.inc.c"
-+
-+static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
-+{
-+    int opr_sz;
-+    TCGv_ptr fpst;
-+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
-+
-+    if (!dc_isar_feature(aa32_vcma, s)
-+        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vn | a->vm | a->vd) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    opr_sz = (1 + a->q) * 8;
-+    fpst = get_fpstatus_ptr(1);
-+    fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
-+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(1, a->vn),
-+                       vfp_reg_offset(1, a->vm),
-+                       fpst, opr_sz, opr_sz, a->rot,
-+                       fn_gvec_ptr);
-+    tcg_temp_free_ptr(fpst);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
-     bool is_long = false, q = extract32(insn, 6, 1);
-     bool ptr_is_env = false;
--    if ((insn & 0xfe200f10) == 0xfc200800) {
--        /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
--        int size = extract32(insn, 20, 1);
--        data = extract32(insn, 23, 2); /* rot */
--        if (!dc_isar_feature(aa32_vcma, s)
--            || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
--            return 1;
--        }
--        fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
--    } else if ((insn & 0xfea00f10) == 0xfc800800) {
-+    if ((insn & 0xfea00f10) == 0xfc800800) {
-         /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
-         int size = extract32(insn, 20, 1);
-         data = extract32(insn, 24, 1); /* rot */
---
-.20.1

-[PULL 24/39] target/arm: Convert VCADD (vector) to decodetree
+Deleted patch
-Convert the VCADD (vector) insns to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-6-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   |  3 +++
- target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 11 +---------
-files changed, 41 insertions(+), 10 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@
- VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+
-+VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
-     tcg_temp_free_ptr(fpst);
-     return true;
- }
-+
-+static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
-+{
-+    int opr_sz;
-+    TCGv_ptr fpst;
-+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
-+
-+    if (!dc_isar_feature(aa32_vcma, s)
-+        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vn | a->vm | a->vd) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    opr_sz = (1 + a->q) * 8;
-+    fpst = get_fpstatus_ptr(1);
-+    fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
-+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(1, a->vn),
-+                       vfp_reg_offset(1, a->vm),
-+                       fpst, opr_sz, opr_sz, a->rot,
-+                       fn_gvec_ptr);
-+    tcg_temp_free_ptr(fpst);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
-     bool is_long = false, q = extract32(insn, 6, 1);
-     bool ptr_is_env = false;
--    if ((insn & 0xfea00f10) == 0xfc800800) {
--        /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
--        int size = extract32(insn, 20, 1);
--        data = extract32(insn, 24, 1); /* rot */
--        if (!dc_isar_feature(aa32_vcma, s)
--            || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
--            return 1;
--        }
--        fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
--    } else if ((insn & 0xfeb00f00) == 0xfc200d00) {
-+    if ((insn & 0xfeb00f00) == 0xfc200d00) {
-         /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
-         bool u = extract32(insn, 4, 1);
-         if (!dc_isar_feature(aa32_dp, s)) {
---
-.20.1

-[PULL 25/39] target/arm: Convert V[US]DOT (vector) to decodetree
+Deleted patch
-Convert the V[US]DOT (vector) insns to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-7-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   |  4 ++++
- target/arm/translate-neon.inc.c | 32 ++++++++++++++++++++++++++++++++
- target/arm/translate.c          |  9 +--------
-files changed, 37 insertions(+), 8 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@ VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
- VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+
-+# VUDOT and VSDOT
-+VDOT           1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
-     tcg_temp_free_ptr(fpst);
-     return true;
- }
-+
-+static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
-+{
-+    int opr_sz;
-+    gen_helper_gvec_3 *fn_gvec;
-+
-+    if (!dc_isar_feature(aa32_dp, s)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vn | a->vm | a->vd) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    opr_sz = (1 + a->q) * 8;
-+    fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
-+    tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(1, a->vn),
-+                       vfp_reg_offset(1, a->vm),
-+                       opr_sz, opr_sz, 0, fn_gvec);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
-     bool is_long = false, q = extract32(insn, 6, 1);
-     bool ptr_is_env = false;
--    if ((insn & 0xfeb00f00) == 0xfc200d00) {
--        /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
--        bool u = extract32(insn, 4, 1);
--        if (!dc_isar_feature(aa32_dp, s)) {
--            return 1;
--        }
--        fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
--    } else if ((insn & 0xff300f10) == 0xfc200810) {
-+    if ((insn & 0xff300f10) == 0xfc200810) {
-         /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
-         int is_s = extract32(insn, 23, 1);
-         if (!dc_isar_feature(aa32_fhm, s)) {
---
-.20.1

-[PULL 26/39] target/arm: Convert VFM[AS]L (vector) to decodetree
+Deleted patch
-Convert the VFM[AS]L (vector) insns to decodetree.  This is the last
-insn in the legacy decoder for the 3same_ext group, so we can
-delete the legacy decoder function for the group entirely.
-Note that in disas_thumb2_insn() the parts of this encoding space
-where the decodetree decoder returns false will correctly be directed
-to illegal_op by the "(insn & (1 << 28))" check so they won't fall
-into disas_coproc_insn() by mistake.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-8-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   |  6 +++
- target/arm/translate-neon.inc.c | 31 +++++++++++
- target/arm/translate.c          | 92 +--------------------------------
-files changed, 38 insertions(+), 91 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@ VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
- # VUDOT and VSDOT
- VDOT           1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+
-+# VFM[AS]L
-+VFML           1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
-+               vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0
-+VFML           1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
-                        opr_sz, opr_sz, 0, fn_gvec);
-     return true;
- }
-+
-+static bool trans_VFML(DisasContext *s, arg_VFML *a)
-+{
-+    int opr_sz;
-+
-+    if (!dc_isar_feature(aa32_fhm, s)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        (a->vd & 0x10)) {
-+        return false;
-+    }
-+
-+    if (a->vd & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    opr_sz = (1 + a->q) * 8;
-+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(a->q, a->vn),
-+                       vfp_reg_offset(a->q, a->vm),
-+                       cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
-+                       gen_helper_gvec_fmlal_a32);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     return 0;
- }
--/* Advanced SIMD three registers of the same length extension.
-- *  31           25    23  22    20   16   12  11   10   9    8        3     0
-- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
-- * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
-- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
-- */
--static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
--{
--    gen_helper_gvec_3 *fn_gvec = NULL;
--    gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
--    int rd, rn, rm, opr_sz;
--    int data = 0;
--    int off_rn, off_rm;
--    bool is_long = false, q = extract32(insn, 6, 1);
--    bool ptr_is_env = false;
--
--    if ((insn & 0xff300f10) == 0xfc200810) {
--        /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
--        int is_s = extract32(insn, 23, 1);
--        if (!dc_isar_feature(aa32_fhm, s)) {
--            return 1;
--        }
--        is_long = true;
--        data = is_s; /* is_2 == 0 */
--        fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
--        ptr_is_env = true;
--    } else {
--        return 1;
--    }
--
--    VFP_DREG_D(rd, insn);
--    if (rd & q) {
--        return 1;
--    }
--    if (q || !is_long) {
--        VFP_DREG_N(rn, insn);
--        VFP_DREG_M(rm, insn);
--        if ((rn | rm) & q & !is_long) {
--            return 1;
--        }
--        off_rn = vfp_reg_offset(1, rn);
--        off_rm = vfp_reg_offset(1, rm);
--    } else {
--        rn = VFP_SREG_N(insn);
--        rm = VFP_SREG_M(insn);
--        off_rn = vfp_reg_offset(0, rn);
--        off_rm = vfp_reg_offset(0, rm);
--    }
--
--    if (s->fp_excp_el) {
--        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
--                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
--        return 0;
--    }
--    if (!s->vfp_enabled) {
--        return 1;
--    }
--
--    opr_sz = (1 + q) * 8;
--    if (fn_gvec_ptr) {
--        TCGv_ptr ptr;
--        if (ptr_is_env) {
--            ptr = cpu_env;
--        } else {
--            ptr = get_fpstatus_ptr(1);
--        }
--        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
--                           opr_sz, opr_sz, data, fn_gvec_ptr);
--        if (!ptr_is_env) {
--            tcg_temp_free_ptr(ptr);
--        }
--    } else {
--        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
--                           opr_sz, opr_sz, data, fn_gvec);
--    }
--    return 0;
--}
--
- /* Advanced SIMD two registers and a scalar extension.
-  *  31             24   23  22   20   16   12  11   10   9    8        3     0
-  * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
-                     }
-                 }
-             }
--        } else if ((insn & 0x0e000a00) == 0x0c000800
--                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
--            if (disas_neon_insn_3same_ext(s, insn)) {
--                goto illegal_op;
--            }
--            return;
-         } else if ((insn & 0x0f000a00) == 0x0e000800
-                    && arm_dc_feature(s, ARM_FEATURE_V8)) {
-             if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
-             }
-             break;
-         }
--        if ((insn & 0xfe000a00) == 0xfc000800
-+        if ((insn & 0xff000a00) == 0xfe000800
-             && arm_dc_feature(s, ARM_FEATURE_V8)) {
-             /* The Thumb2 and ARM encodings are identical.  */
--            if (disas_neon_insn_3same_ext(s, insn)) {
--                goto illegal_op;
--            }
--        } else if ((insn & 0xff000a00) == 0xfe000800
--                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
--            /* The Thumb2 and ARM encodings are identical.  */
-             if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
-                 goto illegal_op;
-             }
---
-.20.1

-[PULL 28/39] target/arm: Convert V[US]DOT (scalar) to decodetree
+Deleted patch
-Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
-to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-10-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   |  3 +++
- target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 13 +-----------
-files changed, 39 insertions(+), 12 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@ VCMLA_scalar   1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
-                vn=%vn_dp vd=%vd_dp size=0
- VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0
-+
-+VDOT_scalar    1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
-     tcg_temp_free_ptr(fpst);
-     return true;
- }
-+
-+static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
-+{
-+    gen_helper_gvec_3 *fn_gvec;
-+    int opr_sz;
-+    TCGv_ptr fpst;
-+
-+    if (!dc_isar_feature(aa32_dp, s)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vd | a->vn) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
-+    opr_sz = (1 + a->q) * 8;
-+    fpst = get_fpstatus_ptr(1);
-+    tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(1, a->vn),
-+                       vfp_reg_offset(1, a->rm),
-+                       opr_sz, opr_sz, a->index, fn_gvec);
-+    tcg_temp_free_ptr(fpst);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
-     bool is_long = false, q = extract32(insn, 6, 1);
-     bool ptr_is_env = false;
--    if ((insn & 0xffb00f00) == 0xfe200d00) {
--        /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
--        int u = extract32(insn, 4, 1);
--
--        if (!dc_isar_feature(aa32_dp, s)) {
--            return 1;
--        }
--        fn_gvec = u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
--        /* rm is just Vm, and index is M.  */
--        data = extract32(insn, 5, 1); /* index */
--        rm = extract32(insn, 0, 4);
--    } else if ((insn & 0xffa00f10) == 0xfe000810) {
-+    if ((insn & 0xffa00f10) == 0xfe000810) {
-         /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
-         int is_s = extract32(insn, 20, 1);
-         int vm20 = extract32(insn, 0, 3);
---
-.20.1

-[PULL 33/39] target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
+Deleted patch
-Convert the Neon 3-reg-same VADD and VSUB insns to decodetree.
-Note that we don't need the neon_3r_sizes[op] check here because all
-size values are OK for VADD and VSUB; we'll add this when we convert
-the first insn that has size restrictions.
-For this we need one of the GVecGen*Fn typedefs currently in
-translate-a64.h; move them all to translate.h as a block so they
-are visible to the 32-bit decoder.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-15-peter.maydell@linaro.org
----
- target/arm/translate-a64.h      |  9 --------
- target/arm/translate.h          |  9 ++++++++
- target/arm/neon-dp.decode       | 17 +++++++++++++++
- target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 14 ++++--------
-files changed, 68 insertions(+), 19 deletions(-)
-diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.h
-+++ b/target/arm/translate-a64.h
-@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)
- bool disas_sve(DisasContext *, uint32_t);
--/* Note that the gvec expanders operate on offsets + sizes.  */
--typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
--typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
--                         uint32_t, uint32_t);
--typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
--                        uint32_t, uint32_t, uint32_t);
--typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
--                        uint32_t, uint32_t, uint32_t);
--
- #endif /* TARGET_ARM_TRANSLATE_A64_H */
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
- #define dc_isar_feature(name, ctx) \
-     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
-+/* Note that the gvec expanders operate on offsets + sizes.  */
-+typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
-+typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
-+                         uint32_t, uint32_t);
-+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
-+                        uint32_t, uint32_t, uint32_t);
-+typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
-+                        uint32_t, uint32_t, uint32_t);
-+
- #endif /* TARGET_ARM_TRANSLATE_H */
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@
- #
- # This file is processed by scripts/decodetree.py
- #
-+# VFP/Neon register fields; same as vfp.decode
-+%vm_dp  5:1 0:4
-+%vn_dp  7:1 16:4
-+%vd_dp  22:1 12:4
- # Encodings for Neon data processing instructions where the T32 encoding
- # is a simple transformation of the A32 encoding.
-@@ -XXX,XX +XXX,XX @@
- #   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
- # This file works on the A32 encoding only; calling code for T32 has to
- # transform the insn into the A32 version first.
-+
-+######################################################################
-+# 3-reg-same grouping:
-+# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
-+######################################################################
-+
-+&3same vm vn vd q size
-+
-+@3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
-+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+
-+VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
-+VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
-     return true;
- }
-+
-+static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
-+{
-+    int vec_size = a->q ? 16 : 8;
-+    int rd_ofs = neon_reg_offset(a->vd, 0);
-+    int rn_ofs = neon_reg_offset(a->vn, 0);
-+    int rm_ofs = neon_reg_offset(a->vm, 0);
-+
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vn | a->vm | a->vd) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
-+    return true;
-+}
-+
-+#define DO_3SAME(INSN, FUNC)                                            \
-+    static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a)        \
-+    {                                                                   \
-+        return do_3same(s, a, FUNC);                                    \
-+    }
-+
-+DO_3SAME(VADD, tcg_gen_gvec_add)
-+DO_3SAME(VSUB, tcg_gen_gvec_sub)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             }
-             return 0;
--        case NEON_3R_VADD_VSUB:
--            if (u) {
--                tcg_gen_gvec_sub(size, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--            } else {
--                tcg_gen_gvec_add(size, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--            }
--            return 0;
--
-         case NEON_3R_VQADD:
-             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-                            rn_ofs, rm_ofs, vec_size, vec_size,
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
-                            u ? &ushl_op[size] : &sshl_op[size]);
-             return 0;
-+
-+        case NEON_3R_VADD_VSUB:
-+            /* Already handled by decodetree */
-+            return 1;
-         }
-         if (size == 3) {
---
-.20.1

-[PULL 34/39] target/arm: Convert Neon 3-reg-same logic ops to decodetree
+Deleted patch
-Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
-Note that for the logic ops the 'size' field forms part of their
-decode and the actual operations are always bitwise.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-16-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       | 12 +++++++++++
- target/arm/translate-neon.inc.c | 19 +++++++++++++++++
- target/arm/translate.c          | 38 +--------------------------------
-files changed, 32 insertions(+), 37 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@
- @3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
-                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+@3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
-+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
-+
-+VAND_3s          1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
-+VBIC_3s          1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
-+VORR_3s          1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
-+VORN_3s          1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
-+VEOR_3s          1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
-+VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
-+VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
-+VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
-+
- VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
- VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
- DO_3SAME(VADD, tcg_gen_gvec_add)
- DO_3SAME(VSUB, tcg_gen_gvec_sub)
-+DO_3SAME(VAND, tcg_gen_gvec_and)
-+DO_3SAME(VBIC, tcg_gen_gvec_andc)
-+DO_3SAME(VORR, tcg_gen_gvec_or)
-+DO_3SAME(VORN, tcg_gen_gvec_orc)
-+DO_3SAME(VEOR, tcg_gen_gvec_xor)
-+
-+/* These insns are all gvec_bitsel but with the inputs in various orders. */
-+#define DO_3SAME_BITSEL(INSN, O1, O2, O3)                               \
-+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
-+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
-+                                uint32_t oprsz, uint32_t maxsz)         \
-+    {                                                                   \
-+        tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz);    \
-+    }                                                                   \
-+    DO_3SAME(INSN, gen_##INSN##_3s)
-+
-+DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
-+DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
-+DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             }
-             return 1;
--        case NEON_3R_LOGIC: /* Logic ops.  */
--            switch ((u << 2) | size) {
--            case 0: /* VAND */
--                tcg_gen_gvec_and(0, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--                break;
--            case 1: /* VBIC */
--                tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
--                                  vec_size, vec_size);
--                break;
--            case 2: /* VORR */
--                tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
--                                vec_size, vec_size);
--                break;
--            case 3: /* VORN */
--                tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--                break;
--            case 4: /* VEOR */
--                tcg_gen_gvec_xor(0, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--                break;
--            case 5: /* VBSL */
--                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rd_ofs, rn_ofs, rm_ofs,
--                                    vec_size, vec_size);
--                break;
--            case 6: /* VBIT */
--                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rn_ofs, rd_ofs,
--                                    vec_size, vec_size);
--                break;
--            case 7: /* VBIF */
--                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rd_ofs, rn_ofs,
--                                    vec_size, vec_size);
--                break;
--            }
--            return 0;
--
-         case NEON_3R_VQADD:
-             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-                            rn_ofs, rm_ofs, vec_size, vec_size,
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             return 0;
-         case NEON_3R_VADD_VSUB:
-+        case NEON_3R_LOGIC:
-             /* Already handled by decodetree */
-             return 1;
-         }
---
-.20.1

-[PULL 35/39] target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
+Deleted patch
-Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-17-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  5 +++++
- target/arm/translate-neon.inc.c | 14 ++++++++++++++
- target/arm/translate.c          | 21 ++-------------------
-files changed, 21 insertions(+), 19 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
- VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
- VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
-+VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
-+VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
-+VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
-+VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
-+
- VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
- VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ DO_3SAME(VEOR, tcg_gen_gvec_xor)
- DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
- DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
- DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
-+
-+#define DO_3SAME_NO_SZ_3(INSN, FUNC)                                    \
-+    static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a)        \
-+    {                                                                   \
-+        if (a->size == 3) {                                             \
-+            return false;                                               \
-+        }                                                               \
-+        return do_3same(s, a, FUNC);                                    \
-+    }
-+
-+DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
-+DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
-+DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
-+DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                              rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
-             return 0;
--        case NEON_3R_VMAX:
--            if (u) {
--                tcg_gen_gvec_umax(size, rd_ofs, rn_ofs, rm_ofs,
--                                  vec_size, vec_size);
--            } else {
--                tcg_gen_gvec_smax(size, rd_ofs, rn_ofs, rm_ofs,
--                                  vec_size, vec_size);
--            }
--            return 0;
--        case NEON_3R_VMIN:
--            if (u) {
--                tcg_gen_gvec_umin(size, rd_ofs, rn_ofs, rm_ofs,
--                                  vec_size, vec_size);
--            } else {
--                tcg_gen_gvec_smin(size, rd_ofs, rn_ofs, rm_ofs,
--                                  vec_size, vec_size);
--            }
--            return 0;
--
-         case NEON_3R_VSHL:
-             /* Note the operation is vshl vd,vm,vn */
-             tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-         case NEON_3R_VADD_VSUB:
-         case NEON_3R_LOGIC:
-+        case NEON_3R_VMAX:
-+        case NEON_3R_VMIN:
-             /* Already handled by decodetree */
-             return 1;
-         }
---
-.20.1

-[PULL 36/39] target/arm: Convert Neon 3-reg-same comparisons to decodetree
+Deleted patch
-Convert the Neon comparison ops in the 3-reg-same grouping
-to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-18-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  8 ++++++++
- target/arm/translate-neon.inc.c | 22 ++++++++++++++++++++++
- target/arm/translate.c          | 23 +++--------------------
-files changed, 33 insertions(+), 20 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
- VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
- VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
-+VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
-+VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
-+VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
-+VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
-+
- VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
- VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
- VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
-@@ -XXX,XX +XXX,XX @@ VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
- VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
- VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
-+
-+VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
-+VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
- DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
- DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
- DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
-+
-+#define DO_3SAME_CMP(INSN, COND)                                        \
-+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
-+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
-+                                uint32_t oprsz, uint32_t maxsz)         \
-+    {                                                                   \
-+        tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \
-+    }                                                                   \
-+    DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
-+
-+DO_3SAME_CMP(VCGT_S, TCG_COND_GT)
-+DO_3SAME_CMP(VCGT_U, TCG_COND_GTU)
-+DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
-+DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
-+DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
-+
-+static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
-+                         uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
-+{
-+    tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);
-+}
-+DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                            u ? &mls_op[size] : &mla_op[size]);
-             return 0;
--        case NEON_3R_VTST_VCEQ:
--            if (u) { /* VCEQ */
--                tcg_gen_gvec_cmp(TCG_COND_EQ, size, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--            } else { /* VTST */
--                tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
--                               vec_size, vec_size, &cmtst_op[size]);
--            }
--            return 0;
--
--        case NEON_3R_VCGT:
--            tcg_gen_gvec_cmp(u ? TCG_COND_GTU : TCG_COND_GT, size,
--                             rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
--            return 0;
--
--        case NEON_3R_VCGE:
--            tcg_gen_gvec_cmp(u ? TCG_COND_GEU : TCG_COND_GE, size,
--                             rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
--            return 0;
--
-         case NEON_3R_VSHL:
-             /* Note the operation is vshl vd,vm,vn */
-             tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-         case NEON_3R_LOGIC:
-         case NEON_3R_VMAX:
-         case NEON_3R_VMIN:
-+        case NEON_3R_VTST_VCEQ:
-+        case NEON_3R_VCGT:
-+        case NEON_3R_VCGE:
-             /* Already handled by decodetree */
-             return 1;
-         }
---
-.20.1

Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups.

thanks
-- PMM

The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835:

Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504

for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:

target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100)

----------------------------------------------------------------
target-arm queue:
 * Start of conversion of Neon insns to decodetree
 * versal board: support SD and RTC
 * Implement ARMv8.2-TTS2UXN
 * Make VQDMULL undefined when U=1
 * Some minor code cleanups

----------------------------------------------------------------
Edgar E. Iglesias (11):
      hw/arm: versal: Remove inclusion of arm_gicv3_common.h
      hw/arm: versal: Move misplaced comment
      hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal
      hw/arm: versal: Embed the UARTs into the SoC type
      hw/arm: versal: Embed the GEMs into the SoC type
      hw/arm: versal: Embed the ADMAs into the SoC type
      hw/arm: versal: Embed the APUs into the SoC type
      hw/arm: versal: Add support for SD
      hw/arm: versal: Add support for the RTC
      hw/arm: versal-virt: Add support for SD
      hw/arm: versal-virt: Add support for the RTC

Fredrik Strupe (1):
      target/arm: Make VQDMULL undefined when U=1

Peter Maydell (25):
      target/arm: Don't use a TLB for ARMMMUIdx_Stage2
      target/arm: Use enum constant in get_phys_addr_lpae() call
      target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()
      target/arm: Implement ARMv8.2-TTS2UXN
      target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0
      target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
      target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
      target/arm: Add stubs for AArch32 Neon decodetree
      target/arm: Convert VCMLA (vector) to decodetree
      target/arm: Convert VCADD (vector) to decodetree
      target/arm: Convert V[US]DOT (vector) to decodetree
      target/arm: Convert VFM[AS]L (vector) to decodetree
      target/arm: Convert VCMLA (scalar) to decodetree
      target/arm: Convert V[US]DOT (scalar) to decodetree
      target/arm: Convert VFM[AS]L (scalar) to decodetree
      target/arm: Convert Neon load/store multiple structures to decodetree
      target/arm: Convert Neon 'load single structure to all lanes' to decodetree
      target/arm: Convert Neon 'load/store single structure' to decodetree
      target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
      target/arm: Convert Neon 3-reg-same logic ops to decodetree
      target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
      target/arm: Convert Neon 3-reg-same comparisons to decodetree
      target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
      target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
      target/arm: Move gen_ function typedefs to translate.h

Philippe Mathieu-Daudé (2):
      hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string
      target/arm: Use uint64_t for midr field in CPU state struct

include/hw/arm/xlnx-versal.h    |  31 +-
 target/arm/cpu-param.h          |   2 +-
 target/arm/cpu.h                |  38 ++-
 target/arm/translate-a64.h      |   9 -
 target/arm/translate.h          |  26 ++
 target/arm/neon-dp.decode       |  86 +++++
 target/arm/neon-ls.decode       |  52 +++
 target/arm/neon-shared.decode   |  66 ++++
 hw/arm/mps2-tz.c                |   2 +-
 hw/arm/xlnx-versal-virt.c       |  74 ++++-
 hw/arm/xlnx-versal.c            | 115 +++++--
 target/arm/cpu.c                |   3 +-
 target/arm/cpu64.c              |   8 +-
 target/arm/helper.c             | 183 ++++------
 target/arm/translate-a64.c      |  17 -
 target/arm/translate-neon.inc.c | 714 +++++++++++++++++++++++++++++++++++++++
 target/arm/translate-vfp.inc.c  |   6 -
 target/arm/translate.c          | 716 +++-------------------------------------
 target/arm/Makefile.objs        |  18 +
 19 files changed, 1302 insertions(+), 864 deletions(-)
 create mode 100644 target/arm/neon-dp.decode
 create mode 100644 target/arm/neon-ls.decode
 create mode 100644 target/arm/neon-shared.decode
 create mode 100644 target/arm/translate-neon.inc.c

From: Fredrik Strupe <fredrik@strupe.net>

According to Arm ARM, VQDMULL is only valid when U=0, while having
U=1 is unallocated.

Signed-off-by: Fredrik Strupe <fredrik@strupe.net>
Fixes: 695272dcb976 ("target-arm: Handle UNDEF cases for Neon 3-regs-different-widths")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     {0, 0, 0, 0}, /* VMLSL */
                     {0, 0, 0, 9}, /* VQDMLSL */
                     {0, 0, 0, 0}, /* Integer VMULL */
-                    {0, 0, 0, 1}, /* VQDMULL */
+                    {0, 0, 0, 9}, /* VQDMULL */
                     {0, 0, 0, 0xa}, /* Polynomial VMULL */
                     {0, 0, 0, 7}, /* Reserved: always UNDEF */
                 };
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

By using the TYPE_* definitions for devices, we can:
 - quickly find where devices are used with 'git-grep'
 - easily rename a device (one-line change).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200428154650.21991-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mps2-tz.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
         exit(EXIT_FAILURE);
     }
 
-    sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
+    sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
                           sizeof(mms->iotkit), mmc->armsse_type);
     iotkitdev = DEVICE(&mms->iotkit);
     object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
-- 
2.20.1

We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU
TLB.  However we never actually use the TLB -- all stage 2 lookups
are done by direct calls to get_phys_addr_lpae() followed by a
physical address load via address_space_ld*().

Remove Stage2 from the list of ARM MMU indexes which correspond to
real core MMU indexes, and instead put it in the set of "NOTLB" ARM
MMU indexes.

This allows us to drop NB_MMU_MODES to 11.  It also means we can
safely add support for the ARMv8.3-TTS2UXN extension, which adds
permission bits to the stage 2 descriptors which define execute
permission separatel for EL0 and EL1; supporting that while keeping
Stage2 in a QEMU TLB would require us to use separate TLBs for
"Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a
lot of extra complication given we aren't even using the QEMU TLB.

In the process of updating the comment on our MMU index use,
fix a couple of other minor errors:
 * NS EL2 EL2&0 was missing from the list in the comment
 * some text hadn't been updated from when we bumped NB_MMU_MODES
   above 8

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200330210400.11724-2-peter.maydell@linaro.org
---
 target/arm/cpu-param.h |   2 +-
 target/arm/cpu.h       |  21 +++++---
 target/arm/helper.c    | 112 ++++-------------------------------------
 3 files changed, 27 insertions(+), 108 deletions(-)

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -XXX,XX +XXX,XX @@
 # define TARGET_PAGE_BITS_MIN  10
 #endif
 
-#define NB_MMU_MODES 12
+#define NB_MMU_MODES 11
 
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  *     handling via the TLB. The only way to do a stage 1 translation without
  *     the immediate stage 2 translation is via the ATS or AT system insns,
  *     which can be slow-pathed and always do a page table walk.
+ *     The only use of stage 2 translations is either as part of an s1+2
+ *     lookup or when loading the descriptors during a stage 1 page table walk,
+ *     and in both those cases we don't use the TLB.
  *  4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
  *     translation regimes, because they map reasonably well to each other
  *     and they can't both be active at the same time.
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
  * NS EL1 EL1&0 stage 1+2 +PAN
  * NS EL0 EL2&0
+ * NS EL2 EL2&0
  * NS EL2 EL2&0 +PAN
  * NS EL2 (aka NS PL2)
  * S EL0 EL1&0 (aka S PL0)
  * S EL1 EL1&0 (not used if EL3 is 32 bit)
  * S EL1 EL1&0 +PAN
  * S EL3 (aka S PL1)
- * NS EL1&0 stage 2
  *
- * for a total of 12 different mmu_idx.
+ * for a total of 11 different mmu_idx.
  *
  * R profile CPUs have an MPU, but can use the same set of MMU indexes
  * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  * are not quite the same -- different CPU types (most notably M profile
  * vs A/R profile) would like to use MMU indexes with different semantics,
  * but since we don't ever need to use all of those in a single CPU we
- * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
+ * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
+ * modes + total number of M profile MMU modes". The lower bits of
  * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
  * the same for any particular CPU.
  * Variables of type ARMMUIdx are always full values, and the core
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
     ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
     ARMMMUIdx_SE3        = 10 | ARM_MMU_IDX_A,
 
-    ARMMMUIdx_Stage2     = 11 | ARM_MMU_IDX_A,
-
     /*
      * These are not allocated TLBs and are used only for AT system
      * instructions or for the first stage of an S12 page table walk.
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
     ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
     ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
+    /*
+     * Not allocated a TLB: used only for second stage of an S12 page
+     * table walk, or for descriptor loads during first stage of an S1
+     * page table walk. Note that if we ever want to have a TLB for this
+     * then various TLB flush insns which currently are no-ops or flush
+     * only stage 1 MMU indexes will need to change to flush stage 2.
+     */
+    ARMMMUIdx_Stage2     = 3 | ARM_MMU_IDX_NOTLB,
 
     /*
      * M-profile.
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
     TO_CORE_BIT(SE10_1),
     TO_CORE_BIT(SE10_1_PAN),
     TO_CORE_BIT(SE3),
-    TO_CORE_BIT(Stage2),
 
     TO_CORE_BIT(MUser),
     TO_CORE_BIT(MPriv),
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx(cs,
                         ARMMMUIdxBit_E10_1 |
                         ARMMMUIdxBit_E10_1_PAN |
-                        ARMMMUIdxBit_E10_0 |
-                        ARMMMUIdxBit_Stage2);
+                        ARMMMUIdxBit_E10_0);
 }
 
 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx_all_cpus_synced(cs,
                                         ARMMMUIdxBit_E10_1 |
                                         ARMMMUIdxBit_E10_1_PAN |
-                                        ARMMMUIdxBit_E10_0 |
-                                        ARMMMUIdxBit_Stage2);
+                                        ARMMMUIdxBit_E10_0);
 }
 
-static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                            uint64_t value)
-{
-    /* Invalidate by IPA. This has to invalidate any structures that
-     * contain only stage 2 translation information, but does not need
-     * to apply to structures that contain combined stage 1 and stage 2
-     * translation information.
-     * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
-     */
-    CPUState *cs = env_cpu(env);
-    uint64_t pageaddr;
-
-    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
-        return;
-    }
-
-    pageaddr = sextract64(value << 12, 0, 40);
-
-    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
-}
-
-static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                               uint64_t value)
-{
-    CPUState *cs = env_cpu(env);
-    uint64_t pageaddr;
-
-    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
-        return;
-    }
-
-    pageaddr = sextract64(value << 12, 0, 40);
-
-    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                             ARMMMUIdxBit_Stage2);
-}
 
 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
                               uint64_t value)
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         tlb_flush_by_mmuidx(cs,
                             ARMMMUIdxBit_E10_1 |
                             ARMMMUIdxBit_E10_1_PAN |
-                            ARMMMUIdxBit_E10_0 |
-                            ARMMMUIdxBit_Stage2);
+                            ARMMMUIdxBit_E10_0);
         raw_write(env, ri, value);
     }
 }
@@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env)
         return ARMMMUIdxBit_SE10_1 |
                ARMMMUIdxBit_SE10_1_PAN |
                ARMMMUIdxBit_SE10_0;
-    } else if (arm_feature(env, ARM_FEATURE_EL2)) {
-        return ARMMMUIdxBit_E10_1 |
-               ARMMMUIdxBit_E10_1_PAN |
-               ARMMMUIdxBit_E10_0 |
-               ARMMMUIdxBit_Stage2;
     } else {
         return ARMMMUIdxBit_E10_1 |
                ARMMMUIdxBit_E10_1_PAN |
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                              ARMMMUIdxBit_SE3);
 }
 
-static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                    uint64_t value)
-{
-    /* Invalidate by IPA. This has to invalidate any structures that
-     * contain only stage 2 translation information, but does not need
-     * to apply to structures that contain combined stage 1 and stage 2
-     * translation information.
-     * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
-     */
-    ARMCPU *cpu = env_archcpu(env);
-    CPUState *cs = CPU(cpu);
-    uint64_t pageaddr;
-
-    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
-        return;
-    }
-
-    pageaddr = sextract64(value << 12, 0, 48);
-
-    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
-}
-
-static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                      uint64_t value)
-{
-    CPUState *cs = env_cpu(env);
-    uint64_t pageaddr;
-
-    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
-        return;
-    }
-
-    pageaddr = sextract64(value << 12, 0, 48);
-
-    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                             ARMMMUIdxBit_Stage2);
-}
-
 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                       bool isread)
 {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
-      .writefn = tlbi_aa64_ipas2e1is_write },
+      .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
-      .writefn = tlbi_aa64_ipas2e1is_write },
+      .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
       .access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbi_aa64_alle1is_write },
     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
-      .writefn = tlbi_aa64_ipas2e1_write },
+      .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
-      .writefn = tlbi_aa64_ipas2e1_write },
+      .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
       .access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbimva_hyp_is_write },
     { .name = "TLBIIPAS2",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
-      .writefn = tlbiipas2_write },
+      .type = ARM_CP_NOP, .access = PL2_W },
     { .name = "TLBIIPAS2IS",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
-      .writefn = tlbiipas2_is_write },
+      .type = ARM_CP_NOP, .access = PL2_W },
     { .name = "TLBIIPAS2L",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
-      .writefn = tlbiipas2_write },
+      .type = ARM_CP_NOP, .access = PL2_W },
     { .name = "TLBIIPAS2LIS",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
-      .writefn = tlbiipas2_is_write },
+      .type = ARM_CP_NOP, .access = PL2_W },
     /* 32 bit cache operations */
     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
-- 
2.20.1

The access_type argument to get_phys_addr_lpae() is an MMUAccessType;
use the enum constant MMU_DATA_LOAD rather than a literal 0 when we
call it in S1_ptw_translate().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200330210400.11724-3-peter.maydell@linaro.org
---
 target/arm/helper.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
             pcacheattrs = &cacheattrs;
         }
 
-        ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa,
-                                 &txattrs, &s2prot, &s2size, fi, pcacheattrs);
+        ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
+                                 &s2pa, &txattrs, &s2prot, &s2size, fi,
+                                 pcacheattrs);
         if (ret) {
             assert(fi->type != ARMFault_None);
             fi->s2addr = addr;
-- 
2.20.1

For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know
whether the stage 1 access is for EL0 or not, because whether
exec permission is given can depend on whether this is an EL0
or EL1 access. Add a new argument to get_phys_addr_lpae() so
the call sites can pass this information in.

Since get_phys_addr_lpae() doesn't already have a doc comment,
add one so we have a place to put the documentation of the
semantics of the new s1_is_el0 argument.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200330210400.11724-4-peter.maydell@linaro.org
---
 target/arm/helper.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
 
 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                               bool s1_is_el0,
                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
                                target_ulong *page_size_ptr,
                                ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
         }
 
         ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
+                                 false,
                                  &s2pa, &txattrs, &s2prot, &s2size, fi,
                                  pcacheattrs);
         if (ret) {
@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
     };
 }
 
+/**
+ * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
+ *
+ * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
+ * prot and page_size may not be filled in, and the populated fsr value provides
+ * information on why the translation aborted, in the format of a long-format
+ * DFSR/IFSR fault register, with the following caveats:
+ *  * the WnR bit is never set (the caller must do this).
+ *
+ * @env: CPUARMState
+ * @address: virtual address to get physical address for
+ * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
+ * @mmu_idx: MMU index indicating required translation regime
+ * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
+ *             walk), must be true if this is stage 2 of a stage 1+2 walk for an
+ *             EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
+ * @phys_ptr: set to the physical address corresponding to the virtual address
+ * @attrs: set to the memory transaction attributes to use
+ * @prot: set to the permissions for the page containing phys_ptr
+ * @page_size_ptr: set to the size of the page containing phys_ptr
+ * @fi: set to fault info if the translation fails
+ * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
+ */
 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                               bool s1_is_el0,
                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
                                target_ulong *page_size_ptr,
                                ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
 
             /* S1 is done. Now do S2 translation.  */
             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,
+                                     mmu_idx == ARMMMUIdx_E10_0,
                                      phys_ptr, attrs, &s2_prot,
                                      page_size, fi,
                                      cacheattrs != NULL ? &cacheattrs2 : NULL);
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
     }
 
     if (regime_using_lpae_format(env, mmu_idx)) {
-        return get_phys_addr_lpae(env, address, access_type, mmu_idx,
+        return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
                                   phys_ptr, attrs, prot, page_size,
                                   fi, cacheattrs);
     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
-- 
2.20.1

The ARMv8.2-TTS2UXN feature extends the XN field in stage 2
translation table descriptors from just bit [54] to bits [54:53],
allowing stage 2 to control execution permissions separately for EL0
and EL1. Implement the new semantics of the XN field and enable
the feature for our 'max' CPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200330210400.11724-5-peter.maydell@linaro.org
---
 target/arm/cpu.h    | 15 +++++++++++++++
 target/arm/cpu.c    |  1 +
 target/arm/cpu64.c  |  2 ++
 target/arm/helper.c | 37 +++++++++++++++++++++++++++++++------
 4 files changed, 49 insertions(+), 6 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
 }
 
+static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
+}
+
 /*
  * 64-bit feature tests via id registers.
  */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
 }
 
+static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
+}
+
 /*
  * Feature tests for "does this exist in either 32-bit or 64-bit?"
  */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
     return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
 }
 
+static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
+}
+
 /*
  * Forward to the above feature tests given an ARMCPU pointer.
  */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
             t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
             t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
             t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+            t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
             cpu->isar.id_mmfr4 = t;
         }
 #endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
         t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
         t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
+        t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
         cpu->isar.id_aa64mmfr1 = t;
 
         t = cpu->isar.id_aa64mmfr2;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
         u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
         u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
+        u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
         cpu->isar.id_mmfr4 = u;
 
         u = cpu->isar.id_aa64dfr0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
  *
  * @env:     CPUARMState
  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
- * @xn:      XN (execute-never) bit
+ * @xn:      XN (execute-never) bits
+ * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
  */
-static int get_S2prot(CPUARMState *env, int s2ap, int xn)
+static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
 {
     int prot = 0;
 
@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn)
     if (s2ap & 2) {
         prot |= PAGE_WRITE;
     }
-    if (!xn) {
-        if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
+
+    if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {
+        switch (xn) {
+        case 0:
             prot |= PAGE_EXEC;
+            break;
+        case 1:
+            if (s1_is_el0) {
+                prot |= PAGE_EXEC;
+            }
+            break;
+        case 2:
+            break;
+        case 3:
+            if (!s1_is_el0) {
+                prot |= PAGE_EXEC;
+            }
+            break;
+        default:
+            g_assert_not_reached();
+        }
+    } else {
+        if (!extract32(xn, 1, 1)) {
+            if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
+                prot |= PAGE_EXEC;
+            }
         }
     }
     return prot;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
     }
 
     ap = extract32(attrs, 4, 2);
-    xn = extract32(attrs, 12, 1);
 
     if (mmu_idx == ARMMMUIdx_Stage2) {
         ns = true;
-        *prot = get_S2prot(env, ap, xn);
+        xn = extract32(attrs, 11, 2);
+        *prot = get_S2prot(env, ap, xn, s1_is_el0);
     } else {
         ns = extract32(attrs, 3, 1);
+        xn = extract32(attrs, 12, 1);
         pxn = extract32(attrs, 11, 1);
         *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
     }
-- 
2.20.1

In aarch64_max_initfn() we update both 32-bit and 64-bit ID
registers.  The intended pattern is that for 64-bit ID registers we
use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
registers use FIELD_DP32 and the uint32_t 'u' register.  For
ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of
this 64-bit ID register would end up always zero.  Luckily at the
moment that's what they should be anyway, so this bug has no visible
effects.

Use the right-sized variable.

Fixes: 3bec78447a958d481991
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200423110915.10527-1-peter.maydell@linaro.org
---
 target/arm/cpu64.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
         cpu->isar.id_mmfr4 = u;
 
-        u = cpu->isar.id_aa64dfr0;
-        u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
-        cpu->isar.id_aa64dfr0 = u;
+        t = cpu->isar.id_aa64dfr0;
+        t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+        cpu->isar.id_aa64dfr0 = t;
 
         u = cpu->isar.id_dfr0;
         u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.
Represent it in QEMU's ARMCPU struct with a uint64_t, not a
uint32_t.

This fixes an error when compiling with -Werror=conversion
because we were manipulating the register value using a
local uint64_t variable:

target/arm/cpu64.c: In function ‘aarch64_max_initfn’:
  target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]
    628 |         cpu->midr = t;
        |                     ^

and future-proofs us against a possible future architecture
change using some of the top 32 bits.

Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20200428172634.29707-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 2 +-
 target/arm/cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
         uint64_t id_aa64dfr0;
         uint64_t id_aa64dfr1;
     } isar;
-    uint32_t midr;
+    uint64_t midr;
     uint32_t revidr;
     uint32_t reset_fpsid;
     uint32_t ctr;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
 static Property arm_cpu_properties[] = {
     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
-    DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
+    DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
                         mp_affinity, ARM64_AFFINITY_INVALID),
     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Move misplaced comment.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-3-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-versal.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
 
         obj = object_new(XLNX_VERSAL_ACPU_TYPE);
         if (!obj) {
-            /* Secondary CPUs start in PSCI powered-down state */
             error_report("Unable to create apu.cpu[%d] of type %s",
                          i, XLNX_VERSAL_ACPU_TYPE);
             exit(EXIT_FAILURE);
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
         object_property_set_int(obj, s->cfg.psci_conduit,
                                 "psci-conduit", &error_abort);
         if (i) {
+            /* Secondary CPUs start in PSCI powered-down state */
             object_property_set_bool(obj, true,
                                      "start-powered-off", &error_abort);
         }
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Fix typo xlnx-ve -> xlnx-versal.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-4-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-versal-virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
         psci_conduit = QEMU_PSCI_CONDUIT_SMC;
     }
 
-    sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
+    sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc,
                           sizeof(s->soc), TYPE_XLNX_VERSAL);
     object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
                              "ddr", &error_abort);
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the UARTs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-5-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  3 ++-
 hw/arm/xlnx-versal.c         | 12 ++++++------
 2 files changed, 8 insertions(+), 7 deletions(-)

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the GEMs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-6-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  3 ++-
 hw/arm/xlnx-versal.c         | 15 ++++++++-------
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/boot.h"
 #include "hw/intc/arm_gicv3.h"
 #include "hw/char/pl011.h"
+#include "hw/net/cadence_gem.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
 #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
 
         struct {
             PL011State uart[XLNX_VERSAL_NR_UARTS];
-            SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
+            CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
             SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
         } iou;
     } lpd;
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
         DeviceState *dev;
         MemoryRegion *mr;
 
-        dev = qdev_create(NULL, "cadence_gem");
-        s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);
-        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
+        sysbus_init_child_obj(OBJECT(s), name,
+                              &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]),
+                              TYPE_CADENCE_GEM);
+        dev = DEVICE(&s->lpd.iou.gem[i]);
         if (nd->used) {
             qemu_check_nic_model(nd, "cadence_gem");
             qdev_set_nic_properties(dev, nd);
         }
-        object_property_set_int(OBJECT(s->lpd.iou.gem[i]),
+        object_property_set_int(OBJECT(dev),
                                 2, "num-priority-queues",
                                 &error_abort);
-        object_property_set_link(OBJECT(s->lpd.iou.gem[i]),
+        object_property_set_link(OBJECT(dev),
                                  OBJECT(&s->mr_ps), "dma",
                                  &error_abort);
         qdev_init_nofail(dev);
 
-        mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);
+        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
         memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
 
-        sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
         g_free(name);
     }
 }
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the ADMAs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-7-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  3 ++-
 hw/arm/xlnx-versal.c         | 14 +++++++-------
 2 files changed, 9 insertions(+), 8 deletions(-)

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the APUs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-8-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  2 +-
 hw/arm/xlnx-versal-virt.c    |  4 ++--
 hw/arm/xlnx-versal.c         | 19 +++++--------------
 3 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
     struct {
         struct {
             MemoryRegion mr;
-            ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
+            ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
             GICv3State gic;
         } apu;
     } fpd;
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
     s->binfo.get_dtb = versal_virt_get_dtb;
     s->binfo.modify_dtb = versal_virt_modify_dtb;
     if (machine->kernel_filename) {
-        arm_load_kernel(s->soc.fpd.apu.cpu[0], machine, &s->binfo);
+        arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo);
     } else {
-        AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
+        AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0],
                                                   &s->binfo);
         /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
          * Offset things by 4K.  */
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
 
     for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
         Object *obj;
-        char *name;
-
-        obj = object_new(XLNX_VERSAL_ACPU_TYPE);
-        if (!obj) {
-            error_report("Unable to create apu.cpu[%d] of type %s",
-                         i, XLNX_VERSAL_ACPU_TYPE);
-            exit(EXIT_FAILURE);
-        }
-
-        name = g_strdup_printf("apu-cpu[%d]", i);
-        object_property_add_child(OBJECT(s), name, obj, &error_fatal);
-        g_free(name);
 
+        object_initialize_child(OBJECT(s), "apu-cpu[*]",
+                                &s->fpd.apu.cpu[i], sizeof(s->fpd.apu.cpu[i]),
+                                XLNX_VERSAL_ACPU_TYPE, &error_abort, NULL);
+        obj = OBJECT(&s->fpd.apu.cpu[i]);
         object_property_set_int(obj, s->cfg.psci_conduit,
                                 "psci-conduit", &error_abort);
         if (i) {
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
         object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
                                  &error_abort);
         object_property_set_bool(obj, true, "realized", &error_fatal);
-        s->fpd.apu.cpu[i] = ARM_CPU(obj);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
     }
 
     for (i = 0; i < nr_apu_cpus; i++) {
-        DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);
+        DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]);
         int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
         qemu_irq maint_irq;
         int ti;
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add support for SD.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-9-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h | 12 ++++++++++++
 hw/arm/xlnx-versal.c         | 31 +++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/sysbus.h"
 #include "hw/arm/boot.h"
+#include "hw/sd/sdhci.h"
 #include "hw/intc/arm_gicv3.h"
 #include "hw/char/pl011.h"
 #include "hw/dma/xlnx-zdma.h"
@@ -XXX,XX +XXX,XX @@
 #define XLNX_VERSAL_NR_UARTS   2
 #define XLNX_VERSAL_NR_GEMS    2
 #define XLNX_VERSAL_NR_ADMAS   8
+#define XLNX_VERSAL_NR_SDS     2
 #define XLNX_VERSAL_NR_IRQS    192
 
 typedef struct Versal {
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
         } iou;
     } lpd;
 
+    /* The Platform Management Controller subsystem.  */
+    struct {
+        struct {
+            SDHCIState sd[XLNX_VERSAL_NR_SDS];
+        } iou;
+    } pmc;
+
     struct {
         MemoryRegion *mr_ddr;
         uint32_t psci_conduit;
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
 #define VERSAL_GEM1_IRQ_0          58
 #define VERSAL_GEM1_WAKE_IRQ_0     59
 #define VERSAL_ADMA_IRQ_0          60
+#define VERSAL_SD0_IRQ_0           126
 
 /* Architecturally reserved IRQs suitable for virtualization.  */
 #define VERSAL_RSVD_IRQ_FIRST 111
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
 #define MM_FPD_CRF                  0xfd1a0000U
 #define MM_FPD_CRF_SIZE             0x140000
 
+#define MM_PMC_SD0                  0xf1040000U
+#define MM_PMC_SD0_SIZE             0x10000
 #define MM_PMC_CRP                  0xf1260000U
 #define MM_PMC_CRP_SIZE             0x10000
 #endif
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
     }
 }
 
+#define SDHCI_CAPABILITIES  0x280737ec6481 /* Same as on ZynqMP.  */
+static void versal_create_sds(Versal *s, qemu_irq *pic)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) {
+        DeviceState *dev;
+        MemoryRegion *mr;
+
+        sysbus_init_child_obj(OBJECT(s), "sd[*]",
+                              &s->pmc.iou.sd[i], sizeof(s->pmc.iou.sd[i]),
+                              TYPE_SYSBUS_SDHCI);
+        dev = DEVICE(&s->pmc.iou.sd[i]);
+
+        object_property_set_uint(OBJECT(dev),
+                                 3, "sd-spec-version", &error_fatal);
+        object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg",
+                                 &error_fatal);
+        object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal);
+        qdev_init_nofail(dev);
+
+        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+        memory_region_add_subregion(&s->mr_ps,
+                                    MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr);
+
+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
+                           pic[VERSAL_SD0_IRQ_0 + i * 2]);
+    }
+}
+
 /* This takes the board allocated linear DDR memory and creates aliases
  * for each split DDR range/aperture on the Versal address map.
  */
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_uarts(s, pic);
     versal_create_gems(s, pic);
     versal_create_admas(s, pic);
+    versal_create_sds(s, pic);
     versal_map_ddr(s);
     versal_unimp(s);
 
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

hw/arm: versal: Add support for the RTC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-10-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  8 ++++++++
 hw/arm/xlnx-versal.c         | 21 +++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/pl011.h"
 #include "hw/dma/xlnx-zdma.h"
 #include "hw/net/cadence_gem.h"
+#include "hw/rtc/xlnx-zynqmp-rtc.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
 #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
         struct {
             SDHCIState sd[XLNX_VERSAL_NR_SDS];
         } iou;
+
+        XlnxZynqMPRTC rtc;
     } pmc;
 
     struct {
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
 #define VERSAL_GEM1_IRQ_0          58
 #define VERSAL_GEM1_WAKE_IRQ_0     59
 #define VERSAL_ADMA_IRQ_0          60
+#define VERSAL_RTC_APB_ERR_IRQ     121
 #define VERSAL_SD0_IRQ_0           126
+#define VERSAL_RTC_ALARM_IRQ       142
+#define VERSAL_RTC_SECONDS_IRQ     143
 
 /* Architecturally reserved IRQs suitable for virtualization.  */
 #define VERSAL_RSVD_IRQ_FIRST 111
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
 #define MM_PMC_SD0_SIZE             0x10000
 #define MM_PMC_CRP                  0xf1260000U
 #define MM_PMC_CRP_SIZE             0x10000
+#define MM_PMC_RTC                  0xf12a0000
+#define MM_PMC_RTC_SIZE             0x10000
 #endif
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_sds(Versal *s, qemu_irq *pic)
     }
 }
 
+static void versal_create_rtc(Versal *s, qemu_irq *pic)
+{
+    SysBusDevice *sbd;
+    MemoryRegion *mr;
+
+    sysbus_init_child_obj(OBJECT(s), "rtc", &s->pmc.rtc, sizeof(s->pmc.rtc),
+                          TYPE_XLNX_ZYNQMP_RTC);
+    sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
+    qdev_init_nofail(DEVICE(sbd));
+
+    mr = sysbus_mmio_get_region(sbd, 0);
+    memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
+
+    /*
+     * TODO: Connect the ALARM and SECONDS interrupts once our RTC model
+     * supports them.
+     */
+    sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
+}
+
 /* This takes the board allocated linear DDR memory and creates aliases
  * for each split DDR range/aperture on the Versal address map.
  */
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_gems(s, pic);
     versal_create_admas(s, pic);
     versal_create_sds(s, pic);
+    versal_create_rtc(s, pic);
     versal_map_ddr(s);
     versal_unimp(s);
 
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add support for SD.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-11-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-versal-virt.c | 46 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/sysbus-fdt.h"
 #include "hw/arm/fdt.h"
 #include "cpu.h"
+#include "hw/qdev-properties.h"
 #include "hw/arm/xlnx-versal.h"
 
 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
@@ -XXX,XX +XXX,XX @@ static void fdt_add_zdma_nodes(VersalVirt *s)
     }
 }
 
+static void fdt_add_sd_nodes(VersalVirt *s)
+{
+    const char clocknames[] = "clk_xin\0clk_ahb";
+    const char compat[] = "arasan,sdhci-8.9a";
+    int i;
+
+    for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) {
+        uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i;
+        char *name = g_strdup_printf("/sdhci@%" PRIx64, addr);
+
+        qemu_fdt_add_subnode(s->fdt, name);
+
+        qemu_fdt_setprop_cells(s->fdt, name, "clocks",
+                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
+        qemu_fdt_setprop(s->fdt, name, "clock-names",
+                         clocknames, sizeof(clocknames));
+        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+                               GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2,
+                               GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                     2, addr, 2, MM_PMC_SD0_SIZE);
+        qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
+        g_free(name);
+    }
+}
+
 static void fdt_nop_memory_nodes(void *fdt, Error **errp)
 {
     Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
     }
 }
 
+static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
+{
+    BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
+    DeviceState *card;
+
+    card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD);
+    object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card),
+                              &error_fatal);
+    qdev_prop_set_drive(card, "drive", blk, &error_fatal);
+    object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
+}
+
 static void versal_virt_init(MachineState *machine)
 {
     VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
     int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
+    int i;
 
     /*
      * If the user provides an Operating System to be loaded, we expect them
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
     fdt_add_gic_nodes(s);
     fdt_add_timer_nodes(s);
     fdt_add_zdma_nodes(s);
+    fdt_add_sd_nodes(s);
     fdt_add_cpu_nodes(s, psci_conduit);
     fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
     memory_region_add_subregion_overlap(get_system_memory(),
                                         0, &s->soc.fpd.apu.mr, 0);
 
+    /* Plugin SD cards.  */
+    for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
+        sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
+    }
+
     s->binfo.ram_size = machine->ram_size;
     s->binfo.loader_start = 0x0;
     s->binfo.get_dtb = versal_virt_get_dtb;
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add support for the RTC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-12-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-versal-virt.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_sd_nodes(VersalVirt *s)
     }
 }
 
+static void fdt_add_rtc_node(VersalVirt *s)
+{
+    const char compat[] = "xlnx,zynqmp-rtc";
+    const char interrupt_names[] = "alarm\0sec";
+    char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC);
+
+    qemu_fdt_add_subnode(s->fdt, name);
+
+    qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+                           GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ,
+                           GIC_FDT_IRQ_FLAGS_LEVEL_HI,
+                           GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ,
+                           GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+    qemu_fdt_setprop(s->fdt, name, "interrupt-names",
+                     interrupt_names, sizeof(interrupt_names));
+    qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE);
+    qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
+    g_free(name);
+}
+
 static void fdt_nop_memory_nodes(void *fdt, Error **errp)
 {
     Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
     fdt_add_timer_nodes(s);
     fdt_add_zdma_nodes(s);
     fdt_add_sd_nodes(s);
+    fdt_add_rtc_node(s);
     fdt_add_cpu_nodes(s, psci_conduit);
     fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
-- 
2.20.1

Somewhere along theline we accidentally added a duplicate
"using D16-D31 when they don't exist" check to do_vfm_dp()
(probably an artifact of a patchseries rebase). Remove it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200430181003.21682-2-peter.maydell@linaro.org
---
 target/arm/translate-vfp.inc.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
         return false;
     }
 
-    /* UNDEF accesses to D16-D31 if they don't exist. */
-    if (!dc_isar_feature(aa32_simd_r32, s) &&
-        ((a->vd | a->vn | a->vm) & 0x10)) {
-        return false;
-    }
-
     if (!vfp_access_check(s)) {
         return true;
     }
-- 
2.20.1

We were accidentally permitting decode of Thumb Neon insns even if
the CPU didn't have the FEATURE_NEON bit set, because the feature
check was being done before the call to disas_neon_data_insn() and
disas_neon_ls_insn() in the Arm decoder but was omitted from the
Thumb decoder.  Push the feature bit check down into the called
functions so it is done for both Arm and Thumb encodings.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200430181003.21682-3-peter.maydell@linaro.org
---
 target/arm/translate.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
     TCGv_i32 tmp2;
     TCGv_i64 tmp64;
 
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return 1;
+    }
+
     /* FIXME: this access check should not take precedence over UNDEF
      * for invalid encodings; we will generate incorrect syndrome information
      * for attempts to execute invalid vfp/neon encodings with FP disabled.
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     TCGv_ptr ptr1, ptr2, ptr3;
     TCGv_i64 tmp64;
 
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return 1;
+    }
+
     /* FIXME: this access check should not take precedence over UNDEF
      * for invalid encodings; we will generate incorrect syndrome information
      * for attempts to execute invalid vfp/neon encodings with FP disabled.
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
 
         if (((insn >> 25) & 7) == 1) {
             /* NEON Data processing.  */
-            if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-                goto illegal_op;
-            }
-
             if (disas_neon_data_insn(s, insn)) {
                 goto illegal_op;
             }
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
         }
         if ((insn & 0x0f100000) == 0x04000000) {
             /* NEON load/store.  */
-            if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-                goto illegal_op;
-            }
-
             if (disas_neon_ls_insn(s, insn)) {
                 goto illegal_op;
             }
-- 
2.20.1

Add the infrastructure for building and invoking a decodetree decoder
for the AArch32 Neon encodings.  At the moment the new decoder covers
nothing, so we always fall back to the existing hand-written decode.

We follow the same pattern we did for the VFP decodetree conversion
(commit 78e138bc1f672c145ef6ace74617d and following): code that deals
with Neon will be moving gradually out to translate-neon.vfp.inc,
which we #include into translate.c.

In order to share the decode files between A32 and T32, we
split Neon into 3 parts:
 * data-processing
 * load-store
 * 'shared' encodings

The first two groups of instructions have similar but not identical
A32 and T32 encodings, so we need to manually transform the T32
encoding into the A32 one before calling the decoder; the third group
covers the Neon instructions which are identical in A32 and T32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-4-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 29 ++++++++++++++++++++++++++
 target/arm/neon-ls.decode       | 29 ++++++++++++++++++++++++++
 target/arm/neon-shared.decode   | 27 +++++++++++++++++++++++++
 target/arm/translate-neon.inc.c | 32 +++++++++++++++++++++++++++++
 target/arm/translate.c          | 36 +++++++++++++++++++++++++++++++--
 target/arm/Makefile.objs        | 18 +++++++++++++++++
 6 files changed, 169 insertions(+), 2 deletions(-)
 create mode 100644 target/arm/neon-dp.decode
 create mode 100644 target/arm/neon-ls.decode
 create mode 100644 target/arm/neon-shared.decode
 create mode 100644 target/arm/translate-neon.inc.c

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@
+# AArch32 Neon data-processing instruction descriptions
+#
+#  Copyright (c) 2020 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
+
+# Encodings for Neon data processing instructions where the T32 encoding
+# is a simple transformation of the A32 encoding.
+# More specifically, this file covers instructions where the A32 encoding is
+#   0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
+# and the T32 encoding is
+#   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
+# This file works on the A32 encoding only; calling code for T32 has to
+# transform the insn into the A32 version first.
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/neon-ls.decode
@@ -XXX,XX +XXX,XX @@
+# AArch32 Neon load/store instruction descriptions
+#
+#  Copyright (c) 2020 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
+
+# Encodings for Neon load/store instructions where the T32 encoding
+# is a simple transformation of the A32 encoding.
+# More specifically, this file covers instructions where the A32 encoding is
+#   0b1111_0100_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
+# and the T32 encoding is
+#   0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
+# This file works on the A32 encoding only; calling code for T32 has to
+# transform the insn into the A32 version first.
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@
+# AArch32 Neon instruction descriptions
+#
+#  Copyright (c) 2020 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
+
+# Encodings for Neon instructions whose encoding is the same for
+# both A32 and T32.
+
+# More specifically, this covers:
+# 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
+# 3same ext:       0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ *  ARM translation: AArch32 Neon instructions
+ *
+ *  Copyright (c) 2003 Fabrice Bellard
+ *  Copyright (c) 2005-2007 CodeSourcery
+ *  Copyright (c) 2007 OpenedHand, Ltd.
+ *  Copyright (c) 2020 Linaro, Ltd.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * This file is intended to be included from translate.c; it uses
+ * some macros and definitions provided by that file.
+ * It might be possible to convert it to a standalone .c file eventually.
+ */
+
+/* Include the generated Neon decoder */
+#include "decode-neon-dp.inc.c"
+#include "decode-neon-ls.inc.c"
+#include "decode-neon-shared.inc.c"
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
 
 #define ARM_CP_RW_BIT   (1 << 20)
 
-/* Include the VFP decoder */
+/* Include the VFP and Neon decoders */
 #include "translate-vfp.inc.c"
+#include "translate-neon.inc.c"
 
 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
 {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
         /* Unconditional instructions.  */
         /* TODO: Perhaps merge these into one decodetree output file.  */
         if (disas_a32_uncond(s, insn) ||
-            disas_vfp_uncond(s, insn)) {
+            disas_vfp_uncond(s, insn) ||
+            disas_neon_dp(s, insn) ||
+            disas_neon_ls(s, insn) ||
+            disas_neon_shared(s, insn)) {
             return;
         }
         /* fall back to legacy decoder */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
         ARCH(6T2);
     }
 
+    if ((insn & 0xef000000) == 0xef000000) {
+        /*
+         * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
+         * transform into
+         * A32 encodings 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
+         */
+        uint32_t a32_insn = (insn & 0xe2ffffff) |
+            ((insn & (1 << 28)) >> 4) | (1 << 28);
+
+        if (disas_neon_dp(s, a32_insn)) {
+            return;
+        }
+    }
+
+    if ((insn & 0xff100000) == 0xf9000000) {
+        /*
+         * T32 encodings 0b1111_1001_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
+         * transform into
+         * A32 encodings 0b1111_0100_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
+         */
+        uint32_t a32_insn = (insn & 0x00ffffff) | 0xf4000000;
+
+        if (disas_neon_ls(s, a32_insn)) {
+            return;
+        }
+    }
+
     /*
      * TODO: Perhaps merge these into one decodetree output file.
      * Note disas_vfp is written for a32 with cond field in the
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
      */
     if (disas_t32(s, insn) ||
         disas_vfp_uncond(s, insn) ||
+        disas_neon_shared(s, insn) ||
         ((insn >> 28) == 0xe && disas_vfp(s, insn))) {
         return;
     }
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -XXX,XX +XXX,XX @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
 	  $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
+target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
+	$(call quiet-command,\
+	  $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
+	  "GEN", $(TARGET_DIR)$@)
+
+target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
+	$(call quiet-command,\
+	  $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
+	  "GEN", $(TARGET_DIR)$@)
+
+target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
+	$(call quiet-command,\
+	  $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
+	  "GEN", $(TARGET_DIR)$@)
+
 target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
@@ -XXX,XX +XXX,XX @@ target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
 	  "GEN", $(TARGET_DIR)$@)
 
 target/arm/translate-sve.o: target/arm/decode-sve.inc.c
+target/arm/translate.o: target/arm/decode-neon-shared.inc.c
+target/arm/translate.o: target/arm/decode-neon-dp.inc.c
+target/arm/translate.o: target/arm/decode-neon-ls.inc.c
 target/arm/translate.o: target/arm/decode-vfp.inc.c
 target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
 target/arm/translate.o: target/arm/decode-a32.inc.c
-- 
2.20.1

Convert the VCMLA (vector) insns in the 3same extension group to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-5-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   | 11 ++++++++++
 target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 11 +---------
 3 files changed, 49 insertions(+), 10 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@
 # More specifically, this covers:
 # 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
 # 3same ext:       0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
+
+# VFP/Neon register fields; same as vfp.decode
+%vm_dp  5:1 0:4
+%vm_sp  0:4 5:1
+%vn_dp  7:1 16:4
+%vn_sp  16:4 7:1
+%vd_dp  22:1 12:4
+%vd_sp  12:4 22:1
+
+VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@
 #include "decode-neon-dp.inc.c"
 #include "decode-neon-ls.inc.c"
 #include "decode-neon-shared.inc.c"
+
+static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
+{
+    int opr_sz;
+    TCGv_ptr fpst;
+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
+
+    if (!dc_isar_feature(aa32_vcma, s)
+        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vn | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vn | a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    opr_sz = (1 + a->q) * 8;
+    fpst = get_fpstatus_ptr(1);
+    fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+                       vfp_reg_offset(1, a->vn),
+                       vfp_reg_offset(1, a->vm),
+                       fpst, opr_sz, opr_sz, a->rot,
+                       fn_gvec_ptr);
+    tcg_temp_free_ptr(fpst);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
     bool is_long = false, q = extract32(insn, 6, 1);
     bool ptr_is_env = false;
 
-    if ((insn & 0xfe200f10) == 0xfc200800) {
-        /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
-        int size = extract32(insn, 20, 1);
-        data = extract32(insn, 23, 2); /* rot */
-        if (!dc_isar_feature(aa32_vcma, s)
-            || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
-            return 1;
-        }
-        fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
-    } else if ((insn & 0xfea00f10) == 0xfc800800) {
+    if ((insn & 0xfea00f10) == 0xfc800800) {
         /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
         int size = extract32(insn, 20, 1);
         data = extract32(insn, 24, 1); /* rot */
-- 
2.20.1

Convert the VCADD (vector) insns to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-6-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |  3 +++
 target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 11 +---------
 3 files changed, 41 insertions(+), 10 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@
 
 VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
                vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
     tcg_temp_free_ptr(fpst);
     return true;
 }
+
+static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
+{
+    int opr_sz;
+    TCGv_ptr fpst;
+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
+
+    if (!dc_isar_feature(aa32_vcma, s)
+        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vn | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vn | a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    opr_sz = (1 + a->q) * 8;
+    fpst = get_fpstatus_ptr(1);
+    fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+                       vfp_reg_offset(1, a->vn),
+                       vfp_reg_offset(1, a->vm),
+                       fpst, opr_sz, opr_sz, a->rot,
+                       fn_gvec_ptr);
+    tcg_temp_free_ptr(fpst);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
     bool is_long = false, q = extract32(insn, 6, 1);
     bool ptr_is_env = false;
 
-    if ((insn & 0xfea00f10) == 0xfc800800) {
-        /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
-        int size = extract32(insn, 20, 1);
-        data = extract32(insn, 24, 1); /* rot */
-        if (!dc_isar_feature(aa32_vcma, s)
-            || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
-            return 1;
-        }
-        fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
-    } else if ((insn & 0xfeb00f00) == 0xfc200d00) {
+    if ((insn & 0xfeb00f00) == 0xfc200d00) {
         /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
         bool u = extract32(insn, 4, 1);
         if (!dc_isar_feature(aa32_dp, s)) {
-- 
2.20.1

Convert the V[US]DOT (vector) insns to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-7-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |  4 ++++
 target/arm/translate-neon.inc.c | 32 ++++++++++++++++++++++++++++++++
 target/arm/translate.c          |  9 +--------
 3 files changed, 37 insertions(+), 8 deletions(-)

Convert the VFM[AS]L (vector) insns to decodetree.  This is the last
insn in the legacy decoder for the 3same_ext group, so we can
delete the legacy decoder function for the group entirely.

Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false will correctly be directed
to illegal_op by the "(insn & (1 << 28))" check so they won't fall
into disas_coproc_insn() by mistake.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-8-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |  6 +++
 target/arm/translate-neon.inc.c | 31 +++++++++++
 target/arm/translate.c          | 92 +--------------------------------
 3 files changed, 38 insertions(+), 91 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@ VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
 # VUDOT and VSDOT
 VDOT           1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
                vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+# VFM[AS]L
+VFML           1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
+               vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0
+VFML           1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
                        opr_sz, opr_sz, 0, fn_gvec);
     return true;
 }
+
+static bool trans_VFML(DisasContext *s, arg_VFML *a)
+{
+    int opr_sz;
+
+    if (!dc_isar_feature(aa32_fhm, s)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        (a->vd & 0x10)) {
+        return false;
+    }
+
+    if (a->vd & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    opr_sz = (1 + a->q) * 8;
+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+                       vfp_reg_offset(a->q, a->vn),
+                       vfp_reg_offset(a->q, a->vm),
+                       cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
+                       gen_helper_gvec_fmlal_a32);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     return 0;
 }
 
-/* Advanced SIMD three registers of the same length extension.
- *  31           25    23  22    20   16   12  11   10   9    8        3     0
- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
- * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
- */
-static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
-{
-    gen_helper_gvec_3 *fn_gvec = NULL;
-    gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
-    int rd, rn, rm, opr_sz;
-    int data = 0;
-    int off_rn, off_rm;
-    bool is_long = false, q = extract32(insn, 6, 1);
-    bool ptr_is_env = false;
-
-    if ((insn & 0xff300f10) == 0xfc200810) {
-        /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
-        int is_s = extract32(insn, 23, 1);
-        if (!dc_isar_feature(aa32_fhm, s)) {
-            return 1;
-        }
-        is_long = true;
-        data = is_s; /* is_2 == 0 */
-        fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
-        ptr_is_env = true;
-    } else {
-        return 1;
-    }
-
-    VFP_DREG_D(rd, insn);
-    if (rd & q) {
-        return 1;
-    }
-    if (q || !is_long) {
-        VFP_DREG_N(rn, insn);
-        VFP_DREG_M(rm, insn);
-        if ((rn | rm) & q & !is_long) {
-            return 1;
-        }
-        off_rn = vfp_reg_offset(1, rn);
-        off_rm = vfp_reg_offset(1, rm);
-    } else {
-        rn = VFP_SREG_N(insn);
-        rm = VFP_SREG_M(insn);
-        off_rn = vfp_reg_offset(0, rn);
-        off_rm = vfp_reg_offset(0, rm);
-    }
-
-    if (s->fp_excp_el) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
-        return 0;
-    }
-    if (!s->vfp_enabled) {
-        return 1;
-    }
-
-    opr_sz = (1 + q) * 8;
-    if (fn_gvec_ptr) {
-        TCGv_ptr ptr;
-        if (ptr_is_env) {
-            ptr = cpu_env;
-        } else {
-            ptr = get_fpstatus_ptr(1);
-        }
-        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
-                           opr_sz, opr_sz, data, fn_gvec_ptr);
-        if (!ptr_is_env) {
-            tcg_temp_free_ptr(ptr);
-        }
-    } else {
-        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
-                           opr_sz, opr_sz, data, fn_gvec);
-    }
-    return 0;
-}
-
 /* Advanced SIMD two registers and a scalar extension.
  *  31             24   23  22   20   16   12  11   10   9    8        3     0
  * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                     }
                 }
             }
-        } else if ((insn & 0x0e000a00) == 0x0c000800
-                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
-            if (disas_neon_insn_3same_ext(s, insn)) {
-                goto illegal_op;
-            }
-            return;
         } else if ((insn & 0x0f000a00) == 0x0e000800
                    && arm_dc_feature(s, ARM_FEATURE_V8)) {
             if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
             }
             break;
         }
-        if ((insn & 0xfe000a00) == 0xfc000800
+        if ((insn & 0xff000a00) == 0xfe000800
             && arm_dc_feature(s, ARM_FEATURE_V8)) {
             /* The Thumb2 and ARM encodings are identical.  */
-            if (disas_neon_insn_3same_ext(s, insn)) {
-                goto illegal_op;
-            }
-        } else if ((insn & 0xff000a00) == 0xfe000800
-                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
-            /* The Thumb2 and ARM encodings are identical.  */
             if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
                 goto illegal_op;
             }
-- 
2.20.1

Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-9-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |  5 +++++
 target/arm/translate-neon.inc.c | 40 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 26 +--------------------
 3 files changed, 46 insertions(+), 25 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@ VFML           1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
                vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0
 VFML           1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
                vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
+
+VCMLA_scalar   1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
+               vn=%vn_dp vd=%vd_dp size=0
+VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VFML(DisasContext *s, arg_VFML *a)
                        gen_helper_gvec_fmlal_a32);
     return true;
 }
+
+static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
+{
+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
+    int opr_sz;
+    TCGv_ptr fpst;
+
+    if (!dc_isar_feature(aa32_vcma, s)) {
+        return false;
+    }
+    if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vn | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vd | a->vn) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx
+                   : gen_helper_gvec_fcmlah_idx);
+    opr_sz = (1 + a->q) * 8;
+    fpst = get_fpstatus_ptr(1);
+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+                       vfp_reg_offset(1, a->vn),
+                       vfp_reg_offset(1, a->vm),
+                       fpst, opr_sz, opr_sz,
+                       (a->index << 2) | a->rot, fn_gvec_ptr);
+    tcg_temp_free_ptr(fpst);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
     bool is_long = false, q = extract32(insn, 6, 1);
     bool ptr_is_env = false;
 
-    if ((insn & 0xff000f10) == 0xfe000800) {
-        /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
-        int rot = extract32(insn, 20, 2);
-        int size = extract32(insn, 23, 1);
-        int index;
-
-        if (!dc_isar_feature(aa32_vcma, s)) {
-            return 1;
-        }
-        if (size == 0) {
-            if (!dc_isar_feature(aa32_fp16_arith, s)) {
-                return 1;
-            }
-            /* For fp16, rm is just Vm, and index is M.  */
-            rm = extract32(insn, 0, 4);
-            index = extract32(insn, 5, 1);
-        } else {
-            /* For fp32, rm is the usual M:Vm, and index is 0.  */
-            VFP_DREG_M(rm, insn);
-            index = 0;
-        }
-        data = (index << 2) | rot;
-        fn_gvec_ptr = (size ? gen_helper_gvec_fcmlas_idx
-                       : gen_helper_gvec_fcmlah_idx);
-    } else if ((insn & 0xffb00f00) == 0xfe200d00) {
+    if ((insn & 0xffb00f00) == 0xfe200d00) {
         /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
         int u = extract32(insn, 4, 1);
 
-- 
2.20.1

Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-10-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |  3 +++
 target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 13 +-----------
 3 files changed, 39 insertions(+), 12 deletions(-)

Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
to decodetree. These are the last ones in the group so we can remove
all the legacy decode for the group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-11-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |   7 +++
 target/arm/translate-neon.inc.c |  32 ++++++++++
 target/arm/translate.c          | 107 +-------------------------------
 3 files changed, 40 insertions(+), 106 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@ VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
 
 VDOT_scalar    1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
                vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+%vfml_scalar_q0_rm 0:3 5:1
+%vfml_scalar_q1_index 5:1 3:1
+VFML_scalar    1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1 index:1 ... \
+               rm=%vfml_scalar_q0_rm vn=%vn_sp vd=%vd_dp q=0
+VFML_scalar    1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \
+               index=%vfml_scalar_q1_index vn=%vn_dp vd=%vd_dp q=1
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
     tcg_temp_free_ptr(fpst);
     return true;
 }
+
+static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
+{
+    int opr_sz;
+
+    if (!dc_isar_feature(aa32_fhm, s)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) {
+        return false;
+    }
+
+    if (a->vd & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    opr_sz = (1 + a->q) * 8;
+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+                       vfp_reg_offset(a->q, a->vn),
+                       vfp_reg_offset(a->q, a->rm),
+                       cpu_env, opr_sz, opr_sz,
+                       (a->index << 2) | a->s, /* is_2 == 0 */
+                       gen_helper_gvec_fmlal_idx_a32);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
 }
 
 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
-#define VFP_SREG(insn, bigbit, smallbit) \
-  ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
     if (dc_isar_feature(aa32_simd_r32, s)) { \
         reg = (((insn) >> (bigbit)) & 0x0f) \
@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
         reg = ((insn) >> (bigbit)) & 0x0f; \
     }} while (0)
 
-#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
-#define VFP_SREG_N(insn) VFP_SREG(insn, 16,  7)
 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16,  7)
-#define VFP_SREG_M(insn) VFP_SREG(insn,  0,  5)
 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn,  0,  5)
 
 static void gen_neon_dup_low16(TCGv_i32 var)
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     return 0;
 }
 
-/* Advanced SIMD two registers and a scalar extension.
- *  31             24   23  22   20   16   12  11   10   9    8        3     0
- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
- * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
- *
- */
-
-static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
-{
-    gen_helper_gvec_3 *fn_gvec = NULL;
-    gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
-    int rd, rn, rm, opr_sz, data;
-    int off_rn, off_rm;
-    bool is_long = false, q = extract32(insn, 6, 1);
-    bool ptr_is_env = false;
-
-    if ((insn & 0xffa00f10) == 0xfe000810) {
-        /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
-        int is_s = extract32(insn, 20, 1);
-        int vm20 = extract32(insn, 0, 3);
-        int vm3 = extract32(insn, 3, 1);
-        int m = extract32(insn, 5, 1);
-        int index;
-
-        if (!dc_isar_feature(aa32_fhm, s)) {
-            return 1;
-        }
-        if (q) {
-            rm = vm20;
-            index = m * 2 + vm3;
-        } else {
-            rm = vm20 * 2 + m;
-            index = vm3;
-        }
-        is_long = true;
-        data = (index << 2) | is_s; /* is_2 == 0 */
-        fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
-        ptr_is_env = true;
-    } else {
-        return 1;
-    }
-
-    VFP_DREG_D(rd, insn);
-    if (rd & q) {
-        return 1;
-    }
-    if (q || !is_long) {
-        VFP_DREG_N(rn, insn);
-        if (rn & q & !is_long) {
-            return 1;
-        }
-        off_rn = vfp_reg_offset(1, rn);
-        off_rm = vfp_reg_offset(1, rm);
-    } else {
-        rn = VFP_SREG_N(insn);
-        off_rn = vfp_reg_offset(0, rn);
-        off_rm = vfp_reg_offset(0, rm);
-    }
-    if (s->fp_excp_el) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
-        return 0;
-    }
-    if (!s->vfp_enabled) {
-        return 1;
-    }
-
-    opr_sz = (1 + q) * 8;
-    if (fn_gvec_ptr) {
-        TCGv_ptr ptr;
-        if (ptr_is_env) {
-            ptr = cpu_env;
-        } else {
-            ptr = get_fpstatus_ptr(1);
-        }
-        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
-                           opr_sz, opr_sz, data, fn_gvec_ptr);
-        if (!ptr_is_env) {
-            tcg_temp_free_ptr(ptr);
-        }
-    } else {
-        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
-                           opr_sz, opr_sz, data, fn_gvec);
-    }
-    return 0;
-}
-
 static int disas_coproc_insn(DisasContext *s, uint32_t insn)
 {
     int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                     }
                 }
             }
-        } else if ((insn & 0x0f000a00) == 0x0e000800
-                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
-            if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
-                goto illegal_op;
-            }
-            return;
         }
         goto illegal_op;
     }
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
             }
             break;
         }
-        if ((insn & 0xff000a00) == 0xfe000800
-            && arm_dc_feature(s, ARM_FEATURE_V8)) {
-            /* The Thumb2 and ARM encodings are identical.  */
-            if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
-                goto illegal_op;
-            }
-        } else if (((insn >> 24) & 3) == 3) {
+        if (((insn >> 24) & 3) == 3) {
             /* Translate into the equivalent ARM encoding.  */
             insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
             if (disas_neon_data_insn(s, insn)) {
-- 
2.20.1

Convert the Neon "load/store multiple structures" insns to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-12-peter.maydell@linaro.org
---
 target/arm/neon-ls.decode       |   7 ++
 target/arm/translate-neon.inc.c | 124 ++++++++++++++++++++++++++++++++
 target/arm/translate.c          |  91 +----------------------
 3 files changed, 133 insertions(+), 89 deletions(-)

diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-ls.decode
+++ b/target/arm/neon-ls.decode
@@ -XXX,XX +XXX,XX @@
 #   0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
 # This file works on the A32 encoding only; calling code for T32 has to
 # transform the insn into the A32 version first.
+
+%vd_dp  22:1 12:4
+
+# Neon load/store multiple structures
+
+VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
+               vd=%vd_dp
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
                        gen_helper_gvec_fmlal_idx_a32);
     return true;
 }
+
+static struct {
+    int nregs;
+    int interleave;
+    int spacing;
+} const neon_ls_element_type[11] = {
+    {1, 4, 1},
+    {1, 4, 2},
+    {4, 1, 1},
+    {2, 2, 2},
+    {1, 3, 1},
+    {1, 3, 2},
+    {3, 1, 1},
+    {1, 1, 1},
+    {1, 2, 1},
+    {1, 2, 2},
+    {2, 1, 1}
+};
+
+static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn,
+                                      int stride)
+{
+    if (rm != 15) {
+        TCGv_i32 base;
+
+        base = load_reg(s, rn);
+        if (rm == 13) {
+            tcg_gen_addi_i32(base, base, stride);
+        } else {
+            TCGv_i32 index;
+            index = load_reg(s, rm);
+            tcg_gen_add_i32(base, base, index);
+            tcg_temp_free_i32(index);
+        }
+        store_reg(s, rn, base);
+    }
+}
+
+static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
+{
+    /* Neon load/store multiple structures */
+    int nregs, interleave, spacing, reg, n;
+    MemOp endian = s->be_data;
+    int mmu_idx = get_mem_index(s);
+    int size = a->size;
+    TCGv_i64 tmp64;
+    TCGv_i32 addr, tmp;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist */
+    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+        return false;
+    }
+    if (a->itype > 10) {
+        return false;
+    }
+    /* Catch UNDEF cases for bad values of align field */
+    switch (a->itype & 0xc) {
+    case 4:
+        if (a->align >= 2) {
+            return false;
+        }
+        break;
+    case 8:
+        if (a->align == 3) {
+            return false;
+        }
+        break;
+    default:
+        break;
+    }
+    nregs = neon_ls_element_type[a->itype].nregs;
+    interleave = neon_ls_element_type[a->itype].interleave;
+    spacing = neon_ls_element_type[a->itype].spacing;
+    if (size == 3 && (interleave | spacing) != 1) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /* For our purposes, bytes are always little-endian.  */
+    if (size == 0) {
+        endian = MO_LE;
+    }
+    /*
+     * Consecutive little-endian elements from a single register
+     * can be promoted to a larger little-endian operation.
+     */
+    if (interleave == 1 && endian == MO_LE) {
+        size = 3;
+    }
+    tmp64 = tcg_temp_new_i64();
+    addr = tcg_temp_new_i32();
+    tmp = tcg_const_i32(1 << size);
+    load_reg_var(s, addr, a->rn);
+    for (reg = 0; reg < nregs; reg++) {
+        for (n = 0; n < 8 >> size; n++) {
+            int xs;
+            for (xs = 0; xs < interleave; xs++) {
+                int tt = a->vd + reg + spacing * xs;
+
+                if (a->l) {
+                    gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
+                    neon_store_element64(tt, n, size, tmp64);
+                } else {
+                    neon_load_element64(tmp64, tt, n, size);
+                    gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
+                }
+                tcg_gen_add_i32(addr, addr, tmp);
+            }
+        }
+    }
+    tcg_temp_free_i32(addr);
+    tcg_temp_free_i32(tmp);
+    tcg_temp_free_i64(tmp64);
+
+    gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
 }
 
 
-static struct {
-    int nregs;
-    int interleave;
-    int spacing;
-} const neon_ls_element_type[11] = {
-    {1, 4, 1},
-    {1, 4, 2},
-    {4, 1, 1},
-    {2, 2, 2},
-    {1, 3, 1},
-    {1, 3, 2},
-    {3, 1, 1},
-    {1, 1, 1},
-    {1, 2, 1},
-    {1, 2, 2},
-    {2, 1, 1}
-};
-
 /* Translate a NEON load/store element instruction.  Return nonzero if the
    instruction is invalid.  */
 static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
 {
     int rd, rn, rm;
-    int op;
     int nregs;
-    int interleave;
-    int spacing;
     int stride;
     int size;
     int reg;
     int load;
-    int n;
     int vec_size;
-    int mmu_idx;
-    MemOp endian;
     TCGv_i32 addr;
     TCGv_i32 tmp;
-    TCGv_i32 tmp2;
-    TCGv_i64 tmp64;
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
         return 1;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
     rn = (insn >> 16) & 0xf;
     rm = insn & 0xf;
     load = (insn & (1 << 21)) != 0;
-    endian = s->be_data;
-    mmu_idx = get_mem_index(s);
     if ((insn & (1 << 23)) == 0) {
-        /* Load store all elements.  */
-        op = (insn >> 8) & 0xf;
-        size = (insn >> 6) & 3;
-        if (op > 10)
-            return 1;
-        /* Catch UNDEF cases for bad values of align field */
-        switch (op & 0xc) {
-        case 4:
-            if (((insn >> 5) & 1) == 1) {
-                return 1;
-            }
-            break;
-        case 8:
-            if (((insn >> 4) & 3) == 3) {
-                return 1;
-            }
-            break;
-        default:
-            break;
-        }
-        nregs = neon_ls_element_type[op].nregs;
-        interleave = neon_ls_element_type[op].interleave;
-        spacing = neon_ls_element_type[op].spacing;
-        if (size == 3 && (interleave | spacing) != 1) {
-            return 1;
-        }
-        /* For our purposes, bytes are always little-endian.  */
-        if (size == 0) {
-            endian = MO_LE;
-        }
-        /* Consecutive little-endian elements from a single register
-         * can be promoted to a larger little-endian operation.
-         */
-        if (interleave == 1 && endian == MO_LE) {
-            size = 3;
-        }
-        tmp64 = tcg_temp_new_i64();
-        addr = tcg_temp_new_i32();
-        tmp2 = tcg_const_i32(1 << size);
-        load_reg_var(s, addr, rn);
-        for (reg = 0; reg < nregs; reg++) {
-            for (n = 0; n < 8 >> size; n++) {
-                int xs;
-                for (xs = 0; xs < interleave; xs++) {
-                    int tt = rd + reg + spacing * xs;
-
-                    if (load) {
-                        gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
-                        neon_store_element64(tt, n, size, tmp64);
-                    } else {
-                        neon_load_element64(tmp64, tt, n, size);
-                        gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
-                    }
-                    tcg_gen_add_i32(addr, addr, tmp2);
-                }
-            }
-        }
-        tcg_temp_free_i32(addr);
-        tcg_temp_free_i32(tmp2);
-        tcg_temp_free_i64(tmp64);
-        stride = nregs * interleave * 8;
+        /* Load store all elements -- handled already by decodetree */
+        return 1;
     } else {
         size = (insn >> 10) & 3;
         if (size == 3) {
-- 
2.20.1

Convert the Neon "load single structure to all lanes" insns to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-13-peter.maydell@linaro.org
---
 target/arm/neon-ls.decode       |  5 +++
 target/arm/translate-neon.inc.c | 73 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 55 +------------------------
 3 files changed, 80 insertions(+), 53 deletions(-)

Convert the Neon "load/store single structure to one lane" insns to
decodetree.

As this is the last set of insns in the neon load/store group,
we can remove the whole disas_neon_ls_insn() function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-14-peter.maydell@linaro.org
---
 target/arm/neon-ls.decode       |  11 +++
 target/arm/translate-neon.inc.c |  89 +++++++++++++++++++
 target/arm/translate.c          | 147 --------------------------------
 3 files changed, 100 insertions(+), 147 deletions(-)

diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-ls.decode
+++ b/target/arm/neon-ls.decode
@@ -XXX,XX +XXX,XX @@ VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
 
 VLD_all_lanes  1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
                vd=%vd_dp
+
+# Neon load/store single structure to one lane
+%imm1_5_p1 5:1 !function=plus1
+%imm1_6_p1 6:1 !function=plus1
+
+VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
+               vd=%vd_dp size=0 stride=1
+VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \
+               vd=%vd_dp size=1 stride=%imm1_5_p1
+VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \
+               vd=%vd_dp size=2 stride=%imm1_6_p1
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@
  * It might be possible to convert it to a standalone .c file eventually.
  */
 
+static inline int plus1(DisasContext *s, int x)
+{
+    return x + 1;
+}
+
 /* Include the generated Neon decoder */
 #include "decode-neon-dp.inc.c"
 #include "decode-neon-ls.inc.c"
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
 
     return true;
 }
+
+static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
+{
+    /* Neon load/store single structure to one lane */
+    int reg;
+    int nregs = a->n + 1;
+    int vd = a->vd;
+    TCGv_i32 addr, tmp;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist */
+    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+        return false;
+    }
+
+    /* Catch the UNDEF cases. This is unavoidably a bit messy. */
+    switch (nregs) {
+    case 1:
+        if (((a->align & (1 << a->size)) != 0) ||
+            (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
+            return false;
+        }
+        break;
+    case 3:
+        if ((a->align & 1) != 0) {
+            return false;
+        }
+        /* fall through */
+    case 2:
+        if (a->size == 2 && (a->align & 2) != 0) {
+            return false;
+        }
+        break;
+    case 4:
+        if ((a->size == 2) && ((a->align & 3) == 3)) {
+            return false;
+        }
+        break;
+    default:
+        abort();
+    }
+    if ((vd + a->stride * (nregs - 1)) > 31) {
+        /*
+         * Attempts to write off the end of the register file are
+         * UNPREDICTABLE; we choose to UNDEF because otherwise we would
+         * access off the end of the array that holds the register data.
+         */
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    tmp = tcg_temp_new_i32();
+    addr = tcg_temp_new_i32();
+    load_reg_var(s, addr, a->rn);
+    /*
+     * TODO: if we implemented alignment exceptions, we should check
+     * addr against the alignment encoded in a->align here.
+     */
+    for (reg = 0; reg < nregs; reg++) {
+        if (a->l) {
+            gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
+                            s->be_data | a->size);
+            neon_store_element(vd, a->reg_idx, a->size, tmp);
+        } else { /* Store */
+            neon_load_element(tmp, vd, a->reg_idx, a->size);
+            gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
+                            s->be_data | a->size);
+        }
+        vd += a->stride;
+        tcg_gen_addi_i32(addr, addr, 1 << a->size);
+    }
+    tcg_temp_free_i32(addr);
+    tcg_temp_free_i32(tmp);
+
+    gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs);
+
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
     tcg_temp_free_i32(rd);
 }
 
-
-/* Translate a NEON load/store element instruction.  Return nonzero if the
-   instruction is invalid.  */
-static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
-{
-    int rd, rn, rm;
-    int nregs;
-    int stride;
-    int size;
-    int reg;
-    int load;
-    TCGv_i32 addr;
-    TCGv_i32 tmp;
-
-    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-        return 1;
-    }
-
-    /* FIXME: this access check should not take precedence over UNDEF
-     * for invalid encodings; we will generate incorrect syndrome information
-     * for attempts to execute invalid vfp/neon encodings with FP disabled.
-     */
-    if (s->fp_excp_el) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
-        return 0;
-    }
-
-    if (!s->vfp_enabled)
-      return 1;
-    VFP_DREG_D(rd, insn);
-    rn = (insn >> 16) & 0xf;
-    rm = insn & 0xf;
-    load = (insn & (1 << 21)) != 0;
-    if ((insn & (1 << 23)) == 0) {
-        /* Load store all elements -- handled already by decodetree */
-        return 1;
-    } else {
-        size = (insn >> 10) & 3;
-        if (size == 3) {
-            /* Load single element to all lanes -- handled by decodetree  */
-            return 1;
-        } else {
-            /* Single element.  */
-            int idx = (insn >> 4) & 0xf;
-            int reg_idx;
-            switch (size) {
-            case 0:
-                reg_idx = (insn >> 5) & 7;
-                stride = 1;
-                break;
-            case 1:
-                reg_idx = (insn >> 6) & 3;
-                stride = (insn & (1 << 5)) ? 2 : 1;
-                break;
-            case 2:
-                reg_idx = (insn >> 7) & 1;
-                stride = (insn & (1 << 6)) ? 2 : 1;
-                break;
-            default:
-                abort();
-            }
-            nregs = ((insn >> 8) & 3) + 1;
-            /* Catch the UNDEF cases. This is unavoidably a bit messy. */
-            switch (nregs) {
-            case 1:
-                if (((idx & (1 << size)) != 0) ||
-                    (size == 2 && ((idx & 3) == 1 || (idx & 3) == 2))) {
-                    return 1;
-                }
-                break;
-            case 3:
-                if ((idx & 1) != 0) {
-                    return 1;
-                }
-                /* fall through */
-            case 2:
-                if (size == 2 && (idx & 2) != 0) {
-                    return 1;
-                }
-                break;
-            case 4:
-                if ((size == 2) && ((idx & 3) == 3)) {
-                    return 1;
-                }
-                break;
-            default:
-                abort();
-            }
-            if ((rd + stride * (nregs - 1)) > 31) {
-                /* Attempts to write off the end of the register file
-                 * are UNPREDICTABLE; we choose to UNDEF because otherwise
-                 * the neon_load_reg() would write off the end of the array.
-                 */
-                return 1;
-            }
-            tmp = tcg_temp_new_i32();
-            addr = tcg_temp_new_i32();
-            load_reg_var(s, addr, rn);
-            for (reg = 0; reg < nregs; reg++) {
-                if (load) {
-                    gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
-                                    s->be_data | size);
-                    neon_store_element(rd, reg_idx, size, tmp);
-                } else { /* Store */
-                    neon_load_element(tmp, rd, reg_idx, size);
-                    gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
-                                    s->be_data | size);
-                }
-                rd += stride;
-                tcg_gen_addi_i32(addr, addr, 1 << size);
-            }
-            tcg_temp_free_i32(addr);
-            tcg_temp_free_i32(tmp);
-            stride = nregs * (1 << size);
-        }
-    }
-    if (rm != 15) {
-        TCGv_i32 base;
-
-        base = load_reg(s, rn);
-        if (rm == 13) {
-            tcg_gen_addi_i32(base, base, stride);
-        } else {
-            TCGv_i32 index;
-            index = load_reg(s, rm);
-            tcg_gen_add_i32(base, base, index);
-            tcg_temp_free_i32(index);
-        }
-        store_reg(s, rn, base);
-    }
-    return 0;
-}
-
 static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
 {
     switch (size) {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
             }
             return;
         }
-        if ((insn & 0x0f100000) == 0x04000000) {
-            /* NEON load/store.  */
-            if (disas_neon_ls_insn(s, insn)) {
-                goto illegal_op;
-            }
-            return;
-        }
         if ((insn & 0x0e000f00) == 0x0c000100) {
             if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
                 /* iWMMXt register transfer.  */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
         }
         break;
     case 12:
-        if ((insn & 0x01100000) == 0x01000000) {
-            if (disas_neon_ls_insn(s, insn)) {
-                goto illegal_op;
-            }
-            break;
-        }
         goto illegal_op;
     default:
     illegal_op:
-- 
2.20.1

Convert the Neon 3-reg-same VADD and VSUB insns to decodetree.

Note that we don't need the neon_3r_sizes[op] check here because all
size values are OK for VADD and VSUB; we'll add this when we convert
the first insn that has size restrictions.

For this we need one of the GVecGen*Fn typedefs currently in
translate-a64.h; move them all to translate.h as a block so they
are visible to the 32-bit decoder.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-15-peter.maydell@linaro.org
---
 target/arm/translate-a64.h      |  9 --------
 target/arm/translate.h          |  9 ++++++++
 target/arm/neon-dp.decode       | 17 +++++++++++++++
 target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 14 ++++--------
 5 files changed, 68 insertions(+), 19 deletions(-)

diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)
 
 bool disas_sve(DisasContext *, uint32_t);
 
-/* Note that the gvec expanders operate on offsets + sizes.  */
-typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
-typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
-                         uint32_t, uint32_t);
-typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
-                        uint32_t, uint32_t, uint32_t);
-typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
-                        uint32_t, uint32_t, uint32_t);
-
 #endif /* TARGET_ARM_TRANSLATE_A64_H */
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 #define dc_isar_feature(name, ctx) \
     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
 
+/* Note that the gvec expanders operate on offsets + sizes.  */
+typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
+typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
+                         uint32_t, uint32_t);
+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+                        uint32_t, uint32_t, uint32_t);
+typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
+                        uint32_t, uint32_t, uint32_t);
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@
 #
 # This file is processed by scripts/decodetree.py
 #
+# VFP/Neon register fields; same as vfp.decode
+%vm_dp  5:1 0:4
+%vn_dp  7:1 16:4
+%vd_dp  22:1 12:4
 
 # Encodings for Neon data processing instructions where the T32 encoding
 # is a simple transformation of the A32 encoding.
@@ -XXX,XX +XXX,XX @@
 #   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
 # This file works on the A32 encoding only; calling code for T32 has to
 # transform the insn into the A32 version first.
+
+######################################################################
+# 3-reg-same grouping:
+# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
+######################################################################
+
+&3same vm vn vd q size
+
+@3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
+VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
 
     return true;
 }
+
+static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
+{
+    int vec_size = a->q ? 16 : 8;
+    int rd_ofs = neon_reg_offset(a->vd, 0);
+    int rn_ofs = neon_reg_offset(a->vn, 0);
+    int rm_ofs = neon_reg_offset(a->vm, 0);
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vn | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vn | a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
+    return true;
+}
+
+#define DO_3SAME(INSN, FUNC)                                            \
+    static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a)        \
+    {                                                                   \
+        return do_3same(s, a, FUNC);                                    \
+    }
+
+DO_3SAME(VADD, tcg_gen_gvec_add)
+DO_3SAME(VSUB, tcg_gen_gvec_sub)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             }
             return 0;
 
-        case NEON_3R_VADD_VSUB:
-            if (u) {
-                tcg_gen_gvec_sub(size, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-            } else {
-                tcg_gen_gvec_add(size, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-            }
-            return 0;
-
         case NEON_3R_VQADD:
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
                            u ? &ushl_op[size] : &sshl_op[size]);
             return 0;
+
+        case NEON_3R_VADD_VSUB:
+            /* Already handled by decodetree */
+            return 1;
         }
 
         if (size == 3) {
-- 
2.20.1

Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
Note that for the logic ops the 'size' field forms part of their
decode and the actual operations are always bitwise.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-16-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 12 +++++++++++
 target/arm/translate-neon.inc.c | 19 +++++++++++++++++
 target/arm/translate.c          | 38 +--------------------------------
 3 files changed, 32 insertions(+), 37 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@
 @3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
 
+@3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
+
+VAND_3s          1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
+VBIC_3s          1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
+VORR_3s          1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
+VORN_3s          1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
+VEOR_3s          1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
+VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
+VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
+VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
+
 VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
 VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
 
 DO_3SAME(VADD, tcg_gen_gvec_add)
 DO_3SAME(VSUB, tcg_gen_gvec_sub)
+DO_3SAME(VAND, tcg_gen_gvec_and)
+DO_3SAME(VBIC, tcg_gen_gvec_andc)
+DO_3SAME(VORR, tcg_gen_gvec_or)
+DO_3SAME(VORN, tcg_gen_gvec_orc)
+DO_3SAME(VEOR, tcg_gen_gvec_xor)
+
+/* These insns are all gvec_bitsel but with the inputs in various orders. */
+#define DO_3SAME_BITSEL(INSN, O1, O2, O3)                               \
+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+                                uint32_t oprsz, uint32_t maxsz)         \
+    {                                                                   \
+        tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz);    \
+    }                                                                   \
+    DO_3SAME(INSN, gen_##INSN##_3s)
+
+DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
+DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
+DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             }
             return 1;
 
-        case NEON_3R_LOGIC: /* Logic ops.  */
-            switch ((u << 2) | size) {
-            case 0: /* VAND */
-                tcg_gen_gvec_and(0, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-                break;
-            case 1: /* VBIC */
-                tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
-                                  vec_size, vec_size);
-                break;
-            case 2: /* VORR */
-                tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
-                                vec_size, vec_size);
-                break;
-            case 3: /* VORN */
-                tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-                break;
-            case 4: /* VEOR */
-                tcg_gen_gvec_xor(0, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-                break;
-            case 5: /* VBSL */
-                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rd_ofs, rn_ofs, rm_ofs,
-                                    vec_size, vec_size);
-                break;
-            case 6: /* VBIT */
-                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rn_ofs, rd_ofs,
-                                    vec_size, vec_size);
-                break;
-            case 7: /* VBIF */
-                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rd_ofs, rn_ofs,
-                                    vec_size, vec_size);
-                break;
-            }
-            return 0;
-
         case NEON_3R_VQADD:
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             return 0;
 
         case NEON_3R_VADD_VSUB:
+        case NEON_3R_LOGIC:
             /* Already handled by decodetree */
             return 1;
         }
-- 
2.20.1

Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-17-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  5 +++++
 target/arm/translate-neon.inc.c | 14 ++++++++++++++
 target/arm/translate.c          | 21 ++-------------------
 3 files changed, 21 insertions(+), 19 deletions(-)

Convert the Neon comparison ops in the 3-reg-same grouping
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-18-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  8 ++++++++
 target/arm/translate-neon.inc.c | 22 ++++++++++++++++++++++
 target/arm/translate.c          | 23 +++--------------------
 3 files changed, 33 insertions(+), 20 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
 VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
 VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
 
+VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
+VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
+VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
+VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
+
 VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
 VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
 VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
@@ -XXX,XX +XXX,XX @@ VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
 
 VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
 VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
+
+VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
+VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
 DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
 DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
 DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
+
+#define DO_3SAME_CMP(INSN, COND)                                        \
+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+                                uint32_t oprsz, uint32_t maxsz)         \
+    {                                                                   \
+        tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \
+    }                                                                   \
+    DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
+
+DO_3SAME_CMP(VCGT_S, TCG_COND_GT)
+DO_3SAME_CMP(VCGT_U, TCG_COND_GTU)
+DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
+DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
+DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
+
+static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+                         uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+    tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);
+}
+DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                            u ? &mls_op[size] : &mla_op[size]);
             return 0;
 
-        case NEON_3R_VTST_VCEQ:
-            if (u) { /* VCEQ */
-                tcg_gen_gvec_cmp(TCG_COND_EQ, size, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-            } else { /* VTST */
-                tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
-                               vec_size, vec_size, &cmtst_op[size]);
-            }
-            return 0;
-
-        case NEON_3R_VCGT:
-            tcg_gen_gvec_cmp(u ? TCG_COND_GTU : TCG_COND_GT, size,
-                             rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
-            return 0;
-
-        case NEON_3R_VCGE:
-            tcg_gen_gvec_cmp(u ? TCG_COND_GEU : TCG_COND_GE, size,
-                             rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
-            return 0;
-
         case NEON_3R_VSHL:
             /* Note the operation is vshl vd,vm,vn */
             tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         case NEON_3R_LOGIC:
         case NEON_3R_VMAX:
         case NEON_3R_VMIN:
+        case NEON_3R_VTST_VCEQ:
+        case NEON_3R_VCGT:
+        case NEON_3R_VCGE:
             /* Already handled by decodetree */
             return 1;
         }
-- 
2.20.1

Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-19-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  6 ++++++
 target/arm/translate-neon.inc.c | 15 +++++++++++++++
 target/arm/translate.c          | 14 ++------------
 3 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@
 @3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
 
+VQADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
+VQADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
+
 @3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
 
@@ -XXX,XX +XXX,XX @@ VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
 VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
 VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
 
+VQSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
+VQSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
+
 VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
 VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
 VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
     tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);
 }
 DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)
+
+#define DO_3SAME_GVEC4(INSN, OPARRAY)                                   \
+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+                                uint32_t oprsz, uint32_t maxsz)         \
+    {                                                                   \
+        tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),           \
+                       rn_ofs, rm_ofs, oprsz, maxsz, &OPARRAY[vece]);   \
+    }                                                                   \
+    DO_3SAME(INSN, gen_##INSN##_3s)
+
+DO_3SAME_GVEC4(VQADD_S, sqadd_op)
+DO_3SAME_GVEC4(VQADD_U, uqadd_op)
+DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
+DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             }
             return 1;
 
-        case NEON_3R_VQADD:
-            tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-                           rn_ofs, rm_ofs, vec_size, vec_size,
-                           (u ? uqadd_op : sqadd_op) + size);
-            return 0;
-
-        case NEON_3R_VQSUB:
-            tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-                           rn_ofs, rm_ofs, vec_size, vec_size,
-                           (u ? uqsub_op : sqsub_op) + size);
-            return 0;
-
         case NEON_3R_VMUL: /* VMUL */
             if (u) {
                 /* Polynomial case allows only P8.  */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         case NEON_3R_VTST_VCEQ:
         case NEON_3R_VCGT:
         case NEON_3R_VCGE:
+        case NEON_3R_VQADD:
+        case NEON_3R_VQSUB:
             /* Already handled by decodetree */
             return 1;
         }
-- 
2.20.1

Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
3-reg-same grouping to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-20-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  9 +++++++
 target/arm/translate-neon.inc.c | 44 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 28 +++------------------
 3 files changed, 56 insertions(+), 25 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
 VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
 VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
 
+VSHL_S_3s        1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same
+VSHL_U_3s        1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same
+
 VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
 VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
 VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
@@ -XXX,XX +XXX,XX @@ VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
 
 VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
 VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
+
+VMLA_3s          1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
+VMLS_3s          1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
+
+VMUL_3s          1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
+VMUL_p_3s        1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
 DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
 DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
 DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
+DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul)
 
 #define DO_3SAME_CMP(INSN, COND)                                        \
     static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
@@ -XXX,XX +XXX,XX @@ DO_3SAME_GVEC4(VQADD_S, sqadd_op)
 DO_3SAME_GVEC4(VQADD_U, uqadd_op)
 DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
 DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
+
+static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+                           uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+    tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
+                       0, gen_helper_gvec_pmul_b);
+}
+
+static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
+{
+    if (a->size != 0) {
+        return false;
+    }
+    return do_3same(s, a, gen_VMUL_p_3s);
+}
+
+#define DO_3SAME_GVEC3_NO_SZ_3(INSN, OPARRAY)                           \
+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+                                uint32_t oprsz, uint32_t maxsz)         \
+    {                                                                   \
+        tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,                          \
+                       oprsz, maxsz, &OPARRAY[vece]);                   \
+    }                                                                   \
+    DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
+
+
+DO_3SAME_GVEC3_NO_SZ_3(VMLA, mla_op)
+DO_3SAME_GVEC3_NO_SZ_3(VMLS, mls_op)
+
+#define DO_3SAME_GVEC3_SHIFT(INSN, OPARRAY)                             \
+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+                                uint32_t oprsz, uint32_t maxsz)         \
+    {                                                                   \
+        /* Note the operation is vshl vd,vm,vn */                       \
+        tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs,                          \
+                       oprsz, maxsz, &OPARRAY[vece]);                   \
+    }                                                                   \
+    DO_3SAME(INSN, gen_##INSN##_3s)
+
+DO_3SAME_GVEC3_SHIFT(VSHL_S, sshl_op)
+DO_3SAME_GVEC3_SHIFT(VSHL_U, ushl_op)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             }
             return 1;
 
-        case NEON_3R_VMUL: /* VMUL */
-            if (u) {
-                /* Polynomial case allows only P8.  */
-                if (size != 0) {
-                    return 1;
-                }
-                tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
-                                   0, gen_helper_gvec_pmul_b);
-            } else {
-                tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-            }
-            return 0;
-
-        case NEON_3R_VML: /* VMLA, VMLS */
-            tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
-                           u ? &mls_op[size] : &mla_op[size]);
-            return 0;
-
-        case NEON_3R_VSHL:
-            /* Note the operation is vshl vd,vm,vn */
-            tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
-                           u ? &ushl_op[size] : &sshl_op[size]);
-            return 0;
-
         case NEON_3R_VADD_VSUB:
         case NEON_3R_LOGIC:
         case NEON_3R_VMAX:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         case NEON_3R_VCGE:
         case NEON_3R_VQADD:
         case NEON_3R_VQSUB:
+        case NEON_3R_VMUL:
+        case NEON_3R_VML:
+        case NEON_3R_VSHL:
             /* Already handled by decodetree */
             return 1;
         }
-- 
2.20.1

We're going to want at least some of the NeonGen* typedefs
for the refactored 32-bit Neon decoder, so move them all
to translate.h since it makes more sense to keep them in
one group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-23-peter.maydell@linaro.org
---
 target/arm/translate.h     | 17 +++++++++++++++++
 target/arm/translate-a64.c | 17 -----------------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
                         uint32_t, uint32_t, uint32_t);
 
+/* Function prototype for gen_ functions for calling Neon helpers */
+typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
+typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
+typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
+typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
+typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
+typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
+typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
+typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
+typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
+typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
+typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
+typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
+typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
+typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ typedef struct AArch64DecodeTable {
     AArch64DecodeFn *disas_fn;
 } AArch64DecodeTable;
 
-/* Function prototype for gen_ functions for calling Neon helpers */
-typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
-typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
-typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
-typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
-typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
-typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
-typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
-typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
-typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
-typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
-typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
-typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
-typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
-typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
-typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
-
 /* initialize TCG globals.  */
 void a64_translate_init(void)
 {
-- 
2.20.1

Arm changes for before softfreeze: mostly my PL061/GPIO patches,
but also a new M-profile board and various other things.

thanks
-- PMM

The following changes since commit 05de778b5b8ab0b402996769117b88c7ea5c7c61:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2021-07-09 14:30:01 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210709

for you to fetch changes up to 05449abb1d4c5f0c69ceb3d8d03cbc75de39b646:

hw/intc: Improve formatting of MEMTX_ERROR guest error message (2021-07-09 16:09:12 +0100)

----------------------------------------------------------------
target-arm queue:
 * New machine type: stm32vldiscovery
 * hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write
 * hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
 * virt: Fix implementation of GPIO-based powerdown/shutdown mechanism
 * Correct the encoding of MDCCSR_EL0 and DBGDSCRint
 * hw/intc: Improve formatting of MEMTX_ERROR guest error message

----------------------------------------------------------------
Alexandre Iooss (4):
      stm32f100: Add the stm32f100 SoC
      stm32vldiscovery: Add the STM32VLDISCOVERY Machine
      docs/system: arm: Add stm32 boards description
      tests/boot-serial-test: Add STM32VLDISCOVERY board testcase

Peter Maydell (10):
      hw/gpio/pl061: Convert DPRINTF to tracepoints
      hw/gpio/pl061: Clean up read/write offset handling logic
      hw/gpio/pl061: Add tracepoints for register read and write
      hw/gpio/pl061: Document the interface of this device
      hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers
      hw/gpio/pl061: Make pullup/pulldown of outputs configurable
      hw/arm/virt: Make PL061 GPIO lines pulled low, not high
      hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset
      hw/gpio/pl061: Document a shortcoming in our implementation
      hw/arm/stellaris: Expand comment about handling of OLED chipselect

Rebecca Cran (1):
      hw/intc: Improve formatting of MEMTX_ERROR guest error message

Ricardo Koller (1):
      hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write

hnick@vmware.com (1):
      target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint

docs/system/arm/stm32.rst               |  66 +++++++
 docs/system/target-arm.rst              |   1 +
 default-configs/devices/arm-softmmu.mak |   1 +
 include/hw/arm/stm32f100_soc.h          |  57 ++++++
 hw/arm/stellaris.c                      |  56 +++++-
 hw/arm/stm32f100_soc.c                  | 182 +++++++++++++++++
 hw/arm/stm32vldiscovery.c               |  66 +++++++
 hw/arm/virt.c                           |   3 +
 hw/gpio/pl061.c                         | 341 +++++++++++++++++++++++++-------
 hw/intc/arm_gicv3_cpuif.c               |   4 +-
 hw/intc/arm_gicv3_redist.c              |   4 +-
 target/arm/helper.c                     |  16 +-
 tests/qtest/boot-serial-test.c          |  37 ++++
 MAINTAINERS                             |  13 ++
 hw/arm/Kconfig                          |  10 +
 hw/arm/meson.build                      |   2 +
 hw/gpio/trace-events                    |   9 +
 17 files changed, 790 insertions(+), 78 deletions(-)
 create mode 100644 docs/system/arm/stm32.rst
 create mode 100644 include/hw/arm/stm32f100_soc.h
 create mode 100644 hw/arm/stm32f100_soc.c
 create mode 100644 hw/arm/stm32vldiscovery.c

From: Alexandre Iooss <erdnaxe@crans.org>

This SoC is similar to stm32f205 SoC.
This will be used by the STM32VLDISCOVERY to create a machine.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-2-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/stm32f100_soc.h |  57 +++++++++++
 hw/arm/stm32f100_soc.c         | 182 +++++++++++++++++++++++++++++++++
 MAINTAINERS                    |   6 ++
 hw/arm/Kconfig                 |   6 ++
 hw/arm/meson.build             |   1 +
 5 files changed, 252 insertions(+)
 create mode 100644 include/hw/arm/stm32f100_soc.h
 create mode 100644 hw/arm/stm32f100_soc.c

diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/arm/stm32f100_soc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F100 SoC
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_STM32F100_SOC_H
+#define HW_ARM_STM32F100_SOC_H
+
+#include "hw/char/stm32f2xx_usart.h"
+#include "hw/ssi/stm32f2xx_spi.h"
+#include "hw/arm/armv7m.h"
+#include "qom/object.h"
+
+#define TYPE_STM32F100_SOC "stm32f100-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC)
+
+#define STM_NUM_USARTS 3
+#define STM_NUM_SPIS 2
+
+#define FLASH_BASE_ADDRESS 0x08000000
+#define FLASH_SIZE (128 * 1024)
+#define SRAM_BASE_ADDRESS 0x20000000
+#define SRAM_SIZE (8 * 1024)
+
+struct STM32F100State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    char *cpu_type;
+
+    ARMv7MState armv7m;
+
+    STM32F2XXUsartState usart[STM_NUM_USARTS];
+    STM32F2XXSPIState spi[STM_NUM_SPIS];
+};
+
+#endif
diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/stm32f100_soc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * STM32F100 SoC
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/module.h"
+#include "hw/arm/boot.h"
+#include "exec/address-spaces.h"
+#include "hw/arm/stm32f100_soc.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+
+/* stm32f100_soc implementation is derived from stm32f205_soc */
+
+static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40013800, 0x40004400,
+    0x40004800 };
+static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800 };
+
+static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39};
+static const int spi_irq[STM_NUM_SPIS] = {35, 36};
+
+static void stm32f100_soc_initfn(Object *obj)
+{
+    STM32F100State *s = STM32F100_SOC(obj);
+    int i;
+
+    object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+
+    for (i = 0; i < STM_NUM_USARTS; i++) {
+        object_initialize_child(obj, "usart[*]", &s->usart[i],
+                                TYPE_STM32F2XX_USART);
+    }
+
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
+    }
+}
+
+static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+    STM32F100State *s = STM32F100_SOC(dev_soc);
+    DeviceState *dev, *armv7m;
+    SysBusDevice *busdev;
+    int i;
+
+    MemoryRegion *system_memory = get_system_memory();
+    MemoryRegion *sram = g_new(MemoryRegion, 1);
+    MemoryRegion *flash = g_new(MemoryRegion, 1);
+    MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
+
+    /*
+     * Init flash region
+     * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0
+     */
+    memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash",
+                           FLASH_SIZE, &error_fatal);
+    memory_region_init_alias(flash_alias, OBJECT(dev_soc),
+                             "STM32F100.flash.alias", flash, 0, FLASH_SIZE);
+    memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
+    memory_region_add_subregion(system_memory, 0, flash_alias);
+
+    /* Init SRAM region */
+    memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE,
+                           &error_fatal);
+    memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+
+    /* Init ARMv7m */
+    armv7m = DEVICE(&s->armv7m);
+    qdev_prop_set_uint32(armv7m, "num-irq", 61);
+    qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
+    qdev_prop_set_bit(armv7m, "enable-bitband", true);
+    object_property_set_link(OBJECT(&s->armv7m), "memory",
+                             OBJECT(get_system_memory()), &error_abort);
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
+        return;
+    }
+
+    /* Attach UART (uses USART registers) and USART controllers */
+    for (i = 0; i < STM_NUM_USARTS; i++) {
+        dev = DEVICE(&(s->usart[i]));
+        qdev_prop_set_chr(dev, "chardev", serial_hd(i));
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, usart_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
+    }
+
+    /* SPI 1 and 2 */
+    for (i = 0; i < STM_NUM_SPIS; i++) {
+        dev = DEVICE(&(s->spi[i]));
+        if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, spi_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
+    }
+
+    create_unimplemented_device("timer[2]",  0x40000000, 0x400);
+    create_unimplemented_device("timer[3]",  0x40000400, 0x400);
+    create_unimplemented_device("timer[4]",  0x40000800, 0x400);
+    create_unimplemented_device("timer[6]",  0x40001000, 0x400);
+    create_unimplemented_device("timer[7]",  0x40001400, 0x400);
+    create_unimplemented_device("RTC",       0x40002800, 0x400);
+    create_unimplemented_device("WWDG",      0x40002C00, 0x400);
+    create_unimplemented_device("IWDG",      0x40003000, 0x400);
+    create_unimplemented_device("I2C1",      0x40005400, 0x400);
+    create_unimplemented_device("I2C2",      0x40005800, 0x400);
+    create_unimplemented_device("BKP",       0x40006C00, 0x400);
+    create_unimplemented_device("PWR",       0x40007000, 0x400);
+    create_unimplemented_device("DAC",       0x40007400, 0x400);
+    create_unimplemented_device("CEC",       0x40007800, 0x400);
+    create_unimplemented_device("AFIO",      0x40010000, 0x400);
+    create_unimplemented_device("EXTI",      0x40010400, 0x400);
+    create_unimplemented_device("GPIOA",     0x40010800, 0x400);
+    create_unimplemented_device("GPIOB",     0x40010C00, 0x400);
+    create_unimplemented_device("GPIOC",     0x40011000, 0x400);
+    create_unimplemented_device("GPIOD",     0x40011400, 0x400);
+    create_unimplemented_device("GPIOE",     0x40011800, 0x400);
+    create_unimplemented_device("ADC1",      0x40012400, 0x400);
+    create_unimplemented_device("timer[1]",  0x40012C00, 0x400);
+    create_unimplemented_device("timer[15]", 0x40014000, 0x400);
+    create_unimplemented_device("timer[16]", 0x40014400, 0x400);
+    create_unimplemented_device("timer[17]", 0x40014800, 0x400);
+    create_unimplemented_device("DMA",       0x40020000, 0x400);
+    create_unimplemented_device("RCC",       0x40021000, 0x400);
+    create_unimplemented_device("Flash Int", 0x40022000, 0x400);
+    create_unimplemented_device("CRC",       0x40023000, 0x400);
+}
+
+static Property stm32f100_soc_properties[] = {
+    DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void stm32f100_soc_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = stm32f100_soc_realize;
+    device_class_set_props(dc, stm32f100_soc_properties);
+}
+
+static const TypeInfo stm32f100_soc_info = {
+    .name          = TYPE_STM32F100_SOC,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F100State),
+    .instance_init = stm32f100_soc_initfn,
+    .class_init    = stm32f100_soc_class_init,
+};
+
+static void stm32f100_soc_types(void)
+{
+    type_register_static(&stm32f100_soc_info);
+}
+
+type_init(stm32f100_soc_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/virt-acpi-build.c
 
+STM32F100
+M: Alexandre Iooss <erdnaxe@crans.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/stm32f100_soc.c
+
 STM32F205
 M: Alistair Francis <alistair@alistair23.me>
 M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config RASPI
     select SDHCI
     select USB_DWC2
 
+config STM32F100_SOC
+    bool
+    select ARM_V7M
+    select STM32F2XX_USART
+    select STM32F2XX_SPI
+
 config STM32F205_SOC
     bool
     select ARM_V7M
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
 arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
 arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', 'bcm2836.c', 'raspi.c'))
+arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c'))
 arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c'))
 arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c'))
 arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c', 'xlnx-zcu102.c'))
-- 
2.20.1

From: Alexandre Iooss <erdnaxe@crans.org>

This is a Cortex-M3 based machine. Information can be found at:
https://www.st.com/en/evaluation-tools/stm32vldiscovery.html

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-3-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 default-configs/devices/arm-softmmu.mak |  1 +
 hw/arm/stm32vldiscovery.c               | 66 +++++++++++++++++++++++++
 MAINTAINERS                             |  6 +++
 hw/arm/Kconfig                          |  4 ++
 hw/arm/meson.build                      |  1 +
 5 files changed, 78 insertions(+)
 create mode 100644 hw/arm/stm32vldiscovery.c

diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devices/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/devices/arm-softmmu.mak
+++ b/default-configs/devices/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_CHEETAH=y
 CONFIG_SX1=y
 CONFIG_NSERIES=y
 CONFIG_STELLARIS=y
+CONFIG_STM32VLDISCOVERY=y
 CONFIG_REALVIEW=y
 CONFIG_VERSATILE=y
 CONFIG_VEXPRESS=y
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/arm/stm32vldiscovery.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ST STM32VLDISCOVERY machine
+ *
+ * Copyright (c) 2021 Alexandre Iooss <erdnaxe@crans.org>
+ * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "qemu/error-report.h"
+#include "hw/arm/stm32f100_soc.h"
+#include "hw/arm/boot.h"
+
+/* stm32vldiscovery implementation is derived from netduinoplus2 */
+
+/* Main SYSCLK frequency in Hz (24MHz) */
+#define SYSCLK_FRQ 24000000ULL
+
+static void stm32vldiscovery_init(MachineState *machine)
+{
+    DeviceState *dev;
+
+    /*
+     * TODO: ideally we would model the SoC RCC and let it handle
+     * system_clock_scale, including its ability to define different
+     * possible SYSCLK sources.
+     */
+    system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ;
+
+    dev = qdev_new(TYPE_STM32F100_SOC);
+    qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3"));
+    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+    armv7m_load_kernel(ARM_CPU(first_cpu),
+                       machine->kernel_filename,
+                       FLASH_SIZE);
+}
+
+static void stm32vldiscovery_machine_init(MachineClass *mc)
+{
+    mc->desc = "ST STM32VLDISCOVERY (Cortex-M3)";
+    mc->init = stm32vldiscovery_init;
+}
+
+DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
+
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/*/stellaris*
 F: include/hw/input/gamepad.h
 F: docs/system/arm/stellaris.rst
 
+STM32VLDISCOVERY
+M: Alexandre Iooss <erdnaxe@crans.org>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/arm/stm32vldiscovery.c
+
 Versatile Express
 M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config STELLARIS
     select STELLARIS_ENET # ethernet
     select UNIMP
 
+config STM32VLDISCOVERY
+    bool
+    select STM32F100_SOC
+
 config STRONGARM
     bool
     select PXA2XX
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
 arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
 arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
 arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
+arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
 arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
 arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
 arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
-- 
2.20.1

From: Alexandre Iooss <erdnaxe@crans.org>

This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCOVERY.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-4-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/stm32.rst  | 66 ++++++++++++++++++++++++++++++++++++++
 docs/system/target-arm.rst |  1 +
 MAINTAINERS                |  1 +
 3 files changed, 68 insertions(+)
 create mode 100644 docs/system/arm/stm32.rst

diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/docs/system/arm/stm32.rst
@@ -XXX,XX +XXX,XX @@
+STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32vldiscovery``)
+========================================================================================
+
+The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
+STMicroelectronics.
+
+.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
+
+The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
+based on this chip :
+
+- ``stm32vldiscovery``  STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
+
+The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
+based on this chip :
+
+- ``netduino2``         Netduino 2 board with STM32F205RFT6 microcontroller
+
+The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-pin
+compatible with STM32F2 series. The following machines are based on this chip :
+
+- ``netduinoplus2``     Netduino Plus 2 board with STM32F405RGT6 microcontroller
+
+There are many other STM32 series that are currently not supported by QEMU.
+
+Supported devices
+-----------------
+
+ * ARM Cortex-M3, Cortex M4F
+ * Analog to Digital Converter (ADC)
+ * EXTI interrupt
+ * Serial ports (USART)
+ * SPI controller
+ * System configuration (SYSCFG)
+ * Timer controller (TIMER)
+
+Missing devices
+---------------
+
+ * Camera interface (DCMI)
+ * Controller Area Network (CAN)
+ * Cycle Redundancy Check (CRC) calculation unit
+ * Digital to Analog Converter (DAC)
+ * DMA controller
+ * Ethernet controller
+ * Flash Interface Unit
+ * GPIO controller
+ * I2C controller
+ * Inter-Integrated Sound (I2S) controller
+ * Power supply configuration (PWR)
+ * Random Number Generator (RNG)
+ * Real-Time Clock (RTC) controller
+ * Reset and Clock Controller (RCC)
+ * Secure Digital Input/Output (SDIO) interface
+ * USB OTG
+ * Watchdog controller (IWDG, WWDG)
+
+Boot options
+------------
+
+The STM32 machines can be started using the ``-kernel`` option to load a
+firmware. Example:
+
+.. code-block:: bash
+
+  $ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
    arm/collie
    arm/sx1
    arm/stellaris
+   arm/stm32
    arm/virt
    arm/xlnx-versal-virt
 
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Alexandre Iooss <erdnaxe@crans.org>
 L: qemu-arm@nongnu.org
 S: Maintained
 F: hw/arm/stm32vldiscovery.c
+F: docs/system/arm/stm32.rst
 
 Versatile Express
 M: Peter Maydell <peter.maydell@linaro.org>
-- 
2.20.1

From: Alexandre Iooss <erdnaxe@crans.org>

New mini-kernel test for STM32VLDISCOVERY USART1.

Signed-off-by: Alexandre Iooss <erdnaxe@crans.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210617165647.2575955-5-erdnaxe@crans.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c
index XXXXXXX..XXXXXXX 100644
--- a/tests/qtest/boot-serial-test.c
+++ b/tests/qtest/boot-serial-test.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t kernel_nrf51[] = {
     0x1c, 0x25, 0x00, 0x40                  /* 0x4000251c = UART TXD */
 };
 
+static const uint8_t kernel_stm32vldiscovery[] = {
+    0x00, 0x00, 0x00, 0x00,                 /* Stack top address */
+    0x1d, 0x00, 0x00, 0x00,                 /* Reset handler address */
+    0x00, 0x00, 0x00, 0x00,                 /* NMI */
+    0x00, 0x00, 0x00, 0x00,                 /* Hard fault */
+    0x00, 0x00, 0x00, 0x00,                 /* Memory management fault */
+    0x00, 0x00, 0x00, 0x00,                 /* Bus fault */
+    0x00, 0x00, 0x00, 0x00,                 /* Usage fault */
+    0x0b, 0x4b,                             /* ldr  r3, [pc, #44] Get RCC */
+    0x44, 0xf2, 0x04, 0x02,                 /* movw r2, #16388 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x0a, 0x4b,                             /* ldr  r3, [pc, #40] Get GPIOA */
+    0x1a, 0x68,                             /* ldr  r2, [r3] */
+    0x22, 0xf0, 0xf0, 0x02,                 /* bic  r2, r2, #240 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x1a, 0x68,                             /* ldr  r2, [r3] */
+    0x42, 0xf0, 0xb0, 0x02,                 /* orr  r2, r2, #176 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x07, 0x4b,                             /* ldr  r3, [pc, #26] Get BAUD */
+    0x45, 0x22,                             /* movs r2, #69 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x06, 0x4b,                             /* ldr  r3, [pc, #24] Get ENABLE */
+    0x42, 0xf2, 0x08, 0x02,                 /* movw r2, #8200 */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0x05, 0x4b,                             /* ldr  r3, [pc, #20] Get TXD */
+    0x54, 0x22,                             /* movs r2, 'T' */
+    0x1a, 0x60,                             /* str  r2, [r3] */
+    0xfe, 0xe7,                             /* b    . */
+    0x18, 0x10, 0x02, 0x40,                 /* 0x40021018 = RCC */
+    0x04, 0x08, 0x01, 0x40,                 /* 0x40010804 = GPIOA */
+    0x08, 0x38, 0x01, 0x40,                 /* 0x40013808 = USART1 BAUD */
+    0x0c, 0x38, 0x01, 0x40,                 /* 0x4001380c = USART1 ENABLE */
+    0x04, 0x38, 0x01, 0x40                  /* 0x40013804 = USART1 TXD */
+};
+
 typedef struct testdef {
     const char *arch;       /* Target architecture */
     const char *machine;    /* Name of the machine */
@@ -XXX,XX +XXX,XX @@ static testdef_t tests[] = {
     { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
       kernel_aarch64 },
     { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
+    { "arm", "stm32vldiscovery", "", "T",
+      sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
 
     { NULL }
 };
-- 
2.20.1

From: Ricardo Koller <ricarkol@google.com>

icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers
(like LPIs).  The issue is that these functions check against the number
of implemented IRQs (QEMU's default is num_irq=288) which can be lower
than the maximum virtual IRQ number (1020 - 1).  The consequence is that
if a hypervisor creates an LR for an IRQ between 288 and 1020, then the
guest is unable to deactivate the resulting IRQ. Note that other
functions that deal with large IRQ numbers, like icv_iar_read, check
against 1020 and not against num_irq.

Fix the checks by using GICV3_MAXIRQ (1020) instead of the number of
implemented IRQs.

Signed-off-by: Ricardo Koller <ricarkol@google.com>
Message-id: 20210702233701.3369-1-ricarkol@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_cpuif.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void icv_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value);
 
-    if (irq >= cs->gic->num_irq) {
+    if (irq >= GICV3_MAXIRQ) {
         /* Also catches special interrupt numbers and LPIs */
         return;
     }
@@ -XXX,XX +XXX,XX @@ static void icv_eoir_write(CPUARMState *env, const ARMCPRegInfo *ri,
     trace_gicv3_icv_eoir_write(ri->crm == 8 ? 0 : 1,
                                gicv3_redist_affid(cs), value);
 
-    if (irq >= cs->gic->num_irq) {
+    if (irq >= GICV3_MAXIRQ) {
         /* Also catches special interrupt numbers and LPIs */
         return;
     }
-- 
2.20.1

Convert the use of the DPRINTF debug macro in the PL061 model to
use tracepoints.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 27 +++++++++------------------
 hw/gpio/trace-events |  6 ++++++
 2 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "qom/object.h"
-
-//#define DEBUG_PL061 1
-
-#ifdef DEBUG_PL061
-#define DPRINTF(fmt, ...) \
-do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
-#define BADF(fmt, ...) \
-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
-#else
-#define DPRINTF(fmt, ...) do {} while(0)
-#define BADF(fmt, ...) \
-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
-#endif
+#include "trace.h"
 
 static const uint8_t pl061_id[12] =
   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
     uint8_t out;
     int i;
 
-    DPRINTF("dir = %d, data = %d\n", s->dir, s->data);
+    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
 
     /* Outputs float high.  */
     /* FIXME: This is board dependent.  */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
         for (i = 0; i < N_GPIOS; i++) {
             mask = 1 << i;
             if (changed & mask) {
-                DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
-                qemu_set_irq(s->out[i], (out & mask) != 0);
+                int level = (out & mask) != 0;
+                trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
+                qemu_set_irq(s->out[i], level);
             }
         }
     }
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
         for (i = 0; i < N_GPIOS; i++) {
             mask = 1 << i;
             if (changed & mask) {
-                DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
+                trace_pl061_input_change(DEVICE(s)->canonical_path, i,
+                                         (s->data & mask) != 0);
 
                 if (!(s->isense & mask)) {
                     /* Edge interrupt */
@@ -XXX,XX +XXX,XX @@ static void pl061_update(PL061State *s)
     /* Level interrupt */
     s->istate |= ~(s->data ^ s->iev) & s->isense;
 
-    DPRINTF("istate = %02X\n", s->istate);
+    trace_pl061_update_istate(DEVICE(s)->canonical_path,
+                              s->istate, s->im, (s->istate & s->im) != 0);
 
     qemu_set_irq(s->irq, (s->istate & s->im) != 0);
 }
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x
 nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 
+# pl061.c
+pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
+pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
+pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
+pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
+
 # sifive_gpio.c
 sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
 sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
-- 
2.20.1

Currently the pl061_read() and pl061_write() functions handle offsets
using a combination of three if() statements and a switch().  Clean
this up to use just a switch, using case ranges.

This requires that instead of catching accesses to the luminary-only
registers on a stock PL061 via a check on s->rsvd_start we use
an "is this luminary?" check in the cases for each luminary-only
register.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c | 104 ++++++++++++++++++++++++++++++++++++------------
 1 file changed, 79 insertions(+), 25 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ struct PL061State {
     qemu_irq irq;
     qemu_irq out[N_GPIOS];
     const unsigned char *id;
-    uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */
 };
 
 static const VMStateDescription vmstate_pl061 = {
@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
 {
     PL061State *s = (PL061State *)opaque;
 
-    if (offset < 0x400) {
-        return s->data & (offset >> 2);
-    }
-    if (offset >= s->rsvd_start && offset <= 0xfcc) {
-        goto err_out;
-    }
-    if (offset >= 0xfd0 && offset < 0x1000) {
-        return s->id[(offset - 0xfd0) >> 2];
-    }
     switch (offset) {
+    case 0x0 ... 0x3ff: /* Data */
+        return s->data & (offset >> 2);
     case 0x400: /* Direction */
         return s->dir;
     case 0x404: /* Interrupt sense */
@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
     case 0x420: /* Alternate function select */
         return s->afsel;
     case 0x500: /* 2mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->dr2r;
     case 0x504: /* 4mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->dr4r;
     case 0x508: /* 8mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->dr8r;
     case 0x50c: /* Open drain */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->odr;
     case 0x510: /* Pull-up */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->pur;
     case 0x514: /* Pull-down */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->pdr;
     case 0x518: /* Slew rate control */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->slr;
     case 0x51c: /* Digital enable */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->den;
     case 0x520: /* Lock */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->locked;
     case 0x524: /* Commit */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->cr;
     case 0x528: /* Analog mode select */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         return s->amsel;
+    case 0xfd0 ... 0xfff: /* ID registers */
+        return s->id[(offset - 0xfd0) >> 2];
     default:
+    bad_offset:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "pl061_read: Bad offset %x\n", (int)offset);
         break;
     }
-err_out:
-    qemu_log_mask(LOG_GUEST_ERROR,
-                  "pl061_read: Bad offset %x\n", (int)offset);
     return 0;
 }
 
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
     PL061State *s = (PL061State *)opaque;
     uint8_t mask;
 
-    if (offset < 0x400) {
+    switch (offset) {
+    case 0 ... 0x3ff:
         mask = (offset >> 2) & s->dir;
         s->data = (s->data & ~mask) | (value & mask);
         pl061_update(s);
         return;
-    }
-    if (offset >= s->rsvd_start) {
-        goto err_out;
-    }
-    switch (offset) {
     case 0x400: /* Direction */
         s->dir = value & 0xff;
         break;
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
         s->afsel = (s->afsel & ~mask) | (value & mask);
         break;
     case 0x500: /* 2mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->dr2r = value & 0xff;
         break;
     case 0x504: /* 4mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->dr4r = value & 0xff;
         break;
     case 0x508: /* 8mA drive */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->dr8r = value & 0xff;
         break;
     case 0x50c: /* Open drain */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->odr = value & 0xff;
         break;
     case 0x510: /* Pull-up */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->pur = value & 0xff;
         break;
     case 0x514: /* Pull-down */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->pdr = value & 0xff;
         break;
     case 0x518: /* Slew rate control */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->slr = value & 0xff;
         break;
     case 0x51c: /* Digital enable */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->den = value & 0xff;
         break;
     case 0x520: /* Lock */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->locked = (value != 0xacce551);
         break;
     case 0x524: /* Commit */
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         if (!s->locked)
             s->cr = value & 0xff;
         break;
     case 0x528:
+        if (s->id != pl061_id_luminary) {
+            goto bad_offset;
+        }
         s->amsel = value & 0xff;
         break;
     default:
-        goto err_out;
+    bad_offset:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "pl061_write: Bad offset %x\n", (int)offset);
+        return;
     }
     pl061_update(s);
     return;
-err_out:
-    qemu_log_mask(LOG_GUEST_ERROR,
-                  "pl061_write: Bad offset %x\n", (int)offset);
 }
 
 static void pl061_reset(DeviceState *dev)
@@ -XXX,XX +XXX,XX @@ static void pl061_luminary_init(Object *obj)
     PL061State *s = PL061(obj);
 
     s->id = pl061_id_luminary;
-    s->rsvd_start = 0x52c;
 }
 
 static void pl061_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 
     s->id = pl061_id;
-    s->rsvd_start = 0x424;
 
     memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000);
     sysbus_init_mmio(sbd, &s->iomem);
-- 
2.20.1

Add tracepoints for reads and writes to the PL061 registers. This requires
restructuring pl061_read() to only return after the tracepoint, rather
than having lots of early-returns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 70 ++++++++++++++++++++++++++++++--------------
 hw/gpio/trace-events |  2 ++
 2 files changed, 50 insertions(+), 22 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static uint64_t pl061_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
     PL061State *s = (PL061State *)opaque;
+    uint64_t r = 0;
 
     switch (offset) {
     case 0x0 ... 0x3ff: /* Data */
-        return s->data & (offset >> 2);
+        r = s->data & (offset >> 2);
+        break;
     case 0x400: /* Direction */
-        return s->dir;
+        r = s->dir;
+        break;
     case 0x404: /* Interrupt sense */
-        return s->isense;
+        r = s->isense;
+        break;
     case 0x408: /* Interrupt both edges */
-        return s->ibe;
+        r = s->ibe;
+        break;
     case 0x40c: /* Interrupt event */
-        return s->iev;
+        r = s->iev;
+        break;
     case 0x410: /* Interrupt mask */
-        return s->im;
+        r = s->im;
+        break;
     case 0x414: /* Raw interrupt status */
-        return s->istate;
+        r = s->istate;
+        break;
     case 0x418: /* Masked interrupt status */
-        return s->istate & s->im;
+        r = s->istate & s->im;
+        break;
     case 0x420: /* Alternate function select */
-        return s->afsel;
+        r = s->afsel;
+        break;
     case 0x500: /* 2mA drive */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->dr2r;
+        r = s->dr2r;
+        break;
     case 0x504: /* 4mA drive */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->dr4r;
+        r = s->dr4r;
+        break;
     case 0x508: /* 8mA drive */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->dr8r;
+        r = s->dr8r;
+        break;
     case 0x50c: /* Open drain */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->odr;
+        r = s->odr;
+        break;
     case 0x510: /* Pull-up */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->pur;
+        r = s->pur;
+        break;
     case 0x514: /* Pull-down */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->pdr;
+        r = s->pdr;
+        break;
     case 0x518: /* Slew rate control */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->slr;
+        r = s->slr;
+        break;
     case 0x51c: /* Digital enable */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->den;
+        r = s->den;
+        break;
     case 0x520: /* Lock */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->locked;
+        r = s->locked;
+        break;
     case 0x524: /* Commit */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->cr;
+        r = s->cr;
+        break;
     case 0x528: /* Analog mode select */
         if (s->id != pl061_id_luminary) {
             goto bad_offset;
         }
-        return s->amsel;
+        r = s->amsel;
+        break;
     case 0xfd0 ... 0xfff: /* ID registers */
-        return s->id[(offset - 0xfd0) >> 2];
+        r = s->id[(offset - 0xfd0) >> 2];
+        break;
     default:
     bad_offset:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "pl061_read: Bad offset %x\n", (int)offset);
         break;
     }
-    return 0;
+
+    trace_pl061_read(DEVICE(s)->canonical_path, offset, r);
+    return r;
 }
 
 static void pl061_write(void *opaque, hwaddr offset,
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
     PL061State *s = (PL061State *)opaque;
     uint8_t mask;
 
+    trace_pl061_write(DEVICE(s)->canonical_path, offset, value);
+
     switch (offset) {
     case 0 ... 0x3ff:
         mask = (offset >> 2) & s->dir;
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIOD
 pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
 pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
 pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
+pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
+pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
 
 # sifive_gpio.c
 sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-- 
2.20.1

The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR
which lets the guest configure whether the GPIO lines are pull-up,
pull-down, or truly floating. Instead of assuming all lines are pulled
high, honour the PUR and PDR registers.

For the plain PL061, continue to assume that lines have an external
pull-up resistor, as we did before.

The stellaris board actually relies on this behaviour -- the CD line
of the ssd0323 display device is connected to GPIO output C7, and it
is only because of a different bug which we're about to fix that we
weren't incorrectly driving this line high on reset and putting the
ssd0323 into data mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 58 +++++++++++++++++++++++++++++++++++++++++---
 hw/gpio/trace-events |  2 +-
 2 files changed, 55 insertions(+), 5 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_pl061 = {
     }
 };
 
+static uint8_t pl061_floating(PL061State *s)
+{
+    /*
+     * Return mask of bits which correspond to pins configured as inputs
+     * and which are floating (neither pulled up to 1 nor down to 0).
+     */
+    uint8_t floating;
+
+    if (s->id == pl061_id_luminary) {
+        /*
+         * If both PUR and PDR bits are clear, there is neither a pullup
+         * nor a pulldown in place, and the output truly floats.
+         */
+        floating = ~(s->pur | s->pdr);
+    } else {
+        /* Assume outputs are pulled high. FIXME: this is board dependent. */
+        floating = 0;
+    }
+    return floating & ~s->dir;
+}
+
+static uint8_t pl061_pullups(PL061State *s)
+{
+    /*
+     * Return mask of bits which correspond to pins configured as inputs
+     * and which are pulled up to 1.
+     */
+    uint8_t pullups;
+
+    if (s->id == pl061_id_luminary) {
+        /*
+         * The Luminary variant of the PL061 has an extra registers which
+         * the guest can use to configure whether lines should be pullup
+         * or pulldown.
+         */
+        pullups = s->pur;
+    } else {
+        /* Assume outputs are pulled high. FIXME: this is board dependent. */
+        pullups = 0xff;
+    }
+    return pullups & ~s->dir;
+}
+
 static void pl061_update(PL061State *s)
 {
     uint8_t changed;
     uint8_t mask;
     uint8_t out;
     int i;
+    uint8_t pullups = pl061_pullups(s);
+    uint8_t floating = pl061_floating(s);
 
-    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
+    trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data,
+                       pullups, floating);
 
-    /* Outputs float high.  */
-    /* FIXME: This is board dependent.  */
-    out = (s->data & s->dir) | ~s->dir;
+    /*
+     * Pins configured as output are driven from the data register;
+     * otherwise if they're pulled up they're 1, and if they're floating
+     * then we give them the same value they had previously, so we don't
+     * report any change to the other end.
+     */
+    out = (s->data & s->dir) | pullups | (s->old_out_data & floating);
     changed = s->old_out_data ^ out;
     if (changed) {
         s->old_out_data = out;
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
 
 # pl061.c
-pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x GPIODATA 0x%x"
+pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups, uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0x%x"
 pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to %d"
 pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to %d"
 pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
-- 
2.20.1

The PL061 GPIO does not itself include pullup or pulldown resistors
to set the value of a GPIO line treated as an output when it is
configured as an input (ie when the PL061 itself is not driving it).
In real hardware it is up to the board to add suitable pullups or
pulldowns.  Currently our implementation hardwires this to "outputs
pulled high", which is correct for some boards (eg the realview ones:
see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S
User Guide" DUI0224I), but wrong for others.

In particular, the wiring in the 'virt' board and the gpio-pwr device
assumes that wires should be pulled low, because otherwise the
pull-to-high will trigger a shutdown or reset action.  (The only
reason this doesn't happen immediately on startup is due to another
bug in the PL061, where we don't assert the GPIOs to the correct
value on reset, but will do so as soon as the guest touches a
register and pl061_update() gets called.)

Add properties to the pl061 so the board can configure whether it
wants GPIO lines to have pullup, pulldown, or neither.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c | 51 +++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 47 insertions(+), 4 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@
  *  + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lines
  *  + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as
  *    outputs
+ *  + QOM property "pullups": an integer defining whether non-floating lines
+ *    configured as inputs should be pulled up to logical 1 (ie whether in
+ *    real hardware they have a pullup resistor on the line out of the PL061).
+ *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
+ *    be pulled high, bit 1 configures line 1, and so on. The default is 0xff,
+ *    indicating that all GPIO lines are pulled up to logical 1.
+ *  + QOM property "pulldowns": an integer defining whether non-floating lines
+ *    configured as inputs should be pulled down to logical 0 (ie whether in
+ *    real hardware they have a pulldown resistor on the line out of the PL061).
+ *    This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should
+ *    be pulled low, bit 1 configures line 1, and so on. The default is 0x0.
+ *    It is an error to set a bit in both "pullups" and "pulldowns". If a bit
+ *    is 0 in both, then the line is considered to be floating, and it will
+ *    not have qemu_set_irq() called on it when it is configured as an input.
  */
 
 #include "qemu/osdep.h"
 #include "hw/irq.h"
 #include "hw/sysbus.h"
+#include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
+#include "qapi/error.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct PL061State {
     qemu_irq irq;
     qemu_irq out[N_GPIOS];
     const unsigned char *id;
+    /* Properties, for non-Luminary PL061 */
+    uint32_t pullups;
+    uint32_t pulldowns;
 };
 
 static const VMStateDescription vmstate_pl061 = {
@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_floating(PL061State *s)
          */
         floating = ~(s->pur | s->pdr);
     } else {
-        /* Assume outputs are pulled high. FIXME: this is board dependent. */
-        floating = 0;
+        floating = ~(s->pullups | s->pulldowns);
     }
     return floating & ~s->dir;
 }
@@ -XXX,XX +XXX,XX @@ static uint8_t pl061_pullups(PL061State *s)
          */
         pullups = s->pur;
     } else {
-        /* Assume outputs are pulled high. FIXME: this is board dependent. */
-        pullups = 0xff;
+        pullups = s->pullups;
     }
     return pullups & ~s->dir;
 }
@@ -XXX,XX +XXX,XX @@ static void pl061_init(Object *obj)
     qdev_init_gpio_out(dev, s->out, N_GPIOS);
 }
 
+static void pl061_realize(DeviceState *dev, Error **errp)
+{
+    PL061State *s = PL061(dev);
+
+    if (s->pullups > 0xff) {
+        error_setg(errp, "pullups property must be between 0 and 0xff");
+        return;
+    }
+    if (s->pulldowns > 0xff) {
+        error_setg(errp, "pulldowns property must be between 0 and 0xff");
+        return;
+    }
+    if (s->pullups & s->pulldowns) {
+        error_setg(errp, "no bit may be set both in pullups and pulldowns");
+        return;
+    }
+}
+
+static Property pl061_props[] = {
+    DEFINE_PROP_UINT32("pullups", PL061State, pullups, 0xff),
+    DEFINE_PROP_UINT32("pulldowns", PL061State, pulldowns, 0x0),
+    DEFINE_PROP_END_OF_LIST()
+};
+
 static void pl061_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
     dc->vmsd = &vmstate_pl061;
     dc->reset = &pl061_reset;
+    dc->realize = pl061_realize;
+    device_class_set_props(dc, pl061_props);
 }
 
 static const TypeInfo pl061_info = {
-- 
2.20.1

For the virt board we have two PL061 devices -- one for NonSecure which
is inputs only, and one for Secure which is outputs only. For the former,
we don't care whether its outputs are pulled low or high when the line is
configured as an input, because we don't connect them. For the latter,
we do care, because we wire the lines up to the gpio-pwr device, which
assumes that level 1 means "do the action" and 1 means "do nothing".
For consistency in case we add more outputs in future, configure both
PL061s to pull GPIO lines down to 0.

Reported-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/arm/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_gpio_devices(const VirtMachineState *vms, int gpio,
     MachineState *ms = MACHINE(vms);
 
     pl061_dev = qdev_new("pl061");
+    /* Pull lines down to 0 if not driven by the PL061 */
+    qdev_prop_set_uint32(pl061_dev, "pullups", 0);
+    qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
     s = SYS_BUS_DEVICE(pl061_dev);
     sysbus_realize_and_unref(s, &error_fatal);
     memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
-- 
2.20.1

The PL061 comes out of reset with all its lines configured as input,
which means they might need to be pulled to 0 or 1 depending on the
'pullups' and 'pulldowns' properties.  Currently we do not assert
these lines on reset; they will only be set whenever the guest first
touches a register that triggers a call to pl061_update().

Convert the device to three-phase reset so we have a place where we
can safely call qemu_set_irq() to set the floating lines to their
correct values.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/gpio/pl061.c      | 29 +++++++++++++++++++++++++----
 hw/gpio/trace-events |  1 +
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static void pl061_write(void *opaque, hwaddr offset,
     return;
 }
 
-static void pl061_reset(DeviceState *dev)
+static void pl061_enter_reset(Object *obj, ResetType type)
 {
-    PL061State *s = PL061(dev);
+    PL061State *s = PL061(obj);
+
+    trace_pl061_reset(DEVICE(s)->canonical_path);
 
     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
     s->data = 0;
-    s->old_out_data = 0;
     s->old_in_data = 0;
     s->dir = 0;
     s->isense = 0;
@@ -XXX,XX +XXX,XX @@ static void pl061_reset(DeviceState *dev)
     s->amsel = 0;
 }
 
+static void pl061_hold_reset(Object *obj)
+{
+    PL061State *s = PL061(obj);
+    int i, level;
+    uint8_t floating = pl061_floating(s);
+    uint8_t pullups = pl061_pullups(s);
+
+    for (i = 0; i < N_GPIOS; i++) {
+        if (extract32(floating, i, 1)) {
+            continue;
+        }
+        level = extract32(pullups, i, 1);
+        trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
+        qemu_set_irq(s->out[i], level);
+    }
+    s->old_out_data = pullups;
+}
+
 static void pl061_set_irq(void * opaque, int irq, int level)
 {
     PL061State *s = (PL061State *)opaque;
@@ -XXX,XX +XXX,XX @@ static Property pl061_props[] = {
 static void pl061_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
     dc->vmsd = &vmstate_pl061;
-    dc->reset = &pl061_reset;
     dc->realize = pl061_realize;
     device_class_set_props(dc, pl061_props);
+    rc->phases.enter = pl061_enter_reset;
+    rc->phases.hold = pl061_hold_reset;
 }
 
 static const TypeInfo pl061_info = {
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -XXX,XX +XXX,XX @@ pl061_input_change(const char *id, int gpio, int level) "%s input %d changed to
 pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
 pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
 pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x%" PRIx64 " value 0x%" PRIx64
+pl061_reset(const char *id) "%s reset"
 
 # sifive_gpio.c
 sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" PRIx64
-- 
2.20.1

The Luminary PL061s in the Stellaris LM3S9695 don't all have the same
reset value for GPIOPUR.  We can get away with not letting the board
configure the PUR reset value because we don't actually wire anything
up to the lines which should reset to pull-up.  Add a comment noting
this omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/gpio/pl061.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -XXX,XX +XXX,XX @@ static void pl061_enter_reset(Object *obj, ResetType type)
     trace_pl061_reset(DEVICE(s)->canonical_path);
 
     /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */
+
+    /*
+     * FIXME: For the LM3S6965, not all of the PL061 instances have the
+     * same reset values for GPIOPUR, GPIOAFSEL and GPIODEN, so in theory
+     * we should allow the board to configure these via properties.
+     * In practice, we don't wire anything up to the affected GPIO lines
+     * (PB7, PC0, PC1, PC2, PC3 -- they're used for JTAG), so we can
+     * get away with this inaccuracy.
+     */
     s->data = 0;
     s->old_in_data = 0;
     s->dir = 0;
-- 
2.20.1

The stellaris board doesn't emulate the handling of the OLED
chipselect line correctly.  Expand the comment describing this,
including a sketch of the theoretical correct way to do it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 56 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
             DeviceState *sddev;
             DeviceState *ssddev;
 
-            /* Some boards have both an OLED controller and SD card connected to
+            /*
+             * Some boards have both an OLED controller and SD card connected to
              * the same SSI port, with the SD card chip select connected to a
              * GPIO pin.  Technically the OLED chip select is connected to the
              * SSI Fss pin.  We do not bother emulating that as both devices
              * should never be selected simultaneously, and our OLED controller
              * ignores stray 0xff commands that occur when deselecting the SD
              * card.
+             *
+             * The h/w wiring is:
+             *  - GPIO pin D0 is wired to the active-low SD card chip select
+             *  - GPIO pin A3 is wired to the active-low OLED chip select
+             *  - The SoC wiring of the PL061 "auxiliary function" for A3 is
+             *    SSI0Fss ("frame signal"), which is an output from the SoC's
+             *    SSI controller. The SSI controller takes SSI0Fss low when it
+             *    transmits a frame, so it can work as a chip-select signal.
+             *  - GPIO A4 is aux-function SSI0Rx, and wired to the SD card Tx
+             *    (the OLED never sends data to the CPU, so no wiring needed)
+             *  - GPIO A5 is aux-function SSI0Tx, and wired to the SD card Rx
+             *    and the OLED display-data-in
+             *  - GPIO A2 is aux-function SSI0Clk, wired to SD card and OLED
+             *    serial-clock input
+             * So a guest that wants to use the OLED can configure the PL061
+             * to make pins A2, A3, A5 aux-function, so they are connected
+             * directly to the SSI controller. When the SSI controller sends
+             * data it asserts SSI0Fss which selects the OLED.
+             * A guest that wants to use the SD card configures A2, A4 and A5
+             * as aux-function, but leaves A3 as a software-controlled GPIO
+             * line. It asserts the SD card chip-select by using the PL061
+             * to control pin D0, and lets the SSI controller handle Clk, Tx
+             * and Rx. (The SSI controller asserts Fss during tx cycles as
+             * usual, but because A3 is not set to aux-function this is not
+             * forwarded to the OLED, and so the OLED stays unselected.)
+             *
+             * The QEMU implementation instead is:
+             *  - GPIO pin D0 is wired to the active-low SD card chip select,
+             *    and also to the OLED chip-select which is implemented
+             *    as *active-high*
+             *  - SSI controller signals go to the devices regardless of
+             *    whether the guest programs A2, A4, A5 as aux-function or not
+             *
+             * The problem with this implementation is if the guest doesn't
+             * care about the SD card and only uses the OLED. In that case it
+             * may choose never to do anything with D0 (leaving it in its
+             * default floating state, which reliably leaves the card disabled
+             * because an SD card has a pullup on CS within the card itself),
+             * and only set up A2, A3, A5. This for us would mean the OLED
+             * never gets the chip-select assert it needs. We work around
+             * this with a manual raise of D0 here (despite board creation
+             * code being the wrong place to raise IRQ lines) to put the OLED
+             * into an initially selected state.
+             *
+             * In theory the right way to model this would be:
+             *  - Implement aux-function support in the PL061, with an
+             *    extra set of AFIN and AFOUT GPIO lines (set up so that
+             *    if a GPIO line is in auxfn mode the main GPIO in and out
+             *    track the AFIN and AFOUT lines)
+             *  - Wire the AFOUT for D0 up to either a line from the
+             *    SSI controller that's pulled low around every transmit,
+             *    or at least to an always-0 line here on the board
+             *  - Make the ssd0323 OLED controller chipselect active-low
              */
             bus = qdev_get_child_bus(dev, "ssi");
 
-- 
2.20.1

From: "hnick@vmware.com" <hnick@vmware.com>

Signed-off-by: Nick Hudson <hnick@vmware.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
       .access = PL1_RW, .accessfn = access_tda,
       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
       .resetvalue = 0 },
-    /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
+    /*
+     * MDCCSR_EL0[30:29] map to EDSCR[30:29].  Simply RAZ as the external
+     * Debug Communication Channel is not implemented.
+     */
+    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_AA64,
+      .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
+      .access = PL0_R, .accessfn = access_tda,
+      .type = ARM_CP_CONST, .resetvalue = 0 },
+    /*
+     * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2].  Map all bits as
+     * it is unlikely a guest will care.
      * We don't implement the configurable EL0 access.
      */
-    { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
-      .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
+    { .name = "DBGDSCRint", .state = ARM_CP_STATE_AA32,
+      .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
       .type = ARM_CP_ALIAS,
       .access = PL1_R, .accessfn = access_tda,
       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
-- 
2.20.1

From: Rebecca Cran <rebecca@nuviainc.com>

Add a space in the message printed when gicr_read*/gicr_write* returns
MEMTX_ERROR in arm_gicv3_redist.c.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210706211432.31902-1-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gicv3_redist.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_redist.c
+++ b/hw/intc/arm_gicv3_redist.c
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data,
     if (r == MEMTX_ERROR) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: invalid guest read at offset " TARGET_FMT_plx
-                      "size %u\n", __func__, offset, size);
+                      " size %u\n", __func__, offset, size);
         trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset,
                                    size, attrs.secure);
         /* The spec requires that reserved registers are RAZ/WI;
@@ -XXX,XX +XXX,XX @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data,
     if (r == MEMTX_ERROR) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "%s: invalid guest write at offset " TARGET_FMT_plx
-                      "size %u\n", __func__, offset, size);
+                      " size %u\n", __func__, offset, size);
         trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data,
                                     size, attrs.secure);
         /* The spec requires that reserved registers are RAZ/WI;
-- 
2.20.1