Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200330210400.11724-4-peter.maydell@linaro.org

target_ulong *page_size_ptr,

ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);

@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,

}

ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,

+ false,

&s2pa, &txattrs, &s2prot, &s2size, fi,

pcacheattrs);

if (ret) {

target_ulong *page_size_ptr,

ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)

@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,

/* S1 is done. Now do S2 translation. */

ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,

+ mmu_idx == ARMMMUIdx_E10_0,

phys_ptr, attrs, &s2_prot,

page_size, fi,

cacheattrs != NULL ? &cacheattrs2 : NULL);

@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,

}

if (regime_using_lpae_format(env, mmu_idx)) {

- return get_phys_addr_lpae(env, address, access_type, mmu_idx,

+ return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,

phys_ptr, attrs, prot, page_size,

fi, cacheattrs);

} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200430181003.21682-11-peter.maydell@linaro.org

-/* Advanced SIMD two registers and a scalar extension.

- * 31 24 23 22 20 16 12 11 10 9 8 3 0

- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+

- * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |

- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+

- *

- */

-

-static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)

-{

- gen_helper_gvec_3 *fn_gvec = NULL;

- gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;

- int rd, rn, rm, opr_sz, data;

- int off_rn, off_rm;

- bool is_long = false, q = extract32(insn, 6, 1);

- bool ptr_is_env = false;

-

- if ((insn & 0xffa00f10) == 0xfe000810) {

- /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */

- int is_s = extract32(insn, 20, 1);

- int vm20 = extract32(insn, 0, 3);

- int vm3 = extract32(insn, 3, 1);

- int m = extract32(insn, 5, 1);

- int index;

-

- if (!dc_isar_feature(aa32_fhm, s)) {

- return 1;

- }

- if (q) {

- rm = vm20;

- index = m * 2 + vm3;

- } else {

- rm = vm20 * 2 + m;

- index = vm3;

- }

- is_long = true;

- data = (index << 2) | is_s; /* is_2 == 0 */

- fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;

- ptr_is_env = true;

- } else {

- return 1;

- }

-

- VFP_DREG_D(rd, insn);

- if (rd & q) {

- return 1;

- }

- if (q || !is_long) {

- VFP_DREG_N(rn, insn);

- if (rn & q & !is_long) {

- return 1;

- }

- off_rn = vfp_reg_offset(1, rn);

- off_rm = vfp_reg_offset(1, rm);

- } else {

- rn = VFP_SREG_N(insn);

- off_rn = vfp_reg_offset(0, rn);

- off_rm = vfp_reg_offset(0, rm);

- }

- if (s->fp_excp_el) {

- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,

- syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);

- return 0;

- }

- if (!s->vfp_enabled) {

- return 1;

- }

-

- opr_sz = (1 + q) * 8;

- if (fn_gvec_ptr) {

- TCGv_ptr ptr;

- if (ptr_is_env) {

- ptr = cpu_env;

- } else {

- ptr = get_fpstatus_ptr(1);

- }

- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,

- opr_sz, opr_sz, data, fn_gvec_ptr);

- if (!ptr_is_env) {

- tcg_temp_free_ptr(ptr);

- }

- } else {

- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,

- opr_sz, opr_sz, data, fn_gvec);

- }

- return 0;

-}

-

static int disas_coproc_insn(DisasContext *s, uint32_t insn)

{

int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

}

}

}

- } else if ((insn & 0x0f000a00) == 0x0e000800

- && arm_dc_feature(s, ARM_FEATURE_V8)) {

- if (disas_neon_insn_2reg_scalar_ext(s, insn)) {

- goto illegal_op;

- }

- return;

}

goto illegal_op;

}

@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)

}

break;

}

- if ((insn & 0xff000a00) == 0xfe000800

- && arm_dc_feature(s, ARM_FEATURE_V8)) {

- /* The Thumb2 and ARM encodings are identical. */

- if (disas_neon_insn_2reg_scalar_ext(s, insn)) {

- goto illegal_op;

- }

- } else if (((insn >> 24) & 3) == 3) {

+ if (((insn >> 24) & 3) == 3) {

/* Translate into the equivalent ARM encoding. */

insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);

if (disas_neon_data_insn(s, insn)) {

MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.

Represent it in QEMU's ARMCPU struct with a uint64_t, not a

uint32_t.

This fixes an error when compiling with -Werror=conversion

because we were manipulating the register value using a

local uint64_t variable:

target/arm/cpu64.c: In function ‘aarch64_max_initfn’:

target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]

628 | cpu->midr = t;

| ^

and future-proofs us against a possible future architecture

change using some of the top 32 bits.

Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200430181003.21682-20-peter.maydell@linaro.org