Series comparison

-[PULL 00/39] target-arm queue
+[PULL 00/18] target-arm queue
-Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups.
+Nothing very exciting this time around...
-thanks
 -- PMM
+The following changes since commit 37a712a0f969ca2df7f01182409a6c4825cebfb5:
-The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835:
+  Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-10-01 12:23:19 +0100)
   Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201001
-for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:
+for you to fetch changes up to cdfaa57dcb53ba012439765a1462247dfda8595d:
-  target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100)
+  hw/arm/raspi: Remove use of the 'version' value in the board code (2020-10-01 15:31:01 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * Start of conversion of Neon insns to decodetree
+ * Make isar_feature_aa32_fp16_arith() handle M-profile
- * versal board: support SD and RTC
+ * Fix SVE splice
- * Implement ARMv8.2-TTS2UXN
+ * Fix SVE LDR/STR
- * Make VQDMULL undefined when U=1
+ * Remove ignore_memory_transaction_failures on the raspi2
- * Some minor code cleanups
+ * raspi: Various cleanup/refactoring
 ----------------------------------------------------------------
-Edgar E. Iglesias (11):
+Peter Maydell (5):
-      hw/arm: versal: Remove inclusion of arm_gicv3_common.h
+      target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
-      hw/arm: versal: Move misplaced comment
+      target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
-      hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal
+      hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
-      hw/arm: versal: Embed the UARTs into the SoC type
+      target/arm: Add ID register values for Cortex-M0
-      hw/arm: versal: Embed the GEMs into the SoC type
+      target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
       hw/arm: versal: Embed the ADMAs into the SoC type
       hw/arm: versal: Embed the APUs into the SoC type
       hw/arm: versal: Add support for SD
       hw/arm: versal: Add support for the RTC
       hw/arm: versal-virt: Add support for SD
       hw/arm: versal-virt: Add support for the RTC
-Fredrik Strupe (1):
+Philippe Mathieu-Daudé (11):
-      target/arm: Make VQDMULL undefined when U=1
+      hw/arm/raspi: Define various blocks base addresses
       hw/arm/bcm2835: Add more unimplemented peripherals
       hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
       hw/arm/raspi: Display the board revision in the machine description
       hw/arm/raspi: Load the firmware on the first core
       hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
       hw/arm/raspi: Avoid using TypeInfo::class_data pointer
       hw/arm/raspi: Use more specific machine names
       hw/arm/raspi: Introduce RaspiProcessorId enum
       hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
       hw/arm/raspi: Remove use of the 'version' value in the board code
-Peter Maydell (25):
+Richard Henderson (2):
-      target/arm: Don't use a TLB for ARMMMUIdx_Stage2
+      target/arm: Fix sve ldr/str
-      target/arm: Use enum constant in get_phys_addr_lpae() call
+      target/arm: Fix SVE splice
       target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()
       target/arm: Implement ARMv8.2-TTS2UXN
       target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0
       target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
       target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
       target/arm: Add stubs for AArch32 Neon decodetree
       target/arm: Convert VCMLA (vector) to decodetree
       target/arm: Convert VCADD (vector) to decodetree
       target/arm: Convert V[US]DOT (vector) to decodetree
       target/arm: Convert VFM[AS]L (vector) to decodetree
       target/arm: Convert VCMLA (scalar) to decodetree
       target/arm: Convert V[US]DOT (scalar) to decodetree
       target/arm: Convert VFM[AS]L (scalar) to decodetree
       target/arm: Convert Neon load/store multiple structures to decodetree
       target/arm: Convert Neon 'load single structure to all lanes' to decodetree
       target/arm: Convert Neon 'load/store single structure' to decodetree
       target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
       target/arm: Convert Neon 3-reg-same logic ops to decodetree
       target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
       target/arm: Convert Neon 3-reg-same comparisons to decodetree
       target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
       target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
       target/arm: Move gen_ function typedefs to translate.h
-Philippe Mathieu-Daudé (2):
+ include/hw/arm/bcm2835_peripherals.h |   2 +
-      hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string
+ include/hw/arm/raspi_platform.h      |  51 ++++++++++--
-      target/arm: Use uint64_t for midr field in CPU state struct
+ target/arm/cpu.h                     |  50 +++++++++--
  hw/arm/bcm2835_peripherals.c         |   2 +
  hw/arm/raspi.c                       | 155 +++++++++++++++++++----------------
  hw/intc/armv7m_nvic.c                |  46 ++++++++++-
  target/arm/cpu.c                     |  21 +++--
  target/arm/cpu64.c                   |  12 +--
  target/arm/cpu_tcg.c                 |  60 ++++++++++----
  target/arm/helper.c                  |   9 +-
  target/arm/kvm64.c                   |   4 +
  target/arm/translate-sve.c           |   6 +-
 files changed, 286 insertions(+), 132 deletions(-)
- include/hw/arm/xlnx-versal.h    |  31 +-
- target/arm/cpu-param.h          |   2 +-
- target/arm/cpu.h                |  38 ++-
- target/arm/translate-a64.h      |   9 -
- target/arm/translate.h          |  26 ++
- target/arm/neon-dp.decode       |  86 +++++
- target/arm/neon-ls.decode       |  52 +++
- target/arm/neon-shared.decode   |  66 ++++
- hw/arm/mps2-tz.c                |   2 +-
- hw/arm/xlnx-versal-virt.c       |  74 ++++-
- hw/arm/xlnx-versal.c            | 115 +++++--
- target/arm/cpu.c                |   3 +-
- target/arm/cpu64.c              |   8 +-
- target/arm/helper.c             | 183 ++++------
- target/arm/translate-a64.c      |  17 -
- target/arm/translate-neon.inc.c | 714 +++++++++++++++++++++++++++++++++++++++
- target/arm/translate-vfp.inc.c  |   6 -
- target/arm/translate.c          | 716 +++-------------------------------------
- target/arm/Makefile.objs        |  18 +
-files changed, 1302 insertions(+), 864 deletions(-)
- create mode 100644 target/arm/neon-dp.decode
- create mode 100644 target/arm/neon-ls.decode
- create mode 100644 target/arm/neon-shared.decode
- create mode 100644 target/arm/translate-neon.inc.c

-[PULL 06/39] target/arm: Implement ARMv8.2-TTS2UXN
+[PULL 01/18] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
-The ARMv8.2-TTS2UXN feature extends the XN field in stage 2
+The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN
-translation table descriptors from just bit [54] to bits [54:53],
+bit in short-descriptor translation table format descriptors.  This
-allowing stage 2 to control execution permissions separately for EL0
+is indicated by ID_MMFR0.VMSA being at least 0b0100.  Replace the
-and EL1. Implement the new semantics of the XN field and enable
+feature bit with an ID register check, in line with our preference
-the feature for our 'max' CPU.
+for ID register checks over feature bits.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200330210400.11724-5-peter.maydell@linaro.org
+Message-id: 20200910173855.4068-2-peter.maydell@linaro.org
 ---
- target/arm/cpu.h    | 15 +++++++++++++++
+ target/arm/cpu.h    | 15 ++++++++++++++-
- target/arm/cpu.c    |  1 +
+ target/arm/cpu.c    |  1 -
- target/arm/cpu64.c  |  2 ++
+ target/arm/helper.c |  5 +++--
- target/arm/helper.c | 37 +++++++++++++++++++++++++++++++------
+files changed, 17 insertions(+), 4 deletions(-)
 files changed, 49 insertions(+), 6 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, FHM, 8, 4)
-     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
+ FIELD(ID_ISAR6, SB, 12, 4)
  FIELD(ID_ISAR6, SPECRES, 16, 4)
 +FIELD(ID_MMFR0, VMSA, 0, 4)
 +FIELD(ID_MMFR0, PMSA, 4, 4)
 +FIELD(ID_MMFR0, OUTERSHR, 8, 4)
 +FIELD(ID_MMFR0, SHARELVL, 12, 4)
 +FIELD(ID_MMFR0, TCM, 16, 4)
 +FIELD(ID_MMFR0, AUXREG, 20, 4)
 +FIELD(ID_MMFR0, FCSE, 24, 4)
 +FIELD(ID_MMFR0, INNERSHR, 28, 4)
 +
  FIELD(ID_MMFR3, CMAINTVA, 0, 4)
  FIELD(ID_MMFR3, CMAINTSW, 4, 4)
  FIELD(ID_MMFR3, BPMAINT, 8, 4)
@@ -XXX,XX +XXX,XX @@ enum arm_features {
      ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
      ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
      ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 -    ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
      ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
      ARM_FEATURE_V8,
      ARM_FEATURE_AARCH64, /* supports 64 bit mode */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
      return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
  }
-+static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
++static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
 +{
-+    return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
++    return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
 +}
 +
- /*
+ static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
-  * 64-bit feature tests via id registers.
+ {
-  */
+     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
      return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
  }
 +static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
 +{
 +    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
 +}
 +
  /*
   * Feature tests for "does this exist in either 32-bit or 64-bit?"
   */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
      return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
  }
 +static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
 +{
 +    return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
 +}
 +
  /*
   * Forward to the above feature tests given an ARMCPU pointer.
   */
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-             t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+     }
-             t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+     if (arm_feature(env, ARM_FEATURE_LPAE)) {
-             t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+         set_feature(env, ARM_FEATURE_V7MP);
-+            t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+-        set_feature(env, ARM_FEATURE_PXN);
-             cpu->isar.id_mmfr4 = t;
+     }
-         }
+     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
- #endif
+         set_feature(env, ARM_FEATURE_CBAR);
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
          t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
          t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
          t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
 +        t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
          cpu->isar.id_aa64mmfr1 = t;
          t = cpu->isar.id_aa64mmfr2;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
          u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
          u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
          u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
 +        u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
          cpu->isar.id_mmfr4 = u;
          u = cpu->isar.id_aa64dfr0;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
-  *
+                              target_ulong *page_size, ARMMMUFaultInfo *fi)
   * @env:     CPUARMState
   * @s2ap:    The 2-bit stage2 access permissions (S2AP)
 - * @xn:      XN (execute-never) bit
 + * @xn:      XN (execute-never) bits
 + * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
   */
 -static int get_S2prot(CPUARMState *env, int s2ap, int xn)
 +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
  {
-     int prot = 0;
+     CPUState *cs = env_cpu(env);
++    ARMCPU *cpu = env_archcpu(env);
-@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn)
+     int level = 1;
-     if (s2ap & 2) {
+     uint32_t table;
-         prot |= PAGE_WRITE;
+     uint32_t desc;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
          goto do_fault;
      }
--    if (!xn) {
+     type = (desc & 3);
--        if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
+-    if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
-+
++    if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
-+    if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {
+         /* Section translation fault, or attempt to use the encoding
-+        switch (xn) {
+          * which is Reserved on implementations without PXN.
-+        case 0:
+          */
-             prot |= PAGE_EXEC;
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
-+            break;
+         pxn = desc & 1;
-+        case 1:
+         ns = extract32(desc, 19, 1);
-+            if (s1_is_el0) {
+     } else {
-+                prot |= PAGE_EXEC;
+-        if (arm_feature(env, ARM_FEATURE_PXN)) {
-+            }
++        if (cpu_isar_feature(aa32_pxn, cpu)) {
-+            break;
+             pxn = (desc >> 2) & 1;
 +        case 2:
 +            break;
 +        case 3:
 +            if (!s1_is_el0) {
 +                prot |= PAGE_EXEC;
 +            }
 +            break;
 +        default:
 +            g_assert_not_reached();
 +        }
 +    } else {
 +        if (!extract32(xn, 1, 1)) {
 +            if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
 +                prot |= PAGE_EXEC;
 +            }
          }
-     }
+         ns = extract32(desc, 3, 1);
      return prot;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
      }
      ap = extract32(attrs, 4, 2);
 -    xn = extract32(attrs, 12, 1);
      if (mmu_idx == ARMMMUIdx_Stage2) {
          ns = true;
 -        *prot = get_S2prot(env, ap, xn);
 +        xn = extract32(attrs, 11, 2);
 +        *prot = get_S2prot(env, ap, xn, s1_is_el0);
      } else {
          ns = extract32(attrs, 3, 1);
 +        xn = extract32(attrs, 12, 1);
          pxn = extract32(attrs, 11, 1);
          *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
      }
 --
 .20.1

-[PULL 08/39] target/arm: Use uint64_t for midr field in CPU state struct
+[PULL 02/18] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
-From: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters
+sub-struct. We're going to want id_pfr1 for an isar_features
-MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.
+check, and moving both at the same time avoids an odd
-Represent it in QEMU's ARMCPU struct with a uint64_t, not a
+inconsistency.
-uint32_t.
+Changes other than the ones to cpu.h and kvm64.c made
-This fixes an error when compiling with -Werror=conversion
+automatically with:
-because we were manipulating the register value using a
+  perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c
-local uint64_t variable:
   target/arm/cpu64.c: In function ‘aarch64_max_initfn’:
   target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]
 |         cpu->midr = t;
         |                     ^
 and future-proofs us against a possible future architecture
 change using some of the top 32 bits.
 Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Suggested-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
 Message-id: 20200428172634.29707-1-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
 ---
- target/arm/cpu.h | 2 +-
+ target/arm/cpu.h      |  4 ++--
- target/arm/cpu.c | 2 +-
+ hw/intc/armv7m_nvic.c |  4 ++--
-files changed, 2 insertions(+), 2 deletions(-)
+ target/arm/cpu.c      | 20 ++++++++++----------
  target/arm/cpu64.c    | 12 ++++++------
  target/arm/cpu_tcg.c  | 36 ++++++++++++++++++------------------
  target/arm/helper.c   |  4 ++--
  target/arm/kvm64.c    |  4 ++++
 files changed, 44 insertions(+), 40 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
 @@ -XXX,XX +XXX,XX @@ struct ARMCPU {
-         uint64_t id_aa64dfr0;
+         uint32_t id_mmfr2;
-         uint64_t id_aa64dfr1;
+         uint32_t id_mmfr3;
-     } isar;
+         uint32_t id_mmfr4;
--    uint32_t midr;
++        uint32_t id_pfr0;
-+    uint64_t midr;
++        uint32_t id_pfr1;
-     uint32_t revidr;
+         uint32_t mvfr0;
          uint32_t mvfr1;
          uint32_t mvfr2;
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
      uint32_t reset_fpsid;
      uint32_t ctr;
+     uint32_t reset_sctlr;
+-    uint32_t id_pfr0;
+-    uint32_t id_pfr1;
+     uint64_t pmceid0;
+     uint64_t pmceid1;
+     uint32_t id_afr0;
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/armv7m_nvic.c
++++ b/hw/intc/armv7m_nvic.c
+@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
+                       "Aux Fault status registers unimplemented\n");
+         return 0;
+     case 0xd40: /* PFR0.  */
+-        return cpu->id_pfr0;
++        return cpu->isar.id_pfr0;
+     case 0xd44: /* PFR1.  */
+-        return cpu->id_pfr1;
++        return cpu->isar.id_pfr1;
+     case 0xd48: /* DFR0.  */
+         return cpu->isar.id_dfr0;
+     case 0xd4c: /* AFR0.  */
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
- static Property arm_cpu_properties[] = {
+         /* Disable the security extension feature bits in the processor feature
-     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
+          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
-     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
+          */
--    DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
+-        cpu->id_pfr1 &= ~0xf0;
-+    DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
++        cpu->isar.id_pfr1 &= ~0xf0;
-     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
+         cpu->isar.id_aa64pfr0 &= ~0xf000;
-                         mp_affinity, ARM64_AFFINITY_INVALID),
+     }
-     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
           * id_aa64pfr0_el1[11:8].
           */
          cpu->isar.id_aa64pfr0 &= ~0xf00;
 -        cpu->id_pfr1 &= ~0xf000;
 +        cpu->isar.id_pfr1 &= ~0xf000;
      }
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
      cpu->isar.mvfr1 = 0x00011111;
      cpu->ctr = 0x82048004;
      cpu->reset_sctlr = 0x00c50078;
 -    cpu->id_pfr0 = 0x1031;
 -    cpu->id_pfr1 = 0x11;
 +    cpu->isar.id_pfr0 = 0x1031;
 +    cpu->isar.id_pfr1 = 0x11;
      cpu->isar.id_dfr0 = 0x400;
      cpu->id_afr0 = 0;
      cpu->isar.id_mmfr0 = 0x31100003;
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
      cpu->isar.mvfr1 = 0x01111111;
      cpu->ctr = 0x80038003;
      cpu->reset_sctlr = 0x00c50078;
 -    cpu->id_pfr0 = 0x1031;
 -    cpu->id_pfr1 = 0x11;
 +    cpu->isar.id_pfr0 = 0x1031;
 +    cpu->isar.id_pfr1 = 0x11;
      cpu->isar.id_dfr0 = 0x000;
      cpu->id_afr0 = 0;
      cpu->isar.id_mmfr0 = 0x00100103;
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
      cpu->isar.mvfr1 = 0x11111111;
      cpu->ctr = 0x84448003;
      cpu->reset_sctlr = 0x00c50078;
 -    cpu->id_pfr0 = 0x00001131;
 -    cpu->id_pfr1 = 0x00011011;
 +    cpu->isar.id_pfr0 = 0x00001131;
 +    cpu->isar.id_pfr1 = 0x00011011;
      cpu->isar.id_dfr0 = 0x02010555;
      cpu->id_afr0 = 0x00000000;
      cpu->isar.id_mmfr0 = 0x10101105;
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
      cpu->isar.mvfr1 = 0x11111111;
      cpu->ctr = 0x8444c004;
      cpu->reset_sctlr = 0x00c50078;
 -    cpu->id_pfr0 = 0x00001131;
 -    cpu->id_pfr1 = 0x00011011;
 +    cpu->isar.id_pfr0 = 0x00001131;
 +    cpu->isar.id_pfr1 = 0x00011011;
      cpu->isar.id_dfr0 = 0x02010555;
      cpu->id_afr0 = 0x00000000;
      cpu->isar.id_mmfr0 = 0x10201105;
 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu64.c
 +++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
      cpu->isar.mvfr2 = 0x00000043;
      cpu->ctr = 0x8444c004;
      cpu->reset_sctlr = 0x00c50838;
 -    cpu->id_pfr0 = 0x00000131;
 -    cpu->id_pfr1 = 0x00011011;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
      cpu->isar.id_dfr0 = 0x03010066;
      cpu->id_afr0 = 0x00000000;
      cpu->isar.id_mmfr0 = 0x10101105;
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
      cpu->isar.mvfr2 = 0x00000043;
      cpu->ctr = 0x84448004; /* L1Ip = VIPT */
      cpu->reset_sctlr = 0x00c50838;
 -    cpu->id_pfr0 = 0x00000131;
 -    cpu->id_pfr1 = 0x00011011;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
      cpu->isar.id_dfr0 = 0x03010066;
      cpu->id_afr0 = 0x00000000;
      cpu->isar.id_mmfr0 = 0x10101105;
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
      cpu->isar.mvfr2 = 0x00000043;
      cpu->ctr = 0x8444c004;
      cpu->reset_sctlr = 0x00c50838;
 -    cpu->id_pfr0 = 0x00000131;
 -    cpu->id_pfr1 = 0x00011011;
 +    cpu->isar.id_pfr0 = 0x00000131;
 +    cpu->isar.id_pfr1 = 0x00011011;
      cpu->isar.id_dfr0 = 0x03010066;
      cpu->id_afr0 = 0x00000000;
      cpu->isar.id_mmfr0 = 0x10201105;
 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu_tcg.c
 +++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
      cpu->isar.mvfr1 = 0x00000000;
      cpu->ctr = 0x1dd20d2;
      cpu->reset_sctlr = 0x00050078;
 -    cpu->id_pfr0 = 0x111;
 -    cpu->id_pfr1 = 0x1;
 +    cpu->isar.id_pfr0 = 0x111;
 +    cpu->isar.id_pfr1 = 0x1;
      cpu->isar.id_dfr0 = 0x2;
      cpu->id_afr0 = 0x3;
      cpu->isar.id_mmfr0 = 0x01130003;
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
      cpu->isar.mvfr1 = 0x00000000;
      cpu->ctr = 0x1dd20d2;
      cpu->reset_sctlr = 0x00050078;
 -    cpu->id_pfr0 = 0x111;
 -    cpu->id_pfr1 = 0x1;
 +    cpu->isar.id_pfr0 = 0x111;
 +    cpu->isar.id_pfr1 = 0x1;
      cpu->isar.id_dfr0 = 0x2;
      cpu->id_afr0 = 0x3;
      cpu->isar.id_mmfr0 = 0x01130003;
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
      cpu->isar.mvfr1 = 0x00000000;
      cpu->ctr = 0x1dd20d2;
      cpu->reset_sctlr = 0x00050078;
 -    cpu->id_pfr0 = 0x111;
 -    cpu->id_pfr1 = 0x11;
 +    cpu->isar.id_pfr0 = 0x111;
 +    cpu->isar.id_pfr1 = 0x11;
      cpu->isar.id_dfr0 = 0x33;
      cpu->id_afr0 = 0;
      cpu->isar.id_mmfr0 = 0x01130003;
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
      cpu->isar.mvfr0 = 0x11111111;
      cpu->isar.mvfr1 = 0x00000000;
      cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 -    cpu->id_pfr0 = 0x111;
 -    cpu->id_pfr1 = 0x1;
 +    cpu->isar.id_pfr0 = 0x111;
 +    cpu->isar.id_pfr1 = 0x1;
      cpu->isar.id_dfr0 = 0;
      cpu->id_afr0 = 0x2;
      cpu->isar.id_mmfr0 = 0x01100103;
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
      cpu->midr = 0x410fc231;
      cpu->pmsav7_dregion = 8;
 -    cpu->id_pfr0 = 0x00000030;
 -    cpu->id_pfr1 = 0x00000200;
 +    cpu->isar.id_pfr0 = 0x00000030;
 +    cpu->isar.id_pfr1 = 0x00000200;
      cpu->isar.id_dfr0 = 0x00100000;
      cpu->id_afr0 = 0x00000000;
      cpu->isar.id_mmfr0 = 0x00000030;
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
      cpu->isar.mvfr0 = 0x10110021;
      cpu->isar.mvfr1 = 0x11000011;
      cpu->isar.mvfr2 = 0x00000000;
 -    cpu->id_pfr0 = 0x00000030;
 -    cpu->id_pfr1 = 0x00000200;
 +    cpu->isar.id_pfr0 = 0x00000030;
 +    cpu->isar.id_pfr1 = 0x00000200;
      cpu->isar.id_dfr0 = 0x00100000;
      cpu->id_afr0 = 0x00000000;
      cpu->isar.id_mmfr0 = 0x00000030;
@@ -XXX,XX +XXX,XX @@ static void cortex_m7_initfn(Object *obj)
      cpu->isar.mvfr0 = 0x10110221;
      cpu->isar.mvfr1 = 0x12000011;
      cpu->isar.mvfr2 = 0x00000040;
 -    cpu->id_pfr0 = 0x00000030;
 -    cpu->id_pfr1 = 0x00000200;
 +    cpu->isar.id_pfr0 = 0x00000030;
 +    cpu->isar.id_pfr1 = 0x00000200;
      cpu->isar.id_dfr0 = 0x00100000;
      cpu->id_afr0 = 0x00000000;
      cpu->isar.id_mmfr0 = 0x00100030;
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
      cpu->isar.mvfr0 = 0x10110021;
      cpu->isar.mvfr1 = 0x11000011;
      cpu->isar.mvfr2 = 0x00000040;
 -    cpu->id_pfr0 = 0x00000030;
 -    cpu->id_pfr1 = 0x00000210;
 +    cpu->isar.id_pfr0 = 0x00000030;
 +    cpu->isar.id_pfr1 = 0x00000210;
      cpu->isar.id_dfr0 = 0x00200000;
      cpu->id_afr0 = 0x00000000;
      cpu->isar.id_mmfr0 = 0x00101F40;
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
      set_feature(&cpu->env, ARM_FEATURE_PMSA);
      set_feature(&cpu->env, ARM_FEATURE_PMU);
      cpu->midr = 0x411fc153; /* r1p3 */
 -    cpu->id_pfr0 = 0x0131;
 -    cpu->id_pfr1 = 0x001;
 +    cpu->isar.id_pfr0 = 0x0131;
 +    cpu->isar.id_pfr1 = 0x001;
      cpu->isar.id_dfr0 = 0x010400;
      cpu->id_afr0 = 0x0;
      cpu->isar.id_mmfr0 = 0x0210030;
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
  static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
      ARMCPU *cpu = env_archcpu(env);
 -    uint64_t pfr1 = cpu->id_pfr1;
 +    uint64_t pfr1 = cpu->isar.id_pfr1;
      if (env->gicv3state) {
          pfr1 |= 1 << 28;
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
                .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
                .access = PL1_R, .type = ARM_CP_CONST,
                .accessfn = access_aa32_tid3,
 -              .resetvalue = cpu->id_pfr0 },
 +              .resetvalue = cpu->isar.id_pfr0 },
              /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
               * the value of the GIC field until after we define these regs.
               */
 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm64.c
 +++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
           * than skipping the reads and leaving 0, as we must avoid
           * considering the values in every case.
           */
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
 +                              ARM64_SYS_REG(3, 0, 0, 1, 0));
 +        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
 +                              ARM64_SYS_REG(3, 0, 0, 1, 1));
          err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
                                ARM64_SYS_REG(3, 0, 0, 1, 2));
          err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
 --
 .20.1

-[PULL 39/39] target/arm: Move gen_ function typedefs to translate.h
+[PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
-We're going to want at least some of the NeonGen* typedefs
+M-profile CPUs only implement the ID registers as guest-visible if
-for the refactored 32-bit Neon decoder, so move them all
+the CPU implements the Main Extension (all our current CPUs except
-to translate.h since it makes more sense to keep them in
+the Cortex-M0 do).
-one group.
 Currently we handle this by having the Cortex-M0 leave the ID
 register values in the ARMCPU struct as zero, but this conflicts with
 our design decision to make QEMU behaviour be keyed off ID register
 fields wherever possible.
 Explicitly code the ID registers in the NVIC to return 0 if the Main
 Extension is not implemented, so we can make the M0 model set the
 ARMCPU struct fields to obtain the correct behaviour without those
 values becoming guest-visible.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-23-peter.maydell@linaro.org
+Message-id: 20200910173855.4068-4-peter.maydell@linaro.org
 ---
- target/arm/translate.h     | 17 +++++++++++++++++
+ hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++++++++++++
- target/arm/translate-a64.c | 17 -----------------
+file changed, 42 insertions(+)
 files changed, 17 insertions(+), 17 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/hw/intc/armv7m_nvic.c
-+++ b/target/arm/translate.h
++++ b/hw/intc/armv7m_nvic.c
-@@ -XXX,XX +XXX,XX @@ typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
- typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
+                       "Aux Fault status registers unimplemented\n");
-                         uint32_t, uint32_t, uint32_t);
+         return 0;
+     case 0xd40: /* PFR0.  */
-+/* Function prototype for gen_ functions for calling Neon helpers */
++        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
-+typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
++            goto bad_offset;
-+typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
++        }
-+typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
+         return cpu->isar.id_pfr0;
-+typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
+     case 0xd44: /* PFR1.  */
-+typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
++        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
-+typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
++            goto bad_offset;
-+typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
++        }
-+typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
+         return cpu->isar.id_pfr1;
-+typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
+     case 0xd48: /* DFR0.  */
-+typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
++        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
-+typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
++            goto bad_offset;
-+typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
++        }
-+typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
+         return cpu->isar.id_dfr0;
-+typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
+     case 0xd4c: /* AFR0.  */
-+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
++        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
-+
++            goto bad_offset;
- #endif /* TARGET_ARM_TRANSLATE_H */
++        }
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+         return cpu->id_afr0;
-index XXXXXXX..XXXXXXX 100644
+     case 0xd50: /* MMFR0.  */
---- a/target/arm/translate-a64.c
++        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
-+++ b/target/arm/translate-a64.c
++            goto bad_offset;
-@@ -XXX,XX +XXX,XX @@ typedef struct AArch64DecodeTable {
++        }
-     AArch64DecodeFn *disas_fn;
+         return cpu->isar.id_mmfr0;
- } AArch64DecodeTable;
+     case 0xd54: /* MMFR1.  */
++        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
--/* Function prototype for gen_ functions for calling Neon helpers */
++            goto bad_offset;
--typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
++        }
--typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
+         return cpu->isar.id_mmfr1;
--typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
+     case 0xd58: /* MMFR2.  */
--typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
++        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
--typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
++            goto bad_offset;
--typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
++        }
--typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
+         return cpu->isar.id_mmfr2;
--typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
+     case 0xd5c: /* MMFR3.  */
--typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
++        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
--typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
++            goto bad_offset;
--typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
++        }
--typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
+         return cpu->isar.id_mmfr3;
--typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
+     case 0xd60: /* ISAR0.  */
--typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
++        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
--typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
++            goto bad_offset;
--
++        }
- /* initialize TCG globals.  */
+         return cpu->isar.id_isar0;
- void a64_translate_init(void)
+     case 0xd64: /* ISAR1.  */
- {
++        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
 +            goto bad_offset;
 +        }
          return cpu->isar.id_isar1;
      case 0xd68: /* ISAR2.  */
 +        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
 +            goto bad_offset;
 +        }
          return cpu->isar.id_isar2;
      case 0xd6c: /* ISAR3.  */
 +        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
 +            goto bad_offset;
 +        }
          return cpu->isar.id_isar3;
      case 0xd70: /* ISAR4.  */
 +        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
 +            goto bad_offset;
 +        }
          return cpu->isar.id_isar4;
      case 0xd74: /* ISAR5.  */
 +        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
 +            goto bad_offset;
 +        }
          return cpu->isar.id_isar5;
      case 0xd78: /* CLIDR */
          return cpu->clidr;
 --
 .20.1

-[PULL 31/39] target/arm: Convert Neon 'load single structure to all lanes' to decodetree
+[PULL 04/18] target/arm: Add ID register values for Cortex-M0
-Convert the Neon "load single structure to all lanes" insns to
+Give the Cortex-M0 ID register values corresponding to its
-decodetree.
+implemented behaviour.  These will not be guest-visible but will be
 used to govern the behaviour of QEMU's emulation.  We use the same
 values that the Cortex-M3 does.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-13-peter.maydell@linaro.org
+Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
 ---
- target/arm/neon-ls.decode       |  5 +++
+ target/arm/cpu_tcg.c | 24 ++++++++++++++++++++++++
- target/arm/translate-neon.inc.c | 73 +++++++++++++++++++++++++++++++++
+file changed, 24 insertions(+)
  target/arm/translate.c          | 55 +------------------------
 files changed, 80 insertions(+), 53 deletions(-)
-diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
+diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-ls.decode
+--- a/target/arm/cpu_tcg.c
-+++ b/target/arm/neon-ls.decode
++++ b/target/arm/cpu_tcg.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void cortex_m0_initfn(Object *obj)
+     set_feature(&cpu->env, ARM_FEATURE_M);
- VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
-                vd=%vd_dp
+     cpu->midr = 0x410cc200;
 +
 +# Neon load single element to all lanes
 +
 +VLD_all_lanes  1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
 +               vd=%vd_dp
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
      gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
      return true;
  }
 +
 +static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
 +{
 +    /* Neon load single structure to all lanes */
 +    int reg, stride, vec_size;
 +    int vd = a->vd;
 +    int size = a->size;
 +    int nregs = a->n + 1;
 +    TCGv_i32 addr, tmp;
 +
 +    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 +        return false;
 +    }
 +
 +    /* UNDEF accesses to D16-D31 if they don't exist */
 +    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
 +        return false;
 +    }
 +
 +    if (size == 3) {
 +        if (nregs != 4 || a->a == 0) {
 +            return false;
 +        }
 +        /* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */
 +        size = 2;
 +    }
 +    if (nregs == 1 && a->a == 1 && size == 0) {
 +        return false;
 +    }
 +    if (nregs == 3 && a->a == 1) {
 +        return false;
 +    }
 +
 +    if (!vfp_access_check(s)) {
 +        return true;
 +    }
 +
 +    /*
-+     * VLD1 to all lanes: T bit indicates how many Dregs to write.
++     * These ID register values are not guest visible, because
-+     * VLD2/3/4 to all lanes: T bit indicates register stride.
++     * we do not implement the Main Extension. They must be set
 +     * to values corresponding to the Cortex-M0's implemented
 +     * features, because QEMU generally controls its emulation
 +     * by looking at ID register fields. We use the same values as
 +     * for the M3.
 +     */
-+    stride = a->t ? 2 : 1;
++    cpu->isar.id_pfr0 = 0x00000030;
-+    vec_size = nregs == 1 ? stride * 8 : 8;
++    cpu->isar.id_pfr1 = 0x00000200;
-+
++    cpu->isar.id_dfr0 = 0x00100000;
-+    tmp = tcg_temp_new_i32();
++    cpu->id_afr0 = 0x00000000;
-+    addr = tcg_temp_new_i32();
++    cpu->isar.id_mmfr0 = 0x00000030;
-+    load_reg_var(s, addr, a->rn);
++    cpu->isar.id_mmfr1 = 0x00000000;
-+    for (reg = 0; reg < nregs; reg++) {
++    cpu->isar.id_mmfr2 = 0x00000000;
-+        gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
++    cpu->isar.id_mmfr3 = 0x00000000;
-+                        s->be_data | size);
++    cpu->isar.id_isar0 = 0x01141110;
-+        if ((vd & 1) && vec_size == 16) {
++    cpu->isar.id_isar1 = 0x02111000;
-+            /*
++    cpu->isar.id_isar2 = 0x21112231;
-+             * We cannot write 16 bytes at once because the
++    cpu->isar.id_isar3 = 0x01111110;
-+             * destination is unaligned.
++    cpu->isar.id_isar4 = 0x01310102;
-+             */
++    cpu->isar.id_isar5 = 0x00000000;
-+            tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
++    cpu->isar.id_isar6 = 0x00000000;
-+                                 8, 8, tmp);
+ }
-+            tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0),
-+                             neon_reg_offset(vd, 0), 8, 8);
+ static void cortex_m3_initfn(Object *obj)
 +        } else {
 +            tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0),
 +                                 vec_size, vec_size, tmp);
 +        }
 +        tcg_gen_addi_i32(addr, addr, 1 << size);
 +        vd += stride;
 +    }
 +    tcg_temp_free_i32(tmp);
 +    tcg_temp_free_i32(addr);
 +
 +    gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << size) * nregs);
 +
 +    return true;
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
      int size;
      int reg;
      int load;
 -    int vec_size;
      TCGv_i32 addr;
      TCGv_i32 tmp;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
      } else {
          size = (insn >> 10) & 3;
          if (size == 3) {
 -            /* Load single element to all lanes.  */
 -            int a = (insn >> 4) & 1;
 -            if (!load) {
 -                return 1;
 -            }
 -            size = (insn >> 6) & 3;
 -            nregs = ((insn >> 8) & 3) + 1;
 -
 -            if (size == 3) {
 -                if (nregs != 4 || a == 0) {
 -                    return 1;
 -                }
 -                /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
 -                size = 2;
 -            }
 -            if (nregs == 1 && a == 1 && size == 0) {
 -                return 1;
 -            }
 -            if (nregs == 3 && a == 1) {
 -                return 1;
 -            }
 -            addr = tcg_temp_new_i32();
 -            load_reg_var(s, addr, rn);
 -
 -            /* VLD1 to all lanes: bit 5 indicates how many Dregs to write.
 -             * VLD2/3/4 to all lanes: bit 5 indicates register stride.
 -             */
 -            stride = (insn & (1 << 5)) ? 2 : 1;
 -            vec_size = nregs == 1 ? stride * 8 : 8;
 -
 -            tmp = tcg_temp_new_i32();
 -            for (reg = 0; reg < nregs; reg++) {
 -                gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
 -                                s->be_data | size);
 -                if ((rd & 1) && vec_size == 16) {
 -                    /* We cannot write 16 bytes at once because the
 -                     * destination is unaligned.
 -                     */
 -                    tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0),
 -                                         8, 8, tmp);
 -                    tcg_gen_gvec_mov(0, neon_reg_offset(rd + 1, 0),
 -                                     neon_reg_offset(rd, 0), 8, 8);
 -                } else {
 -                    tcg_gen_gvec_dup_i32(size, neon_reg_offset(rd, 0),
 -                                         vec_size, vec_size, tmp);
 -                }
 -                tcg_gen_addi_i32(addr, addr, 1 << size);
 -                rd += stride;
 -            }
 -            tcg_temp_free_i32(tmp);
 -            tcg_temp_free_i32(addr);
 -            stride = (1 << size) * nregs;
 +            /* Load single element to all lanes -- handled by decodetree  */
 +            return 1;
          } else {
              /* Single element.  */
              int idx = (insn >> 4) & 0xf;
 --
 .20.1

-[PULL 03/39] target/arm: Don't use a TLB for ARMMMUIdx_Stage2
+[PULL 05/18] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
-We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU
+The M-profile definition of the MVFR1 ID register differs slightly
-TLB.  However we never actually use the TLB -- all stage 2 lookups
+from the A-profile one, and in particular the check for "does the CPU
-are done by direct calls to get_phys_addr_lpae() followed by a
+support fp16 arithmetic" is not the same.
 physical address load via address_space_ld*().
-Remove Stage2 from the list of ARM MMU indexes which correspond to
+We don't currently implement any M-profile CPUs with fp16 arithmetic,
-real core MMU indexes, and instead put it in the set of "NOTLB" ARM
+so this is not yet a visible bug, but correcting the logic now
-MMU indexes.
+disarms this beartrap for when we eventually do.
 This allows us to drop NB_MMU_MODES to 11.  It also means we can
 safely add support for the ARMv8.3-TTS2UXN extension, which adds
 permission bits to the stage 2 descriptors which define execute
 permission separatel for EL0 and EL1; supporting that while keeping
 Stage2 in a QEMU TLB would require us to use separate TLBs for
 "Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a
 lot of extra complication given we aren't even using the QEMU TLB.
 In the process of updating the comment on our MMU index use,
 fix a couple of other minor errors:
  * NS EL2 EL2&0 was missing from the list in the comment
  * some text hadn't been updated from when we bumped NB_MMU_MODES
    above 8
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200330210400.11724-2-peter.maydell@linaro.org
+Message-id: 20200910173855.4068-6-peter.maydell@linaro.org
 ---
- target/arm/cpu-param.h |   2 +-
+ target/arm/cpu.h | 31 ++++++++++++++++++++++++++-----
- target/arm/cpu.h       |  21 +++++---
+file changed, 26 insertions(+), 5 deletions(-)
  target/arm/helper.c    | 112 ++++-------------------------------------
 files changed, 27 insertions(+), 108 deletions(-)
-diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu-param.h
-+++ b/target/arm/cpu-param.h
-@@ -XXX,XX +XXX,XX @@
- # define TARGET_PAGE_BITS_MIN  10
- #endif
--#define NB_MMU_MODES 12
-+#define NB_MMU_MODES 11
- #endif
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
+@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
-  *     handling via the TLB. The only way to do a stage 1 translation without
+ FIELD(ID_MMFR4, CCIDX, 24, 4)
-  *     the immediate stage 2 translation is via the ATS or AT system insns,
+ FIELD(ID_MMFR4, EVT, 28, 4)
-  *     which can be slow-pathed and always do a page table walk.
-+ *     The only use of stage 2 translations is either as part of an s1+2
++FIELD(ID_PFR1, PROGMOD, 0, 4)
-+ *     lookup or when loading the descriptors during a stage 1 page table walk,
++FIELD(ID_PFR1, SECURITY, 4, 4)
-+ *     and in both those cases we don't use the TLB.
++FIELD(ID_PFR1, MPROGMOD, 8, 4)
-  *  4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
++FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
-  *     translation regimes, because they map reasonably well to each other
++FIELD(ID_PFR1, GENTIMER, 16, 4)
-  *     and they can't both be active at the same time.
++FIELD(ID_PFR1, SEC_FRAC, 20, 4)
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
++FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
-  * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
++FIELD(ID_PFR1, GIC, 28, 4)
-  * NS EL1 EL1&0 stage 1+2 +PAN
++
-  * NS EL0 EL2&0
+ FIELD(ID_AA64ISAR0, AES, 4, 4)
-+ * NS EL2 EL2&0
+ FIELD(ID_AA64ISAR0, SHA1, 8, 4)
-  * NS EL2 EL2&0 +PAN
+ FIELD(ID_AA64ISAR0, SHA2, 12, 4)
-  * NS EL2 (aka NS PL2)
+@@ -XXX,XX +XXX,XX @@ FIELD(MVFR0, FPROUND, 28, 4)
-  * S EL0 EL1&0 (aka S PL0)
-  * S EL1 EL1&0 (not used if EL3 is 32 bit)
+ FIELD(MVFR1, FPFTZ, 0, 4)
-  * S EL1 EL1&0 +PAN
+ FIELD(MVFR1, FPDNAN, 4, 4)
-  * S EL3 (aka S PL1)
+-FIELD(MVFR1, SIMDLS, 8, 4)
-- * NS EL1&0 stage 2
+-FIELD(MVFR1, SIMDINT, 12, 4)
-  *
+-FIELD(MVFR1, SIMDSP, 16, 4)
-- * for a total of 12 different mmu_idx.
+-FIELD(MVFR1, SIMDHP, 20, 4)
-+ * for a total of 11 different mmu_idx.
++FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
-  *
++FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
-  * R profile CPUs have an MPU, but can use the same set of MMU indexes
++FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
-  * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
++FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
++FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
-  * are not quite the same -- different CPU types (most notably M profile
++FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
-  * vs A/R profile) would like to use MMU indexes with different semantics,
+ FIELD(MVFR1, FPHP, 24, 4)
-  * but since we don't ever need to use all of those in a single CPU we
+ FIELD(MVFR1, SIMDFMAC, 28, 4)
-- * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
-+ * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
+@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
-+ * modes + total number of M profile MMU modes". The lower bits of
+     return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
   * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
   * the same for any particular CPU.
   * Variables of type ARMMUIdx are always full values, and the core
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
      ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
      ARMMMUIdx_SE3        = 10 | ARM_MMU_IDX_A,
 -    ARMMMUIdx_Stage2     = 11 | ARM_MMU_IDX_A,
 -
      /*
       * These are not allocated TLBs and are used only for AT system
       * instructions or for the first stage of an S12 page table walk.
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
      ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
      ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
      ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
 +    /*
 +     * Not allocated a TLB: used only for second stage of an S12 page
 +     * table walk, or for descriptor loads during first stage of an S1
 +     * page table walk. Note that if we ever want to have a TLB for this
 +     * then various TLB flush insns which currently are no-ops or flush
 +     * only stage 1 MMU indexes will need to change to flush stage 2.
 +     */
 +    ARMMMUIdx_Stage2     = 3 | ARM_MMU_IDX_NOTLB,
      /*
       * M-profile.
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
      TO_CORE_BIT(SE10_1),
      TO_CORE_BIT(SE10_1_PAN),
      TO_CORE_BIT(SE3),
 -    TO_CORE_BIT(Stage2),
      TO_CORE_BIT(MUser),
      TO_CORE_BIT(MPriv),
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
      tlb_flush_by_mmuidx(cs,
                          ARMMMUIdxBit_E10_1 |
                          ARMMMUIdxBit_E10_1_PAN |
 -                        ARMMMUIdxBit_E10_0 |
 -                        ARMMMUIdxBit_Stage2);
 +                        ARMMMUIdxBit_E10_0);
  }
- static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
++static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
-@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
++{
-     tlb_flush_by_mmuidx_all_cpus_synced(cs,
++    return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
-                                         ARMMMUIdxBit_E10_1 |
++}
-                                         ARMMMUIdxBit_E10_1_PAN |
++
--                                        ARMMMUIdxBit_E10_0 |
+ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
--                                        ARMMMUIdxBit_Stage2);
+ {
-+                                        ARMMMUIdxBit_E10_0);
+-    return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
 +    /* Sadly this is encoded differently for A-profile and M-profile */
 +    if (isar_feature_aa32_mprofile(id)) {
 +        return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
 +    } else {
 +        return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
 +    }
  }
--static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
 -                            uint64_t value)
 -{
 -    /* Invalidate by IPA. This has to invalidate any structures that
 -     * contain only stage 2 translation information, but does not need
 -     * to apply to structures that contain combined stage 1 and stage 2
 -     * translation information.
 -     * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
 -     */
 -    CPUState *cs = env_cpu(env);
 -    uint64_t pageaddr;
 -
 -    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
 -        return;
 -    }
 -
 -    pageaddr = sextract64(value << 12, 0, 40);
 -
 -    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
 -}
 -
 -static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 -                               uint64_t value)
 -{
 -    CPUState *cs = env_cpu(env);
 -    uint64_t pageaddr;
 -
 -    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
 -        return;
 -    }
 -
 -    pageaddr = sextract64(value << 12, 0, 40);
 -
 -    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
 -                                             ARMMMUIdxBit_Stage2);
 -}
  static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                uint64_t value)
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
          tlb_flush_by_mmuidx(cs,
                              ARMMMUIdxBit_E10_1 |
                              ARMMMUIdxBit_E10_1_PAN |
 -                            ARMMMUIdxBit_E10_0 |
 -                            ARMMMUIdxBit_Stage2);
 +                            ARMMMUIdxBit_E10_0);
          raw_write(env, ri, value);
      }
  }
@@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env)
          return ARMMMUIdxBit_SE10_1 |
                 ARMMMUIdxBit_SE10_1_PAN |
                 ARMMMUIdxBit_SE10_0;
 -    } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 -        return ARMMMUIdxBit_E10_1 |
 -               ARMMMUIdxBit_E10_1_PAN |
 -               ARMMMUIdxBit_E10_0 |
 -               ARMMMUIdxBit_Stage2;
      } else {
          return ARMMMUIdxBit_E10_1 |
                 ARMMMUIdxBit_E10_1_PAN |
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                               ARMMMUIdxBit_SE3);
  }
 -static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
 -                                    uint64_t value)
 -{
 -    /* Invalidate by IPA. This has to invalidate any structures that
 -     * contain only stage 2 translation information, but does not need
 -     * to apply to structures that contain combined stage 1 and stage 2
 -     * translation information.
 -     * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
 -     */
 -    ARMCPU *cpu = env_archcpu(env);
 -    CPUState *cs = CPU(cpu);
 -    uint64_t pageaddr;
 -
 -    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
 -        return;
 -    }
 -
 -    pageaddr = sextract64(value << 12, 0, 48);
 -
 -    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
 -}
 -
 -static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 -                                      uint64_t value)
 -{
 -    CPUState *cs = env_cpu(env);
 -    uint64_t pageaddr;
 -
 -    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
 -        return;
 -    }
 -
 -    pageaddr = sextract64(value << 12, 0, 48);
 -
 -    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
 -                                             ARMMMUIdxBit_Stage2);
 -}
 -
  static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                        bool isread)
  {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .writefn = tlbi_aa64_vae1_write },
      { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 -      .writefn = tlbi_aa64_ipas2e1is_write },
 +      .access = PL2_W, .type = ARM_CP_NOP },
      { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 -      .writefn = tlbi_aa64_ipas2e1is_write },
 +      .access = PL2_W, .type = ARM_CP_NOP },
      { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
        .access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .writefn = tlbi_aa64_alle1is_write },
      { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 -      .writefn = tlbi_aa64_ipas2e1_write },
 +      .access = PL2_W, .type = ARM_CP_NOP },
      { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
 -      .access = PL2_W, .type = ARM_CP_NO_RAW,
 -      .writefn = tlbi_aa64_ipas2e1_write },
 +      .access = PL2_W, .type = ARM_CP_NOP },
      { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
        .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
        .access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
        .writefn = tlbimva_hyp_is_write },
      { .name = "TLBIIPAS2",
        .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 -      .writefn = tlbiipas2_write },
 +      .type = ARM_CP_NOP, .access = PL2_W },
      { .name = "TLBIIPAS2IS",
        .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 -      .writefn = tlbiipas2_is_write },
 +      .type = ARM_CP_NOP, .access = PL2_W },
      { .name = "TLBIIPAS2L",
        .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 -      .writefn = tlbiipas2_write },
 +      .type = ARM_CP_NOP, .access = PL2_W },
      { .name = "TLBIIPAS2LIS",
        .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
 -      .type = ARM_CP_NO_RAW, .access = PL2_W,
 -      .writefn = tlbiipas2_is_write },
 +      .type = ARM_CP_NOP, .access = PL2_W },
      /* 32 bit cache operations */
      { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
        .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
 --
 .20.1

-[PULL 16/39] hw/arm: versal: Add support for SD
+[PULL 06/18] target/arm: Fix sve ldr/str
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Richard Henderson <richard.henderson@linaro.org>
-Add support for SD.
+The mte update missed a bit when producing clean addresses.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Fixes: b2aa8879b88
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Message-id: 20200916014102.2446323-1-richard.henderson@linaro.org
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20200427181649.26851-9-edgar.iglesias@gmail.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/xlnx-versal.h | 12 ++++++++++++
+ target/arm/translate-sve.c | 4 ++--
- hw/arm/xlnx-versal.c         | 31 +++++++++++++++++++++++++++++++
+file changed, 2 insertions(+), 2 deletions(-)
 files changed, 43 insertions(+)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
+--- a/target/arm/translate-sve.c
-+++ b/include/hw/arm/xlnx-versal.h
++++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
+         for (i = 0; i < len_align; i += 8) {
- #include "hw/sysbus.h"
+             tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ);
- #include "hw/arm/boot.h"
+             tcg_gen_st_i64(t0, cpu_env, vofs + i);
-+#include "hw/sd/sdhci.h"
+-            tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
- #include "hw/intc/arm_gicv3.h"
++            tcg_gen_addi_i64(clean_addr, clean_addr, 8);
- #include "hw/char/pl011.h"
+         }
- #include "hw/dma/xlnx-zdma.h"
+         tcg_temp_free_i64(t0);
-@@ -XXX,XX +XXX,XX @@
+     } else {
- #define XLNX_VERSAL_NR_UARTS   2
+@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
- #define XLNX_VERSAL_NR_GEMS    2
+         for (i = 0; i < len_align; i += 8) {
- #define XLNX_VERSAL_NR_ADMAS   8
+             tcg_gen_ld_i64(t0, cpu_env, vofs + i);
-+#define XLNX_VERSAL_NR_SDS     2
+             tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ);
- #define XLNX_VERSAL_NR_IRQS    192
+-            tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
++            tcg_gen_addi_i64(clean_addr, clean_addr, 8);
- typedef struct Versal {
+         }
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
+         tcg_temp_free_i64(t0);
-         } iou;
+     } else {
      } lpd;
 +    /* The Platform Management Controller subsystem.  */
 +    struct {
 +        struct {
 +            SDHCIState sd[XLNX_VERSAL_NR_SDS];
 +        } iou;
 +    } pmc;
 +
      struct {
          MemoryRegion *mr_ddr;
          uint32_t psci_conduit;
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
  #define VERSAL_GEM1_IRQ_0          58
  #define VERSAL_GEM1_WAKE_IRQ_0     59
  #define VERSAL_ADMA_IRQ_0          60
 +#define VERSAL_SD0_IRQ_0           126
  /* Architecturally reserved IRQs suitable for virtualization.  */
  #define VERSAL_RSVD_IRQ_FIRST 111
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
  #define MM_FPD_CRF                  0xfd1a0000U
  #define MM_FPD_CRF_SIZE             0x140000
 +#define MM_PMC_SD0                  0xf1040000U
 +#define MM_PMC_SD0_SIZE             0x10000
  #define MM_PMC_CRP                  0xf1260000U
  #define MM_PMC_CRP_SIZE             0x10000
  #endif
 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal.c
 +++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
      }
  }
 +#define SDHCI_CAPABILITIES  0x280737ec6481 /* Same as on ZynqMP.  */
 +static void versal_create_sds(Versal *s, qemu_irq *pic)
 +{
 +    int i;
 +
 +    for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) {
 +        DeviceState *dev;
 +        MemoryRegion *mr;
 +
 +        sysbus_init_child_obj(OBJECT(s), "sd[*]",
 +                              &s->pmc.iou.sd[i], sizeof(s->pmc.iou.sd[i]),
 +                              TYPE_SYSBUS_SDHCI);
 +        dev = DEVICE(&s->pmc.iou.sd[i]);
 +
 +        object_property_set_uint(OBJECT(dev),
 +                                 3, "sd-spec-version", &error_fatal);
 +        object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg",
 +                                 &error_fatal);
 +        object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal);
 +        qdev_init_nofail(dev);
 +
 +        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
 +        memory_region_add_subregion(&s->mr_ps,
 +                                    MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr);
 +
 +        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
 +                           pic[VERSAL_SD0_IRQ_0 + i * 2]);
 +    }
 +}
 +
  /* This takes the board allocated linear DDR memory and creates aliases
   * for each split DDR range/aperture on the Versal address map.
   */
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
      versal_create_uarts(s, pic);
      versal_create_gems(s, pic);
      versal_create_admas(s, pic);
 +    versal_create_sds(s, pic);
      versal_map_ddr(s);
      versal_unimp(s);
 --
 .20.1

-[PULL 01/39] target/arm: Make VQDMULL undefined when U=1
+[PULL 07/18] target/arm: Fix SVE splice
-From: Fredrik Strupe <fredrik@strupe.net>
+From: Richard Henderson <richard.henderson@linaro.org>
-According to Arm ARM, VQDMULL is only valid when U=0, while having
+While converting to gen_gvec_ool_zzzp, we lost passing
-U=1 is unallocated.
+a->esz as the data argument to the function.
-Signed-off-by: Fredrik Strupe <fredrik@strupe.net>
+Fixes: 36cbb7a8e71
-Fixes: 695272dcb976 ("target-arm: Handle UNDEF cases for Neon 3-regs-different-widths")
+Cc: qemu-stable@nongnu.org
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20200918000500.2690937-1-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.c | 2 +-
+ target/arm/translate-sve.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/target/arm/translate-sve.c
-+++ b/target/arm/translate.c
++++ b/target/arm/translate-sve.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
-                     {0, 0, 0, 0}, /* VMLSL */
+ {
-                     {0, 0, 0, 9}, /* VQDMLSL */
+     if (sve_access_check(s)) {
-                     {0, 0, 0, 0}, /* Integer VMULL */
+         gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
--                    {0, 0, 0, 1}, /* VQDMULL */
+-                          a->rd, a->rn, a->rm, a->pg, 0);
-+                    {0, 0, 0, 9}, /* VQDMULL */
++                          a->rd, a->rn, a->rm, a->pg, a->esz);
-                     {0, 0, 0, 0xa}, /* Polynomial VMULL */
+     }
-                     {0, 0, 0, 7}, /* Reserved: always UNDEF */
+     return true;
-                 };
+ }
 --
 .20.1

-[PULL 32/39] target/arm: Convert Neon 'load/store single structure' to decodetree
+[PULL 08/18] hw/arm/raspi: Define various blocks base addresses
-Convert the Neon "load/store single structure to one lane" insns to
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
 decodetree.
-As this is the last set of insns in the neon load/store group,
+The Raspberry firmware is closed-source. While running it, it
-we can remove the whole disas_neon_ls_insn() function.
+accesses various I/O registers. Logging these accesses as UNIMP
 (unimplemented) help to understand what the firmware is doing
 (ideally we want it able to boot a Linux kernel).
+Document various blocks we might use later.
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Luc Michel <luc.michel@greensocs.com>
+Message-id: 20200921034729.432931-2-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-14-peter.maydell@linaro.org
 ---
- target/arm/neon-ls.decode       |  11 +++
+ include/hw/arm/raspi_platform.h | 51 +++++++++++++++++++++++++++------
- target/arm/translate-neon.inc.c |  89 +++++++++++++++++++
+file changed, 43 insertions(+), 8 deletions(-)
  target/arm/translate.c          | 147 --------------------------------
 files changed, 100 insertions(+), 147 deletions(-)
-diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
+diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-ls.decode
+--- a/include/hw/arm/raspi_platform.h
-+++ b/target/arm/neon-ls.decode
++++ b/include/hw/arm/raspi_platform.h
@@ -XXX,XX +XXX,XX @@ VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
  VLD_all_lanes  1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
                 vd=%vd_dp
 +
 +# Neon load/store single structure to one lane
 +%imm1_5_p1 5:1 !function=plus1
 +%imm1_6_p1 6:1 !function=plus1
 +
 +VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
 +               vd=%vd_dp size=0 stride=1
 +VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \
 +               vd=%vd_dp size=1 stride=%imm1_5_p1
 +VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \
 +               vd=%vd_dp size=2 stride=%imm1_6_p1
 diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-neon.inc.c
 +++ b/target/arm/translate-neon.inc.c
 @@ -XXX,XX +XXX,XX @@
-  * It might be possible to convert it to a standalone .c file eventually.
+  * You should have received a copy of the GNU General Public License
   * along with this program; if not, write to the Free Software
   * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 + *
 + * Various undocumented addresses and names come from Herman Hermitage's VC4
 + * documentation:
 + * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map
   */
-+static inline int plus1(DisasContext *s, int x)
+ #ifndef HW_ARM_RASPI_PLATFORM_H
-+{
+ #define HW_ARM_RASPI_PLATFORM_H
-+    return x + 1;
-+}
+ #define MSYNC_OFFSET            0x0000   /* Multicore Sync Block */
-+
+-#define IC0_OFFSET              0x2000
- /* Include the generated Neon decoder */
++#define CCPT_OFFSET             0x1000   /* Compact Camera Port 2 TX */
- #include "decode-neon-dp.inc.c"
++#define INTE_OFFSET             0x2000   /* VC Interrupt controller */
- #include "decode-neon-ls.inc.c"
+ #define ST_OFFSET               0x3000   /* System Timer */
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
++#define TXP_OFFSET              0x4000   /* Transposer */
++#define JPEG_OFFSET             0x5000
-     return true;
+ #define MPHI_OFFSET             0x6000   /* Message-based Parallel Host Intf. */
- }
+ #define DMA_OFFSET              0x7000   /* DMA controller, channels 0-14 */
-+
+-#define ARM_OFFSET              0xB000   /* BCM2708 ARM control block */
-+static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
++#define ARBA_OFFSET             0x9000
-+{
++#define BRDG_OFFSET             0xa000
-+    /* Neon load/store single structure to one lane */
++#define ARM_OFFSET              0xB000   /* ARM control block */
-+    int reg;
+ #define ARMCTRL_OFFSET          (ARM_OFFSET + 0x000)
-+    int nregs = a->n + 1;
+ #define ARMCTRL_IC_OFFSET       (ARM_OFFSET + 0x200) /* Interrupt controller */
-+    int vd = a->vd;
+-#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
-+    TCGv_i32 addr, tmp;
++#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
-+
+ #define ARMCTRL_0_SBM_OFFSET    (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+                                                       * Doorbells & Mailboxes */
-+        return false;
+ #define CPRMAN_OFFSET           0x100000 /* Power Management, Watchdog */
-+    }
+@@ -XXX,XX +XXX,XX @@
-+
+ #define AVS_OFFSET              0x103000 /* Audio Video Standard */
-+    /* UNDEF accesses to D16-D31 if they don't exist */
+ #define RNG_OFFSET              0x104000
-+    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ #define GPIO_OFFSET             0x200000
-+        return false;
+-#define UART0_OFFSET            0x201000
-+    }
+-#define MMCI0_OFFSET            0x202000
-+
+-#define I2S_OFFSET              0x203000
-+    /* Catch the UNDEF cases. This is unavoidably a bit messy. */
+-#define SPI0_OFFSET             0x204000
-+    switch (nregs) {
++#define UART0_OFFSET            0x201000 /* PL011 */
-+    case 1:
++#define MMCI0_OFFSET            0x202000 /* Legacy MMC */
-+        if (((a->align & (1 << a->size)) != 0) ||
++#define I2S_OFFSET              0x203000 /* PCM */
-+            (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
++#define SPI0_OFFSET             0x204000 /* SPI master */
-+            return false;
+ #define BSC0_OFFSET             0x205000 /* BSC0 I2C/TWI */
-+        }
++#define PIXV0_OFFSET            0x206000
-+        break;
++#define PIXV1_OFFSET            0x207000
-+    case 3:
++#define DPI_OFFSET              0x208000
-+        if ((a->align & 1) != 0) {
++#define DSI0_OFFSET             0x209000 /* Display Serial Interface */
-+            return false;
++#define PWM_OFFSET              0x20c000
-+        }
++#define PERM_OFFSET             0x20d000
-+        /* fall through */
++#define TEC_OFFSET              0x20e000
-+    case 2:
+ #define OTP_OFFSET              0x20f000
-+        if (a->size == 2 && (a->align & 2) != 0) {
++#define SLIM_OFFSET             0x210000 /* SLIMbus */
-+            return false;
++#define CPG_OFFSET              0x211000
-+        }
+ #define THERMAL_OFFSET          0x212000
-+        break;
+-#define BSC_SL_OFFSET           0x214000 /* SPI slave */
-+    case 4:
++#define AVSP_OFFSET             0x213000
-+        if ((a->size == 2) && ((a->align & 3) == 3)) {
++#define BSC_SL_OFFSET           0x214000 /* SPI slave (bootrom) */
-+            return false;
+ #define AUX_OFFSET              0x215000 /* AUX: UART1/SPI1/SPI2 */
-+        }
+ #define EMMC1_OFFSET            0x300000
-+        break;
++#define EMMC2_OFFSET            0x340000
-+    default:
++#define HVS_OFFSET              0x400000
-+        abort();
+ #define SMI_OFFSET              0x600000
-+    }
++#define DSI1_OFFSET             0x700000
-+    if ((vd + a->stride * (nregs - 1)) > 31) {
++#define UCAM_OFFSET             0x800000
-+        /*
++#define CMI_OFFSET              0x802000
-+         * Attempts to write off the end of the register file are
+ #define BSC1_OFFSET             0x804000 /* BSC1 I2C/TWI */
-+         * UNPREDICTABLE; we choose to UNDEF because otherwise we would
+ #define BSC2_OFFSET             0x805000 /* BSC2 I2C/TWI */
-+         * access off the end of the array that holds the register data.
++#define VECA_OFFSET             0x806000
-+         */
++#define PIXV2_OFFSET            0x807000
-+        return false;
++#define HDMI_OFFSET             0x808000
-+    }
++#define HDCP_OFFSET             0x809000
-+
++#define ARBR0_OFFSET            0x80a000
-+    if (!vfp_access_check(s)) {
+ #define DBUS_OFFSET             0x900000
-+        return true;
+ #define AVE0_OFFSET             0x910000
-+    }
+ #define USB_OTG_OFFSET          0x980000 /* DTC_OTG USB controller */
-+
++#define V3D_OFFSET              0xc00000
-+    tmp = tcg_temp_new_i32();
+ #define SDRAMC_OFFSET           0xe00000
-+    addr = tcg_temp_new_i32();
++#define L2CC_OFFSET             0xe01000 /* Level 2 Cache controller */
-+    load_reg_var(s, addr, a->rn);
++#define L1CC_OFFSET             0xe02000 /* Level 1 Cache controller */
-+    /*
++#define ARBR1_OFFSET            0xe04000
-+     * TODO: if we implemented alignment exceptions, we should check
+ #define DMA15_OFFSET            0xE05000 /* DMA controller, channel 15 */
-+     * addr against the alignment encoded in a->align here.
++#define DCRC_OFFSET             0xe07000
-+     */
++#define AXIP_OFFSET             0xe08000
-+    for (reg = 0; reg < nregs; reg++) {
-+        if (a->l) {
+ /* GPU interrupts */
-+            gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
+ #define INTERRUPT_TIMER0               0
 +                            s->be_data | a->size);
 +            neon_store_element(vd, a->reg_idx, a->size, tmp);
 +        } else { /* Store */
 +            neon_load_element(tmp, vd, a->reg_idx, a->size);
 +            gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
 +                            s->be_data | a->size);
 +        }
 +        vd += a->stride;
 +        tcg_gen_addi_i32(addr, addr, 1 << a->size);
 +    }
 +    tcg_temp_free_i32(addr);
 +    tcg_temp_free_i32(tmp);
 +
 +    gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs);
 +
 +    return true;
 +}
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
      tcg_temp_free_i32(rd);
  }
 -
 -/* Translate a NEON load/store element instruction.  Return nonzero if the
 -   instruction is invalid.  */
 -static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
 -{
 -    int rd, rn, rm;
 -    int nregs;
 -    int stride;
 -    int size;
 -    int reg;
 -    int load;
 -    TCGv_i32 addr;
 -    TCGv_i32 tmp;
 -
 -    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
 -        return 1;
 -    }
 -
 -    /* FIXME: this access check should not take precedence over UNDEF
 -     * for invalid encodings; we will generate incorrect syndrome information
 -     * for attempts to execute invalid vfp/neon encodings with FP disabled.
 -     */
 -    if (s->fp_excp_el) {
 -        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
 -                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
 -        return 0;
 -    }
 -
 -    if (!s->vfp_enabled)
 -      return 1;
 -    VFP_DREG_D(rd, insn);
 -    rn = (insn >> 16) & 0xf;
 -    rm = insn & 0xf;
 -    load = (insn & (1 << 21)) != 0;
 -    if ((insn & (1 << 23)) == 0) {
 -        /* Load store all elements -- handled already by decodetree */
 -        return 1;
 -    } else {
 -        size = (insn >> 10) & 3;
 -        if (size == 3) {
 -            /* Load single element to all lanes -- handled by decodetree  */
 -            return 1;
 -        } else {
 -            /* Single element.  */
 -            int idx = (insn >> 4) & 0xf;
 -            int reg_idx;
 -            switch (size) {
 -            case 0:
 -                reg_idx = (insn >> 5) & 7;
 -                stride = 1;
 -                break;
 -            case 1:
 -                reg_idx = (insn >> 6) & 3;
 -                stride = (insn & (1 << 5)) ? 2 : 1;
 -                break;
 -            case 2:
 -                reg_idx = (insn >> 7) & 1;
 -                stride = (insn & (1 << 6)) ? 2 : 1;
 -                break;
 -            default:
 -                abort();
 -            }
 -            nregs = ((insn >> 8) & 3) + 1;
 -            /* Catch the UNDEF cases. This is unavoidably a bit messy. */
 -            switch (nregs) {
 -            case 1:
 -                if (((idx & (1 << size)) != 0) ||
 -                    (size == 2 && ((idx & 3) == 1 || (idx & 3) == 2))) {
 -                    return 1;
 -                }
 -                break;
 -            case 3:
 -                if ((idx & 1) != 0) {
 -                    return 1;
 -                }
 -                /* fall through */
 -            case 2:
 -                if (size == 2 && (idx & 2) != 0) {
 -                    return 1;
 -                }
 -                break;
 -            case 4:
 -                if ((size == 2) && ((idx & 3) == 3)) {
 -                    return 1;
 -                }
 -                break;
 -            default:
 -                abort();
 -            }
 -            if ((rd + stride * (nregs - 1)) > 31) {
 -                /* Attempts to write off the end of the register file
 -                 * are UNPREDICTABLE; we choose to UNDEF because otherwise
 -                 * the neon_load_reg() would write off the end of the array.
 -                 */
 -                return 1;
 -            }
 -            tmp = tcg_temp_new_i32();
 -            addr = tcg_temp_new_i32();
 -            load_reg_var(s, addr, rn);
 -            for (reg = 0; reg < nregs; reg++) {
 -                if (load) {
 -                    gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
 -                                    s->be_data | size);
 -                    neon_store_element(rd, reg_idx, size, tmp);
 -                } else { /* Store */
 -                    neon_load_element(tmp, rd, reg_idx, size);
 -                    gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
 -                                    s->be_data | size);
 -                }
 -                rd += stride;
 -                tcg_gen_addi_i32(addr, addr, 1 << size);
 -            }
 -            tcg_temp_free_i32(addr);
 -            tcg_temp_free_i32(tmp);
 -            stride = nregs * (1 << size);
 -        }
 -    }
 -    if (rm != 15) {
 -        TCGv_i32 base;
 -
 -        base = load_reg(s, rn);
 -        if (rm == 13) {
 -            tcg_gen_addi_i32(base, base, stride);
 -        } else {
 -            TCGv_i32 index;
 -            index = load_reg(s, rm);
 -            tcg_gen_add_i32(base, base, index);
 -            tcg_temp_free_i32(index);
 -        }
 -        store_reg(s, rn, base);
 -    }
 -    return 0;
 -}
 -
  static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
  {
      switch (size) {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
              }
              return;
          }
 -        if ((insn & 0x0f100000) == 0x04000000) {
 -            /* NEON load/store.  */
 -            if (disas_neon_ls_insn(s, insn)) {
 -                goto illegal_op;
 -            }
 -            return;
 -        }
          if ((insn & 0x0e000f00) == 0x0c000100) {
              if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
                  /* iWMMXt register transfer.  */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
          }
          break;
      case 12:
 -        if ((insn & 0x01100000) == 0x01000000) {
 -            if (disas_neon_ls_insn(s, insn)) {
 -                goto illegal_op;
 -            }
 -            break;
 -        }
          goto illegal_op;
      default:
      illegal_op:
 --
 .20.1

-[PULL 09/39] hw/arm: versal: Remove inclusion of arm_gicv3_common.h
+[PULL 09/18] hw/arm/bcm2835: Add more unimplemented peripherals
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Remove inclusion of arm_gicv3_common.h, this already gets
+The bcm2835-v3d is used since Linux 4.7, see commit
-included via xlnx-versal.h.
+ac67e0c39c ("ARM: bcm2835: Add VC4 to the device tree"),
 and the bcm2835-txp since Linux 4.19, see commit
 b7dd29b401f5 ("ARM: dts: bcm283x: Add Transposer block").
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-2-edgar.iglesias@gmail.com
+Message-id: 20200921034729.432931-3-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/xlnx-versal.c | 1 -
+ include/hw/arm/bcm2835_peripherals.h | 2 ++
-file changed, 1 deletion(-)
+ hw/arm/bcm2835_peripherals.c         | 2 ++
 files changed, 4 insertions(+)
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
+diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal.c
+--- a/include/hw/arm/bcm2835_peripherals.h
-+++ b/hw/arm/xlnx-versal.c
++++ b/include/hw/arm/bcm2835_peripherals.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
- #include "hw/arm/boot.h"
- #include "kvm_arm.h"
+     BCM2835SystemTimerState systmr;
- #include "hw/misc/unimp.h"
+     BCM2835MphiState mphi;
--#include "hw/intc/arm_gicv3_common.h"
++    UnimplementedDeviceState txp;
- #include "hw/arm/xlnx-versal.h"
+     UnimplementedDeviceState armtmr;
- #include "hw/char/pl011.h"
+     UnimplementedDeviceState cprman;
      UnimplementedDeviceState a2w;
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
      UnimplementedDeviceState otp;
      UnimplementedDeviceState dbus;
      UnimplementedDeviceState ave0;
 +    UnimplementedDeviceState v3d;
      UnimplementedDeviceState bscsl;
      UnimplementedDeviceState smi;
      DWC2State dwc2;
 diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/bcm2835_peripherals.c
 +++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
          qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
                                 INTERRUPT_USB));
 +    create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
      create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
      create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
      create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
      create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
      create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
      create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
 +    create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000);
      create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);
  }
 --
 .20.1

-[PULL 14/39] hw/arm: versal: Embed the ADMAs into the SoC type
+[PULL 10/18] hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Embed the ADMAs into the SoC type.
+Commit 1c3db49d39 added the raspi3, which uses the same peripherals
 than the raspi2 (but with different ARM cores). The raspi3 was
 introduced without the ignore_memory_transaction_failures flag.
 Almost 2 years later, the machine is usable running U-Boot and
 Linux.
 In commit 00cbd5bd74 we mapped a lot of unimplemented devices,
 commit d442d95f added thermal block and commit 0e5bbd7406 the
 system timer.
 As we are happy with the raspi3, let's remove this flag on the
 raspi2.
-Suggested-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-7-edgar.iglesias@gmail.com
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200921034729.432931-4-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/xlnx-versal.h |  3 ++-
+ hw/arm/raspi.c | 3 ---
- hw/arm/xlnx-versal.c         | 14 +++++++-------
+file changed, 3 deletions(-)
 files changed, 9 insertions(+), 8 deletions(-)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
+--- a/hw/arm/raspi.c
-+++ b/include/hw/arm/xlnx-versal.h
++++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
- #include "hw/arm/boot.h"
+     mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
- #include "hw/intc/arm_gicv3.h"
+     mc->default_ram_size = board_ram_size(board_rev);
- #include "hw/char/pl011.h"
+     mc->default_ram_id = "ram";
-+#include "hw/dma/xlnx-zdma.h"
+-    if (board_version(board_rev) == 2) {
- #include "hw/net/cadence_gem.h"
+-        mc->ignore_memory_transaction_failures = true;
+-    }
- #define TYPE_XLNX_VERSAL "xlnx-versal"
+ };
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
-         struct {
+ static const TypeInfo raspi_machine_types[] = {
              PL011State uart[XLNX_VERSAL_NR_UARTS];
              CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
 -            SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
 +            XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];
          } iou;
      } lpd;
 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal.c
 +++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
          DeviceState *dev;
          MemoryRegion *mr;
 -        dev = qdev_create(NULL, "xlnx.zdma");
 -        s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev);
 -        object_property_set_int(OBJECT(s->lpd.iou.adma[i]), 128, "bus-width",
 -                                &error_abort);
 -        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
 +        sysbus_init_child_obj(OBJECT(s), name,
 +                              &s->lpd.iou.adma[i], sizeof(s->lpd.iou.adma[i]),
 +                              TYPE_XLNX_ZDMA);
 +        dev = DEVICE(&s->lpd.iou.adma[i]);
 +        object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort);
          qdev_init_nofail(dev);
 -        mr = sysbus_mmio_get_region(s->lpd.iou.adma[i], 0);
 +        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
          memory_region_add_subregion(&s->mr_ps,
                                      MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
 -        sysbus_connect_irq(s->lpd.iou.adma[i], 0, pic[VERSAL_ADMA_IRQ_0 + i]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]);
          g_free(name);
      }
  }
 --
 .20.1

-[PULL 13/39] hw/arm: versal: Embed the GEMs into the SoC type
+[PULL 11/18] hw/arm/raspi: Display the board revision in the machine description
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Embed the GEMs into the SoC type.
+Display the board revision in the machine description.
-Suggested-by: Peter Maydell <peter.maydell@linaro.org>
+Before:
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+  $ qemu-system-aarch64 -M help | fgrep raspi
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+  raspi2               Raspberry Pi 2B
   raspi3               Raspberry Pi 3B
 After:
   raspi2               Raspberry Pi 2B (revision 1.1)
   raspi3               Raspberry Pi 3B (revision 1.2)
 Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-6-edgar.iglesias@gmail.com
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200924111808.77168-2-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/xlnx-versal.h |  3 ++-
+ hw/arm/raspi.c | 4 +++-
- hw/arm/xlnx-versal.c         | 15 ++++++++-------
+file changed, 3 insertions(+), 1 deletion(-)
 files changed, 10 insertions(+), 8 deletions(-)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
+--- a/hw/arm/raspi.c
-+++ b/include/hw/arm/xlnx-versal.h
++++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
- #include "hw/arm/boot.h"
+     uint32_t board_rev = (uint32_t)(uintptr_t)data;
- #include "hw/intc/arm_gicv3.h"
- #include "hw/char/pl011.h"
+     rmc->board_rev = board_rev;
-+#include "hw/net/cadence_gem.h"
+-    mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev));
++    mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
- #define TYPE_XLNX_VERSAL "xlnx-versal"
++                               board_type(board_rev),
- #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
++                               FIELD_EX32(board_rev, REV_CODE, REVISION));
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
+     mc->init = raspi_machine_init;
+     mc->block_default_type = IF_SD;
-         struct {
+     mc->no_parallel = 1;
              PL011State uart[XLNX_VERSAL_NR_UARTS];
 -            SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
 +            CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
              SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
          } iou;
      } lpd;
 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal.c
 +++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
          DeviceState *dev;
          MemoryRegion *mr;
 -        dev = qdev_create(NULL, "cadence_gem");
 -        s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);
 -        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
 +        sysbus_init_child_obj(OBJECT(s), name,
 +                              &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]),
 +                              TYPE_CADENCE_GEM);
 +        dev = DEVICE(&s->lpd.iou.gem[i]);
          if (nd->used) {
              qemu_check_nic_model(nd, "cadence_gem");
              qdev_set_nic_properties(dev, nd);
          }
 -        object_property_set_int(OBJECT(s->lpd.iou.gem[i]),
 +        object_property_set_int(OBJECT(dev),
 , "num-priority-queues",
                                  &error_abort);
 -        object_property_set_link(OBJECT(s->lpd.iou.gem[i]),
 +        object_property_set_link(OBJECT(dev),
                                   OBJECT(&s->mr_ps), "dma",
                                   &error_abort);
          qdev_init_nofail(dev);
 -        mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);
 +        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
          memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
 -        sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
          g_free(name);
      }
  }
 --
 .20.1

-[PULL 11/39] hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal
+[PULL 12/18] hw/arm/raspi: Load the firmware on the first core
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Fix typo xlnx-ve -> xlnx-versal.
+The 'first_cpu' is more a QEMU accelerator-related concept
 than a variable the machine requires to use.
 Since the machine is aware of its CPUs, directly use the
 first one to load the firmware.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-4-edgar.iglesias@gmail.com
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200924111808.77168-3-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/xlnx-versal-virt.c | 2 +-
+ hw/arm/raspi.c | 3 ++-
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal-virt.c
+--- a/hw/arm/raspi.c
-+++ b/hw/arm/xlnx-versal-virt.c
++++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
-         psci_conduit = QEMU_PSCI_CONDUIT_SMC;
  static void setup_boot(MachineState *machine, int version, size_t ram_size)
  {
 +    RaspiMachineState *s = RASPI_MACHINE(machine);
      static struct arm_boot_info binfo;
      int r;
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
          binfo.firmware_loaded = true;
      }
--    sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
+-    arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
-+    sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc,
++    arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
-                           sizeof(s->soc), TYPE_XLNX_VERSAL);
+ }
-     object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
-                              "ddr", &error_abort);
+ static void raspi_machine_init(MachineState *machine)
 --
 .20.1

-[PULL 02/39] hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string
+[PULL 13/18] hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
 From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-By using the TYPE_* definitions for devices, we can:
+The arm_boot_info structure belong to the machine,
- - quickly find where devices are used with 'git-grep'
+move it to RaspiMachineState.
  - easily rename a device (one-line change).
+Reviewed-by: Luc Michel <luc.michel@greensocs.com>
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200428154650.21991-1-f4bug@amsat.org
+Message-id: 20200924111808.77168-4-f4bug@amsat.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/mps2-tz.c | 2 +-
+ hw/arm/raspi.c | 30 +++++++++++++++---------------
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 15 insertions(+), 15 deletions(-)
-diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2-tz.c
+--- a/hw/arm/raspi.c
-+++ b/hw/arm/mps2-tz.c
++++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
+@@ -XXX,XX +XXX,XX @@ struct RaspiMachineState {
-         exit(EXIT_FAILURE);
+     MachineState parent_obj;
      /*< public >*/
      BCM283XState soc;
 +    struct arm_boot_info binfo;
  };
  typedef struct RaspiMachineState RaspiMachineState;
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  static void setup_boot(MachineState *machine, int version, size_t ram_size)
  {
      RaspiMachineState *s = RASPI_MACHINE(machine);
 -    static struct arm_boot_info binfo;
      int r;
 -    binfo.board_id = MACH_TYPE_BCM2708;
 -    binfo.ram_size = ram_size;
 -    binfo.nb_cpus = machine->smp.cpus;
 +    s->binfo.board_id = MACH_TYPE_BCM2708;
 +    s->binfo.ram_size = ram_size;
 +    s->binfo.nb_cpus = machine->smp.cpus;
      if (version <= 2) {
          /* The rpi1 and 2 require some custom setup code to run in Secure
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
           * firmware for some cache maintenance operations.
           * The rpi3 doesn't need this.
           */
 -        binfo.board_setup_addr = BOARDSETUP_ADDR;
 -        binfo.write_board_setup = write_board_setup;
 -        binfo.secure_board_setup = true;
 -        binfo.secure_boot = true;
 +        s->binfo.board_setup_addr = BOARDSETUP_ADDR;
 +        s->binfo.write_board_setup = write_board_setup;
 +        s->binfo.secure_board_setup = true;
 +        s->binfo.secure_boot = true;
      }
--    sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
+     /* Pi2 and Pi3 requires SMP setup */
-+    sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
+     if (version >= 2) {
-                           sizeof(mms->iotkit), mmc->armsse_type);
+-        binfo.smp_loader_start = SMPBOOT_ADDR;
-     iotkitdev = DEVICE(&mms->iotkit);
++        s->binfo.smp_loader_start = SMPBOOT_ADDR;
-     object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
+         if (version == 2) {
 -            binfo.write_secondary_boot = write_smpboot;
 +            s->binfo.write_secondary_boot = write_smpboot;
          } else {
 -            binfo.write_secondary_boot = write_smpboot64;
 +            s->binfo.write_secondary_boot = write_smpboot64;
          }
 -        binfo.secondary_cpu_reset_hook = reset_secondary;
 +        s->binfo.secondary_cpu_reset_hook = reset_secondary;
      }
      /* If the user specified a "firmware" image (e.g. UEFI), we bypass
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
              exit(1);
          }
 -        binfo.entry = firmware_addr;
 -        binfo.firmware_loaded = true;
 +        s->binfo.entry = firmware_addr;
 +        s->binfo.firmware_loaded = true;
      }
 -    arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
 +    arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo);
  }
  static void raspi_machine_init(MachineState *machine)
 --
 .20.1

-[PULL 04/39] target/arm: Use enum constant in get_phys_addr_lpae() call
+Deleted patch
-The access_type argument to get_phys_addr_lpae() is an MMUAccessType;
-use the enum constant MMU_DATA_LOAD rather than a literal 0 when we
-call it in S1_ptw_translate().
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200330210400.11724-3-peter.maydell@linaro.org
----
- target/arm/helper.c | 5 +++--
-file changed, 3 insertions(+), 2 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
-             pcacheattrs = &cacheattrs;
-         }
--        ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa,
--                                 &txattrs, &s2prot, &s2size, fi, pcacheattrs);
-+        ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
-+                                 &s2pa, &txattrs, &s2prot, &s2size, fi,
-+                                 pcacheattrs);
-         if (ret) {
-             assert(fi->type != ARMFault_None);
-             fi->s2addr = addr;
---
-.20.1

-[PULL 05/39] target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()
+Deleted patch
-For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know
-whether the stage 1 access is for EL0 or not, because whether
-exec permission is given can depend on whether this is an EL0
-or EL1 access. Add a new argument to get_phys_addr_lpae() so
-the call sites can pass this information in.
-Since get_phys_addr_lpae() doesn't already have a doc comment,
-add one so we have a place to put the documentation of the
-semantics of the new s1_is_el0 argument.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200330210400.11724-4-peter.maydell@linaro.org
----
- target/arm/helper.c | 29 ++++++++++++++++++++++++++++-
-file changed, 28 insertions(+), 1 deletion(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
- static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
-                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
-+                               bool s1_is_el0,
-                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
-                                target_ulong *page_size_ptr,
-                                ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
-@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
-         }
-         ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
-+                                 false,
-                                  &s2pa, &txattrs, &s2prot, &s2size, fi,
-                                  pcacheattrs);
-         if (ret) {
-@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
-     };
- }
-+/**
-+ * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
-+ *
-+ * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
-+ * prot and page_size may not be filled in, and the populated fsr value provides
-+ * information on why the translation aborted, in the format of a long-format
-+ * DFSR/IFSR fault register, with the following caveats:
-+ *  * the WnR bit is never set (the caller must do this).
-+ *
-+ * @env: CPUARMState
-+ * @address: virtual address to get physical address for
-+ * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
-+ * @mmu_idx: MMU index indicating required translation regime
-+ * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
-+ *             walk), must be true if this is stage 2 of a stage 1+2 walk for an
-+ *             EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
-+ * @phys_ptr: set to the physical address corresponding to the virtual address
-+ * @attrs: set to the memory transaction attributes to use
-+ * @prot: set to the permissions for the page containing phys_ptr
-+ * @page_size_ptr: set to the size of the page containing phys_ptr
-+ * @fi: set to fault info if the translation fails
-+ * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
-+ */
- static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
-                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
-+                               bool s1_is_el0,
-                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
-                                target_ulong *page_size_ptr,
-                                ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
-             /* S1 is done. Now do S2 translation.  */
-             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,
-+                                     mmu_idx == ARMMMUIdx_E10_0,
-                                      phys_ptr, attrs, &s2_prot,
-                                      page_size, fi,
-                                      cacheattrs != NULL ? &cacheattrs2 : NULL);
-@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
-     }
-     if (regime_using_lpae_format(env, mmu_idx)) {
--        return get_phys_addr_lpae(env, address, access_type, mmu_idx,
-+        return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
-                                   phys_ptr, attrs, prot, page_size,
-                                   fi, cacheattrs);
-     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
---
-.20.1

-[PULL 07/39] target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0
+Deleted patch
-In aarch64_max_initfn() we update both 32-bit and 64-bit ID
-registers.  The intended pattern is that for 64-bit ID registers we
-use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
-registers use FIELD_DP32 and the uint32_t 'u' register.  For
-ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of
-this 64-bit ID register would end up always zero.  Luckily at the
-moment that's what they should be anyway, so this bug has no visible
-effects.
-Use the right-sized variable.
-Fixes: 3bec78447a958d481991
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200423110915.10527-1-peter.maydell@linaro.org
----
- target/arm/cpu64.c | 6 +++---
-file changed, 3 insertions(+), 3 deletions(-)
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-         u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
-         cpu->isar.id_mmfr4 = u;
--        u = cpu->isar.id_aa64dfr0;
--        u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
--        cpu->isar.id_aa64dfr0 = u;
-+        t = cpu->isar.id_aa64dfr0;
-+        t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
-+        cpu->isar.id_aa64dfr0 = t;
-         u = cpu->isar.id_dfr0;
-         u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
---
-.20.1

-[PULL 19/39] hw/arm: versal-virt: Add support for the RTC
+[PULL 14/18] hw/arm/raspi: Avoid using TypeInfo::class_data pointer
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Add support for the RTC.
+Using class_data pointer to create a MachineClass is not
 the recommended way anymore. The correct way is to open-code
 the MachineClass::fields in the class_init() method.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+We can not use TYPE_RASPI_MACHINE::class_base_init() because
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+it is called *before* each machine class_init(), therefore the
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
+board_rev field is not populated. We have to manually call
-Message-id: 20200427181649.26851-12-edgar.iglesias@gmail.com
+raspi_machine_class_common_init() for each machine.
 This partly reverts commit a03bde3674e.
 Suggested-by: Igor Mammedov <imammedo@redhat.com>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Igor Mammedov <imammedo@redhat.com>
 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200924111808.77168-5-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/xlnx-versal-virt.c | 22 ++++++++++++++++++++++
+ hw/arm/raspi.c | 34 ++++++++++++++++++++++++----------
-file changed, 22 insertions(+)
+file changed, 24 insertions(+), 10 deletions(-)
-diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal-virt.c
+--- a/hw/arm/raspi.c
-+++ b/hw/arm/xlnx-versal-virt.c
++++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_sd_nodes(VersalVirt *s)
+@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
-     }
+     setup_boot(machine, version, machine->ram_size - vcram_size);
  }
-+static void fdt_add_rtc_node(VersalVirt *s)
+-static void raspi_machine_class_init(ObjectClass *oc, void *data)
 +static void raspi_machine_class_common_init(MachineClass *mc,
 +                                            uint32_t board_rev)
  {
 -    MachineClass *mc = MACHINE_CLASS(oc);
 -    RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
 -    uint32_t board_rev = (uint32_t)(uintptr_t)data;
 -
 -    rmc->board_rev = board_rev;
      mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
                                 board_type(board_rev),
                                 FIELD_EX32(board_rev, REV_CODE, REVISION));
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
      mc->default_ram_id = "ram";
  };
 +static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
 +{
-+    const char compat[] = "xlnx,zynqmp-rtc";
++    MachineClass *mc = MACHINE_CLASS(oc);
-+    const char interrupt_names[] = "alarm\0sec";
++    RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
 +    char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC);
 +
-+    qemu_fdt_add_subnode(s->fdt, name);
++    rmc->board_rev = 0xa21041;
 +    raspi_machine_class_common_init(mc, rmc->board_rev);
 +};
 +
-+    qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
++#ifdef TARGET_AARCH64
-+                           GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ,
++static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
-+                           GIC_FDT_IRQ_FLAGS_LEVEL_HI,
++{
-+                           GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ,
++    MachineClass *mc = MACHINE_CLASS(oc);
-+                           GIC_FDT_IRQ_FLAGS_LEVEL_HI);
++    RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
 +    qemu_fdt_setprop(s->fdt, name, "interrupt-names",
 +                     interrupt_names, sizeof(interrupt_names));
 +    qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 +                                 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE);
 +    qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
 +    g_free(name);
 +}
 +
- static void fdt_nop_memory_nodes(void *fdt, Error **errp)
++    rmc->board_rev = 0xa02082;
- {
++    raspi_machine_class_common_init(mc, rmc->board_rev);
-     Error *err = NULL;
++};
-@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
++#endif /* TARGET_AARCH64 */
-     fdt_add_timer_nodes(s);
++
-     fdt_add_zdma_nodes(s);
+ static const TypeInfo raspi_machine_types[] = {
-     fdt_add_sd_nodes(s);
+     {
-+    fdt_add_rtc_node(s);
+         .name           = MACHINE_TYPE_NAME("raspi2"),
-     fdt_add_cpu_nodes(s, psci_conduit);
+         .parent         = TYPE_RASPI_MACHINE,
-     fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
+-        .class_init     = raspi_machine_class_init,
-     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
+-        .class_data     = (void *)0xa21041,
 +        .class_init     = raspi2b_machine_class_init,
  #ifdef TARGET_AARCH64
      }, {
          .name           = MACHINE_TYPE_NAME("raspi3"),
          .parent         = TYPE_RASPI_MACHINE,
 -        .class_init     = raspi_machine_class_init,
 -        .class_data     = (void *)0xa02082,
 +        .class_init     = raspi3b_machine_class_init,
  #endif
      }, {
          .name           = TYPE_RASPI_MACHINE,
 --
 .20.1

-[PULL 12/39] hw/arm: versal: Embed the UARTs into the SoC type
+[PULL 15/18] hw/arm/raspi: Use more specific machine names
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Embed the UARTs into the SoC type.
+Now that we can instantiate different machines based on their
 board_rev register value, we can have various raspi2 and raspi3.
-Suggested-by: Peter Maydell <peter.maydell@linaro.org>
+In commit fc78a990ec103 we corrected the machine description.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Correct the machine names too. For backward compatibility, add
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+an alias to the previous generic name.
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-5-edgar.iglesias@gmail.com
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200924111808.77168-6-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/xlnx-versal.h |  3 ++-
+ hw/arm/raspi.c | 6 ++++--
- hw/arm/xlnx-versal.c         | 12 ++++++------
+file changed, 4 insertions(+), 2 deletions(-)
 files changed, 8 insertions(+), 7 deletions(-)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
+--- a/hw/arm/raspi.c
-+++ b/include/hw/arm/xlnx-versal.h
++++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
- #include "hw/sysbus.h"
+     MachineClass *mc = MACHINE_CLASS(oc);
- #include "hw/arm/boot.h"
+     RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
- #include "hw/intc/arm_gicv3.h"
-+#include "hw/char/pl011.h"
++    mc->alias = "raspi2";
+     rmc->board_rev = 0xa21041;
- #define TYPE_XLNX_VERSAL "xlnx-versal"
+     raspi_machine_class_common_init(mc, rmc->board_rev);
- #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
+ };
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
+@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
-         MemoryRegion mr_ocm;
+     MachineClass *mc = MACHINE_CLASS(oc);
+     RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
-         struct {
--            SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
++    mc->alias = "raspi3";
-+            PL011State uart[XLNX_VERSAL_NR_UARTS];
+     rmc->board_rev = 0xa02082;
-             SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
+     raspi_machine_class_common_init(mc, rmc->board_rev);
-             SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
+ };
-         } iou;
+@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
-index XXXXXXX..XXXXXXX 100644
+ static const TypeInfo raspi_machine_types[] = {
---- a/hw/arm/xlnx-versal.c
+     {
-+++ b/hw/arm/xlnx-versal.c
+-        .name           = MACHINE_TYPE_NAME("raspi2"),
-@@ -XXX,XX +XXX,XX @@
++        .name           = MACHINE_TYPE_NAME("raspi2b"),
- #include "kvm_arm.h"
+         .parent         = TYPE_RASPI_MACHINE,
- #include "hw/misc/unimp.h"
+         .class_init     = raspi2b_machine_class_init,
- #include "hw/arm/xlnx-versal.h"
+ #ifdef TARGET_AARCH64
--#include "hw/char/pl011.h"
+     }, {
+-        .name           = MACHINE_TYPE_NAME("raspi3"),
- #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
++        .name           = MACHINE_TYPE_NAME("raspi3b"),
- #define GEM_REVISION        0x40070106
+         .parent         = TYPE_RASPI_MACHINE,
-@@ -XXX,XX +XXX,XX @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)
+         .class_init     = raspi3b_machine_class_init,
-         DeviceState *dev;
+ #endif
          MemoryRegion *mr;
 -        dev = qdev_create(NULL, TYPE_PL011);
 -        s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);
 +        sysbus_init_child_obj(OBJECT(s), name,
 +                              &s->lpd.iou.uart[i], sizeof(s->lpd.iou.uart[i]),
 +                              TYPE_PL011);
 +        dev = DEVICE(&s->lpd.iou.uart[i]);
          qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 -        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
          qdev_init_nofail(dev);
 -        mr = sysbus_mmio_get_region(s->lpd.iou.uart[i], 0);
 +        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
          memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
 -        sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
          g_free(name);
      }
  }
 --
 .20.1

-[PULL 18/39] hw/arm: versal-virt: Add support for SD
+[PULL 16/18] hw/arm/raspi: Introduce RaspiProcessorId enum
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Add support for SD.
+As we only support a reduced set of the REV_CODE_PROCESSOR id
 encoded in the board revision, define the PROCESSOR_ID values
 as an enum. We can simplify the board_soc_type and cores_count
 methods.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-11-edgar.iglesias@gmail.com
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200924111808.77168-7-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/xlnx-versal-virt.c | 46 +++++++++++++++++++++++++++++++++++++++
+ hw/arm/raspi.c | 45 +++++++++++++++++++++------------------------
-file changed, 46 insertions(+)
+file changed, 21 insertions(+), 24 deletions(-)
-diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal-virt.c
+--- a/hw/arm/raspi.c
-+++ b/hw/arm/xlnx-versal-virt.c
++++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ FIELD(REV_CODE, MANUFACTURER,      16, 4);
- #include "hw/arm/sysbus-fdt.h"
+ FIELD(REV_CODE, MEMORY_SIZE,       20, 3);
- #include "hw/arm/fdt.h"
+ FIELD(REV_CODE, STYLE,             23, 1);
- #include "cpu.h"
-+#include "hw/qdev-properties.h"
++typedef enum RaspiProcessorId {
- #include "hw/arm/xlnx-versal.h"
++    PROCESSOR_ID_BCM2836 = 1,
++    PROCESSOR_ID_BCM2837 = 2,
- #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
++} RaspiProcessorId;
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_zdma_nodes(VersalVirt *s)
++
-     }
++static const struct {
 +    const char *type;
 +    int cores_count;
 +} soc_property[] = {
 +    [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
 +    [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
 +};
 +
  static uint64_t board_ram_size(uint32_t board_rev)
  {
      assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
      return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
  }
-+static void fdt_add_sd_nodes(VersalVirt *s)
+-static int board_processor_id(uint32_t board_rev)
-+{
++static RaspiProcessorId board_processor_id(uint32_t board_rev)
-+    const char clocknames[] = "clk_xin\0clk_ahb";
+ {
-+    const char compat[] = "arasan,sdhci-8.9a";
++    int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
 +    int i;
 +
-+    for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) {
+     assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
-+        uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i;
+-    return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
-+        char *name = g_strdup_printf("/sdhci@%" PRIx64, addr);
++    assert(proc_id < ARRAY_SIZE(soc_property) && soc_property[proc_id].type);
 +
-+        qemu_fdt_add_subnode(s->fdt, name);
++    return proc_id;
-+
+ }
-+        qemu_fdt_setprop_cells(s->fdt, name, "clocks",
-+                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
+ static int board_version(uint32_t board_rev)
-+        qemu_fdt_setprop(s->fdt, name, "clock-names",
+@@ -XXX,XX +XXX,XX @@ static int board_version(uint32_t board_rev)
-+                         clocknames, sizeof(clocknames));
-+        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+ static const char *board_soc_type(uint32_t board_rev)
 +                               GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2,
 +                               GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 +        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
 +                                     2, addr, 2, MM_PMC_SD0_SIZE);
 +        qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
 +        g_free(name);
 +    }
 +}
 +
  static void fdt_nop_memory_nodes(void *fdt, Error **errp)
  {
-     Error *err = NULL;
+-    static const char *soc_types[] = {
-@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
+-        NULL, TYPE_BCM2836, TYPE_BCM2837,
-     }
+-    };
 -    int proc_id = board_processor_id(board_rev);
 -
 -    if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) {
 -        error_report("Unsupported processor id '%d' (board revision: 0x%x)",
 -                     proc_id, board_rev);
 -        exit(1);
 -    }
 -    return soc_types[proc_id];
 +    return soc_property[board_processor_id(board_rev)].type;
  }
-+static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
+ static int cores_count(uint32_t board_rev)
 +{
 +    BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
 +    DeviceState *card;
 +
 +    card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD);
 +    object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card),
 +                              &error_fatal);
 +    qdev_prop_set_drive(card, "drive", blk, &error_fatal);
 +    object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
 +}
 +
  static void versal_virt_init(MachineState *machine)
  {
-     VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
+-    static const int soc_cores_count[] = {
-     int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
+-        0, BCM283X_NCPUS, BCM283X_NCPUS,
-+    int i;
+-    };
+-    int proc_id = board_processor_id(board_rev);
-     /*
+-
-      * If the user provides an Operating System to be loaded, we expect them
+-    if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) {
-@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
+-        error_report("Unsupported processor id '%d' (board revision: 0x%x)",
-     fdt_add_gic_nodes(s);
+-                     proc_id, board_rev);
-     fdt_add_timer_nodes(s);
+-        exit(1);
-     fdt_add_zdma_nodes(s);
+-    }
-+    fdt_add_sd_nodes(s);
+-    return soc_cores_count[proc_id];
-     fdt_add_cpu_nodes(s, psci_conduit);
++    return soc_property[board_processor_id(board_rev)].cores_count;
-     fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
+ }
-     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
-@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
+ static const char *board_type(uint32_t board_rev)
      memory_region_add_subregion_overlap(get_system_memory(),
 , &s->soc.fpd.apu.mr, 0);
 +    /* Plugin SD cards.  */
 +    for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
 +        sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
 +    }
 +
      s->binfo.ram_size = machine->ram_size;
      s->binfo.loader_start = 0x0;
      s->binfo.get_dtb = versal_virt_get_dtb;
 --
 .20.1

-[PULL 10/39] hw/arm: versal: Move misplaced comment
+[PULL 17/18] hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Move misplaced comment.
+The firmware load address depends on the SoC ("processor id") used,
 not on the version of the board.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+Suggested-by: Luc Michel <luc.michel@greensocs.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-3-edgar.iglesias@gmail.com
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200924111808.77168-8-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/xlnx-versal.c | 2 +-
+ hw/arm/raspi.c | 3 ++-
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal.c
+--- a/hw/arm/raspi.c
-+++ b/hw/arm/xlnx-versal.c
++++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
+@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
+      * the normal Linux boot process
-         obj = object_new(XLNX_VERSAL_ACPU_TYPE);
+      */
-         if (!obj) {
+     if (machine->firmware) {
--            /* Secondary CPUs start in PSCI powered-down state */
+-        hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
-             error_report("Unable to create apu.cpu[%d] of type %s",
++        hwaddr firmware_addr = processor_id <= PROCESSOR_ID_BCM2836
-                          i, XLNX_VERSAL_ACPU_TYPE);
++                             ? FIRMWARE_ADDR_2 : FIRMWARE_ADDR_3;
-             exit(EXIT_FAILURE);
+         /* load the firmware image (typically kernel.img) */
-@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
+         r = load_image_targphys(machine->firmware, firmware_addr,
-         object_property_set_int(obj, s->cfg.psci_conduit,
+                                 ram_size - firmware_addr);
                                  "psci-conduit", &error_abort);
          if (i) {
 +            /* Secondary CPUs start in PSCI powered-down state */
              object_property_set_bool(obj, true,
                                       "start-powered-off", &error_abort);
          }
 --
 .20.1

-[PULL 15/39] hw/arm: versal: Embed the APUs into the SoC type
+[PULL 18/18] hw/arm/raspi: Remove use of the 'version' value in the board code
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
+From: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Embed the APUs into the SoC type.
+We expected the 'version' ID to match the board processor ID,
 but this is not always true (for example boards with revision
 id 0xa02042/0xa22042 are Raspberry Pi 2 with a BCM2837 SoC).
 This was not important because we were not modelling them, but
 since the recent refactor now allow to model these boards, it
 is safer to check the processor id directly. Remove the version
 check.
 Suggested-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-8-edgar.iglesias@gmail.com
+Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Message-id: 20200924111808.77168-9-f4bug@amsat.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/xlnx-versal.h |  2 +-
+ hw/arm/raspi.c | 29 +++++++++++++----------------
- hw/arm/xlnx-versal-virt.c    |  4 ++--
+file changed, 13 insertions(+), 16 deletions(-)
  hw/arm/xlnx-versal.c         | 19 +++++--------------
 files changed, 8 insertions(+), 17 deletions(-)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
+--- a/hw/arm/raspi.c
-+++ b/include/hw/arm/xlnx-versal.h
++++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
+@@ -XXX,XX +XXX,XX @@ static RaspiProcessorId board_processor_id(uint32_t board_rev)
-     struct {
+     return proc_id;
-         struct {
+ }
-             MemoryRegion mr;
--            ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
+-static int board_version(uint32_t board_rev)
-+            ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
+-{
-             GICv3State gic;
+-    return board_processor_id(board_rev) + 1;
-         } apu;
+-}
      } fpd;
 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal-virt.c
 +++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
      s->binfo.get_dtb = versal_virt_get_dtb;
      s->binfo.modify_dtb = versal_virt_modify_dtb;
      if (machine->kernel_filename) {
 -        arm_load_kernel(s->soc.fpd.apu.cpu[0], machine, &s->binfo);
 +        arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo);
      } else {
 -        AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
 +        AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0],
                                                    &s->binfo);
          /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
           * Offset things by 4K.  */
 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal.c
 +++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
      for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
          Object *obj;
 -        char *name;
 -
--        obj = object_new(XLNX_VERSAL_ACPU_TYPE);
+ static const char *board_soc_type(uint32_t board_rev)
--        if (!obj) {
+ {
--            error_report("Unable to create apu.cpu[%d] of type %s",
+     return soc_property[board_processor_id(board_rev)].type;
--                         i, XLNX_VERSAL_ACPU_TYPE);
+@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
--            exit(EXIT_FAILURE);
+     cpu_set_pc(cs, info->smp_loader_start);
--        }
+ }
--
--        name = g_strdup_printf("apu-cpu[%d]", i);
+-static void setup_boot(MachineState *machine, int version, size_t ram_size)
--        object_property_add_child(OBJECT(s), name, obj, &error_fatal);
++static void setup_boot(MachineState *machine, RaspiProcessorId processor_id,
--        g_free(name);
++                       size_t ram_size)
+ {
-+        object_initialize_child(OBJECT(s), "apu-cpu[*]",
+     RaspiMachineState *s = RASPI_MACHINE(machine);
-+                                &s->fpd.apu.cpu[i], sizeof(s->fpd.apu.cpu[i]),
+     int r;
-+                                XLNX_VERSAL_ACPU_TYPE, &error_abort, NULL);
+@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
-+        obj = OBJECT(&s->fpd.apu.cpu[i]);
+     s->binfo.ram_size = ram_size;
-         object_property_set_int(obj, s->cfg.psci_conduit,
+     s->binfo.nb_cpus = machine->smp.cpus;
-                                 "psci-conduit", &error_abort);
-         if (i) {
+-    if (version <= 2) {
-@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
+-        /* The rpi1 and 2 require some custom setup code to run in Secure
-         object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
+-         * mode before booting a kernel (to set up the SMC vectors so
-                                  &error_abort);
+-         * that we get a no-op SMC; this is used by Linux to call the
-         object_property_set_bool(obj, true, "realized", &error_fatal);
++    if (processor_id <= PROCESSOR_ID_BCM2836) {
--        s->fpd.apu.cpu[i] = ARM_CPU(obj);
++        /*
 +         * The BCM2835 and BCM2836 require some custom setup code to run
 +         * in Secure mode before booting a kernel (to set up the SMC vectors
 +         * so that we get a no-op SMC; this is used by Linux to call the
           * firmware for some cache maintenance operations.
 -         * The rpi3 doesn't need this.
 +         * The BCM2837 doesn't need this.
           */
          s->binfo.board_setup_addr = BOARDSETUP_ADDR;
          s->binfo.write_board_setup = write_board_setup;
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
          s->binfo.secure_boot = true;
      }
+-    /* Pi2 and Pi3 requires SMP setup */
+-    if (version >= 2) {
++    /* BCM2836 and BCM2837 requires SMP setup */
++    if (processor_id >= PROCESSOR_ID_BCM2836) {
+         s->binfo.smp_loader_start = SMPBOOT_ADDR;
+-        if (version == 2) {
++        if (processor_id == PROCESSOR_ID_BCM2836) {
+             s->binfo.write_secondary_boot = write_smpboot;
+         } else {
+             s->binfo.write_secondary_boot = write_smpboot64;
+@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
+     RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine);
+     RaspiMachineState *s = RASPI_MACHINE(machine);
+     uint32_t board_rev = mc->board_rev;
+-    int version = board_version(board_rev);
+     uint64_t ram_size = board_ram_size(board_rev);
+     uint32_t vcram_size;
+     DriveInfo *di;
+@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
+     vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
+                                           &error_abort);
+-    setup_boot(machine, version, machine->ram_size - vcram_size);
++    setup_boot(machine, board_processor_id(mc->board_rev),
++               machine->ram_size - vcram_size);
  }
-@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
+ static void raspi_machine_class_common_init(MachineClass *mc,
      }
      for (i = 0; i < nr_apu_cpus; i++) {
 -        DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);
 +        DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]);
          int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
          qemu_irq maint_irq;
          int ti;
 --
 .20.1

-[PULL 17/39] hw/arm: versal: Add support for the RTC
+Deleted patch
-From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
-hw/arm: versal: Add support for the RTC.
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Luc Michel <luc.michel@greensocs.com>
-Message-id: 20200427181649.26851-10-edgar.iglesias@gmail.com
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- include/hw/arm/xlnx-versal.h |  8 ++++++++
- hw/arm/xlnx-versal.c         | 21 +++++++++++++++++++++
-files changed, 29 insertions(+)
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
-+++ b/include/hw/arm/xlnx-versal.h
-@@ -XXX,XX +XXX,XX @@
- #include "hw/char/pl011.h"
- #include "hw/dma/xlnx-zdma.h"
- #include "hw/net/cadence_gem.h"
-+#include "hw/rtc/xlnx-zynqmp-rtc.h"
- #define TYPE_XLNX_VERSAL "xlnx-versal"
- #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
-         struct {
-             SDHCIState sd[XLNX_VERSAL_NR_SDS];
-         } iou;
-+
-+        XlnxZynqMPRTC rtc;
-     } pmc;
-     struct {
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
- #define VERSAL_GEM1_IRQ_0          58
- #define VERSAL_GEM1_WAKE_IRQ_0     59
- #define VERSAL_ADMA_IRQ_0          60
-+#define VERSAL_RTC_APB_ERR_IRQ     121
- #define VERSAL_SD0_IRQ_0           126
-+#define VERSAL_RTC_ALARM_IRQ       142
-+#define VERSAL_RTC_SECONDS_IRQ     143
- /* Architecturally reserved IRQs suitable for virtualization.  */
- #define VERSAL_RSVD_IRQ_FIRST 111
-@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
- #define MM_PMC_SD0_SIZE             0x10000
- #define MM_PMC_CRP                  0xf1260000U
- #define MM_PMC_CRP_SIZE             0x10000
-+#define MM_PMC_RTC                  0xf12a0000
-+#define MM_PMC_RTC_SIZE             0x10000
- #endif
-diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/xlnx-versal.c
-+++ b/hw/arm/xlnx-versal.c
-@@ -XXX,XX +XXX,XX @@ static void versal_create_sds(Versal *s, qemu_irq *pic)
-     }
- }
-+static void versal_create_rtc(Versal *s, qemu_irq *pic)
-+{
-+    SysBusDevice *sbd;
-+    MemoryRegion *mr;
-+
-+    sysbus_init_child_obj(OBJECT(s), "rtc", &s->pmc.rtc, sizeof(s->pmc.rtc),
-+                          TYPE_XLNX_ZYNQMP_RTC);
-+    sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
-+    qdev_init_nofail(DEVICE(sbd));
-+
-+    mr = sysbus_mmio_get_region(sbd, 0);
-+    memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
-+
-+    /*
-+     * TODO: Connect the ALARM and SECONDS interrupts once our RTC model
-+     * supports them.
-+     */
-+    sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
-+}
-+
- /* This takes the board allocated linear DDR memory and creates aliases
-  * for each split DDR range/aperture on the Versal address map.
-  */
-@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
-     versal_create_gems(s, pic);
-     versal_create_admas(s, pic);
-     versal_create_sds(s, pic);
-+    versal_create_rtc(s, pic);
-     versal_map_ddr(s);
-     versal_unimp(s);
---
-.20.1

-[PULL 20/39] target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
+Deleted patch
-Somewhere along theline we accidentally added a duplicate
-"using D16-D31 when they don't exist" check to do_vfm_dp()
-(probably an artifact of a patchseries rebase). Remove it.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200430181003.21682-2-peter.maydell@linaro.org
----
- target/arm/translate-vfp.inc.c | 6 ------
-file changed, 6 deletions(-)
-diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-vfp.inc.c
-+++ b/target/arm/translate-vfp.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
-         return false;
-     }
--    /* UNDEF accesses to D16-D31 if they don't exist. */
--    if (!dc_isar_feature(aa32_simd_r32, s) &&
--        ((a->vd | a->vn | a->vm) & 0x10)) {
--        return false;
--    }
--
-     if (!vfp_access_check(s)) {
-         return true;
-     }
---
-.20.1

-[PULL 21/39] target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
+Deleted patch
-We were accidentally permitting decode of Thumb Neon insns even if
-the CPU didn't have the FEATURE_NEON bit set, because the feature
-check was being done before the call to disas_neon_data_insn() and
-disas_neon_ls_insn() in the Arm decoder but was omitted from the
-Thumb decoder.  Push the feature bit check down into the called
-functions so it is done for both Arm and Thumb encodings.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
-Message-id: 20200430181003.21682-3-peter.maydell@linaro.org
----
- target/arm/translate.c | 16 ++++++++--------
-file changed, 8 insertions(+), 8 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
-     TCGv_i32 tmp2;
-     TCGv_i64 tmp64;
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-+        return 1;
-+    }
-+
-     /* FIXME: this access check should not take precedence over UNDEF
-      * for invalid encodings; we will generate incorrect syndrome information
-      * for attempts to execute invalid vfp/neon encodings with FP disabled.
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     TCGv_ptr ptr1, ptr2, ptr3;
-     TCGv_i64 tmp64;
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-+        return 1;
-+    }
-+
-     /* FIXME: this access check should not take precedence over UNDEF
-      * for invalid encodings; we will generate incorrect syndrome information
-      * for attempts to execute invalid vfp/neon encodings with FP disabled.
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
-         if (((insn >> 25) & 7) == 1) {
-             /* NEON Data processing.  */
--            if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
--                goto illegal_op;
--            }
--
-             if (disas_neon_data_insn(s, insn)) {
-                 goto illegal_op;
-             }
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
-         }
-         if ((insn & 0x0f100000) == 0x04000000) {
-             /* NEON load/store.  */
--            if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
--                goto illegal_op;
--            }
--
-             if (disas_neon_ls_insn(s, insn)) {
-                 goto illegal_op;
-             }
---
-.20.1

-[PULL 22/39] target/arm: Add stubs for AArch32 Neon decodetree
+Deleted patch
-Add the infrastructure for building and invoking a decodetree decoder
-for the AArch32 Neon encodings.  At the moment the new decoder covers
-nothing, so we always fall back to the existing hand-written decode.
-We follow the same pattern we did for the VFP decodetree conversion
-(commit 78e138bc1f672c145ef6ace74617d and following): code that deals
-with Neon will be moving gradually out to translate-neon.vfp.inc,
-which we #include into translate.c.
-In order to share the decode files between A32 and T32, we
-split Neon into 3 parts:
- * data-processing
- * load-store
- * 'shared' encodings
-The first two groups of instructions have similar but not identical
-A32 and T32 encodings, so we need to manually transform the T32
-encoding into the A32 one before calling the decoder; the third group
-covers the Neon instructions which are identical in A32 and T32.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-4-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       | 29 ++++++++++++++++++++++++++
- target/arm/neon-ls.decode       | 29 ++++++++++++++++++++++++++
- target/arm/neon-shared.decode   | 27 +++++++++++++++++++++++++
- target/arm/translate-neon.inc.c | 32 +++++++++++++++++++++++++++++
- target/arm/translate.c          | 36 +++++++++++++++++++++++++++++++--
- target/arm/Makefile.objs        | 18 +++++++++++++++++
-files changed, 169 insertions(+), 2 deletions(-)
- create mode 100644 target/arm/neon-dp.decode
- create mode 100644 target/arm/neon-ls.decode
- create mode 100644 target/arm/neon-shared.decode
- create mode 100644 target/arm/translate-neon.inc.c
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@
-+# AArch32 Neon data-processing instruction descriptions
-+#
-+#  Copyright (c) 2020 Linaro, Ltd
-+#
-+# This library is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU Lesser General Public
-+# License as published by the Free Software Foundation; either
-+# version 2 of the License, or (at your option) any later version.
-+#
-+# This library is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+# Lesser General Public License for more details.
-+#
-+# You should have received a copy of the GNU Lesser General Public
-+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
-+
-+#
-+# This file is processed by scripts/decodetree.py
-+#
-+
-+# Encodings for Neon data processing instructions where the T32 encoding
-+# is a simple transformation of the A32 encoding.
-+# More specifically, this file covers instructions where the A32 encoding is
-+#   0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
-+# and the T32 encoding is
-+#   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
-+# This file works on the A32 encoding only; calling code for T32 has to
-+# transform the insn into the A32 version first.
-diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/target/arm/neon-ls.decode
-@@ -XXX,XX +XXX,XX @@
-+# AArch32 Neon load/store instruction descriptions
-+#
-+#  Copyright (c) 2020 Linaro, Ltd
-+#
-+# This library is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU Lesser General Public
-+# License as published by the Free Software Foundation; either
-+# version 2 of the License, or (at your option) any later version.
-+#
-+# This library is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+# Lesser General Public License for more details.
-+#
-+# You should have received a copy of the GNU Lesser General Public
-+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
-+
-+#
-+# This file is processed by scripts/decodetree.py
-+#
-+
-+# Encodings for Neon load/store instructions where the T32 encoding
-+# is a simple transformation of the A32 encoding.
-+# More specifically, this file covers instructions where the A32 encoding is
-+#   0b1111_0100_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
-+# and the T32 encoding is
-+#   0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
-+# This file works on the A32 encoding only; calling code for T32 has to
-+# transform the insn into the A32 version first.
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@
-+# AArch32 Neon instruction descriptions
-+#
-+#  Copyright (c) 2020 Linaro, Ltd
-+#
-+# This library is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU Lesser General Public
-+# License as published by the Free Software Foundation; either
-+# version 2 of the License, or (at your option) any later version.
-+#
-+# This library is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+# Lesser General Public License for more details.
-+#
-+# You should have received a copy of the GNU Lesser General Public
-+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
-+
-+#
-+# This file is processed by scripts/decodetree.py
-+#
-+
-+# Encodings for Neon instructions whose encoding is the same for
-+# both A32 and T32.
-+
-+# More specifically, this covers:
-+# 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
-+# 3same ext:       0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-new file mode 100644
-index XXXXXXX..XXXXXXX
---- /dev/null
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@
-+/*
-+ *  ARM translation: AArch32 Neon instructions
-+ *
-+ *  Copyright (c) 2003 Fabrice Bellard
-+ *  Copyright (c) 2005-2007 CodeSourcery
-+ *  Copyright (c) 2007 OpenedHand, Ltd.
-+ *  Copyright (c) 2020 Linaro, Ltd.
-+ *
-+ * This library is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU Lesser General Public
-+ * License as published by the Free Software Foundation; either
-+ * version 2 of the License, or (at your option) any later version.
-+ *
-+ * This library is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-+ * Lesser General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU Lesser General Public
-+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
-+ */
-+
-+/*
-+ * This file is intended to be included from translate.c; it uses
-+ * some macros and definitions provided by that file.
-+ * It might be possible to convert it to a standalone .c file eventually.
-+ */
-+
-+/* Include the generated Neon decoder */
-+#include "decode-neon-dp.inc.c"
-+#include "decode-neon-ls.inc.c"
-+#include "decode-neon-shared.inc.c"
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
- #define ARM_CP_RW_BIT   (1 << 20)
--/* Include the VFP decoder */
-+/* Include the VFP and Neon decoders */
- #include "translate-vfp.inc.c"
-+#include "translate-neon.inc.c"
- static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
- {
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
-         /* Unconditional instructions.  */
-         /* TODO: Perhaps merge these into one decodetree output file.  */
-         if (disas_a32_uncond(s, insn) ||
--            disas_vfp_uncond(s, insn)) {
-+            disas_vfp_uncond(s, insn) ||
-+            disas_neon_dp(s, insn) ||
-+            disas_neon_ls(s, insn) ||
-+            disas_neon_shared(s, insn)) {
-             return;
-         }
-         /* fall back to legacy decoder */
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
-         ARCH(6T2);
-     }
-+    if ((insn & 0xef000000) == 0xef000000) {
-+        /*
-+         * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
-+         * transform into
-+         * A32 encodings 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
-+         */
-+        uint32_t a32_insn = (insn & 0xe2ffffff) |
-+            ((insn & (1 << 28)) >> 4) | (1 << 28);
-+
-+        if (disas_neon_dp(s, a32_insn)) {
-+            return;
-+        }
-+    }
-+
-+    if ((insn & 0xff100000) == 0xf9000000) {
-+        /*
-+         * T32 encodings 0b1111_1001_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
-+         * transform into
-+         * A32 encodings 0b1111_0100_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
-+         */
-+        uint32_t a32_insn = (insn & 0x00ffffff) | 0xf4000000;
-+
-+        if (disas_neon_ls(s, a32_insn)) {
-+            return;
-+        }
-+    }
-+
-     /*
-      * TODO: Perhaps merge these into one decodetree output file.
-      * Note disas_vfp is written for a32 with cond field in the
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
-      */
-     if (disas_t32(s, insn) ||
-         disas_vfp_uncond(s, insn) ||
-+        disas_neon_shared(s, insn) ||
-         ((insn >> 28) == 0xe && disas_vfp(s, insn))) {
-         return;
-     }
-diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/Makefile.objs
-+++ b/target/arm/Makefile.objs
-@@ -XXX,XX +XXX,XX @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
-       $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
-       "GEN", $(TARGET_DIR)$@)
-+target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
-+    $(call quiet-command,\
-+      $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
-+      "GEN", $(TARGET_DIR)$@)
-+
-+target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
-+    $(call quiet-command,\
-+      $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
-+      "GEN", $(TARGET_DIR)$@)
-+
-+target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
-+    $(call quiet-command,\
-+      $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
-+      "GEN", $(TARGET_DIR)$@)
-+
- target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
-     $(call quiet-command,\
-       $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
-@@ -XXX,XX +XXX,XX @@ target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
-       "GEN", $(TARGET_DIR)$@)
- target/arm/translate-sve.o: target/arm/decode-sve.inc.c
-+target/arm/translate.o: target/arm/decode-neon-shared.inc.c
-+target/arm/translate.o: target/arm/decode-neon-dp.inc.c
-+target/arm/translate.o: target/arm/decode-neon-ls.inc.c
- target/arm/translate.o: target/arm/decode-vfp.inc.c
- target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
- target/arm/translate.o: target/arm/decode-a32.inc.c
---
-.20.1

-[PULL 23/39] target/arm: Convert VCMLA (vector) to decodetree
+Deleted patch
-Convert the VCMLA (vector) insns in the 3same extension group to
-decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-5-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   | 11 ++++++++++
- target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 11 +---------
-files changed, 49 insertions(+), 10 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@
- # More specifically, this covers:
- # 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
- # 3same ext:       0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
-+
-+# VFP/Neon register fields; same as vfp.decode
-+%vm_dp  5:1 0:4
-+%vm_sp  0:4 5:1
-+%vn_dp  7:1 16:4
-+%vn_sp  16:4 7:1
-+%vd_dp  22:1 12:4
-+%vd_sp  12:4 22:1
-+
-+VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@
- #include "decode-neon-dp.inc.c"
- #include "decode-neon-ls.inc.c"
- #include "decode-neon-shared.inc.c"
-+
-+static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
-+{
-+    int opr_sz;
-+    TCGv_ptr fpst;
-+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
-+
-+    if (!dc_isar_feature(aa32_vcma, s)
-+        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vn | a->vm | a->vd) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    opr_sz = (1 + a->q) * 8;
-+    fpst = get_fpstatus_ptr(1);
-+    fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
-+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(1, a->vn),
-+                       vfp_reg_offset(1, a->vm),
-+                       fpst, opr_sz, opr_sz, a->rot,
-+                       fn_gvec_ptr);
-+    tcg_temp_free_ptr(fpst);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
-     bool is_long = false, q = extract32(insn, 6, 1);
-     bool ptr_is_env = false;
--    if ((insn & 0xfe200f10) == 0xfc200800) {
--        /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
--        int size = extract32(insn, 20, 1);
--        data = extract32(insn, 23, 2); /* rot */
--        if (!dc_isar_feature(aa32_vcma, s)
--            || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
--            return 1;
--        }
--        fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
--    } else if ((insn & 0xfea00f10) == 0xfc800800) {
-+    if ((insn & 0xfea00f10) == 0xfc800800) {
-         /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
-         int size = extract32(insn, 20, 1);
-         data = extract32(insn, 24, 1); /* rot */
---
-.20.1

-[PULL 24/39] target/arm: Convert VCADD (vector) to decodetree
+Deleted patch
-Convert the VCADD (vector) insns to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-6-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   |  3 +++
- target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 11 +---------
-files changed, 41 insertions(+), 10 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@
- VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+
-+VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
-     tcg_temp_free_ptr(fpst);
-     return true;
- }
-+
-+static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
-+{
-+    int opr_sz;
-+    TCGv_ptr fpst;
-+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
-+
-+    if (!dc_isar_feature(aa32_vcma, s)
-+        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vn | a->vm | a->vd) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    opr_sz = (1 + a->q) * 8;
-+    fpst = get_fpstatus_ptr(1);
-+    fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
-+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(1, a->vn),
-+                       vfp_reg_offset(1, a->vm),
-+                       fpst, opr_sz, opr_sz, a->rot,
-+                       fn_gvec_ptr);
-+    tcg_temp_free_ptr(fpst);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
-     bool is_long = false, q = extract32(insn, 6, 1);
-     bool ptr_is_env = false;
--    if ((insn & 0xfea00f10) == 0xfc800800) {
--        /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
--        int size = extract32(insn, 20, 1);
--        data = extract32(insn, 24, 1); /* rot */
--        if (!dc_isar_feature(aa32_vcma, s)
--            || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
--            return 1;
--        }
--        fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
--    } else if ((insn & 0xfeb00f00) == 0xfc200d00) {
-+    if ((insn & 0xfeb00f00) == 0xfc200d00) {
-         /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
-         bool u = extract32(insn, 4, 1);
-         if (!dc_isar_feature(aa32_dp, s)) {
---
-.20.1

-[PULL 25/39] target/arm: Convert V[US]DOT (vector) to decodetree
+Deleted patch
-Convert the V[US]DOT (vector) insns to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-7-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   |  4 ++++
- target/arm/translate-neon.inc.c | 32 ++++++++++++++++++++++++++++++++
- target/arm/translate.c          |  9 +--------
-files changed, 37 insertions(+), 8 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@ VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
- VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+
-+# VUDOT and VSDOT
-+VDOT           1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
-     tcg_temp_free_ptr(fpst);
-     return true;
- }
-+
-+static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
-+{
-+    int opr_sz;
-+    gen_helper_gvec_3 *fn_gvec;
-+
-+    if (!dc_isar_feature(aa32_dp, s)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vn | a->vm | a->vd) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    opr_sz = (1 + a->q) * 8;
-+    fn_gvec = a->u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
-+    tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(1, a->vn),
-+                       vfp_reg_offset(1, a->vm),
-+                       opr_sz, opr_sz, 0, fn_gvec);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
-     bool is_long = false, q = extract32(insn, 6, 1);
-     bool ptr_is_env = false;
--    if ((insn & 0xfeb00f00) == 0xfc200d00) {
--        /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
--        bool u = extract32(insn, 4, 1);
--        if (!dc_isar_feature(aa32_dp, s)) {
--            return 1;
--        }
--        fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
--    } else if ((insn & 0xff300f10) == 0xfc200810) {
-+    if ((insn & 0xff300f10) == 0xfc200810) {
-         /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
-         int is_s = extract32(insn, 23, 1);
-         if (!dc_isar_feature(aa32_fhm, s)) {
---
-.20.1

-[PULL 26/39] target/arm: Convert VFM[AS]L (vector) to decodetree
+Deleted patch
-Convert the VFM[AS]L (vector) insns to decodetree.  This is the last
-insn in the legacy decoder for the 3same_ext group, so we can
-delete the legacy decoder function for the group entirely.
-Note that in disas_thumb2_insn() the parts of this encoding space
-where the decodetree decoder returns false will correctly be directed
-to illegal_op by the "(insn & (1 << 28))" check so they won't fall
-into disas_coproc_insn() by mistake.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-8-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   |  6 +++
- target/arm/translate-neon.inc.c | 31 +++++++++++
- target/arm/translate.c          | 92 +--------------------------------
-files changed, 38 insertions(+), 91 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@ VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
- # VUDOT and VSDOT
- VDOT           1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+
-+# VFM[AS]L
-+VFML           1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
-+               vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0
-+VFML           1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
-                        opr_sz, opr_sz, 0, fn_gvec);
-     return true;
- }
-+
-+static bool trans_VFML(DisasContext *s, arg_VFML *a)
-+{
-+    int opr_sz;
-+
-+    if (!dc_isar_feature(aa32_fhm, s)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        (a->vd & 0x10)) {
-+        return false;
-+    }
-+
-+    if (a->vd & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    opr_sz = (1 + a->q) * 8;
-+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(a->q, a->vn),
-+                       vfp_reg_offset(a->q, a->vm),
-+                       cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
-+                       gen_helper_gvec_fmlal_a32);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     return 0;
- }
--/* Advanced SIMD three registers of the same length extension.
-- *  31           25    23  22    20   16   12  11   10   9    8        3     0
-- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
-- * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
-- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
-- */
--static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
--{
--    gen_helper_gvec_3 *fn_gvec = NULL;
--    gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
--    int rd, rn, rm, opr_sz;
--    int data = 0;
--    int off_rn, off_rm;
--    bool is_long = false, q = extract32(insn, 6, 1);
--    bool ptr_is_env = false;
--
--    if ((insn & 0xff300f10) == 0xfc200810) {
--        /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
--        int is_s = extract32(insn, 23, 1);
--        if (!dc_isar_feature(aa32_fhm, s)) {
--            return 1;
--        }
--        is_long = true;
--        data = is_s; /* is_2 == 0 */
--        fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
--        ptr_is_env = true;
--    } else {
--        return 1;
--    }
--
--    VFP_DREG_D(rd, insn);
--    if (rd & q) {
--        return 1;
--    }
--    if (q || !is_long) {
--        VFP_DREG_N(rn, insn);
--        VFP_DREG_M(rm, insn);
--        if ((rn | rm) & q & !is_long) {
--            return 1;
--        }
--        off_rn = vfp_reg_offset(1, rn);
--        off_rm = vfp_reg_offset(1, rm);
--    } else {
--        rn = VFP_SREG_N(insn);
--        rm = VFP_SREG_M(insn);
--        off_rn = vfp_reg_offset(0, rn);
--        off_rm = vfp_reg_offset(0, rm);
--    }
--
--    if (s->fp_excp_el) {
--        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
--                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
--        return 0;
--    }
--    if (!s->vfp_enabled) {
--        return 1;
--    }
--
--    opr_sz = (1 + q) * 8;
--    if (fn_gvec_ptr) {
--        TCGv_ptr ptr;
--        if (ptr_is_env) {
--            ptr = cpu_env;
--        } else {
--            ptr = get_fpstatus_ptr(1);
--        }
--        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
--                           opr_sz, opr_sz, data, fn_gvec_ptr);
--        if (!ptr_is_env) {
--            tcg_temp_free_ptr(ptr);
--        }
--    } else {
--        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
--                           opr_sz, opr_sz, data, fn_gvec);
--    }
--    return 0;
--}
--
- /* Advanced SIMD two registers and a scalar extension.
-  *  31             24   23  22   20   16   12  11   10   9    8        3     0
-  * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
-                     }
-                 }
-             }
--        } else if ((insn & 0x0e000a00) == 0x0c000800
--                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
--            if (disas_neon_insn_3same_ext(s, insn)) {
--                goto illegal_op;
--            }
--            return;
-         } else if ((insn & 0x0f000a00) == 0x0e000800
-                    && arm_dc_feature(s, ARM_FEATURE_V8)) {
-             if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
-             }
-             break;
-         }
--        if ((insn & 0xfe000a00) == 0xfc000800
-+        if ((insn & 0xff000a00) == 0xfe000800
-             && arm_dc_feature(s, ARM_FEATURE_V8)) {
-             /* The Thumb2 and ARM encodings are identical.  */
--            if (disas_neon_insn_3same_ext(s, insn)) {
--                goto illegal_op;
--            }
--        } else if ((insn & 0xff000a00) == 0xfe000800
--                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
--            /* The Thumb2 and ARM encodings are identical.  */
-             if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
-                 goto illegal_op;
-             }
---
-.20.1

-[PULL 27/39] target/arm: Convert VCMLA (scalar) to decodetree
+Deleted patch
-Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-9-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   |  5 +++++
- target/arm/translate-neon.inc.c | 40 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 26 +--------------------
-files changed, 46 insertions(+), 25 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@ VFML           1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
-                vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0
- VFML           1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
-+
-+VCMLA_scalar   1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
-+               vn=%vn_dp vd=%vd_dp size=0
-+VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VFML(DisasContext *s, arg_VFML *a)
-                        gen_helper_gvec_fmlal_a32);
-     return true;
- }
-+
-+static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
-+{
-+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
-+    int opr_sz;
-+    TCGv_ptr fpst;
-+
-+    if (!dc_isar_feature(aa32_vcma, s)) {
-+        return false;
-+    }
-+    if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vd | a->vn) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx
-+                   : gen_helper_gvec_fcmlah_idx);
-+    opr_sz = (1 + a->q) * 8;
-+    fpst = get_fpstatus_ptr(1);
-+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(1, a->vn),
-+                       vfp_reg_offset(1, a->vm),
-+                       fpst, opr_sz, opr_sz,
-+                       (a->index << 2) | a->rot, fn_gvec_ptr);
-+    tcg_temp_free_ptr(fpst);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
-     bool is_long = false, q = extract32(insn, 6, 1);
-     bool ptr_is_env = false;
--    if ((insn & 0xff000f10) == 0xfe000800) {
--        /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
--        int rot = extract32(insn, 20, 2);
--        int size = extract32(insn, 23, 1);
--        int index;
--
--        if (!dc_isar_feature(aa32_vcma, s)) {
--            return 1;
--        }
--        if (size == 0) {
--            if (!dc_isar_feature(aa32_fp16_arith, s)) {
--                return 1;
--            }
--            /* For fp16, rm is just Vm, and index is M.  */
--            rm = extract32(insn, 0, 4);
--            index = extract32(insn, 5, 1);
--        } else {
--            /* For fp32, rm is the usual M:Vm, and index is 0.  */
--            VFP_DREG_M(rm, insn);
--            index = 0;
--        }
--        data = (index << 2) | rot;
--        fn_gvec_ptr = (size ? gen_helper_gvec_fcmlas_idx
--                       : gen_helper_gvec_fcmlah_idx);
--    } else if ((insn & 0xffb00f00) == 0xfe200d00) {
-+    if ((insn & 0xffb00f00) == 0xfe200d00) {
-         /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
-         int u = extract32(insn, 4, 1);
---
-.20.1

-[PULL 28/39] target/arm: Convert V[US]DOT (scalar) to decodetree
+Deleted patch
-Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
-to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-10-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   |  3 +++
- target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 13 +-----------
-files changed, 39 insertions(+), 12 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@ VCMLA_scalar   1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
-                vn=%vn_dp vd=%vd_dp size=0
- VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0
-+
-+VDOT_scalar    1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
-+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
-     tcg_temp_free_ptr(fpst);
-     return true;
- }
-+
-+static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
-+{
-+    gen_helper_gvec_3 *fn_gvec;
-+    int opr_sz;
-+    TCGv_ptr fpst;
-+
-+    if (!dc_isar_feature(aa32_dp, s)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vd | a->vn) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    fn_gvec = a->u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
-+    opr_sz = (1 + a->q) * 8;
-+    fpst = get_fpstatus_ptr(1);
-+    tcg_gen_gvec_3_ool(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(1, a->vn),
-+                       vfp_reg_offset(1, a->rm),
-+                       opr_sz, opr_sz, a->index, fn_gvec);
-+    tcg_temp_free_ptr(fpst);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
-     bool is_long = false, q = extract32(insn, 6, 1);
-     bool ptr_is_env = false;
--    if ((insn & 0xffb00f00) == 0xfe200d00) {
--        /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
--        int u = extract32(insn, 4, 1);
--
--        if (!dc_isar_feature(aa32_dp, s)) {
--            return 1;
--        }
--        fn_gvec = u ? gen_helper_gvec_udot_idx_b : gen_helper_gvec_sdot_idx_b;
--        /* rm is just Vm, and index is M.  */
--        data = extract32(insn, 5, 1); /* index */
--        rm = extract32(insn, 0, 4);
--    } else if ((insn & 0xffa00f10) == 0xfe000810) {
-+    if ((insn & 0xffa00f10) == 0xfe000810) {
-         /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
-         int is_s = extract32(insn, 20, 1);
-         int vm20 = extract32(insn, 0, 3);
---
-.20.1

-[PULL 29/39] target/arm: Convert VFM[AS]L (scalar) to decodetree
+Deleted patch
-Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
-to decodetree. These are the last ones in the group so we can remove
-all the legacy decode for the group.
-Note that in disas_thumb2_insn() the parts of this encoding space
-where the decodetree decoder returns false will correctly be directed
-to illegal_op by the "(insn & (1 << 28))" check so they won't fall
-into disas_coproc_insn() by mistake.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-11-peter.maydell@linaro.org
----
- target/arm/neon-shared.decode   |   7 +++
- target/arm/translate-neon.inc.c |  32 ++++++++++
- target/arm/translate.c          | 107 +-------------------------------
-files changed, 40 insertions(+), 106 deletions(-)
-diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-shared.decode
-+++ b/target/arm/neon-shared.decode
-@@ -XXX,XX +XXX,XX @@ VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
- VDOT_scalar    1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
-                vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+
-+%vfml_scalar_q0_rm 0:3 5:1
-+%vfml_scalar_q1_index 5:1 3:1
-+VFML_scalar    1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1 index:1 ... \
-+               rm=%vfml_scalar_q0_rm vn=%vn_sp vd=%vd_dp q=0
-+VFML_scalar    1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \
-+               index=%vfml_scalar_q1_index vn=%vn_dp vd=%vd_dp q=1
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
-     tcg_temp_free_ptr(fpst);
-     return true;
- }
-+
-+static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
-+{
-+    int opr_sz;
-+
-+    if (!dc_isar_feature(aa32_fhm, s)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) {
-+        return false;
-+    }
-+
-+    if (a->vd & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    opr_sz = (1 + a->q) * 8;
-+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
-+                       vfp_reg_offset(a->q, a->vn),
-+                       vfp_reg_offset(a->q, a->rm),
-+                       cpu_env, opr_sz, opr_sz,
-+                       (a->index << 2) | a->s, /* is_2 == 0 */
-+                       gen_helper_gvec_fmlal_idx_a32);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
- }
- #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
--#define VFP_SREG(insn, bigbit, smallbit) \
--  ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
- #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
-     if (dc_isar_feature(aa32_simd_r32, s)) { \
-         reg = (((insn) >> (bigbit)) & 0x0f) \
-@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
-         reg = ((insn) >> (bigbit)) & 0x0f; \
-     }} while (0)
--#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
- #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
--#define VFP_SREG_N(insn) VFP_SREG(insn, 16,  7)
- #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16,  7)
--#define VFP_SREG_M(insn) VFP_SREG(insn,  0,  5)
- #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn,  0,  5)
- static void gen_neon_dup_low16(TCGv_i32 var)
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     return 0;
- }
--/* Advanced SIMD two registers and a scalar extension.
-- *  31             24   23  22   20   16   12  11   10   9    8        3     0
-- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
-- * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
-- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
-- *
-- */
--
--static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
--{
--    gen_helper_gvec_3 *fn_gvec = NULL;
--    gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
--    int rd, rn, rm, opr_sz, data;
--    int off_rn, off_rm;
--    bool is_long = false, q = extract32(insn, 6, 1);
--    bool ptr_is_env = false;
--
--    if ((insn & 0xffa00f10) == 0xfe000810) {
--        /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
--        int is_s = extract32(insn, 20, 1);
--        int vm20 = extract32(insn, 0, 3);
--        int vm3 = extract32(insn, 3, 1);
--        int m = extract32(insn, 5, 1);
--        int index;
--
--        if (!dc_isar_feature(aa32_fhm, s)) {
--            return 1;
--        }
--        if (q) {
--            rm = vm20;
--            index = m * 2 + vm3;
--        } else {
--            rm = vm20 * 2 + m;
--            index = vm3;
--        }
--        is_long = true;
--        data = (index << 2) | is_s; /* is_2 == 0 */
--        fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
--        ptr_is_env = true;
--    } else {
--        return 1;
--    }
--
--    VFP_DREG_D(rd, insn);
--    if (rd & q) {
--        return 1;
--    }
--    if (q || !is_long) {
--        VFP_DREG_N(rn, insn);
--        if (rn & q & !is_long) {
--            return 1;
--        }
--        off_rn = vfp_reg_offset(1, rn);
--        off_rm = vfp_reg_offset(1, rm);
--    } else {
--        rn = VFP_SREG_N(insn);
--        off_rn = vfp_reg_offset(0, rn);
--        off_rm = vfp_reg_offset(0, rm);
--    }
--    if (s->fp_excp_el) {
--        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
--                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
--        return 0;
--    }
--    if (!s->vfp_enabled) {
--        return 1;
--    }
--
--    opr_sz = (1 + q) * 8;
--    if (fn_gvec_ptr) {
--        TCGv_ptr ptr;
--        if (ptr_is_env) {
--            ptr = cpu_env;
--        } else {
--            ptr = get_fpstatus_ptr(1);
--        }
--        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
--                           opr_sz, opr_sz, data, fn_gvec_ptr);
--        if (!ptr_is_env) {
--            tcg_temp_free_ptr(ptr);
--        }
--    } else {
--        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
--                           opr_sz, opr_sz, data, fn_gvec);
--    }
--    return 0;
--}
--
- static int disas_coproc_insn(DisasContext *s, uint32_t insn)
- {
-     int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
-                     }
-                 }
-             }
--        } else if ((insn & 0x0f000a00) == 0x0e000800
--                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
--            if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
--                goto illegal_op;
--            }
--            return;
-         }
-         goto illegal_op;
-     }
-@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
-             }
-             break;
-         }
--        if ((insn & 0xff000a00) == 0xfe000800
--            && arm_dc_feature(s, ARM_FEATURE_V8)) {
--            /* The Thumb2 and ARM encodings are identical.  */
--            if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
--                goto illegal_op;
--            }
--        } else if (((insn >> 24) & 3) == 3) {
-+        if (((insn >> 24) & 3) == 3) {
-             /* Translate into the equivalent ARM encoding.  */
-             insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
-             if (disas_neon_data_insn(s, insn)) {
---
-.20.1

-[PULL 30/39] target/arm: Convert Neon load/store multiple structures to decodetree
+Deleted patch
-Convert the Neon "load/store multiple structures" insns to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-12-peter.maydell@linaro.org
----
- target/arm/neon-ls.decode       |   7 ++
- target/arm/translate-neon.inc.c | 124 ++++++++++++++++++++++++++++++++
- target/arm/translate.c          |  91 +----------------------
-files changed, 133 insertions(+), 89 deletions(-)
-diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-ls.decode
-+++ b/target/arm/neon-ls.decode
-@@ -XXX,XX +XXX,XX @@
- #   0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
- # This file works on the A32 encoding only; calling code for T32 has to
- # transform the insn into the A32 version first.
-+
-+%vd_dp  22:1 12:4
-+
-+# Neon load/store multiple structures
-+
-+VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
-+               vd=%vd_dp
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
-                        gen_helper_gvec_fmlal_idx_a32);
-     return true;
- }
-+
-+static struct {
-+    int nregs;
-+    int interleave;
-+    int spacing;
-+} const neon_ls_element_type[11] = {
-+    {1, 4, 1},
-+    {1, 4, 2},
-+    {4, 1, 1},
-+    {2, 2, 2},
-+    {1, 3, 1},
-+    {1, 3, 2},
-+    {3, 1, 1},
-+    {1, 1, 1},
-+    {1, 2, 1},
-+    {1, 2, 2},
-+    {2, 1, 1}
-+};
-+
-+static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn,
-+                                      int stride)
-+{
-+    if (rm != 15) {
-+        TCGv_i32 base;
-+
-+        base = load_reg(s, rn);
-+        if (rm == 13) {
-+            tcg_gen_addi_i32(base, base, stride);
-+        } else {
-+            TCGv_i32 index;
-+            index = load_reg(s, rm);
-+            tcg_gen_add_i32(base, base, index);
-+            tcg_temp_free_i32(index);
-+        }
-+        store_reg(s, rn, base);
-+    }
-+}
-+
-+static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
-+{
-+    /* Neon load/store multiple structures */
-+    int nregs, interleave, spacing, reg, n;
-+    MemOp endian = s->be_data;
-+    int mmu_idx = get_mem_index(s);
-+    int size = a->size;
-+    TCGv_i64 tmp64;
-+    TCGv_i32 addr, tmp;
-+
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist */
-+    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
-+        return false;
-+    }
-+    if (a->itype > 10) {
-+        return false;
-+    }
-+    /* Catch UNDEF cases for bad values of align field */
-+    switch (a->itype & 0xc) {
-+    case 4:
-+        if (a->align >= 2) {
-+            return false;
-+        }
-+        break;
-+    case 8:
-+        if (a->align == 3) {
-+            return false;
-+        }
-+        break;
-+    default:
-+        break;
-+    }
-+    nregs = neon_ls_element_type[a->itype].nregs;
-+    interleave = neon_ls_element_type[a->itype].interleave;
-+    spacing = neon_ls_element_type[a->itype].spacing;
-+    if (size == 3 && (interleave | spacing) != 1) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    /* For our purposes, bytes are always little-endian.  */
-+    if (size == 0) {
-+        endian = MO_LE;
-+    }
-+    /*
-+     * Consecutive little-endian elements from a single register
-+     * can be promoted to a larger little-endian operation.
-+     */
-+    if (interleave == 1 && endian == MO_LE) {
-+        size = 3;
-+    }
-+    tmp64 = tcg_temp_new_i64();
-+    addr = tcg_temp_new_i32();
-+    tmp = tcg_const_i32(1 << size);
-+    load_reg_var(s, addr, a->rn);
-+    for (reg = 0; reg < nregs; reg++) {
-+        for (n = 0; n < 8 >> size; n++) {
-+            int xs;
-+            for (xs = 0; xs < interleave; xs++) {
-+                int tt = a->vd + reg + spacing * xs;
-+
-+                if (a->l) {
-+                    gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
-+                    neon_store_element64(tt, n, size, tmp64);
-+                } else {
-+                    neon_load_element64(tmp64, tt, n, size);
-+                    gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
-+                }
-+                tcg_gen_add_i32(addr, addr, tmp);
-+            }
-+        }
-+    }
-+    tcg_temp_free_i32(addr);
-+    tcg_temp_free_i32(tmp);
-+    tcg_temp_free_i64(tmp64);
-+
-+    gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
-+    return true;
-+}
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
- }
--static struct {
--    int nregs;
--    int interleave;
--    int spacing;
--} const neon_ls_element_type[11] = {
--    {1, 4, 1},
--    {1, 4, 2},
--    {4, 1, 1},
--    {2, 2, 2},
--    {1, 3, 1},
--    {1, 3, 2},
--    {3, 1, 1},
--    {1, 1, 1},
--    {1, 2, 1},
--    {1, 2, 2},
--    {2, 1, 1}
--};
--
- /* Translate a NEON load/store element instruction.  Return nonzero if the
-    instruction is invalid.  */
- static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
- {
-     int rd, rn, rm;
--    int op;
-     int nregs;
--    int interleave;
--    int spacing;
-     int stride;
-     int size;
-     int reg;
-     int load;
--    int n;
-     int vec_size;
--    int mmu_idx;
--    MemOp endian;
-     TCGv_i32 addr;
-     TCGv_i32 tmp;
--    TCGv_i32 tmp2;
--    TCGv_i64 tmp64;
-     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-         return 1;
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
-     rn = (insn >> 16) & 0xf;
-     rm = insn & 0xf;
-     load = (insn & (1 << 21)) != 0;
--    endian = s->be_data;
--    mmu_idx = get_mem_index(s);
-     if ((insn & (1 << 23)) == 0) {
--        /* Load store all elements.  */
--        op = (insn >> 8) & 0xf;
--        size = (insn >> 6) & 3;
--        if (op > 10)
--            return 1;
--        /* Catch UNDEF cases for bad values of align field */
--        switch (op & 0xc) {
--        case 4:
--            if (((insn >> 5) & 1) == 1) {
--                return 1;
--            }
--            break;
--        case 8:
--            if (((insn >> 4) & 3) == 3) {
--                return 1;
--            }
--            break;
--        default:
--            break;
--        }
--        nregs = neon_ls_element_type[op].nregs;
--        interleave = neon_ls_element_type[op].interleave;
--        spacing = neon_ls_element_type[op].spacing;
--        if (size == 3 && (interleave | spacing) != 1) {
--            return 1;
--        }
--        /* For our purposes, bytes are always little-endian.  */
--        if (size == 0) {
--            endian = MO_LE;
--        }
--        /* Consecutive little-endian elements from a single register
--         * can be promoted to a larger little-endian operation.
--         */
--        if (interleave == 1 && endian == MO_LE) {
--            size = 3;
--        }
--        tmp64 = tcg_temp_new_i64();
--        addr = tcg_temp_new_i32();
--        tmp2 = tcg_const_i32(1 << size);
--        load_reg_var(s, addr, rn);
--        for (reg = 0; reg < nregs; reg++) {
--            for (n = 0; n < 8 >> size; n++) {
--                int xs;
--                for (xs = 0; xs < interleave; xs++) {
--                    int tt = rd + reg + spacing * xs;
--
--                    if (load) {
--                        gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
--                        neon_store_element64(tt, n, size, tmp64);
--                    } else {
--                        neon_load_element64(tmp64, tt, n, size);
--                        gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
--                    }
--                    tcg_gen_add_i32(addr, addr, tmp2);
--                }
--            }
--        }
--        tcg_temp_free_i32(addr);
--        tcg_temp_free_i32(tmp2);
--        tcg_temp_free_i64(tmp64);
--        stride = nregs * interleave * 8;
-+        /* Load store all elements -- handled already by decodetree */
-+        return 1;
-     } else {
-         size = (insn >> 10) & 3;
-         if (size == 3) {
---
-.20.1

-[PULL 33/39] target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
+Deleted patch
-Convert the Neon 3-reg-same VADD and VSUB insns to decodetree.
-Note that we don't need the neon_3r_sizes[op] check here because all
-size values are OK for VADD and VSUB; we'll add this when we convert
-the first insn that has size restrictions.
-For this we need one of the GVecGen*Fn typedefs currently in
-translate-a64.h; move them all to translate.h as a block so they
-are visible to the 32-bit decoder.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-15-peter.maydell@linaro.org
----
- target/arm/translate-a64.h      |  9 --------
- target/arm/translate.h          |  9 ++++++++
- target/arm/neon-dp.decode       | 17 +++++++++++++++
- target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 14 ++++--------
-files changed, 68 insertions(+), 19 deletions(-)
-diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.h
-+++ b/target/arm/translate-a64.h
-@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)
- bool disas_sve(DisasContext *, uint32_t);
--/* Note that the gvec expanders operate on offsets + sizes.  */
--typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
--typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
--                         uint32_t, uint32_t);
--typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
--                        uint32_t, uint32_t, uint32_t);
--typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
--                        uint32_t, uint32_t, uint32_t);
--
- #endif /* TARGET_ARM_TRANSLATE_A64_H */
-diff --git a/target/arm/translate.h b/target/arm/translate.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
-+++ b/target/arm/translate.h
-@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
- #define dc_isar_feature(name, ctx) \
-     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
-+/* Note that the gvec expanders operate on offsets + sizes.  */
-+typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
-+typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
-+                         uint32_t, uint32_t);
-+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
-+                        uint32_t, uint32_t, uint32_t);
-+typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
-+                        uint32_t, uint32_t, uint32_t);
-+
- #endif /* TARGET_ARM_TRANSLATE_H */
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@
- #
- # This file is processed by scripts/decodetree.py
- #
-+# VFP/Neon register fields; same as vfp.decode
-+%vm_dp  5:1 0:4
-+%vn_dp  7:1 16:4
-+%vd_dp  22:1 12:4
- # Encodings for Neon data processing instructions where the T32 encoding
- # is a simple transformation of the A32 encoding.
-@@ -XXX,XX +XXX,XX @@
- #   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
- # This file works on the A32 encoding only; calling code for T32 has to
- # transform the insn into the A32 version first.
-+
-+######################################################################
-+# 3-reg-same grouping:
-+# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
-+######################################################################
-+
-+&3same vm vn vd q size
-+
-+@3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
-+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+
-+VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
-+VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
-     return true;
- }
-+
-+static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
-+{
-+    int vec_size = a->q ? 16 : 8;
-+    int rd_ofs = neon_reg_offset(a->vd, 0);
-+    int rn_ofs = neon_reg_offset(a->vn, 0);
-+    int rm_ofs = neon_reg_offset(a->vm, 0);
-+
-+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-+        return false;
-+    }
-+
-+    /* UNDEF accesses to D16-D31 if they don't exist. */
-+    if (!dc_isar_feature(aa32_simd_r32, s) &&
-+        ((a->vd | a->vn | a->vm) & 0x10)) {
-+        return false;
-+    }
-+
-+    if ((a->vn | a->vm | a->vd) & a->q) {
-+        return false;
-+    }
-+
-+    if (!vfp_access_check(s)) {
-+        return true;
-+    }
-+
-+    fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
-+    return true;
-+}
-+
-+#define DO_3SAME(INSN, FUNC)                                            \
-+    static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a)        \
-+    {                                                                   \
-+        return do_3same(s, a, FUNC);                                    \
-+    }
-+
-+DO_3SAME(VADD, tcg_gen_gvec_add)
-+DO_3SAME(VSUB, tcg_gen_gvec_sub)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             }
-             return 0;
--        case NEON_3R_VADD_VSUB:
--            if (u) {
--                tcg_gen_gvec_sub(size, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--            } else {
--                tcg_gen_gvec_add(size, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--            }
--            return 0;
--
-         case NEON_3R_VQADD:
-             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-                            rn_ofs, rm_ofs, vec_size, vec_size,
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
-                            u ? &ushl_op[size] : &sshl_op[size]);
-             return 0;
-+
-+        case NEON_3R_VADD_VSUB:
-+            /* Already handled by decodetree */
-+            return 1;
-         }
-         if (size == 3) {
---
-.20.1

-[PULL 34/39] target/arm: Convert Neon 3-reg-same logic ops to decodetree
+Deleted patch
-Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
-Note that for the logic ops the 'size' field forms part of their
-decode and the actual operations are always bitwise.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-16-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       | 12 +++++++++++
- target/arm/translate-neon.inc.c | 19 +++++++++++++++++
- target/arm/translate.c          | 38 +--------------------------------
-files changed, 32 insertions(+), 37 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@
- @3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
-                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+@3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
-+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
-+
-+VAND_3s          1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
-+VBIC_3s          1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
-+VORR_3s          1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
-+VORN_3s          1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
-+VEOR_3s          1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
-+VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
-+VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
-+VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
-+
- VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
- VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
- DO_3SAME(VADD, tcg_gen_gvec_add)
- DO_3SAME(VSUB, tcg_gen_gvec_sub)
-+DO_3SAME(VAND, tcg_gen_gvec_and)
-+DO_3SAME(VBIC, tcg_gen_gvec_andc)
-+DO_3SAME(VORR, tcg_gen_gvec_or)
-+DO_3SAME(VORN, tcg_gen_gvec_orc)
-+DO_3SAME(VEOR, tcg_gen_gvec_xor)
-+
-+/* These insns are all gvec_bitsel but with the inputs in various orders. */
-+#define DO_3SAME_BITSEL(INSN, O1, O2, O3)                               \
-+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
-+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
-+                                uint32_t oprsz, uint32_t maxsz)         \
-+    {                                                                   \
-+        tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz);    \
-+    }                                                                   \
-+    DO_3SAME(INSN, gen_##INSN##_3s)
-+
-+DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
-+DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
-+DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             }
-             return 1;
--        case NEON_3R_LOGIC: /* Logic ops.  */
--            switch ((u << 2) | size) {
--            case 0: /* VAND */
--                tcg_gen_gvec_and(0, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--                break;
--            case 1: /* VBIC */
--                tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
--                                  vec_size, vec_size);
--                break;
--            case 2: /* VORR */
--                tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
--                                vec_size, vec_size);
--                break;
--            case 3: /* VORN */
--                tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--                break;
--            case 4: /* VEOR */
--                tcg_gen_gvec_xor(0, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--                break;
--            case 5: /* VBSL */
--                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rd_ofs, rn_ofs, rm_ofs,
--                                    vec_size, vec_size);
--                break;
--            case 6: /* VBIT */
--                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rn_ofs, rd_ofs,
--                                    vec_size, vec_size);
--                break;
--            case 7: /* VBIF */
--                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rd_ofs, rn_ofs,
--                                    vec_size, vec_size);
--                break;
--            }
--            return 0;
--
-         case NEON_3R_VQADD:
-             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-                            rn_ofs, rm_ofs, vec_size, vec_size,
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             return 0;
-         case NEON_3R_VADD_VSUB:
-+        case NEON_3R_LOGIC:
-             /* Already handled by decodetree */
-             return 1;
-         }
---
-.20.1

-[PULL 35/39] target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
+Deleted patch
-Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-17-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  5 +++++
- target/arm/translate-neon.inc.c | 14 ++++++++++++++
- target/arm/translate.c          | 21 ++-------------------
-files changed, 21 insertions(+), 19 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
- VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
- VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
-+VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
-+VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
-+VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
-+VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
-+
- VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
- VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ DO_3SAME(VEOR, tcg_gen_gvec_xor)
- DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
- DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
- DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
-+
-+#define DO_3SAME_NO_SZ_3(INSN, FUNC)                                    \
-+    static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a)        \
-+    {                                                                   \
-+        if (a->size == 3) {                                             \
-+            return false;                                               \
-+        }                                                               \
-+        return do_3same(s, a, FUNC);                                    \
-+    }
-+
-+DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
-+DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
-+DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
-+DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                              rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
-             return 0;
--        case NEON_3R_VMAX:
--            if (u) {
--                tcg_gen_gvec_umax(size, rd_ofs, rn_ofs, rm_ofs,
--                                  vec_size, vec_size);
--            } else {
--                tcg_gen_gvec_smax(size, rd_ofs, rn_ofs, rm_ofs,
--                                  vec_size, vec_size);
--            }
--            return 0;
--        case NEON_3R_VMIN:
--            if (u) {
--                tcg_gen_gvec_umin(size, rd_ofs, rn_ofs, rm_ofs,
--                                  vec_size, vec_size);
--            } else {
--                tcg_gen_gvec_smin(size, rd_ofs, rn_ofs, rm_ofs,
--                                  vec_size, vec_size);
--            }
--            return 0;
--
-         case NEON_3R_VSHL:
-             /* Note the operation is vshl vd,vm,vn */
-             tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-         case NEON_3R_VADD_VSUB:
-         case NEON_3R_LOGIC:
-+        case NEON_3R_VMAX:
-+        case NEON_3R_VMIN:
-             /* Already handled by decodetree */
-             return 1;
-         }
---
-.20.1

-[PULL 36/39] target/arm: Convert Neon 3-reg-same comparisons to decodetree
+Deleted patch
-Convert the Neon comparison ops in the 3-reg-same grouping
-to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-18-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  8 ++++++++
- target/arm/translate-neon.inc.c | 22 ++++++++++++++++++++++
- target/arm/translate.c          | 23 +++--------------------
-files changed, 33 insertions(+), 20 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
- VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
- VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
-+VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
-+VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
-+VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
-+VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
-+
- VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
- VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
- VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
-@@ -XXX,XX +XXX,XX @@ VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
- VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
- VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
-+
-+VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
-+VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
- DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
- DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
- DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
-+
-+#define DO_3SAME_CMP(INSN, COND)                                        \
-+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
-+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
-+                                uint32_t oprsz, uint32_t maxsz)         \
-+    {                                                                   \
-+        tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \
-+    }                                                                   \
-+    DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
-+
-+DO_3SAME_CMP(VCGT_S, TCG_COND_GT)
-+DO_3SAME_CMP(VCGT_U, TCG_COND_GTU)
-+DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
-+DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
-+DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
-+
-+static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
-+                         uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
-+{
-+    tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);
-+}
-+DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                            u ? &mls_op[size] : &mla_op[size]);
-             return 0;
--        case NEON_3R_VTST_VCEQ:
--            if (u) { /* VCEQ */
--                tcg_gen_gvec_cmp(TCG_COND_EQ, size, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--            } else { /* VTST */
--                tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
--                               vec_size, vec_size, &cmtst_op[size]);
--            }
--            return 0;
--
--        case NEON_3R_VCGT:
--            tcg_gen_gvec_cmp(u ? TCG_COND_GTU : TCG_COND_GT, size,
--                             rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
--            return 0;
--
--        case NEON_3R_VCGE:
--            tcg_gen_gvec_cmp(u ? TCG_COND_GEU : TCG_COND_GE, size,
--                             rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
--            return 0;
--
-         case NEON_3R_VSHL:
-             /* Note the operation is vshl vd,vm,vn */
-             tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-         case NEON_3R_LOGIC:
-         case NEON_3R_VMAX:
-         case NEON_3R_VMIN:
-+        case NEON_3R_VTST_VCEQ:
-+        case NEON_3R_VCGT:
-+        case NEON_3R_VCGE:
-             /* Already handled by decodetree */
-             return 1;
-         }
---
-.20.1

-[PULL 37/39] target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
+Deleted patch
-Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping
-to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-19-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  6 ++++++
- target/arm/translate-neon.inc.c | 15 +++++++++++++++
- target/arm/translate.c          | 14 ++------------
-files changed, 23 insertions(+), 12 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@
- @3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
-                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
-+VQADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
-+VQADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
-+
- @3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
-                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
-@@ -XXX,XX +XXX,XX @@ VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
- VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
- VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
-+VQSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
-+VQSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
-+
- VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
- VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
- VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
-     tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);
- }
- DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)
-+
-+#define DO_3SAME_GVEC4(INSN, OPARRAY)                                   \
-+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
-+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
-+                                uint32_t oprsz, uint32_t maxsz)         \
-+    {                                                                   \
-+        tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),           \
-+                       rn_ofs, rm_ofs, oprsz, maxsz, &OPARRAY[vece]);   \
-+    }                                                                   \
-+    DO_3SAME(INSN, gen_##INSN##_3s)
-+
-+DO_3SAME_GVEC4(VQADD_S, sqadd_op)
-+DO_3SAME_GVEC4(VQADD_U, uqadd_op)
-+DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
-+DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             }
-             return 1;
--        case NEON_3R_VQADD:
--            tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
--                           rn_ofs, rm_ofs, vec_size, vec_size,
--                           (u ? uqadd_op : sqadd_op) + size);
--            return 0;
--
--        case NEON_3R_VQSUB:
--            tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
--                           rn_ofs, rm_ofs, vec_size, vec_size,
--                           (u ? uqsub_op : sqsub_op) + size);
--            return 0;
--
-         case NEON_3R_VMUL: /* VMUL */
-             if (u) {
-                 /* Polynomial case allows only P8.  */
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-         case NEON_3R_VTST_VCEQ:
-         case NEON_3R_VCGT:
-         case NEON_3R_VCGE:
-+        case NEON_3R_VQADD:
-+        case NEON_3R_VQSUB:
-             /* Already handled by decodetree */
-             return 1;
-         }
---
-.20.1

-[PULL 38/39] target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
+Deleted patch
-Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
--reg-same grouping to decodetree.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20200430181003.21682-20-peter.maydell@linaro.org
----
- target/arm/neon-dp.decode       |  9 +++++++
- target/arm/translate-neon.inc.c | 44 +++++++++++++++++++++++++++++++++
- target/arm/translate.c          | 28 +++------------------
-files changed, 56 insertions(+), 25 deletions(-)
-diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/neon-dp.decode
-+++ b/target/arm/neon-dp.decode
-@@ -XXX,XX +XXX,XX @@ VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
- VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
- VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
-+VSHL_S_3s        1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same
-+VSHL_U_3s        1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same
-+
- VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
- VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
- VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
-@@ -XXX,XX +XXX,XX @@ VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
- VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
- VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
-+
-+VMLA_3s          1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
-+VMLS_3s          1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
-+
-+VMUL_3s          1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
-+VMUL_p_3s        1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
-diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-neon.inc.c
-+++ b/target/arm/translate-neon.inc.c
-@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
- DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
- DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
- DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
-+DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul)
- #define DO_3SAME_CMP(INSN, COND)                                        \
-     static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
-@@ -XXX,XX +XXX,XX @@ DO_3SAME_GVEC4(VQADD_S, sqadd_op)
- DO_3SAME_GVEC4(VQADD_U, uqadd_op)
- DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
- DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
-+
-+static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
-+                           uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
-+{
-+    tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
-+                       0, gen_helper_gvec_pmul_b);
-+}
-+
-+static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
-+{
-+    if (a->size != 0) {
-+        return false;
-+    }
-+    return do_3same(s, a, gen_VMUL_p_3s);
-+}
-+
-+#define DO_3SAME_GVEC3_NO_SZ_3(INSN, OPARRAY)                           \
-+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
-+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
-+                                uint32_t oprsz, uint32_t maxsz)         \
-+    {                                                                   \
-+        tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,                          \
-+                       oprsz, maxsz, &OPARRAY[vece]);                   \
-+    }                                                                   \
-+    DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
-+
-+
-+DO_3SAME_GVEC3_NO_SZ_3(VMLA, mla_op)
-+DO_3SAME_GVEC3_NO_SZ_3(VMLS, mls_op)
-+
-+#define DO_3SAME_GVEC3_SHIFT(INSN, OPARRAY)                             \
-+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
-+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
-+                                uint32_t oprsz, uint32_t maxsz)         \
-+    {                                                                   \
-+        /* Note the operation is vshl vd,vm,vn */                       \
-+        tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs,                          \
-+                       oprsz, maxsz, &OPARRAY[vece]);                   \
-+    }                                                                   \
-+    DO_3SAME(INSN, gen_##INSN##_3s)
-+
-+DO_3SAME_GVEC3_SHIFT(VSHL_S, sshl_op)
-+DO_3SAME_GVEC3_SHIFT(VSHL_U, ushl_op)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-             }
-             return 1;
--        case NEON_3R_VMUL: /* VMUL */
--            if (u) {
--                /* Polynomial case allows only P8.  */
--                if (size != 0) {
--                    return 1;
--                }
--                tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
--                                   0, gen_helper_gvec_pmul_b);
--            } else {
--                tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs,
--                                 vec_size, vec_size);
--            }
--            return 0;
--
--        case NEON_3R_VML: /* VMLA, VMLS */
--            tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
--                           u ? &mls_op[size] : &mla_op[size]);
--            return 0;
--
--        case NEON_3R_VSHL:
--            /* Note the operation is vshl vd,vm,vn */
--            tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
--                           u ? &ushl_op[size] : &sshl_op[size]);
--            return 0;
--
-         case NEON_3R_VADD_VSUB:
-         case NEON_3R_LOGIC:
-         case NEON_3R_VMAX:
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-         case NEON_3R_VCGE:
-         case NEON_3R_VQADD:
-         case NEON_3R_VQSUB:
-+        case NEON_3R_VMUL:
-+        case NEON_3R_VML:
-+        case NEON_3R_VSHL:
-             /* Already handled by decodetree */
-             return 1;
-         }
---
-.20.1

Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups.

thanks
-- PMM

The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835:

Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504

for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:

target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100)

----------------------------------------------------------------
target-arm queue:
 * Start of conversion of Neon insns to decodetree
 * versal board: support SD and RTC
 * Implement ARMv8.2-TTS2UXN
 * Make VQDMULL undefined when U=1
 * Some minor code cleanups

----------------------------------------------------------------
Edgar E. Iglesias (11):
      hw/arm: versal: Remove inclusion of arm_gicv3_common.h
      hw/arm: versal: Move misplaced comment
      hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal
      hw/arm: versal: Embed the UARTs into the SoC type
      hw/arm: versal: Embed the GEMs into the SoC type
      hw/arm: versal: Embed the ADMAs into the SoC type
      hw/arm: versal: Embed the APUs into the SoC type
      hw/arm: versal: Add support for SD
      hw/arm: versal: Add support for the RTC
      hw/arm: versal-virt: Add support for SD
      hw/arm: versal-virt: Add support for the RTC

Fredrik Strupe (1):
      target/arm: Make VQDMULL undefined when U=1

Peter Maydell (25):
      target/arm: Don't use a TLB for ARMMMUIdx_Stage2
      target/arm: Use enum constant in get_phys_addr_lpae() call
      target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()
      target/arm: Implement ARMv8.2-TTS2UXN
      target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0
      target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check
      target/arm: Don't allow Thumb Neon insns without FEATURE_NEON
      target/arm: Add stubs for AArch32 Neon decodetree
      target/arm: Convert VCMLA (vector) to decodetree
      target/arm: Convert VCADD (vector) to decodetree
      target/arm: Convert V[US]DOT (vector) to decodetree
      target/arm: Convert VFM[AS]L (vector) to decodetree
      target/arm: Convert VCMLA (scalar) to decodetree
      target/arm: Convert V[US]DOT (scalar) to decodetree
      target/arm: Convert VFM[AS]L (scalar) to decodetree
      target/arm: Convert Neon load/store multiple structures to decodetree
      target/arm: Convert Neon 'load single structure to all lanes' to decodetree
      target/arm: Convert Neon 'load/store single structure' to decodetree
      target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree
      target/arm: Convert Neon 3-reg-same logic ops to decodetree
      target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree
      target/arm: Convert Neon 3-reg-same comparisons to decodetree
      target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree
      target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree
      target/arm: Move gen_ function typedefs to translate.h

Philippe Mathieu-Daudé (2):
      hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string
      target/arm: Use uint64_t for midr field in CPU state struct

include/hw/arm/xlnx-versal.h    |  31 +-
 target/arm/cpu-param.h          |   2 +-
 target/arm/cpu.h                |  38 ++-
 target/arm/translate-a64.h      |   9 -
 target/arm/translate.h          |  26 ++
 target/arm/neon-dp.decode       |  86 +++++
 target/arm/neon-ls.decode       |  52 +++
 target/arm/neon-shared.decode   |  66 ++++
 hw/arm/mps2-tz.c                |   2 +-
 hw/arm/xlnx-versal-virt.c       |  74 ++++-
 hw/arm/xlnx-versal.c            | 115 +++++--
 target/arm/cpu.c                |   3 +-
 target/arm/cpu64.c              |   8 +-
 target/arm/helper.c             | 183 ++++------
 target/arm/translate-a64.c      |  17 -
 target/arm/translate-neon.inc.c | 714 +++++++++++++++++++++++++++++++++++++++
 target/arm/translate-vfp.inc.c  |   6 -
 target/arm/translate.c          | 716 +++-------------------------------------
 target/arm/Makefile.objs        |  18 +
 19 files changed, 1302 insertions(+), 864 deletions(-)
 create mode 100644 target/arm/neon-dp.decode
 create mode 100644 target/arm/neon-ls.decode
 create mode 100644 target/arm/neon-shared.decode
 create mode 100644 target/arm/translate-neon.inc.c

From: Fredrik Strupe <fredrik@strupe.net>

According to Arm ARM, VQDMULL is only valid when U=0, while having
U=1 is unallocated.

Signed-off-by: Fredrik Strupe <fredrik@strupe.net>
Fixes: 695272dcb976 ("target-arm: Handle UNDEF cases for Neon 3-regs-different-widths")
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     {0, 0, 0, 0}, /* VMLSL */
                     {0, 0, 0, 9}, /* VQDMLSL */
                     {0, 0, 0, 0}, /* Integer VMULL */
-                    {0, 0, 0, 1}, /* VQDMULL */
+                    {0, 0, 0, 9}, /* VQDMULL */
                     {0, 0, 0, 0xa}, /* Polynomial VMULL */
                     {0, 0, 0, 7}, /* Reserved: always UNDEF */
                 };
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

By using the TYPE_* definitions for devices, we can:
 - quickly find where devices are used with 'git-grep'
 - easily rename a device (one-line change).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200428154650.21991-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/mps2-tz.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
         exit(EXIT_FAILURE);
     }
 
-    sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
+    sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,
                           sizeof(mms->iotkit), mmc->armsse_type);
     iotkitdev = DEVICE(&mms->iotkit);
     object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
-- 
2.20.1

We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU
TLB.  However we never actually use the TLB -- all stage 2 lookups
are done by direct calls to get_phys_addr_lpae() followed by a
physical address load via address_space_ld*().

Remove Stage2 from the list of ARM MMU indexes which correspond to
real core MMU indexes, and instead put it in the set of "NOTLB" ARM
MMU indexes.

This allows us to drop NB_MMU_MODES to 11.  It also means we can
safely add support for the ARMv8.3-TTS2UXN extension, which adds
permission bits to the stage 2 descriptors which define execute
permission separatel for EL0 and EL1; supporting that while keeping
Stage2 in a QEMU TLB would require us to use separate TLBs for
"Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a
lot of extra complication given we aren't even using the QEMU TLB.

In the process of updating the comment on our MMU index use,
fix a couple of other minor errors:
 * NS EL2 EL2&0 was missing from the list in the comment
 * some text hadn't been updated from when we bumped NB_MMU_MODES
   above 8

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200330210400.11724-2-peter.maydell@linaro.org
---
 target/arm/cpu-param.h |   2 +-
 target/arm/cpu.h       |  21 +++++---
 target/arm/helper.c    | 112 ++++-------------------------------------
 3 files changed, 27 insertions(+), 108 deletions(-)

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -XXX,XX +XXX,XX @@
 # define TARGET_PAGE_BITS_MIN  10
 #endif
 
-#define NB_MMU_MODES 12
+#define NB_MMU_MODES 11
 
 #endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  *     handling via the TLB. The only way to do a stage 1 translation without
  *     the immediate stage 2 translation is via the ATS or AT system insns,
  *     which can be slow-pathed and always do a page table walk.
+ *     The only use of stage 2 translations is either as part of an s1+2
+ *     lookup or when loading the descriptors during a stage 1 page table walk,
+ *     and in both those cases we don't use the TLB.
  *  4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
  *     translation regimes, because they map reasonably well to each other
  *     and they can't both be active at the same time.
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
  * NS EL1 EL1&0 stage 1+2 +PAN
  * NS EL0 EL2&0
+ * NS EL2 EL2&0
  * NS EL2 EL2&0 +PAN
  * NS EL2 (aka NS PL2)
  * S EL0 EL1&0 (aka S PL0)
  * S EL1 EL1&0 (not used if EL3 is 32 bit)
  * S EL1 EL1&0 +PAN
  * S EL3 (aka S PL1)
- * NS EL1&0 stage 2
  *
- * for a total of 12 different mmu_idx.
+ * for a total of 11 different mmu_idx.
  *
  * R profile CPUs have an MPU, but can use the same set of MMU indexes
  * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
  * are not quite the same -- different CPU types (most notably M profile
  * vs A/R profile) would like to use MMU indexes with different semantics,
  * but since we don't ever need to use all of those in a single CPU we
- * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
+ * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
+ * modes + total number of M profile MMU modes". The lower bits of
  * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
  * the same for any particular CPU.
  * Variables of type ARMMUIdx are always full values, and the core
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
     ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
     ARMMMUIdx_SE3        = 10 | ARM_MMU_IDX_A,
 
-    ARMMMUIdx_Stage2     = 11 | ARM_MMU_IDX_A,
-
     /*
      * These are not allocated TLBs and are used only for AT system
      * instructions or for the first stage of an S12 page table walk.
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
     ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
     ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
     ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
+    /*
+     * Not allocated a TLB: used only for second stage of an S12 page
+     * table walk, or for descriptor loads during first stage of an S1
+     * page table walk. Note that if we ever want to have a TLB for this
+     * then various TLB flush insns which currently are no-ops or flush
+     * only stage 1 MMU indexes will need to change to flush stage 2.
+     */
+    ARMMMUIdx_Stage2     = 3 | ARM_MMU_IDX_NOTLB,
 
     /*
      * M-profile.
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
     TO_CORE_BIT(SE10_1),
     TO_CORE_BIT(SE10_1_PAN),
     TO_CORE_BIT(SE3),
-    TO_CORE_BIT(Stage2),
 
     TO_CORE_BIT(MUser),
     TO_CORE_BIT(MPriv),
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx(cs,
                         ARMMMUIdxBit_E10_1 |
                         ARMMMUIdxBit_E10_1_PAN |
-                        ARMMMUIdxBit_E10_0 |
-                        ARMMMUIdxBit_Stage2);
+                        ARMMMUIdxBit_E10_0);
 }
 
 static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
     tlb_flush_by_mmuidx_all_cpus_synced(cs,
                                         ARMMMUIdxBit_E10_1 |
                                         ARMMMUIdxBit_E10_1_PAN |
-                                        ARMMMUIdxBit_E10_0 |
-                                        ARMMMUIdxBit_Stage2);
+                                        ARMMMUIdxBit_E10_0);
 }
 
-static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                            uint64_t value)
-{
-    /* Invalidate by IPA. This has to invalidate any structures that
-     * contain only stage 2 translation information, but does not need
-     * to apply to structures that contain combined stage 1 and stage 2
-     * translation information.
-     * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
-     */
-    CPUState *cs = env_cpu(env);
-    uint64_t pageaddr;
-
-    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
-        return;
-    }
-
-    pageaddr = sextract64(value << 12, 0, 40);
-
-    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
-}
-
-static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                               uint64_t value)
-{
-    CPUState *cs = env_cpu(env);
-    uint64_t pageaddr;
-
-    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
-        return;
-    }
-
-    pageaddr = sextract64(value << 12, 0, 40);
-
-    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                             ARMMMUIdxBit_Stage2);
-}
 
 static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
                               uint64_t value)
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         tlb_flush_by_mmuidx(cs,
                             ARMMMUIdxBit_E10_1 |
                             ARMMMUIdxBit_E10_1_PAN |
-                            ARMMMUIdxBit_E10_0 |
-                            ARMMMUIdxBit_Stage2);
+                            ARMMMUIdxBit_E10_0);
         raw_write(env, ri, value);
     }
 }
@@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env)
         return ARMMMUIdxBit_SE10_1 |
                ARMMMUIdxBit_SE10_1_PAN |
                ARMMMUIdxBit_SE10_0;
-    } else if (arm_feature(env, ARM_FEATURE_EL2)) {
-        return ARMMMUIdxBit_E10_1 |
-               ARMMMUIdxBit_E10_1_PAN |
-               ARMMMUIdxBit_E10_0 |
-               ARMMMUIdxBit_Stage2;
     } else {
         return ARMMMUIdxBit_E10_1 |
                ARMMMUIdxBit_E10_1_PAN |
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                              ARMMMUIdxBit_SE3);
 }
 
-static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                    uint64_t value)
-{
-    /* Invalidate by IPA. This has to invalidate any structures that
-     * contain only stage 2 translation information, but does not need
-     * to apply to structures that contain combined stage 1 and stage 2
-     * translation information.
-     * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
-     */
-    ARMCPU *cpu = env_archcpu(env);
-    CPUState *cs = CPU(cpu);
-    uint64_t pageaddr;
-
-    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
-        return;
-    }
-
-    pageaddr = sextract64(value << 12, 0, 48);
-
-    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);
-}
-
-static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
-                                      uint64_t value)
-{
-    CPUState *cs = env_cpu(env);
-    uint64_t pageaddr;
-
-    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
-        return;
-    }
-
-    pageaddr = sextract64(value << 12, 0, 48);
-
-    tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
-                                             ARMMMUIdxBit_Stage2);
-}
-
 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
                                       bool isread)
 {
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbi_aa64_vae1_write },
     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
-      .writefn = tlbi_aa64_ipas2e1is_write },
+      .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
-      .writefn = tlbi_aa64_ipas2e1is_write },
+      .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
       .access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbi_aa64_alle1is_write },
     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
-      .writefn = tlbi_aa64_ipas2e1_write },
+      .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
-      .access = PL2_W, .type = ARM_CP_NO_RAW,
-      .writefn = tlbi_aa64_ipas2e1_write },
+      .access = PL2_W, .type = ARM_CP_NOP },
     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
       .access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
       .writefn = tlbimva_hyp_is_write },
     { .name = "TLBIIPAS2",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
-      .writefn = tlbiipas2_write },
+      .type = ARM_CP_NOP, .access = PL2_W },
     { .name = "TLBIIPAS2IS",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
-      .writefn = tlbiipas2_is_write },
+      .type = ARM_CP_NOP, .access = PL2_W },
     { .name = "TLBIIPAS2L",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
-      .writefn = tlbiipas2_write },
+      .type = ARM_CP_NOP, .access = PL2_W },
     { .name = "TLBIIPAS2LIS",
       .cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
-      .type = ARM_CP_NO_RAW, .access = PL2_W,
-      .writefn = tlbiipas2_is_write },
+      .type = ARM_CP_NOP, .access = PL2_W },
     /* 32 bit cache operations */
     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
       .type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },
-- 
2.20.1

The access_type argument to get_phys_addr_lpae() is an MMUAccessType;
use the enum constant MMU_DATA_LOAD rather than a literal 0 when we
call it in S1_ptw_translate().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200330210400.11724-3-peter.maydell@linaro.org
---
 target/arm/helper.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
             pcacheattrs = &cacheattrs;
         }
 
-        ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa,
-                                 &txattrs, &s2prot, &s2size, fi, pcacheattrs);
+        ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
+                                 &s2pa, &txattrs, &s2prot, &s2size, fi,
+                                 pcacheattrs);
         if (ret) {
             assert(fi->type != ARMFault_None);
             fi->s2addr = addr;
-- 
2.20.1

For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know
whether the stage 1 access is for EL0 or not, because whether
exec permission is given can depend on whether this is an EL0
or EL1 access. Add a new argument to get_phys_addr_lpae() so
the call sites can pass this information in.

Since get_phys_addr_lpae() doesn't already have a doc comment,
add one so we have a place to put the documentation of the
semantics of the new s1_is_el0 argument.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200330210400.11724-4-peter.maydell@linaro.org
---
 target/arm/helper.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@
 
 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                               bool s1_is_el0,
                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
                                target_ulong *page_size_ptr,
                                ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
         }
 
         ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,
+                                 false,
                                  &s2pa, &txattrs, &s2prot, &s2size, fi,
                                  pcacheattrs);
         if (ret) {
@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
     };
 }
 
+/**
+ * get_phys_addr_lpae: perform one stage of page table walk, LPAE format
+ *
+ * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
+ * prot and page_size may not be filled in, and the populated fsr value provides
+ * information on why the translation aborted, in the format of a long-format
+ * DFSR/IFSR fault register, with the following caveats:
+ *  * the WnR bit is never set (the caller must do this).
+ *
+ * @env: CPUARMState
+ * @address: virtual address to get physical address for
+ * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH
+ * @mmu_idx: MMU index indicating required translation regime
+ * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table
+ *             walk), must be true if this is stage 2 of a stage 1+2 walk for an
+ *             EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.
+ * @phys_ptr: set to the physical address corresponding to the virtual address
+ * @attrs: set to the memory transaction attributes to use
+ * @prot: set to the permissions for the page containing phys_ptr
+ * @page_size_ptr: set to the size of the page containing phys_ptr
+ * @fi: set to fault info if the translation fails
+ * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
+ */
 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
                                MMUAccessType access_type, ARMMMUIdx mmu_idx,
+                               bool s1_is_el0,
                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
                                target_ulong *page_size_ptr,
                                ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
 
             /* S1 is done. Now do S2 translation.  */
             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,
+                                     mmu_idx == ARMMMUIdx_E10_0,
                                      phys_ptr, attrs, &s2_prot,
                                      page_size, fi,
                                      cacheattrs != NULL ? &cacheattrs2 : NULL);
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
     }
 
     if (regime_using_lpae_format(env, mmu_idx)) {
-        return get_phys_addr_lpae(env, address, access_type, mmu_idx,
+        return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
                                   phys_ptr, attrs, prot, page_size,
                                   fi, cacheattrs);
     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
-- 
2.20.1

The ARMv8.2-TTS2UXN feature extends the XN field in stage 2
translation table descriptors from just bit [54] to bits [54:53],
allowing stage 2 to control execution permissions separately for EL0
and EL1. Implement the new semantics of the XN field and enable
the feature for our 'max' CPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200330210400.11724-5-peter.maydell@linaro.org
---
 target/arm/cpu.h    | 15 +++++++++++++++
 target/arm/cpu.c    |  1 +
 target/arm/cpu64.c  |  2 ++
 target/arm/helper.c | 37 +++++++++++++++++++++++++++++++------
 4 files changed, 49 insertions(+), 6 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
 }
 
+static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
+}
+
 /*
  * 64-bit feature tests via id registers.
  */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
 }
 
+static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
+}
+
 /*
  * Feature tests for "does this exist in either 32-bit or 64-bit?"
  */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
     return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
 }
 
+static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
+{
+    return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
+}
+
 /*
  * Forward to the above feature tests given an ARMCPU pointer.
  */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
             t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
             t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
             t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+            t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
             cpu->isar.id_mmfr4 = t;
         }
 #endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
         t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
         t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
+        t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
         cpu->isar.id_aa64mmfr1 = t;
 
         t = cpu->isar.id_aa64mmfr2;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
         u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
         u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
+        u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
         cpu->isar.id_mmfr4 = u;
 
         u = cpu->isar.id_aa64dfr0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
  *
  * @env:     CPUARMState
  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
- * @xn:      XN (execute-never) bit
+ * @xn:      XN (execute-never) bits
+ * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0
  */
-static int get_S2prot(CPUARMState *env, int s2ap, int xn)
+static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)
 {
     int prot = 0;
 
@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn)
     if (s2ap & 2) {
         prot |= PAGE_WRITE;
     }
-    if (!xn) {
-        if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
+
+    if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {
+        switch (xn) {
+        case 0:
             prot |= PAGE_EXEC;
+            break;
+        case 1:
+            if (s1_is_el0) {
+                prot |= PAGE_EXEC;
+            }
+            break;
+        case 2:
+            break;
+        case 3:
+            if (!s1_is_el0) {
+                prot |= PAGE_EXEC;
+            }
+            break;
+        default:
+            g_assert_not_reached();
+        }
+    } else {
+        if (!extract32(xn, 1, 1)) {
+            if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {
+                prot |= PAGE_EXEC;
+            }
         }
     }
     return prot;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
     }
 
     ap = extract32(attrs, 4, 2);
-    xn = extract32(attrs, 12, 1);
 
     if (mmu_idx == ARMMMUIdx_Stage2) {
         ns = true;
-        *prot = get_S2prot(env, ap, xn);
+        xn = extract32(attrs, 11, 2);
+        *prot = get_S2prot(env, ap, xn, s1_is_el0);
     } else {
         ns = extract32(attrs, 3, 1);
+        xn = extract32(attrs, 12, 1);
         pxn = extract32(attrs, 11, 1);
         *prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
     }
-- 
2.20.1

In aarch64_max_initfn() we update both 32-bit and 64-bit ID
registers.  The intended pattern is that for 64-bit ID registers we
use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
registers use FIELD_DP32 and the uint32_t 'u' register.  For
ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of
this 64-bit ID register would end up always zero.  Luckily at the
moment that's what they should be anyway, so this bug has no visible
effects.

Use the right-sized variable.

Fixes: 3bec78447a958d481991
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200423110915.10527-1-peter.maydell@linaro.org
---
 target/arm/cpu64.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
         cpu->isar.id_mmfr4 = u;
 
-        u = cpu->isar.id_aa64dfr0;
-        u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
-        cpu->isar.id_aa64dfr0 = u;
+        t = cpu->isar.id_aa64dfr0;
+        t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+        cpu->isar.id_aa64dfr0 = t;
 
         u = cpu->isar.id_dfr0;
         u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.
Represent it in QEMU's ARMCPU struct with a uint64_t, not a
uint32_t.

This fixes an error when compiling with -Werror=conversion
because we were manipulating the register value using a
local uint64_t variable:

target/arm/cpu64.c: In function ‘aarch64_max_initfn’:
  target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]
    628 |         cpu->midr = t;
        |                     ^

and future-proofs us against a possible future architecture
change using some of the top 32 bits.

Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20200428172634.29707-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h | 2 +-
 target/arm/cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
         uint64_t id_aa64dfr0;
         uint64_t id_aa64dfr1;
     } isar;
-    uint32_t midr;
+    uint64_t midr;
     uint32_t revidr;
     uint32_t reset_fpsid;
     uint32_t ctr;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
 static Property arm_cpu_properties[] = {
     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
-    DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
+    DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),
     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
                         mp_affinity, ARM64_AFFINITY_INVALID),
     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Move misplaced comment.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-3-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-versal.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
 
         obj = object_new(XLNX_VERSAL_ACPU_TYPE);
         if (!obj) {
-            /* Secondary CPUs start in PSCI powered-down state */
             error_report("Unable to create apu.cpu[%d] of type %s",
                          i, XLNX_VERSAL_ACPU_TYPE);
             exit(EXIT_FAILURE);
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
         object_property_set_int(obj, s->cfg.psci_conduit,
                                 "psci-conduit", &error_abort);
         if (i) {
+            /* Secondary CPUs start in PSCI powered-down state */
             object_property_set_bool(obj, true,
                                      "start-powered-off", &error_abort);
         }
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Fix typo xlnx-ve -> xlnx-versal.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-4-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-versal-virt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
         psci_conduit = QEMU_PSCI_CONDUIT_SMC;
     }
 
-    sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,
+    sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc,
                           sizeof(s->soc), TYPE_XLNX_VERSAL);
     object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),
                              "ddr", &error_abort);
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the UARTs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-5-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  3 ++-
 hw/arm/xlnx-versal.c         | 12 ++++++------
 2 files changed, 8 insertions(+), 7 deletions(-)

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the GEMs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-6-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  3 ++-
 hw/arm/xlnx-versal.c         | 15 ++++++++-------
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/boot.h"
 #include "hw/intc/arm_gicv3.h"
 #include "hw/char/pl011.h"
+#include "hw/net/cadence_gem.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
 #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
 
         struct {
             PL011State uart[XLNX_VERSAL_NR_UARTS];
-            SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
+            CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];
             SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
         } iou;
     } lpd;
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)
         DeviceState *dev;
         MemoryRegion *mr;
 
-        dev = qdev_create(NULL, "cadence_gem");
-        s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);
-        object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
+        sysbus_init_child_obj(OBJECT(s), name,
+                              &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]),
+                              TYPE_CADENCE_GEM);
+        dev = DEVICE(&s->lpd.iou.gem[i]);
         if (nd->used) {
             qemu_check_nic_model(nd, "cadence_gem");
             qdev_set_nic_properties(dev, nd);
         }
-        object_property_set_int(OBJECT(s->lpd.iou.gem[i]),
+        object_property_set_int(OBJECT(dev),
                                 2, "num-priority-queues",
                                 &error_abort);
-        object_property_set_link(OBJECT(s->lpd.iou.gem[i]),
+        object_property_set_link(OBJECT(dev),
                                  OBJECT(&s->mr_ps), "dma",
                                  &error_abort);
         qdev_init_nofail(dev);
 
-        mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);
+        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
         memory_region_add_subregion(&s->mr_ps, addrs[i], mr);
 
-        sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);
+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);
         g_free(name);
     }
 }
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the ADMAs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-7-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  3 ++-
 hw/arm/xlnx-versal.c         | 14 +++++++-------
 2 files changed, 9 insertions(+), 8 deletions(-)

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the APUs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-8-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  2 +-
 hw/arm/xlnx-versal-virt.c    |  4 ++--
 hw/arm/xlnx-versal.c         | 19 +++++--------------
 3 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
     struct {
         struct {
             MemoryRegion mr;
-            ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS];
+            ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
             GICv3State gic;
         } apu;
     } fpd;
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
     s->binfo.get_dtb = versal_virt_get_dtb;
     s->binfo.modify_dtb = versal_virt_modify_dtb;
     if (machine->kernel_filename) {
-        arm_load_kernel(s->soc.fpd.apu.cpu[0], machine, &s->binfo);
+        arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo);
     } else {
-        AddressSpace *as = arm_boot_address_space(s->soc.fpd.apu.cpu[0],
+        AddressSpace *as = arm_boot_address_space(&s->soc.fpd.apu.cpu[0],
                                                   &s->binfo);
         /* Some boot-loaders (e.g u-boot) don't like blobs at address 0 (NULL).
          * Offset things by 4K.  */
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
 
     for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
         Object *obj;
-        char *name;
-
-        obj = object_new(XLNX_VERSAL_ACPU_TYPE);
-        if (!obj) {
-            error_report("Unable to create apu.cpu[%d] of type %s",
-                         i, XLNX_VERSAL_ACPU_TYPE);
-            exit(EXIT_FAILURE);
-        }
-
-        name = g_strdup_printf("apu-cpu[%d]", i);
-        object_property_add_child(OBJECT(s), name, obj, &error_fatal);
-        g_free(name);
 
+        object_initialize_child(OBJECT(s), "apu-cpu[*]",
+                                &s->fpd.apu.cpu[i], sizeof(s->fpd.apu.cpu[i]),
+                                XLNX_VERSAL_ACPU_TYPE, &error_abort, NULL);
+        obj = OBJECT(&s->fpd.apu.cpu[i]);
         object_property_set_int(obj, s->cfg.psci_conduit,
                                 "psci-conduit", &error_abort);
         if (i) {
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
         object_property_set_link(obj, OBJECT(&s->fpd.apu.mr), "memory",
                                  &error_abort);
         object_property_set_bool(obj, true, "realized", &error_fatal);
-        s->fpd.apu.cpu[i] = ARM_CPU(obj);
     }
 }
 
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
     }
 
     for (i = 0; i < nr_apu_cpus; i++) {
-        DeviceState *cpudev = DEVICE(s->fpd.apu.cpu[i]);
+        DeviceState *cpudev = DEVICE(&s->fpd.apu.cpu[i]);
         int ppibase = XLNX_VERSAL_NR_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
         qemu_irq maint_irq;
         int ti;
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add support for SD.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-9-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h | 12 ++++++++++++
 hw/arm/xlnx-versal.c         | 31 +++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/sysbus.h"
 #include "hw/arm/boot.h"
+#include "hw/sd/sdhci.h"
 #include "hw/intc/arm_gicv3.h"
 #include "hw/char/pl011.h"
 #include "hw/dma/xlnx-zdma.h"
@@ -XXX,XX +XXX,XX @@
 #define XLNX_VERSAL_NR_UARTS   2
 #define XLNX_VERSAL_NR_GEMS    2
 #define XLNX_VERSAL_NR_ADMAS   8
+#define XLNX_VERSAL_NR_SDS     2
 #define XLNX_VERSAL_NR_IRQS    192
 
 typedef struct Versal {
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
         } iou;
     } lpd;
 
+    /* The Platform Management Controller subsystem.  */
+    struct {
+        struct {
+            SDHCIState sd[XLNX_VERSAL_NR_SDS];
+        } iou;
+    } pmc;
+
     struct {
         MemoryRegion *mr_ddr;
         uint32_t psci_conduit;
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
 #define VERSAL_GEM1_IRQ_0          58
 #define VERSAL_GEM1_WAKE_IRQ_0     59
 #define VERSAL_ADMA_IRQ_0          60
+#define VERSAL_SD0_IRQ_0           126
 
 /* Architecturally reserved IRQs suitable for virtualization.  */
 #define VERSAL_RSVD_IRQ_FIRST 111
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
 #define MM_FPD_CRF                  0xfd1a0000U
 #define MM_FPD_CRF_SIZE             0x140000
 
+#define MM_PMC_SD0                  0xf1040000U
+#define MM_PMC_SD0_SIZE             0x10000
 #define MM_PMC_CRP                  0xf1260000U
 #define MM_PMC_CRP_SIZE             0x10000
 #endif
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)
     }
 }
 
+#define SDHCI_CAPABILITIES  0x280737ec6481 /* Same as on ZynqMP.  */
+static void versal_create_sds(Versal *s, qemu_irq *pic)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(s->pmc.iou.sd); i++) {
+        DeviceState *dev;
+        MemoryRegion *mr;
+
+        sysbus_init_child_obj(OBJECT(s), "sd[*]",
+                              &s->pmc.iou.sd[i], sizeof(s->pmc.iou.sd[i]),
+                              TYPE_SYSBUS_SDHCI);
+        dev = DEVICE(&s->pmc.iou.sd[i]);
+
+        object_property_set_uint(OBJECT(dev),
+                                 3, "sd-spec-version", &error_fatal);
+        object_property_set_uint(OBJECT(dev), SDHCI_CAPABILITIES, "capareg",
+                                 &error_fatal);
+        object_property_set_uint(OBJECT(dev), UHS_I, "uhs", &error_fatal);
+        qdev_init_nofail(dev);
+
+        mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+        memory_region_add_subregion(&s->mr_ps,
+                                    MM_PMC_SD0 + i * MM_PMC_SD0_SIZE, mr);
+
+        sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
+                           pic[VERSAL_SD0_IRQ_0 + i * 2]);
+    }
+}
+
 /* This takes the board allocated linear DDR memory and creates aliases
  * for each split DDR range/aperture on the Versal address map.
  */
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_uarts(s, pic);
     versal_create_gems(s, pic);
     versal_create_admas(s, pic);
+    versal_create_sds(s, pic);
     versal_map_ddr(s);
     versal_unimp(s);
 
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

hw/arm: versal: Add support for the RTC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-10-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  8 ++++++++
 hw/arm/xlnx-versal.c         | 21 +++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/char/pl011.h"
 #include "hw/dma/xlnx-zdma.h"
 #include "hw/net/cadence_gem.h"
+#include "hw/rtc/xlnx-zynqmp-rtc.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
 #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
         struct {
             SDHCIState sd[XLNX_VERSAL_NR_SDS];
         } iou;
+
+        XlnxZynqMPRTC rtc;
     } pmc;
 
     struct {
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
 #define VERSAL_GEM1_IRQ_0          58
 #define VERSAL_GEM1_WAKE_IRQ_0     59
 #define VERSAL_ADMA_IRQ_0          60
+#define VERSAL_RTC_APB_ERR_IRQ     121
 #define VERSAL_SD0_IRQ_0           126
+#define VERSAL_RTC_ALARM_IRQ       142
+#define VERSAL_RTC_SECONDS_IRQ     143
 
 /* Architecturally reserved IRQs suitable for virtualization.  */
 #define VERSAL_RSVD_IRQ_FIRST 111
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
 #define MM_PMC_SD0_SIZE             0x10000
 #define MM_PMC_CRP                  0xf1260000U
 #define MM_PMC_CRP_SIZE             0x10000
+#define MM_PMC_RTC                  0xf12a0000
+#define MM_PMC_RTC_SIZE             0x10000
 #endif
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_sds(Versal *s, qemu_irq *pic)
     }
 }
 
+static void versal_create_rtc(Versal *s, qemu_irq *pic)
+{
+    SysBusDevice *sbd;
+    MemoryRegion *mr;
+
+    sysbus_init_child_obj(OBJECT(s), "rtc", &s->pmc.rtc, sizeof(s->pmc.rtc),
+                          TYPE_XLNX_ZYNQMP_RTC);
+    sbd = SYS_BUS_DEVICE(&s->pmc.rtc);
+    qdev_init_nofail(DEVICE(sbd));
+
+    mr = sysbus_mmio_get_region(sbd, 0);
+    memory_region_add_subregion(&s->mr_ps, MM_PMC_RTC, mr);
+
+    /*
+     * TODO: Connect the ALARM and SECONDS interrupts once our RTC model
+     * supports them.
+     */
+    sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]);
+}
+
 /* This takes the board allocated linear DDR memory and creates aliases
  * for each split DDR range/aperture on the Versal address map.
  */
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_gems(s, pic);
     versal_create_admas(s, pic);
     versal_create_sds(s, pic);
+    versal_create_rtc(s, pic);
     versal_map_ddr(s);
     versal_unimp(s);
 
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add support for SD.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-11-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-versal-virt.c | 46 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/sysbus-fdt.h"
 #include "hw/arm/fdt.h"
 #include "cpu.h"
+#include "hw/qdev-properties.h"
 #include "hw/arm/xlnx-versal.h"
 
 #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
@@ -XXX,XX +XXX,XX @@ static void fdt_add_zdma_nodes(VersalVirt *s)
     }
 }
 
+static void fdt_add_sd_nodes(VersalVirt *s)
+{
+    const char clocknames[] = "clk_xin\0clk_ahb";
+    const char compat[] = "arasan,sdhci-8.9a";
+    int i;
+
+    for (i = ARRAY_SIZE(s->soc.pmc.iou.sd) - 1; i >= 0; i--) {
+        uint64_t addr = MM_PMC_SD0 + MM_PMC_SD0_SIZE * i;
+        char *name = g_strdup_printf("/sdhci@%" PRIx64, addr);
+
+        qemu_fdt_add_subnode(s->fdt, name);
+
+        qemu_fdt_setprop_cells(s->fdt, name, "clocks",
+                               s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
+        qemu_fdt_setprop(s->fdt, name, "clock-names",
+                         clocknames, sizeof(clocknames));
+        qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+                               GIC_FDT_IRQ_TYPE_SPI, VERSAL_SD0_IRQ_0 + i * 2,
+                               GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+        qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                     2, addr, 2, MM_PMC_SD0_SIZE);
+        qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
+        g_free(name);
+    }
+}
+
 static void fdt_nop_memory_nodes(void *fdt, Error **errp)
 {
     Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
     }
 }
 
+static void sd_plugin_card(SDHCIState *sd, DriveInfo *di)
+{
+    BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
+    DeviceState *card;
+
+    card = qdev_create(qdev_get_child_bus(DEVICE(sd), "sd-bus"), TYPE_SD_CARD);
+    object_property_add_child(OBJECT(sd), "card[*]", OBJECT(card),
+                              &error_fatal);
+    qdev_prop_set_drive(card, "drive", blk, &error_fatal);
+    object_property_set_bool(OBJECT(card), true, "realized", &error_fatal);
+}
+
 static void versal_virt_init(MachineState *machine)
 {
     VersalVirt *s = XLNX_VERSAL_VIRT_MACHINE(machine);
     int psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
+    int i;
 
     /*
      * If the user provides an Operating System to be loaded, we expect them
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
     fdt_add_gic_nodes(s);
     fdt_add_timer_nodes(s);
     fdt_add_zdma_nodes(s);
+    fdt_add_sd_nodes(s);
     fdt_add_cpu_nodes(s, psci_conduit);
     fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
     memory_region_add_subregion_overlap(get_system_memory(),
                                         0, &s->soc.fpd.apu.mr, 0);
 
+    /* Plugin SD cards.  */
+    for (i = 0; i < ARRAY_SIZE(s->soc.pmc.iou.sd); i++) {
+        sd_plugin_card(&s->soc.pmc.iou.sd[i], drive_get_next(IF_SD));
+    }
+
     s->binfo.ram_size = machine->ram_size;
     s->binfo.loader_start = 0x0;
     s->binfo.get_dtb = versal_virt_get_dtb;
-- 
2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add support for the RTC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200427181649.26851-12-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-versal-virt.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_sd_nodes(VersalVirt *s)
     }
 }
 
+static void fdt_add_rtc_node(VersalVirt *s)
+{
+    const char compat[] = "xlnx,zynqmp-rtc";
+    const char interrupt_names[] = "alarm\0sec";
+    char *name = g_strdup_printf("/rtc@%x", MM_PMC_RTC);
+
+    qemu_fdt_add_subnode(s->fdt, name);
+
+    qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
+                           GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_ALARM_IRQ,
+                           GIC_FDT_IRQ_FLAGS_LEVEL_HI,
+                           GIC_FDT_IRQ_TYPE_SPI, VERSAL_RTC_SECONDS_IRQ,
+                           GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+    qemu_fdt_setprop(s->fdt, name, "interrupt-names",
+                     interrupt_names, sizeof(interrupt_names));
+    qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
+                                 2, MM_PMC_RTC, 2, MM_PMC_RTC_SIZE);
+    qemu_fdt_setprop(s->fdt, name, "compatible", compat, sizeof(compat));
+    g_free(name);
+}
+
 static void fdt_nop_memory_nodes(void *fdt, Error **errp)
 {
     Error *err = NULL;
@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)
     fdt_add_timer_nodes(s);
     fdt_add_zdma_nodes(s);
     fdt_add_sd_nodes(s);
+    fdt_add_rtc_node(s);
     fdt_add_cpu_nodes(s, psci_conduit);
     fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz);
     fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz);
-- 
2.20.1

Somewhere along theline we accidentally added a duplicate
"using D16-D31 when they don't exist" check to do_vfm_dp()
(probably an artifact of a patchseries rebase). Remove it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200430181003.21682-2-peter.maydell@linaro.org
---
 target/arm/translate-vfp.inc.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -XXX,XX +XXX,XX @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool neg_d)
         return false;
     }
 
-    /* UNDEF accesses to D16-D31 if they don't exist. */
-    if (!dc_isar_feature(aa32_simd_r32, s) &&
-        ((a->vd | a->vn | a->vm) & 0x10)) {
-        return false;
-    }
-
     if (!vfp_access_check(s)) {
         return true;
     }
-- 
2.20.1

We were accidentally permitting decode of Thumb Neon insns even if
the CPU didn't have the FEATURE_NEON bit set, because the feature
check was being done before the call to disas_neon_data_insn() and
disas_neon_ls_insn() in the Arm decoder but was omitted from the
Thumb decoder.  Push the feature bit check down into the called
functions so it is done for both Arm and Thumb encodings.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200430181003.21682-3-peter.maydell@linaro.org
---
 target/arm/translate.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
     TCGv_i32 tmp2;
     TCGv_i64 tmp64;
 
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return 1;
+    }
+
     /* FIXME: this access check should not take precedence over UNDEF
      * for invalid encodings; we will generate incorrect syndrome information
      * for attempts to execute invalid vfp/neon encodings with FP disabled.
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     TCGv_ptr ptr1, ptr2, ptr3;
     TCGv_i64 tmp64;
 
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return 1;
+    }
+
     /* FIXME: this access check should not take precedence over UNDEF
      * for invalid encodings; we will generate incorrect syndrome information
      * for attempts to execute invalid vfp/neon encodings with FP disabled.
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
 
         if (((insn >> 25) & 7) == 1) {
             /* NEON Data processing.  */
-            if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-                goto illegal_op;
-            }
-
             if (disas_neon_data_insn(s, insn)) {
                 goto illegal_op;
             }
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
         }
         if ((insn & 0x0f100000) == 0x04000000) {
             /* NEON load/store.  */
-            if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-                goto illegal_op;
-            }
-
             if (disas_neon_ls_insn(s, insn)) {
                 goto illegal_op;
             }
-- 
2.20.1

Add the infrastructure for building and invoking a decodetree decoder
for the AArch32 Neon encodings.  At the moment the new decoder covers
nothing, so we always fall back to the existing hand-written decode.

We follow the same pattern we did for the VFP decodetree conversion
(commit 78e138bc1f672c145ef6ace74617d and following): code that deals
with Neon will be moving gradually out to translate-neon.vfp.inc,
which we #include into translate.c.

In order to share the decode files between A32 and T32, we
split Neon into 3 parts:
 * data-processing
 * load-store
 * 'shared' encodings

The first two groups of instructions have similar but not identical
A32 and T32 encodings, so we need to manually transform the T32
encoding into the A32 one before calling the decoder; the third group
covers the Neon instructions which are identical in A32 and T32.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-4-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 29 ++++++++++++++++++++++++++
 target/arm/neon-ls.decode       | 29 ++++++++++++++++++++++++++
 target/arm/neon-shared.decode   | 27 +++++++++++++++++++++++++
 target/arm/translate-neon.inc.c | 32 +++++++++++++++++++++++++++++
 target/arm/translate.c          | 36 +++++++++++++++++++++++++++++++--
 target/arm/Makefile.objs        | 18 +++++++++++++++++
 6 files changed, 169 insertions(+), 2 deletions(-)
 create mode 100644 target/arm/neon-dp.decode
 create mode 100644 target/arm/neon-ls.decode
 create mode 100644 target/arm/neon-shared.decode
 create mode 100644 target/arm/translate-neon.inc.c

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@
+# AArch32 Neon data-processing instruction descriptions
+#
+#  Copyright (c) 2020 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
+
+# Encodings for Neon data processing instructions where the T32 encoding
+# is a simple transformation of the A32 encoding.
+# More specifically, this file covers instructions where the A32 encoding is
+#   0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
+# and the T32 encoding is
+#   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
+# This file works on the A32 encoding only; calling code for T32 has to
+# transform the insn into the A32 version first.
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/neon-ls.decode
@@ -XXX,XX +XXX,XX @@
+# AArch32 Neon load/store instruction descriptions
+#
+#  Copyright (c) 2020 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
+
+# Encodings for Neon load/store instructions where the T32 encoding
+# is a simple transformation of the A32 encoding.
+# More specifically, this file covers instructions where the A32 encoding is
+#   0b1111_0100_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
+# and the T32 encoding is
+#   0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
+# This file works on the A32 encoding only; calling code for T32 has to
+# transform the insn into the A32 version first.
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@
+# AArch32 Neon instruction descriptions
+#
+#  Copyright (c) 2020 Linaro, Ltd
+#
+# This library is free software; you can redistribute it and/or
+# modify it under the terms of the GNU Lesser General Public
+# License as published by the Free Software Foundation; either
+# version 2 of the License, or (at your option) any later version.
+#
+# This library is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# Lesser General Public License for more details.
+#
+# You should have received a copy of the GNU Lesser General Public
+# License along with this library; if not, see <http://www.gnu.org/licenses/>.
+
+#
+# This file is processed by scripts/decodetree.py
+#
+
+# Encodings for Neon instructions whose encoding is the same for
+# both A32 and T32.
+
+# More specifically, this covers:
+# 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
+# 3same ext:       0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@
+/*
+ *  ARM translation: AArch32 Neon instructions
+ *
+ *  Copyright (c) 2003 Fabrice Bellard
+ *  Copyright (c) 2005-2007 CodeSourcery
+ *  Copyright (c) 2007 OpenedHand, Ltd.
+ *  Copyright (c) 2020 Linaro, Ltd.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * This file is intended to be included from translate.c; it uses
+ * some macros and definitions provided by that file.
+ * It might be possible to convert it to a standalone .c file eventually.
+ */
+
+/* Include the generated Neon decoder */
+#include "decode-neon-dp.inc.c"
+#include "decode-neon-ls.inc.c"
+#include "decode-neon-shared.inc.c"
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
 
 #define ARM_CP_RW_BIT   (1 << 20)
 
-/* Include the VFP decoder */
+/* Include the VFP and Neon decoders */
 #include "translate-vfp.inc.c"
+#include "translate-neon.inc.c"
 
 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
 {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
         /* Unconditional instructions.  */
         /* TODO: Perhaps merge these into one decodetree output file.  */
         if (disas_a32_uncond(s, insn) ||
-            disas_vfp_uncond(s, insn)) {
+            disas_vfp_uncond(s, insn) ||
+            disas_neon_dp(s, insn) ||
+            disas_neon_ls(s, insn) ||
+            disas_neon_shared(s, insn)) {
             return;
         }
         /* fall back to legacy decoder */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
         ARCH(6T2);
     }
 
+    if ((insn & 0xef000000) == 0xef000000) {
+        /*
+         * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
+         * transform into
+         * A32 encodings 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
+         */
+        uint32_t a32_insn = (insn & 0xe2ffffff) |
+            ((insn & (1 << 28)) >> 4) | (1 << 28);
+
+        if (disas_neon_dp(s, a32_insn)) {
+            return;
+        }
+    }
+
+    if ((insn & 0xff100000) == 0xf9000000) {
+        /*
+         * T32 encodings 0b1111_1001_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
+         * transform into
+         * A32 encodings 0b1111_0100_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq
+         */
+        uint32_t a32_insn = (insn & 0x00ffffff) | 0xf4000000;
+
+        if (disas_neon_ls(s, a32_insn)) {
+            return;
+        }
+    }
+
     /*
      * TODO: Perhaps merge these into one decodetree output file.
      * Note disas_vfp is written for a32 with cond field in the
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
      */
     if (disas_t32(s, insn) ||
         disas_vfp_uncond(s, insn) ||
+        disas_neon_shared(s, insn) ||
         ((insn >> 28) == 0xe && disas_vfp(s, insn))) {
         return;
     }
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -XXX,XX +XXX,XX @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
 	  $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
+target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
+	$(call quiet-command,\
+	  $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
+	  "GEN", $(TARGET_DIR)$@)
+
+target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
+	$(call quiet-command,\
+	  $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
+	  "GEN", $(TARGET_DIR)$@)
+
+target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
+	$(call quiet-command,\
+	  $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
+	  "GEN", $(TARGET_DIR)$@)
+
 target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
@@ -XXX,XX +XXX,XX @@ target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
 	  "GEN", $(TARGET_DIR)$@)
 
 target/arm/translate-sve.o: target/arm/decode-sve.inc.c
+target/arm/translate.o: target/arm/decode-neon-shared.inc.c
+target/arm/translate.o: target/arm/decode-neon-dp.inc.c
+target/arm/translate.o: target/arm/decode-neon-ls.inc.c
 target/arm/translate.o: target/arm/decode-vfp.inc.c
 target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
 target/arm/translate.o: target/arm/decode-a32.inc.c
-- 
2.20.1

Convert the VCMLA (vector) insns in the 3same extension group to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-5-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   | 11 ++++++++++
 target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 11 +---------
 3 files changed, 49 insertions(+), 10 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@
 # More specifically, this covers:
 # 2reg scalar ext: 0b1111_1110_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
 # 3same ext:       0b1111_110x_xxxx_xxxx_xxxx_1x0x_xxxx_xxxx
+
+# VFP/Neon register fields; same as vfp.decode
+%vm_dp  5:1 0:4
+%vm_sp  0:4 5:1
+%vn_dp  7:1 16:4
+%vn_sp  16:4 7:1
+%vd_dp  22:1 12:4
+%vd_sp  12:4 22:1
+
+VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@
 #include "decode-neon-dp.inc.c"
 #include "decode-neon-ls.inc.c"
 #include "decode-neon-shared.inc.c"
+
+static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
+{
+    int opr_sz;
+    TCGv_ptr fpst;
+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
+
+    if (!dc_isar_feature(aa32_vcma, s)
+        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vn | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vn | a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    opr_sz = (1 + a->q) * 8;
+    fpst = get_fpstatus_ptr(1);
+    fn_gvec_ptr = a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+                       vfp_reg_offset(1, a->vn),
+                       vfp_reg_offset(1, a->vm),
+                       fpst, opr_sz, opr_sz, a->rot,
+                       fn_gvec_ptr);
+    tcg_temp_free_ptr(fpst);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
     bool is_long = false, q = extract32(insn, 6, 1);
     bool ptr_is_env = false;
 
-    if ((insn & 0xfe200f10) == 0xfc200800) {
-        /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
-        int size = extract32(insn, 20, 1);
-        data = extract32(insn, 23, 2); /* rot */
-        if (!dc_isar_feature(aa32_vcma, s)
-            || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
-            return 1;
-        }
-        fn_gvec_ptr = size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcmlah;
-    } else if ((insn & 0xfea00f10) == 0xfc800800) {
+    if ((insn & 0xfea00f10) == 0xfc800800) {
         /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
         int size = extract32(insn, 20, 1);
         data = extract32(insn, 24, 1); /* rot */
-- 
2.20.1

Convert the VCADD (vector) insns to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-6-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |  3 +++
 target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 11 +---------
 3 files changed, 41 insertions(+), 10 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@
 
 VCMLA          1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
                vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
     tcg_temp_free_ptr(fpst);
     return true;
 }
+
+static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
+{
+    int opr_sz;
+    TCGv_ptr fpst;
+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
+
+    if (!dc_isar_feature(aa32_vcma, s)
+        || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vn | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vn | a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    opr_sz = (1 + a->q) * 8;
+    fpst = get_fpstatus_ptr(1);
+    fn_gvec_ptr = a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+                       vfp_reg_offset(1, a->vn),
+                       vfp_reg_offset(1, a->vm),
+                       fpst, opr_sz, opr_sz, a->rot,
+                       fn_gvec_ptr);
+    tcg_temp_free_ptr(fpst);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
     bool is_long = false, q = extract32(insn, 6, 1);
     bool ptr_is_env = false;
 
-    if ((insn & 0xfea00f10) == 0xfc800800) {
-        /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
-        int size = extract32(insn, 20, 1);
-        data = extract32(insn, 24, 1); /* rot */
-        if (!dc_isar_feature(aa32_vcma, s)
-            || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
-            return 1;
-        }
-        fn_gvec_ptr = size ? gen_helper_gvec_fcadds : gen_helper_gvec_fcaddh;
-    } else if ((insn & 0xfeb00f00) == 0xfc200d00) {
+    if ((insn & 0xfeb00f00) == 0xfc200d00) {
         /* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
         bool u = extract32(insn, 4, 1);
         if (!dc_isar_feature(aa32_dp, s)) {
-- 
2.20.1

Convert the V[US]DOT (vector) insns to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-7-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |  4 ++++
 target/arm/translate-neon.inc.c | 32 ++++++++++++++++++++++++++++++++
 target/arm/translate.c          |  9 +--------
 3 files changed, 37 insertions(+), 8 deletions(-)

Convert the VFM[AS]L (vector) insns to decodetree.  This is the last
insn in the legacy decoder for the 3same_ext group, so we can
delete the legacy decoder function for the group entirely.

Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false will correctly be directed
to illegal_op by the "(insn & (1 << 28))" check so they won't fall
into disas_coproc_insn() by mistake.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-8-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |  6 +++
 target/arm/translate-neon.inc.c | 31 +++++++++++
 target/arm/translate.c          | 92 +--------------------------------
 3 files changed, 38 insertions(+), 91 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@ VCADD          1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
 # VUDOT and VSDOT
 VDOT           1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
                vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+# VFM[AS]L
+VFML           1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
+               vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0
+VFML           1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
                        opr_sz, opr_sz, 0, fn_gvec);
     return true;
 }
+
+static bool trans_VFML(DisasContext *s, arg_VFML *a)
+{
+    int opr_sz;
+
+    if (!dc_isar_feature(aa32_fhm, s)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        (a->vd & 0x10)) {
+        return false;
+    }
+
+    if (a->vd & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    opr_sz = (1 + a->q) * 8;
+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+                       vfp_reg_offset(a->q, a->vn),
+                       vfp_reg_offset(a->q, a->vm),
+                       cpu_env, opr_sz, opr_sz, a->s, /* is_2 == 0 */
+                       gen_helper_gvec_fmlal_a32);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     return 0;
 }
 
-/* Advanced SIMD three registers of the same length extension.
- *  31           25    23  22    20   16   12  11   10   9    8        3     0
- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
- * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+
- */
-static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
-{
-    gen_helper_gvec_3 *fn_gvec = NULL;
-    gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
-    int rd, rn, rm, opr_sz;
-    int data = 0;
-    int off_rn, off_rm;
-    bool is_long = false, q = extract32(insn, 6, 1);
-    bool ptr_is_env = false;
-
-    if ((insn & 0xff300f10) == 0xfc200810) {
-        /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
-        int is_s = extract32(insn, 23, 1);
-        if (!dc_isar_feature(aa32_fhm, s)) {
-            return 1;
-        }
-        is_long = true;
-        data = is_s; /* is_2 == 0 */
-        fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
-        ptr_is_env = true;
-    } else {
-        return 1;
-    }
-
-    VFP_DREG_D(rd, insn);
-    if (rd & q) {
-        return 1;
-    }
-    if (q || !is_long) {
-        VFP_DREG_N(rn, insn);
-        VFP_DREG_M(rm, insn);
-        if ((rn | rm) & q & !is_long) {
-            return 1;
-        }
-        off_rn = vfp_reg_offset(1, rn);
-        off_rm = vfp_reg_offset(1, rm);
-    } else {
-        rn = VFP_SREG_N(insn);
-        rm = VFP_SREG_M(insn);
-        off_rn = vfp_reg_offset(0, rn);
-        off_rm = vfp_reg_offset(0, rm);
-    }
-
-    if (s->fp_excp_el) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
-        return 0;
-    }
-    if (!s->vfp_enabled) {
-        return 1;
-    }
-
-    opr_sz = (1 + q) * 8;
-    if (fn_gvec_ptr) {
-        TCGv_ptr ptr;
-        if (ptr_is_env) {
-            ptr = cpu_env;
-        } else {
-            ptr = get_fpstatus_ptr(1);
-        }
-        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
-                           opr_sz, opr_sz, data, fn_gvec_ptr);
-        if (!ptr_is_env) {
-            tcg_temp_free_ptr(ptr);
-        }
-    } else {
-        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
-                           opr_sz, opr_sz, data, fn_gvec);
-    }
-    return 0;
-}
-
 /* Advanced SIMD two registers and a scalar extension.
  *  31             24   23  22   20   16   12  11   10   9    8        3     0
  * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                     }
                 }
             }
-        } else if ((insn & 0x0e000a00) == 0x0c000800
-                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
-            if (disas_neon_insn_3same_ext(s, insn)) {
-                goto illegal_op;
-            }
-            return;
         } else if ((insn & 0x0f000a00) == 0x0e000800
                    && arm_dc_feature(s, ARM_FEATURE_V8)) {
             if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
             }
             break;
         }
-        if ((insn & 0xfe000a00) == 0xfc000800
+        if ((insn & 0xff000a00) == 0xfe000800
             && arm_dc_feature(s, ARM_FEATURE_V8)) {
             /* The Thumb2 and ARM encodings are identical.  */
-            if (disas_neon_insn_3same_ext(s, insn)) {
-                goto illegal_op;
-            }
-        } else if ((insn & 0xff000a00) == 0xfe000800
-                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
-            /* The Thumb2 and ARM encodings are identical.  */
             if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
                 goto illegal_op;
             }
-- 
2.20.1

Convert VCMLA (scalar) in the 2reg-scalar-ext group to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-9-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |  5 +++++
 target/arm/translate-neon.inc.c | 40 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 26 +--------------------
 3 files changed, 46 insertions(+), 25 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@ VFML           1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
                vm=%vm_sp vn=%vn_sp vd=%vd_dp q=0
 VFML           1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
                vm=%vm_dp vn=%vn_dp vd=%vd_dp q=1
+
+VCMLA_scalar   1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \
+               vn=%vn_dp vd=%vd_dp size=0
+VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
+               vm=%vm_dp vn=%vn_dp vd=%vd_dp size=1 index=0
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VFML(DisasContext *s, arg_VFML *a)
                        gen_helper_gvec_fmlal_a32);
     return true;
 }
+
+static bool trans_VCMLA_scalar(DisasContext *s, arg_VCMLA_scalar *a)
+{
+    gen_helper_gvec_3_ptr *fn_gvec_ptr;
+    int opr_sz;
+    TCGv_ptr fpst;
+
+    if (!dc_isar_feature(aa32_vcma, s)) {
+        return false;
+    }
+    if (a->size == 0 && !dc_isar_feature(aa32_fp16_arith, s)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vn | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vd | a->vn) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    fn_gvec_ptr = (a->size ? gen_helper_gvec_fcmlas_idx
+                   : gen_helper_gvec_fcmlah_idx);
+    opr_sz = (1 + a->q) * 8;
+    fpst = get_fpstatus_ptr(1);
+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+                       vfp_reg_offset(1, a->vn),
+                       vfp_reg_offset(1, a->vm),
+                       fpst, opr_sz, opr_sz,
+                       (a->index << 2) | a->rot, fn_gvec_ptr);
+    tcg_temp_free_ptr(fpst);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
     bool is_long = false, q = extract32(insn, 6, 1);
     bool ptr_is_env = false;
 
-    if ((insn & 0xff000f10) == 0xfe000800) {
-        /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
-        int rot = extract32(insn, 20, 2);
-        int size = extract32(insn, 23, 1);
-        int index;
-
-        if (!dc_isar_feature(aa32_vcma, s)) {
-            return 1;
-        }
-        if (size == 0) {
-            if (!dc_isar_feature(aa32_fp16_arith, s)) {
-                return 1;
-            }
-            /* For fp16, rm is just Vm, and index is M.  */
-            rm = extract32(insn, 0, 4);
-            index = extract32(insn, 5, 1);
-        } else {
-            /* For fp32, rm is the usual M:Vm, and index is 0.  */
-            VFP_DREG_M(rm, insn);
-            index = 0;
-        }
-        data = (index << 2) | rot;
-        fn_gvec_ptr = (size ? gen_helper_gvec_fcmlas_idx
-                       : gen_helper_gvec_fcmlah_idx);
-    } else if ((insn & 0xffb00f00) == 0xfe200d00) {
+    if ((insn & 0xffb00f00) == 0xfe200d00) {
         /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
         int u = extract32(insn, 4, 1);
 
-- 
2.20.1

Convert the V[US]DOT (scalar) insns in the 2reg-scalar-ext group
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-10-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |  3 +++
 target/arm/translate-neon.inc.c | 35 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 13 +-----------
 3 files changed, 39 insertions(+), 12 deletions(-)

Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
to decodetree. These are the last ones in the group so we can remove
all the legacy decode for the group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-11-peter.maydell@linaro.org
---
 target/arm/neon-shared.decode   |   7 +++
 target/arm/translate-neon.inc.c |  32 ++++++++++
 target/arm/translate.c          | 107 +-------------------------------
 3 files changed, 40 insertions(+), 106 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -XXX,XX +XXX,XX @@ VCMLA_scalar   1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \
 
 VDOT_scalar    1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
                vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+%vfml_scalar_q0_rm 0:3 5:1
+%vfml_scalar_q1_index 5:1 3:1
+VFML_scalar    1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1 index:1 ... \
+               rm=%vfml_scalar_q0_rm vn=%vn_sp vd=%vd_dp q=0
+VFML_scalar    1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \
+               index=%vfml_scalar_q1_index vn=%vn_dp vd=%vd_dp q=1
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)
     tcg_temp_free_ptr(fpst);
     return true;
 }
+
+static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
+{
+    int opr_sz;
+
+    if (!dc_isar_feature(aa32_fhm, s)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) {
+        return false;
+    }
+
+    if (a->vd & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    opr_sz = (1 + a->q) * 8;
+    tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+                       vfp_reg_offset(a->q, a->vn),
+                       vfp_reg_offset(a->q, a->rm),
+                       cpu_env, opr_sz, opr_sz,
+                       (a->index << 2) | a->s, /* is_2 == 0 */
+                       gen_helper_gvec_fmlal_idx_a32);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
 }
 
 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
-#define VFP_SREG(insn, bigbit, smallbit) \
-  ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
     if (dc_isar_feature(aa32_simd_r32, s)) { \
         reg = (((insn) >> (bigbit)) & 0x0f) \
@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
         reg = ((insn) >> (bigbit)) & 0x0f; \
     }} while (0)
 
-#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
-#define VFP_SREG_N(insn) VFP_SREG(insn, 16,  7)
 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16,  7)
-#define VFP_SREG_M(insn) VFP_SREG(insn,  0,  5)
 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn,  0,  5)
 
 static void gen_neon_dup_low16(TCGv_i32 var)
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
     return 0;
 }
 
-/* Advanced SIMD two registers and a scalar extension.
- *  31             24   23  22   20   16   12  11   10   9    8        3     0
- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
- * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |
- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+
- *
- */
-
-static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
-{
-    gen_helper_gvec_3 *fn_gvec = NULL;
-    gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
-    int rd, rn, rm, opr_sz, data;
-    int off_rn, off_rm;
-    bool is_long = false, q = extract32(insn, 6, 1);
-    bool ptr_is_env = false;
-
-    if ((insn & 0xffa00f10) == 0xfe000810) {
-        /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
-        int is_s = extract32(insn, 20, 1);
-        int vm20 = extract32(insn, 0, 3);
-        int vm3 = extract32(insn, 3, 1);
-        int m = extract32(insn, 5, 1);
-        int index;
-
-        if (!dc_isar_feature(aa32_fhm, s)) {
-            return 1;
-        }
-        if (q) {
-            rm = vm20;
-            index = m * 2 + vm3;
-        } else {
-            rm = vm20 * 2 + m;
-            index = vm3;
-        }
-        is_long = true;
-        data = (index << 2) | is_s; /* is_2 == 0 */
-        fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
-        ptr_is_env = true;
-    } else {
-        return 1;
-    }
-
-    VFP_DREG_D(rd, insn);
-    if (rd & q) {
-        return 1;
-    }
-    if (q || !is_long) {
-        VFP_DREG_N(rn, insn);
-        if (rn & q & !is_long) {
-            return 1;
-        }
-        off_rn = vfp_reg_offset(1, rn);
-        off_rm = vfp_reg_offset(1, rm);
-    } else {
-        rn = VFP_SREG_N(insn);
-        off_rn = vfp_reg_offset(0, rn);
-        off_rm = vfp_reg_offset(0, rm);
-    }
-    if (s->fp_excp_el) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
-        return 0;
-    }
-    if (!s->vfp_enabled) {
-        return 1;
-    }
-
-    opr_sz = (1 + q) * 8;
-    if (fn_gvec_ptr) {
-        TCGv_ptr ptr;
-        if (ptr_is_env) {
-            ptr = cpu_env;
-        } else {
-            ptr = get_fpstatus_ptr(1);
-        }
-        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
-                           opr_sz, opr_sz, data, fn_gvec_ptr);
-        if (!ptr_is_env) {
-            tcg_temp_free_ptr(ptr);
-        }
-    } else {
-        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
-                           opr_sz, opr_sz, data, fn_gvec);
-    }
-    return 0;
-}
-
 static int disas_coproc_insn(DisasContext *s, uint32_t insn)
 {
     int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                     }
                 }
             }
-        } else if ((insn & 0x0f000a00) == 0x0e000800
-                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
-            if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
-                goto illegal_op;
-            }
-            return;
         }
         goto illegal_op;
     }
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
             }
             break;
         }
-        if ((insn & 0xff000a00) == 0xfe000800
-            && arm_dc_feature(s, ARM_FEATURE_V8)) {
-            /* The Thumb2 and ARM encodings are identical.  */
-            if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
-                goto illegal_op;
-            }
-        } else if (((insn >> 24) & 3) == 3) {
+        if (((insn >> 24) & 3) == 3) {
             /* Translate into the equivalent ARM encoding.  */
             insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
             if (disas_neon_data_insn(s, insn)) {
-- 
2.20.1

Convert the Neon "load/store multiple structures" insns to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-12-peter.maydell@linaro.org
---
 target/arm/neon-ls.decode       |   7 ++
 target/arm/translate-neon.inc.c | 124 ++++++++++++++++++++++++++++++++
 target/arm/translate.c          |  91 +----------------------
 3 files changed, 133 insertions(+), 89 deletions(-)

diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-ls.decode
+++ b/target/arm/neon-ls.decode
@@ -XXX,XX +XXX,XX @@
 #   0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
 # This file works on the A32 encoding only; calling code for T32 has to
 # transform the insn into the A32 version first.
+
+%vd_dp  22:1 12:4
+
+# Neon load/store multiple structures
+
+VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
+               vd=%vd_dp
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
                        gen_helper_gvec_fmlal_idx_a32);
     return true;
 }
+
+static struct {
+    int nregs;
+    int interleave;
+    int spacing;
+} const neon_ls_element_type[11] = {
+    {1, 4, 1},
+    {1, 4, 2},
+    {4, 1, 1},
+    {2, 2, 2},
+    {1, 3, 1},
+    {1, 3, 2},
+    {3, 1, 1},
+    {1, 1, 1},
+    {1, 2, 1},
+    {1, 2, 2},
+    {2, 1, 1}
+};
+
+static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn,
+                                      int stride)
+{
+    if (rm != 15) {
+        TCGv_i32 base;
+
+        base = load_reg(s, rn);
+        if (rm == 13) {
+            tcg_gen_addi_i32(base, base, stride);
+        } else {
+            TCGv_i32 index;
+            index = load_reg(s, rm);
+            tcg_gen_add_i32(base, base, index);
+            tcg_temp_free_i32(index);
+        }
+        store_reg(s, rn, base);
+    }
+}
+
+static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
+{
+    /* Neon load/store multiple structures */
+    int nregs, interleave, spacing, reg, n;
+    MemOp endian = s->be_data;
+    int mmu_idx = get_mem_index(s);
+    int size = a->size;
+    TCGv_i64 tmp64;
+    TCGv_i32 addr, tmp;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist */
+    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+        return false;
+    }
+    if (a->itype > 10) {
+        return false;
+    }
+    /* Catch UNDEF cases for bad values of align field */
+    switch (a->itype & 0xc) {
+    case 4:
+        if (a->align >= 2) {
+            return false;
+        }
+        break;
+    case 8:
+        if (a->align == 3) {
+            return false;
+        }
+        break;
+    default:
+        break;
+    }
+    nregs = neon_ls_element_type[a->itype].nregs;
+    interleave = neon_ls_element_type[a->itype].interleave;
+    spacing = neon_ls_element_type[a->itype].spacing;
+    if (size == 3 && (interleave | spacing) != 1) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    /* For our purposes, bytes are always little-endian.  */
+    if (size == 0) {
+        endian = MO_LE;
+    }
+    /*
+     * Consecutive little-endian elements from a single register
+     * can be promoted to a larger little-endian operation.
+     */
+    if (interleave == 1 && endian == MO_LE) {
+        size = 3;
+    }
+    tmp64 = tcg_temp_new_i64();
+    addr = tcg_temp_new_i32();
+    tmp = tcg_const_i32(1 << size);
+    load_reg_var(s, addr, a->rn);
+    for (reg = 0; reg < nregs; reg++) {
+        for (n = 0; n < 8 >> size; n++) {
+            int xs;
+            for (xs = 0; xs < interleave; xs++) {
+                int tt = a->vd + reg + spacing * xs;
+
+                if (a->l) {
+                    gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
+                    neon_store_element64(tt, n, size, tmp64);
+                } else {
+                    neon_load_element64(tmp64, tt, n, size);
+                    gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
+                }
+                tcg_gen_add_i32(addr, addr, tmp);
+            }
+        }
+    }
+    tcg_temp_free_i32(addr);
+    tcg_temp_free_i32(tmp);
+    tcg_temp_free_i64(tmp64);
+
+    gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
 }
 
 
-static struct {
-    int nregs;
-    int interleave;
-    int spacing;
-} const neon_ls_element_type[11] = {
-    {1, 4, 1},
-    {1, 4, 2},
-    {4, 1, 1},
-    {2, 2, 2},
-    {1, 3, 1},
-    {1, 3, 2},
-    {3, 1, 1},
-    {1, 1, 1},
-    {1, 2, 1},
-    {1, 2, 2},
-    {2, 1, 1}
-};
-
 /* Translate a NEON load/store element instruction.  Return nonzero if the
    instruction is invalid.  */
 static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
 {
     int rd, rn, rm;
-    int op;
     int nregs;
-    int interleave;
-    int spacing;
     int stride;
     int size;
     int reg;
     int load;
-    int n;
     int vec_size;
-    int mmu_idx;
-    MemOp endian;
     TCGv_i32 addr;
     TCGv_i32 tmp;
-    TCGv_i32 tmp2;
-    TCGv_i64 tmp64;
 
     if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
         return 1;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
     rn = (insn >> 16) & 0xf;
     rm = insn & 0xf;
     load = (insn & (1 << 21)) != 0;
-    endian = s->be_data;
-    mmu_idx = get_mem_index(s);
     if ((insn & (1 << 23)) == 0) {
-        /* Load store all elements.  */
-        op = (insn >> 8) & 0xf;
-        size = (insn >> 6) & 3;
-        if (op > 10)
-            return 1;
-        /* Catch UNDEF cases for bad values of align field */
-        switch (op & 0xc) {
-        case 4:
-            if (((insn >> 5) & 1) == 1) {
-                return 1;
-            }
-            break;
-        case 8:
-            if (((insn >> 4) & 3) == 3) {
-                return 1;
-            }
-            break;
-        default:
-            break;
-        }
-        nregs = neon_ls_element_type[op].nregs;
-        interleave = neon_ls_element_type[op].interleave;
-        spacing = neon_ls_element_type[op].spacing;
-        if (size == 3 && (interleave | spacing) != 1) {
-            return 1;
-        }
-        /* For our purposes, bytes are always little-endian.  */
-        if (size == 0) {
-            endian = MO_LE;
-        }
-        /* Consecutive little-endian elements from a single register
-         * can be promoted to a larger little-endian operation.
-         */
-        if (interleave == 1 && endian == MO_LE) {
-            size = 3;
-        }
-        tmp64 = tcg_temp_new_i64();
-        addr = tcg_temp_new_i32();
-        tmp2 = tcg_const_i32(1 << size);
-        load_reg_var(s, addr, rn);
-        for (reg = 0; reg < nregs; reg++) {
-            for (n = 0; n < 8 >> size; n++) {
-                int xs;
-                for (xs = 0; xs < interleave; xs++) {
-                    int tt = rd + reg + spacing * xs;
-
-                    if (load) {
-                        gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
-                        neon_store_element64(tt, n, size, tmp64);
-                    } else {
-                        neon_load_element64(tmp64, tt, n, size);
-                        gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
-                    }
-                    tcg_gen_add_i32(addr, addr, tmp2);
-                }
-            }
-        }
-        tcg_temp_free_i32(addr);
-        tcg_temp_free_i32(tmp2);
-        tcg_temp_free_i64(tmp64);
-        stride = nregs * interleave * 8;
+        /* Load store all elements -- handled already by decodetree */
+        return 1;
     } else {
         size = (insn >> 10) & 3;
         if (size == 3) {
-- 
2.20.1

Convert the Neon "load single structure to all lanes" insns to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-13-peter.maydell@linaro.org
---
 target/arm/neon-ls.decode       |  5 +++
 target/arm/translate-neon.inc.c | 73 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 55 +------------------------
 3 files changed, 80 insertions(+), 53 deletions(-)

Convert the Neon "load/store single structure to one lane" insns to
decodetree.

As this is the last set of insns in the neon load/store group,
we can remove the whole disas_neon_ls_insn() function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-14-peter.maydell@linaro.org
---
 target/arm/neon-ls.decode       |  11 +++
 target/arm/translate-neon.inc.c |  89 +++++++++++++++++++
 target/arm/translate.c          | 147 --------------------------------
 3 files changed, 100 insertions(+), 147 deletions(-)

diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-ls.decode
+++ b/target/arm/neon-ls.decode
@@ -XXX,XX +XXX,XX @@ VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
 
 VLD_all_lanes  1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
                vd=%vd_dp
+
+# Neon load/store single structure to one lane
+%imm1_5_p1 5:1 !function=plus1
+%imm1_6_p1 6:1 !function=plus1
+
+VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
+               vd=%vd_dp size=0 stride=1
+VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \
+               vd=%vd_dp size=1 stride=%imm1_5_p1
+VLDST_single   1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \
+               vd=%vd_dp size=2 stride=%imm1_6_p1
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@
  * It might be possible to convert it to a standalone .c file eventually.
  */
 
+static inline int plus1(DisasContext *s, int x)
+{
+    return x + 1;
+}
+
 /* Include the generated Neon decoder */
 #include "decode-neon-dp.inc.c"
 #include "decode-neon-ls.inc.c"
@@ -XXX,XX +XXX,XX @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
 
     return true;
 }
+
+static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
+{
+    /* Neon load/store single structure to one lane */
+    int reg;
+    int nregs = a->n + 1;
+    int vd = a->vd;
+    TCGv_i32 addr, tmp;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist */
+    if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+        return false;
+    }
+
+    /* Catch the UNDEF cases. This is unavoidably a bit messy. */
+    switch (nregs) {
+    case 1:
+        if (((a->align & (1 << a->size)) != 0) ||
+            (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
+            return false;
+        }
+        break;
+    case 3:
+        if ((a->align & 1) != 0) {
+            return false;
+        }
+        /* fall through */
+    case 2:
+        if (a->size == 2 && (a->align & 2) != 0) {
+            return false;
+        }
+        break;
+    case 4:
+        if ((a->size == 2) && ((a->align & 3) == 3)) {
+            return false;
+        }
+        break;
+    default:
+        abort();
+    }
+    if ((vd + a->stride * (nregs - 1)) > 31) {
+        /*
+         * Attempts to write off the end of the register file are
+         * UNPREDICTABLE; we choose to UNDEF because otherwise we would
+         * access off the end of the array that holds the register data.
+         */
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    tmp = tcg_temp_new_i32();
+    addr = tcg_temp_new_i32();
+    load_reg_var(s, addr, a->rn);
+    /*
+     * TODO: if we implemented alignment exceptions, we should check
+     * addr against the alignment encoded in a->align here.
+     */
+    for (reg = 0; reg < nregs; reg++) {
+        if (a->l) {
+            gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
+                            s->be_data | a->size);
+            neon_store_element(vd, a->reg_idx, a->size, tmp);
+        } else { /* Store */
+            neon_load_element(tmp, vd, a->reg_idx, a->size);
+            gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
+                            s->be_data | a->size);
+        }
+        vd += a->stride;
+        tcg_gen_addi_i32(addr, addr, 1 << a->size);
+    }
+    tcg_temp_free_i32(addr);
+    tcg_temp_free_i32(tmp);
+
+    gen_neon_ldst_base_update(s, a->rm, a->rn, (1 << a->size) * nregs);
+
+    return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
     tcg_temp_free_i32(rd);
 }
 
-
-/* Translate a NEON load/store element instruction.  Return nonzero if the
-   instruction is invalid.  */
-static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
-{
-    int rd, rn, rm;
-    int nregs;
-    int stride;
-    int size;
-    int reg;
-    int load;
-    TCGv_i32 addr;
-    TCGv_i32 tmp;
-
-    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
-        return 1;
-    }
-
-    /* FIXME: this access check should not take precedence over UNDEF
-     * for invalid encodings; we will generate incorrect syndrome information
-     * for attempts to execute invalid vfp/neon encodings with FP disabled.
-     */
-    if (s->fp_excp_el) {
-        gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
-                           syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
-        return 0;
-    }
-
-    if (!s->vfp_enabled)
-      return 1;
-    VFP_DREG_D(rd, insn);
-    rn = (insn >> 16) & 0xf;
-    rm = insn & 0xf;
-    load = (insn & (1 << 21)) != 0;
-    if ((insn & (1 << 23)) == 0) {
-        /* Load store all elements -- handled already by decodetree */
-        return 1;
-    } else {
-        size = (insn >> 10) & 3;
-        if (size == 3) {
-            /* Load single element to all lanes -- handled by decodetree  */
-            return 1;
-        } else {
-            /* Single element.  */
-            int idx = (insn >> 4) & 0xf;
-            int reg_idx;
-            switch (size) {
-            case 0:
-                reg_idx = (insn >> 5) & 7;
-                stride = 1;
-                break;
-            case 1:
-                reg_idx = (insn >> 6) & 3;
-                stride = (insn & (1 << 5)) ? 2 : 1;
-                break;
-            case 2:
-                reg_idx = (insn >> 7) & 1;
-                stride = (insn & (1 << 6)) ? 2 : 1;
-                break;
-            default:
-                abort();
-            }
-            nregs = ((insn >> 8) & 3) + 1;
-            /* Catch the UNDEF cases. This is unavoidably a bit messy. */
-            switch (nregs) {
-            case 1:
-                if (((idx & (1 << size)) != 0) ||
-                    (size == 2 && ((idx & 3) == 1 || (idx & 3) == 2))) {
-                    return 1;
-                }
-                break;
-            case 3:
-                if ((idx & 1) != 0) {
-                    return 1;
-                }
-                /* fall through */
-            case 2:
-                if (size == 2 && (idx & 2) != 0) {
-                    return 1;
-                }
-                break;
-            case 4:
-                if ((size == 2) && ((idx & 3) == 3)) {
-                    return 1;
-                }
-                break;
-            default:
-                abort();
-            }
-            if ((rd + stride * (nregs - 1)) > 31) {
-                /* Attempts to write off the end of the register file
-                 * are UNPREDICTABLE; we choose to UNDEF because otherwise
-                 * the neon_load_reg() would write off the end of the array.
-                 */
-                return 1;
-            }
-            tmp = tcg_temp_new_i32();
-            addr = tcg_temp_new_i32();
-            load_reg_var(s, addr, rn);
-            for (reg = 0; reg < nregs; reg++) {
-                if (load) {
-                    gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
-                                    s->be_data | size);
-                    neon_store_element(rd, reg_idx, size, tmp);
-                } else { /* Store */
-                    neon_load_element(tmp, rd, reg_idx, size);
-                    gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
-                                    s->be_data | size);
-                }
-                rd += stride;
-                tcg_gen_addi_i32(addr, addr, 1 << size);
-            }
-            tcg_temp_free_i32(addr);
-            tcg_temp_free_i32(tmp);
-            stride = nregs * (1 << size);
-        }
-    }
-    if (rm != 15) {
-        TCGv_i32 base;
-
-        base = load_reg(s, rn);
-        if (rm == 13) {
-            tcg_gen_addi_i32(base, base, stride);
-        } else {
-            TCGv_i32 index;
-            index = load_reg(s, rm);
-            tcg_gen_add_i32(base, base, index);
-            tcg_temp_free_i32(index);
-        }
-        store_reg(s, rn, base);
-    }
-    return 0;
-}
-
 static inline void gen_neon_narrow(int size, TCGv_i32 dest, TCGv_i64 src)
 {
     switch (size) {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
             }
             return;
         }
-        if ((insn & 0x0f100000) == 0x04000000) {
-            /* NEON load/store.  */
-            if (disas_neon_ls_insn(s, insn)) {
-                goto illegal_op;
-            }
-            return;
-        }
         if ((insn & 0x0e000f00) == 0x0c000100) {
             if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
                 /* iWMMXt register transfer.  */
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
         }
         break;
     case 12:
-        if ((insn & 0x01100000) == 0x01000000) {
-            if (disas_neon_ls_insn(s, insn)) {
-                goto illegal_op;
-            }
-            break;
-        }
         goto illegal_op;
     default:
     illegal_op:
-- 
2.20.1

Convert the Neon 3-reg-same VADD and VSUB insns to decodetree.

Note that we don't need the neon_3r_sizes[op] check here because all
size values are OK for VADD and VSUB; we'll add this when we convert
the first insn that has size restrictions.

For this we need one of the GVecGen*Fn typedefs currently in
translate-a64.h; move them all to translate.h as a block so they
are visible to the 32-bit decoder.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-15-peter.maydell@linaro.org
---
 target/arm/translate-a64.h      |  9 --------
 target/arm/translate.h          |  9 ++++++++
 target/arm/neon-dp.decode       | 17 +++++++++++++++
 target/arm/translate-neon.inc.c | 38 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 14 ++++--------
 5 files changed, 68 insertions(+), 19 deletions(-)

diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -XXX,XX +XXX,XX @@ static inline int vec_full_reg_size(DisasContext *s)
 
 bool disas_sve(DisasContext *, uint32_t);
 
-/* Note that the gvec expanders operate on offsets + sizes.  */
-typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
-typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
-                         uint32_t, uint32_t);
-typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
-                        uint32_t, uint32_t, uint32_t);
-typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
-                        uint32_t, uint32_t, uint32_t);
-
 #endif /* TARGET_ARM_TRANSLATE_A64_H */
diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 #define dc_isar_feature(name, ctx) \
     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
 
+/* Note that the gvec expanders operate on offsets + sizes.  */
+typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
+typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
+                         uint32_t, uint32_t);
+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+                        uint32_t, uint32_t, uint32_t);
+typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
+                        uint32_t, uint32_t, uint32_t);
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@
 #
 # This file is processed by scripts/decodetree.py
 #
+# VFP/Neon register fields; same as vfp.decode
+%vm_dp  5:1 0:4
+%vn_dp  7:1 16:4
+%vd_dp  22:1 12:4
 
 # Encodings for Neon data processing instructions where the T32 encoding
 # is a simple transformation of the A32 encoding.
@@ -XXX,XX +XXX,XX @@
 #   0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
 # This file works on the A32 encoding only; calling code for T32 has to
 # transform the insn into the A32 version first.
+
+######################################################################
+# 3-reg-same grouping:
+# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
+######################################################################
+
+&3same vm vn vd q size
+
+@3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
+VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
 
     return true;
 }
+
+static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
+{
+    int vec_size = a->q ? 16 : 8;
+    int rd_ofs = neon_reg_offset(a->vd, 0);
+    int rn_ofs = neon_reg_offset(a->vn, 0);
+    int rm_ofs = neon_reg_offset(a->vm, 0);
+
+    if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
+    /* UNDEF accesses to D16-D31 if they don't exist. */
+    if (!dc_isar_feature(aa32_simd_r32, s) &&
+        ((a->vd | a->vn | a->vm) & 0x10)) {
+        return false;
+    }
+
+    if ((a->vn | a->vm | a->vd) & a->q) {
+        return false;
+    }
+
+    if (!vfp_access_check(s)) {
+        return true;
+    }
+
+    fn(a->size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
+    return true;
+}
+
+#define DO_3SAME(INSN, FUNC)                                            \
+    static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a)        \
+    {                                                                   \
+        return do_3same(s, a, FUNC);                                    \
+    }
+
+DO_3SAME(VADD, tcg_gen_gvec_add)
+DO_3SAME(VSUB, tcg_gen_gvec_sub)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             }
             return 0;
 
-        case NEON_3R_VADD_VSUB:
-            if (u) {
-                tcg_gen_gvec_sub(size, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-            } else {
-                tcg_gen_gvec_add(size, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-            }
-            return 0;
-
         case NEON_3R_VQADD:
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
                            u ? &ushl_op[size] : &sshl_op[size]);
             return 0;
+
+        case NEON_3R_VADD_VSUB:
+            /* Already handled by decodetree */
+            return 1;
         }
 
         if (size == 3) {
-- 
2.20.1

Convert the Neon logic ops in the 3-reg-same grouping to decodetree.
Note that for the logic ops the 'size' field forms part of their
decode and the actual operations are always bitwise.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-16-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       | 12 +++++++++++
 target/arm/translate-neon.inc.c | 19 +++++++++++++++++
 target/arm/translate.c          | 38 +--------------------------------
 3 files changed, 32 insertions(+), 37 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@
 @3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
 
+@3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
+                 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
+
+VAND_3s          1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
+VBIC_3s          1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
+VORR_3s          1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
+VORN_3s          1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
+VEOR_3s          1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
+VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
+VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
+VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
+
 VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
 VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn)
 
 DO_3SAME(VADD, tcg_gen_gvec_add)
 DO_3SAME(VSUB, tcg_gen_gvec_sub)
+DO_3SAME(VAND, tcg_gen_gvec_and)
+DO_3SAME(VBIC, tcg_gen_gvec_andc)
+DO_3SAME(VORR, tcg_gen_gvec_or)
+DO_3SAME(VORN, tcg_gen_gvec_orc)
+DO_3SAME(VEOR, tcg_gen_gvec_xor)
+
+/* These insns are all gvec_bitsel but with the inputs in various orders. */
+#define DO_3SAME_BITSEL(INSN, O1, O2, O3)                               \
+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+                                uint32_t oprsz, uint32_t maxsz)         \
+    {                                                                   \
+        tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz);    \
+    }                                                                   \
+    DO_3SAME(INSN, gen_##INSN##_3s)
+
+DO_3SAME_BITSEL(VBSL, rd_ofs, rn_ofs, rm_ofs)
+DO_3SAME_BITSEL(VBIT, rm_ofs, rn_ofs, rd_ofs)
+DO_3SAME_BITSEL(VBIF, rm_ofs, rd_ofs, rn_ofs)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             }
             return 1;
 
-        case NEON_3R_LOGIC: /* Logic ops.  */
-            switch ((u << 2) | size) {
-            case 0: /* VAND */
-                tcg_gen_gvec_and(0, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-                break;
-            case 1: /* VBIC */
-                tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
-                                  vec_size, vec_size);
-                break;
-            case 2: /* VORR */
-                tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
-                                vec_size, vec_size);
-                break;
-            case 3: /* VORN */
-                tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-                break;
-            case 4: /* VEOR */
-                tcg_gen_gvec_xor(0, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-                break;
-            case 5: /* VBSL */
-                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rd_ofs, rn_ofs, rm_ofs,
-                                    vec_size, vec_size);
-                break;
-            case 6: /* VBIT */
-                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rn_ofs, rd_ofs,
-                                    vec_size, vec_size);
-                break;
-            case 7: /* VBIF */
-                tcg_gen_gvec_bitsel(MO_8, rd_ofs, rm_ofs, rd_ofs, rn_ofs,
-                                    vec_size, vec_size);
-                break;
-            }
-            return 0;
-
         case NEON_3R_VQADD:
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             return 0;
 
         case NEON_3R_VADD_VSUB:
+        case NEON_3R_LOGIC:
             /* Already handled by decodetree */
             return 1;
         }
-- 
2.20.1

Convert the Neon 3-reg-same VMAX and VMIN insns to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-17-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  5 +++++
 target/arm/translate-neon.inc.c | 14 ++++++++++++++
 target/arm/translate.c          | 21 ++-------------------
 3 files changed, 21 insertions(+), 19 deletions(-)

Convert the Neon comparison ops in the 3-reg-same grouping
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-18-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  8 ++++++++
 target/arm/translate-neon.inc.c | 22 ++++++++++++++++++++++
 target/arm/translate.c          | 23 +++--------------------
 3 files changed, 33 insertions(+), 20 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
 VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
 VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
 
+VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
+VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
+VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
+VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
+
 VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
 VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
 VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
@@ -XXX,XX +XXX,XX @@ VMIN_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 1 .... @3same
 
 VADD_3s          1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
 VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
+
+VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
+VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
 DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
 DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
 DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
+
+#define DO_3SAME_CMP(INSN, COND)                                        \
+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+                                uint32_t oprsz, uint32_t maxsz)         \
+    {                                                                   \
+        tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \
+    }                                                                   \
+    DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
+
+DO_3SAME_CMP(VCGT_S, TCG_COND_GT)
+DO_3SAME_CMP(VCGT_U, TCG_COND_GTU)
+DO_3SAME_CMP(VCGE_S, TCG_COND_GE)
+DO_3SAME_CMP(VCGE_U, TCG_COND_GEU)
+DO_3SAME_CMP(VCEQ, TCG_COND_EQ)
+
+static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+                         uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+    tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);
+}
+DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                            u ? &mls_op[size] : &mla_op[size]);
             return 0;
 
-        case NEON_3R_VTST_VCEQ:
-            if (u) { /* VCEQ */
-                tcg_gen_gvec_cmp(TCG_COND_EQ, size, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-            } else { /* VTST */
-                tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,
-                               vec_size, vec_size, &cmtst_op[size]);
-            }
-            return 0;
-
-        case NEON_3R_VCGT:
-            tcg_gen_gvec_cmp(u ? TCG_COND_GTU : TCG_COND_GT, size,
-                             rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
-            return 0;
-
-        case NEON_3R_VCGE:
-            tcg_gen_gvec_cmp(u ? TCG_COND_GEU : TCG_COND_GE, size,
-                             rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size);
-            return 0;
-
         case NEON_3R_VSHL:
             /* Note the operation is vshl vd,vm,vn */
             tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         case NEON_3R_LOGIC:
         case NEON_3R_VMAX:
         case NEON_3R_VMIN:
+        case NEON_3R_VTST_VCEQ:
+        case NEON_3R_VCGT:
+        case NEON_3R_VCGE:
             /* Already handled by decodetree */
             return 1;
         }
-- 
2.20.1

Convert the Neon VQADD/VQSUB insns in the 3-reg-same grouping
to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-19-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  6 ++++++
 target/arm/translate-neon.inc.c | 15 +++++++++++++++
 target/arm/translate.c          | 14 ++------------
 3 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@
 @3same           .... ... . . . size:2 .... .... .... . q:1 . . .... \
                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
 
+VQADD_S_3s       1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
+VQADD_U_3s       1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
+
 @3same_logic     .... ... . . . .. .... .... .... . q:1 .. .... \
                  &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
 
@@ -XXX,XX +XXX,XX @@ VBSL_3s          1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
 VBIT_3s          1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
 VBIF_3s          1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
 
+VQSUB_S_3s       1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
+VQSUB_U_3s       1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
+
 VCGT_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 0 .... @3same
 VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
 VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ static void gen_VTST_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
     tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &cmtst_op[vece]);
 }
 DO_3SAME_NO_SZ_3(VTST, gen_VTST_3s)
+
+#define DO_3SAME_GVEC4(INSN, OPARRAY)                                   \
+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+                                uint32_t oprsz, uint32_t maxsz)         \
+    {                                                                   \
+        tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),           \
+                       rn_ofs, rm_ofs, oprsz, maxsz, &OPARRAY[vece]);   \
+    }                                                                   \
+    DO_3SAME(INSN, gen_##INSN##_3s)
+
+DO_3SAME_GVEC4(VQADD_S, sqadd_op)
+DO_3SAME_GVEC4(VQADD_U, uqadd_op)
+DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
+DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             }
             return 1;
 
-        case NEON_3R_VQADD:
-            tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-                           rn_ofs, rm_ofs, vec_size, vec_size,
-                           (u ? uqadd_op : sqadd_op) + size);
-            return 0;
-
-        case NEON_3R_VQSUB:
-            tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-                           rn_ofs, rm_ofs, vec_size, vec_size,
-                           (u ? uqsub_op : sqsub_op) + size);
-            return 0;
-
         case NEON_3R_VMUL: /* VMUL */
             if (u) {
                 /* Polynomial case allows only P8.  */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         case NEON_3R_VTST_VCEQ:
         case NEON_3R_VCGT:
         case NEON_3R_VCGE:
+        case NEON_3R_VQADD:
+        case NEON_3R_VQSUB:
             /* Already handled by decodetree */
             return 1;
         }
-- 
2.20.1

Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
3-reg-same grouping to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-20-peter.maydell@linaro.org
---
 target/arm/neon-dp.decode       |  9 +++++++
 target/arm/translate-neon.inc.c | 44 +++++++++++++++++++++++++++++++++
 target/arm/translate.c          | 28 +++------------------
 3 files changed, 56 insertions(+), 25 deletions(-)

diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -XXX,XX +XXX,XX @@ VCGT_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
 VCGE_S_3s        1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
 VCGE_U_3s        1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
 
+VSHL_S_3s        1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same
+VSHL_U_3s        1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same
+
 VMAX_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
 VMAX_U_3s        1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
 VMIN_S_3s        1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
@@ -XXX,XX +XXX,XX @@ VSUB_3s          1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
 
 VTST_3s          1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
 VCEQ_3s          1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
+
+VMLA_3s          1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
+VMLS_3s          1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
+
+VMUL_3s          1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
+VMUL_p_3s        1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -XXX,XX +XXX,XX @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
 DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
 DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
 DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
+DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul)
 
 #define DO_3SAME_CMP(INSN, COND)                                        \
     static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
@@ -XXX,XX +XXX,XX @@ DO_3SAME_GVEC4(VQADD_S, sqadd_op)
 DO_3SAME_GVEC4(VQADD_U, uqadd_op)
 DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
 DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
+
+static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+                           uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+    tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
+                       0, gen_helper_gvec_pmul_b);
+}
+
+static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
+{
+    if (a->size != 0) {
+        return false;
+    }
+    return do_3same(s, a, gen_VMUL_p_3s);
+}
+
+#define DO_3SAME_GVEC3_NO_SZ_3(INSN, OPARRAY)                           \
+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+                                uint32_t oprsz, uint32_t maxsz)         \
+    {                                                                   \
+        tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs,                          \
+                       oprsz, maxsz, &OPARRAY[vece]);                   \
+    }                                                                   \
+    DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
+
+
+DO_3SAME_GVEC3_NO_SZ_3(VMLA, mla_op)
+DO_3SAME_GVEC3_NO_SZ_3(VMLS, mls_op)
+
+#define DO_3SAME_GVEC3_SHIFT(INSN, OPARRAY)                             \
+    static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs,         \
+                                uint32_t rn_ofs, uint32_t rm_ofs,       \
+                                uint32_t oprsz, uint32_t maxsz)         \
+    {                                                                   \
+        /* Note the operation is vshl vd,vm,vn */                       \
+        tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs,                          \
+                       oprsz, maxsz, &OPARRAY[vece]);                   \
+    }                                                                   \
+    DO_3SAME(INSN, gen_##INSN##_3s)
+
+DO_3SAME_GVEC3_SHIFT(VSHL_S, sshl_op)
+DO_3SAME_GVEC3_SHIFT(VSHL_U, ushl_op)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             }
             return 1;
 
-        case NEON_3R_VMUL: /* VMUL */
-            if (u) {
-                /* Polynomial case allows only P8.  */
-                if (size != 0) {
-                    return 1;
-                }
-                tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
-                                   0, gen_helper_gvec_pmul_b);
-            } else {
-                tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs,
-                                 vec_size, vec_size);
-            }
-            return 0;
-
-        case NEON_3R_VML: /* VMLA, VMLS */
-            tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
-                           u ? &mls_op[size] : &mla_op[size]);
-            return 0;
-
-        case NEON_3R_VSHL:
-            /* Note the operation is vshl vd,vm,vn */
-            tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
-                           u ? &ushl_op[size] : &sshl_op[size]);
-            return 0;
-
         case NEON_3R_VADD_VSUB:
         case NEON_3R_LOGIC:
         case NEON_3R_VMAX:
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
         case NEON_3R_VCGE:
         case NEON_3R_VQADD:
         case NEON_3R_VQSUB:
+        case NEON_3R_VMUL:
+        case NEON_3R_VML:
+        case NEON_3R_VSHL:
             /* Already handled by decodetree */
             return 1;
         }
-- 
2.20.1

We're going to want at least some of the NeonGen* typedefs
for the refactored 32-bit Neon decoder, so move them all
to translate.h since it makes more sense to keep them in
one group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-23-peter.maydell@linaro.org
---
 target/arm/translate.h     | 17 +++++++++++++++++
 target/arm/translate-a64.c | 17 -----------------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
                         uint32_t, uint32_t, uint32_t);
 
+/* Function prototype for gen_ functions for calling Neon helpers */
+typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
+typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
+typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
+typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
+typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
+typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
+typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
+typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
+typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
+typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
+typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
+typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
+typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
+typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
+
 #endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ typedef struct AArch64DecodeTable {
     AArch64DecodeFn *disas_fn;
 } AArch64DecodeTable;
 
-/* Function prototype for gen_ functions for calling Neon helpers */
-typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
-typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
-typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
-typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
-typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
-typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
-typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
-typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
-typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
-typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
-typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
-typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
-typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
-typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
-typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
-
 /* initialize TCG globals.  */
 void a64_translate_init(void)
 {
-- 
2.20.1

Nothing very exciting this time around...

-- PMM

The following changes since commit 37a712a0f969ca2df7f01182409a6c4825cebfb5:

Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-10-01 12:23:19 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201001

for you to fetch changes up to cdfaa57dcb53ba012439765a1462247dfda8595d:

hw/arm/raspi: Remove use of the 'version' value in the board code (2020-10-01 15:31:01 +0100)

----------------------------------------------------------------
target-arm queue:
 * Make isar_feature_aa32_fp16_arith() handle M-profile
 * Fix SVE splice
 * Fix SVE LDR/STR
 * Remove ignore_memory_transaction_failures on the raspi2
 * raspi: Various cleanup/refactoring

----------------------------------------------------------------
Peter Maydell (5):
      target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
      target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
      hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
      target/arm: Add ID register values for Cortex-M0
      target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile

Philippe Mathieu-Daudé (11):
      hw/arm/raspi: Define various blocks base addresses
      hw/arm/bcm2835: Add more unimplemented peripherals
      hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
      hw/arm/raspi: Display the board revision in the machine description
      hw/arm/raspi: Load the firmware on the first core
      hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
      hw/arm/raspi: Avoid using TypeInfo::class_data pointer
      hw/arm/raspi: Use more specific machine names
      hw/arm/raspi: Introduce RaspiProcessorId enum
      hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
      hw/arm/raspi: Remove use of the 'version' value in the board code

Richard Henderson (2):
      target/arm: Fix sve ldr/str
      target/arm: Fix SVE splice

The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN
bit in short-descriptor translation table format descriptors.  This
is indicated by ID_MMFR0.VMSA being at least 0b0100.  Replace the
feature bit with an ID register check, in line with our preference
for ID register checks over feature bits.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-2-peter.maydell@linaro.org
---
 target/arm/cpu.h    | 15 ++++++++++++++-
 target/arm/cpu.c    |  1 -
 target/arm/helper.c |  5 +++--
 3 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, FHM, 8, 4)
 FIELD(ID_ISAR6, SB, 12, 4)
 FIELD(ID_ISAR6, SPECRES, 16, 4)
 
+FIELD(ID_MMFR0, VMSA, 0, 4)
+FIELD(ID_MMFR0, PMSA, 4, 4)
+FIELD(ID_MMFR0, OUTERSHR, 8, 4)
+FIELD(ID_MMFR0, SHARELVL, 12, 4)
+FIELD(ID_MMFR0, TCM, 16, 4)
+FIELD(ID_MMFR0, AUXREG, 20, 4)
+FIELD(ID_MMFR0, FCSE, 24, 4)
+FIELD(ID_MMFR0, INNERSHR, 28, 4)
+
 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
 FIELD(ID_MMFR3, BPMAINT, 8, 4)
@@ -XXX,XX +XXX,XX @@ enum arm_features {
     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
-    ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
     ARM_FEATURE_V8,
     ARM_FEATURE_AARCH64, /* supports 64 bit mode */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
 }
 
+static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
+}
+
 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
 {
     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
     if (arm_feature(env, ARM_FEATURE_LPAE)) {
         set_feature(env, ARM_FEATURE_V7MP);
-        set_feature(env, ARM_FEATURE_PXN);
     }
     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
         set_feature(env, ARM_FEATURE_CBAR);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
                              target_ulong *page_size, ARMMMUFaultInfo *fi)
 {
     CPUState *cs = env_cpu(env);
+    ARMCPU *cpu = env_archcpu(env);
     int level = 1;
     uint32_t table;
     uint32_t desc;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
         goto do_fault;
     }
     type = (desc & 3);
-    if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
+    if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
         /* Section translation fault, or attempt to use the encoding
          * which is Reserved on implementations without PXN.
          */
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
         pxn = desc & 1;
         ns = extract32(desc, 19, 1);
     } else {
-        if (arm_feature(env, ARM_FEATURE_PXN)) {
+        if (cpu_isar_feature(aa32_pxn, cpu)) {
             pxn = (desc >> 2) & 1;
         }
         ns = extract32(desc, 3, 1);
-- 
2.20.1

Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters
sub-struct. We're going to want id_pfr1 for an isar_features
check, and moving both at the same time avoids an odd
inconsistency.

Changes other than the ones to cpu.h and kvm64.c made
automatically with:
  perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
---
 target/arm/cpu.h      |  4 ++--
 hw/intc/armv7m_nvic.c |  4 ++--
 target/arm/cpu.c      | 20 ++++++++++----------
 target/arm/cpu64.c    | 12 ++++++------
 target/arm/cpu_tcg.c  | 36 ++++++++++++++++++------------------
 target/arm/helper.c   |  4 ++--
 target/arm/kvm64.c    |  4 ++++
 7 files changed, 44 insertions(+), 40 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
         uint32_t id_mmfr2;
         uint32_t id_mmfr3;
         uint32_t id_mmfr4;
+        uint32_t id_pfr0;
+        uint32_t id_pfr1;
         uint32_t mvfr0;
         uint32_t mvfr1;
         uint32_t mvfr2;
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
     uint32_t reset_fpsid;
     uint32_t ctr;
     uint32_t reset_sctlr;
-    uint32_t id_pfr0;
-    uint32_t id_pfr1;
     uint64_t pmceid0;
     uint64_t pmceid1;
     uint32_t id_afr0;
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
                       "Aux Fault status registers unimplemented\n");
         return 0;
     case 0xd40: /* PFR0.  */
-        return cpu->id_pfr0;
+        return cpu->isar.id_pfr0;
     case 0xd44: /* PFR1.  */
-        return cpu->id_pfr1;
+        return cpu->isar.id_pfr1;
     case 0xd48: /* DFR0.  */
         return cpu->isar.id_dfr0;
     case 0xd4c: /* AFR0.  */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         /* Disable the security extension feature bits in the processor feature
          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
          */
-        cpu->id_pfr1 &= ~0xf0;
+        cpu->isar.id_pfr1 &= ~0xf0;
         cpu->isar.id_aa64pfr0 &= ~0xf000;
     }
 
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          * id_aa64pfr0_el1[11:8].
          */
         cpu->isar.id_aa64pfr0 &= ~0xf00;
-        cpu->id_pfr1 &= ~0xf000;
+        cpu->isar.id_pfr1 &= ~0xf000;
     }
 
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
     cpu->isar.mvfr1 = 0x00011111;
     cpu->ctr = 0x82048004;
     cpu->reset_sctlr = 0x00c50078;
-    cpu->id_pfr0 = 0x1031;
-    cpu->id_pfr1 = 0x11;
+    cpu->isar.id_pfr0 = 0x1031;
+    cpu->isar.id_pfr1 = 0x11;
     cpu->isar.id_dfr0 = 0x400;
     cpu->id_afr0 = 0;
     cpu->isar.id_mmfr0 = 0x31100003;
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
     cpu->isar.mvfr1 = 0x01111111;
     cpu->ctr = 0x80038003;
     cpu->reset_sctlr = 0x00c50078;
-    cpu->id_pfr0 = 0x1031;
-    cpu->id_pfr1 = 0x11;
+    cpu->isar.id_pfr0 = 0x1031;
+    cpu->isar.id_pfr1 = 0x11;
     cpu->isar.id_dfr0 = 0x000;
     cpu->id_afr0 = 0;
     cpu->isar.id_mmfr0 = 0x00100103;
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
     cpu->isar.mvfr1 = 0x11111111;
     cpu->ctr = 0x84448003;
     cpu->reset_sctlr = 0x00c50078;
-    cpu->id_pfr0 = 0x00001131;
-    cpu->id_pfr1 = 0x00011011;
+    cpu->isar.id_pfr0 = 0x00001131;
+    cpu->isar.id_pfr1 = 0x00011011;
     cpu->isar.id_dfr0 = 0x02010555;
     cpu->id_afr0 = 0x00000000;
     cpu->isar.id_mmfr0 = 0x10101105;
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
     cpu->isar.mvfr1 = 0x11111111;
     cpu->ctr = 0x8444c004;
     cpu->reset_sctlr = 0x00c50078;
-    cpu->id_pfr0 = 0x00001131;
-    cpu->id_pfr1 = 0x00011011;
+    cpu->isar.id_pfr0 = 0x00001131;
+    cpu->isar.id_pfr1 = 0x00011011;
     cpu->isar.id_dfr0 = 0x02010555;
     cpu->id_afr0 = 0x00000000;
     cpu->isar.id_mmfr0 = 0x10201105;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
     cpu->isar.mvfr2 = 0x00000043;
     cpu->ctr = 0x8444c004;
     cpu->reset_sctlr = 0x00c50838;
-    cpu->id_pfr0 = 0x00000131;
-    cpu->id_pfr1 = 0x00011011;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
     cpu->isar.id_dfr0 = 0x03010066;
     cpu->id_afr0 = 0x00000000;
     cpu->isar.id_mmfr0 = 0x10101105;
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
     cpu->isar.mvfr2 = 0x00000043;
     cpu->ctr = 0x84448004; /* L1Ip = VIPT */
     cpu->reset_sctlr = 0x00c50838;
-    cpu->id_pfr0 = 0x00000131;
-    cpu->id_pfr1 = 0x00011011;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
     cpu->isar.id_dfr0 = 0x03010066;
     cpu->id_afr0 = 0x00000000;
     cpu->isar.id_mmfr0 = 0x10101105;
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
     cpu->isar.mvfr2 = 0x00000043;
     cpu->ctr = 0x8444c004;
     cpu->reset_sctlr = 0x00c50838;
-    cpu->id_pfr0 = 0x00000131;
-    cpu->id_pfr1 = 0x00011011;
+    cpu->isar.id_pfr0 = 0x00000131;
+    cpu->isar.id_pfr1 = 0x00011011;
     cpu->isar.id_dfr0 = 0x03010066;
     cpu->id_afr0 = 0x00000000;
     cpu->isar.id_mmfr0 = 0x10201105;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
     cpu->isar.mvfr1 = 0x00000000;
     cpu->ctr = 0x1dd20d2;
     cpu->reset_sctlr = 0x00050078;
-    cpu->id_pfr0 = 0x111;
-    cpu->id_pfr1 = 0x1;
+    cpu->isar.id_pfr0 = 0x111;
+    cpu->isar.id_pfr1 = 0x1;
     cpu->isar.id_dfr0 = 0x2;
     cpu->id_afr0 = 0x3;
     cpu->isar.id_mmfr0 = 0x01130003;
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
     cpu->isar.mvfr1 = 0x00000000;
     cpu->ctr = 0x1dd20d2;
     cpu->reset_sctlr = 0x00050078;
-    cpu->id_pfr0 = 0x111;
-    cpu->id_pfr1 = 0x1;
+    cpu->isar.id_pfr0 = 0x111;
+    cpu->isar.id_pfr1 = 0x1;
     cpu->isar.id_dfr0 = 0x2;
     cpu->id_afr0 = 0x3;
     cpu->isar.id_mmfr0 = 0x01130003;
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
     cpu->isar.mvfr1 = 0x00000000;
     cpu->ctr = 0x1dd20d2;
     cpu->reset_sctlr = 0x00050078;
-    cpu->id_pfr0 = 0x111;
-    cpu->id_pfr1 = 0x11;
+    cpu->isar.id_pfr0 = 0x111;
+    cpu->isar.id_pfr1 = 0x11;
     cpu->isar.id_dfr0 = 0x33;
     cpu->id_afr0 = 0;
     cpu->isar.id_mmfr0 = 0x01130003;
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
     cpu->isar.mvfr0 = 0x11111111;
     cpu->isar.mvfr1 = 0x00000000;
     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
-    cpu->id_pfr0 = 0x111;
-    cpu->id_pfr1 = 0x1;
+    cpu->isar.id_pfr0 = 0x111;
+    cpu->isar.id_pfr1 = 0x1;
     cpu->isar.id_dfr0 = 0;
     cpu->id_afr0 = 0x2;
     cpu->isar.id_mmfr0 = 0x01100103;
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
     cpu->midr = 0x410fc231;
     cpu->pmsav7_dregion = 8;
-    cpu->id_pfr0 = 0x00000030;
-    cpu->id_pfr1 = 0x00000200;
+    cpu->isar.id_pfr0 = 0x00000030;
+    cpu->isar.id_pfr1 = 0x00000200;
     cpu->isar.id_dfr0 = 0x00100000;
     cpu->id_afr0 = 0x00000000;
     cpu->isar.id_mmfr0 = 0x00000030;
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
     cpu->isar.mvfr0 = 0x10110021;
     cpu->isar.mvfr1 = 0x11000011;
     cpu->isar.mvfr2 = 0x00000000;
-    cpu->id_pfr0 = 0x00000030;
-    cpu->id_pfr1 = 0x00000200;
+    cpu->isar.id_pfr0 = 0x00000030;
+    cpu->isar.id_pfr1 = 0x00000200;
     cpu->isar.id_dfr0 = 0x00100000;
     cpu->id_afr0 = 0x00000000;
     cpu->isar.id_mmfr0 = 0x00000030;
@@ -XXX,XX +XXX,XX @@ static void cortex_m7_initfn(Object *obj)
     cpu->isar.mvfr0 = 0x10110221;
     cpu->isar.mvfr1 = 0x12000011;
     cpu->isar.mvfr2 = 0x00000040;
-    cpu->id_pfr0 = 0x00000030;
-    cpu->id_pfr1 = 0x00000200;
+    cpu->isar.id_pfr0 = 0x00000030;
+    cpu->isar.id_pfr1 = 0x00000200;
     cpu->isar.id_dfr0 = 0x00100000;
     cpu->id_afr0 = 0x00000000;
     cpu->isar.id_mmfr0 = 0x00100030;
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
     cpu->isar.mvfr0 = 0x10110021;
     cpu->isar.mvfr1 = 0x11000011;
     cpu->isar.mvfr2 = 0x00000040;
-    cpu->id_pfr0 = 0x00000030;
-    cpu->id_pfr1 = 0x00000210;
+    cpu->isar.id_pfr0 = 0x00000030;
+    cpu->isar.id_pfr1 = 0x00000210;
     cpu->isar.id_dfr0 = 0x00200000;
     cpu->id_afr0 = 0x00000000;
     cpu->isar.id_mmfr0 = 0x00101F40;
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_PMSA);
     set_feature(&cpu->env, ARM_FEATURE_PMU);
     cpu->midr = 0x411fc153; /* r1p3 */
-    cpu->id_pfr0 = 0x0131;
-    cpu->id_pfr1 = 0x001;
+    cpu->isar.id_pfr0 = 0x0131;
+    cpu->isar.id_pfr1 = 0x001;
     cpu->isar.id_dfr0 = 0x010400;
     cpu->id_afr0 = 0x0;
     cpu->isar.id_mmfr0 = 0x0210030;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
 static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     ARMCPU *cpu = env_archcpu(env);
-    uint64_t pfr1 = cpu->id_pfr1;
+    uint64_t pfr1 = cpu->isar.id_pfr1;
 
     if (env->gicv3state) {
         pfr1 |= 1 << 28;
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_CONST,
               .accessfn = access_aa32_tid3,
-              .resetvalue = cpu->id_pfr0 },
+              .resetvalue = cpu->isar.id_pfr0 },
             /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
              * the value of the GIC field until after we define these regs.
              */
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
          * than skipping the reads and leaving 0, as we must avoid
          * considering the values in every case.
          */
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
+                              ARM64_SYS_REG(3, 0, 0, 1, 0));
+        err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
+                              ARM64_SYS_REG(3, 0, 0, 1, 1));
         err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
                               ARM64_SYS_REG(3, 0, 0, 1, 2));
         err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
-- 
2.20.1

M-profile CPUs only implement the ID registers as guest-visible if
the CPU implements the Main Extension (all our current CPUs except
the Cortex-M0 do).

Currently we handle this by having the Cortex-M0 leave the ID
register values in the ARMCPU struct as zero, but this conflicts with
our design decision to make QEMU behaviour be keyed off ID register
fields wherever possible.

Explicitly code the ID registers in the NVIC to return 0 if the Main
Extension is not implemented, so we can make the M0 model set the
ARMCPU struct fields to obtain the correct behaviour without those
values becoming guest-visible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-4-peter.maydell@linaro.org
---
 hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
                       "Aux Fault status registers unimplemented\n");
         return 0;
     case 0xd40: /* PFR0.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_pfr0;
     case 0xd44: /* PFR1.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_pfr1;
     case 0xd48: /* DFR0.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_dfr0;
     case 0xd4c: /* AFR0.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->id_afr0;
     case 0xd50: /* MMFR0.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_mmfr0;
     case 0xd54: /* MMFR1.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_mmfr1;
     case 0xd58: /* MMFR2.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_mmfr2;
     case 0xd5c: /* MMFR3.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_mmfr3;
     case 0xd60: /* ISAR0.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_isar0;
     case 0xd64: /* ISAR1.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_isar1;
     case 0xd68: /* ISAR2.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_isar2;
     case 0xd6c: /* ISAR3.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_isar3;
     case 0xd70: /* ISAR4.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_isar4;
     case 0xd74: /* ISAR5.  */
+        if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
+            goto bad_offset;
+        }
         return cpu->isar.id_isar5;
     case 0xd78: /* CLIDR */
         return cpu->clidr;
-- 
2.20.1

Give the Cortex-M0 ID register values corresponding to its
implemented behaviour.  These will not be guest-visible but will be
used to govern the behaviour of QEMU's emulation.  We use the same
values that the Cortex-M3 does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
---
 target/arm/cpu_tcg.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -XXX,XX +XXX,XX @@ static void cortex_m0_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_M);
 
     cpu->midr = 0x410cc200;
+
+    /*
+     * These ID register values are not guest visible, because
+     * we do not implement the Main Extension. They must be set
+     * to values corresponding to the Cortex-M0's implemented
+     * features, because QEMU generally controls its emulation
+     * by looking at ID register fields. We use the same values as
+     * for the M3.
+     */
+    cpu->isar.id_pfr0 = 0x00000030;
+    cpu->isar.id_pfr1 = 0x00000200;
+    cpu->isar.id_dfr0 = 0x00100000;
+    cpu->id_afr0 = 0x00000000;
+    cpu->isar.id_mmfr0 = 0x00000030;
+    cpu->isar.id_mmfr1 = 0x00000000;
+    cpu->isar.id_mmfr2 = 0x00000000;
+    cpu->isar.id_mmfr3 = 0x00000000;
+    cpu->isar.id_isar0 = 0x01141110;
+    cpu->isar.id_isar1 = 0x02111000;
+    cpu->isar.id_isar2 = 0x21112231;
+    cpu->isar.id_isar3 = 0x01111110;
+    cpu->isar.id_isar4 = 0x01310102;
+    cpu->isar.id_isar5 = 0x00000000;
+    cpu->isar.id_isar6 = 0x00000000;
 }
 
 static void cortex_m3_initfn(Object *obj)
-- 
2.20.1

The M-profile definition of the MVFR1 ID register differs slightly
from the A-profile one, and in particular the check for "does the CPU
support fp16 arithmetic" is not the same.

We don't currently implement any M-profile CPUs with fp16 arithmetic,
so this is not yet a visible bug, but correcting the logic now
disarms this beartrap for when we eventually do.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-6-peter.maydell@linaro.org
---
 target/arm/cpu.h | 31 ++++++++++++++++++++++++++-----
 1 file changed, 26 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
 FIELD(ID_MMFR4, CCIDX, 24, 4)
 FIELD(ID_MMFR4, EVT, 28, 4)
 
+FIELD(ID_PFR1, PROGMOD, 0, 4)
+FIELD(ID_PFR1, SECURITY, 4, 4)
+FIELD(ID_PFR1, MPROGMOD, 8, 4)
+FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
+FIELD(ID_PFR1, GENTIMER, 16, 4)
+FIELD(ID_PFR1, SEC_FRAC, 20, 4)
+FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
+FIELD(ID_PFR1, GIC, 28, 4)
+
 FIELD(ID_AA64ISAR0, AES, 4, 4)
 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
@@ -XXX,XX +XXX,XX @@ FIELD(MVFR0, FPROUND, 28, 4)
 
 FIELD(MVFR1, FPFTZ, 0, 4)
 FIELD(MVFR1, FPDNAN, 4, 4)
-FIELD(MVFR1, SIMDLS, 8, 4)
-FIELD(MVFR1, SIMDINT, 12, 4)
-FIELD(MVFR1, SIMDSP, 16, 4)
-FIELD(MVFR1, SIMDHP, 20, 4)
+FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
+FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
+FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
+FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
+FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
+FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
 FIELD(MVFR1, FPHP, 24, 4)
 FIELD(MVFR1, SIMDFMAC, 28, 4)
 
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
     return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
 }
 
+static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
+}
+
 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
 {
-    return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
+    /* Sadly this is encoded differently for A-profile and M-profile */
+    if (isar_feature_aa32_mprofile(id)) {
+        return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
+    } else {
+        return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
+    }
 }
 
 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The mte update missed a bit when producing clean addresses.

Fixes: b2aa8879b88
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200916014102.2446323-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-sve.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         for (i = 0; i < len_align; i += 8) {
             tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ);
             tcg_gen_st_i64(t0, cpu_env, vofs + i);
-            tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
+            tcg_gen_addi_i64(clean_addr, clean_addr, 8);
         }
         tcg_temp_free_i64(t0);
     } else {
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
         for (i = 0; i < len_align; i += 8) {
             tcg_gen_ld_i64(t0, cpu_env, vofs + i);
             tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ);
-            tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
+            tcg_gen_addi_i64(clean_addr, clean_addr, 8);
         }
         tcg_temp_free_i64(t0);
     } else {
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

While converting to gen_gvec_ool_zzzp, we lost passing
a->esz as the data argument to the function.

Fixes: 36cbb7a8e71
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200918000500.2690937-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-sve.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -XXX,XX +XXX,XX @@ static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
 {
     if (sve_access_check(s)) {
         gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
-                          a->rd, a->rn, a->rm, a->pg, 0);
+                          a->rd, a->rn, a->rm, a->pg, a->esz);
     }
     return true;
 }
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The Raspberry firmware is closed-source. While running it, it
accesses various I/O registers. Logging these accesses as UNIMP
(unimplemented) help to understand what the firmware is doing
(ideally we want it able to boot a Linux kernel).

Document various blocks we might use later.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200921034729.432931-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/raspi_platform.h | 51 +++++++++++++++++++++++++++------
 1 file changed, 43 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/raspi_platform.h
+++ b/include/hw/arm/raspi_platform.h
@@ -XXX,XX +XXX,XX @@
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Various undocumented addresses and names come from Herman Hermitage's VC4
+ * documentation:
+ * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map
  */
 
 #ifndef HW_ARM_RASPI_PLATFORM_H
 #define HW_ARM_RASPI_PLATFORM_H
 
 #define MSYNC_OFFSET            0x0000   /* Multicore Sync Block */
-#define IC0_OFFSET              0x2000
+#define CCPT_OFFSET             0x1000   /* Compact Camera Port 2 TX */
+#define INTE_OFFSET             0x2000   /* VC Interrupt controller */
 #define ST_OFFSET               0x3000   /* System Timer */
+#define TXP_OFFSET              0x4000   /* Transposer */
+#define JPEG_OFFSET             0x5000
 #define MPHI_OFFSET             0x6000   /* Message-based Parallel Host Intf. */
 #define DMA_OFFSET              0x7000   /* DMA controller, channels 0-14 */
-#define ARM_OFFSET              0xB000   /* BCM2708 ARM control block */
+#define ARBA_OFFSET             0x9000
+#define BRDG_OFFSET             0xa000
+#define ARM_OFFSET              0xB000   /* ARM control block */
 #define ARMCTRL_OFFSET          (ARM_OFFSET + 0x000)
 #define ARMCTRL_IC_OFFSET       (ARM_OFFSET + 0x200) /* Interrupt controller */
-#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
+#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
 #define ARMCTRL_0_SBM_OFFSET    (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
                                                       * Doorbells & Mailboxes */
 #define CPRMAN_OFFSET           0x100000 /* Power Management, Watchdog */
@@ -XXX,XX +XXX,XX @@
 #define AVS_OFFSET              0x103000 /* Audio Video Standard */
 #define RNG_OFFSET              0x104000
 #define GPIO_OFFSET             0x200000
-#define UART0_OFFSET            0x201000
-#define MMCI0_OFFSET            0x202000
-#define I2S_OFFSET              0x203000
-#define SPI0_OFFSET             0x204000
+#define UART0_OFFSET            0x201000 /* PL011 */
+#define MMCI0_OFFSET            0x202000 /* Legacy MMC */
+#define I2S_OFFSET              0x203000 /* PCM */
+#define SPI0_OFFSET             0x204000 /* SPI master */
 #define BSC0_OFFSET             0x205000 /* BSC0 I2C/TWI */
+#define PIXV0_OFFSET            0x206000
+#define PIXV1_OFFSET            0x207000
+#define DPI_OFFSET              0x208000
+#define DSI0_OFFSET             0x209000 /* Display Serial Interface */
+#define PWM_OFFSET              0x20c000
+#define PERM_OFFSET             0x20d000
+#define TEC_OFFSET              0x20e000
 #define OTP_OFFSET              0x20f000
+#define SLIM_OFFSET             0x210000 /* SLIMbus */
+#define CPG_OFFSET              0x211000
 #define THERMAL_OFFSET          0x212000
-#define BSC_SL_OFFSET           0x214000 /* SPI slave */
+#define AVSP_OFFSET             0x213000
+#define BSC_SL_OFFSET           0x214000 /* SPI slave (bootrom) */
 #define AUX_OFFSET              0x215000 /* AUX: UART1/SPI1/SPI2 */
 #define EMMC1_OFFSET            0x300000
+#define EMMC2_OFFSET            0x340000
+#define HVS_OFFSET              0x400000
 #define SMI_OFFSET              0x600000
+#define DSI1_OFFSET             0x700000
+#define UCAM_OFFSET             0x800000
+#define CMI_OFFSET              0x802000
 #define BSC1_OFFSET             0x804000 /* BSC1 I2C/TWI */
 #define BSC2_OFFSET             0x805000 /* BSC2 I2C/TWI */
+#define VECA_OFFSET             0x806000
+#define PIXV2_OFFSET            0x807000
+#define HDMI_OFFSET             0x808000
+#define HDCP_OFFSET             0x809000
+#define ARBR0_OFFSET            0x80a000
 #define DBUS_OFFSET             0x900000
 #define AVE0_OFFSET             0x910000
 #define USB_OTG_OFFSET          0x980000 /* DTC_OTG USB controller */
+#define V3D_OFFSET              0xc00000
 #define SDRAMC_OFFSET           0xe00000
+#define L2CC_OFFSET             0xe01000 /* Level 2 Cache controller */
+#define L1CC_OFFSET             0xe02000 /* Level 1 Cache controller */
+#define ARBR1_OFFSET            0xe04000
 #define DMA15_OFFSET            0xE05000 /* DMA controller, channel 15 */
+#define DCRC_OFFSET             0xe07000
+#define AXIP_OFFSET             0xe08000
 
 /* GPU interrupts */
 #define INTERRUPT_TIMER0               0
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The bcm2835-v3d is used since Linux 4.7, see commit
49ac67e0c39c ("ARM: bcm2835: Add VC4 to the device tree"),
and the bcm2835-txp since Linux 4.19, see commit
b7dd29b401f5 ("ARM: dts: bcm283x: Add Transposer block").

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20200921034729.432931-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bcm2835_peripherals.h | 2 ++
 hw/arm/bcm2835_peripherals.c         | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
 
     BCM2835SystemTimerState systmr;
     BCM2835MphiState mphi;
+    UnimplementedDeviceState txp;
     UnimplementedDeviceState armtmr;
     UnimplementedDeviceState cprman;
     UnimplementedDeviceState a2w;
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
     UnimplementedDeviceState otp;
     UnimplementedDeviceState dbus;
     UnimplementedDeviceState ave0;
+    UnimplementedDeviceState v3d;
     UnimplementedDeviceState bscsl;
     UnimplementedDeviceState smi;
     DWC2State dwc2;
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
         qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
                                INTERRUPT_USB));
 
+    create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
     create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
     create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
     create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
     create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
     create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
     create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
+    create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000);
     create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);
 }
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Commit 1c3db49d39 added the raspi3, which uses the same peripherals
than the raspi2 (but with different ARM cores). The raspi3 was
introduced without the ignore_memory_transaction_failures flag.
Almost 2 years later, the machine is usable running U-Boot and
Linux.
In commit 00cbd5bd74 we mapped a lot of unimplemented devices,
commit d442d95f added thermal block and commit 0e5bbd7406 the
system timer.
As we are happy with the raspi3, let's remove this flag on the
raspi2.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200921034729.432931-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/raspi.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
     mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
     mc->default_ram_size = board_ram_size(board_rev);
     mc->default_ram_id = "ram";
-    if (board_version(board_rev) == 2) {
-        mc->ignore_memory_transaction_failures = true;
-    }
 };
 
 static const TypeInfo raspi_machine_types[] = {
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Display the board revision in the machine description.

Before:

$ qemu-system-aarch64 -M help | fgrep raspi
  raspi2               Raspberry Pi 2B
  raspi3               Raspberry Pi 3B

After:

raspi2               Raspberry Pi 2B (revision 1.1)
  raspi3               Raspberry Pi 3B (revision 1.2)

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/raspi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
     uint32_t board_rev = (uint32_t)(uintptr_t)data;
 
     rmc->board_rev = board_rev;
-    mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev));
+    mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
+                               board_type(board_rev),
+                               FIELD_EX32(board_rev, REV_CODE, REVISION));
     mc->init = raspi_machine_init;
     mc->block_default_type = IF_SD;
     mc->no_parallel = 1;
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The 'first_cpu' is more a QEMU accelerator-related concept
than a variable the machine requires to use.
Since the machine is aware of its CPUs, directly use the
first one to load the firmware.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/raspi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
 
 static void setup_boot(MachineState *machine, int version, size_t ram_size)
 {
+    RaspiMachineState *s = RASPI_MACHINE(machine);
     static struct arm_boot_info binfo;
     int r;
 
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
         binfo.firmware_loaded = true;
     }
 
-    arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
+    arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
 }
 
 static void raspi_machine_init(MachineState *machine)
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The arm_boot_info structure belong to the machine,
move it to RaspiMachineState.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/raspi.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ struct RaspiMachineState {
     MachineState parent_obj;
     /*< public >*/
     BCM283XState soc;
+    struct arm_boot_info binfo;
 };
 typedef struct RaspiMachineState RaspiMachineState;
 
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
 static void setup_boot(MachineState *machine, int version, size_t ram_size)
 {
     RaspiMachineState *s = RASPI_MACHINE(machine);
-    static struct arm_boot_info binfo;
     int r;
 
-    binfo.board_id = MACH_TYPE_BCM2708;
-    binfo.ram_size = ram_size;
-    binfo.nb_cpus = machine->smp.cpus;
+    s->binfo.board_id = MACH_TYPE_BCM2708;
+    s->binfo.ram_size = ram_size;
+    s->binfo.nb_cpus = machine->smp.cpus;
 
     if (version <= 2) {
         /* The rpi1 and 2 require some custom setup code to run in Secure
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
          * firmware for some cache maintenance operations.
          * The rpi3 doesn't need this.
          */
-        binfo.board_setup_addr = BOARDSETUP_ADDR;
-        binfo.write_board_setup = write_board_setup;
-        binfo.secure_board_setup = true;
-        binfo.secure_boot = true;
+        s->binfo.board_setup_addr = BOARDSETUP_ADDR;
+        s->binfo.write_board_setup = write_board_setup;
+        s->binfo.secure_board_setup = true;
+        s->binfo.secure_boot = true;
     }
 
     /* Pi2 and Pi3 requires SMP setup */
     if (version >= 2) {
-        binfo.smp_loader_start = SMPBOOT_ADDR;
+        s->binfo.smp_loader_start = SMPBOOT_ADDR;
         if (version == 2) {
-            binfo.write_secondary_boot = write_smpboot;
+            s->binfo.write_secondary_boot = write_smpboot;
         } else {
-            binfo.write_secondary_boot = write_smpboot64;
+            s->binfo.write_secondary_boot = write_smpboot64;
         }
-        binfo.secondary_cpu_reset_hook = reset_secondary;
+        s->binfo.secondary_cpu_reset_hook = reset_secondary;
     }
 
     /* If the user specified a "firmware" image (e.g. UEFI), we bypass
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
             exit(1);
         }
 
-        binfo.entry = firmware_addr;
-        binfo.firmware_loaded = true;
+        s->binfo.entry = firmware_addr;
+        s->binfo.firmware_loaded = true;
     }
 
-    arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
+    arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo);
 }
 
 static void raspi_machine_init(MachineState *machine)
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Using class_data pointer to create a MachineClass is not
the recommended way anymore. The correct way is to open-code
the MachineClass::fields in the class_init() method.

We can not use TYPE_RASPI_MACHINE::class_base_init() because
it is called *before* each machine class_init(), therefore the
board_rev field is not populated. We have to manually call
raspi_machine_class_common_init() for each machine.

This partly reverts commit a03bde3674e.

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/raspi.c | 34 ++++++++++++++++++++++++----------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
     setup_boot(machine, version, machine->ram_size - vcram_size);
 }
 
-static void raspi_machine_class_init(ObjectClass *oc, void *data)
+static void raspi_machine_class_common_init(MachineClass *mc,
+                                            uint32_t board_rev)
 {
-    MachineClass *mc = MACHINE_CLASS(oc);
-    RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
-    uint32_t board_rev = (uint32_t)(uintptr_t)data;
-
-    rmc->board_rev = board_rev;
     mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
                                board_type(board_rev),
                                FIELD_EX32(board_rev, REV_CODE, REVISION));
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
     mc->default_ram_id = "ram";
 };
 
+static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
+
+    rmc->board_rev = 0xa21041;
+    raspi_machine_class_common_init(mc, rmc->board_rev);
+};
+
+#ifdef TARGET_AARCH64
+static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
+{
+    MachineClass *mc = MACHINE_CLASS(oc);
+    RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
+
+    rmc->board_rev = 0xa02082;
+    raspi_machine_class_common_init(mc, rmc->board_rev);
+};
+#endif /* TARGET_AARCH64 */
+
 static const TypeInfo raspi_machine_types[] = {
     {
         .name           = MACHINE_TYPE_NAME("raspi2"),
         .parent         = TYPE_RASPI_MACHINE,
-        .class_init     = raspi_machine_class_init,
-        .class_data     = (void *)0xa21041,
+        .class_init     = raspi2b_machine_class_init,
 #ifdef TARGET_AARCH64
     }, {
         .name           = MACHINE_TYPE_NAME("raspi3"),
         .parent         = TYPE_RASPI_MACHINE,
-        .class_init     = raspi_machine_class_init,
-        .class_data     = (void *)0xa02082,
+        .class_init     = raspi3b_machine_class_init,
 #endif
     }, {
         .name           = TYPE_RASPI_MACHINE,
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Now that we can instantiate different machines based on their
board_rev register value, we can have various raspi2 and raspi3.

In commit fc78a990ec103 we corrected the machine description.
Correct the machine names too. For backward compatibility, add
an alias to the previous generic name.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-6-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/raspi.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
     MachineClass *mc = MACHINE_CLASS(oc);
     RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
 
+    mc->alias = "raspi2";
     rmc->board_rev = 0xa21041;
     raspi_machine_class_common_init(mc, rmc->board_rev);
 };
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
     MachineClass *mc = MACHINE_CLASS(oc);
     RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
 
+    mc->alias = "raspi3";
     rmc->board_rev = 0xa02082;
     raspi_machine_class_common_init(mc, rmc->board_rev);
 };
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
 
 static const TypeInfo raspi_machine_types[] = {
     {
-        .name           = MACHINE_TYPE_NAME("raspi2"),
+        .name           = MACHINE_TYPE_NAME("raspi2b"),
         .parent         = TYPE_RASPI_MACHINE,
         .class_init     = raspi2b_machine_class_init,
 #ifdef TARGET_AARCH64
     }, {
-        .name           = MACHINE_TYPE_NAME("raspi3"),
+        .name           = MACHINE_TYPE_NAME("raspi3b"),
         .parent         = TYPE_RASPI_MACHINE,
         .class_init     = raspi3b_machine_class_init,
 #endif
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

As we only support a reduced set of the REV_CODE_PROCESSOR id
encoded in the board revision, define the PROCESSOR_ID values
as an enum. We can simplify the board_soc_type and cores_count
methods.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-7-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/raspi.c | 45 +++++++++++++++++++++------------------------
 1 file changed, 21 insertions(+), 24 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ FIELD(REV_CODE, MANUFACTURER,      16, 4);
 FIELD(REV_CODE, MEMORY_SIZE,       20, 3);
 FIELD(REV_CODE, STYLE,             23, 1);
 
+typedef enum RaspiProcessorId {
+    PROCESSOR_ID_BCM2836 = 1,
+    PROCESSOR_ID_BCM2837 = 2,
+} RaspiProcessorId;
+
+static const struct {
+    const char *type;
+    int cores_count;
+} soc_property[] = {
+    [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
+    [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
+};
+
 static uint64_t board_ram_size(uint32_t board_rev)
 {
     assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
     return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
 }
 
-static int board_processor_id(uint32_t board_rev)
+static RaspiProcessorId board_processor_id(uint32_t board_rev)
 {
+    int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
+
     assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
-    return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
+    assert(proc_id < ARRAY_SIZE(soc_property) && soc_property[proc_id].type);
+
+    return proc_id;
 }
 
 static int board_version(uint32_t board_rev)
@@ -XXX,XX +XXX,XX @@ static int board_version(uint32_t board_rev)
 
 static const char *board_soc_type(uint32_t board_rev)
 {
-    static const char *soc_types[] = {
-        NULL, TYPE_BCM2836, TYPE_BCM2837,
-    };
-    int proc_id = board_processor_id(board_rev);
-
-    if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) {
-        error_report("Unsupported processor id '%d' (board revision: 0x%x)",
-                     proc_id, board_rev);
-        exit(1);
-    }
-    return soc_types[proc_id];
+    return soc_property[board_processor_id(board_rev)].type;
 }
 
 static int cores_count(uint32_t board_rev)
 {
-    static const int soc_cores_count[] = {
-        0, BCM283X_NCPUS, BCM283X_NCPUS,
-    };
-    int proc_id = board_processor_id(board_rev);
-
-    if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) {
-        error_report("Unsupported processor id '%d' (board revision: 0x%x)",
-                     proc_id, board_rev);
-        exit(1);
-    }
-    return soc_cores_count[proc_id];
+    return soc_property[board_processor_id(board_rev)].cores_count;
 }
 
 static const char *board_type(uint32_t board_rev)
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The firmware load address depends on the SoC ("processor id") used,
not on the version of the board.

Suggested-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-8-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/raspi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
      * the normal Linux boot process
      */
     if (machine->firmware) {
-        hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
+        hwaddr firmware_addr = processor_id <= PROCESSOR_ID_BCM2836
+                             ? FIRMWARE_ADDR_2 : FIRMWARE_ADDR_3;
         /* load the firmware image (typically kernel.img) */
         r = load_image_targphys(machine->firmware, firmware_addr,
                                 ram_size - firmware_addr);
-- 
2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

We expected the 'version' ID to match the board processor ID,
but this is not always true (for example boards with revision
id 0xa02042/0xa22042 are Raspberry Pi 2 with a BCM2837 SoC).
This was not important because we were not modelling them, but
since the recent refactor now allow to model these boards, it
is safer to check the processor id directly. Remove the version
check.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200924111808.77168-9-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/raspi.c | 29 +++++++++++++----------------
 1 file changed, 13 insertions(+), 16 deletions(-)

diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@ static RaspiProcessorId board_processor_id(uint32_t board_rev)
     return proc_id;
 }
 
-static int board_version(uint32_t board_rev)
-{
-    return board_processor_id(board_rev) + 1;
-}
-
 static const char *board_soc_type(uint32_t board_rev)
 {
     return soc_property[board_processor_id(board_rev)].type;
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
     cpu_set_pc(cs, info->smp_loader_start);
 }
 
-static void setup_boot(MachineState *machine, int version, size_t ram_size)
+static void setup_boot(MachineState *machine, RaspiProcessorId processor_id,
+                       size_t ram_size)
 {
     RaspiMachineState *s = RASPI_MACHINE(machine);
     int r;
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
     s->binfo.ram_size = ram_size;
     s->binfo.nb_cpus = machine->smp.cpus;
 
-    if (version <= 2) {
-        /* The rpi1 and 2 require some custom setup code to run in Secure
-         * mode before booting a kernel (to set up the SMC vectors so
-         * that we get a no-op SMC; this is used by Linux to call the
+    if (processor_id <= PROCESSOR_ID_BCM2836) {
+        /*
+         * The BCM2835 and BCM2836 require some custom setup code to run
+         * in Secure mode before booting a kernel (to set up the SMC vectors
+         * so that we get a no-op SMC; this is used by Linux to call the
          * firmware for some cache maintenance operations.
-         * The rpi3 doesn't need this.
+         * The BCM2837 doesn't need this.
          */
         s->binfo.board_setup_addr = BOARDSETUP_ADDR;
         s->binfo.write_board_setup = write_board_setup;
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
         s->binfo.secure_boot = true;
     }
 
-    /* Pi2 and Pi3 requires SMP setup */
-    if (version >= 2) {
+    /* BCM2836 and BCM2837 requires SMP setup */
+    if (processor_id >= PROCESSOR_ID_BCM2836) {
         s->binfo.smp_loader_start = SMPBOOT_ADDR;
-        if (version == 2) {
+        if (processor_id == PROCESSOR_ID_BCM2836) {
             s->binfo.write_secondary_boot = write_smpboot;
         } else {
             s->binfo.write_secondary_boot = write_smpboot64;
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
     RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine);
     RaspiMachineState *s = RASPI_MACHINE(machine);
     uint32_t board_rev = mc->board_rev;
-    int version = board_version(board_rev);
     uint64_t ram_size = board_ram_size(board_rev);
     uint32_t vcram_size;
     DriveInfo *di;
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
 
     vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
                                           &error_abort);
-    setup_boot(machine, version, machine->ram_size - vcram_size);
+    setup_boot(machine, board_processor_id(mc->board_rev),
+               machine->ram_size - vcram_size);
 }
 
 static void raspi_machine_class_common_init(MachineClass *mc,
-- 
2.20.1