Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups.

The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835:

Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504

for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:

target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100)

* Start of conversion of Neon insns to decodetree

* versal board: support SD and RTC

* Implement ARMv8.2-TTS2UXN

* Make VQDMULL undefined when U=1

* Some minor code cleanups

Edgar E. Iglesias (11):

hw/arm: versal: Remove inclusion of arm_gicv3_common.h

hw/arm: versal: Move misplaced comment

hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal

hw/arm: versal: Embed the UARTs into the SoC type

hw/arm: versal: Embed the GEMs into the SoC type

hw/arm: versal: Embed the ADMAs into the SoC type

hw/arm: versal: Embed the APUs into the SoC type

hw/arm: versal: Add support for SD

hw/arm: versal: Add support for the RTC

hw/arm: versal-virt: Add support for SD

hw/arm: versal-virt: Add support for the RTC

Fredrik Strupe (1):

target/arm: Make VQDMULL undefined when U=1

Peter Maydell (25):

target/arm: Don't use a TLB for ARMMMUIdx_Stage2

target/arm: Use enum constant in get_phys_addr_lpae() call

target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()

target/arm: Implement ARMv8.2-TTS2UXN

target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0

target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check

target/arm: Don't allow Thumb Neon insns without FEATURE_NEON

target/arm: Add stubs for AArch32 Neon decodetree

target/arm: Convert VCMLA (vector) to decodetree

target/arm: Convert VCADD (vector) to decodetree

target/arm: Convert V[US]DOT (vector) to decodetree

target/arm: Convert VFM[AS]L (vector) to decodetree

target/arm: Convert VCMLA (scalar) to decodetree

target/arm: Convert V[US]DOT (scalar) to decodetree

target/arm: Convert VFM[AS]L (scalar) to decodetree

target/arm: Convert Neon load/store multiple structures to decodetree

target/arm: Convert Neon 'load single structure to all lanes' to decodetree

target/arm: Convert Neon 'load/store single structure' to decodetree

target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree

target/arm: Convert Neon 3-reg-same logic ops to decodetree

target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree

target/arm: Convert Neon 3-reg-same comparisons to decodetree

target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree

target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree

target/arm: Move gen_ function typedefs to translate.h

Philippe Mathieu-Daudé (2):

hw/arm/mps2-tz: Use TYPE_IOTKIT instead of hardcoded string

target/arm: Use uint64_t for midr field in CPU state struct

The ARMv8.2-TTS2UXN feature extends the XN field in stage 2

translation table descriptors from just bit [54] to bits [54:53],

allowing stage 2 to control execution permissions separately for EL0

and EL1. Implement the new semantics of the XN field and enable

the feature for our 'max' CPU.

target/arm/cpu.h | 15 +++++++++++++++

target/arm/cpu.c | 1 +

target/arm/cpu64.c | 2 ++

target/arm/helper.c | 37 +++++++++++++++++++++++++++++++------

4 files changed, 49 insertions(+), 6 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)

return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;

+static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)

+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;

/*

* 64-bit feature tests via id registers.

*/

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)

return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;

}

+static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)

+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;

/*

* Feature tests for "does this exist in either 32-bit or 64-bit?"

*/

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)

return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);

}

+static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)

+{

+ return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);

+}

/*

* Forward to the above feature tests given an ARMCPU pointer.

*/

@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)

t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */

t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */

t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */

+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */

cpu->isar.id_mmfr4 = t;

#endif

t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);

t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */

t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */

+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */

cpu->isar.id_aa64mmfr1 = t;

t = cpu->isar.id_aa64mmfr2;

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */

u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */

u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */

+ u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */

cpu->isar.id_mmfr4 = u;

u = cpu->isar.id_aa64dfr0;

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)

*

* @env: CPUARMState

* @s2ap: The 2-bit stage2 access permissions (S2AP)

- * @xn: XN (execute-never) bit

+ * @xn: XN (execute-never) bits

+ * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0

*/

-static int get_S2prot(CPUARMState *env, int s2ap, int xn)

+static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)

{

int prot = 0;

@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn)

if (s2ap & 2) {

prot |= PAGE_WRITE;

}

- if (!xn) {

- if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {

+

+ if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {

+ switch (xn) {

+ case 0:

prot |= PAGE_EXEC;

+ break;

+ case 1:

+ if (s1_is_el0) {

+ prot |= PAGE_EXEC;

+ }

+ break;

+ case 2:

+ break;

+ case 3:

+ if (!s1_is_el0) {

+ prot |= PAGE_EXEC;

+ }

+ break;

+ default:

+ g_assert_not_reached();

+ }

+ } else {

+ if (!extract32(xn, 1, 1)) {

+ if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {

+ prot |= PAGE_EXEC;

+ }

}

}

return prot;

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

}

ap = extract32(attrs, 4, 2);

- xn = extract32(attrs, 12, 1);

if (mmu_idx == ARMMMUIdx_Stage2) {

ns = true;

- *prot = get_S2prot(env, ap, xn);

+ xn = extract32(attrs, 11, 2);

+ *prot = get_S2prot(env, ap, xn, s1_is_el0);

} else {

ns = extract32(attrs, 3, 1);

+ xn = extract32(attrs, 12, 1);

pxn = extract32(attrs, 11, 1);

*prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);

}

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.

Represent it in QEMU's ARMCPU struct with a uint64_t, not a

uint32_t.

This fixes an error when compiling with -Werror=conversion

because we were manipulating the register value using a

local uint64_t variable:

target/arm/cpu64.c: In function ‘aarch64_max_initfn’:

target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]

628 | cpu->midr = t;

| ^

and future-proofs us against a possible future architecture

change using some of the top 32 bits.

Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Message-id: 20200428172634.29707-1-f4bug@amsat.org

target/arm/cpu.h | 2 +-

target/arm/cpu.c | 2 +-

2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ struct ARMCPU {

uint64_t id_aa64dfr0;

uint64_t id_aa64dfr1;

} isar;

- uint32_t midr;

+ uint64_t midr;

uint32_t revidr;

uint32_t reset_fpsid;

uint32_t ctr;

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {

static Property arm_cpu_properties[] = {

DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),

DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),

- DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),

+ DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),

DEFINE_PROP_UINT64("mp-affinity", ARMCPU,

mp_affinity, ARM64_AFFINITY_INVALID),

DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

By using the TYPE_* definitions for devices, we can:

- quickly find where devices are used with 'git-grep'

- easily rename a device (one-line change).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20200428154650.21991-1-f4bug@amsat.org

hw/arm/mps2-tz.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c

--- a/hw/arm/mps2-tz.c

+++ b/hw/arm/mps2-tz.c

@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)

exit(EXIT_FAILURE);

- sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,

+ sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,

sizeof(mms->iotkit), mmc->armsse_type);

iotkitdev = DEVICE(&mms->iotkit);

object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),

From: Fredrik Strupe <fredrik@strupe.net>

According to Arm ARM, VQDMULL is only valid when U=0, while having

U=1 is unallocated.

Signed-off-by: Fredrik Strupe <fredrik@strupe.net>

Fixes: 695272dcb976 ("target-arm: Handle UNDEF cases for Neon 3-regs-different-widths")

target/arm/translate.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)

{0, 0, 0, 0}, /* VMLSL */

{0, 0, 0, 9}, /* VQDMLSL */

{0, 0, 0, 0}, /* Integer VMULL */

- {0, 0, 0, 1}, /* VQDMULL */

+ {0, 0, 0, 9}, /* VQDMULL */

{0, 0, 0, 0xa}, /* Polynomial VMULL */

{0, 0, 0, 7}, /* Reserved: always UNDEF */

};

Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group

to decodetree. These are the last ones in the group so we can remove

all the legacy decode for the group.

Note that in disas_thumb2_insn() the parts of this encoding space

where the decodetree decoder returns false will correctly be directed

to illegal_op by the "(insn & (1 << 28))" check so they won't fall

into disas_coproc_insn() by mistake.

Message-id: 20200430181003.21682-11-peter.maydell@linaro.org

target/arm/neon-shared.decode | 7 +++

target/arm/translate-neon.inc.c | 32 ++++++++++

target/arm/translate.c | 107 +-------------------------------

3 files changed, 40 insertions(+), 106 deletions(-)

diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode

--- a/target/arm/neon-shared.decode

+++ b/target/arm/neon-shared.decode

@@ -XXX,XX +XXX,XX @@ VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \

VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \

vm=%vm_dp vn=%vn_dp vd=%vd_dp

+

+%vfml_scalar_q0_rm 0:3 5:1

+%vfml_scalar_q1_index 5:1 3:1

+VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1 index:1 ... \

+ rm=%vfml_scalar_q0_rm vn=%vn_sp vd=%vd_dp q=0

+VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \

+ index=%vfml_scalar_q1_index vn=%vn_dp vd=%vd_dp q=1

diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c

--- a/target/arm/translate-neon.inc.c

+++ b/target/arm/translate-neon.inc.c

@@ -XXX,XX +XXX,XX @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDOT_scalar *a)

tcg_temp_free_ptr(fpst);

return true;

+

+static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)

+{

+ int opr_sz;

+

+ if (!dc_isar_feature(aa32_fhm, s)) {

+ return false;

+ }

+

+ /* UNDEF accesses to D16-D31 if they don't exist. */

+ if (!dc_isar_feature(aa32_simd_r32, s) &&

+ ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) {

+ return false;

+ }

+

+ if (a->vd & a->q) {

+ return false;

+ }

+

+ if (!vfp_access_check(s)) {

+ return true;

+ }

+

+ opr_sz = (1 + a->q) * 8;

+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),

+ vfp_reg_offset(a->q, a->vn),

+ vfp_reg_offset(a->q, a->rm),

+ cpu_env, opr_sz, opr_sz,

+ (a->index << 2) | a->s, /* is_2 == 0 */

+ gen_helper_gvec_fmlal_idx_a32);

+ return true;

+}

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)

#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))

-#define VFP_SREG(insn, bigbit, smallbit) \

- ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))

#define VFP_DREG(reg, insn, bigbit, smallbit) do { \

if (dc_isar_feature(aa32_simd_r32, s)) { \

reg = (((insn) >> (bigbit)) & 0x0f) \

@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)

reg = ((insn) >> (bigbit)) & 0x0f; \

}} while (0)

-#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)

#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)

-#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)

#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)

-#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)

#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)

static void gen_neon_dup_low16(TCGv_i32 var)

@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)

return 0;

-/* Advanced SIMD two registers and a scalar extension.

- * 31 24 23 22 20 16 12 11 10 9 8 3 0

- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+

- * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | Vm |

- * +-----------------+----+---+----+----+----+---+----+---+----+---------+----+

- *

-

-static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)

-{

- gen_helper_gvec_3 *fn_gvec = NULL;

- gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;

- int rd, rn, rm, opr_sz, data;

- int off_rn, off_rm;

- bool is_long = false, q = extract32(insn, 6, 1);

- bool ptr_is_env = false;

-

- if ((insn & 0xffa00f10) == 0xfe000810) {

- /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */

- int is_s = extract32(insn, 20, 1);

- int vm20 = extract32(insn, 0, 3);

- int vm3 = extract32(insn, 3, 1);

- int m = extract32(insn, 5, 1);

- int index;

-

- if (!dc_isar_feature(aa32_fhm, s)) {

- return 1;

- }

- if (q) {

- rm = vm20;

- index = m * 2 + vm3;

- } else {

- rm = vm20 * 2 + m;

- index = vm3;

- }

- is_long = true;

- data = (index << 2) | is_s; /* is_2 == 0 */

- fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;

- ptr_is_env = true;

- } else {

- return 1;

- }

-

- VFP_DREG_D(rd, insn);

- if (rd & q) {

- return 1;

- }

- if (q || !is_long) {

- VFP_DREG_N(rn, insn);

- if (rn & q & !is_long) {

- return 1;

- }

- off_rn = vfp_reg_offset(1, rn);

- off_rm = vfp_reg_offset(1, rm);

- } else {

- rn = VFP_SREG_N(insn);

- off_rn = vfp_reg_offset(0, rn);

- off_rm = vfp_reg_offset(0, rm);

- }

- if (s->fp_excp_el) {

- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,

- syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);

- return 0;

- }

- if (!s->vfp_enabled) {

- return 1;

- }

-

- opr_sz = (1 + q) * 8;

- if (fn_gvec_ptr) {

- TCGv_ptr ptr;

- if (ptr_is_env) {

- ptr = cpu_env;

- } else {

- ptr = get_fpstatus_ptr(1);

- }

- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,

- opr_sz, opr_sz, data, fn_gvec_ptr);

- if (!ptr_is_env) {

- tcg_temp_free_ptr(ptr);

- }

- } else {

- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,

- opr_sz, opr_sz, data, fn_gvec);

- }

- return 0;

-}

-

static int disas_coproc_insn(DisasContext *s, uint32_t insn)

int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

}

}

}

- } else if ((insn & 0x0f000a00) == 0x0e000800

- && arm_dc_feature(s, ARM_FEATURE_V8)) {

- if (disas_neon_insn_2reg_scalar_ext(s, insn)) {

- goto illegal_op;

- }

- return;

}

goto illegal_op;

}

@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)

}

break;

}

- if ((insn & 0xff000a00) == 0xfe000800

- && arm_dc_feature(s, ARM_FEATURE_V8)) {

- /* The Thumb2 and ARM encodings are identical. */

- if (disas_neon_insn_2reg_scalar_ext(s, insn)) {

- goto illegal_op;

- }

- } else if (((insn >> 24) & 3) == 3) {

+ if (((insn >> 24) & 3) == 3) {

/* Translate into the equivalent ARM encoding. */

insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);

if (disas_neon_data_insn(s, insn)) {

We're going to want at least some of the NeonGen* typedefs

for the refactored 32-bit Neon decoder, so move them all

to translate.h since it makes more sense to keep them in

one group.

Message-id: 20200430181003.21682-23-peter.maydell@linaro.org

target/arm/translate.h | 17 +++++++++++++++++

target/arm/translate-a64.c | 17 -----------------

2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,

typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,

uint32_t, uint32_t, uint32_t);

+/* Function prototype for gen_ functions for calling Neon helpers */

+typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);

+typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);

+typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);

+typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);

+typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);

+typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);

+typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);

+typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);

+typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);

+typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);

+typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);

+typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);

+typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);

+typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);

+typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);

+

#endif /* TARGET_ARM_TRANSLATE_H */

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ typedef struct AArch64DecodeTable {

AArch64DecodeFn *disas_fn;

} AArch64DecodeTable;

-/* Function prototype for gen_ functions for calling Neon helpers */

-typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);

-typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);

-typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);

-typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);

-typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);

-typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);

-typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);

-typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);

-typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);

-typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);

-typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);

-typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);

-typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);

-typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);

-typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);

-

/* initialize TCG globals. */

void a64_translate_init(void)

{

For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know

whether the stage 1 access is for EL0 or not, because whether

exec permission is given can depend on whether this is an EL0

or EL1 access. Add a new argument to get_phys_addr_lpae() so

the call sites can pass this information in.

Since get_phys_addr_lpae() doesn't already have a doc comment,

add one so we have a place to put the documentation of the

semantics of the new s1_is_el0 argument.

Message-id: 20200330210400.11724-4-peter.maydell@linaro.org

target/arm/helper.c | 29 ++++++++++++++++++++++++++++-

1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@

static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

MMUAccessType access_type, ARMMMUIdx mmu_idx,

+ bool s1_is_el0,