Series comparison

-[PULL 00/11] target-arm queue
+[PULL 00/31] target-arm queue
-Last handful of arm patches before softfreeze...
+First arm pullreq for 7.1. The bulk of this is the qemu_split_irq
 removal.
-The following changes since commit a98135f727595382e200d04c2996e868b7925a01:
+I have enough stuff in my to-review queue that I expect to do another
 pullreq early next week, but 31 patches is enough to not hang on to.
-  Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request' into staging (2020-03-16 14:55:59 +0000)
+thanks
 -- PMM
 The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b:
   Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging (2022-04-20 16:43:11 -0700)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200317
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220421
-for you to fetch changes up to e88d3671e3bbd59d385838a4101ea19cdcf47309:
+for you to fetch changes up to 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6:
-  hw/arm/pxa2xx: Do not wire up OHCI for PXA255 (2020-03-17 11:36:48 +0000)
+  hw/arm: Use bit fields for NPCM7XX PWRON STRAPs (2022-04-21 11:37:05 +0100)
 ----------------------------------------------------------------
-target-arm:
+target-arm queue:
- * hw/arm/pxa2xx: Do not wire up OHCI for PXA255
+ * hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
- * aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
+ * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
- * m25p80: Improve command handling for Jedec and unsupported commands
+ * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s
- * hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
+ * xlnx-zynqmp: Connect 4 TTC timers
- * hw/arm/fsl-imx6, imx6ul: Wire up USB controllers
+ * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq
- * hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices
+ * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
  * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
  * hw/core/irq: remove unused 'qemu_irq_split' function
  * npcm7xx: use symbolic constants for PWRON STRAP bit fields
  * virt: document impact of gic-version on max CPUs
 ----------------------------------------------------------------
-Chen Qun (1):
+Edgar E. Iglesias (6):
-      hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
+      timer: cadence_ttc: Break out header file to allow embedding
       hw/arm/xlnx-zynqmp: Connect 4 TTC timers
       hw/arm: versal: Create an APU CPU Cluster
       hw/arm: versal: Add the Cortex-R5Fs
       hw/misc: Add a model of the Xilinx Versal CRL
       hw/arm: versal: Connect the CRL
-Guenter Roeck (10):
+Hao Wu (2):
-      hw/usb: Add basic i.MX USB Phy support
+      hw/misc: Add PWRON STRAP bit fields in GCR module
-      hw/arm/fsl-imx6ul: Fix USB interrupt numbers
+      hw/arm: Use bit fields for NPCM7XX PWRON STRAPs
       hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices
       hw/arm/fsl-imx6ul: Wire up USB controllers
       hw/arm/fsl-imx6: Wire up USB controllers
       m25p80: Convert to support tracing
       m25p80: Improve command handling for Jedec commands
       m25p80: Improve command handling for unsupported commands
       aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
       hw/arm/pxa2xx: Do not wire up OHCI for PXA255
- hw/usb/Makefile.objs         |   2 +
+Heinrich Schuchardt (1):
- include/hw/arm/fsl-imx6.h    |   6 ++
+      hw/arm/virt: impact of gic-version on max CPUs
  include/hw/arm/fsl-imx6ul.h  |  16 ++-
  include/hw/usb/imx-usb-phy.h |  53 ++++++++++
  hw/arm/fsl-imx6.c            |  36 +++++++
  hw/arm/fsl-imx6ul.c          |  49 ++++++++++
  hw/arm/pxa2xx.c              |   3 -
  hw/block/m25p80.c            |  58 +++++------
  hw/net/imx_fec.c             |   6 +-
  hw/ssi/aspeed_smc.c          |   2 +-
  hw/usb/imx-usb-phy.c         | 225 +++++++++++++++++++++++++++++++++++++++++++
  MAINTAINERS                  |   2 +
  hw/arm/Kconfig               |   1 +
  hw/block/trace-events        |  16 +++
  hw/usb/Kconfig               |   5 +
 files changed, 444 insertions(+), 36 deletions(-)
  create mode 100644 include/hw/usb/imx-usb-phy.h
  create mode 100644 hw/usb/imx-usb-phy.c
+Peter Maydell (19):
+      hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
+      hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device
+      hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
+      hw/arm/exynos4210: Put a9mpcore device into state struct
+      hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct
+      hw/arm/exynos4210: Coalesce board_irqs and irq_table
+      hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
+      hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
+      hw/arm/exynos4210: Put external GIC into state struct
+      hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
+      hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c
+      hw/arm/exynos4210: Delete unused macro definitions
+      hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
+      hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines
+      hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
+      hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
+      hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
+      hw/arm/exynos4210: Put combiners into state struct
+      hw/arm/exynos4210: Drop Exynos4210Irq struct
+Zongyuan Li (3):
+      hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
+      hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
+      hw/core/irq: remove unused 'qemu_irq_split' function
+ docs/system/arm/virt.rst              |   4 +-
+ include/hw/arm/exynos4210.h           |  50 ++--
+ include/hw/arm/xlnx-versal.h          |  16 ++
+ include/hw/arm/xlnx-zynqmp.h          |   4 +
+ include/hw/intc/exynos4210_combiner.h |  57 +++++
+ include/hw/intc/exynos4210_gic.h      |  43 ++++
+ include/hw/irq.h                      |   5 -
+ include/hw/misc/npcm7xx_gcr.h         |  30 +++
+ include/hw/misc/xlnx-versal-crl.h     | 235 +++++++++++++++++++
+ include/hw/timer/cadence_ttc.h        |  54 +++++
+ hw/arm/exynos4210.c                   | 430 ++++++++++++++++++++++++++++++----
+ hw/arm/npcm7xx_boards.c               |  24 +-
+ hw/arm/realview.c                     |  33 ++-
+ hw/arm/stellaris.c                    |  15 +-
+ hw/arm/virt.c                         |   7 +
+ hw/arm/xlnx-versal-virt.c             |   6 +-
+ hw/arm/xlnx-versal.c                  |  99 +++++++-
+ hw/arm/xlnx-zynqmp.c                  |  22 ++
+ hw/core/irq.c                         |  15 --
+ hw/intc/exynos4210_combiner.c         | 108 +--------
+ hw/intc/exynos4210_gic.c              | 344 +--------------------------
+ hw/misc/xlnx-versal-crl.c             | 421 +++++++++++++++++++++++++++++++++
+ hw/timer/cadence_ttc.c                |  32 +--
+ MAINTAINERS                           |   2 +-
+ hw/misc/meson.build                   |   1 +
+files changed, 1457 insertions(+), 600 deletions(-)
+ create mode 100644 include/hw/intc/exynos4210_combiner.h
+ create mode 100644 include/hw/intc/exynos4210_gic.h
+ create mode 100644 include/hw/misc/xlnx-versal-crl.h
+ create mode 100644 include/hw/timer/cadence_ttc.h
+ create mode 100644 hw/misc/xlnx-versal-crl.c

-New patch
+[PULL 01/31] hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
+It's not possible to provide the guest with the Security extensions
+(TrustZone) when using KVM or HVF, because the hardware
+virtualization extensions don't permit running EL3 guest code.
+However, we weren't checking for this combination, with the result
+that QEMU would assert if you tried it:
+$ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none
+Unexpected error in object_property_find_err() at ../../qom/object.c:1304:
+qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found
+Aborted
+Check for this combination of options and report an error, in the
+same way we already do for attempts to give a KVM or HVF guest the
+Virtualization or MTE extensions. Now we will report:
+qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404155301.566542-1-peter.maydell@linaro.org
+---
+ hw/arm/virt.c | 7 +++++++
+file changed, 7 insertions(+)
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/virt.c
++++ b/hw/arm/virt.c
+@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
+         exit(1);
+     }
++    if (vms->secure && (kvm_enabled() || hvf_enabled())) {
++        error_report("mach-virt: %s does not support providing "
++                     "Security extensions (TrustZone) to the guest CPU",
++                     kvm_enabled() ? "KVM" : "HVF");
++        exit(1);
++    }
++
+     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "Virtualization extensions to the guest CPU",
+--
+.25.1

-New patch
+[PULL 02/31] timer: cadence_ttc: Break out header file to allow embedding
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
+Break out header file to allow embedding of the the TTC.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Luc Michel <luc@lmichel.fr>
+Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++
+ hw/timer/cadence_ttc.c         | 32 ++------------------
+files changed, 56 insertions(+), 30 deletions(-)
+ create mode 100644 include/hw/timer/cadence_ttc.h
+diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/timer/cadence_ttc.h
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Xilinx Zynq cadence TTC model
++ *
++ * Copyright (c) 2011 Xilinx Inc.
++ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
++ * Copyright (c) 2012 PetaLogix Pty Ltd.
++ * Written By Haibing Ma
++ *            M. Habib
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++#ifndef HW_TIMER_CADENCE_TTC_H
++#define HW_TIMER_CADENCE_TTC_H
++
++#include "hw/sysbus.h"
++#include "qemu/timer.h"
++
++typedef struct {
++    QEMUTimer *timer;
++    int freq;
++
++    uint32_t reg_clock;
++    uint32_t reg_count;
++    uint32_t reg_value;
++    uint16_t reg_interval;
++    uint16_t reg_match[3];
++    uint32_t reg_intr;
++    uint32_t reg_intr_en;
++    uint32_t reg_event_ctrl;
++    uint32_t reg_event;
++
++    uint64_t cpu_time;
++    unsigned int cpu_time_valid;
++
++    qemu_irq irq;
++} CadenceTimerState;
++
++#define TYPE_CADENCE_TTC "cadence_ttc"
++OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
++
++struct CadenceTTCState {
++    SysBusDevice parent_obj;
++
++    MemoryRegion iomem;
++    CadenceTimerState timer[3];
++};
++
++#endif
+diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/timer/cadence_ttc.c
++++ b/hw/timer/cadence_ttc.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/timer.h"
+ #include "qom/object.h"
++#include "hw/timer/cadence_ttc.h"
++
+ #ifdef CADENCE_TTC_ERR_DEBUG
+ #define DB_PRINT(...) do { \
+     fprintf(stderr,  ": %s: ", __func__); \
+@@ -XXX,XX +XXX,XX @@
+ #define CLOCK_CTRL_PS_EN    0x00000001
+ #define CLOCK_CTRL_PS_V     0x0000001e
+-typedef struct {
+-    QEMUTimer *timer;
+-    int freq;
+-
+-    uint32_t reg_clock;
+-    uint32_t reg_count;
+-    uint32_t reg_value;
+-    uint16_t reg_interval;
+-    uint16_t reg_match[3];
+-    uint32_t reg_intr;
+-    uint32_t reg_intr_en;
+-    uint32_t reg_event_ctrl;
+-    uint32_t reg_event;
+-
+-    uint64_t cpu_time;
+-    unsigned int cpu_time_valid;
+-
+-    qemu_irq irq;
+-} CadenceTimerState;
+-
+-#define TYPE_CADENCE_TTC "cadence_ttc"
+-OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
+-
+-struct CadenceTTCState {
+-    SysBusDevice parent_obj;
+-
+-    MemoryRegion iomem;
+-    CadenceTimerState timer[3];
+-};
+-
+ static void cadence_timer_update(CadenceTimerState *s)
+ {
+     qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
+--
+.25.1

-New patch
+[PULL 03/31] hw/arm/xlnx-zynqmp: Connect 4 TTC timers
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
+Connect the 4 TTC timers on the ZynqMP.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Luc Michel <luc@lmichel.fr>
+Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/xlnx-zynqmp.h |  4 ++++
+ hw/arm/xlnx-zynqmp.c         | 22 ++++++++++++++++++++++
+files changed, 26 insertions(+)
+diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/xlnx-zynqmp.h
++++ b/include/hw/arm/xlnx-zynqmp.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/or-irq.h"
+ #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
+ #include "hw/misc/xlnx-zynqmp-crf.h"
++#include "hw/timer/cadence_ttc.h"
+ #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
+ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
+ #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
+                                   XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
++#define XLNX_ZYNQMP_NUM_TTC 4
++
+ /*
+  * Unimplemented mmio regions needed to boot some images.
+  */
+@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
+     qemu_or_irq qspi_irq_orgate;
+     XlnxZynqMPAPUCtrl apu_ctrl;
+     XlnxZynqMPCRF crf;
++    CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
+     char *boot_cpu;
+     ARMCPU *boot_cpu_ptr;
+diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/xlnx-zynqmp.c
++++ b/hw/arm/xlnx-zynqmp.c
+@@ -XXX,XX +XXX,XX @@
+ #define APU_ADDR            0xfd5c0000
+ #define APU_IRQ             153
++#define TTC0_ADDR           0xFF110000
++#define TTC0_IRQ            36
++
+ #define IPI_ADDR            0xFF300000
+ #define IPI_IRQ             64
+@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
+     sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
+ }
++static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
++{
++    SysBusDevice *sbd;
++    int i, irq;
++
++    for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
++        object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
++                                TYPE_CADENCE_TTC);
++        sbd = SYS_BUS_DEVICE(&s->ttc[i]);
++
++        sysbus_realize(sbd, &error_fatal);
++        sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
++        for (irq = 0; irq < 3; irq++) {
++            sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
++        }
++    }
++}
++
+ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
+ {
+     static const struct UnimpInfo {
+@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
+     xlnx_zynqmp_create_efuse(s, gic_spi);
+     xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
+     xlnx_zynqmp_create_crf(s, gic_spi);
++    xlnx_zynqmp_create_ttc(s, gic_spi);
+     xlnx_zynqmp_create_unimp_mmio(s);
+     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
+--
+.25.1

-New patch
+[PULL 04/31] hw/arm: versal: Create an APU CPU Cluster
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
+Create an APU CPU Cluster. This is in preparation to add the RPU.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
+Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/xlnx-versal.h | 2 ++
+ hw/arm/xlnx-versal.c         | 9 ++++++++-
+files changed, 10 insertions(+), 1 deletion(-)
+diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/xlnx-versal.h
++++ b/include/hw/arm/xlnx-versal.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "hw/arm/boot.h"
++#include "hw/cpu/cluster.h"
+ #include "hw/or-irq.h"
+ #include "hw/sd/sdhci.h"
+ #include "hw/intc/arm_gicv3.h"
+@@ -XXX,XX +XXX,XX @@ struct Versal {
+     struct {
+         struct {
+             MemoryRegion mr;
++            CPUClusterState cluster;
+             ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
+             GICv3State gic;
+         } apu;
+diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/xlnx-versal.c
++++ b/hw/arm/xlnx-versal.c
+@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
+ {
+     int i;
++    object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster,
++                            TYPE_CPU_CLUSTER);
++    qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0);
++
+     for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
+         Object *obj;
+-        object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
++        object_initialize_child(OBJECT(&s->fpd.apu.cluster),
++                                "apu-cpu[*]", &s->fpd.apu.cpu[i],
+                                 XLNX_VERSAL_ACPU_TYPE);
+         obj = OBJECT(&s->fpd.apu.cpu[i]);
+         if (i) {
+@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
+                                  &error_abort);
+         qdev_realize(DEVICE(obj), NULL, &error_fatal);
+     }
++
++    qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal);
+ }
+ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
+--
+.25.1

-New patch
+[PULL 05/31] hw/arm: versal: Add the Cortex-R5Fs
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
+Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit)
+subsystem.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
+Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/xlnx-versal.h | 10 ++++++++++
+ hw/arm/xlnx-versal-virt.c    |  6 +++---
+ hw/arm/xlnx-versal.c         | 36 ++++++++++++++++++++++++++++++++++++
+files changed, 49 insertions(+), 3 deletions(-)
+diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/xlnx-versal.h
++++ b/include/hw/arm/xlnx-versal.h
+@@ -XXX,XX +XXX,XX @@
+ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
+ #define XLNX_VERSAL_NR_ACPUS   2
++#define XLNX_VERSAL_NR_RCPUS   2
+ #define XLNX_VERSAL_NR_UARTS   2
+ #define XLNX_VERSAL_NR_GEMS    2
+ #define XLNX_VERSAL_NR_ADMAS   8
+@@ -XXX,XX +XXX,XX @@ struct Versal {
+             VersalUsb2 usb;
+         } iou;
++        /* Real-time Processing Unit.  */
++        struct {
++            MemoryRegion mr;
++            MemoryRegion mr_ps_alias;
++
++            CPUClusterState cluster;
++            ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
++        } rpu;
++
+         struct {
+             qemu_or_irq irq_orgate;
+             XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
+diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/xlnx-versal-virt.c
++++ b/hw/arm/xlnx-versal-virt.c
+@@ -XXX,XX +XXX,XX @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
+     mc->desc = "Xilinx Versal Virtual development board";
+     mc->init = versal_virt_init;
+-    mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
+-    mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
+-    mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
++    mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
++    mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
++    mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
+     mc->no_cdrom = true;
+     mc->default_ram_id = "ddr";
+ }
+diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/xlnx-versal.c
++++ b/hw/arm/xlnx-versal.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
++#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
+ #define GEM_REVISION        0x40070106
+ #define VERSAL_NUM_PMC_APB_IRQS 3
+@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
+     }
+ }
++static void versal_create_rpu_cpus(Versal *s)
++{
++    int i;
++
++    object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster,
++                            TYPE_CPU_CLUSTER);
++    qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1);
++
++    for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
++        Object *obj;
++
++        object_initialize_child(OBJECT(&s->lpd.rpu.cluster),
++                                "rpu-cpu[*]", &s->lpd.rpu.cpu[i],
++                                XLNX_VERSAL_RCPU_TYPE);
++        obj = OBJECT(&s->lpd.rpu.cpu[i]);
++        object_property_set_bool(obj, "start-powered-off", true,
++                                 &error_abort);
++
++        object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort);
++        object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu),
++                                &error_abort);
++        object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr),
++                                 &error_abort);
++        qdev_realize(DEVICE(obj), NULL, &error_fatal);
++    }
++
++    qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal);
++}
++
+ static void versal_create_uarts(Versal *s, qemu_irq *pic)
+ {
+     int i;
+@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
+     versal_create_apu_cpus(s);
+     versal_create_apu_gic(s, pic);
++    versal_create_rpu_cpus(s);
+     versal_create_uarts(s, pic);
+     versal_create_usbs(s, pic);
+     versal_create_gems(s, pic);
+@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
+     memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
+     memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
++    memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0,
++                                        &s->lpd.rpu.mr_ps_alias, 0);
+ }
+ static void versal_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void versal_init(Object *obj)
+     Versal *s = XLNX_VERSAL(obj);
+     memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
++    memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX);
+     memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
++    memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s),
++                             "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX);
+ }
+ static Property versal_properties[] = {
+--
+.25.1

-[PULL 01/11] hw/usb: Add basic i.MX USB Phy support
+[PULL 06/31] hw/misc: Add a model of the Xilinx Versal CRL
-From: Guenter Roeck <linux@roeck-us.net>
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
-Add basic USB PHY support as implemented in i.MX23, i.MX28, i.MX6,
+Add a model of the Xilinx Versal CRL.
 and i.MX7 SoCs.
-The only support really needed - at least to boot Linux - is support
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
-for soft reset, which needs to reset various registers to their initial
+Reviewed-by: Frederic Konrad <fkonrad@amd.com>
-value. Otherwise, just record register values.
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
+Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Message-id: 20200313014551.12554-2-linux@roeck-us.net
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/usb/Makefile.objs         |   2 +
+ include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++
- include/hw/usb/imx-usb-phy.h |  53 +++++++++
+ hw/misc/xlnx-versal-crl.c         | 421 ++++++++++++++++++++++++++++++
- hw/usb/imx-usb-phy.c         | 225 +++++++++++++++++++++++++++++++++++
+ hw/misc/meson.build               |   1 +
- MAINTAINERS                  |   2 +
+files changed, 657 insertions(+)
- hw/arm/Kconfig               |   1 +
+ create mode 100644 include/hw/misc/xlnx-versal-crl.h
- hw/usb/Kconfig               |   5 +
+ create mode 100644 hw/misc/xlnx-versal-crl.c
 files changed, 288 insertions(+)
  create mode 100644 include/hw/usb/imx-usb-phy.h
  create mode 100644 hw/usb/imx-usb-phy.c
-diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
+diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/usb/Makefile.objs
 +++ b/hw/usb/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XEN) += xen-usb.o
  xen-usb.o-cflags := $(LIBUSB_CFLAGS)
  xen-usb.o-libs := $(LIBUSB_LIBS)
  endif
 +
 +common-obj-$(CONFIG_IMX_USBPHY) += imx-usb-phy.o
 diff --git a/include/hw/usb/imx-usb-phy.h b/include/hw/usb/imx-usb-phy.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/include/hw/usb/imx-usb-phy.h
++++ b/include/hw/misc/xlnx-versal-crl.h
 @@ -XXX,XX +XXX,XX @@
-+#ifndef IMX_USB_PHY_H
++/*
-+#define IMX_USB_PHY_H
++ * QEMU model of the Clock-Reset-LPD (CRL).
 + *
 + * Copyright (c) 2022 Xilinx Inc.
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + *
 + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 + */
 +#ifndef HW_MISC_XLNX_VERSAL_CRL_H
 +#define HW_MISC_XLNX_VERSAL_CRL_H
 +
 +#include "hw/sysbus.h"
-+#include "qemu/bitops.h"
++#include "hw/register.h"
-+
++#include "target/arm/cpu.h"
-+enum IMXUsbPhyRegisters {
++
-+    USBPHY_PWD,
++#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl"
-+    USBPHY_PWD_SET,
++OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
-+    USBPHY_PWD_CLR,
++
-+    USBPHY_PWD_TOG,
++REG32(ERR_CTRL, 0x0)
-+    USBPHY_TX,
++    FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
-+    USBPHY_TX_SET,
++REG32(IR_STATUS, 0x4)
-+    USBPHY_TX_CLR,
++    FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
-+    USBPHY_TX_TOG,
++REG32(IR_MASK, 0x8)
-+    USBPHY_RX,
++    FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
-+    USBPHY_RX_SET,
++REG32(IR_ENABLE, 0xc)
-+    USBPHY_RX_CLR,
++    FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
-+    USBPHY_RX_TOG,
++REG32(IR_DISABLE, 0x10)
-+    USBPHY_CTRL,
++    FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
-+    USBPHY_CTRL_SET,
++REG32(WPROT, 0x1c)
-+    USBPHY_CTRL_CLR,
++    FIELD(WPROT, ACTIVE, 0, 1)
-+    USBPHY_CTRL_TOG,
++REG32(PLL_CLK_OTHER_DMN, 0x20)
-+    USBPHY_STATUS,
++    FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
-+    USBPHY_DEBUG = 0x14,
++REG32(RPLL_CTRL, 0x40)
-+    USBPHY_DEBUG_SET,
++    FIELD(RPLL_CTRL, POST_SRC, 24, 3)
-+    USBPHY_DEBUG_CLR,
++    FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
-+    USBPHY_DEBUG_TOG,
++    FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2)
-+    USBPHY_DEBUG0_STATUS,
++    FIELD(RPLL_CTRL, FBDIV, 8, 8)
-+    USBPHY_DEBUG1 = 0x1c,
++    FIELD(RPLL_CTRL, BYPASS, 3, 1)
-+    USBPHY_DEBUG1_SET,
++    FIELD(RPLL_CTRL, RESET, 0, 1)
-+    USBPHY_DEBUG1_CLR,
++REG32(RPLL_CFG, 0x44)
-+    USBPHY_DEBUG1_TOG,
++    FIELD(RPLL_CFG, LOCK_DLY, 25, 7)
-+    USBPHY_VERSION,
++    FIELD(RPLL_CFG, LOCK_CNT, 13, 10)
-+    USBPHY_MAX
++    FIELD(RPLL_CFG, LFHF, 10, 2)
 +    FIELD(RPLL_CFG, CP, 5, 4)
 +    FIELD(RPLL_CFG, RES, 0, 4)
 +REG32(RPLL_FRAC_CFG, 0x48)
 +    FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1)
 +    FIELD(RPLL_FRAC_CFG, SEED, 22, 3)
 +    FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1)
 +    FIELD(RPLL_FRAC_CFG, ORDER, 18, 1)
 +    FIELD(RPLL_FRAC_CFG, DATA, 0, 16)
 +REG32(PLL_STATUS, 0x50)
 +    FIELD(PLL_STATUS, RPLL_STABLE, 2, 1)
 +    FIELD(PLL_STATUS, RPLL_LOCK, 0, 1)
 +REG32(RPLL_TO_XPD_CTRL, 0x100)
 +    FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1)
 +    FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
 +REG32(LPD_TOP_SWITCH_CTRL, 0x104)
 +    FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
 +    FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1)
 +    FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
 +    FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
 +REG32(LPD_LSBUS_CTRL, 0x108)
 +    FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1)
 +    FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10)
 +    FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3)
 +REG32(CPU_R5_CTRL, 0x10c)
 +    FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1)
 +    FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1)
 +    FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1)
 +    FIELD(CPU_R5_CTRL, CLKACT, 25, 1)
 +    FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10)
 +    FIELD(CPU_R5_CTRL, SRCSEL, 0, 3)
 +REG32(IOU_SWITCH_CTRL, 0x114)
 +    FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1)
 +    FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10)
 +    FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3)
 +REG32(GEM0_REF_CTRL, 0x118)
 +    FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1)
 +    FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1)
 +    FIELD(GEM0_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3)
 +REG32(GEM1_REF_CTRL, 0x11c)
 +    FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1)
 +    FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1)
 +    FIELD(GEM1_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3)
 +REG32(GEM_TSU_REF_CTRL, 0x120)
 +    FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3)
 +REG32(USB0_BUS_REF_CTRL, 0x124)
 +    FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3)
 +REG32(UART0_REF_CTRL, 0x128)
 +    FIELD(UART0_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(UART0_REF_CTRL, SRCSEL, 0, 3)
 +REG32(UART1_REF_CTRL, 0x12c)
 +    FIELD(UART1_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(UART1_REF_CTRL, SRCSEL, 0, 3)
 +REG32(SPI0_REF_CTRL, 0x130)
 +    FIELD(SPI0_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3)
 +REG32(SPI1_REF_CTRL, 0x134)
 +    FIELD(SPI1_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3)
 +REG32(CAN0_REF_CTRL, 0x138)
 +    FIELD(CAN0_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3)
 +REG32(CAN1_REF_CTRL, 0x13c)
 +    FIELD(CAN1_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3)
 +REG32(I2C0_REF_CTRL, 0x140)
 +    FIELD(I2C0_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3)
 +REG32(I2C1_REF_CTRL, 0x144)
 +    FIELD(I2C1_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3)
 +REG32(DBG_LPD_CTRL, 0x148)
 +    FIELD(DBG_LPD_CTRL, CLKACT, 25, 1)
 +    FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10)
 +    FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3)
 +REG32(TIMESTAMP_REF_CTRL, 0x14c)
 +    FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
 +REG32(CRL_SAFETY_CHK, 0x150)
 +REG32(PSM_REF_CTRL, 0x154)
 +    FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(PSM_REF_CTRL, SRCSEL, 0, 3)
 +REG32(DBG_TSTMP_CTRL, 0x158)
 +    FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1)
 +    FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10)
 +    FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
 +REG32(CPM_TOPSW_REF_CTRL, 0x15c)
 +    FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3)
 +REG32(USB3_DUAL_REF_CTRL, 0x160)
 +    FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3)
 +REG32(RST_CPU_R5, 0x300)
 +    FIELD(RST_CPU_R5, RESET_PGE, 4, 1)
 +    FIELD(RST_CPU_R5, RESET_AMBA, 2, 1)
 +    FIELD(RST_CPU_R5, RESET_CPU1, 1, 1)
 +    FIELD(RST_CPU_R5, RESET_CPU0, 0, 1)
 +REG32(RST_ADMA, 0x304)
 +    FIELD(RST_ADMA, RESET, 0, 1)
 +REG32(RST_GEM0, 0x308)
 +    FIELD(RST_GEM0, RESET, 0, 1)
 +REG32(RST_GEM1, 0x30c)
 +    FIELD(RST_GEM1, RESET, 0, 1)
 +REG32(RST_SPARE, 0x310)
 +    FIELD(RST_SPARE, RESET, 0, 1)
 +REG32(RST_USB0, 0x314)
 +    FIELD(RST_USB0, RESET, 0, 1)
 +REG32(RST_UART0, 0x318)
 +    FIELD(RST_UART0, RESET, 0, 1)
 +REG32(RST_UART1, 0x31c)
 +    FIELD(RST_UART1, RESET, 0, 1)
 +REG32(RST_SPI0, 0x320)
 +    FIELD(RST_SPI0, RESET, 0, 1)
 +REG32(RST_SPI1, 0x324)
 +    FIELD(RST_SPI1, RESET, 0, 1)
 +REG32(RST_CAN0, 0x328)
 +    FIELD(RST_CAN0, RESET, 0, 1)
 +REG32(RST_CAN1, 0x32c)
 +    FIELD(RST_CAN1, RESET, 0, 1)
 +REG32(RST_I2C0, 0x330)
 +    FIELD(RST_I2C0, RESET, 0, 1)
 +REG32(RST_I2C1, 0x334)
 +    FIELD(RST_I2C1, RESET, 0, 1)
 +REG32(RST_DBG_LPD, 0x338)
 +    FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1)
 +    FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1)
 +    FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1)
 +    FIELD(RST_DBG_LPD, RESET, 0, 1)
 +REG32(RST_GPIO, 0x33c)
 +    FIELD(RST_GPIO, RESET, 0, 1)
 +REG32(RST_TTC, 0x344)
 +    FIELD(RST_TTC, TTC3_RESET, 3, 1)
 +    FIELD(RST_TTC, TTC2_RESET, 2, 1)
 +    FIELD(RST_TTC, TTC1_RESET, 1, 1)
 +    FIELD(RST_TTC, TTC0_RESET, 0, 1)
 +REG32(RST_TIMESTAMP, 0x348)
 +    FIELD(RST_TIMESTAMP, RESET, 0, 1)
 +REG32(RST_SWDT, 0x34c)
 +    FIELD(RST_SWDT, RESET, 0, 1)
 +REG32(RST_OCM, 0x350)
 +    FIELD(RST_OCM, RESET, 0, 1)
 +REG32(RST_IPI, 0x354)
 +    FIELD(RST_IPI, RESET, 0, 1)
 +REG32(RST_SYSMON, 0x358)
 +    FIELD(RST_SYSMON, SEQ_RST, 1, 1)
 +    FIELD(RST_SYSMON, CFG_RST, 0, 1)
 +REG32(RST_FPD, 0x360)
 +    FIELD(RST_FPD, SRST, 1, 1)
 +    FIELD(RST_FPD, POR, 0, 1)
 +REG32(PSM_RST_MODE, 0x370)
 +    FIELD(PSM_RST_MODE, WAKEUP, 2, 1)
 +    FIELD(PSM_RST_MODE, RST_MODE, 0, 2)
 +
 +#define CRL_R_MAX (R_PSM_RST_MODE + 1)
 +
 +#define RPU_MAX_CPU 2
 +
 +struct XlnxVersalCRL {
 +    SysBusDevice parent_obj;
 +    qemu_irq irq;
 +
 +    struct {
 +        ARMCPU *cpu_r5[RPU_MAX_CPU];
 +        DeviceState *adma[8];
 +        DeviceState *uart[2];
 +        DeviceState *gem[2];
 +        DeviceState *usb;
 +    } cfg;
 +
 +    RegisterInfoArray *reg_array;
 +    uint32_t regs[CRL_R_MAX];
 +    RegisterInfo regs_info[CRL_R_MAX];
 +};
-+
++#endif
-+#define USBPHY_CTRL_SFTRST BIT(31)
+diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
 +
 +#define TYPE_IMX_USBPHY "imx.usbphy"
 +#define IMX_USBPHY(obj) OBJECT_CHECK(IMXUSBPHYState, (obj), TYPE_IMX_USBPHY)
 +
 +typedef struct IMXUSBPHYState {
 +    /* <private> */
 +    SysBusDevice parent_obj;
 +
 +    /* <public> */
 +    MemoryRegion iomem;
 +
 +    uint32_t usbphy[USBPHY_MAX];
 +} IMXUSBPHYState;
 +
 +#endif /* IMX_USB_PHY_H */
 diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/hw/usb/imx-usb-phy.c
++++ b/hw/misc/xlnx-versal-crl.c
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * i.MX USB PHY
++ * QEMU model of the Clock-Reset-LPD (CRL).
 + *
-+ * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
++ * Copyright (c) 2022 Advanced Micro Devices, Inc.
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + *
-+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
++ * Written by Edgar E. Iglesias <edgar.iglesias@amd.com>
 + * See the COPYING file in the top-level directory.
 + *
 + * We need to implement basic reset control in the PHY control register.
 + * For everything else, it is sufficient to set whatever is written.
 + */
 +
 +#include "qemu/osdep.h"
-+#include "hw/usb/imx-usb-phy.h"
++#include "qapi/error.h"
 +#include "qemu/log.h"
 +#include "qemu/bitops.h"
 +#include "migration/vmstate.h"
-+#include "qemu/log.h"
++#include "hw/qdev-properties.h"
-+#include "qemu/module.h"
++#include "hw/sysbus.h"
-+
++#include "hw/irq.h"
-+static const VMStateDescription vmstate_imx_usbphy = {
++#include "hw/register.h"
-+    .name = TYPE_IMX_USBPHY,
++#include "hw/resettable.h"
 +
 +#include "target/arm/arm-powerctl.h"
 +#include "hw/misc/xlnx-versal-crl.h"
 +
 +#ifndef XLNX_VERSAL_CRL_ERR_DEBUG
 +#define XLNX_VERSAL_CRL_ERR_DEBUG 0
 +#endif
 +
 +static void crl_update_irq(XlnxVersalCRL *s)
 +{
 +    bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
 +    qemu_set_irq(s->irq, pending);
 +}
 +
 +static void crl_status_postw(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +    crl_update_irq(s);
 +}
 +
 +static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +    uint32_t val = val64;
 +
 +    s->regs[R_IR_MASK] &= ~val;
 +    crl_update_irq(s);
 +    return 0;
 +}
 +
 +static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +    uint32_t val = val64;
 +
 +    s->regs[R_IR_MASK] |= val;
 +    crl_update_irq(s);
 +    return 0;
 +}
 +
 +static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev,
 +                          bool rst_old, bool rst_new)
 +{
 +    device_cold_reset(dev);
 +}
 +
 +static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu,
 +                          bool rst_old, bool rst_new)
 +{
 +    if (rst_new) {
 +        arm_set_cpu_off(armcpu->mp_affinity);
 +    } else {
 +        arm_set_cpu_on_and_reset(armcpu->mp_affinity);
 +    }
 +}
 +
 +#define REGFIELD_RESET(type, s, reg, f, new_val, dev) {     \
 +    bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f);       \
 +    bool new_f = FIELD_EX32(new_val, reg, f);               \
 +                                                            \
 +    /* Detect edges.  */                                    \
 +    if (dev && old_f != new_f) {                            \
 +        crl_reset_ ## type(s, dev, old_f, new_f);           \
 +    }                                                       \
 +}
 +
 +static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]);
 +    REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]);
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +    int i;
 +
 +    /* A single register fans out to all ADMA reset inputs.  */
 +    for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) {
 +        REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]);
 +    }
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]);
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]);
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]);
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]);
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb);
 +    return val64;
 +}
 +
 +static const RegisterAccessInfo crl_regs_info[] = {
 +    {   .name = "ERR_CTRL",  .addr = A_ERR_CTRL,
 +    },{ .name = "IR_STATUS",  .addr = A_IR_STATUS,
 +        .w1c = 0x1,
 +        .post_write = crl_status_postw,
 +    },{ .name = "IR_MASK",  .addr = A_IR_MASK,
 +        .reset = 0x1,
 +        .ro = 0x1,
 +    },{ .name = "IR_ENABLE",  .addr = A_IR_ENABLE,
 +        .pre_write = crl_enable_prew,
 +    },{ .name = "IR_DISABLE",  .addr = A_IR_DISABLE,
 +        .pre_write = crl_disable_prew,
 +    },{ .name = "WPROT",  .addr = A_WPROT,
 +    },{ .name = "PLL_CLK_OTHER_DMN",  .addr = A_PLL_CLK_OTHER_DMN,
 +        .reset = 0x1,
 +        .rsvd = 0xe,
 +    },{ .name = "RPLL_CTRL",  .addr = A_RPLL_CTRL,
 +        .reset = 0x24809,
 +        .rsvd = 0xf88c00f6,
 +    },{ .name = "RPLL_CFG",  .addr = A_RPLL_CFG,
 +        .reset = 0x2000000,
 +        .rsvd = 0x1801210,
 +    },{ .name = "RPLL_FRAC_CFG",  .addr = A_RPLL_FRAC_CFG,
 +        .rsvd = 0x7e330000,
 +    },{ .name = "PLL_STATUS",  .addr = A_PLL_STATUS,
 +        .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
 +                 R_PLL_STATUS_RPLL_LOCK_MASK,
 +        .rsvd = 0xfa,
 +        .ro = 0x5,
 +    },{ .name = "RPLL_TO_XPD_CTRL",  .addr = A_RPLL_TO_XPD_CTRL,
 +        .reset = 0x2000100,
 +        .rsvd = 0xfdfc00ff,
 +    },{ .name = "LPD_TOP_SWITCH_CTRL",  .addr = A_LPD_TOP_SWITCH_CTRL,
 +        .reset = 0x6000300,
 +        .rsvd = 0xf9fc00f8,
 +    },{ .name = "LPD_LSBUS_CTRL",  .addr = A_LPD_LSBUS_CTRL,
 +        .reset = 0x2000800,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "CPU_R5_CTRL",  .addr = A_CPU_R5_CTRL,
 +        .reset = 0xe000300,
 +        .rsvd = 0xe1fc00f8,
 +    },{ .name = "IOU_SWITCH_CTRL",  .addr = A_IOU_SWITCH_CTRL,
 +        .reset = 0x2000500,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "GEM0_REF_CTRL",  .addr = A_GEM0_REF_CTRL,
 +        .reset = 0xe000a00,
 +        .rsvd = 0xf1fc00f8,
 +    },{ .name = "GEM1_REF_CTRL",  .addr = A_GEM1_REF_CTRL,
 +        .reset = 0xe000a00,
 +        .rsvd = 0xf1fc00f8,
 +    },{ .name = "GEM_TSU_REF_CTRL",  .addr = A_GEM_TSU_REF_CTRL,
 +        .reset = 0x300,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "USB0_BUS_REF_CTRL",  .addr = A_USB0_BUS_REF_CTRL,
 +        .reset = 0x2001900,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "UART0_REF_CTRL",  .addr = A_UART0_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "UART1_REF_CTRL",  .addr = A_UART1_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "SPI0_REF_CTRL",  .addr = A_SPI0_REF_CTRL,
 +        .reset = 0x600,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "SPI1_REF_CTRL",  .addr = A_SPI1_REF_CTRL,
 +        .reset = 0x600,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "CAN0_REF_CTRL",  .addr = A_CAN0_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "CAN1_REF_CTRL",  .addr = A_CAN1_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "I2C0_REF_CTRL",  .addr = A_I2C0_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "I2C1_REF_CTRL",  .addr = A_I2C1_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "DBG_LPD_CTRL",  .addr = A_DBG_LPD_CTRL,
 +        .reset = 0x300,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "TIMESTAMP_REF_CTRL",  .addr = A_TIMESTAMP_REF_CTRL,
 +        .reset = 0x2000c00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "CRL_SAFETY_CHK",  .addr = A_CRL_SAFETY_CHK,
 +    },{ .name = "PSM_REF_CTRL",  .addr = A_PSM_REF_CTRL,
 +        .reset = 0xf04,
 +        .rsvd = 0xfffc00f8,
 +    },{ .name = "DBG_TSTMP_CTRL",  .addr = A_DBG_TSTMP_CTRL,
 +        .reset = 0x300,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "CPM_TOPSW_REF_CTRL",  .addr = A_CPM_TOPSW_REF_CTRL,
 +        .reset = 0x300,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "USB3_DUAL_REF_CTRL",  .addr = A_USB3_DUAL_REF_CTRL,
 +        .reset = 0x3c00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "RST_CPU_R5",  .addr = A_RST_CPU_R5,
 +        .reset = 0x17,
 +        .rsvd = 0x8,
 +        .pre_write = crl_rst_r5_prew,
 +    },{ .name = "RST_ADMA",  .addr = A_RST_ADMA,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_adma_prew,
 +    },{ .name = "RST_GEM0",  .addr = A_RST_GEM0,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_gem0_prew,
 +    },{ .name = "RST_GEM1",  .addr = A_RST_GEM1,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_gem1_prew,
 +    },{ .name = "RST_SPARE",  .addr = A_RST_SPARE,
 +        .reset = 0x1,
 +    },{ .name = "RST_USB0",  .addr = A_RST_USB0,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_usb_prew,
 +    },{ .name = "RST_UART0",  .addr = A_RST_UART0,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_uart0_prew,
 +    },{ .name = "RST_UART1",  .addr = A_RST_UART1,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_uart1_prew,
 +    },{ .name = "RST_SPI0",  .addr = A_RST_SPI0,
 +        .reset = 0x1,
 +    },{ .name = "RST_SPI1",  .addr = A_RST_SPI1,
 +        .reset = 0x1,
 +    },{ .name = "RST_CAN0",  .addr = A_RST_CAN0,
 +        .reset = 0x1,
 +    },{ .name = "RST_CAN1",  .addr = A_RST_CAN1,
 +        .reset = 0x1,
 +    },{ .name = "RST_I2C0",  .addr = A_RST_I2C0,
 +        .reset = 0x1,
 +    },{ .name = "RST_I2C1",  .addr = A_RST_I2C1,
 +        .reset = 0x1,
 +    },{ .name = "RST_DBG_LPD",  .addr = A_RST_DBG_LPD,
 +        .reset = 0x33,
 +        .rsvd = 0xcc,
 +    },{ .name = "RST_GPIO",  .addr = A_RST_GPIO,
 +        .reset = 0x1,
 +    },{ .name = "RST_TTC",  .addr = A_RST_TTC,
 +        .reset = 0xf,
 +    },{ .name = "RST_TIMESTAMP",  .addr = A_RST_TIMESTAMP,
 +        .reset = 0x1,
 +    },{ .name = "RST_SWDT",  .addr = A_RST_SWDT,
 +        .reset = 0x1,
 +    },{ .name = "RST_OCM",  .addr = A_RST_OCM,
 +    },{ .name = "RST_IPI",  .addr = A_RST_IPI,
 +    },{ .name = "RST_FPD",  .addr = A_RST_FPD,
 +        .reset = 0x3,
 +    },{ .name = "PSM_RST_MODE",  .addr = A_PSM_RST_MODE,
 +        .reset = 0x1,
 +        .rsvd = 0xf8,
 +    }
 +};
 +
 +static void crl_reset_enter(Object *obj, ResetType type)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
 +    unsigned int i;
 +
 +    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
 +        register_reset(&s->regs_info[i]);
 +    }
 +}
 +
 +static void crl_reset_hold(Object *obj)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
 +
 +    crl_update_irq(s);
 +}
 +
 +static const MemoryRegionOps crl_ops = {
 +    .read = register_read_memory,
 +    .write = register_write_memory,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +    },
 +};
 +
 +static void crl_init(Object *obj)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    int i;
 +
 +    s->reg_array =
 +        register_init_block32(DEVICE(obj), crl_regs_info,
 +                              ARRAY_SIZE(crl_regs_info),
 +                              s->regs_info, s->regs,
 +                              &crl_ops,
 +                              XLNX_VERSAL_CRL_ERR_DEBUG,
 +                              CRL_R_MAX * 4);
 +    sysbus_init_mmio(sbd, &s->reg_array->mem);
 +    sysbus_init_irq(sbd, &s->irq);
 +
 +    for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) {
 +        object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU,
 +                                 (Object **)&s->cfg.cpu_r5[i],
 +                                 qdev_prop_allow_set_link_before_realize,
 +                                 OBJ_PROP_LINK_STRONG);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) {
 +        object_property_add_link(obj, "adma[*]", TYPE_DEVICE,
 +                                 (Object **)&s->cfg.adma[i],
 +                                 qdev_prop_allow_set_link_before_realize,
 +                                 OBJ_PROP_LINK_STRONG);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) {
 +        object_property_add_link(obj, "uart[*]", TYPE_DEVICE,
 +                                 (Object **)&s->cfg.uart[i],
 +                                 qdev_prop_allow_set_link_before_realize,
 +                                 OBJ_PROP_LINK_STRONG);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) {
 +        object_property_add_link(obj, "gem[*]", TYPE_DEVICE,
 +                                 (Object **)&s->cfg.gem[i],
 +                                 qdev_prop_allow_set_link_before_realize,
 +                                 OBJ_PROP_LINK_STRONG);
 +    }
 +
 +    object_property_add_link(obj, "usb", TYPE_DEVICE,
 +                             (Object **)&s->cfg.gem[i],
 +                             qdev_prop_allow_set_link_before_realize,
 +                             OBJ_PROP_LINK_STRONG);
 +}
 +
 +static void crl_finalize(Object *obj)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
 +    register_finalize_block(s->reg_array);
 +}
 +
 +static const VMStateDescription vmstate_crl = {
 +    .name = TYPE_XLNX_VERSAL_CRL,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
-+        VMSTATE_UINT32_ARRAY(usbphy, IMXUSBPHYState, USBPHY_MAX),
++        VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX),
-+        VMSTATE_END_OF_LIST()
++        VMSTATE_END_OF_LIST(),
-+    },
++    }
 +};
 +
-+static void imx_usbphy_softreset(IMXUSBPHYState *s)
++static void crl_class_init(ObjectClass *klass, void *data)
 +{
-+    s->usbphy[USBPHY_PWD] = 0x001e1c00;
++    ResettableClass *rc = RESETTABLE_CLASS(klass);
-+    s->usbphy[USBPHY_TX] = 0x10060607;
++    DeviceClass *dc = DEVICE_CLASS(klass);
-+    s->usbphy[USBPHY_RX] = 0x00000000;
++
-+    s->usbphy[USBPHY_CTRL] = 0xc0200000;
++    dc->vmsd = &vmstate_crl;
-+}
++
-+
++    rc->phases.enter = crl_reset_enter;
-+static void imx_usbphy_reset(DeviceState *dev)
++    rc->phases.hold = crl_reset_hold;
-+{
++}
-+    IMXUSBPHYState *s = IMX_USBPHY(dev);
++
-+
++static const TypeInfo crl_info = {
-+    s->usbphy[USBPHY_STATUS] = 0x00000000;
++    .name          = TYPE_XLNX_VERSAL_CRL,
-+    s->usbphy[USBPHY_DEBUG] = 0x7f180000;
++    .parent        = TYPE_SYS_BUS_DEVICE,
-+    s->usbphy[USBPHY_DEBUG0_STATUS] = 0x00000000;
++    .instance_size = sizeof(XlnxVersalCRL),
-+    s->usbphy[USBPHY_DEBUG1] = 0x00001000;
++    .class_init    = crl_class_init,
-+    s->usbphy[USBPHY_VERSION] = 0x04020000;
++    .instance_init = crl_init,
-+
++    .instance_finalize = crl_finalize,
 +    imx_usbphy_softreset(s);
 +}
 +
 +static uint64_t imx_usbphy_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
 +    uint32_t index = offset >> 2;
 +    uint32_t value;
 +
 +    switch (index) {
 +    case USBPHY_PWD_SET:
 +    case USBPHY_TX_SET:
 +    case USBPHY_RX_SET:
 +    case USBPHY_CTRL_SET:
 +    case USBPHY_DEBUG_SET:
 +    case USBPHY_DEBUG1_SET:
 +        /*
 +         * All REG_NAME_SET register access are in fact targeting the
 +         * REG_NAME register.
 +         */
 +        value = s->usbphy[index - 1];
 +        break;
 +    case USBPHY_PWD_CLR:
 +    case USBPHY_TX_CLR:
 +    case USBPHY_RX_CLR:
 +    case USBPHY_CTRL_CLR:
 +    case USBPHY_DEBUG_CLR:
 +    case USBPHY_DEBUG1_CLR:
 +        /*
 +         * All REG_NAME_CLR register access are in fact targeting the
 +         * REG_NAME register.
 +         */
 +        value = s->usbphy[index - 2];
 +        break;
 +    case USBPHY_PWD_TOG:
 +    case USBPHY_TX_TOG:
 +    case USBPHY_RX_TOG:
 +    case USBPHY_CTRL_TOG:
 +    case USBPHY_DEBUG_TOG:
 +    case USBPHY_DEBUG1_TOG:
 +        /*
 +         * All REG_NAME_TOG register access are in fact targeting the
 +         * REG_NAME register.
 +         */
 +        value = s->usbphy[index - 3];
 +        break;
 +    default:
 +        value = s->usbphy[index];
 +        break;
 +    }
 +    return (uint64_t)value;
 +}
 +
 +static void imx_usbphy_write(void *opaque, hwaddr offset, uint64_t value,
 +                             unsigned size)
 +{
 +    IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
 +    uint32_t index = offset >> 2;
 +
 +    switch (index) {
 +    case USBPHY_CTRL:
 +        s->usbphy[index] = value;
 +        if (value & USBPHY_CTRL_SFTRST) {
 +            imx_usbphy_softreset(s);
 +        }
 +        break;
 +    case USBPHY_PWD:
 +    case USBPHY_TX:
 +    case USBPHY_RX:
 +    case USBPHY_STATUS:
 +    case USBPHY_DEBUG:
 +    case USBPHY_DEBUG1:
 +        s->usbphy[index] = value;
 +        break;
 +    case USBPHY_CTRL_SET:
 +        s->usbphy[index - 1] |= value;
 +        if (value & USBPHY_CTRL_SFTRST) {
 +            imx_usbphy_softreset(s);
 +        }
 +        break;
 +    case USBPHY_PWD_SET:
 +    case USBPHY_TX_SET:
 +    case USBPHY_RX_SET:
 +    case USBPHY_DEBUG_SET:
 +    case USBPHY_DEBUG1_SET:
 +        /*
 +         * All REG_NAME_SET register access are in fact targeting the
 +         * REG_NAME register. So we change the value of the REG_NAME
 +         * register, setting bits passed in the value.
 +         */
 +        s->usbphy[index - 1] |= value;
 +        break;
 +    case USBPHY_PWD_CLR:
 +    case USBPHY_TX_CLR:
 +    case USBPHY_RX_CLR:
 +    case USBPHY_CTRL_CLR:
 +    case USBPHY_DEBUG_CLR:
 +    case USBPHY_DEBUG1_CLR:
 +        /*
 +         * All REG_NAME_CLR register access are in fact targeting the
 +         * REG_NAME register. So we change the value of the REG_NAME
 +         * register, unsetting bits passed in the value.
 +         */
 +        s->usbphy[index - 2] &= ~value;
 +        break;
 +    case USBPHY_CTRL_TOG:
 +        s->usbphy[index - 3] ^= value;
 +        if ((value & USBPHY_CTRL_SFTRST) &&
 +            (s->usbphy[index - 3] & USBPHY_CTRL_SFTRST)) {
 +            imx_usbphy_softreset(s);
 +        }
 +        break;
 +    case USBPHY_PWD_TOG:
 +    case USBPHY_TX_TOG:
 +    case USBPHY_RX_TOG:
 +    case USBPHY_DEBUG_TOG:
 +    case USBPHY_DEBUG1_TOG:
 +        /*
 +         * All REG_NAME_TOG register access are in fact targeting the
 +         * REG_NAME register. So we change the value of the REG_NAME
 +         * register, toggling bits passed in the value.
 +         */
 +        s->usbphy[index - 3] ^= value;
 +        break;
 +    default:
 +        /* Other registers are read-only */
 +        break;
 +    }
 +}
 +
 +static const struct MemoryRegionOps imx_usbphy_ops = {
 +    .read = imx_usbphy_read,
 +    .write = imx_usbphy_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .valid = {
 +        /*
 +         * Our device would not work correctly if the guest was doing
 +         * unaligned access. This might not be a limitation on the real
 +         * device but in practice there is no reason for a guest to access
 +         * this device unaligned.
 +         */
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +        .unaligned = false,
 +    },
 +};
 +
-+static void imx_usbphy_realize(DeviceState *dev, Error **errp)
++static void crl_register_types(void)
 +{
-+    IMXUSBPHYState *s = IMX_USBPHY(dev);
++    type_register_static(&crl_info);
-+
++}
-+    memory_region_init_io(&s->iomem, OBJECT(s), &imx_usbphy_ops, s,
++
-+                          "imx-usbphy", 0x1000);
++type_init(crl_register_types)
-+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 +}
 +
 +static void imx_usbphy_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->reset = imx_usbphy_reset;
 +    dc->vmsd = &vmstate_imx_usbphy;
 +    dc->desc = "i.MX USB PHY Module";
 +    dc->realize = imx_usbphy_realize;
 +}
 +
 +static const TypeInfo imx_usbphy_info = {
 +    .name          = TYPE_IMX_USBPHY,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(IMXUSBPHYState),
 +    .class_init    = imx_usbphy_class_init,
 +};
 +
 +static void imx_usbphy_register_types(void)
 +{
 +    type_register_static(&imx_usbphy_info);
 +}
 +
 +type_init(imx_usbphy_register_types)
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/hw/misc/meson.build
-+++ b/MAINTAINERS
++++ b/hw/misc/meson.build
-@@ -XXX,XX +XXX,XX @@ F: hw/arm/sabrelite.c
+@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
- F: hw/arm/fsl-imx6.c
+ softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
- F: hw/misc/imx6_*.c
+ specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
- F: hw/ssi/imx_spi.c
+ specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
-+F: hw/usb/imx-usb-phy.c
++specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
-+F: include/hw/usb/imx-usb-phy.h
+ softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
- F: include/hw/arm/fsl-imx6.h
+   'xlnx-versal-xramc.c',
- F: include/hw/misc/imx6_*.h
+   'xlnx-versal-pmc-iou-slcr.c',
  F: include/hw/ssi/imx_spi.h
 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/Kconfig
 +++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
      select IMX
      select IMX_FEC
      select IMX_I2C
 +    select IMX_USBPHY
      select SDHCI
  config ASPEED_SOC
 diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/usb/Kconfig
 +++ b/hw/usb/Kconfig
@@ -XXX,XX +XXX,XX @@ config USB_STORAGE_MTP
      bool
      default y
      depends on USB
 +
 +config IMX_USBPHY
 +    bool
 +    default y
 +    depends on USB
 --
-.20.1
+.25.1

-[PULL 04/11] hw/arm/fsl-imx6ul: Wire up USB controllers
+[PULL 07/31] hw/arm: versal: Connect the CRL
-From: Guenter Roeck <linux@roeck-us.net>
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
-IMX6UL USB controllers are quite similar to IMX7 USB controllers.
+Connect the CRL (Clock Reset LPD) to the Versal SoC.
 Wire them up the same way.
-The only real difference is that wiring up phy devices is necessary
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
-to avoid phy reset timeouts in the Linux kernel.
+Reviewed-by: Frederic Konrad <fkonrad@amd.com>
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com
 Message-id: 20200313014551.12554-5-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/fsl-imx6ul.h | 10 ++++++++++
+ include/hw/arm/xlnx-versal.h |  4 +++
- hw/arm/fsl-imx6ul.c         | 35 +++++++++++++++++++++++++++++++++++
+ hw/arm/xlnx-versal.c         | 54 ++++++++++++++++++++++++++++++++++--
-files changed, 45 insertions(+)
+files changed, 56 insertions(+), 2 deletions(-)
-diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx6ul.h
+--- a/include/hw/arm/xlnx-versal.h
-+++ b/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/xlnx-versal.h
 @@ -XXX,XX +XXX,XX @@
- #include "hw/sd/sdhci.h"
+ #include "hw/nvram/xlnx-versal-efuse.h"
- #include "hw/ssi/imx_spi.h"
+ #include "hw/ssi/xlnx-versal-ospi.h"
- #include "hw/net/imx_fec.h"
+ #include "hw/dma/xlnx_csu_dma.h"
-+#include "hw/usb/chipidea.h"
++#include "hw/misc/xlnx-versal-crl.h"
-+#include "hw/usb/imx-usb-phy.h"
+ #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
- #include "exec/memory.h"
- #include "cpu.h"
+ #define TYPE_XLNX_VERSAL "xlnx-versal"
+@@ -XXX,XX +XXX,XX @@ struct Versal {
-@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
+             qemu_or_irq irq_orgate;
-     FSL_IMX6UL_NUM_I2CS         = 4,
+             XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
-     FSL_IMX6UL_NUM_ECSPIS       = 4,
+         } xram;
-     FSL_IMX6UL_NUM_ADCS         = 2,
++
-+    FSL_IMX6UL_NUM_USB_PHYS     = 2,
++        XlnxVersalCRL crl;
-+    FSL_IMX6UL_NUM_USBS         = 2,
+     } lpd;
- };
+     /* The Platform Management Controller subsystem.  */
- typedef struct FslIMX6ULState {
+@@ -XXX,XX +XXX,XX @@ struct Versal {
-@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
+ #define VERSAL_TIMER_NS_EL1_IRQ     14
-     IMXFECState        eth[FSL_IMX6UL_NUM_ETHS];
+ #define VERSAL_TIMER_NS_EL2_IRQ     10
-     SDHCIState         usdhc[FSL_IMX6UL_NUM_USDHCS];
-     IMX2WdtState       wdt[FSL_IMX6UL_NUM_WDTS];
++#define VERSAL_CRL_IRQ             10
-+    IMXUSBPHYState     usbphy[FSL_IMX6UL_NUM_USB_PHYS];
+ #define VERSAL_UART0_IRQ_0         18
-+    ChipideaState      usb[FSL_IMX6UL_NUM_USBS];
+ #define VERSAL_UART1_IRQ_0         19
-     MemoryRegion       rom;
+ #define VERSAL_USB0_IRQ_0          22
-     MemoryRegion       caam;
+diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
      MemoryRegion       ocram;
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULMemoryMap {
      FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
      FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
      FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
 +    FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
 +    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
 +    FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
 +    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
      FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
      FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
      FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
 diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/fsl-imx6ul.c
+--- a/hw/arm/xlnx-versal.c
-+++ b/hw/arm/fsl-imx6ul.c
++++ b/hw/arm/xlnx-versal.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void versal_create_ospi(Versal *s, qemu_irq *pic)
- #include "qapi/error.h"
+     qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
- #include "hw/arm/fsl-imx6ul.h"
+ }
- #include "hw/misc/unimp.h"
-+#include "hw/usb/imx-usb-phy.h"
++static void versal_create_crl(Versal *s, qemu_irq *pic)
- #include "hw/boards.h"
++{
- #include "sysemu/sysemu.h"
++    SysBusDevice *sbd;
- #include "qemu/error-report.h"
++    int i;
-@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
++
-                               TYPE_IMX_ENET);
++    object_initialize_child(OBJECT(s), "crl", &s->lpd.crl,
-     }
++                            TYPE_XLNX_VERSAL_CRL);
++    sbd = SYS_BUS_DEVICE(&s->lpd.crl);
-+    /* USB */
++
-+    for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
++    for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
-+        snprintf(name, NAME_SIZE, "usbphy%d", i);
++        g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i);
-+        sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
++
-+                              TYPE_IMX_USBPHY);
++        object_property_set_link(OBJECT(&s->lpd.crl),
-+    }
++                                 name, OBJECT(&s->lpd.rpu.cpu[i]),
-+    for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
++                                 &error_abort);
 +        snprintf(name, NAME_SIZE, "usb%d", i);
 +        sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
 +                              TYPE_CHIPIDEA);
 +    }
 +
-     /*
++    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
-      * SDHCI
++        g_autofree gchar *name = g_strdup_printf("gem[%d]", i);
-      */
++
-@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
++        object_property_set_link(OBJECT(&s->lpd.crl),
-                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
++                                 name, OBJECT(&s->lpd.iou.gem[i]),
      }
 +    /* USB */
 +    for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
 +        object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
 +                                 &error_abort);
-+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
-+                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
 +    }
 +
-+    for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
++    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
-+        static const int FSL_IMX6UL_USBn_IRQ[] = {
++        g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
-+            FSL_IMX6UL_USB1_IRQ,
++
-+            FSL_IMX6UL_USB2_IRQ,
++        object_property_set_link(OBJECT(&s->lpd.crl),
-+        };
++                                 name, OBJECT(&s->lpd.iou.adma[i]),
 +        object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
 +                                 &error_abort);
-+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
-+                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
-+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
-+                           qdev_get_gpio_in(DEVICE(&s->a7mpcore),
-+                                            FSL_IMX6UL_USBn_IRQ[i]));
 +    }
 +
-     /*
++    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
-      * USDHC
++        g_autofree gchar *name = g_strdup_printf("uart[%d]", i);
-      */
++
 +        object_property_set_link(OBJECT(&s->lpd.crl),
 +                                 name, OBJECT(&s->lpd.iou.uart[i]),
 +                                 &error_abort);
 +    }
 +
 +    object_property_set_link(OBJECT(&s->lpd.crl),
 +                             "usb", OBJECT(&s->lpd.iou.usb),
 +                             &error_abort);
 +
 +    sysbus_realize(sbd, &error_fatal);
 +    memory_region_add_subregion(&s->mr_ps, MM_CRL,
 +                                sysbus_mmio_get_region(sbd, 0));
 +    sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]);
 +}
 +
  /* This takes the board allocated linear DDR memory and creates aliases
   * for each split DDR range/aperture on the Versal address map.
   */
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
      versal_unimp_area(s, "psm", &s->mr_ps,
                          MM_PSM_START, MM_PSM_END - MM_PSM_START);
 -    versal_unimp_area(s, "crl", &s->mr_ps,
 -                        MM_CRL, MM_CRL_SIZE);
      versal_unimp_area(s, "crf", &s->mr_ps,
                          MM_FPD_CRF, MM_FPD_CRF_SIZE);
      versal_unimp_area(s, "apu", &s->mr_ps,
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
      versal_create_efuse(s, pic);
      versal_create_pmc_iou_slcr(s, pic);
      versal_create_ospi(s, pic);
 +    versal_create_crl(s, pic);
      versal_map_ddr(s);
      versal_unimp(s);
 --
-.20.1
+.25.1

-New patch
+[PULL 08/31] hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device
+The Exynos4210 SoC device currently uses a custom device
+"exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ
+line.  We have a standard TYPE_OR_IRQ device for this now, so use
+that instead.
+(This is a migration compatibility break, but that is OK for this
+machine type.)
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-2-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  1 +
+ hw/arm/exynos4210.c         | 31 ++++++++++++++++---------------
+files changed, 17 insertions(+), 15 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
+     MemoryRegion bootreg_mem;
+     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
+     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
++    qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+ };
+ #define TYPE_EXYNOS4210_SOC "exynos4210"
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+ {
+     Exynos4210State *s = EXYNOS4210_SOC(socdev);
+     MemoryRegion *system_mem = get_system_memory();
+-    qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
+     SysBusDevice *busdev;
+     DeviceState *dev, *uart[4], *pl330[3];
+     int i, n;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     /* IRQ Gate */
+     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
+-        dev = qdev_new("exynos4210.irq_gate");
+-        qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
+-        sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+-        /* Get IRQ Gate input in gate_irq */
+-        for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
+-            gate_irq[i][n] = qdev_get_gpio_in(dev, n);
+-        }
+-        busdev = SYS_BUS_DEVICE(dev);
+-
+-        /* Connect IRQ Gate output to CPU's IRQ line */
+-        sysbus_connect_irq(busdev, 0,
+-                           qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
++        DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
++        object_property_set_int(OBJECT(orgate), "num-lines",
++                                EXYNOS4210_IRQ_GATE_NINPUTS,
++                                &error_abort);
++        qdev_realize(orgate, NULL, &error_abort);
++        qdev_connect_gpio_out(orgate, 0,
++                              qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
+     }
+     /* Private memory region and Internal GIC */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     sysbus_realize_and_unref(busdev, &error_fatal);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
+     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
+-        sysbus_connect_irq(busdev, n, gate_irq[n][0]);
++        sysbus_connect_irq(busdev, n,
++                           qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
+     }
+     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
+         s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     /* Map Distributer interface */
+     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
+     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
+-        sysbus_connect_irq(busdev, n, gate_irq[n][1]);
++        sysbus_connect_irq(busdev, n,
++                           qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
+     }
+     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
+         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
+         object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
+         g_free(name);
+     }
++
++    for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
++        g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
++        object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
++    }
+ }
+ static void exynos4210_class_init(ObjectClass *klass, void *data)
+--
+.25.1

-New patch
+[PULL 09/31] hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
+Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can
+delete the device entirely.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Message-id: 20220404154658.565020-3-peter.maydell@linaro.org
+---
+ hw/intc/exynos4210_gic.c | 107 ---------------------------------------
+file changed, 107 deletions(-)
+diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_gic.c
++++ b/hw/intc/exynos4210_gic.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_register_types(void)
+ }
+ type_init(exynos4210_gic_register_types)
+-
+-/* IRQ OR Gate struct.
+- *
+- * This device models an OR gate. There are n_in input qdev gpio lines and one
+- * output sysbus IRQ line. The output IRQ level is formed as OR between all
+- * gpio inputs.
+- */
+-
+-#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
+-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE)
+-
+-struct Exynos4210IRQGateState {
+-    SysBusDevice parent_obj;
+-
+-    uint32_t n_in;      /* inputs amount */
+-    uint32_t *level;    /* input levels */
+-    qemu_irq out;       /* output IRQ */
+-};
+-
+-static Property exynos4210_irq_gate_properties[] = {
+-    DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
+-    DEFINE_PROP_END_OF_LIST(),
+-};
+-
+-static const VMStateDescription vmstate_exynos4210_irq_gate = {
+-    .name = "exynos4210.irq_gate",
+-    .version_id = 2,
+-    .minimum_version_id = 2,
+-    .fields = (VMStateField[]) {
+-        VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in),
+-        VMSTATE_END_OF_LIST()
+-    }
+-};
+-
+-/* Process a change in IRQ input. */
+-static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
+-{
+-    Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque;
+-    uint32_t i;
+-
+-    assert(irq < s->n_in);
+-
+-    s->level[irq] = level;
+-
+-    for (i = 0; i < s->n_in; i++) {
+-        if (s->level[i] >= 1) {
+-            qemu_irq_raise(s->out);
+-            return;
+-        }
+-    }
+-
+-    qemu_irq_lower(s->out);
+-}
+-
+-static void exynos4210_irq_gate_reset(DeviceState *d)
+-{
+-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);
+-
+-    memset(s->level, 0, s->n_in * sizeof(*s->level));
+-}
+-
+-/*
+- * IRQ Gate initialization.
+- */
+-static void exynos4210_irq_gate_init(Object *obj)
+-{
+-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj);
+-    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+-
+-    sysbus_init_irq(sbd, &s->out);
+-}
+-
+-static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp)
+-{
+-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);
+-
+-    /* Allocate general purpose input signals and connect a handler to each of
+-     * them */
+-    qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);
+-
+-    s->level = g_malloc0(s->n_in * sizeof(*s->level));
+-}
+-
+-static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
+-{
+-    DeviceClass *dc = DEVICE_CLASS(klass);
+-
+-    dc->reset = exynos4210_irq_gate_reset;
+-    dc->vmsd = &vmstate_exynos4210_irq_gate;
+-    device_class_set_props(dc, exynos4210_irq_gate_properties);
+-    dc->realize = exynos4210_irq_gate_realize;
+-}
+-
+-static const TypeInfo exynos4210_irq_gate_info = {
+-    .name          = TYPE_EXYNOS4210_IRQ_GATE,
+-    .parent        = TYPE_SYS_BUS_DEVICE,
+-    .instance_size = sizeof(Exynos4210IRQGateState),
+-    .instance_init = exynos4210_irq_gate_init,
+-    .class_init    = exynos4210_irq_gate_class_init,
+-};
+-
+-static void exynos4210_irq_gate_register_types(void)
+-{
+-    type_register_static(&exynos4210_irq_gate_info);
+-}
+-
+-type_init(exynos4210_irq_gate_register_types)
+--
+.25.1

-[PULL 07/11] m25p80: Convert to support tracing
+[PULL 10/31] hw/arm/exynos4210: Put a9mpcore device into state struct
-From: Guenter Roeck <linux@roeck-us.net>
+The exynos4210 SoC mostly creates its child devices as if it were
 board code.  This includes the a9mpcore object.  Switch that to a
 new-style "embedded in the state struct" creation, because in the
 next commit we're going to want to refer to the object again further
 down in the exynos4210_realize() function.
-While at it, add some trace messages to help debug problems
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-seen when running the latest Linux kernel.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220404154658.565020-4-peter.maydell@linaro.org
 ---
  include/hw/arm/exynos4210.h |  2 ++
  hw/arm/exynos4210.c         | 11 ++++++-----
 files changed, 8 insertions(+), 5 deletions(-)
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/block/m25p80.c     | 48 ++++++++++++++++++++-----------------------
  hw/block/trace-events | 16 +++++++++++++++
 files changed, 38 insertions(+), 26 deletions(-)
 diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/include/hw/arm/exynos4210.h
-+++ b/hw/block/m25p80.c
++++ b/include/hw/arm/exynos4210.h
 @@ -XXX,XX +XXX,XX @@
- #include "qemu/module.h"
- #include "qemu/error-report.h"
+ #include "hw/or-irq.h"
- #include "qapi/error.h"
+ #include "hw/sysbus.h"
--
++#include "hw/cpu/a9mpcore.h"
--#ifndef M25P80_ERR_DEBUG
+ #include "target/arm/cpu-qom.h"
--#define M25P80_ERR_DEBUG 0
+ #include "qom/object.h"
--#endif
--
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
--#define DB_PRINT_L(level, ...) do { \
+     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
--    if (M25P80_ERR_DEBUG > (level)) { \
+     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
--        fprintf(stderr,  ": %s: ", __func__); \
+     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
--        fprintf(stderr, ## __VA_ARGS__); \
++    A9MPPrivState a9mpcore;
--    } \
+ };
--} while (0)
-+#include "trace.h"
+ #define TYPE_EXYNOS4210_SOC "exynos4210"
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
- /* Fields for FlashPartInfo->flags */
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
-@@ -XXX,XX +XXX,XX @@ static void flash_erase(Flash *s, int offset, FlashCMD cmd)
++++ b/hw/arm/exynos4210.c
-         abort();
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
      }
--    DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
+     /* Private memory region and Internal GIC */
-+    trace_m25p80_flash_erase(s, offset, len);
+-    dev = qdev_new(TYPE_A9MPCORE_PRIV);
 -    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
 -    busdev = SYS_BUS_DEVICE(dev);
 -    sysbus_realize_and_unref(busdev, &error_fatal);
 +    qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
 +    busdev = SYS_BUS_DEVICE(&s->a9mpcore);
 +    sysbus_realize(busdev, &error_fatal);
      sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
      for (n = 0; n < EXYNOS4210_NCPUS; n++) {
          sysbus_connect_irq(busdev, n,
                             qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
      }
      for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
 -        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
 +        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
      }
      /* Cache controller */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
          g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
          object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
      }
 +
-     if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
++    object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
          qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
                        " device\n", len);
@@ -XXX,XX +XXX,XX @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)
      }
      if ((prev ^ data) & data) {
 -        DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 "  %" PRIx8
 -                   " -> %" PRIx8 "\n", addr, prev, data);
 +        trace_m25p80_programming_zero_to_one(s, addr, prev, data);
      }
      if (s->pi->flags & EEPROM) {
@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
      s->state = STATE_IDLE;
 +    trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
 +                                     s->cur_addr);
 +
      switch (s->cmd_in_progress) {
      case DPP:
      case QPP:
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
          break;
      }
 -    DB_PRINT_L(0, "Reset done.\n");
 +    trace_m25p80_reset_done(s);
  }
- static void decode_fast_read_cmd(Flash *s)
+ static void exynos4210_class_init(ObjectClass *klass, void *data)
@@ -XXX,XX +XXX,XX @@ static void decode_qio_read_cmd(Flash *s)
  static void decode_new_cmd(Flash *s, uint32_t value)
  {
 -    s->cmd_in_progress = value;
      int i;
 -    DB_PRINT_L(0, "decoded new command:%x\n", value);
 +
 +    s->cmd_in_progress = value;
 +    trace_m25p80_command_decoded(s, value);
      if (value != RESET_MEMORY) {
          s->reset_enable = false;
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
          break;
      case JEDEC_READ:
 -        DB_PRINT_L(0, "populated jedec code\n");
 +        trace_m25p80_populated_jedec(s);
          for (i = 0; i < s->pi->id_len; i++) {
              s->data[i] = s->pi->id[i];
          }
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
      case BULK_ERASE_60:
      case BULK_ERASE:
          if (s->write_enable) {
 -            DB_PRINT_L(0, "chip erase\n");
 +            trace_m25p80_chip_erase(s);
              flash_erase(s, 0, BULK_ERASE);
          } else {
              qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
@@ -XXX,XX +XXX,XX @@ static int m25p80_cs(SSISlave *ss, bool select)
          s->data_read_loop = false;
      }
 -    DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
 +    trace_m25p80_select(s, select ? "de" : "");
      return 0;
  }
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
      Flash *s = M25P80(ss);
      uint32_t r = 0;
 +    trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
 +                          s->cur_addr, (uint8_t)tx);
 +
      switch (s->state) {
      case STATE_PAGE_PROGRAM:
 -        DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
 -                   s->cur_addr, (uint8_t)tx);
 +        trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
          flash_write8(s, s->cur_addr, (uint8_t)tx);
          s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
          break;
      case STATE_READ:
          r = s->storage[s->cur_addr];
 -        DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
 -                   (uint8_t)r);
 +        trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
          s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
          break;
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
          }
          r = s->data[s->pos];
 +        trace_m25p80_read_data(s, s->pos, (uint8_t)r);
          s->pos++;
          if (s->pos == s->len) {
              s->pos = 0;
@@ -XXX,XX +XXX,XX @@ static void m25p80_realize(SSISlave *ss, Error **errp)
              return;
          }
 -        DB_PRINT_L(0, "Binding to IF_MTD drive\n");
 +        trace_m25p80_binding(s);
          s->storage = blk_blockalign(s->blk, s->size);
          if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
@@ -XXX,XX +XXX,XX @@ static void m25p80_realize(SSISlave *ss, Error **errp)
              return;
          }
      } else {
 -        DB_PRINT_L(0, "No BDRV - binding to RAM\n");
 +        trace_m25p80_binding_no_bdrv(s);
          s->storage = blk_blockalign(NULL, s->size);
          memset(s->storage, 0xFF, s->size);
      }
 diff --git a/hw/block/trace-events b/hw/block/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/block/trace-events
 +++ b/hw/block/trace-events
@@ -XXX,XX +XXX,XX @@ xen_block_blockdev_add(char *str) "%s"
  xen_block_blockdev_del(const char *node_name) "%s"
  xen_block_device_create(unsigned int number) "%u"
  xen_block_device_destroy(unsigned int number) "%u"
 +
 +# m25p80.c
 +m25p80_flash_erase(void *s, int offset, uint32_t len) "[%p] offset = 0x%"PRIx32", len = %u"
 +m25p80_programming_zero_to_one(void *s, uint32_t addr, uint8_t prev, uint8_t data) "[%p] programming zero to one! addr=0x%"PRIx32"  0x%"PRIx8" -> 0x%"PRIx8
 +m25p80_reset_done(void *s) "[%p] Reset done."
 +m25p80_command_decoded(void *s, uint32_t cmd) "[%p] new command:0x%"PRIx32
 +m25p80_complete_collecting(void *s, uint32_t cmd, int n, uint8_t ear, uint32_t cur_addr) "[%p] decode cmd: 0x%"PRIx32" len %d ear 0x%"PRIx8" addr 0x%"PRIx32
 +m25p80_populated_jedec(void *s) "[%p] populated jedec code"
 +m25p80_chip_erase(void *s) "[%p] chip erase"
 +m25p80_select(void *s, const char *what) "[%p] %sselect"
 +m25p80_page_program(void *s, uint32_t addr, uint8_t tx) "[%p] page program cur_addr=0x%"PRIx32" data=0x%"PRIx8
 +m25p80_transfer(void *s, uint8_t state, uint32_t len, uint8_t needed, uint32_t pos, uint32_t cur_addr, uint8_t t) "[%p] Transfer state 0x%"PRIx8" len 0x%"PRIx32" needed 0x%"PRIx8" pos 0x%"PRIx32" addr 0x%"PRIx32" tx 0x%"PRIx8
 +m25p80_read_byte(void *s, uint32_t addr, uint8_t v) "[%p] Read byte 0x%"PRIx32"=0x%"PRIx8
 +m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0x%"PRIx8
 +m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
 +m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
 --
-.20.1
+.25.1

-New patch
+[PULL 11/31] hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct
+The only time we use the int_gic_irq[] array in the Exynos4210Irq
+struct is in the exynos4210_realize() function: we initialize it with
+the GPIO inputs of the a9mpcore device, and then a bit later on we
+connect those to the outputs of the internal combiner.  Now that the
+a9mpcore object is easily accessible as s->a9mpcore we can make the
+connection directly from one device to the other without going via
+this array.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-5-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h | 1 -
+ hw/arm/exynos4210.c         | 6 ++----
+files changed, 2 insertions(+), 5 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ typedef struct Exynos4210Irq {
+     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
+-    qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
+     qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
+     qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+ } Exynos4210Irq;
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+         sysbus_connect_irq(busdev, n,
+                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
+     }
+-    for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
+-        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
+-    }
+     /* Cache controller */
+     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     busdev = SYS_BUS_DEVICE(dev);
+     sysbus_realize_and_unref(busdev, &error_fatal);
+     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+-        sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
++        sysbus_connect_irq(busdev, n,
++                           qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
+     }
+     exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
+--
+.25.1

-New patch
+[PULL 12/31] hw/arm/exynos4210: Coalesce board_irqs and irq_table
+The exynos4210 code currently has two very similar arrays of IRQs:
+ * board_irqs is a field of the Exynos4210Irq struct which is filled
+   in by exynos4210_init_board_irqs() with the appropriate qemu_irqs
+   for each IRQ the board/SoC can assert
+ * irq_table is a set of qemu_irqs pointed to from the
+   Exynos4210State struct.  It's allocated in exynos4210_init_irq,
+   and the only behaviour these irqs have is that they pass on the
+   level to the equivalent board_irqs[] irq
+The extra indirection through irq_table is unnecessary, so coalesce
+these into a single irq_table[] array as a direct field in
+Exynos4210State which exynos4210_init_board_irqs() fills in.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-6-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  8 ++------
+ hw/arm/exynos4210.c         |  6 +-----
+ hw/intc/exynos4210_gic.c    | 32 ++++++++------------------------
+files changed, 11 insertions(+), 35 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
+     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
+     qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
+-    qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+ } Exynos4210Irq;
+ struct Exynos4210State {
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
+     /*< public >*/
+     ARMCPU *cpu[EXYNOS4210_NCPUS];
+     Exynos4210Irq irqs;
+-    qemu_irq *irq_table;
++    qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     MemoryRegion chipid_mem;
+     MemoryRegion iram_mem;
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
+ void exynos4210_write_secondary(ARMCPU *cpu,
+         const struct arm_boot_info *info);
+-/* Initialize exynos4210 IRQ subsystem stub */
+-qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
+-
+ /* Initialize board IRQs.
+  * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
+-void exynos4210_init_board_irqs(Exynos4210Irq *s);
++void exynos4210_init_board_irqs(Exynos4210State *s);
+ /* Get IRQ number from exynos4210 IRQ subsystem stub.
+  * To identify IRQ source use internal combiner group and bit number
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
+     }
+-    /*** IRQs ***/
+-
+-    s->irq_table = exynos4210_init_irq(&s->irqs);
+-
+     /* IRQ Gate */
+     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
+         DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
+     /* Initialize board IRQs. */
+-    exynos4210_init_board_irqs(&s->irqs);
++    exynos4210_init_board_irqs(s);
+     /*** Memory ***/
+diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_gic.c
++++ b/hw/intc/exynos4210_gic.c
+@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+ #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
+ #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
+-static void exynos4210_irq_handler(void *opaque, int irq, int level)
+-{
+-    Exynos4210Irq *s = (Exynos4210Irq *)opaque;
+-
+-    /* Bypass */
+-    qemu_set_irq(s->board_irqs[irq], level);
+-}
+-
+-/*
+- * Initialize exynos4210 IRQ subsystem stub.
+- */
+-qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
+-{
+-    return qemu_allocate_irqs(exynos4210_irq_handler, s,
+-            EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
+-}
+-
+ /*
+  * Initialize board IRQs.
+  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
+  */
+-void exynos4210_init_board_irqs(Exynos4210Irq *s)
++void exynos4210_init_board_irqs(Exynos4210State *s)
+ {
+     uint32_t grp, bit, irq_id, n;
++    Exynos4210Irq *is = &s->irqs;
+     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+         irq_id = 0;
+@@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
+             irq_id = EXT_GIC_ID_MCT_G1;
+         }
+         if (irq_id) {
+-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
+-                    s->ext_gic_irq[irq_id-32]);
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_gic_irq[irq_id - 32]);
+         } else {
+-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
+-                    s->ext_combiner_irq[n]);
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_combiner_irq[n]);
+         }
+     }
+     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
+@@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
+                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
+         if (irq_id) {
+-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
+-                    s->ext_gic_irq[irq_id-32]);
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_gic_irq[irq_id - 32]);
+         }
+     }
+ }
+--
+.25.1

-[PULL 10/11] aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
+[PULL 13/31] hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
-From: Guenter Roeck <linux@roeck-us.net>
+Fix a missing set of spaces around '-' in the definition of
 combiner_grp_to_gic_id[]. We're about to move this code, so
 fix the style issue first to keep checkpatch happy with the
 code-motion patch.
-The Linux kernel recently started using FAST_READ_4 commands.
-This results in flash read failures. At the same time, the m25p80
-emulation is seen to read 8 more bytes than expected. Adjusting the
-expected number of dummy cycles to match FAST_READ fixes the problem.
-Fixes: f95c4bffdc4c ("aspeed/smc: snoop SPI transfers to fake dummy cycles")
-Reviewed-by: Cédric Le Goater <clg@kaod.org>
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-7-peter.maydell@linaro.org
 ---
- hw/ssi/aspeed_smc.c | 2 +-
+ hw/intc/exynos4210_gic.c | 2 +-
 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
+diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/aspeed_smc.c
+--- a/hw/intc/exynos4210_gic.c
-+++ b/hw/ssi/aspeed_smc.c
++++ b/hw/intc/exynos4210_gic.c
-@@ -XXX,XX +XXX,XX @@ static int aspeed_smc_num_dummies(uint8_t command)
+@@ -XXX,XX +XXX,XX @@ enum ExtInt {
-     case FAST_READ:
+  */
-     case DOR:
-     case QOR:
+ static const uint32_t
-+    case FAST_READ_4:
+-combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
-     case DOR_4:
++combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
-     case QOR_4:
+     /* int combiner groups 16-19 */
-         return 1;
+     { }, { }, { }, { },
-     case DIOR:
+     /* int combiner group 20 */
 -    case FAST_READ_4:
      case DIOR_4:
          return 2;
      case QIOR:
 --
-.20.1
+.25.1

-New patch
+[PULL 14/31] hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
+The function exynos4210_init_board_irqs() currently lives in
+exynos4210_gic.c, but it isn't really part of the exynos4210.gic
+device -- it is a function that implements (some of) the wiring up of
+interrupts between the SoC's GIC and combiner components.  This means
+it fits better in exynos4210.c, which is the SoC-level code.  Move it
+there. Similarly, exynos4210_git_irq() is used almost only in the
+SoC-level code, so move it too.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-8-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |   4 -
+ hw/arm/exynos4210.c         | 202 +++++++++++++++++++++++++++++++++++
+ hw/intc/exynos4210_gic.c    | 204 ------------------------------------
+files changed, 202 insertions(+), 208 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
+ void exynos4210_write_secondary(ARMCPU *cpu,
+         const struct arm_boot_info *info);
+-/* Initialize board IRQs.
+- * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
+-void exynos4210_init_board_irqs(Exynos4210State *s);
+-
+ /* Get IRQ number from exynos4210 IRQ subsystem stub.
+  * To identify IRQ source use internal combiner group and bit number
+  *  grp - group number
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@
+ #define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
+ #define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
++enum ExtGicId {
++    EXT_GIC_ID_MDMA_LCD0 = 66,
++    EXT_GIC_ID_PDMA0,
++    EXT_GIC_ID_PDMA1,
++    EXT_GIC_ID_TIMER0,
++    EXT_GIC_ID_TIMER1,
++    EXT_GIC_ID_TIMER2,
++    EXT_GIC_ID_TIMER3,
++    EXT_GIC_ID_TIMER4,
++    EXT_GIC_ID_MCT_L0,
++    EXT_GIC_ID_WDT,
++    EXT_GIC_ID_RTC_ALARM,
++    EXT_GIC_ID_RTC_TIC,
++    EXT_GIC_ID_GPIO_XB,
++    EXT_GIC_ID_GPIO_XA,
++    EXT_GIC_ID_MCT_L1,
++    EXT_GIC_ID_IEM_APC,
++    EXT_GIC_ID_IEM_IEC,
++    EXT_GIC_ID_NFC,
++    EXT_GIC_ID_UART0,
++    EXT_GIC_ID_UART1,
++    EXT_GIC_ID_UART2,
++    EXT_GIC_ID_UART3,
++    EXT_GIC_ID_UART4,
++    EXT_GIC_ID_MCT_G0,
++    EXT_GIC_ID_I2C0,
++    EXT_GIC_ID_I2C1,
++    EXT_GIC_ID_I2C2,
++    EXT_GIC_ID_I2C3,
++    EXT_GIC_ID_I2C4,
++    EXT_GIC_ID_I2C5,
++    EXT_GIC_ID_I2C6,
++    EXT_GIC_ID_I2C7,
++    EXT_GIC_ID_SPI0,
++    EXT_GIC_ID_SPI1,
++    EXT_GIC_ID_SPI2,
++    EXT_GIC_ID_MCT_G1,
++    EXT_GIC_ID_USB_HOST,
++    EXT_GIC_ID_USB_DEVICE,
++    EXT_GIC_ID_MODEMIF,
++    EXT_GIC_ID_HSMMC0,
++    EXT_GIC_ID_HSMMC1,
++    EXT_GIC_ID_HSMMC2,
++    EXT_GIC_ID_HSMMC3,
++    EXT_GIC_ID_SDMMC,
++    EXT_GIC_ID_MIPI_CSI_4LANE,
++    EXT_GIC_ID_MIPI_DSI_4LANE,
++    EXT_GIC_ID_MIPI_CSI_2LANE,
++    EXT_GIC_ID_MIPI_DSI_2LANE,
++    EXT_GIC_ID_ONENAND_AUDI,
++    EXT_GIC_ID_ROTATOR,
++    EXT_GIC_ID_FIMC0,
++    EXT_GIC_ID_FIMC1,
++    EXT_GIC_ID_FIMC2,
++    EXT_GIC_ID_FIMC3,
++    EXT_GIC_ID_JPEG,
++    EXT_GIC_ID_2D,
++    EXT_GIC_ID_PCIe,
++    EXT_GIC_ID_MIXER,
++    EXT_GIC_ID_HDMI,
++    EXT_GIC_ID_HDMI_I2C,
++    EXT_GIC_ID_MFC,
++    EXT_GIC_ID_TVENC,
++};
++
++enum ExtInt {
++    EXT_GIC_ID_EXTINT0 = 48,
++    EXT_GIC_ID_EXTINT1,
++    EXT_GIC_ID_EXTINT2,
++    EXT_GIC_ID_EXTINT3,
++    EXT_GIC_ID_EXTINT4,
++    EXT_GIC_ID_EXTINT5,
++    EXT_GIC_ID_EXTINT6,
++    EXT_GIC_ID_EXTINT7,
++    EXT_GIC_ID_EXTINT8,
++    EXT_GIC_ID_EXTINT9,
++    EXT_GIC_ID_EXTINT10,
++    EXT_GIC_ID_EXTINT11,
++    EXT_GIC_ID_EXTINT12,
++    EXT_GIC_ID_EXTINT13,
++    EXT_GIC_ID_EXTINT14,
++    EXT_GIC_ID_EXTINT15
++};
++
++/*
++ * External GIC sources which are not from External Interrupt Combiner or
++ * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
++ * which is INTG16 in Internal Interrupt Combiner.
++ */
++
++static const uint32_t
++combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
++    /* int combiner groups 16-19 */
++    { }, { }, { }, { },
++    /* int combiner group 20 */
++    { 0, EXT_GIC_ID_MDMA_LCD0 },
++    /* int combiner group 21 */
++    { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
++    /* int combiner group 22 */
++    { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
++            EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
++    /* int combiner group 23 */
++    { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
++    /* int combiner group 24 */
++    { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
++    /* int combiner group 25 */
++    { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
++    /* int combiner group 26 */
++    { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
++            EXT_GIC_ID_UART4 },
++    /* int combiner group 27 */
++    { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
++            EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
++            EXT_GIC_ID_I2C7 },
++    /* int combiner group 28 */
++    { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
++    /* int combiner group 29 */
++    { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
++     EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
++    /* int combiner group 30 */
++    { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
++    /* int combiner group 31 */
++    { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
++    /* int combiner group 32 */
++    { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
++    /* int combiner group 33 */
++    { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
++    /* int combiner group 34 */
++    { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
++    /* int combiner group 35 */
++    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    /* int combiner group 36 */
++    { EXT_GIC_ID_MIXER },
++    /* int combiner group 37 */
++    { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
++     EXT_GIC_ID_EXTINT7 },
++    /* groups 38-50 */
++    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
++    /* int combiner group 51 */
++    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    /* group 52 */
++    { },
++    /* int combiner group 53 */
++    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    /* groups 54-63 */
++    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
++};
++
++/*
++ * Initialize board IRQs.
++ * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
++ */
++static void exynos4210_init_board_irqs(Exynos4210State *s)
++{
++    uint32_t grp, bit, irq_id, n;
++    Exynos4210Irq *is = &s->irqs;
++
++    for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
++        irq_id = 0;
++        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
++                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
++            /* MCT_G0 is passed to External GIC */
++            irq_id = EXT_GIC_ID_MCT_G0;
++        }
++        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
++                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
++            /* MCT_G1 is passed to External and GIC */
++            irq_id = EXT_GIC_ID_MCT_G1;
++        }
++        if (irq_id) {
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_gic_irq[irq_id - 32]);
++        } else {
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_combiner_irq[n]);
++        }
++    }
++    for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
++        /* these IDs are passed to Internal Combiner and External GIC */
++        grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
++        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
++        irq_id = combiner_grp_to_gic_id[grp -
++                     EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
++
++        if (irq_id) {
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_gic_irq[irq_id - 32]);
++        }
++    }
++}
++
++/*
++ * Get IRQ number from exynos4210 IRQ subsystem stub.
++ * To identify IRQ source use internal combiner group and bit number
++ *  grp - group number
++ *  bit - bit number inside group
++ */
++uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
++{
++    return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
++}
++
+ static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
+x09, 0x00, 0x00, 0x00 };
+diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_gic.c
++++ b/hw/intc/exynos4210_gic.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/arm/exynos4210.h"
+ #include "qom/object.h"
+-enum ExtGicId {
+-    EXT_GIC_ID_MDMA_LCD0 = 66,
+-    EXT_GIC_ID_PDMA0,
+-    EXT_GIC_ID_PDMA1,
+-    EXT_GIC_ID_TIMER0,
+-    EXT_GIC_ID_TIMER1,
+-    EXT_GIC_ID_TIMER2,
+-    EXT_GIC_ID_TIMER3,
+-    EXT_GIC_ID_TIMER4,
+-    EXT_GIC_ID_MCT_L0,
+-    EXT_GIC_ID_WDT,
+-    EXT_GIC_ID_RTC_ALARM,
+-    EXT_GIC_ID_RTC_TIC,
+-    EXT_GIC_ID_GPIO_XB,
+-    EXT_GIC_ID_GPIO_XA,
+-    EXT_GIC_ID_MCT_L1,
+-    EXT_GIC_ID_IEM_APC,
+-    EXT_GIC_ID_IEM_IEC,
+-    EXT_GIC_ID_NFC,
+-    EXT_GIC_ID_UART0,
+-    EXT_GIC_ID_UART1,
+-    EXT_GIC_ID_UART2,
+-    EXT_GIC_ID_UART3,
+-    EXT_GIC_ID_UART4,
+-    EXT_GIC_ID_MCT_G0,
+-    EXT_GIC_ID_I2C0,
+-    EXT_GIC_ID_I2C1,
+-    EXT_GIC_ID_I2C2,
+-    EXT_GIC_ID_I2C3,
+-    EXT_GIC_ID_I2C4,
+-    EXT_GIC_ID_I2C5,
+-    EXT_GIC_ID_I2C6,
+-    EXT_GIC_ID_I2C7,
+-    EXT_GIC_ID_SPI0,
+-    EXT_GIC_ID_SPI1,
+-    EXT_GIC_ID_SPI2,
+-    EXT_GIC_ID_MCT_G1,
+-    EXT_GIC_ID_USB_HOST,
+-    EXT_GIC_ID_USB_DEVICE,
+-    EXT_GIC_ID_MODEMIF,
+-    EXT_GIC_ID_HSMMC0,
+-    EXT_GIC_ID_HSMMC1,
+-    EXT_GIC_ID_HSMMC2,
+-    EXT_GIC_ID_HSMMC3,
+-    EXT_GIC_ID_SDMMC,
+-    EXT_GIC_ID_MIPI_CSI_4LANE,
+-    EXT_GIC_ID_MIPI_DSI_4LANE,
+-    EXT_GIC_ID_MIPI_CSI_2LANE,
+-    EXT_GIC_ID_MIPI_DSI_2LANE,
+-    EXT_GIC_ID_ONENAND_AUDI,
+-    EXT_GIC_ID_ROTATOR,
+-    EXT_GIC_ID_FIMC0,
+-    EXT_GIC_ID_FIMC1,
+-    EXT_GIC_ID_FIMC2,
+-    EXT_GIC_ID_FIMC3,
+-    EXT_GIC_ID_JPEG,
+-    EXT_GIC_ID_2D,
+-    EXT_GIC_ID_PCIe,
+-    EXT_GIC_ID_MIXER,
+-    EXT_GIC_ID_HDMI,
+-    EXT_GIC_ID_HDMI_I2C,
+-    EXT_GIC_ID_MFC,
+-    EXT_GIC_ID_TVENC,
+-};
+-
+-enum ExtInt {
+-    EXT_GIC_ID_EXTINT0 = 48,
+-    EXT_GIC_ID_EXTINT1,
+-    EXT_GIC_ID_EXTINT2,
+-    EXT_GIC_ID_EXTINT3,
+-    EXT_GIC_ID_EXTINT4,
+-    EXT_GIC_ID_EXTINT5,
+-    EXT_GIC_ID_EXTINT6,
+-    EXT_GIC_ID_EXTINT7,
+-    EXT_GIC_ID_EXTINT8,
+-    EXT_GIC_ID_EXTINT9,
+-    EXT_GIC_ID_EXTINT10,
+-    EXT_GIC_ID_EXTINT11,
+-    EXT_GIC_ID_EXTINT12,
+-    EXT_GIC_ID_EXTINT13,
+-    EXT_GIC_ID_EXTINT14,
+-    EXT_GIC_ID_EXTINT15
+-};
+-
+-/*
+- * External GIC sources which are not from External Interrupt Combiner or
+- * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
+- * which is INTG16 in Internal Interrupt Combiner.
+- */
+-
+-static const uint32_t
+-combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+-    /* int combiner groups 16-19 */
+-    { }, { }, { }, { },
+-    /* int combiner group 20 */
+-    { 0, EXT_GIC_ID_MDMA_LCD0 },
+-    /* int combiner group 21 */
+-    { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
+-    /* int combiner group 22 */
+-    { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
+-            EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
+-    /* int combiner group 23 */
+-    { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
+-    /* int combiner group 24 */
+-    { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
+-    /* int combiner group 25 */
+-    { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
+-    /* int combiner group 26 */
+-    { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
+-            EXT_GIC_ID_UART4 },
+-    /* int combiner group 27 */
+-    { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
+-            EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
+-            EXT_GIC_ID_I2C7 },
+-    /* int combiner group 28 */
+-    { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
+-    /* int combiner group 29 */
+-    { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
+-     EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
+-    /* int combiner group 30 */
+-    { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
+-    /* int combiner group 31 */
+-    { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
+-    /* int combiner group 32 */
+-    { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
+-    /* int combiner group 33 */
+-    { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
+-    /* int combiner group 34 */
+-    { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
+-    /* int combiner group 35 */
+-    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+-    /* int combiner group 36 */
+-    { EXT_GIC_ID_MIXER },
+-    /* int combiner group 37 */
+-    { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
+-     EXT_GIC_ID_EXTINT7 },
+-    /* groups 38-50 */
+-    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
+-    /* int combiner group 51 */
+-    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+-    /* group 52 */
+-    { },
+-    /* int combiner group 53 */
+-    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+-    /* groups 54-63 */
+-    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
+-};
+-
+ #define EXYNOS4210_GIC_NIRQ 160
+ #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE     0x10000
+@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+ #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
+ #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
+-/*
+- * Initialize board IRQs.
+- * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
+- */
+-void exynos4210_init_board_irqs(Exynos4210State *s)
+-{
+-    uint32_t grp, bit, irq_id, n;
+-    Exynos4210Irq *is = &s->irqs;
+-
+-    for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+-        irq_id = 0;
+-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
+-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
+-            /* MCT_G0 is passed to External GIC */
+-            irq_id = EXT_GIC_ID_MCT_G0;
+-        }
+-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
+-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
+-            /* MCT_G1 is passed to External and GIC */
+-            irq_id = EXT_GIC_ID_MCT_G1;
+-        }
+-        if (irq_id) {
+-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_gic_irq[irq_id - 32]);
+-        } else {
+-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_combiner_irq[n]);
+-        }
+-    }
+-    for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
+-        /* these IDs are passed to Internal Combiner and External GIC */
+-        grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
+-        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
+-        irq_id = combiner_grp_to_gic_id[grp -
+-                     EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
+-
+-        if (irq_id) {
+-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_gic_irq[irq_id - 32]);
+-        }
+-    }
+-}
+-
+-/*
+- * Get IRQ number from exynos4210 IRQ subsystem stub.
+- * To identify IRQ source use internal combiner group and bit number
+- *  grp - group number
+- *  bit - bit number inside group
+- */
+-uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
+-{
+-    return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
+-}
+-
+-/********* GIC part *********/
+-
+ #define TYPE_EXYNOS4210_GIC "exynos4210.gic"
+ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
+--
+.25.1

-New patch
+[PULL 15/31] hw/arm/exynos4210: Put external GIC into state struct
+Switch the creation of the external GIC to the new-style "embedded in
+state struct" approach, so we can easily refer to the object
+elsewhere during realize.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-9-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h      |  2 ++
+ include/hw/intc/exynos4210_gic.h | 43 ++++++++++++++++++++++++++++++++
+ hw/arm/exynos4210.c              | 10 ++++----
+ hw/intc/exynos4210_gic.c         | 17 ++-----------
+ MAINTAINERS                      |  2 +-
+files changed, 53 insertions(+), 21 deletions(-)
+ create mode 100644 include/hw/intc/exynos4210_gic.h
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/or-irq.h"
+ #include "hw/sysbus.h"
+ #include "hw/cpu/a9mpcore.h"
++#include "hw/intc/exynos4210_gic.h"
+ #include "target/arm/cpu-qom.h"
+ #include "qom/object.h"
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
+     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
+     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+     A9MPPrivState a9mpcore;
++    Exynos4210GicState ext_gic;
+ };
+ #define TYPE_EXYNOS4210_SOC "exynos4210"
+diff --git a/include/hw/intc/exynos4210_gic.h b/include/hw/intc/exynos4210_gic.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/intc/exynos4210_gic.h
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
++ *
++ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
++ * All rights reserved.
++ *
++ * Evgeny Voevodin <e.voevodin@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++#ifndef HW_INTC_EXYNOS4210_GIC_H
++#define HW_INTC_EXYNOS4210_GIC_H
++
++#include "hw/sysbus.h"
++
++#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
++OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
++
++#define EXYNOS4210_GIC_NCPUS 2
++
++struct Exynos4210GicState {
++    SysBusDevice parent_obj;
++
++    MemoryRegion cpu_container;
++    MemoryRegion dist_container;
++    MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS];
++    MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS];
++    uint32_t num_cpu;
++    DeviceState *gic;
++};
++
++#endif
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
+     /* External GIC */
+-    dev = qdev_new("exynos4210.gic");
+-    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
+-    busdev = SYS_BUS_DEVICE(dev);
+-    sysbus_realize_and_unref(busdev, &error_fatal);
++    qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
++    busdev = SYS_BUS_DEVICE(&s->ext_gic);
++    sysbus_realize(busdev, &error_fatal);
+     /* Map CPU interface */
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
+     /* Map Distributer interface */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
+     }
+     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
+-        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
++        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
+     }
+     /* Internal Interrupt Combiner */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
+     }
+     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
++    object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
+ }
+ static void exynos4210_class_init(ObjectClass *klass, void *data)
+diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_gic.c
++++ b/hw/intc/exynos4210_gic.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/module.h"
+ #include "hw/irq.h"
+ #include "hw/qdev-properties.h"
++#include "hw/intc/exynos4210_gic.h"
+ #include "hw/arm/exynos4210.h"
+ #include "qom/object.h"
+@@ -XXX,XX +XXX,XX @@
+ #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
+ #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
+-#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
+-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
+-
+-struct Exynos4210GicState {
+-    SysBusDevice parent_obj;
+-
+-    MemoryRegion cpu_container;
+-    MemoryRegion dist_container;
+-    MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
+-    MemoryRegion dist_alias[EXYNOS4210_NCPUS];
+-    uint32_t num_cpu;
+-    DeviceState *gic;
+-};
+-
+ static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
+ {
+     Exynos4210GicState *s = (Exynos4210GicState *)opaque;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp)
+      * enough room for the cpu numbers.  gcc 9.2.1 on 32-bit x86
+      * doesn't figure this out, otherwise and gives spurious warnings.
+      */
+-    assert(n <= EXYNOS4210_NCPUS);
++    assert(n <= EXYNOS4210_GIC_NCPUS);
+     for (i = 0; i < n; i++) {
+         /* Map CPU interface per SMP Core */
+         sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+ S: Odd Fixes
+ F: hw/*/exynos*
+-F: include/hw/arm/exynos4210.h
++F: include/hw/*/exynos*
+ Calxeda Highbank
+ M: Rob Herring <robh@kernel.org>
+--
+.25.1

-New patch
+[PULL 16/31] hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
+The only time we use the ext_gic_irq[] array in the Exynos4210Irq
+struct is during realize of the SoC -- we initialize it with the
+input IRQs of the external GIC device, and then connect those to
+outputs of other devices further on in realize (including in the
+exynos4210_init_board_irqs() function).  Now that the ext_gic object
+is easily accessible as s->ext_gic we can make the connections
+directly from one device to the other without going via this array.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-10-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  1 -
+ hw/arm/exynos4210.c         | 12 ++++++------
+files changed, 6 insertions(+), 7 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ typedef struct Exynos4210Irq {
+     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
+-    qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
+ } Exynos4210Irq;
+ struct Exynos4210State {
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+ {
+     uint32_t grp, bit, irq_id, n;
+     Exynos4210Irq *is = &s->irqs;
++    DeviceState *extgicdev = DEVICE(&s->ext_gic);
+     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+         irq_id = 0;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+         }
+         if (irq_id) {
+             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_gic_irq[irq_id - 32]);
++                                             qdev_get_gpio_in(extgicdev,
++                                                              irq_id - 32));
+         } else {
+             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                     is->ext_combiner_irq[n]);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+         if (irq_id) {
+             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_gic_irq[irq_id - 32]);
++                                             qdev_get_gpio_in(extgicdev,
++                                                              irq_id - 32));
+         }
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+         sysbus_connect_irq(busdev, n,
+                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
+     }
+-    for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
+-        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
+-    }
+     /* Internal Interrupt Combiner */
+     dev = qdev_new("exynos4210.combiner");
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     busdev = SYS_BUS_DEVICE(dev);
+     sysbus_realize_and_unref(busdev, &error_fatal);
+     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+-        sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
++        sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
+     }
+     exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
+--
+.25.1

-New patch
+[PULL 17/31] hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c
+The function exynos4210_combiner_get_gpioin() currently lives in
+exynos4210_combiner.c, but it isn't really part of the combiner
+device itself -- it is a function that implements the wiring up of
+some interrupt sources to multiple combiner inputs.  Move it to live
+with the other SoC-level code in exynos4210.c, along with a few
+macros previously defined in exynos4210.h which are now used only
+in exynos4210.c.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-11-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h   | 11 -----
+ hw/arm/exynos4210.c           | 82 +++++++++++++++++++++++++++++++++++
+ hw/intc/exynos4210_combiner.c | 77 --------------------------------
+files changed, 82 insertions(+), 88 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ   \
+     (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
+-#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit)  ((grp)*8 + (bit))
+-#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq)       ((irq) / 8)
+-#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
+-    ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
+-
+ /* IRQs number for external and internal GIC */
+ #define EXYNOS4210_EXT_GIC_NIRQ     (160-32)
+ #define EXYNOS4210_INT_GIC_NIRQ     64
+@@ -XXX,XX +XXX,XX @@ void exynos4210_write_secondary(ARMCPU *cpu,
+  *  bit - bit number inside group */
+ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
+-/*
+- * Get Combiner input GPIO into irqs structure
+- */
+-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
+-        int ext);
+-
+ /*
+  * exynos4210 UART
+  */
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
+ };
++#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit)  ((grp) * 8 + (bit))
++#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq)       ((irq) / 8)
++#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
++    ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
++
+ /*
+  * Initialize board IRQs.
+  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
+@@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
+     return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
+ }
++/*
++ * Get Combiner input GPIO into irqs structure
++ */
++static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
++                                           DeviceState *dev, int ext)
++{
++    int n;
++    int bit;
++    int max;
++    qemu_irq *irq;
++
++    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
++        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
++    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
++
++    /*
++     * Some IRQs of Int/External Combiner are going to two Combiners groups,
++     * so let split them.
++     */
++    for (n = 0; n < max; n++) {
++
++        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
++
++        switch (n) {
++        /* MDNIE_LCD1 INTG1 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
++            continue;
++
++        /* TMU INTG3 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
++            continue;
++
++        /* LCD1 INTG12 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
++            continue;
++
++        /* Multi-Core Timer INTG12 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
++               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
++            continue;
++
++        /* Multi-Core Timer INTG35 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
++            continue;
++
++        /* Multi-Core Timer INTG51 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
++            continue;
++
++        /* Multi-Core Timer INTG53 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
++            continue;
++        }
++
++        irq[n] = qdev_get_gpio_in(dev, n);
++    }
++}
++
+ static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
+x09, 0x00, 0x00, 0x00 };
+diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_combiner.c
++++ b/hw/intc/exynos4210_combiner.c
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_combiner = {
+     }
+ };
+-/*
+- * Get Combiner input GPIO into irqs structure
+- */
+-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
+-        int ext)
+-{
+-    int n;
+-    int bit;
+-    int max;
+-    qemu_irq *irq;
+-
+-    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
+-        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
+-    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
+-
+-    /*
+-     * Some IRQs of Int/External Combiner are going to two Combiners groups,
+-     * so let split them.
+-     */
+-    for (n = 0; n < max; n++) {
+-
+-        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
+-
+-        switch (n) {
+-        /* MDNIE_LCD1 INTG1 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
+-            continue;
+-
+-        /* TMU INTG3 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
+-            continue;
+-
+-        /* LCD1 INTG12 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
+-            continue;
+-
+-        /* Multi-Core Timer INTG12 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
+-               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+-            continue;
+-
+-        /* Multi-Core Timer INTG35 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+-            continue;
+-
+-        /* Multi-Core Timer INTG51 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+-            continue;
+-
+-        /* Multi-Core Timer INTG53 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+-            continue;
+-        }
+-
+-        irq[n] = qdev_get_gpio_in(dev, n);
+-    }
+-}
+-
+ static uint64_t
+ exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
+ {
+--
+.25.1

-New patch
+[PULL 18/31] hw/arm/exynos4210: Delete unused macro definitions
+Delete a couple of #defines which are never used.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-12-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h | 4 ----
+file changed, 4 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ   \
+     (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
+-/* IRQs number for external and internal GIC */
+-#define EXYNOS4210_EXT_GIC_NIRQ     (160-32)
+-#define EXYNOS4210_INT_GIC_NIRQ     64
+-
+ #define EXYNOS4210_I2C_NUMBER               9
+ #define EXYNOS4210_NUM_DMA      3
+--
+.25.1

-[PULL 05/11] hw/arm/fsl-imx6: Wire up USB controllers
+[PULL 19/31] hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
-From: Guenter Roeck <linux@roeck-us.net>
+In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device
 instead of qemu_irq_split().
-With this patch, the USB controllers on 'sabrelite' are detected
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-and can be used to boot the system.
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220404154658.565020-13-peter.maydell@linaro.org
 ---
  include/hw/arm/exynos4210.h |  9 ++++++++
  hw/arm/exynos4210.c         | 41 +++++++++++++++++++++++++++++--------
 files changed, 42 insertions(+), 8 deletions(-)
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
 Message-id: 20200313014551.12554-6-linux@roeck-us.net
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/fsl-imx6.h |  6 ++++++
  hw/arm/fsl-imx6.c         | 36 ++++++++++++++++++++++++++++++++++++
 files changed, 42 insertions(+)
 diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx6.h
+--- a/include/hw/arm/exynos4210.h
-+++ b/include/hw/arm/fsl-imx6.h
++++ b/include/hw/arm/exynos4210.h
 @@ -XXX,XX +XXX,XX @@
- #include "hw/sd/sdhci.h"
+ #include "hw/sysbus.h"
- #include "hw/ssi/imx_spi.h"
+ #include "hw/cpu/a9mpcore.h"
- #include "hw/net/imx_fec.h"
+ #include "hw/intc/exynos4210_gic.h"
-+#include "hw/usb/chipidea.h"
++#include "hw/core/split-irq.h"
-+#include "hw/usb/imx-usb-phy.h"
+ #include "target/arm/cpu-qom.h"
- #include "exec/memory.h"
+ #include "qom/object.h"
  #include "cpu.h"
 @@ -XXX,XX +XXX,XX @@
- #define FSL_IMX6_NUM_ESDHCS 4
- #define FSL_IMX6_NUM_ECSPIS 5
+ #define EXYNOS4210_NUM_DMA      3
- #define FSL_IMX6_NUM_WDTS 2
-+#define FSL_IMX6_NUM_USB_PHYS 2
++/*
-+#define FSL_IMX6_NUM_USBS 4
++ * We need one splitter for every external combiner input, plus
++ * one for every non-zero entry in combiner_grp_to_gic_id[].
- typedef struct FslIMX6State {
++ * We'll assert in exynos4210_init_board_irqs() if this is wrong.
-     /*< private >*/
++ */
-@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
++#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
-     SDHCIState     esdhc[FSL_IMX6_NUM_ESDHCS];
++
-     IMXSPIState    spi[FSL_IMX6_NUM_ECSPIS];
+ typedef struct Exynos4210Irq {
-     IMX2WdtState   wdt[FSL_IMX6_NUM_WDTS];
+     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
-+    IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
+     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
-+    ChipideaState  usb[FSL_IMX6_NUM_USBS];
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
-     IMXFECState    eth;
+     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
-     MemoryRegion   rom;
+     A9MPPrivState a9mpcore;
-     MemoryRegion   caam;
+     Exynos4210GicState ext_gic;
-diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
++    SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
  };
  #define TYPE_EXYNOS4210_SOC "exynos4210"
 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/fsl-imx6.c
+--- a/hw/arm/exynos4210.c
-+++ b/hw/arm/fsl-imx6.c
++++ b/hw/arm/exynos4210.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
- #include "qemu/osdep.h"
+     uint32_t grp, bit, irq_id, n;
- #include "qapi/error.h"
+     Exynos4210Irq *is = &s->irqs;
- #include "hw/arm/fsl-imx6.h"
+     DeviceState *extgicdev = DEVICE(&s->ext_gic);
-+#include "hw/usb/imx-usb-phy.h"
++    int splitcount = 0;
- #include "hw/boards.h"
++    DeviceState *splitter;
- #include "hw/qdev-properties.h"
- #include "sysemu/sysemu.h"
+     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
-@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
+         irq_id = 0;
-                               TYPE_IMX_USDHC);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
              /* MCT_G1 is passed to External and GIC */
              irq_id = EXT_GIC_ID_MCT_G1;
          }
 +
 +        assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
 +        splitter = DEVICE(&s->splitter[splitcount]);
 +        qdev_prop_set_uint16(splitter, "num-lines", 2);
 +        qdev_realize(splitter, NULL, &error_abort);
 +        splitcount++;
 +        s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
 +        qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
          if (irq_id) {
 -            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
 -                                             qdev_get_gpio_in(extgicdev,
 -                                                              irq_id - 32));
 +            qdev_connect_gpio_out(splitter, 1,
 +                                  qdev_get_gpio_in(extgicdev, irq_id - 32));
          } else {
 -            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
 -                    is->ext_combiner_irq[n]);
 +            qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
          }
      }
+     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
-+    for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
-+        snprintf(name, NAME_SIZE, "usbphy%d", i);
+                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
-+        sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
-+                              TYPE_IMX_USBPHY);
+         if (irq_id) {
-+    }
+-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-+    for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
+-                                             qdev_get_gpio_in(extgicdev,
-+        snprintf(name, NAME_SIZE, "usb%d", i);
+-                                                              irq_id - 32));
-+        sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
++            assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
-+                              TYPE_CHIPIDEA);
++            splitter = DEVICE(&s->splitter[splitcount]);
 +            qdev_prop_set_uint16(splitter, "num-lines", 2);
 +            qdev_realize(splitter, NULL, &error_abort);
 +            splitcount++;
 +            s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
 +            qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
 +            qdev_connect_gpio_out(splitter, 1,
 +                                  qdev_get_gpio_in(extgicdev, irq_id - 32));
          }
      }
 +    /*
 +     * We check this here to avoid a more obscure assert later when
 +     * qdev_assert_realized_properly() checks that we realized every
 +     * child object we initialized.
 +     */
 +    assert(splitcount == EXYNOS4210_NUM_SPLITTERS);
  }
  /*
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
          object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
      }
 +    for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
 +        g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
 +        object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ);
 +    }
 +
-     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
+     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
-         snprintf(name, NAME_SIZE, "spi%d", i + 1);
+     object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
-         sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
+ }
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
                                              esdhc_table[i].irq));
      }
 +    /* USB */
 +    for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
 +        object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
 +                                 &error_abort);
 +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
 +                        FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
 +    }
 +    for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
 +        static const int FSL_IMX6_USBn_IRQ[] = {
 +            FSL_IMX6_USB_OTG_IRQ,
 +            FSL_IMX6_USB_HOST1_IRQ,
 +            FSL_IMX6_USB_HOST2_IRQ,
 +            FSL_IMX6_USB_HOST3_IRQ,
 +        };
 +
 +        object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
 +                                 &error_abort);
 +        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
 +                        FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
 +        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
 +                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
 +                                            FSL_IMX6_USBn_IRQ[i]));
 +    }
 +
      /* Initialize all ECSPI */
      for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
          static const struct {
 --
-.20.1
+.25.1

-New patch
+[PULL 20/31] hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines
+In exynos4210_init_board_irqs(), the loop that handles IRQ lines that
+are in a range that applies to the internal combiner only creates a
+splitter for those interrupts which go to both the internal combiner
+and to the external GIC, but it does nothing at all for the
+interrupts which don't go to the external GIC, leaving the
+irq_table[] array element empty for those.  (This will result in
+those interrupts simply being lost, not in a QEMU crash.)
+I don't have a reliable datasheet for this SoC, but since we do wire
+up one interrupt line in this category (the HDMI I2C device on
+interrupt 16,1), this seems like it must be a bug in the existing
+QEMU code.  Fill in the irq_table[] entries where we're not splitting
+the IRQ to both the internal combiner and the external GIC with the
+IRQ line of the internal combiner.  (That is, these IRQ lines go to
+just one device, not multiple.)
+This bug didn't have any visible guest effects because the only
+implemented device that was affected was the HDMI I2C controller,
+and we never connect any I2C devices to that bus.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-14-peter.maydell@linaro.org
+---
+ hw/arm/exynos4210.c | 2 ++
+file changed, 2 insertions(+)
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+             qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
+             qdev_connect_gpio_out(splitter, 1,
+                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
++        } else {
++            s->irq_table[n] = is->int_combiner_irq[n];
+         }
+     }
+     /*
+--
+.25.1

-New patch
+[PULL 21/31] hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
+Currently for the interrupts MCT_G0 and MCT_G1 which are
+the only ones in the input range of the external combiner
+and which are also wired to the external GIC, we connect
+them only to the internal combiner and the external GIC.
+This seems likely to be a bug, as all other interrupts
+which are in the input range of both combiners are
+connected to both combiners. (The fact that the code in
+exynos4210_combiner_get_gpioin() is also trying to wire
+up these inputs on both combiners also suggests this.)
+Wire these interrupts up to both combiners, like the rest.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-15-peter.maydell@linaro.org
+---
+ hw/arm/exynos4210.c | 7 +++----
+file changed, 3 insertions(+), 4 deletions(-)
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+         assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
+         splitter = DEVICE(&s->splitter[splitcount]);
+-        qdev_prop_set_uint16(splitter, "num-lines", 2);
++        qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2);
+         qdev_realize(splitter, NULL, &error_abort);
+         splitcount++;
+         s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
+         qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
++        qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
+         if (irq_id) {
+-            qdev_connect_gpio_out(splitter, 1,
++            qdev_connect_gpio_out(splitter, 2,
+                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
+-        } else {
+-            qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
+         }
+     }
+     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
+--
+.25.1

-New patch
+[PULL 22/31] hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
+The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0
+and EXT_GIC_ID_MCT_G1 multiple times. This means that we will
+connect multiple IRQs up to the same external GIC input, which
+is not permitted. We do the same thing in the code in
+exynos4210_init_board_irqs() because the conditionals selecting
+an irq_id in the first loop match multiple interrupt IDs.
+Overall we do this for interrupt IDs
+(1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0
+and
+(1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1
+These correspond to the cases for the multi-core timer that we are
+wiring up to multiple inputs on the combiner in
+exynos4210_combiner_get_gpioin().  That code already deals with all
+these interrupt IDs being the same input source, so we don't need to
+connect the external GIC interrupt for any of them except the first
+(1, 4) and (1, 5). Remove the array entries and conditionals which
+were incorrectly causing us to wire up extra lines.
+This bug didn't cause any visible effects, because we only connect
+up a device to the "primary" ID values (1, 4) and (1, 5), so the
+extra lines would never be set to a level.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-16-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  2 +-
+ hw/arm/exynos4210.c         | 12 +++++-------
+files changed, 6 insertions(+), 8 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+  * one for every non-zero entry in combiner_grp_to_gic_id[].
+  * We'll assert in exynos4210_init_board_irqs() if this is wrong.
+  */
+-#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
++#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
+ typedef struct Exynos4210Irq {
+     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+     /* int combiner group 34 */
+     { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
+     /* int combiner group 35 */
+-    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    { 0, 0, 0, EXT_GIC_ID_MCT_L1 },
+     /* int combiner group 36 */
+     { EXT_GIC_ID_MIXER },
+     /* int combiner group 37 */
+@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+     /* groups 38-50 */
+     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
+     /* int combiner group 51 */
+-    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    { EXT_GIC_ID_MCT_L0 },
+     /* group 52 */
+     { },
+     /* int combiner group 53 */
+-    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    { EXT_GIC_ID_WDT },
+     /* groups 54-63 */
+     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
+ };
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+         irq_id = 0;
+-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
+-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
++        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) {
+             /* MCT_G0 is passed to External GIC */
+             irq_id = EXT_GIC_ID_MCT_G0;
+         }
+-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
+-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
++        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) {
+             /* MCT_G1 is passed to External and GIC */
+             irq_id = EXT_GIC_ID_MCT_G1;
+         }
+--
+.25.1

-New patch
+[PULL 23/31] hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
+At this point, the function exynos4210_init_board_irqs() splits input
 IRQ lines to connect them to the input combiner, output combiner and
 external GIC.  The function exynos4210_combiner_get_gpioin() splits
 some of the combiner input lines further to connect them to multiple
 different inputs on the combiner.
 Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a
 configurable number of outputs, we can do all this in one place, by
 making exynos4210_init_board_irqs() add extra outputs to the splitter
 device when it must be connected to more than one input on each
 combiner.
 We do this with a new data structure, the combinermap, which is an
 array each of whose elements is a list of the interrupt IDs on the
 combiner which must be tied together.  As we loop through each
 interrupt ID, if we find that it is the first one in one of these
 lists, we configure the splitter device with eonugh extra outputs and
 wire them up to the other interrupt IDs in the list.
 Conveniently, for all the cases where this is necessary, the
 lowest-numbered interrupt ID in each group is in the range of the
 external combiner, so we only need to code for this in the first of
 the two loops in exynos4210_init_board_irqs().
 The old code in exynos4210_combiner_get_gpioin() which is being
 deleted here had several problems which don't exist in the new code
 in its handling of the multi-core timer interrupts:
  (1) the case labels specified bits 4 ... 8, but bit '8' doesn't
      exist; these should have been 4 ... 7
  (2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]
      multiple times as the input of several different splitters,
      which isn't allowed
  (3) in an apparent cut-and-paste error, the cases for all the
      multi-core timer inputs used "bit + 4" even though the
      bit range for the case was (intended to be) 4 ... 7, which
      meant it was looking at non-existent bits 8 ... 11.
 None of these exist in the new code.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220404154658.565020-17-peter.maydell@linaro.org
 ---
  include/hw/arm/exynos4210.h |   6 +-
  hw/arm/exynos4210.c         | 178 +++++++++++++++++++++++-------------
 files changed, 119 insertions(+), 65 deletions(-)
 diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/exynos4210.h
 +++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
  /*
   * We need one splitter for every external combiner input, plus
 - * one for every non-zero entry in combiner_grp_to_gic_id[].
 + * one for every non-zero entry in combiner_grp_to_gic_id[],
 + * minus one for every external combiner ID in second or later
 + * places in a combinermap[] line.
   * We'll assert in exynos4210_init_board_irqs() if this is wrong.
   */
 -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
 +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
  typedef struct Exynos4210Irq {
      qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/exynos4210.c
 +++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
  #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
      ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
 +/*
 + * Some interrupt lines go to multiple combiner inputs.
 + * This data structure defines those: each array element is
 + * a list of combiner inputs which are connected together;
 + * the one with the smallest interrupt ID value must be first.
 + * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being
 + * wired to anything so we can use 0 as a terminator.
 + */
 +#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B)
 +#define IRQNONE 0
 +
 +#define COMBINERMAP_SIZE 16
 +
 +static const int combinermap[COMBINERMAP_SIZE][6] = {
 +    /* MDNIE_LCD1 */
 +    { IRQNO(0, 4), IRQNO(1, 0), IRQNONE },
 +    { IRQNO(0, 5), IRQNO(1, 1), IRQNONE },
 +    { IRQNO(0, 6), IRQNO(1, 2), IRQNONE },
 +    { IRQNO(0, 7), IRQNO(1, 3), IRQNONE },
 +    /* TMU */
 +    { IRQNO(2, 4), IRQNO(3, 4), IRQNONE },
 +    { IRQNO(2, 5), IRQNO(3, 5), IRQNONE },
 +    { IRQNO(2, 6), IRQNO(3, 6), IRQNONE },
 +    { IRQNO(2, 7), IRQNO(3, 7), IRQNONE },
 +    /* LCD1 */
 +    { IRQNO(11, 4), IRQNO(12, 0), IRQNONE },
 +    { IRQNO(11, 5), IRQNO(12, 1), IRQNONE },
 +    { IRQNO(11, 6), IRQNO(12, 2), IRQNONE },
 +    { IRQNO(11, 7), IRQNO(12, 3), IRQNONE },
 +    /* Multi-core timer */
 +    { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE },
 +    { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE },
 +    { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE },
 +    { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE },
 +};
 +
 +#undef IRQNO
 +
 +static const int *combinermap_entry(int irq)
 +{
 +    /*
 +     * If the interrupt number passed in is the first entry in some
 +     * line of the combinermap, return a pointer to that line;
 +     * otherwise return NULL.
 +     */
 +    int i;
 +    for (i = 0; i < COMBINERMAP_SIZE; i++) {
 +        if (combinermap[i][0] == irq) {
 +            return combinermap[i];
 +        }
 +    }
 +    return NULL;
 +}
 +
 +static int mapline_size(const int *mapline)
 +{
 +    /* Return number of entries in this mapline in total */
 +    int i = 0;
 +
 +    if (!mapline) {
 +        /* Not in the map? IRQ goes to exactly one combiner input */
 +        return 1;
 +    }
 +    while (*mapline != IRQNONE) {
 +        mapline++;
 +        i++;
 +    }
 +    return i;
 +}
 +
  /*
   * Initialize board IRQs.
   * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
      DeviceState *extgicdev = DEVICE(&s->ext_gic);
      int splitcount = 0;
      DeviceState *splitter;
 +    const int *mapline;
 +    int numlines, splitin, in;
      for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
          irq_id = 0;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
              irq_id = EXT_GIC_ID_MCT_G1;
          }
 +        if (s->irq_table[n]) {
 +            /*
 +             * This must be some non-first entry in a combinermap line,
 +             * and we've already filled it in.
 +             */
 +            continue;
 +        }
 +        mapline = combinermap_entry(n);
 +        /*
 +         * We need to connect the IRQ to multiple inputs on both combiners
 +         * and possibly also to the external GIC.
 +         */
 +        numlines = 2 * mapline_size(mapline);
 +        if (irq_id) {
 +            numlines++;
 +        }
          assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
          splitter = DEVICE(&s->splitter[splitcount]);
 -        qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2);
 +        qdev_prop_set_uint16(splitter, "num-lines", numlines);
          qdev_realize(splitter, NULL, &error_abort);
          splitcount++;
 -        s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
 -        qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
 -        qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
 +
 +        in = n;
 +        splitin = 0;
 +        for (;;) {
 +            s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
 +            qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]);
 +            qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]);
 +            splitin += 2;
 +            if (!mapline) {
 +                break;
 +            }
 +            mapline++;
 +            in = *mapline;
 +            if (in == IRQNONE) {
 +                break;
 +            }
 +        }
          if (irq_id) {
 -            qdev_connect_gpio_out(splitter, 2,
 +            qdev_connect_gpio_out(splitter, splitin,
                                    qdev_get_gpio_in(extgicdev, irq_id - 32));
          }
      }
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
          irq_id = combiner_grp_to_gic_id[grp -
                       EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
 +        if (s->irq_table[n]) {
 +            /*
 +             * This must be some non-first entry in a combinermap line,
 +             * and we've already filled it in.
 +             */
 +            continue;
 +        }
 +
          if (irq_id) {
              assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
              splitter = DEVICE(&s->splitter[splitcount]);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
                                             DeviceState *dev, int ext)
  {
      int n;
 -    int bit;
      int max;
      qemu_irq *irq;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
          EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
      irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
 -    /*
 -     * Some IRQs of Int/External Combiner are going to two Combiners groups,
 -     * so let split them.
 -     */
      for (n = 0; n < max; n++) {
 -
 -        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
 -
 -        switch (n) {
 -        /* MDNIE_LCD1 INTG1 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
 -            continue;
 -
 -        /* TMU INTG3 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
 -            continue;
 -
 -        /* LCD1 INTG12 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
 -            continue;
 -
 -        /* Multi-Core Timer INTG12 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
 -               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 -            continue;
 -
 -        /* Multi-Core Timer INTG35 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 -            continue;
 -
 -        /* Multi-Core Timer INTG51 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 -            continue;
 -
 -        /* Multi-Core Timer INTG53 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 -            continue;
 -        }
 -
          irq[n] = qdev_get_gpio_in(dev, n);
      }
  }
 --
 .25.1

-New patch
+[PULL 24/31] hw/arm/exynos4210: Put combiners into state struct
+Switch the creation of the combiner devices to the new-style
+"embedded in state struct" approach, so we can easily refer
+to the object elsewhere during realize.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-18-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h           |  3 ++
+ include/hw/intc/exynos4210_combiner.h | 57 +++++++++++++++++++++++++++
+ hw/arm/exynos4210.c                   | 20 +++++-----
+ hw/intc/exynos4210_combiner.c         | 31 +--------------
+files changed, 72 insertions(+), 39 deletions(-)
+ create mode 100644 include/hw/intc/exynos4210_combiner.h
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "hw/cpu/a9mpcore.h"
+ #include "hw/intc/exynos4210_gic.h"
++#include "hw/intc/exynos4210_combiner.h"
+ #include "hw/core/split-irq.h"
+ #include "target/arm/cpu-qom.h"
+ #include "qom/object.h"
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
+     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+     A9MPPrivState a9mpcore;
+     Exynos4210GicState ext_gic;
++    Exynos4210CombinerState int_combiner;
++    Exynos4210CombinerState ext_combiner;
+     SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
+ };
+diff --git a/include/hw/intc/exynos4210_combiner.h b/include/hw/intc/exynos4210_combiner.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/intc/exynos4210_combiner.h
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Samsung exynos4210 Interrupt Combiner
++ *
++ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
++ * All rights reserved.
++ *
++ * Evgeny Voevodin <e.voevodin@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef HW_INTC_EXYNOS4210_COMBINER
++#define HW_INTC_EXYNOS4210_COMBINER
++
++#include "hw/sysbus.h"
++
++/*
++ * State for each output signal of internal combiner
++ */
++typedef struct CombinerGroupState {
++    uint8_t src_mask;            /* 1 - source enabled, 0 - disabled */
++    uint8_t src_pending;        /* Pending source interrupts before masking */
++} CombinerGroupState;
++
++#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
++OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
++
++/* Number of groups and total number of interrupts for the internal combiner */
++#define IIC_NGRP 64
++#define IIC_NIRQ (IIC_NGRP * 8)
++#define IIC_REGSET_SIZE 0x41
++
++struct Exynos4210CombinerState {
++    SysBusDevice parent_obj;
++
++    MemoryRegion iomem;
++
++    struct CombinerGroupState group[IIC_NGRP];
++    uint32_t reg_set[IIC_REGSET_SIZE];
++    uint32_t icipsr[2];
++    uint32_t external;          /* 1 means that this combiner is external */
++
++    qemu_irq output_irq[IIC_NGRP];
++};
++
++#endif
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     }
+     /* Internal Interrupt Combiner */
+-    dev = qdev_new("exynos4210.combiner");
+-    busdev = SYS_BUS_DEVICE(dev);
+-    sysbus_realize_and_unref(busdev, &error_fatal);
++    busdev = SYS_BUS_DEVICE(&s->int_combiner);
++    sysbus_realize(busdev, &error_fatal);
+     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+         sysbus_connect_irq(busdev, n,
+                            qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
+     }
+-    exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
++    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
+     /* External Interrupt Combiner */
+-    dev = qdev_new("exynos4210.combiner");
+-    qdev_prop_set_uint32(dev, "external", 1);
+-    busdev = SYS_BUS_DEVICE(dev);
+-    sysbus_realize_and_unref(busdev, &error_fatal);
++    qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1);
++    busdev = SYS_BUS_DEVICE(&s->ext_combiner);
++    sysbus_realize(busdev, &error_fatal);
+     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
+     }
+-    exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
++    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
+     /* Initialize board IRQs. */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
+     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
+     object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
++    object_initialize_child(obj, "int-combiner", &s->int_combiner,
++                            TYPE_EXYNOS4210_COMBINER);
++    object_initialize_child(obj, "ext-combiner", &s->ext_combiner,
++                            TYPE_EXYNOS4210_COMBINER);
+ }
+ static void exynos4210_class_init(ObjectClass *klass, void *data)
+diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_combiner.c
++++ b/hw/intc/exynos4210_combiner.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "migration/vmstate.h"
+ #include "qemu/module.h"
+-
++#include "hw/intc/exynos4210_combiner.h"
+ #include "hw/arm/exynos4210.h"
+ #include "hw/hw.h"
+ #include "hw/irq.h"
+@@ -XXX,XX +XXX,XX @@
+ #define DPRINTF(fmt, ...) do {} while (0)
+ #endif
+-#define    IIC_NGRP        64            /* Internal Interrupt Combiner
+-                                            Groups number */
+-#define    IIC_NIRQ        (IIC_NGRP * 8)/* Internal Interrupt Combiner
+-                                            Interrupts number */
+ #define IIC_REGION_SIZE    0x108         /* Size of memory mapped region */
+-#define IIC_REGSET_SIZE    0x41
+-
+-/*
+- * State for each output signal of internal combiner
+- */
+-typedef struct CombinerGroupState {
+-    uint8_t src_mask;            /* 1 - source enabled, 0 - disabled */
+-    uint8_t src_pending;        /* Pending source interrupts before masking */
+-} CombinerGroupState;
+-
+-#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
+-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
+-
+-struct Exynos4210CombinerState {
+-    SysBusDevice parent_obj;
+-
+-    MemoryRegion iomem;
+-
+-    struct CombinerGroupState group[IIC_NGRP];
+-    uint32_t reg_set[IIC_REGSET_SIZE];
+-    uint32_t icipsr[2];
+-    uint32_t external;          /* 1 means that this combiner is external */
+-
+-    qemu_irq output_irq[IIC_NGRP];
+-};
+ static const VMStateDescription vmstate_exynos4210_combiner_group_state = {
+     .name = "exynos4210.combiner.groupstate",
+--
+.25.1

-New patch
+[PULL 25/31] hw/arm/exynos4210: Drop Exynos4210Irq struct
+The only time we use the int_combiner_irq[] and ext_combiner_irq[]
+arrays in the Exynos4210Irq struct is during realize of the SoC -- we
+initialize them with the input IRQs of the combiner devices, and then
+connect those to outputs of other devices in
+exynos4210_init_board_irqs().  Now that the combiner objects are
+easily accessible as s->int_combiner and s->ext_combiner we can make
+the connections directly from one device to the other without going
+via these arrays.
+Since these are the only two remaining elements of Exynos4210Irq,
+we can remove that struct entirely.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-19-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  6 ------
+ hw/arm/exynos4210.c         | 34 ++++++++--------------------------
+files changed, 8 insertions(+), 32 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+  */
+ #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
+-typedef struct Exynos4210Irq {
+-    qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+-    qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
+-} Exynos4210Irq;
+-
+ struct Exynos4210State {
+     /*< private >*/
+     SysBusDevice parent_obj;
+     /*< public >*/
+     ARMCPU *cpu[EXYNOS4210_NCPUS];
+-    Exynos4210Irq irqs;
+     qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     MemoryRegion chipid_mem;
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline)
+ static void exynos4210_init_board_irqs(Exynos4210State *s)
+ {
+     uint32_t grp, bit, irq_id, n;
+-    Exynos4210Irq *is = &s->irqs;
+     DeviceState *extgicdev = DEVICE(&s->ext_gic);
++    DeviceState *intcdev = DEVICE(&s->int_combiner);
++    DeviceState *extcdev = DEVICE(&s->ext_combiner);
+     int splitcount = 0;
+     DeviceState *splitter;
+     const int *mapline;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+         splitin = 0;
+         for (;;) {
+             s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
+-            qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]);
+-            qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]);
++            qdev_connect_gpio_out(splitter, splitin,
++                                  qdev_get_gpio_in(intcdev, in));
++            qdev_connect_gpio_out(splitter, splitin + 1,
++                                  qdev_get_gpio_in(extcdev, in));
+             splitin += 2;
+             if (!mapline) {
+                 break;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+             qdev_realize(splitter, NULL, &error_abort);
+             splitcount++;
+             s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
+-            qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
++            qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n));
+             qdev_connect_gpio_out(splitter, 1,
+                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
+         } else {
+-            s->irq_table[n] = is->int_combiner_irq[n];
++            s->irq_table[n] = qdev_get_gpio_in(intcdev, n);
+         }
+     }
+     /*
+@@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
+     return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
+ }
+-/*
+- * Get Combiner input GPIO into irqs structure
+- */
+-static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
+-                                           DeviceState *dev, int ext)
+-{
+-    int n;
+-    int max;
+-    qemu_irq *irq;
+-
+-    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
+-        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
+-    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
+-
+-    for (n = 0; n < max; n++) {
+-        irq[n] = qdev_get_gpio_in(dev, n);
+-    }
+-}
+-
+ static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
+x09, 0x00, 0x00, 0x00 };
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+         sysbus_connect_irq(busdev, n,
+                            qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
+     }
+-    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
+     /* External Interrupt Combiner */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
+     }
+-    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
+     /* Initialize board IRQs. */
+--
+.25.1

-[PULL 09/11] m25p80: Improve command handling for unsupported commands
+[PULL 26/31] hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
-From: Guenter Roeck <linux@roeck-us.net>
+From: Zongyuan Li <zongyuan.li@smartx.com>
-Whenever an unsupported command is encountered, the current code
+Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
-interprets each transferred byte as new command. Most of the time, those
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-'commands' are interpreted as new unknown commands. However, in rare
+Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com
 cases, it may be that for example address or length information
 passed with the original command is by itself a valid command.
 If that happens, the state machine may get completely confused and,
 worst case, start writing data into the flash or even erase it.
 To avoid the problem, transition into STATE_READING_DATA and keep
 sending a value of 0 until the chip is deselected after encountering
 an unsupported command.
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/block/m25p80.c | 5 +++++
+ hw/arm/realview.c | 33 ++++++++++++++++++++++++---------
-file changed, 5 insertions(+)
+file changed, 24 insertions(+), 9 deletions(-)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+diff --git a/hw/arm/realview.c b/hw/arm/realview.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/hw/arm/realview.c
-+++ b/hw/block/m25p80.c
++++ b/hw/arm/realview.c
-@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
+@@ -XXX,XX +XXX,XX @@
-         s->quad_enable = false;
+ #include "hw/sysbus.h"
-         break;
+ #include "hw/arm/boot.h"
-     default:
+ #include "hw/arm/primecell.h"
-+        s->pos = 0;
++#include "hw/core/split-irq.h"
-+        s->len = 1;
+ #include "hw/net/lan9118.h"
-+        s->state = STATE_READING_DATA;
+ #include "hw/net/smc91c111.h"
-+        s->data_read_loop = true;
+ #include "hw/pci/pci.h"
-+        s->data[0] = 0;
++#include "hw/qdev-core.h"
-         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
+ #include "net/net.h"
-         break;
+ #include "sysemu/sysemu.h"
-     }
+ #include "hw/boards.h"
@@ -XXX,XX +XXX,XX @@ static const int realview_board_id[] = {
 x76d
  };
 +static void split_irq_from_named(DeviceState *src, const char* outname,
 +                                 qemu_irq out1, qemu_irq out2) {
 +    DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
 +
 +    qdev_prop_set_uint32(splitter, "num-lines", 2);
 +
 +    qdev_realize_and_unref(splitter, NULL, &error_fatal);
 +
 +    qdev_connect_gpio_out(splitter, 0, out1);
 +    qdev_connect_gpio_out(splitter, 1, out2);
 +    qdev_connect_gpio_out_named(src, outname, 0,
 +                                qdev_get_gpio_in(splitter, 0));
 +}
 +
  static void realview_init(MachineState *machine,
                            enum realview_board_type board_type)
  {
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
      DeviceState *dev, *sysctl, *gpio2, *pl041;
      SysBusDevice *busdev;
      qemu_irq pic[64];
 -    qemu_irq mmc_irq[2];
      PCIBus *pci_bus = NULL;
      NICInfo *nd;
      DriveInfo *dinfo;
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
       * and the PL061 has them the other way about. Also the card
       * detect line is inverted.
       */
 -    mmc_irq[0] = qemu_irq_split(
 -        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
 -        qdev_get_gpio_in(gpio2, 1));
 -    mmc_irq[1] = qemu_irq_split(
 -        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
 -        qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
 -    qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]);
 -    qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]);
 +    split_irq_from_named(dev, "card-read-only",
 +                   qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
 +                   qdev_get_gpio_in(gpio2, 1));
 +
 +    split_irq_from_named(dev, "card-inserted",
 +                   qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
 +                   qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
 +
      dinfo = drive_get(IF_SD, 0, 0);
      if (dinfo) {
          DeviceState *card;
 --
-.20.1
+.25.1

-[PULL 08/11] m25p80: Improve command handling for Jedec commands
+[PULL 27/31] hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
-From: Guenter Roeck <linux@roeck-us.net>
+From: Zongyuan Li <zongyuan.li@smartx.com>
-When requesting JEDEC data using the JEDEC_READ command, the Linux kernel
+Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
-always requests 6 bytes. The current implementation only returns three
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-bytes, and interprets the remaining three bytes as new commands.
+Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com
 While this does not matter most of the time, it is at the very least
 confusing. To avoid the problem, always report up to 6 bytes of JEDEC
 data. Fill remaining data with 0.
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/block/m25p80.c | 5 ++++-
+ hw/arm/stellaris.c | 15 +++++++++++++--
-file changed, 4 insertions(+), 1 deletion(-)
+file changed, 13 insertions(+), 2 deletions(-)
-diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/block/m25p80.c
+--- a/hw/arm/stellaris.c
-+++ b/hw/block/m25p80.c
++++ b/hw/arm/stellaris.c
-@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
+@@ -XXX,XX +XXX,XX @@
-         for (i = 0; i < s->pi->id_len; i++) {
-             s->data[i] = s->pi->id[i];
+ #include "qemu/osdep.h"
-         }
+ #include "qapi/error.h"
-+        for (; i < SPI_NOR_MAX_ID_LEN; i++) {
++#include "hw/core/split-irq.h"
-+            s->data[i] = 0;
+ #include "hw/sysbus.h"
-+        }
+ #include "hw/sd/sd.h"
+ #include "hw/ssi/ssi.h"
--        s->len = s->pi->id_len;
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
-+        s->len = SPI_NOR_MAX_ID_LEN;
+             DeviceState *ssddev;
-         s->pos = 0;
+             DriveInfo *dinfo;
-         s->state = STATE_READING_DATA;
+             DeviceState *carddev;
-         break;
++            DeviceState *gpio_d_splitter;
              BlockBackend *blk;
              /*
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
                                     &error_fatal);
              ssddev = ssi_create_peripheral(bus, "ssd0323");
 -            gpio_out[GPIO_D][0] = qemu_irq_split(
 -                    qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
 +
 +            gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
 +            qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
 +            qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
 +            qdev_connect_gpio_out(
 +                    gpio_d_splitter, 0,
 +                    qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0));
 +            qdev_connect_gpio_out(
 +                    gpio_d_splitter, 1,
                      qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
 +            gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0);
 +
              gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
              /* Make sure the select pin is high.  */
 --
-.20.1
+.25.1

-[PULL 06/11] hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
+[PULL 28/31] hw/core/irq: remove unused 'qemu_irq_split' function
-From: Chen Qun <kuhn.chenqun@huawei.com>
+From: Zongyuan Li <zongyuan.li@smartx.com>
-The current code causes clang static code analyzer generate warning:
+Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
 hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
         value = value & 0x0000000f;
         ^       ~~~~~~~~~~~~~~~~~~
 hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read
         value = value & 0x000000fd;
         ^       ~~~~~~~~~~~~~~~~~~
 According to the definition of the function, the two “value” assignments
  should be written to registers.
 Reported-by: Euler Robot <euler.robot@huawei.com>
 Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
 Message-id: 20200313123242.13236-1-kuhn.chenqun@huawei.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/net/imx_fec.c | 6 ++++--
+ include/hw/irq.h |  5 -----
-file changed, 4 insertions(+), 2 deletions(-)
+ hw/core/irq.c    | 15 ---------------
 files changed, 20 deletions(-)
-diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
+diff --git a/include/hw/irq.h b/include/hw/irq.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/net/imx_fec.c
+--- a/include/hw/irq.h
-+++ b/hw/net/imx_fec.c
++++ b/include/hw/irq.h
-@@ -XXX,XX +XXX,XX @@ static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value)
+@@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq);
-         break;
+ /* Returns a new IRQ with opposite polarity.  */
-     case ENET_TGSR:
+ qemu_irq qemu_irq_invert(qemu_irq irq);
-         /* implement clear timer flag */
--        value = value & 0x0000000f;
+-/* Returns a new IRQ which feeds into both the passed IRQs.
-+        s->regs[index] &= ~(value & 0x0000000f); /* all bits W1C */
+- * It's probably better to use the TYPE_SPLIT_IRQ device instead.
-         break;
+- */
-     case ENET_TCSR0:
+-qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
-     case ENET_TCSR1:
+-
-     case ENET_TCSR2:
+ /* For internal use in qtest.  Similar to qemu_irq_split, but operating
-     case ENET_TCSR3:
+    on an existing vector of qemu_irq.  */
--        value = value & 0x000000fd;
+ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
-+        s->regs[index] &= ~(value & 0x00000080); /* W1C bits */
+diff --git a/hw/core/irq.c b/hw/core/irq.c
-+        s->regs[index] &= ~0x0000007d; /* writable fields */
+index XXXXXXX..XXXXXXX 100644
-+        s->regs[index] |= (value & 0x0000007d);
+--- a/hw/core/irq.c
-         break;
++++ b/hw/core/irq.c
-     case ENET_TCCR0:
+@@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_invert(qemu_irq irq)
-     case ENET_TCCR1:
+     return qemu_allocate_irq(qemu_notirq, irq, 0);
  }
 -static void qemu_splitirq(void *opaque, int line, int level)
 -{
 -    struct IRQState **irq = opaque;
 -    irq[0]->handler(irq[0]->opaque, irq[0]->n, level);
 -    irq[1]->handler(irq[1]->opaque, irq[1]->n, level);
 -}
 -
 -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
 -{
 -    qemu_irq *s = g_new0(qemu_irq, 2);
 -    s[0] = irq1;
 -    s[1] = irq2;
 -    return qemu_allocate_irq(qemu_splitirq, s, 0);
 -}
 -
  void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
  {
      int i;
 --
-.20.1
+.25.1

-[PULL 03/11] hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices
+[PULL 29/31] hw/arm/virt: impact of gic-version on max CPUs
-From: Guenter Roeck <linux@roeck-us.net>
+From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
-Recent Linux kernels (post v4.20) crash due to accesses to flexcan
+Describe that the gic-version influences the maximum number of CPUs.
 and pwm controllers. Instantiate as unimplemented devices to work
 around the problem.
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
-Message-id: 20200313014551.12554-4-linux@roeck-us.net
+Message-id: 20220413231456.35811-1-heinrich.schuchardt@canonical.com
 [PMM: minor punctuation tweaks]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/fsl-imx6ul.c | 14 ++++++++++++++
+ docs/system/arm/virt.rst | 4 ++--
-file changed, 14 insertions(+)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
+diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/fsl-imx6ul.c
+--- a/docs/system/arm/virt.rst
-+++ b/hw/arm/fsl-imx6ul.c
++++ b/docs/system/arm/virt.rst
-@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@ gic-version
-      */
+   Valid values are:
-     create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
+   ``2``
-+    /*
+-    GICv2
-+     * PWM
++    GICv2. Note that this limits the number of CPUs to 8.
-+     */
+   ``3``
-+    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
+-    GICv3
-+    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
++    GICv3. This allows up to 512 CPUs.
-+    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
+   ``host``
-+    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
+     Use the same GIC version the host provides, when using KVM
-+
+   ``max``
 +    /*
 +     * CAN
 +     */
 +    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
 +    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
 +
      /*
       * APHB_DMA
       */
 --
-.20.1
+.25.1

-[PULL 02/11] hw/arm/fsl-imx6ul: Fix USB interrupt numbers
+[PULL 30/31] hw/misc: Add PWRON STRAP bit fields in GCR module
-From: Guenter Roeck <linux@roeck-us.net>
+From: Hao Wu <wuhaotsh@google.com>
-USB1 and USB2 interrupt numbers were swapped. USB_PHY2 interrupt number
+Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
-is 45. That didn't really matter up to now since the interrupts were not
+the PWRON STRAP fields in their corresponding module for NPCM7XX.
 used, but it needs to be fixed to be able to wire up the USB controllers.
-Fixes: 31cbf933f0e ("i.MX6UL: Add i.MX6UL SOC")
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Reviewed-by: Patrick Venture <venture@google.com>
-Message-id: 20200313014551.12554-3-linux@roeck-us.net
+Message-id: 20220411165842.3912945-2-wuhaotsh@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- include/hw/arm/fsl-imx6ul.h | 6 +++---
+ include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++
-file changed, 3 insertions(+), 3 deletions(-)
+file changed, 30 insertions(+)
-diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx6ul.h
+--- a/include/hw/misc/npcm7xx_gcr.h
-+++ b/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/misc/npcm7xx_gcr.h
-@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULIRQs {
+@@ -XXX,XX +XXX,XX @@
-     FSL_IMX6UL_UART7_IRQ    = 39,
+ #include "exec/memory.h"
-     FSL_IMX6UL_UART8_IRQ    = 40,
+ #include "hw/sysbus.h"
--    FSL_IMX6UL_USB1_IRQ     = 42,
++/*
--    FSL_IMX6UL_USB2_IRQ     = 43,
++ * NPCM7XX PWRON STRAP bit fields
-+    FSL_IMX6UL_USB1_IRQ     = 43,
++ * 12: SPI0 powered by VSBV3 at 1.8V
-+    FSL_IMX6UL_USB2_IRQ     = 42,
++ * 11: System flash attached to BMC
-     FSL_IMX6UL_USB_PHY1_IRQ = 44,
++ * 10: BSP alternative pins.
--    FSL_IMX6UL_USB_PHY2_IRQ = 44,
++ * 9:8: Flash UART command route enabled.
-+    FSL_IMX6UL_USB_PHY2_IRQ = 45,
++ * 7: Security enabled.
++ * 6: HI-Z state control.
-     FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
++ * 5: ECC disabled.
-     FSL_IMX6UL_CAAM_ERR_IRQ = 47,
++ * 4: Reserved
 + * 3: JTAG2 enabled.
 + * 2:0: CPU and DRAM clock frequency.
 + */
 +#define NPCM7XX_PWRON_STRAP_SPI0F18                 BIT(12)
 +#define NPCM7XX_PWRON_STRAP_SFAB                    BIT(11)
 +#define NPCM7XX_PWRON_STRAP_BSPA                    BIT(10)
 +#define NPCM7XX_PWRON_STRAP_FUP(x)                  ((x) << 8)
 +#define     FUP_NORM_UART2      3
 +#define     FUP_PROG_UART3      2
 +#define     FUP_PROG_UART2      1
 +#define     FUP_NORM_UART3      0
 +#define NPCM7XX_PWRON_STRAP_SECEN                   BIT(7)
 +#define NPCM7XX_PWRON_STRAP_HIZ                     BIT(6)
 +#define NPCM7XX_PWRON_STRAP_ECC                     BIT(5)
 +#define NPCM7XX_PWRON_STRAP_RESERVE1                BIT(4)
 +#define NPCM7XX_PWRON_STRAP_J2EN                    BIT(3)
 +#define NPCM7XX_PWRON_STRAP_CKFRQ(x)                (x)
 +#define     CKFRQ_SKIPINIT      0x000
 +#define     CKFRQ_DEFAULT       0x111
 +
  /*
   * Number of registers in our device state structure. Don't change this without
   * incrementing the version_id in the vmstate.
 --
-.20.1
+.25.1

-[PULL 11/11] hw/arm/pxa2xx: Do not wire up OHCI for PXA255
+[PULL 31/31] hw/arm: Use bit fields for NPCM7XX PWRON STRAPs
-From: Guenter Roeck <linux@roeck-us.net>
+From: Hao Wu <wuhaotsh@google.com>
-PXA255 does not support a USB OHCI controller, so don't wire it up.
+This patch uses the defined fields to describe PWRON STRAPs for
 better readability.
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
-Message-id: 20200313160215.28155-1-linux@roeck-us.net
+Reviewed-by: Patrick Venture <venture@google.com>
 Message-id: 20220411165842.3912945-3-wuhaotsh@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/pxa2xx.c | 3 ---
+ hw/arm/npcm7xx_boards.c | 24 +++++++++++++++++++-----
-file changed, 3 deletions(-)
+file changed, 19 insertions(+), 5 deletions(-)
-diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
+diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/pxa2xx.c
+--- a/hw/arm/npcm7xx_boards.c
-+++ b/hw/arm/pxa2xx.c
++++ b/hw/arm/npcm7xx_boards.c
-@@ -XXX,XX +XXX,XX @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
+@@ -XXX,XX +XXX,XX @@
-         s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
+ #include "sysemu/sysemu.h"
-     }
+ #include "sysemu/block-backend.h"
--    sysbus_create_simple("sysbus-ohci", 0x4c000000,
+-#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
--                         qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
+-#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
--
+-#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff
-     s->pcmcia[0] = pxa2xx_pcmcia_init(address_space, 0x20000000);
+-#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff
-     s->pcmcia[1] = pxa2xx_pcmcia_init(address_space, 0x30000000);
+-#define MORI_BMC_POWER_ON_STRAPS 0x00001fff
 +#define NPCM7XX_POWER_ON_STRAPS_DEFAULT (           \
 +        NPCM7XX_PWRON_STRAP_SPI0F18 |               \
 +        NPCM7XX_PWRON_STRAP_SFAB |                  \
 +        NPCM7XX_PWRON_STRAP_BSPA |                  \
 +        NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) |   \
 +        NPCM7XX_PWRON_STRAP_SECEN |                 \
 +        NPCM7XX_PWRON_STRAP_HIZ |                   \
 +        NPCM7XX_PWRON_STRAP_ECC |                   \
 +        NPCM7XX_PWRON_STRAP_RESERVE1 |              \
 +        NPCM7XX_PWRON_STRAP_J2EN |                  \
 +        NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT))
 +
 +#define NPCM750_EVB_POWER_ON_STRAPS ( \
 +        NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN)
 +#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
 +#define QUANTA_GBS_POWER_ON_STRAPS ( \
 +        NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
 +#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
 +#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
  static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
 --
-.20.1
+.25.1

Last handful of arm patches before softfreeze...

The following changes since commit a98135f727595382e200d04c2996e868b7925a01:

Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200316-pull-request' into staging (2020-03-16 14:55:59 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200317

for you to fetch changes up to e88d3671e3bbd59d385838a4101ea19cdcf47309:

hw/arm/pxa2xx: Do not wire up OHCI for PXA255 (2020-03-17 11:36:48 +0000)

----------------------------------------------------------------
target-arm:
 * hw/arm/pxa2xx: Do not wire up OHCI for PXA255
 * aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
 * m25p80: Improve command handling for Jedec and unsupported commands
 * hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()
 * hw/arm/fsl-imx6, imx6ul: Wire up USB controllers
 * hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices

----------------------------------------------------------------
Chen Qun (1):
      hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write()

Guenter Roeck (10):
      hw/usb: Add basic i.MX USB Phy support
      hw/arm/fsl-imx6ul: Fix USB interrupt numbers
      hw/arm/fsl-imx6ul: Instantiate unimplemented pwm and can devices
      hw/arm/fsl-imx6ul: Wire up USB controllers
      hw/arm/fsl-imx6: Wire up USB controllers
      m25p80: Convert to support tracing
      m25p80: Improve command handling for Jedec commands
      m25p80: Improve command handling for unsupported commands
      aspeed/smc: Fix number of dummy cycles for FAST_READ_4 command
      hw/arm/pxa2xx: Do not wire up OHCI for PXA255

From: Guenter Roeck <linux@roeck-us.net>

Add basic USB PHY support as implemented in i.MX23, i.MX28, i.MX6,
and i.MX7 SoCs.

The only support really needed - at least to boot Linux - is support
for soft reset, which needs to reset various registers to their initial
value. Otherwise, just record register values.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-2-linux@roeck-us.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/usb/Makefile.objs         |   2 +
 include/hw/usb/imx-usb-phy.h |  53 +++++++++
 hw/usb/imx-usb-phy.c         | 225 +++++++++++++++++++++++++++++++++++
 MAINTAINERS                  |   2 +
 hw/arm/Kconfig               |   1 +
 hw/usb/Kconfig               |   5 +
 6 files changed, 288 insertions(+)
 create mode 100644 include/hw/usb/imx-usb-phy.h
 create mode 100644 hw/usb/imx-usb-phy.c

diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/Makefile.objs
+++ b/hw/usb/Makefile.objs
@@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XEN) += xen-usb.o
 xen-usb.o-cflags := $(LIBUSB_CFLAGS)
 xen-usb.o-libs := $(LIBUSB_LIBS)
 endif
+
+common-obj-$(CONFIG_IMX_USBPHY) += imx-usb-phy.o
diff --git a/include/hw/usb/imx-usb-phy.h b/include/hw/usb/imx-usb-phy.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/usb/imx-usb-phy.h
@@ -XXX,XX +XXX,XX @@
+#ifndef IMX_USB_PHY_H
+#define IMX_USB_PHY_H
+
+#include "hw/sysbus.h"
+#include "qemu/bitops.h"
+
+enum IMXUsbPhyRegisters {
+    USBPHY_PWD,
+    USBPHY_PWD_SET,
+    USBPHY_PWD_CLR,
+    USBPHY_PWD_TOG,
+    USBPHY_TX,
+    USBPHY_TX_SET,
+    USBPHY_TX_CLR,
+    USBPHY_TX_TOG,
+    USBPHY_RX,
+    USBPHY_RX_SET,
+    USBPHY_RX_CLR,
+    USBPHY_RX_TOG,
+    USBPHY_CTRL,
+    USBPHY_CTRL_SET,
+    USBPHY_CTRL_CLR,
+    USBPHY_CTRL_TOG,
+    USBPHY_STATUS,
+    USBPHY_DEBUG = 0x14,
+    USBPHY_DEBUG_SET,
+    USBPHY_DEBUG_CLR,
+    USBPHY_DEBUG_TOG,
+    USBPHY_DEBUG0_STATUS,
+    USBPHY_DEBUG1 = 0x1c,
+    USBPHY_DEBUG1_SET,
+    USBPHY_DEBUG1_CLR,
+    USBPHY_DEBUG1_TOG,
+    USBPHY_VERSION,
+    USBPHY_MAX
+};
+
+#define USBPHY_CTRL_SFTRST BIT(31)
+
+#define TYPE_IMX_USBPHY "imx.usbphy"
+#define IMX_USBPHY(obj) OBJECT_CHECK(IMXUSBPHYState, (obj), TYPE_IMX_USBPHY)
+
+typedef struct IMXUSBPHYState {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion iomem;
+
+    uint32_t usbphy[USBPHY_MAX];
+} IMXUSBPHYState;
+
+#endif /* IMX_USB_PHY_H */
diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/usb/imx-usb-phy.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * i.MX USB PHY
+ *
+ * Copyright (c) 2020 Guenter Roeck <linux@roeck-us.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ * We need to implement basic reset control in the PHY control register.
+ * For everything else, it is sufficient to set whatever is written.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/usb/imx-usb-phy.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+
+static const VMStateDescription vmstate_imx_usbphy = {
+    .name = TYPE_IMX_USBPHY,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(usbphy, IMXUSBPHYState, USBPHY_MAX),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static void imx_usbphy_softreset(IMXUSBPHYState *s)
+{
+    s->usbphy[USBPHY_PWD] = 0x001e1c00;
+    s->usbphy[USBPHY_TX] = 0x10060607;
+    s->usbphy[USBPHY_RX] = 0x00000000;
+    s->usbphy[USBPHY_CTRL] = 0xc0200000;
+}
+
+static void imx_usbphy_reset(DeviceState *dev)
+{
+    IMXUSBPHYState *s = IMX_USBPHY(dev);
+
+    s->usbphy[USBPHY_STATUS] = 0x00000000;
+    s->usbphy[USBPHY_DEBUG] = 0x7f180000;
+    s->usbphy[USBPHY_DEBUG0_STATUS] = 0x00000000;
+    s->usbphy[USBPHY_DEBUG1] = 0x00001000;
+    s->usbphy[USBPHY_VERSION] = 0x04020000;
+
+    imx_usbphy_softreset(s);
+}
+
+static uint64_t imx_usbphy_read(void *opaque, hwaddr offset, unsigned size)
+{
+    IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
+    uint32_t index = offset >> 2;
+    uint32_t value;
+
+    switch (index) {
+    case USBPHY_PWD_SET:
+    case USBPHY_TX_SET:
+    case USBPHY_RX_SET:
+    case USBPHY_CTRL_SET:
+    case USBPHY_DEBUG_SET:
+    case USBPHY_DEBUG1_SET:
+        /*
+         * All REG_NAME_SET register access are in fact targeting the
+         * REG_NAME register.
+         */
+        value = s->usbphy[index - 1];
+        break;
+    case USBPHY_PWD_CLR:
+    case USBPHY_TX_CLR:
+    case USBPHY_RX_CLR:
+    case USBPHY_CTRL_CLR:
+    case USBPHY_DEBUG_CLR:
+    case USBPHY_DEBUG1_CLR:
+        /*
+         * All REG_NAME_CLR register access are in fact targeting the
+         * REG_NAME register.
+         */
+        value = s->usbphy[index - 2];
+        break;
+    case USBPHY_PWD_TOG:
+    case USBPHY_TX_TOG:
+    case USBPHY_RX_TOG:
+    case USBPHY_CTRL_TOG:
+    case USBPHY_DEBUG_TOG:
+    case USBPHY_DEBUG1_TOG:
+        /*
+         * All REG_NAME_TOG register access are in fact targeting the
+         * REG_NAME register.
+         */
+        value = s->usbphy[index - 3];
+        break;
+    default:
+        value = s->usbphy[index];
+        break;
+    }
+    return (uint64_t)value;
+}
+
+static void imx_usbphy_write(void *opaque, hwaddr offset, uint64_t value,
+                             unsigned size)
+{
+    IMXUSBPHYState *s = (IMXUSBPHYState *)opaque;
+    uint32_t index = offset >> 2;
+
+    switch (index) {
+    case USBPHY_CTRL:
+        s->usbphy[index] = value;
+        if (value & USBPHY_CTRL_SFTRST) {
+            imx_usbphy_softreset(s);
+        }
+        break;
+    case USBPHY_PWD:
+    case USBPHY_TX:
+    case USBPHY_RX:
+    case USBPHY_STATUS:
+    case USBPHY_DEBUG:
+    case USBPHY_DEBUG1:
+        s->usbphy[index] = value;
+        break;
+    case USBPHY_CTRL_SET:
+        s->usbphy[index - 1] |= value;
+        if (value & USBPHY_CTRL_SFTRST) {
+            imx_usbphy_softreset(s);
+        }
+        break;
+    case USBPHY_PWD_SET:
+    case USBPHY_TX_SET:
+    case USBPHY_RX_SET:
+    case USBPHY_DEBUG_SET:
+    case USBPHY_DEBUG1_SET:
+        /*
+         * All REG_NAME_SET register access are in fact targeting the
+         * REG_NAME register. So we change the value of the REG_NAME
+         * register, setting bits passed in the value.
+         */
+        s->usbphy[index - 1] |= value;
+        break;
+    case USBPHY_PWD_CLR:
+    case USBPHY_TX_CLR:
+    case USBPHY_RX_CLR:
+    case USBPHY_CTRL_CLR:
+    case USBPHY_DEBUG_CLR:
+    case USBPHY_DEBUG1_CLR:
+        /*
+         * All REG_NAME_CLR register access are in fact targeting the
+         * REG_NAME register. So we change the value of the REG_NAME
+         * register, unsetting bits passed in the value.
+         */
+        s->usbphy[index - 2] &= ~value;
+        break;
+    case USBPHY_CTRL_TOG:
+        s->usbphy[index - 3] ^= value;
+        if ((value & USBPHY_CTRL_SFTRST) &&
+            (s->usbphy[index - 3] & USBPHY_CTRL_SFTRST)) {
+            imx_usbphy_softreset(s);
+        }
+        break;
+    case USBPHY_PWD_TOG:
+    case USBPHY_TX_TOG:
+    case USBPHY_RX_TOG:
+    case USBPHY_DEBUG_TOG:
+    case USBPHY_DEBUG1_TOG:
+        /*
+         * All REG_NAME_TOG register access are in fact targeting the
+         * REG_NAME register. So we change the value of the REG_NAME
+         * register, toggling bits passed in the value.
+         */
+        s->usbphy[index - 3] ^= value;
+        break;
+    default:
+        /* Other registers are read-only */
+        break;
+    }
+}
+
+static const struct MemoryRegionOps imx_usbphy_ops = {
+    .read = imx_usbphy_read,
+    .write = imx_usbphy_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        /*
+         * Our device would not work correctly if the guest was doing
+         * unaligned access. This might not be a limitation on the real
+         * device but in practice there is no reason for a guest to access
+         * this device unaligned.
+         */
+        .min_access_size = 4,
+        .max_access_size = 4,
+        .unaligned = false,
+    },
+};
+
+static void imx_usbphy_realize(DeviceState *dev, Error **errp)
+{
+    IMXUSBPHYState *s = IMX_USBPHY(dev);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &imx_usbphy_ops, s,
+                          "imx-usbphy", 0x1000);
+    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+}
+
+static void imx_usbphy_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = imx_usbphy_reset;
+    dc->vmsd = &vmstate_imx_usbphy;
+    dc->desc = "i.MX USB PHY Module";
+    dc->realize = imx_usbphy_realize;
+}
+
+static const TypeInfo imx_usbphy_info = {
+    .name          = TYPE_IMX_USBPHY,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(IMXUSBPHYState),
+    .class_init    = imx_usbphy_class_init,
+};
+
+static void imx_usbphy_register_types(void)
+{
+    type_register_static(&imx_usbphy_info);
+}
+
+type_init(imx_usbphy_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/arm/sabrelite.c
 F: hw/arm/fsl-imx6.c
 F: hw/misc/imx6_*.c
 F: hw/ssi/imx_spi.c
+F: hw/usb/imx-usb-phy.c
+F: include/hw/usb/imx-usb-phy.h
 F: include/hw/arm/fsl-imx6.h
 F: include/hw/misc/imx6_*.h
 F: include/hw/ssi/imx_spi.h
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -XXX,XX +XXX,XX @@ config FSL_IMX6
     select IMX
     select IMX_FEC
     select IMX_I2C
+    select IMX_USBPHY
     select SDHCI
 
 config ASPEED_SOC
diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig
index XXXXXXX..XXXXXXX 100644
--- a/hw/usb/Kconfig
+++ b/hw/usb/Kconfig
@@ -XXX,XX +XXX,XX @@ config USB_STORAGE_MTP
     bool
     default y
     depends on USB
+
+config IMX_USBPHY
+    bool
+    default y
+    depends on USB
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

USB1 and USB2 interrupt numbers were swapped. USB_PHY2 interrupt number
is 45. That didn't really matter up to now since the interrupts were not
used, but it needs to be fixed to be able to wire up the USB controllers.

Fixes: 31cbf933f0e ("i.MX6UL: Add i.MX6UL SOC")
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-3-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULIRQs {
     FSL_IMX6UL_UART7_IRQ    = 39,
     FSL_IMX6UL_UART8_IRQ    = 40,
 
-    FSL_IMX6UL_USB1_IRQ     = 42,
-    FSL_IMX6UL_USB2_IRQ     = 43,
+    FSL_IMX6UL_USB1_IRQ     = 43,
+    FSL_IMX6UL_USB2_IRQ     = 42,
     FSL_IMX6UL_USB_PHY1_IRQ = 44,
-    FSL_IMX6UL_USB_PHY2_IRQ = 44,
+    FSL_IMX6UL_USB_PHY2_IRQ = 45,
 
     FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
     FSL_IMX6UL_CAAM_ERR_IRQ = 47,
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

Recent Linux kernels (post v4.20) crash due to accesses to flexcan
and pwm controllers. Instantiate as unimplemented devices to work
around the problem.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-4-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/fsl-imx6ul.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      */
     create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
 
+    /*
+     * PWM
+     */
+    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
+    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
+    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
+    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
+
+    /*
+     * CAN
+     */
+    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
+    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
+
     /*
      * APHB_DMA
      */
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

IMX6UL USB controllers are quite similar to IMX7 USB controllers.
Wire them up the same way.

The only real difference is that wiring up phy devices is necessary
to avoid phy reset timeouts in the Linux kernel.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-5-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h | 10 ++++++++++
 hw/arm/fsl-imx6ul.c         | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/sd/sdhci.h"
 #include "hw/ssi/imx_spi.h"
 #include "hw/net/imx_fec.h"
+#include "hw/usb/chipidea.h"
+#include "hw/usb/imx-usb-phy.h"
 #include "exec/memory.h"
 #include "cpu.h"
 
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_I2CS         = 4,
     FSL_IMX6UL_NUM_ECSPIS       = 4,
     FSL_IMX6UL_NUM_ADCS         = 2,
+    FSL_IMX6UL_NUM_USB_PHYS     = 2,
+    FSL_IMX6UL_NUM_USBS         = 2,
 };
 
 typedef struct FslIMX6ULState {
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
     IMXFECState        eth[FSL_IMX6UL_NUM_ETHS];
     SDHCIState         usdhc[FSL_IMX6UL_NUM_USDHCS];
     IMX2WdtState       wdt[FSL_IMX6UL_NUM_WDTS];
+    IMXUSBPHYState     usbphy[FSL_IMX6UL_NUM_USB_PHYS];
+    ChipideaState      usb[FSL_IMX6UL_NUM_USBS];
     MemoryRegion       rom;
     MemoryRegion       caam;
     MemoryRegion       ocram;
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULMemoryMap {
     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
+    FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
+    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
+    FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
+    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/arm/fsl-imx6ul.h"
 #include "hw/misc/unimp.h"
+#include "hw/usb/imx-usb-phy.h"
 #include "hw/boards.h"
 #include "sysemu/sysemu.h"
 #include "qemu/error-report.h"
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
                               TYPE_IMX_ENET);
     }
 
+    /* USB */
+    for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+        snprintf(name, NAME_SIZE, "usbphy%d", i);
+        sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
+                              TYPE_IMX_USBPHY);
+    }
+    for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+        snprintf(name, NAME_SIZE, "usb%d", i);
+        sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
+                              TYPE_CHIPIDEA);
+    }
+
     /*
      * SDHCI
      */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
     }
 
+    /* USB */
+    for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+        object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
+                                 &error_abort);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
+    }
+
+    for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+        static const int FSL_IMX6UL_USBn_IRQ[] = {
+            FSL_IMX6UL_USB1_IRQ,
+            FSL_IMX6UL_USB2_IRQ,
+        };
+        object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
+                                 &error_abort);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                           qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                                            FSL_IMX6UL_USBn_IRQ[i]));
+    }
+
     /*
      * USDHC
      */
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

With this patch, the USB controllers on 'sabrelite' are detected
and can be used to boot the system.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200313014551.12554-6-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6.h |  6 ++++++
 hw/arm/fsl-imx6.c         | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/sd/sdhci.h"
 #include "hw/ssi/imx_spi.h"
 #include "hw/net/imx_fec.h"
+#include "hw/usb/chipidea.h"
+#include "hw/usb/imx-usb-phy.h"
 #include "exec/memory.h"
 #include "cpu.h"
 
@@ -XXX,XX +XXX,XX @@
 #define FSL_IMX6_NUM_ESDHCS 4
 #define FSL_IMX6_NUM_ECSPIS 5
 #define FSL_IMX6_NUM_WDTS 2
+#define FSL_IMX6_NUM_USB_PHYS 2
+#define FSL_IMX6_NUM_USBS 4
 
 typedef struct FslIMX6State {
     /*< private >*/
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State {
     SDHCIState     esdhc[FSL_IMX6_NUM_ESDHCS];
     IMXSPIState    spi[FSL_IMX6_NUM_ECSPIS];
     IMX2WdtState   wdt[FSL_IMX6_NUM_WDTS];
+    IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
+    ChipideaState  usb[FSL_IMX6_NUM_USBS];
     IMXFECState    eth;
     MemoryRegion   rom;
     MemoryRegion   caam;
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/arm/fsl-imx6.h"
+#include "hw/usb/imx-usb-phy.h"
 #include "hw/boards.h"
 #include "hw/qdev-properties.h"
 #include "sysemu/sysemu.h"
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
                               TYPE_IMX_USDHC);
     }
 
+    for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
+        snprintf(name, NAME_SIZE, "usbphy%d", i);
+        sysbus_init_child_obj(obj, name, &s->usbphy[i], sizeof(s->usbphy[i]),
+                              TYPE_IMX_USBPHY);
+    }
+    for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
+        snprintf(name, NAME_SIZE, "usb%d", i);
+        sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
+                              TYPE_CHIPIDEA);
+    }
+
     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
         sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
                                             esdhc_table[i].irq));
     }
 
+    /* USB */
+    for (i = 0; i < FSL_IMX6_NUM_USB_PHYS; i++) {
+        object_property_set_bool(OBJECT(&s->usbphy[i]), true, "realized",
+                                 &error_abort);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+                        FSL_IMX6_USBPHY1_ADDR + i * 0x1000);
+    }
+    for (i = 0; i < FSL_IMX6_NUM_USBS; i++) {
+        static const int FSL_IMX6_USBn_IRQ[] = {
+            FSL_IMX6_USB_OTG_IRQ,
+            FSL_IMX6_USB_HOST1_IRQ,
+            FSL_IMX6_USB_HOST2_IRQ,
+            FSL_IMX6_USB_HOST3_IRQ,
+        };
+
+        object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
+                                 &error_abort);
+        sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                        FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
+        sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
+                                            FSL_IMX6_USBn_IRQ[i]));
+    }
+
     /* Initialize all ECSPI */
     for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) {
         static const struct {
-- 
2.20.1

From: Chen Qun <kuhn.chenqun@huawei.com>

The current code causes clang static code analyzer generate warning:
hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read
        value = value & 0x0000000f;
        ^       ~~~~~~~~~~~~~~~~~~
hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read
        value = value & 0x000000fd;
        ^       ~~~~~~~~~~~~~~~~~~

According to the definition of the function, the two “value” assignments
 should be written to registers.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Message-id: 20200313123242.13236-1-kuhn.chenqun@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/net/imx_fec.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -XXX,XX +XXX,XX @@ static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value)
         break;
     case ENET_TGSR:
         /* implement clear timer flag */
-        value = value & 0x0000000f;
+        s->regs[index] &= ~(value & 0x0000000f); /* all bits W1C */
         break;
     case ENET_TCSR0:
     case ENET_TCSR1:
     case ENET_TCSR2:
     case ENET_TCSR3:
-        value = value & 0x000000fd;
+        s->regs[index] &= ~(value & 0x00000080); /* W1C bits */
+        s->regs[index] &= ~0x0000007d; /* writable fields */
+        s->regs[index] |= (value & 0x0000007d);
         break;
     case ENET_TCCR0:
     case ENET_TCCR1:
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

While at it, add some trace messages to help debug problems
seen when running the latest Linux kernel.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/block/m25p80.c     | 48 ++++++++++++++++++++-----------------------
 hw/block/trace-events | 16 +++++++++++++++
 2 files changed, 38 insertions(+), 26 deletions(-)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
-
-#ifndef M25P80_ERR_DEBUG
-#define M25P80_ERR_DEBUG 0
-#endif
-
-#define DB_PRINT_L(level, ...) do { \
-    if (M25P80_ERR_DEBUG > (level)) { \
-        fprintf(stderr,  ": %s: ", __func__); \
-        fprintf(stderr, ## __VA_ARGS__); \
-    } \
-} while (0)
+#include "trace.h"
 
 /* Fields for FlashPartInfo->flags */
 
@@ -XXX,XX +XXX,XX @@ static void flash_erase(Flash *s, int offset, FlashCMD cmd)
         abort();
     }
 
-    DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
+    trace_m25p80_flash_erase(s, offset, len);
+
     if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
                       " device\n", len);
@@ -XXX,XX +XXX,XX @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)
     }
 
     if ((prev ^ data) & data) {
-        DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 "  %" PRIx8
-                   " -> %" PRIx8 "\n", addr, prev, data);
+        trace_m25p80_programming_zero_to_one(s, addr, prev, data);
     }
 
     if (s->pi->flags & EEPROM) {
@@ -XXX,XX +XXX,XX @@ static void complete_collecting_data(Flash *s)
 
     s->state = STATE_IDLE;
 
+    trace_m25p80_complete_collecting(s, s->cmd_in_progress, n, s->ear,
+                                     s->cur_addr);
+
     switch (s->cmd_in_progress) {
     case DPP:
     case QPP:
@@ -XXX,XX +XXX,XX @@ static void reset_memory(Flash *s)
         break;
     }
 
-    DB_PRINT_L(0, "Reset done.\n");
+    trace_m25p80_reset_done(s);
 }
 
 static void decode_fast_read_cmd(Flash *s)
@@ -XXX,XX +XXX,XX @@ static void decode_qio_read_cmd(Flash *s)
 
 static void decode_new_cmd(Flash *s, uint32_t value)
 {
-    s->cmd_in_progress = value;
     int i;
-    DB_PRINT_L(0, "decoded new command:%x\n", value);
+
+    s->cmd_in_progress = value;
+    trace_m25p80_command_decoded(s, value);
 
     if (value != RESET_MEMORY) {
         s->reset_enable = false;
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
         break;
 
     case JEDEC_READ:
-        DB_PRINT_L(0, "populated jedec code\n");
+        trace_m25p80_populated_jedec(s);
         for (i = 0; i < s->pi->id_len; i++) {
             s->data[i] = s->pi->id[i];
         }
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
     case BULK_ERASE_60:
     case BULK_ERASE:
         if (s->write_enable) {
-            DB_PRINT_L(0, "chip erase\n");
+            trace_m25p80_chip_erase(s);
             flash_erase(s, 0, BULK_ERASE);
         } else {
             qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
@@ -XXX,XX +XXX,XX @@ static int m25p80_cs(SSISlave *ss, bool select)
         s->data_read_loop = false;
     }
 
-    DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
+    trace_m25p80_select(s, select ? "de" : "");
 
     return 0;
 }
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
     Flash *s = M25P80(ss);
     uint32_t r = 0;
 
+    trace_m25p80_transfer(s, s->state, s->len, s->needed_bytes, s->pos,
+                          s->cur_addr, (uint8_t)tx);
+
     switch (s->state) {
 
     case STATE_PAGE_PROGRAM:
-        DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
-                   s->cur_addr, (uint8_t)tx);
+        trace_m25p80_page_program(s, s->cur_addr, (uint8_t)tx);
         flash_write8(s, s->cur_addr, (uint8_t)tx);
         s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
         break;
 
     case STATE_READ:
         r = s->storage[s->cur_addr];
-        DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
-                   (uint8_t)r);
+        trace_m25p80_read_byte(s, s->cur_addr, (uint8_t)r);
         s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
         break;
 
@@ -XXX,XX +XXX,XX @@ static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
         }
 
         r = s->data[s->pos];
+        trace_m25p80_read_data(s, s->pos, (uint8_t)r);
         s->pos++;
         if (s->pos == s->len) {
             s->pos = 0;
@@ -XXX,XX +XXX,XX @@ static void m25p80_realize(SSISlave *ss, Error **errp)
             return;
         }
 
-        DB_PRINT_L(0, "Binding to IF_MTD drive\n");
+        trace_m25p80_binding(s);
         s->storage = blk_blockalign(s->blk, s->size);
 
         if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
@@ -XXX,XX +XXX,XX @@ static void m25p80_realize(SSISlave *ss, Error **errp)
             return;
         }
     } else {
-        DB_PRINT_L(0, "No BDRV - binding to RAM\n");
+        trace_m25p80_binding_no_bdrv(s);
         s->storage = blk_blockalign(NULL, s->size);
         memset(s->storage, 0xFF, s->size);
     }
diff --git a/hw/block/trace-events b/hw/block/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/trace-events
+++ b/hw/block/trace-events
@@ -XXX,XX +XXX,XX @@ xen_block_blockdev_add(char *str) "%s"
 xen_block_blockdev_del(const char *node_name) "%s"
 xen_block_device_create(unsigned int number) "%u"
 xen_block_device_destroy(unsigned int number) "%u"
+
+# m25p80.c
+m25p80_flash_erase(void *s, int offset, uint32_t len) "[%p] offset = 0x%"PRIx32", len = %u"
+m25p80_programming_zero_to_one(void *s, uint32_t addr, uint8_t prev, uint8_t data) "[%p] programming zero to one! addr=0x%"PRIx32"  0x%"PRIx8" -> 0x%"PRIx8
+m25p80_reset_done(void *s) "[%p] Reset done."
+m25p80_command_decoded(void *s, uint32_t cmd) "[%p] new command:0x%"PRIx32
+m25p80_complete_collecting(void *s, uint32_t cmd, int n, uint8_t ear, uint32_t cur_addr) "[%p] decode cmd: 0x%"PRIx32" len %d ear 0x%"PRIx8" addr 0x%"PRIx32
+m25p80_populated_jedec(void *s) "[%p] populated jedec code"
+m25p80_chip_erase(void *s) "[%p] chip erase"
+m25p80_select(void *s, const char *what) "[%p] %sselect"
+m25p80_page_program(void *s, uint32_t addr, uint8_t tx) "[%p] page program cur_addr=0x%"PRIx32" data=0x%"PRIx8
+m25p80_transfer(void *s, uint8_t state, uint32_t len, uint8_t needed, uint32_t pos, uint32_t cur_addr, uint8_t t) "[%p] Transfer state 0x%"PRIx8" len 0x%"PRIx32" needed 0x%"PRIx8" pos 0x%"PRIx32" addr 0x%"PRIx32" tx 0x%"PRIx8
+m25p80_read_byte(void *s, uint32_t addr, uint8_t v) "[%p] Read byte 0x%"PRIx32"=0x%"PRIx8
+m25p80_read_data(void *s, uint32_t pos, uint8_t v) "[%p] Read data 0x%"PRIx32"=0x%"PRIx8
+m25p80_binding(void *s) "[%p] Binding to IF_MTD drive"
+m25p80_binding_no_bdrv(void *s) "[%p] No BDRV - binding to RAM"
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

When requesting JEDEC data using the JEDEC_READ command, the Linux kernel
always requests 6 bytes. The current implementation only returns three
bytes, and interprets the remaining three bytes as new commands.
While this does not matter most of the time, it is at the very least
confusing. To avoid the problem, always report up to 6 bytes of JEDEC
data. Fill remaining data with 0.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/block/m25p80.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
         for (i = 0; i < s->pi->id_len; i++) {
             s->data[i] = s->pi->id[i];
         }
+        for (; i < SPI_NOR_MAX_ID_LEN; i++) {
+            s->data[i] = 0;
+        }
 
-        s->len = s->pi->id_len;
+        s->len = SPI_NOR_MAX_ID_LEN;
         s->pos = 0;
         s->state = STATE_READING_DATA;
         break;
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

Whenever an unsupported command is encountered, the current code
interprets each transferred byte as new command. Most of the time, those
'commands' are interpreted as new unknown commands. However, in rare
cases, it may be that for example address or length information
passed with the original command is by itself a valid command.
If that happens, the state machine may get completely confused and,
worst case, start writing data into the flash or even erase it.

To avoid the problem, transition into STATE_READING_DATA and keep
sending a value of 0 until the chip is deselected after encountering
an unsupported command.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/block/m25p80.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -XXX,XX +XXX,XX @@ static void decode_new_cmd(Flash *s, uint32_t value)
         s->quad_enable = false;
         break;
     default:
+        s->pos = 0;
+        s->len = 1;
+        s->state = STATE_READING_DATA;
+        s->data_read_loop = true;
+        s->data[0] = 0;
         qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
         break;
     }
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

The Linux kernel recently started using FAST_READ_4 commands.
This results in flash read failures. At the same time, the m25p80
emulation is seen to read 8 more bytes than expected. Adjusting the
expected number of dummy cycles to match FAST_READ fixes the problem.

Fixes: f95c4bffdc4c ("aspeed/smc: snoop SPI transfers to fake dummy cycles")
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/aspeed_smc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -XXX,XX +XXX,XX @@ static int aspeed_smc_num_dummies(uint8_t command)
     case FAST_READ:
     case DOR:
     case QOR:
+    case FAST_READ_4:
     case DOR_4:
     case QOR_4:
         return 1;
     case DIOR:
-    case FAST_READ_4:
     case DIOR_4:
         return 2;
     case QIOR:
-- 
2.20.1

First arm pullreq for 7.1. The bulk of this is the qemu_split_irq
removal.

I have enough stuff in my to-review queue that I expect to do another
pullreq early next week, but 31 patches is enough to not hang on to.

thanks
-- PMM

The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b:

Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging (2022-04-20 16:43:11 -0700)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220421

for you to fetch changes up to 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6:

hw/arm: Use bit fields for NPCM7XX PWRON STRAPs (2022-04-21 11:37:05 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
 * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
 * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s
 * xlnx-zynqmp: Connect 4 TTC timers
 * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq
 * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
 * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
 * hw/core/irq: remove unused 'qemu_irq_split' function
 * npcm7xx: use symbolic constants for PWRON STRAP bit fields
 * virt: document impact of gic-version on max CPUs

----------------------------------------------------------------
Edgar E. Iglesias (6):
      timer: cadence_ttc: Break out header file to allow embedding
      hw/arm/xlnx-zynqmp: Connect 4 TTC timers
      hw/arm: versal: Create an APU CPU Cluster
      hw/arm: versal: Add the Cortex-R5Fs
      hw/misc: Add a model of the Xilinx Versal CRL
      hw/arm: versal: Connect the CRL

Hao Wu (2):
      hw/misc: Add PWRON STRAP bit fields in GCR module
      hw/arm: Use bit fields for NPCM7XX PWRON STRAPs

Heinrich Schuchardt (1):
      hw/arm/virt: impact of gic-version on max CPUs

Peter Maydell (19):
      hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
      hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device
      hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
      hw/arm/exynos4210: Put a9mpcore device into state struct
      hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct
      hw/arm/exynos4210: Coalesce board_irqs and irq_table
      hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
      hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
      hw/arm/exynos4210: Put external GIC into state struct
      hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
      hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c
      hw/arm/exynos4210: Delete unused macro definitions
      hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
      hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines
      hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
      hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
      hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
      hw/arm/exynos4210: Put combiners into state struct
      hw/arm/exynos4210: Drop Exynos4210Irq struct

Zongyuan Li (3):
      hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
      hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
      hw/core/irq: remove unused 'qemu_irq_split' function

docs/system/arm/virt.rst              |   4 +-
 include/hw/arm/exynos4210.h           |  50 ++--
 include/hw/arm/xlnx-versal.h          |  16 ++
 include/hw/arm/xlnx-zynqmp.h          |   4 +
 include/hw/intc/exynos4210_combiner.h |  57 +++++
 include/hw/intc/exynos4210_gic.h      |  43 ++++
 include/hw/irq.h                      |   5 -
 include/hw/misc/npcm7xx_gcr.h         |  30 +++
 include/hw/misc/xlnx-versal-crl.h     | 235 +++++++++++++++++++
 include/hw/timer/cadence_ttc.h        |  54 +++++
 hw/arm/exynos4210.c                   | 430 ++++++++++++++++++++++++++++++----
 hw/arm/npcm7xx_boards.c               |  24 +-
 hw/arm/realview.c                     |  33 ++-
 hw/arm/stellaris.c                    |  15 +-
 hw/arm/virt.c                         |   7 +
 hw/arm/xlnx-versal-virt.c             |   6 +-
 hw/arm/xlnx-versal.c                  |  99 +++++++-
 hw/arm/xlnx-zynqmp.c                  |  22 ++
 hw/core/irq.c                         |  15 --
 hw/intc/exynos4210_combiner.c         | 108 +--------
 hw/intc/exynos4210_gic.c              | 344 +--------------------------
 hw/misc/xlnx-versal-crl.c             | 421 +++++++++++++++++++++++++++++++++
 hw/timer/cadence_ttc.c                |  32 +--
 MAINTAINERS                           |   2 +-
 hw/misc/meson.build                   |   1 +
 25 files changed, 1457 insertions(+), 600 deletions(-)
 create mode 100644 include/hw/intc/exynos4210_combiner.h
 create mode 100644 include/hw/intc/exynos4210_gic.h
 create mode 100644 include/hw/misc/xlnx-versal-crl.h
 create mode 100644 include/hw/timer/cadence_ttc.h
 create mode 100644 hw/misc/xlnx-versal-crl.c

It's not possible to provide the guest with the Security extensions
(TrustZone) when using KVM or HVF, because the hardware
virtualization extensions don't permit running EL3 guest code.
However, we weren't checking for this combination, with the result
that QEMU would assert if you tried it:

$ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none
Unexpected error in object_property_find_err() at ../../qom/object.c:1304:
qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found
Aborted

Check for this combination of options and report an error, in the
same way we already do for attempts to give a KVM or HVF guest the
Virtualization or MTE extensions. Now we will report:

qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404155301.566542-1-peter.maydell@linaro.org
---
 hw/arm/virt.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
         exit(1);
     }
 
+    if (vms->secure && (kvm_enabled() || hvf_enabled())) {
+        error_report("mach-virt: %s does not support providing "
+                     "Security extensions (TrustZone) to the guest CPU",
+                     kvm_enabled() ? "KVM" : "HVF");
+        exit(1);
+    }
+
     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "Virtualization extensions to the guest CPU",
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Break out header file to allow embedding of the the TTC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++
 hw/timer/cadence_ttc.c         | 32 ++------------------
 2 files changed, 56 insertions(+), 30 deletions(-)
 create mode 100644 include/hw/timer/cadence_ttc.h

diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/timer/cadence_ttc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Xilinx Zynq cadence TTC model
+ *
+ * Copyright (c) 2011 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written By Haibing Ma
+ *            M. Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef HW_TIMER_CADENCE_TTC_H
+#define HW_TIMER_CADENCE_TTC_H
+
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+
+typedef struct {
+    QEMUTimer *timer;
+    int freq;
+
+    uint32_t reg_clock;
+    uint32_t reg_count;
+    uint32_t reg_value;
+    uint16_t reg_interval;
+    uint16_t reg_match[3];
+    uint32_t reg_intr;
+    uint32_t reg_intr_en;
+    uint32_t reg_event_ctrl;
+    uint32_t reg_event;
+
+    uint64_t cpu_time;
+    unsigned int cpu_time_valid;
+
+    qemu_irq irq;
+} CadenceTimerState;
+
+#define TYPE_CADENCE_TTC "cadence_ttc"
+OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
+
+struct CadenceTTCState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+    CadenceTimerState timer[3];
+};
+
+#endif
diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/cadence_ttc.c
+++ b/hw/timer/cadence_ttc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/timer.h"
 #include "qom/object.h"
 
+#include "hw/timer/cadence_ttc.h"
+
 #ifdef CADENCE_TTC_ERR_DEBUG
 #define DB_PRINT(...) do { \
     fprintf(stderr,  ": %s: ", __func__); \
@@ -XXX,XX +XXX,XX @@
 #define CLOCK_CTRL_PS_EN    0x00000001
 #define CLOCK_CTRL_PS_V     0x0000001e
 
-typedef struct {
-    QEMUTimer *timer;
-    int freq;
-
-    uint32_t reg_clock;
-    uint32_t reg_count;
-    uint32_t reg_value;
-    uint16_t reg_interval;
-    uint16_t reg_match[3];
-    uint32_t reg_intr;
-    uint32_t reg_intr_en;
-    uint32_t reg_event_ctrl;
-    uint32_t reg_event;
-
-    uint64_t cpu_time;
-    unsigned int cpu_time_valid;
-
-    qemu_irq irq;
-} CadenceTimerState;
-
-#define TYPE_CADENCE_TTC "cadence_ttc"
-OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
-
-struct CadenceTTCState {
-    SysBusDevice parent_obj;
-
-    MemoryRegion iomem;
-    CadenceTimerState timer[3];
-};
-
 static void cadence_timer_update(CadenceTimerState *s)
 {
     qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Connect the 4 TTC timers on the ZynqMP.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-zynqmp.h |  4 ++++
 hw/arm/xlnx-zynqmp.c         | 22 ++++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/or-irq.h"
 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
 #include "hw/misc/xlnx-zynqmp-crf.h"
+#include "hw/timer/cadence_ttc.h"
 
 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
                                   XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
 
+#define XLNX_ZYNQMP_NUM_TTC 4
+
 /*
  * Unimplemented mmio regions needed to boot some images.
  */
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
     qemu_or_irq qspi_irq_orgate;
     XlnxZynqMPAPUCtrl apu_ctrl;
     XlnxZynqMPCRF crf;
+    CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
 
     char *boot_cpu;
     ARMCPU *boot_cpu_ptr;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@
 #define APU_ADDR            0xfd5c0000
 #define APU_IRQ             153
 
+#define TTC0_ADDR           0xFF110000
+#define TTC0_IRQ            36
+
 #define IPI_ADDR            0xFF300000
 #define IPI_IRQ             64
 
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
     sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
 }
 
+static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
+{
+    SysBusDevice *sbd;
+    int i, irq;
+
+    for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
+        object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
+                                TYPE_CADENCE_TTC);
+        sbd = SYS_BUS_DEVICE(&s->ttc[i]);
+
+        sysbus_realize(sbd, &error_fatal);
+        sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
+        for (irq = 0; irq < 3; irq++) {
+            sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
+        }
+    }
+}
+
 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
 {
     static const struct UnimpInfo {
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
     xlnx_zynqmp_create_efuse(s, gic_spi);
     xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
     xlnx_zynqmp_create_crf(s, gic_spi);
+    xlnx_zynqmp_create_ttc(s, gic_spi);
     xlnx_zynqmp_create_unimp_mmio(s);
 
     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Create an APU CPU Cluster. This is in preparation to add the RPU.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h | 2 ++
 hw/arm/xlnx-versal.c         | 9 ++++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/sysbus.h"
 #include "hw/arm/boot.h"
+#include "hw/cpu/cluster.h"
 #include "hw/or-irq.h"
 #include "hw/sd/sdhci.h"
 #include "hw/intc/arm_gicv3.h"
@@ -XXX,XX +XXX,XX @@ struct Versal {
     struct {
         struct {
             MemoryRegion mr;
+            CPUClusterState cluster;
             ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
             GICv3State gic;
         } apu;
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
 {
     int i;
 
+    object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster,
+                            TYPE_CPU_CLUSTER);
+    qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0);
+
     for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
         Object *obj;
 
-        object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
+        object_initialize_child(OBJECT(&s->fpd.apu.cluster),
+                                "apu-cpu[*]", &s->fpd.apu.cpu[i],
                                 XLNX_VERSAL_ACPU_TYPE);
         obj = OBJECT(&s->fpd.apu.cpu[i]);
         if (i) {
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
                                  &error_abort);
         qdev_realize(DEVICE(obj), NULL, &error_fatal);
     }
+
+    qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal);
 }
 
 static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit)
subsystem.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h | 10 ++++++++++
 hw/arm/xlnx-versal-virt.c    |  6 +++---
 hw/arm/xlnx-versal.c         | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 49 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
 
 #define XLNX_VERSAL_NR_ACPUS   2
+#define XLNX_VERSAL_NR_RCPUS   2
 #define XLNX_VERSAL_NR_UARTS   2
 #define XLNX_VERSAL_NR_GEMS    2
 #define XLNX_VERSAL_NR_ADMAS   8
@@ -XXX,XX +XXX,XX @@ struct Versal {
             VersalUsb2 usb;
         } iou;
 
+        /* Real-time Processing Unit.  */
+        struct {
+            MemoryRegion mr;
+            MemoryRegion mr_ps_alias;
+
+            CPUClusterState cluster;
+            ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
+        } rpu;
+
         struct {
             qemu_or_irq irq_orgate;
             XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
 
     mc->desc = "Xilinx Versal Virtual development board";
     mc->init = versal_virt_init;
-    mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
-    mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
-    mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
+    mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
+    mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
+    mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
     mc->no_cdrom = true;
     mc->default_ram_id = "ddr";
 }
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 
 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
+#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
 #define GEM_REVISION        0x40070106
 
 #define VERSAL_NUM_PMC_APB_IRQS 3
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
     }
 }
 
+static void versal_create_rpu_cpus(Versal *s)
+{
+    int i;
+
+    object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster,
+                            TYPE_CPU_CLUSTER);
+    qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1);
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
+        Object *obj;
+
+        object_initialize_child(OBJECT(&s->lpd.rpu.cluster),
+                                "rpu-cpu[*]", &s->lpd.rpu.cpu[i],
+                                XLNX_VERSAL_RCPU_TYPE);
+        obj = OBJECT(&s->lpd.rpu.cpu[i]);
+        object_property_set_bool(obj, "start-powered-off", true,
+                                 &error_abort);
+
+        object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort);
+        object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu),
+                                &error_abort);
+        object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr),
+                                 &error_abort);
+        qdev_realize(DEVICE(obj), NULL, &error_fatal);
+    }
+
+    qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal);
+}
+
 static void versal_create_uarts(Versal *s, qemu_irq *pic)
 {
     int i;
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
 
     versal_create_apu_cpus(s);
     versal_create_apu_gic(s, pic);
+    versal_create_rpu_cpus(s);
     versal_create_uarts(s, pic);
     versal_create_usbs(s, pic);
     versal_create_gems(s, pic);
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
 
     memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
     memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
+    memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0,
+                                        &s->lpd.rpu.mr_ps_alias, 0);
 }
 
 static void versal_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void versal_init(Object *obj)
     Versal *s = XLNX_VERSAL(obj);
 
     memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
+    memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX);
     memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
+    memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s),
+                             "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX);
 }
 
 static Property versal_properties[] = {
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Add a model of the Xilinx Versal CRL.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++
 hw/misc/xlnx-versal-crl.c         | 421 ++++++++++++++++++++++++++++++
 hw/misc/meson.build               |   1 +
 3 files changed, 657 insertions(+)
 create mode 100644 include/hw/misc/xlnx-versal-crl.h
 create mode 100644 hw/misc/xlnx-versal-crl.c

diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/xlnx-versal-crl.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU model of the Clock-Reset-LPD (CRL).
+ *
+ * Copyright (c) 2022 Xilinx Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ */
+#ifndef HW_MISC_XLNX_VERSAL_CRL_H
+#define HW_MISC_XLNX_VERSAL_CRL_H
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "target/arm/cpu.h"
+
+#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl"
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
+
+REG32(ERR_CTRL, 0x0)
+    FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
+REG32(IR_STATUS, 0x4)
+    FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_MASK, 0x8)
+    FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_ENABLE, 0xc)
+    FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_DISABLE, 0x10)
+    FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
+REG32(WPROT, 0x1c)
+    FIELD(WPROT, ACTIVE, 0, 1)
+REG32(PLL_CLK_OTHER_DMN, 0x20)
+    FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
+REG32(RPLL_CTRL, 0x40)
+    FIELD(RPLL_CTRL, POST_SRC, 24, 3)
+    FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
+    FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2)
+    FIELD(RPLL_CTRL, FBDIV, 8, 8)
+    FIELD(RPLL_CTRL, BYPASS, 3, 1)
+    FIELD(RPLL_CTRL, RESET, 0, 1)
+REG32(RPLL_CFG, 0x44)
+    FIELD(RPLL_CFG, LOCK_DLY, 25, 7)
+    FIELD(RPLL_CFG, LOCK_CNT, 13, 10)
+    FIELD(RPLL_CFG, LFHF, 10, 2)
+    FIELD(RPLL_CFG, CP, 5, 4)
+    FIELD(RPLL_CFG, RES, 0, 4)
+REG32(RPLL_FRAC_CFG, 0x48)
+    FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1)
+    FIELD(RPLL_FRAC_CFG, SEED, 22, 3)
+    FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1)
+    FIELD(RPLL_FRAC_CFG, ORDER, 18, 1)
+    FIELD(RPLL_FRAC_CFG, DATA, 0, 16)
+REG32(PLL_STATUS, 0x50)
+    FIELD(PLL_STATUS, RPLL_STABLE, 2, 1)
+    FIELD(PLL_STATUS, RPLL_LOCK, 0, 1)
+REG32(RPLL_TO_XPD_CTRL, 0x100)
+    FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1)
+    FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
+REG32(LPD_TOP_SWITCH_CTRL, 0x104)
+    FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
+    FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1)
+    FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
+    FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
+REG32(LPD_LSBUS_CTRL, 0x108)
+    FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1)
+    FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10)
+    FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3)
+REG32(CPU_R5_CTRL, 0x10c)
+    FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1)
+    FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1)
+    FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1)
+    FIELD(CPU_R5_CTRL, CLKACT, 25, 1)
+    FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10)
+    FIELD(CPU_R5_CTRL, SRCSEL, 0, 3)
+REG32(IOU_SWITCH_CTRL, 0x114)
+    FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1)
+    FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10)
+    FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3)
+REG32(GEM0_REF_CTRL, 0x118)
+    FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1)
+    FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1)
+    FIELD(GEM0_REF_CTRL, CLKACT, 25, 1)
+    FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3)
+REG32(GEM1_REF_CTRL, 0x11c)
+    FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1)
+    FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1)
+    FIELD(GEM1_REF_CTRL, CLKACT, 25, 1)
+    FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3)
+REG32(GEM_TSU_REF_CTRL, 0x120)
+    FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1)
+    FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3)
+REG32(USB0_BUS_REF_CTRL, 0x124)
+    FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1)
+    FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3)
+REG32(UART0_REF_CTRL, 0x128)
+    FIELD(UART0_REF_CTRL, CLKACT, 25, 1)
+    FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(UART0_REF_CTRL, SRCSEL, 0, 3)
+REG32(UART1_REF_CTRL, 0x12c)
+    FIELD(UART1_REF_CTRL, CLKACT, 25, 1)
+    FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(UART1_REF_CTRL, SRCSEL, 0, 3)
+REG32(SPI0_REF_CTRL, 0x130)
+    FIELD(SPI0_REF_CTRL, CLKACT, 25, 1)
+    FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3)
+REG32(SPI1_REF_CTRL, 0x134)
+    FIELD(SPI1_REF_CTRL, CLKACT, 25, 1)
+    FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3)
+REG32(CAN0_REF_CTRL, 0x138)
+    FIELD(CAN0_REF_CTRL, CLKACT, 25, 1)
+    FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3)
+REG32(CAN1_REF_CTRL, 0x13c)
+    FIELD(CAN1_REF_CTRL, CLKACT, 25, 1)
+    FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3)
+REG32(I2C0_REF_CTRL, 0x140)
+    FIELD(I2C0_REF_CTRL, CLKACT, 25, 1)
+    FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3)
+REG32(I2C1_REF_CTRL, 0x144)
+    FIELD(I2C1_REF_CTRL, CLKACT, 25, 1)
+    FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3)
+REG32(DBG_LPD_CTRL, 0x148)
+    FIELD(DBG_LPD_CTRL, CLKACT, 25, 1)
+    FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10)
+    FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3)
+REG32(TIMESTAMP_REF_CTRL, 0x14c)
+    FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
+    FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
+REG32(CRL_SAFETY_CHK, 0x150)
+REG32(PSM_REF_CTRL, 0x154)
+    FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(PSM_REF_CTRL, SRCSEL, 0, 3)
+REG32(DBG_TSTMP_CTRL, 0x158)
+    FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1)
+    FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10)
+    FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
+REG32(CPM_TOPSW_REF_CTRL, 0x15c)
+    FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1)
+    FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3)
+REG32(USB3_DUAL_REF_CTRL, 0x160)
+    FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1)
+    FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3)
+REG32(RST_CPU_R5, 0x300)
+    FIELD(RST_CPU_R5, RESET_PGE, 4, 1)
+    FIELD(RST_CPU_R5, RESET_AMBA, 2, 1)
+    FIELD(RST_CPU_R5, RESET_CPU1, 1, 1)
+    FIELD(RST_CPU_R5, RESET_CPU0, 0, 1)
+REG32(RST_ADMA, 0x304)
+    FIELD(RST_ADMA, RESET, 0, 1)
+REG32(RST_GEM0, 0x308)
+    FIELD(RST_GEM0, RESET, 0, 1)
+REG32(RST_GEM1, 0x30c)
+    FIELD(RST_GEM1, RESET, 0, 1)
+REG32(RST_SPARE, 0x310)
+    FIELD(RST_SPARE, RESET, 0, 1)
+REG32(RST_USB0, 0x314)
+    FIELD(RST_USB0, RESET, 0, 1)
+REG32(RST_UART0, 0x318)
+    FIELD(RST_UART0, RESET, 0, 1)
+REG32(RST_UART1, 0x31c)
+    FIELD(RST_UART1, RESET, 0, 1)
+REG32(RST_SPI0, 0x320)
+    FIELD(RST_SPI0, RESET, 0, 1)
+REG32(RST_SPI1, 0x324)
+    FIELD(RST_SPI1, RESET, 0, 1)
+REG32(RST_CAN0, 0x328)
+    FIELD(RST_CAN0, RESET, 0, 1)
+REG32(RST_CAN1, 0x32c)
+    FIELD(RST_CAN1, RESET, 0, 1)
+REG32(RST_I2C0, 0x330)
+    FIELD(RST_I2C0, RESET, 0, 1)
+REG32(RST_I2C1, 0x334)
+    FIELD(RST_I2C1, RESET, 0, 1)
+REG32(RST_DBG_LPD, 0x338)
+    FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1)
+    FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1)
+    FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1)
+    FIELD(RST_DBG_LPD, RESET, 0, 1)
+REG32(RST_GPIO, 0x33c)
+    FIELD(RST_GPIO, RESET, 0, 1)
+REG32(RST_TTC, 0x344)
+    FIELD(RST_TTC, TTC3_RESET, 3, 1)
+    FIELD(RST_TTC, TTC2_RESET, 2, 1)
+    FIELD(RST_TTC, TTC1_RESET, 1, 1)
+    FIELD(RST_TTC, TTC0_RESET, 0, 1)
+REG32(RST_TIMESTAMP, 0x348)
+    FIELD(RST_TIMESTAMP, RESET, 0, 1)
+REG32(RST_SWDT, 0x34c)
+    FIELD(RST_SWDT, RESET, 0, 1)
+REG32(RST_OCM, 0x350)
+    FIELD(RST_OCM, RESET, 0, 1)
+REG32(RST_IPI, 0x354)
+    FIELD(RST_IPI, RESET, 0, 1)
+REG32(RST_SYSMON, 0x358)
+    FIELD(RST_SYSMON, SEQ_RST, 1, 1)
+    FIELD(RST_SYSMON, CFG_RST, 0, 1)
+REG32(RST_FPD, 0x360)
+    FIELD(RST_FPD, SRST, 1, 1)
+    FIELD(RST_FPD, POR, 0, 1)
+REG32(PSM_RST_MODE, 0x370)
+    FIELD(PSM_RST_MODE, WAKEUP, 2, 1)
+    FIELD(PSM_RST_MODE, RST_MODE, 0, 2)
+
+#define CRL_R_MAX (R_PSM_RST_MODE + 1)
+
+#define RPU_MAX_CPU 2
+
+struct XlnxVersalCRL {
+    SysBusDevice parent_obj;
+    qemu_irq irq;
+
+    struct {
+        ARMCPU *cpu_r5[RPU_MAX_CPU];
+        DeviceState *adma[8];
+        DeviceState *uart[2];
+        DeviceState *gem[2];
+        DeviceState *usb;
+    } cfg;
+
+    RegisterInfoArray *reg_array;
+    uint32_t regs[CRL_R_MAX];
+    RegisterInfo regs_info[CRL_R_MAX];
+};
+#endif
diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/xlnx-versal-crl.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU model of the Clock-Reset-LPD (CRL).
+ *
+ * Copyright (c) 2022 Advanced Micro Devices, Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Edgar E. Iglesias <edgar.iglesias@amd.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/bitops.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/register.h"
+#include "hw/resettable.h"
+
+#include "target/arm/arm-powerctl.h"
+#include "hw/misc/xlnx-versal-crl.h"
+
+#ifndef XLNX_VERSAL_CRL_ERR_DEBUG
+#define XLNX_VERSAL_CRL_ERR_DEBUG 0
+#endif
+
+static void crl_update_irq(XlnxVersalCRL *s)
+{
+    bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
+    qemu_set_irq(s->irq, pending);
+}
+
+static void crl_status_postw(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+    crl_update_irq(s);
+}
+
+static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+    uint32_t val = val64;
+
+    s->regs[R_IR_MASK] &= ~val;
+    crl_update_irq(s);
+    return 0;
+}
+
+static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+    uint32_t val = val64;
+
+    s->regs[R_IR_MASK] |= val;
+    crl_update_irq(s);
+    return 0;
+}
+
+static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev,
+                          bool rst_old, bool rst_new)
+{
+    device_cold_reset(dev);
+}
+
+static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu,
+                          bool rst_old, bool rst_new)
+{
+    if (rst_new) {
+        arm_set_cpu_off(armcpu->mp_affinity);
+    } else {
+        arm_set_cpu_on_and_reset(armcpu->mp_affinity);
+    }
+}
+
+#define REGFIELD_RESET(type, s, reg, f, new_val, dev) {     \
+    bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f);       \
+    bool new_f = FIELD_EX32(new_val, reg, f);               \
+                                                            \
+    /* Detect edges.  */                                    \
+    if (dev && old_f != new_f) {                            \
+        crl_reset_ ## type(s, dev, old_f, new_f);           \
+    }                                                       \
+}
+
+static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]);
+    REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]);
+    return val64;
+}
+
+static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+    int i;
+
+    /* A single register fans out to all ADMA reset inputs.  */
+    for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) {
+        REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]);
+    }
+    return val64;
+}
+
+static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]);
+    return val64;
+}
+
+static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]);
+    return val64;
+}
+
+static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]);
+    return val64;
+}
+
+static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]);
+    return val64;
+}
+
+static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb);
+    return val64;
+}
+
+static const RegisterAccessInfo crl_regs_info[] = {
+    {   .name = "ERR_CTRL",  .addr = A_ERR_CTRL,
+    },{ .name = "IR_STATUS",  .addr = A_IR_STATUS,
+        .w1c = 0x1,
+        .post_write = crl_status_postw,
+    },{ .name = "IR_MASK",  .addr = A_IR_MASK,
+        .reset = 0x1,
+        .ro = 0x1,
+    },{ .name = "IR_ENABLE",  .addr = A_IR_ENABLE,
+        .pre_write = crl_enable_prew,
+    },{ .name = "IR_DISABLE",  .addr = A_IR_DISABLE,
+        .pre_write = crl_disable_prew,
+    },{ .name = "WPROT",  .addr = A_WPROT,
+    },{ .name = "PLL_CLK_OTHER_DMN",  .addr = A_PLL_CLK_OTHER_DMN,
+        .reset = 0x1,
+        .rsvd = 0xe,
+    },{ .name = "RPLL_CTRL",  .addr = A_RPLL_CTRL,
+        .reset = 0x24809,
+        .rsvd = 0xf88c00f6,
+    },{ .name = "RPLL_CFG",  .addr = A_RPLL_CFG,
+        .reset = 0x2000000,
+        .rsvd = 0x1801210,
+    },{ .name = "RPLL_FRAC_CFG",  .addr = A_RPLL_FRAC_CFG,
+        .rsvd = 0x7e330000,
+    },{ .name = "PLL_STATUS",  .addr = A_PLL_STATUS,
+        .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
+                 R_PLL_STATUS_RPLL_LOCK_MASK,
+        .rsvd = 0xfa,
+        .ro = 0x5,
+    },{ .name = "RPLL_TO_XPD_CTRL",  .addr = A_RPLL_TO_XPD_CTRL,
+        .reset = 0x2000100,
+        .rsvd = 0xfdfc00ff,
+    },{ .name = "LPD_TOP_SWITCH_CTRL",  .addr = A_LPD_TOP_SWITCH_CTRL,
+        .reset = 0x6000300,
+        .rsvd = 0xf9fc00f8,
+    },{ .name = "LPD_LSBUS_CTRL",  .addr = A_LPD_LSBUS_CTRL,
+        .reset = 0x2000800,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "CPU_R5_CTRL",  .addr = A_CPU_R5_CTRL,
+        .reset = 0xe000300,
+        .rsvd = 0xe1fc00f8,
+    },{ .name = "IOU_SWITCH_CTRL",  .addr = A_IOU_SWITCH_CTRL,
+        .reset = 0x2000500,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "GEM0_REF_CTRL",  .addr = A_GEM0_REF_CTRL,
+        .reset = 0xe000a00,
+        .rsvd = 0xf1fc00f8,
+    },{ .name = "GEM1_REF_CTRL",  .addr = A_GEM1_REF_CTRL,
+        .reset = 0xe000a00,
+        .rsvd = 0xf1fc00f8,
+    },{ .name = "GEM_TSU_REF_CTRL",  .addr = A_GEM_TSU_REF_CTRL,
+        .reset = 0x300,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "USB0_BUS_REF_CTRL",  .addr = A_USB0_BUS_REF_CTRL,
+        .reset = 0x2001900,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "UART0_REF_CTRL",  .addr = A_UART0_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "UART1_REF_CTRL",  .addr = A_UART1_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "SPI0_REF_CTRL",  .addr = A_SPI0_REF_CTRL,
+        .reset = 0x600,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "SPI1_REF_CTRL",  .addr = A_SPI1_REF_CTRL,
+        .reset = 0x600,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "CAN0_REF_CTRL",  .addr = A_CAN0_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "CAN1_REF_CTRL",  .addr = A_CAN1_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "I2C0_REF_CTRL",  .addr = A_I2C0_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "I2C1_REF_CTRL",  .addr = A_I2C1_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "DBG_LPD_CTRL",  .addr = A_DBG_LPD_CTRL,
+        .reset = 0x300,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "TIMESTAMP_REF_CTRL",  .addr = A_TIMESTAMP_REF_CTRL,
+        .reset = 0x2000c00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "CRL_SAFETY_CHK",  .addr = A_CRL_SAFETY_CHK,
+    },{ .name = "PSM_REF_CTRL",  .addr = A_PSM_REF_CTRL,
+        .reset = 0xf04,
+        .rsvd = 0xfffc00f8,
+    },{ .name = "DBG_TSTMP_CTRL",  .addr = A_DBG_TSTMP_CTRL,
+        .reset = 0x300,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "CPM_TOPSW_REF_CTRL",  .addr = A_CPM_TOPSW_REF_CTRL,
+        .reset = 0x300,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "USB3_DUAL_REF_CTRL",  .addr = A_USB3_DUAL_REF_CTRL,
+        .reset = 0x3c00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "RST_CPU_R5",  .addr = A_RST_CPU_R5,
+        .reset = 0x17,
+        .rsvd = 0x8,
+        .pre_write = crl_rst_r5_prew,
+    },{ .name = "RST_ADMA",  .addr = A_RST_ADMA,
+        .reset = 0x1,
+        .pre_write = crl_rst_adma_prew,
+    },{ .name = "RST_GEM0",  .addr = A_RST_GEM0,
+        .reset = 0x1,
+        .pre_write = crl_rst_gem0_prew,
+    },{ .name = "RST_GEM1",  .addr = A_RST_GEM1,
+        .reset = 0x1,
+        .pre_write = crl_rst_gem1_prew,
+    },{ .name = "RST_SPARE",  .addr = A_RST_SPARE,
+        .reset = 0x1,
+    },{ .name = "RST_USB0",  .addr = A_RST_USB0,
+        .reset = 0x1,
+        .pre_write = crl_rst_usb_prew,
+    },{ .name = "RST_UART0",  .addr = A_RST_UART0,
+        .reset = 0x1,
+        .pre_write = crl_rst_uart0_prew,
+    },{ .name = "RST_UART1",  .addr = A_RST_UART1,
+        .reset = 0x1,
+        .pre_write = crl_rst_uart1_prew,
+    },{ .name = "RST_SPI0",  .addr = A_RST_SPI0,
+        .reset = 0x1,
+    },{ .name = "RST_SPI1",  .addr = A_RST_SPI1,
+        .reset = 0x1,
+    },{ .name = "RST_CAN0",  .addr = A_RST_CAN0,
+        .reset = 0x1,
+    },{ .name = "RST_CAN1",  .addr = A_RST_CAN1,
+        .reset = 0x1,
+    },{ .name = "RST_I2C0",  .addr = A_RST_I2C0,
+        .reset = 0x1,
+    },{ .name = "RST_I2C1",  .addr = A_RST_I2C1,
+        .reset = 0x1,
+    },{ .name = "RST_DBG_LPD",  .addr = A_RST_DBG_LPD,
+        .reset = 0x33,
+        .rsvd = 0xcc,
+    },{ .name = "RST_GPIO",  .addr = A_RST_GPIO,
+        .reset = 0x1,
+    },{ .name = "RST_TTC",  .addr = A_RST_TTC,
+        .reset = 0xf,
+    },{ .name = "RST_TIMESTAMP",  .addr = A_RST_TIMESTAMP,
+        .reset = 0x1,
+    },{ .name = "RST_SWDT",  .addr = A_RST_SWDT,
+        .reset = 0x1,
+    },{ .name = "RST_OCM",  .addr = A_RST_OCM,
+    },{ .name = "RST_IPI",  .addr = A_RST_IPI,
+    },{ .name = "RST_FPD",  .addr = A_RST_FPD,
+        .reset = 0x3,
+    },{ .name = "PSM_RST_MODE",  .addr = A_PSM_RST_MODE,
+        .reset = 0x1,
+        .rsvd = 0xf8,
+    }
+};
+
+static void crl_reset_enter(Object *obj, ResetType type)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+    unsigned int i;
+
+    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+        register_reset(&s->regs_info[i]);
+    }
+}
+
+static void crl_reset_hold(Object *obj)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+
+    crl_update_irq(s);
+}
+
+static const MemoryRegionOps crl_ops = {
+    .read = register_read_memory,
+    .write = register_write_memory,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+static void crl_init(Object *obj)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    int i;
+
+    s->reg_array =
+        register_init_block32(DEVICE(obj), crl_regs_info,
+                              ARRAY_SIZE(crl_regs_info),
+                              s->regs_info, s->regs,
+                              &crl_ops,
+                              XLNX_VERSAL_CRL_ERR_DEBUG,
+                              CRL_R_MAX * 4);
+    sysbus_init_mmio(sbd, &s->reg_array->mem);
+    sysbus_init_irq(sbd, &s->irq);
+
+    for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) {
+        object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU,
+                                 (Object **)&s->cfg.cpu_r5[i],
+                                 qdev_prop_allow_set_link_before_realize,
+                                 OBJ_PROP_LINK_STRONG);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) {
+        object_property_add_link(obj, "adma[*]", TYPE_DEVICE,
+                                 (Object **)&s->cfg.adma[i],
+                                 qdev_prop_allow_set_link_before_realize,
+                                 OBJ_PROP_LINK_STRONG);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) {
+        object_property_add_link(obj, "uart[*]", TYPE_DEVICE,
+                                 (Object **)&s->cfg.uart[i],
+                                 qdev_prop_allow_set_link_before_realize,
+                                 OBJ_PROP_LINK_STRONG);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) {
+        object_property_add_link(obj, "gem[*]", TYPE_DEVICE,
+                                 (Object **)&s->cfg.gem[i],
+                                 qdev_prop_allow_set_link_before_realize,
+                                 OBJ_PROP_LINK_STRONG);
+    }
+
+    object_property_add_link(obj, "usb", TYPE_DEVICE,
+                             (Object **)&s->cfg.gem[i],
+                             qdev_prop_allow_set_link_before_realize,
+                             OBJ_PROP_LINK_STRONG);
+}
+
+static void crl_finalize(Object *obj)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+    register_finalize_block(s->reg_array);
+}
+
+static const VMStateDescription vmstate_crl = {
+    .name = TYPE_XLNX_VERSAL_CRL,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX),
+        VMSTATE_END_OF_LIST(),
+    }
+};
+
+static void crl_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->vmsd = &vmstate_crl;
+
+    rc->phases.enter = crl_reset_enter;
+    rc->phases.hold = crl_reset_hold;
+}
+
+static const TypeInfo crl_info = {
+    .name          = TYPE_XLNX_VERSAL_CRL,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(XlnxVersalCRL),
+    .class_init    = crl_class_init,
+    .instance_init = crl_init,
+    .instance_finalize = crl_finalize,
+};
+
+static void crl_register_types(void)
+{
+    type_register_static(&crl_info);
+}
+
+type_init(crl_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
 softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
 specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
 specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
+specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
 softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
   'xlnx-versal-xramc.c',
   'xlnx-versal-pmc-iou-slcr.c',
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Connect the CRL (Clock Reset LPD) to the Versal SoC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  4 +++
 hw/arm/xlnx-versal.c         | 54 ++++++++++++++++++++++++++++++++++--
 2 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/nvram/xlnx-versal-efuse.h"
 #include "hw/ssi/xlnx-versal-ospi.h"
 #include "hw/dma/xlnx_csu_dma.h"
+#include "hw/misc/xlnx-versal-crl.h"
 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
@@ -XXX,XX +XXX,XX @@ struct Versal {
             qemu_or_irq irq_orgate;
             XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
         } xram;
+
+        XlnxVersalCRL crl;
     } lpd;
 
     /* The Platform Management Controller subsystem.  */
@@ -XXX,XX +XXX,XX @@ struct Versal {
 #define VERSAL_TIMER_NS_EL1_IRQ     14
 #define VERSAL_TIMER_NS_EL2_IRQ     10
 
+#define VERSAL_CRL_IRQ             10
 #define VERSAL_UART0_IRQ_0         18
 #define VERSAL_UART1_IRQ_0         19
 #define VERSAL_USB0_IRQ_0          22
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_ospi(Versal *s, qemu_irq *pic)
     qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
 }
 
+static void versal_create_crl(Versal *s, qemu_irq *pic)
+{
+    SysBusDevice *sbd;
+    int i;
+
+    object_initialize_child(OBJECT(s), "crl", &s->lpd.crl,
+                            TYPE_XLNX_VERSAL_CRL);
+    sbd = SYS_BUS_DEVICE(&s->lpd.crl);
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
+        g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i);
+
+        object_property_set_link(OBJECT(&s->lpd.crl),
+                                 name, OBJECT(&s->lpd.rpu.cpu[i]),
+                                 &error_abort);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
+        g_autofree gchar *name = g_strdup_printf("gem[%d]", i);
+
+        object_property_set_link(OBJECT(&s->lpd.crl),
+                                 name, OBJECT(&s->lpd.iou.gem[i]),
+                                 &error_abort);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
+        g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
+
+        object_property_set_link(OBJECT(&s->lpd.crl),
+                                 name, OBJECT(&s->lpd.iou.adma[i]),
+                                 &error_abort);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
+        g_autofree gchar *name = g_strdup_printf("uart[%d]", i);
+
+        object_property_set_link(OBJECT(&s->lpd.crl),
+                                 name, OBJECT(&s->lpd.iou.uart[i]),
+                                 &error_abort);
+    }
+
+    object_property_set_link(OBJECT(&s->lpd.crl),
+                             "usb", OBJECT(&s->lpd.iou.usb),
+                             &error_abort);
+
+    sysbus_realize(sbd, &error_fatal);
+    memory_region_add_subregion(&s->mr_ps, MM_CRL,
+                                sysbus_mmio_get_region(sbd, 0));
+    sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]);
+}
+
 /* This takes the board allocated linear DDR memory and creates aliases
  * for each split DDR range/aperture on the Versal address map.
  */
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
 
     versal_unimp_area(s, "psm", &s->mr_ps,
                         MM_PSM_START, MM_PSM_END - MM_PSM_START);
-    versal_unimp_area(s, "crl", &s->mr_ps,
-                        MM_CRL, MM_CRL_SIZE);
     versal_unimp_area(s, "crf", &s->mr_ps,
                         MM_FPD_CRF, MM_FPD_CRF_SIZE);
     versal_unimp_area(s, "apu", &s->mr_ps,
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_efuse(s, pic);
     versal_create_pmc_iou_slcr(s, pic);
     versal_create_ospi(s, pic);
+    versal_create_crl(s, pic);
     versal_map_ddr(s);
     versal_unimp(s);
 
-- 
2.25.1

The Exynos4210 SoC device currently uses a custom device
"exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ
line.  We have a standard TYPE_OR_IRQ device for this now, so use
that instead.

(This is a migration compatibility break, but that is OK for this
machine type.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-2-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  1 +
 hw/arm/exynos4210.c         | 31 ++++++++++++++++---------------
 2 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     MemoryRegion bootreg_mem;
     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
+    qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
 };
 
 #define TYPE_EXYNOS4210_SOC "exynos4210"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
 {
     Exynos4210State *s = EXYNOS4210_SOC(socdev);
     MemoryRegion *system_mem = get_system_memory();
-    qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
     SysBusDevice *busdev;
     DeviceState *dev, *uart[4], *pl330[3];
     int i, n;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
 
     /* IRQ Gate */
     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
-        dev = qdev_new("exynos4210.irq_gate");
-        qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
-        sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-        /* Get IRQ Gate input in gate_irq */
-        for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
-            gate_irq[i][n] = qdev_get_gpio_in(dev, n);
-        }
-        busdev = SYS_BUS_DEVICE(dev);
-
-        /* Connect IRQ Gate output to CPU's IRQ line */
-        sysbus_connect_irq(busdev, 0,
-                           qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
+        DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
+        object_property_set_int(OBJECT(orgate), "num-lines",
+                                EXYNOS4210_IRQ_GATE_NINPUTS,
+                                &error_abort);
+        qdev_realize(orgate, NULL, &error_abort);
+        qdev_connect_gpio_out(orgate, 0,
+                              qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
     }
 
     /* Private memory region and Internal GIC */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     sysbus_realize_and_unref(busdev, &error_fatal);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
-        sysbus_connect_irq(busdev, n, gate_irq[n][0]);
+        sysbus_connect_irq(busdev, n,
+                           qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
     }
     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
         s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     /* Map Distributer interface */
     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
-        sysbus_connect_irq(busdev, n, gate_irq[n][1]);
+        sysbus_connect_irq(busdev, n,
+                           qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
     }
     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
         object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
         g_free(name);
     }
+
+    for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
+        g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
+        object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
+    }
 }
 
 static void exynos4210_class_init(ObjectClass *klass, void *data)
-- 
2.25.1

Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can
delete the device entirely.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220404154658.565020-3-peter.maydell@linaro.org
---
 hw/intc/exynos4210_gic.c | 107 ---------------------------------------
 1 file changed, 107 deletions(-)

diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_register_types(void)
 }
 
 type_init(exynos4210_gic_register_types)
-
-/* IRQ OR Gate struct.
- *
- * This device models an OR gate. There are n_in input qdev gpio lines and one
- * output sysbus IRQ line. The output IRQ level is formed as OR between all
- * gpio inputs.
- */
-
-#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE)
-
-struct Exynos4210IRQGateState {
-    SysBusDevice parent_obj;
-
-    uint32_t n_in;      /* inputs amount */
-    uint32_t *level;    /* input levels */
-    qemu_irq out;       /* output IRQ */
-};
-
-static Property exynos4210_irq_gate_properties[] = {
-    DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
-static const VMStateDescription vmstate_exynos4210_irq_gate = {
-    .name = "exynos4210.irq_gate",
-    .version_id = 2,
-    .minimum_version_id = 2,
-    .fields = (VMStateField[]) {
-        VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in),
-        VMSTATE_END_OF_LIST()
-    }
-};
-
-/* Process a change in IRQ input. */
-static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
-{
-    Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque;
-    uint32_t i;
-
-    assert(irq < s->n_in);
-
-    s->level[irq] = level;
-
-    for (i = 0; i < s->n_in; i++) {
-        if (s->level[i] >= 1) {
-            qemu_irq_raise(s->out);
-            return;
-        }
-    }
-
-    qemu_irq_lower(s->out);
-}
-
-static void exynos4210_irq_gate_reset(DeviceState *d)
-{
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);
-
-    memset(s->level, 0, s->n_in * sizeof(*s->level));
-}
-
-/*
- * IRQ Gate initialization.
- */
-static void exynos4210_irq_gate_init(Object *obj)
-{
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj);
-    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-
-    sysbus_init_irq(sbd, &s->out);
-}
-
-static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp)
-{
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);
-
-    /* Allocate general purpose input signals and connect a handler to each of
-     * them */
-    qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);
-
-    s->level = g_malloc0(s->n_in * sizeof(*s->level));
-}
-
-static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-
-    dc->reset = exynos4210_irq_gate_reset;
-    dc->vmsd = &vmstate_exynos4210_irq_gate;
-    device_class_set_props(dc, exynos4210_irq_gate_properties);
-    dc->realize = exynos4210_irq_gate_realize;
-}
-
-static const TypeInfo exynos4210_irq_gate_info = {
-    .name          = TYPE_EXYNOS4210_IRQ_GATE,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(Exynos4210IRQGateState),
-    .instance_init = exynos4210_irq_gate_init,
-    .class_init    = exynos4210_irq_gate_class_init,
-};
-
-static void exynos4210_irq_gate_register_types(void)
-{
-    type_register_static(&exynos4210_irq_gate_info);
-}
-
-type_init(exynos4210_irq_gate_register_types)
-- 
2.25.1

The exynos4210 SoC mostly creates its child devices as if it were
board code.  This includes the a9mpcore object.  Switch that to a
new-style "embedded in the state struct" creation, because in the
next commit we're going to want to refer to the object again further
down in the exynos4210_realize() function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-4-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  2 ++
 hw/arm/exynos4210.c         | 11 ++++++-----
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/or-irq.h"
 #include "hw/sysbus.h"
+#include "hw/cpu/a9mpcore.h"
 #include "target/arm/cpu-qom.h"
 #include "qom/object.h"
 
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+    A9MPPrivState a9mpcore;
 };
 
 #define TYPE_EXYNOS4210_SOC "exynos4210"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     }
 
     /* Private memory region and Internal GIC */
-    dev = qdev_new(TYPE_A9MPCORE_PRIV);
-    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
-    busdev = SYS_BUS_DEVICE(dev);
-    sysbus_realize_and_unref(busdev, &error_fatal);
+    qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
+    busdev = SYS_BUS_DEVICE(&s->a9mpcore);
+    sysbus_realize(busdev, &error_fatal);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
         sysbus_connect_irq(busdev, n,
                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
     }
     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
-        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
+        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
     }
 
     /* Cache controller */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
         g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
         object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
     }
+
+    object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
 }
 
 static void exynos4210_class_init(ObjectClass *klass, void *data)
-- 
2.25.1

The only time we use the int_gic_irq[] array in the Exynos4210Irq
struct is in the exynos4210_realize() function: we initialize it with
the GPIO inputs of the a9mpcore device, and then a bit later on we
connect those to the outputs of the internal combiner.  Now that the
a9mpcore object is easily accessible as s->a9mpcore we can make the
connection directly from one device to the other without going via
this array.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-5-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h | 1 -
 hw/arm/exynos4210.c         | 6 ++----
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
-    qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
     qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
     qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 } Exynos4210Irq;
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
         sysbus_connect_irq(busdev, n,
                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
     }
-    for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
-        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
-    }
 
     /* Cache controller */
     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     busdev = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(busdev, &error_fatal);
     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
-        sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
+        sysbus_connect_irq(busdev, n,
+                           qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
     }
     exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
-- 
2.25.1

The exynos4210 code currently has two very similar arrays of IRQs:

* board_irqs is a field of the Exynos4210Irq struct which is filled
   in by exynos4210_init_board_irqs() with the appropriate qemu_irqs
   for each IRQ the board/SoC can assert
 * irq_table is a set of qemu_irqs pointed to from the
   Exynos4210State struct.  It's allocated in exynos4210_init_irq,
   and the only behaviour these irqs have is that they pass on the
   level to the equivalent board_irqs[] irq

The extra indirection through irq_table is unnecessary, so coalesce
these into a single irq_table[] array as a direct field in
Exynos4210State which exynos4210_init_board_irqs() fills in.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-6-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  8 ++------
 hw/arm/exynos4210.c         |  6 +-----
 hw/intc/exynos4210_gic.c    | 32 ++++++++------------------------
 3 files changed, 11 insertions(+), 35 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
     qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
-    qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 } Exynos4210Irq;
 
 struct Exynos4210State {
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     /*< public >*/
     ARMCPU *cpu[EXYNOS4210_NCPUS];
     Exynos4210Irq irqs;
-    qemu_irq *irq_table;
+    qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 
     MemoryRegion chipid_mem;
     MemoryRegion iram_mem;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
 void exynos4210_write_secondary(ARMCPU *cpu,
         const struct arm_boot_info *info);
 
-/* Initialize exynos4210 IRQ subsystem stub */
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
-
 /* Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
-void exynos4210_init_board_irqs(Exynos4210Irq *s);
+void exynos4210_init_board_irqs(Exynos4210State *s);
 
 /* Get IRQ number from exynos4210 IRQ subsystem stub.
  * To identify IRQ source use internal combiner group and bit number
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
     }
 
-    /*** IRQs ***/
-
-    s->irq_table = exynos4210_init_irq(&s->irqs);
-
     /* IRQ Gate */
     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
         DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 
     /* Initialize board IRQs. */
-    exynos4210_init_board_irqs(&s->irqs);
+    exynos4210_init_board_irqs(s);
 
     /*** Memory ***/
 
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
 #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
 
-static void exynos4210_irq_handler(void *opaque, int irq, int level)
-{
-    Exynos4210Irq *s = (Exynos4210Irq *)opaque;
-
-    /* Bypass */
-    qemu_set_irq(s->board_irqs[irq], level);
-}
-
-/*
- * Initialize exynos4210 IRQ subsystem stub.
- */
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
-{
-    return qemu_allocate_irqs(exynos4210_irq_handler, s,
-            EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
-}
-
 /*
  * Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
  */
-void exynos4210_init_board_irqs(Exynos4210Irq *s)
+void exynos4210_init_board_irqs(Exynos4210State *s)
 {
     uint32_t grp, bit, irq_id, n;
+    Exynos4210Irq *is = &s->irqs;
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
@@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
             irq_id = EXT_GIC_ID_MCT_G1;
         }
         if (irq_id) {
-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
-                    s->ext_gic_irq[irq_id-32]);
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_gic_irq[irq_id - 32]);
         } else {
-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
-                    s->ext_combiner_irq[n]);
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_combiner_irq[n]);
         }
     }
     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
@@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
 
         if (irq_id) {
-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
-                    s->ext_gic_irq[irq_id-32]);
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_gic_irq[irq_id - 32]);
         }
     }
 }
-- 
2.25.1

The function exynos4210_init_board_irqs() currently lives in
exynos4210_gic.c, but it isn't really part of the exynos4210.gic
device -- it is a function that implements (some of) the wiring up of
interrupts between the SoC's GIC and combiner components.  This means
it fits better in exynos4210.c, which is the SoC-level code.  Move it
there. Similarly, exynos4210_git_irq() is used almost only in the
SoC-level code, so move it too.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-8-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |   4 -
 hw/arm/exynos4210.c         | 202 +++++++++++++++++++++++++++++++++++
 hw/intc/exynos4210_gic.c    | 204 ------------------------------------
 3 files changed, 202 insertions(+), 208 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
 void exynos4210_write_secondary(ARMCPU *cpu,
         const struct arm_boot_info *info);
 
-/* Initialize board IRQs.
- * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
-void exynos4210_init_board_irqs(Exynos4210State *s);
-
 /* Get IRQ number from exynos4210 IRQ subsystem stub.
  * To identify IRQ source use internal combiner group and bit number
  *  grp - group number
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 #define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
 #define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
 
+enum ExtGicId {
+    EXT_GIC_ID_MDMA_LCD0 = 66,
+    EXT_GIC_ID_PDMA0,
+    EXT_GIC_ID_PDMA1,
+    EXT_GIC_ID_TIMER0,
+    EXT_GIC_ID_TIMER1,
+    EXT_GIC_ID_TIMER2,
+    EXT_GIC_ID_TIMER3,
+    EXT_GIC_ID_TIMER4,
+    EXT_GIC_ID_MCT_L0,
+    EXT_GIC_ID_WDT,
+    EXT_GIC_ID_RTC_ALARM,
+    EXT_GIC_ID_RTC_TIC,
+    EXT_GIC_ID_GPIO_XB,
+    EXT_GIC_ID_GPIO_XA,
+    EXT_GIC_ID_MCT_L1,
+    EXT_GIC_ID_IEM_APC,
+    EXT_GIC_ID_IEM_IEC,
+    EXT_GIC_ID_NFC,
+    EXT_GIC_ID_UART0,
+    EXT_GIC_ID_UART1,
+    EXT_GIC_ID_UART2,
+    EXT_GIC_ID_UART3,
+    EXT_GIC_ID_UART4,
+    EXT_GIC_ID_MCT_G0,
+    EXT_GIC_ID_I2C0,
+    EXT_GIC_ID_I2C1,
+    EXT_GIC_ID_I2C2,
+    EXT_GIC_ID_I2C3,
+    EXT_GIC_ID_I2C4,
+    EXT_GIC_ID_I2C5,
+    EXT_GIC_ID_I2C6,
+    EXT_GIC_ID_I2C7,
+    EXT_GIC_ID_SPI0,
+    EXT_GIC_ID_SPI1,
+    EXT_GIC_ID_SPI2,
+    EXT_GIC_ID_MCT_G1,
+    EXT_GIC_ID_USB_HOST,
+    EXT_GIC_ID_USB_DEVICE,
+    EXT_GIC_ID_MODEMIF,
+    EXT_GIC_ID_HSMMC0,
+    EXT_GIC_ID_HSMMC1,
+    EXT_GIC_ID_HSMMC2,
+    EXT_GIC_ID_HSMMC3,
+    EXT_GIC_ID_SDMMC,
+    EXT_GIC_ID_MIPI_CSI_4LANE,
+    EXT_GIC_ID_MIPI_DSI_4LANE,
+    EXT_GIC_ID_MIPI_CSI_2LANE,
+    EXT_GIC_ID_MIPI_DSI_2LANE,
+    EXT_GIC_ID_ONENAND_AUDI,
+    EXT_GIC_ID_ROTATOR,
+    EXT_GIC_ID_FIMC0,
+    EXT_GIC_ID_FIMC1,
+    EXT_GIC_ID_FIMC2,
+    EXT_GIC_ID_FIMC3,
+    EXT_GIC_ID_JPEG,
+    EXT_GIC_ID_2D,
+    EXT_GIC_ID_PCIe,
+    EXT_GIC_ID_MIXER,
+    EXT_GIC_ID_HDMI,
+    EXT_GIC_ID_HDMI_I2C,
+    EXT_GIC_ID_MFC,
+    EXT_GIC_ID_TVENC,
+};
+
+enum ExtInt {
+    EXT_GIC_ID_EXTINT0 = 48,
+    EXT_GIC_ID_EXTINT1,
+    EXT_GIC_ID_EXTINT2,
+    EXT_GIC_ID_EXTINT3,
+    EXT_GIC_ID_EXTINT4,
+    EXT_GIC_ID_EXTINT5,
+    EXT_GIC_ID_EXTINT6,
+    EXT_GIC_ID_EXTINT7,
+    EXT_GIC_ID_EXTINT8,
+    EXT_GIC_ID_EXTINT9,
+    EXT_GIC_ID_EXTINT10,
+    EXT_GIC_ID_EXTINT11,
+    EXT_GIC_ID_EXTINT12,
+    EXT_GIC_ID_EXTINT13,
+    EXT_GIC_ID_EXTINT14,
+    EXT_GIC_ID_EXTINT15
+};
+
+/*
+ * External GIC sources which are not from External Interrupt Combiner or
+ * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
+ * which is INTG16 in Internal Interrupt Combiner.
+ */
+
+static const uint32_t
+combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+    /* int combiner groups 16-19 */
+    { }, { }, { }, { },
+    /* int combiner group 20 */
+    { 0, EXT_GIC_ID_MDMA_LCD0 },
+    /* int combiner group 21 */
+    { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
+    /* int combiner group 22 */
+    { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
+            EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
+    /* int combiner group 23 */
+    { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
+    /* int combiner group 24 */
+    { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
+    /* int combiner group 25 */
+    { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
+    /* int combiner group 26 */
+    { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
+            EXT_GIC_ID_UART4 },
+    /* int combiner group 27 */
+    { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
+            EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
+            EXT_GIC_ID_I2C7 },
+    /* int combiner group 28 */
+    { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
+    /* int combiner group 29 */
+    { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
+     EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
+    /* int combiner group 30 */
+    { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
+    /* int combiner group 31 */
+    { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
+    /* int combiner group 32 */
+    { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
+    /* int combiner group 33 */
+    { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
+    /* int combiner group 34 */
+    { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
+    /* int combiner group 35 */
+    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    /* int combiner group 36 */
+    { EXT_GIC_ID_MIXER },
+    /* int combiner group 37 */
+    { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
+     EXT_GIC_ID_EXTINT7 },
+    /* groups 38-50 */
+    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
+    /* int combiner group 51 */
+    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    /* group 52 */
+    { },
+    /* int combiner group 53 */
+    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    /* groups 54-63 */
+    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
+};
+
+/*
+ * Initialize board IRQs.
+ * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
+ */
+static void exynos4210_init_board_irqs(Exynos4210State *s)
+{
+    uint32_t grp, bit, irq_id, n;
+    Exynos4210Irq *is = &s->irqs;
+
+    for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+        irq_id = 0;
+        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
+                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
+            /* MCT_G0 is passed to External GIC */
+            irq_id = EXT_GIC_ID_MCT_G0;
+        }
+        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
+                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
+            /* MCT_G1 is passed to External and GIC */
+            irq_id = EXT_GIC_ID_MCT_G1;
+        }
+        if (irq_id) {
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_gic_irq[irq_id - 32]);
+        } else {
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_combiner_irq[n]);
+        }
+    }
+    for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
+        /* these IDs are passed to Internal Combiner and External GIC */
+        grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
+        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
+        irq_id = combiner_grp_to_gic_id[grp -
+                     EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
+
+        if (irq_id) {
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_gic_irq[irq_id - 32]);
+        }
+    }
+}
+
+/*
+ * Get IRQ number from exynos4210 IRQ subsystem stub.
+ * To identify IRQ source use internal combiner group and bit number
+ *  grp - group number
+ *  bit - bit number inside group
+ */
+uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
+{
+    return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
+}
+
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/exynos4210.h"
 #include "qom/object.h"
 
-enum ExtGicId {
-    EXT_GIC_ID_MDMA_LCD0 = 66,
-    EXT_GIC_ID_PDMA0,
-    EXT_GIC_ID_PDMA1,
-    EXT_GIC_ID_TIMER0,
-    EXT_GIC_ID_TIMER1,
-    EXT_GIC_ID_TIMER2,
-    EXT_GIC_ID_TIMER3,
-    EXT_GIC_ID_TIMER4,
-    EXT_GIC_ID_MCT_L0,
-    EXT_GIC_ID_WDT,
-    EXT_GIC_ID_RTC_ALARM,
-    EXT_GIC_ID_RTC_TIC,
-    EXT_GIC_ID_GPIO_XB,
-    EXT_GIC_ID_GPIO_XA,
-    EXT_GIC_ID_MCT_L1,
-    EXT_GIC_ID_IEM_APC,
-    EXT_GIC_ID_IEM_IEC,
-    EXT_GIC_ID_NFC,
-    EXT_GIC_ID_UART0,
-    EXT_GIC_ID_UART1,
-    EXT_GIC_ID_UART2,
-    EXT_GIC_ID_UART3,
-    EXT_GIC_ID_UART4,
-    EXT_GIC_ID_MCT_G0,
-    EXT_GIC_ID_I2C0,
-    EXT_GIC_ID_I2C1,
-    EXT_GIC_ID_I2C2,
-    EXT_GIC_ID_I2C3,
-    EXT_GIC_ID_I2C4,
-    EXT_GIC_ID_I2C5,
-    EXT_GIC_ID_I2C6,
-    EXT_GIC_ID_I2C7,
-    EXT_GIC_ID_SPI0,
-    EXT_GIC_ID_SPI1,
-    EXT_GIC_ID_SPI2,
-    EXT_GIC_ID_MCT_G1,
-    EXT_GIC_ID_USB_HOST,
-    EXT_GIC_ID_USB_DEVICE,
-    EXT_GIC_ID_MODEMIF,
-    EXT_GIC_ID_HSMMC0,
-    EXT_GIC_ID_HSMMC1,
-    EXT_GIC_ID_HSMMC2,
-    EXT_GIC_ID_HSMMC3,
-    EXT_GIC_ID_SDMMC,
-    EXT_GIC_ID_MIPI_CSI_4LANE,
-    EXT_GIC_ID_MIPI_DSI_4LANE,
-    EXT_GIC_ID_MIPI_CSI_2LANE,
-    EXT_GIC_ID_MIPI_DSI_2LANE,
-    EXT_GIC_ID_ONENAND_AUDI,
-    EXT_GIC_ID_ROTATOR,
-    EXT_GIC_ID_FIMC0,
-    EXT_GIC_ID_FIMC1,
-    EXT_GIC_ID_FIMC2,
-    EXT_GIC_ID_FIMC3,
-    EXT_GIC_ID_JPEG,
-    EXT_GIC_ID_2D,
-    EXT_GIC_ID_PCIe,
-    EXT_GIC_ID_MIXER,
-    EXT_GIC_ID_HDMI,
-    EXT_GIC_ID_HDMI_I2C,
-    EXT_GIC_ID_MFC,
-    EXT_GIC_ID_TVENC,
-};
-
-enum ExtInt {
-    EXT_GIC_ID_EXTINT0 = 48,
-    EXT_GIC_ID_EXTINT1,
-    EXT_GIC_ID_EXTINT2,
-    EXT_GIC_ID_EXTINT3,
-    EXT_GIC_ID_EXTINT4,
-    EXT_GIC_ID_EXTINT5,
-    EXT_GIC_ID_EXTINT6,
-    EXT_GIC_ID_EXTINT7,
-    EXT_GIC_ID_EXTINT8,
-    EXT_GIC_ID_EXTINT9,
-    EXT_GIC_ID_EXTINT10,
-    EXT_GIC_ID_EXTINT11,
-    EXT_GIC_ID_EXTINT12,
-    EXT_GIC_ID_EXTINT13,
-    EXT_GIC_ID_EXTINT14,
-    EXT_GIC_ID_EXTINT15
-};
-
-/*
- * External GIC sources which are not from External Interrupt Combiner or
- * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
- * which is INTG16 in Internal Interrupt Combiner.
- */
-
-static const uint32_t
-combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
-    /* int combiner groups 16-19 */
-    { }, { }, { }, { },
-    /* int combiner group 20 */
-    { 0, EXT_GIC_ID_MDMA_LCD0 },
-    /* int combiner group 21 */
-    { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
-    /* int combiner group 22 */
-    { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
-            EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
-    /* int combiner group 23 */
-    { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
-    /* int combiner group 24 */
-    { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
-    /* int combiner group 25 */
-    { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
-    /* int combiner group 26 */
-    { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
-            EXT_GIC_ID_UART4 },
-    /* int combiner group 27 */
-    { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
-            EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
-            EXT_GIC_ID_I2C7 },
-    /* int combiner group 28 */
-    { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
-    /* int combiner group 29 */
-    { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
-     EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
-    /* int combiner group 30 */
-    { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
-    /* int combiner group 31 */
-    { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
-    /* int combiner group 32 */
-    { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
-    /* int combiner group 33 */
-    { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
-    /* int combiner group 34 */
-    { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
-    /* int combiner group 35 */
-    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
-    /* int combiner group 36 */
-    { EXT_GIC_ID_MIXER },
-    /* int combiner group 37 */
-    { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
-     EXT_GIC_ID_EXTINT7 },
-    /* groups 38-50 */
-    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
-    /* int combiner group 51 */
-    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
-    /* group 52 */
-    { },
-    /* int combiner group 53 */
-    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
-    /* groups 54-63 */
-    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
-};
-
 #define EXYNOS4210_GIC_NIRQ 160
 
 #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE     0x10000
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
 #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
 
-/*
- * Initialize board IRQs.
- * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
- */
-void exynos4210_init_board_irqs(Exynos4210State *s)
-{
-    uint32_t grp, bit, irq_id, n;
-    Exynos4210Irq *is = &s->irqs;
-
-    for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
-        irq_id = 0;
-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
-            /* MCT_G0 is passed to External GIC */
-            irq_id = EXT_GIC_ID_MCT_G0;
-        }
-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
-            /* MCT_G1 is passed to External and GIC */
-            irq_id = EXT_GIC_ID_MCT_G1;
-        }
-        if (irq_id) {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_gic_irq[irq_id - 32]);
-        } else {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_combiner_irq[n]);
-        }
-    }
-    for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
-        /* these IDs are passed to Internal Combiner and External GIC */
-        grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
-        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
-        irq_id = combiner_grp_to_gic_id[grp -
-                     EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
-
-        if (irq_id) {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_gic_irq[irq_id - 32]);
-        }
-    }
-}
-
-/*
- * Get IRQ number from exynos4210 IRQ subsystem stub.
- * To identify IRQ source use internal combiner group and bit number
- *  grp - group number
- *  bit - bit number inside group
- */
-uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
-{
-    return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
-}
-
-/********* GIC part *********/
-
 #define TYPE_EXYNOS4210_GIC "exynos4210.gic"
 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
 
-- 
2.25.1

Switch the creation of the external GIC to the new-style "embedded in
state struct" approach, so we can easily refer to the object
elsewhere during realize.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-9-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h      |  2 ++
 include/hw/intc/exynos4210_gic.h | 43 ++++++++++++++++++++++++++++++++
 hw/arm/exynos4210.c              | 10 ++++----
 hw/intc/exynos4210_gic.c         | 17 ++-----------
 MAINTAINERS                      |  2 +-
 5 files changed, 53 insertions(+), 21 deletions(-)
 create mode 100644 include/hw/intc/exynos4210_gic.h

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/or-irq.h"
 #include "hw/sysbus.h"
 #include "hw/cpu/a9mpcore.h"
+#include "hw/intc/exynos4210_gic.h"
 #include "target/arm/cpu-qom.h"
 #include "qom/object.h"
 
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
     A9MPPrivState a9mpcore;
+    Exynos4210GicState ext_gic;
 };
 
 #define TYPE_EXYNOS4210_SOC "exynos4210"
diff --git a/include/hw/intc/exynos4210_gic.h b/include/hw/intc/exynos4210_gic.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/intc/exynos4210_gic.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
+ *
+ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
+ * All rights reserved.
+ *
+ * Evgeny Voevodin <e.voevodin@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef HW_INTC_EXYNOS4210_GIC_H
+#define HW_INTC_EXYNOS4210_GIC_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
+
+#define EXYNOS4210_GIC_NCPUS 2
+
+struct Exynos4210GicState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion cpu_container;
+    MemoryRegion dist_container;
+    MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS];
+    MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS];
+    uint32_t num_cpu;
+    DeviceState *gic;
+};
+
+#endif
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
 
     /* External GIC */
-    dev = qdev_new("exynos4210.gic");
-    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
-    busdev = SYS_BUS_DEVICE(dev);
-    sysbus_realize_and_unref(busdev, &error_fatal);
+    qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
+    busdev = SYS_BUS_DEVICE(&s->ext_gic);
+    sysbus_realize(busdev, &error_fatal);
     /* Map CPU interface */
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
     /* Map Distributer interface */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
     }
     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
-        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
+        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
     }
 
     /* Internal Interrupt Combiner */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
     }
 
     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
+    object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
 }
 
 static void exynos4210_class_init(ObjectClass *klass, void *data)
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
+#include "hw/intc/exynos4210_gic.h"
 #include "hw/arm/exynos4210.h"
 #include "qom/object.h"
 
@@ -XXX,XX +XXX,XX @@
 #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
 
-#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
-
-struct Exynos4210GicState {
-    SysBusDevice parent_obj;
-
-    MemoryRegion cpu_container;
-    MemoryRegion dist_container;
-    MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
-    MemoryRegion dist_alias[EXYNOS4210_NCPUS];
-    uint32_t num_cpu;
-    DeviceState *gic;
-};
-
 static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
 {
     Exynos4210GicState *s = (Exynos4210GicState *)opaque;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp)
      * enough room for the cpu numbers.  gcc 9.2.1 on 32-bit x86
      * doesn't figure this out, otherwise and gives spurious warnings.
      */
-    assert(n <= EXYNOS4210_NCPUS);
+    assert(n <= EXYNOS4210_GIC_NCPUS);
     for (i = 0; i < n; i++) {
         /* Map CPU interface per SMP Core */
         sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Odd Fixes
 F: hw/*/exynos*
-F: include/hw/arm/exynos4210.h
+F: include/hw/*/exynos*
 
 Calxeda Highbank
 M: Rob Herring <robh@kernel.org>
-- 
2.25.1

The only time we use the ext_gic_irq[] array in the Exynos4210Irq
struct is during realize of the SoC -- we initialize it with the
input IRQs of the external GIC device, and then connect those to
outputs of other devices further on in realize (including in the
exynos4210_init_board_irqs() function).  Now that the ext_gic object
is easily accessible as s->ext_gic we can make the connections
directly from one device to the other without going via this array.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-10-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  1 -
 hw/arm/exynos4210.c         | 12 ++++++------
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
-    qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
 } Exynos4210Irq;
 
 struct Exynos4210State {
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
 {
     uint32_t grp, bit, irq_id, n;
     Exynos4210Irq *is = &s->irqs;
+    DeviceState *extgicdev = DEVICE(&s->ext_gic);
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
         }
         if (irq_id) {
             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_gic_irq[irq_id - 32]);
+                                             qdev_get_gpio_in(extgicdev,
+                                                              irq_id - 32));
         } else {
             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
                     is->ext_combiner_irq[n]);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
 
         if (irq_id) {
             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_gic_irq[irq_id - 32]);
+                                             qdev_get_gpio_in(extgicdev,
+                                                              irq_id - 32));
         }
     }
 }
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
         sysbus_connect_irq(busdev, n,
                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
     }
-    for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
-        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
-    }
 
     /* Internal Interrupt Combiner */
     dev = qdev_new("exynos4210.combiner");
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     busdev = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(busdev, &error_fatal);
     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
-        sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
+        sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
     }
     exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
-- 
2.25.1

The function exynos4210_combiner_get_gpioin() currently lives in
exynos4210_combiner.c, but it isn't really part of the combiner
device itself -- it is a function that implements the wiring up of
some interrupt sources to multiple combiner inputs.  Move it to live
with the other SoC-level code in exynos4210.c, along with a few
macros previously defined in exynos4210.h which are now used only
in exynos4210.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-11-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h   | 11 -----
 hw/arm/exynos4210.c           | 82 +++++++++++++++++++++++++++++++++++
 hw/intc/exynos4210_combiner.c | 77 --------------------------------
 3 files changed, 82 insertions(+), 88 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ   \
     (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
 
-#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit)  ((grp)*8 + (bit))
-#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq)       ((irq) / 8)
-#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
-    ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
-
 /* IRQs number for external and internal GIC */
 #define EXYNOS4210_EXT_GIC_NIRQ     (160-32)
 #define EXYNOS4210_INT_GIC_NIRQ     64
@@ -XXX,XX +XXX,XX @@ void exynos4210_write_secondary(ARMCPU *cpu,
  *  bit - bit number inside group */
 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
 
-/*
- * Get Combiner input GPIO into irqs structure
- */
-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
-        int ext);
-
 /*
  * exynos4210 UART
  */
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
 };
 
+#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit)  ((grp) * 8 + (bit))
+#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq)       ((irq) / 8)
+#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
+    ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
+
 /*
  * Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
@@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
     return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
 }
 
+/*
+ * Get Combiner input GPIO into irqs structure
+ */
+static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
+                                           DeviceState *dev, int ext)
+{
+    int n;
+    int bit;
+    int max;
+    qemu_irq *irq;
+
+    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
+        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
+    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
+
+    /*
+     * Some IRQs of Int/External Combiner are going to two Combiners groups,
+     * so let split them.
+     */
+    for (n = 0; n < max; n++) {
+
+        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
+
+        switch (n) {
+        /* MDNIE_LCD1 INTG1 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
+            continue;
+
+        /* TMU INTG3 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
+            continue;
+
+        /* LCD1 INTG12 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
+            continue;
+
+        /* Multi-Core Timer INTG12 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
+               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+            continue;
+
+        /* Multi-Core Timer INTG35 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+            continue;
+
+        /* Multi-Core Timer INTG51 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+            continue;
+
+        /* Multi-Core Timer INTG53 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+            continue;
+        }
+
+        irq[n] = qdev_get_gpio_in(dev, n);
+    }
+}
+
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_combiner.c
+++ b/hw/intc/exynos4210_combiner.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_combiner = {
     }
 };
 
-/*
- * Get Combiner input GPIO into irqs structure
- */
-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
-        int ext)
-{
-    int n;
-    int bit;
-    int max;
-    qemu_irq *irq;
-
-    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
-        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
-    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
-
-    /*
-     * Some IRQs of Int/External Combiner are going to two Combiners groups,
-     * so let split them.
-     */
-    for (n = 0; n < max; n++) {
-
-        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
-
-        switch (n) {
-        /* MDNIE_LCD1 INTG1 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
-            continue;
-
-        /* TMU INTG3 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
-            continue;
-
-        /* LCD1 INTG12 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG12 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
-               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG35 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG51 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG53 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-        }
-
-        irq[n] = qdev_get_gpio_in(dev, n);
-    }
-}
-
 static uint64_t
 exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
 {
-- 
2.25.1

In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device
instead of qemu_irq_split().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-13-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  9 ++++++++
 hw/arm/exynos4210.c         | 41 +++++++++++++++++++++++++++++--------
 2 files changed, 42 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/intc/exynos4210_gic.h"
+#include "hw/core/split-irq.h"
 #include "target/arm/cpu-qom.h"
 #include "qom/object.h"
 
@@ -XXX,XX +XXX,XX @@
 
 #define EXYNOS4210_NUM_DMA      3
 
+/*
+ * We need one splitter for every external combiner input, plus
+ * one for every non-zero entry in combiner_grp_to_gic_id[].
+ * We'll assert in exynos4210_init_board_irqs() if this is wrong.
+ */
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
+
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
     A9MPPrivState a9mpcore;
     Exynos4210GicState ext_gic;
+    SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
 };
 
 #define TYPE_EXYNOS4210_SOC "exynos4210"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
     uint32_t grp, bit, irq_id, n;
     Exynos4210Irq *is = &s->irqs;
     DeviceState *extgicdev = DEVICE(&s->ext_gic);
+    int splitcount = 0;
+    DeviceState *splitter;
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
             /* MCT_G1 is passed to External and GIC */
             irq_id = EXT_GIC_ID_MCT_G1;
         }
+
+        assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
+        splitter = DEVICE(&s->splitter[splitcount]);
+        qdev_prop_set_uint16(splitter, "num-lines", 2);
+        qdev_realize(splitter, NULL, &error_abort);
+        splitcount++;
+        s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
+        qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
         if (irq_id) {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                                             qdev_get_gpio_in(extgicdev,
-                                                              irq_id - 32));
+            qdev_connect_gpio_out(splitter, 1,
+                                  qdev_get_gpio_in(extgicdev, irq_id - 32));
         } else {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_combiner_irq[n]);
+            qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
         }
     }
     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
 
         if (irq_id) {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                                             qdev_get_gpio_in(extgicdev,
-                                                              irq_id - 32));
+            assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
+            splitter = DEVICE(&s->splitter[splitcount]);
+            qdev_prop_set_uint16(splitter, "num-lines", 2);
+            qdev_realize(splitter, NULL, &error_abort);
+            splitcount++;
+            s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
+            qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
+            qdev_connect_gpio_out(splitter, 1,
+                                  qdev_get_gpio_in(extgicdev, irq_id - 32));
         }
     }
+    /*
+     * We check this here to avoid a more obscure assert later when
+     * qdev_assert_realized_properly() checks that we realized every
+     * child object we initialized.
+     */
+    assert(splitcount == EXYNOS4210_NUM_SPLITTERS);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
         object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
     }
 
+    for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
+        g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
+        object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ);
+    }
+
     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
     object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
 }
-- 
2.25.1

In exynos4210_init_board_irqs(), the loop that handles IRQ lines that
are in a range that applies to the internal combiner only creates a
splitter for those interrupts which go to both the internal combiner
and to the external GIC, but it does nothing at all for the
interrupts which don't go to the external GIC, leaving the
irq_table[] array element empty for those.  (This will result in
those interrupts simply being lost, not in a QEMU crash.)

I don't have a reliable datasheet for this SoC, but since we do wire
up one interrupt line in this category (the HDMI I2C device on
interrupt 16,1), this seems like it must be a bug in the existing
QEMU code.  Fill in the irq_table[] entries where we're not splitting
the IRQ to both the internal combiner and the external GIC with the
IRQ line of the internal combiner.  (That is, these IRQ lines go to
just one device, not multiple.)

This bug didn't have any visible guest effects because the only
implemented device that was affected was the HDMI I2C controller,
and we never connect any I2C devices to that bus.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-14-peter.maydell@linaro.org
---
 hw/arm/exynos4210.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
             qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
             qdev_connect_gpio_out(splitter, 1,
                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
+        } else {
+            s->irq_table[n] = is->int_combiner_irq[n];
         }
     }
     /*
-- 
2.25.1

Currently for the interrupts MCT_G0 and MCT_G1 which are
the only ones in the input range of the external combiner
and which are also wired to the external GIC, we connect
them only to the internal combiner and the external GIC.
This seems likely to be a bug, as all other interrupts
which are in the input range of both combiners are
connected to both combiners. (The fact that the code in
exynos4210_combiner_get_gpioin() is also trying to wire
up these inputs on both combiners also suggests this.)

Wire these interrupts up to both combiners, like the rest.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-15-peter.maydell@linaro.org
---
 hw/arm/exynos4210.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
 
         assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
         splitter = DEVICE(&s->splitter[splitcount]);
-        qdev_prop_set_uint16(splitter, "num-lines", 2);
+        qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2);
         qdev_realize(splitter, NULL, &error_abort);
         splitcount++;
         s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
         qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
+        qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
         if (irq_id) {
-            qdev_connect_gpio_out(splitter, 1,
+            qdev_connect_gpio_out(splitter, 2,
                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
-        } else {
-            qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
         }
     }
     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
-- 
2.25.1

The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0
and EXT_GIC_ID_MCT_G1 multiple times. This means that we will
connect multiple IRQs up to the same external GIC input, which
is not permitted. We do the same thing in the code in
exynos4210_init_board_irqs() because the conditionals selecting
an irq_id in the first loop match multiple interrupt IDs.

Overall we do this for interrupt IDs
(1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0
and
(1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1

These correspond to the cases for the multi-core timer that we are
wiring up to multiple inputs on the combiner in
exynos4210_combiner_get_gpioin().  That code already deals with all
these interrupt IDs being the same input source, so we don't need to
connect the external GIC interrupt for any of them except the first
(1, 4) and (1, 5). Remove the array entries and conditionals which
were incorrectly causing us to wire up extra lines.

This bug didn't cause any visible effects, because we only connect
up a device to the "primary" ID values (1, 4) and (1, 5), so the
extra lines would never be set to a level.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-16-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  2 +-
 hw/arm/exynos4210.c         | 12 +++++-------
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
  * one for every non-zero entry in combiner_grp_to_gic_id[].
  * We'll assert in exynos4210_init_board_irqs() if this is wrong.
  */
-#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
 
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
     /* int combiner group 34 */
     { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
     /* int combiner group 35 */
-    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    { 0, 0, 0, EXT_GIC_ID_MCT_L1 },
     /* int combiner group 36 */
     { EXT_GIC_ID_MIXER },
     /* int combiner group 37 */
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
     /* groups 38-50 */
     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
     /* int combiner group 51 */
-    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    { EXT_GIC_ID_MCT_L0 },
     /* group 52 */
     { },
     /* int combiner group 53 */
-    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    { EXT_GIC_ID_WDT },
     /* groups 54-63 */
     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
 };
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
+        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) {
             /* MCT_G0 is passed to External GIC */
             irq_id = EXT_GIC_ID_MCT_G0;
         }
-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
+        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) {
             /* MCT_G1 is passed to External and GIC */
             irq_id = EXT_GIC_ID_MCT_G1;
         }
-- 
2.25.1

At this point, the function exynos4210_init_board_irqs() splits input
IRQ lines to connect them to the input combiner, output combiner and
external GIC.  The function exynos4210_combiner_get_gpioin() splits
some of the combiner input lines further to connect them to multiple
different inputs on the combiner.

Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a
configurable number of outputs, we can do all this in one place, by
making exynos4210_init_board_irqs() add extra outputs to the splitter
device when it must be connected to more than one input on each
combiner.

We do this with a new data structure, the combinermap, which is an
array each of whose elements is a list of the interrupt IDs on the
combiner which must be tied together.  As we loop through each
interrupt ID, if we find that it is the first one in one of these
lists, we configure the splitter device with eonugh extra outputs and
wire them up to the other interrupt IDs in the list.

Conveniently, for all the cases where this is necessary, the
lowest-numbered interrupt ID in each group is in the range of the
external combiner, so we only need to code for this in the first of
the two loops in exynos4210_init_board_irqs().

The old code in exynos4210_combiner_get_gpioin() which is being
deleted here had several problems which don't exist in the new code
in its handling of the multi-core timer interrupts:
 (1) the case labels specified bits 4 ... 8, but bit '8' doesn't
     exist; these should have been 4 ... 7
 (2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]
     multiple times as the input of several different splitters,
     which isn't allowed
 (3) in an apparent cut-and-paste error, the cases for all the
     multi-core timer inputs used "bit + 4" even though the
     bit range for the case was (intended to be) 4 ... 7, which
     meant it was looking at non-existent bits 8 ... 11.
None of these exist in the new code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-17-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |   6 +-
 hw/arm/exynos4210.c         | 178 +++++++++++++++++++++++-------------
 2 files changed, 119 insertions(+), 65 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 
 /*
  * We need one splitter for every external combiner input, plus
- * one for every non-zero entry in combiner_grp_to_gic_id[].
+ * one for every non-zero entry in combiner_grp_to_gic_id[],
+ * minus one for every external combiner ID in second or later
+ * places in a combinermap[] line.
  * We'll assert in exynos4210_init_board_irqs() if this is wrong.
  */
-#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
 
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
 #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
     ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
 
+/*
+ * Some interrupt lines go to multiple combiner inputs.
+ * This data structure defines those: each array element is
+ * a list of combiner inputs which are connected together;
+ * the one with the smallest interrupt ID value must be first.
+ * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being
+ * wired to anything so we can use 0 as a terminator.
+ */
+#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B)
+#define IRQNONE 0
+
+#define COMBINERMAP_SIZE 16
+
+static const int combinermap[COMBINERMAP_SIZE][6] = {
+    /* MDNIE_LCD1 */
+    { IRQNO(0, 4), IRQNO(1, 0), IRQNONE },
+    { IRQNO(0, 5), IRQNO(1, 1), IRQNONE },
+    { IRQNO(0, 6), IRQNO(1, 2), IRQNONE },
+    { IRQNO(0, 7), IRQNO(1, 3), IRQNONE },
+    /* TMU */
+    { IRQNO(2, 4), IRQNO(3, 4), IRQNONE },
+    { IRQNO(2, 5), IRQNO(3, 5), IRQNONE },
+    { IRQNO(2, 6), IRQNO(3, 6), IRQNONE },
+    { IRQNO(2, 7), IRQNO(3, 7), IRQNONE },
+    /* LCD1 */
+    { IRQNO(11, 4), IRQNO(12, 0), IRQNONE },
+    { IRQNO(11, 5), IRQNO(12, 1), IRQNONE },
+    { IRQNO(11, 6), IRQNO(12, 2), IRQNONE },
+    { IRQNO(11, 7), IRQNO(12, 3), IRQNONE },
+    /* Multi-core timer */
+    { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE },
+    { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE },
+    { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE },
+    { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE },
+};
+
+#undef IRQNO
+
+static const int *combinermap_entry(int irq)
+{
+    /*
+     * If the interrupt number passed in is the first entry in some
+     * line of the combinermap, return a pointer to that line;
+     * otherwise return NULL.
+     */
+    int i;
+    for (i = 0; i < COMBINERMAP_SIZE; i++) {
+        if (combinermap[i][0] == irq) {
+            return combinermap[i];
+        }
+    }
+    return NULL;
+}
+
+static int mapline_size(const int *mapline)
+{
+    /* Return number of entries in this mapline in total */
+    int i = 0;
+
+    if (!mapline) {
+        /* Not in the map? IRQ goes to exactly one combiner input */
+        return 1;
+    }
+    while (*mapline != IRQNONE) {
+        mapline++;
+        i++;
+    }
+    return i;
+}
+
 /*
  * Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
     DeviceState *extgicdev = DEVICE(&s->ext_gic);
     int splitcount = 0;
     DeviceState *splitter;
+    const int *mapline;
+    int numlines, splitin, in;
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
             irq_id = EXT_GIC_ID_MCT_G1;
         }
 
+        if (s->irq_table[n]) {
+            /*
+             * This must be some non-first entry in a combinermap line,
+             * and we've already filled it in.
+             */
+            continue;
+        }
+        mapline = combinermap_entry(n);
+        /*
+         * We need to connect the IRQ to multiple inputs on both combiners
+         * and possibly also to the external GIC.
+         */
+        numlines = 2 * mapline_size(mapline);
+        if (irq_id) {
+            numlines++;
+        }
         assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
         splitter = DEVICE(&s->splitter[splitcount]);
-        qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2);
+        qdev_prop_set_uint16(splitter, "num-lines", numlines);
         qdev_realize(splitter, NULL, &error_abort);
         splitcount++;
-        s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
-        qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
-        qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
+
+        in = n;
+        splitin = 0;
+        for (;;) {
+            s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
+            qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]);
+            qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]);
+            splitin += 2;
+            if (!mapline) {
+                break;
+            }
+            mapline++;
+            in = *mapline;
+            if (in == IRQNONE) {
+                break;
+            }
+        }
         if (irq_id) {
-            qdev_connect_gpio_out(splitter, 2,
+            qdev_connect_gpio_out(splitter, splitin,
                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
         }
     }
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
         irq_id = combiner_grp_to_gic_id[grp -
                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
 
+        if (s->irq_table[n]) {
+            /*
+             * This must be some non-first entry in a combinermap line,
+             * and we've already filled it in.
+             */
+            continue;
+        }
+
         if (irq_id) {
             assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
             splitter = DEVICE(&s->splitter[splitcount]);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
                                            DeviceState *dev, int ext)
 {
     int n;
-    int bit;
     int max;
     qemu_irq *irq;
 
@@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
         EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
     irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
 
-    /*
-     * Some IRQs of Int/External Combiner are going to two Combiners groups,
-     * so let split them.
-     */
     for (n = 0; n < max; n++) {
-
-        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
-
-        switch (n) {
-        /* MDNIE_LCD1 INTG1 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
-            continue;
-
-        /* TMU INTG3 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
-            continue;
-
-        /* LCD1 INTG12 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG12 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
-               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG35 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG51 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG53 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-        }
-
         irq[n] = qdev_get_gpio_in(dev, n);
     }
 }
-- 
2.25.1

Switch the creation of the combiner devices to the new-style
"embedded in state struct" approach, so we can easily refer
to the object elsewhere during realize.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-18-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h           |  3 ++
 include/hw/intc/exynos4210_combiner.h | 57 +++++++++++++++++++++++++++
 hw/arm/exynos4210.c                   | 20 +++++-----
 hw/intc/exynos4210_combiner.c         | 31 +--------------
 4 files changed, 72 insertions(+), 39 deletions(-)
 create mode 100644 include/hw/intc/exynos4210_combiner.h

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/intc/exynos4210_gic.h"
+#include "hw/intc/exynos4210_combiner.h"
 #include "hw/core/split-irq.h"
 #include "target/arm/cpu-qom.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
     A9MPPrivState a9mpcore;
     Exynos4210GicState ext_gic;
+    Exynos4210CombinerState int_combiner;
+    Exynos4210CombinerState ext_combiner;
     SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
 };
 
diff --git a/include/hw/intc/exynos4210_combiner.h b/include/hw/intc/exynos4210_combiner.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/intc/exynos4210_combiner.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Samsung exynos4210 Interrupt Combiner
+ *
+ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
+ * All rights reserved.
+ *
+ * Evgeny Voevodin <e.voevodin@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_INTC_EXYNOS4210_COMBINER
+#define HW_INTC_EXYNOS4210_COMBINER
+
+#include "hw/sysbus.h"
+
+/*
+ * State for each output signal of internal combiner
+ */
+typedef struct CombinerGroupState {
+    uint8_t src_mask;            /* 1 - source enabled, 0 - disabled */
+    uint8_t src_pending;        /* Pending source interrupts before masking */
+} CombinerGroupState;
+
+#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
+
+/* Number of groups and total number of interrupts for the internal combiner */
+#define IIC_NGRP 64
+#define IIC_NIRQ (IIC_NGRP * 8)
+#define IIC_REGSET_SIZE 0x41
+
+struct Exynos4210CombinerState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+
+    struct CombinerGroupState group[IIC_NGRP];
+    uint32_t reg_set[IIC_REGSET_SIZE];
+    uint32_t icipsr[2];
+    uint32_t external;          /* 1 means that this combiner is external */
+
+    qemu_irq output_irq[IIC_NGRP];
+};
+
+#endif
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     }
 
     /* Internal Interrupt Combiner */
-    dev = qdev_new("exynos4210.combiner");
-    busdev = SYS_BUS_DEVICE(dev);
-    sysbus_realize_and_unref(busdev, &error_fatal);
+    busdev = SYS_BUS_DEVICE(&s->int_combiner);
+    sysbus_realize(busdev, &error_fatal);
     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
         sysbus_connect_irq(busdev, n,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
     }
-    exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
+    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 
     /* External Interrupt Combiner */
-    dev = qdev_new("exynos4210.combiner");
-    qdev_prop_set_uint32(dev, "external", 1);
-    busdev = SYS_BUS_DEVICE(dev);
-    sysbus_realize_and_unref(busdev, &error_fatal);
+    qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1);
+    busdev = SYS_BUS_DEVICE(&s->ext_combiner);
+    sysbus_realize(busdev, &error_fatal);
     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
     }
-    exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
+    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 
     /* Initialize board IRQs. */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
 
     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
     object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
+    object_initialize_child(obj, "int-combiner", &s->int_combiner,
+                            TYPE_EXYNOS4210_COMBINER);
+    object_initialize_child(obj, "ext-combiner", &s->ext_combiner,
+                            TYPE_EXYNOS4210_COMBINER);
 }
 
 static void exynos4210_class_init(ObjectClass *klass, void *data)
diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_combiner.c
+++ b/hw/intc/exynos4210_combiner.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "qemu/module.h"
-
+#include "hw/intc/exynos4210_combiner.h"
 #include "hw/arm/exynos4210.h"
 #include "hw/hw.h"
 #include "hw/irq.h"
@@ -XXX,XX +XXX,XX @@
 #define DPRINTF(fmt, ...) do {} while (0)
 #endif
 
-#define    IIC_NGRP        64            /* Internal Interrupt Combiner
-                                            Groups number */
-#define    IIC_NIRQ        (IIC_NGRP * 8)/* Internal Interrupt Combiner
-                                            Interrupts number */
 #define IIC_REGION_SIZE    0x108         /* Size of memory mapped region */
-#define IIC_REGSET_SIZE    0x41
-
-/*
- * State for each output signal of internal combiner
- */
-typedef struct CombinerGroupState {
-    uint8_t src_mask;            /* 1 - source enabled, 0 - disabled */
-    uint8_t src_pending;        /* Pending source interrupts before masking */
-} CombinerGroupState;
-
-#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
-
-struct Exynos4210CombinerState {
-    SysBusDevice parent_obj;
-
-    MemoryRegion iomem;
-
-    struct CombinerGroupState group[IIC_NGRP];
-    uint32_t reg_set[IIC_REGSET_SIZE];
-    uint32_t icipsr[2];
-    uint32_t external;          /* 1 means that this combiner is external */
-
-    qemu_irq output_irq[IIC_NGRP];
-};
 
 static const VMStateDescription vmstate_exynos4210_combiner_group_state = {
     .name = "exynos4210.combiner.groupstate",
-- 
2.25.1

The only time we use the int_combiner_irq[] and ext_combiner_irq[]
arrays in the Exynos4210Irq struct is during realize of the SoC -- we
initialize them with the input IRQs of the combiner devices, and then
connect those to outputs of other devices in
exynos4210_init_board_irqs().  Now that the combiner objects are
easily accessible as s->int_combiner and s->ext_combiner we can make
the connections directly from one device to the other without going
via these arrays.

Since these are the only two remaining elements of Exynos4210Irq,
we can remove that struct entirely.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-19-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  6 ------
 hw/arm/exynos4210.c         | 34 ++++++++--------------------------
 2 files changed, 8 insertions(+), 32 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
  */
 #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
 
-typedef struct Exynos4210Irq {
-    qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
-    qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
-} Exynos4210Irq;
-
 struct Exynos4210State {
     /*< private >*/
     SysBusDevice parent_obj;
     /*< public >*/
     ARMCPU *cpu[EXYNOS4210_NCPUS];
-    Exynos4210Irq irqs;
     qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 
     MemoryRegion chipid_mem;
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline)
 static void exynos4210_init_board_irqs(Exynos4210State *s)
 {
     uint32_t grp, bit, irq_id, n;
-    Exynos4210Irq *is = &s->irqs;
     DeviceState *extgicdev = DEVICE(&s->ext_gic);
+    DeviceState *intcdev = DEVICE(&s->int_combiner);
+    DeviceState *extcdev = DEVICE(&s->ext_combiner);
     int splitcount = 0;
     DeviceState *splitter;
     const int *mapline;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
         splitin = 0;
         for (;;) {
             s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
-            qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]);
-            qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]);
+            qdev_connect_gpio_out(splitter, splitin,
+                                  qdev_get_gpio_in(intcdev, in));
+            qdev_connect_gpio_out(splitter, splitin + 1,
+                                  qdev_get_gpio_in(extcdev, in));
             splitin += 2;
             if (!mapline) {
                 break;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
             qdev_realize(splitter, NULL, &error_abort);
             splitcount++;
             s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
-            qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
+            qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n));
             qdev_connect_gpio_out(splitter, 1,
                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
         } else {
-            s->irq_table[n] = is->int_combiner_irq[n];
+            s->irq_table[n] = qdev_get_gpio_in(intcdev, n);
         }
     }
     /*
@@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
     return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
 }
 
-/*
- * Get Combiner input GPIO into irqs structure
- */
-static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
-                                           DeviceState *dev, int ext)
-{
-    int n;
-    int max;
-    qemu_irq *irq;
-
-    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
-        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
-    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
-
-    for (n = 0; n < max; n++) {
-        irq[n] = qdev_get_gpio_in(dev, n);
-    }
-}
-
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
         sysbus_connect_irq(busdev, n,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
     }
-    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 
     /* External Interrupt Combiner */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
     }
-    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 
     /* Initialize board IRQs. */
-- 
2.25.1

From: Zongyuan Li <zongyuan.li@smartx.com>

Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/realview.c | 33 ++++++++++++++++++++++++---------
 1 file changed, 24 insertions(+), 9 deletions(-)

diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
+#include "hw/core/split-irq.h"
 #include "hw/net/lan9118.h"
 #include "hw/net/smc91c111.h"
 #include "hw/pci/pci.h"
+#include "hw/qdev-core.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "hw/boards.h"
@@ -XXX,XX +XXX,XX @@ static const int realview_board_id[] = {
     0x76d
 };
 
+static void split_irq_from_named(DeviceState *src, const char* outname,
+                                 qemu_irq out1, qemu_irq out2) {
+    DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
+
+    qdev_prop_set_uint32(splitter, "num-lines", 2);
+
+    qdev_realize_and_unref(splitter, NULL, &error_fatal);
+
+    qdev_connect_gpio_out(splitter, 0, out1);
+    qdev_connect_gpio_out(splitter, 1, out2);
+    qdev_connect_gpio_out_named(src, outname, 0,
+                                qdev_get_gpio_in(splitter, 0));
+}
+
 static void realview_init(MachineState *machine,
                           enum realview_board_type board_type)
 {
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
     DeviceState *dev, *sysctl, *gpio2, *pl041;
     SysBusDevice *busdev;
     qemu_irq pic[64];
-    qemu_irq mmc_irq[2];
     PCIBus *pci_bus = NULL;
     NICInfo *nd;
     DriveInfo *dinfo;
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
      * and the PL061 has them the other way about. Also the card
      * detect line is inverted.
      */
-    mmc_irq[0] = qemu_irq_split(
-        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
-        qdev_get_gpio_in(gpio2, 1));
-    mmc_irq[1] = qemu_irq_split(
-        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
-        qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
-    qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]);
-    qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]);
+    split_irq_from_named(dev, "card-read-only",
+                   qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
+                   qdev_get_gpio_in(gpio2, 1));
+
+    split_irq_from_named(dev, "card-inserted",
+                   qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
+                   qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
+
     dinfo = drive_get(IF_SD, 0, 0);
     if (dinfo) {
         DeviceState *card;
-- 
2.25.1

From: Zongyuan Li <zongyuan.li@smartx.com>

Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
+#include "hw/core/split-irq.h"
 #include "hw/sysbus.h"
 #include "hw/sd/sd.h"
 #include "hw/ssi/ssi.h"
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
             DeviceState *ssddev;
             DriveInfo *dinfo;
             DeviceState *carddev;
+            DeviceState *gpio_d_splitter;
             BlockBackend *blk;
 
             /*
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
                                    &error_fatal);
 
             ssddev = ssi_create_peripheral(bus, "ssd0323");
-            gpio_out[GPIO_D][0] = qemu_irq_split(
-                    qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
+
+            gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
+            qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
+            qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
+            qdev_connect_gpio_out(
+                    gpio_d_splitter, 0,
+                    qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0));
+            qdev_connect_gpio_out(
+                    gpio_d_splitter, 1,
                     qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
+            gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0);
+
             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
 
             /* Make sure the select pin is high.  */
-- 
2.25.1

From: Zongyuan Li <zongyuan.li@smartx.com>

Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/irq.h |  5 -----
 hw/core/irq.c    | 15 ---------------
 2 files changed, 20 deletions(-)

diff --git a/include/hw/irq.h b/include/hw/irq.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq);
 /* Returns a new IRQ with opposite polarity.  */
 qemu_irq qemu_irq_invert(qemu_irq irq);
 
-/* Returns a new IRQ which feeds into both the passed IRQs.
- * It's probably better to use the TYPE_SPLIT_IRQ device instead.
- */
-qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
-
 /* For internal use in qtest.  Similar to qemu_irq_split, but operating
    on an existing vector of qemu_irq.  */
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
diff --git a/hw/core/irq.c b/hw/core/irq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_invert(qemu_irq irq)
     return qemu_allocate_irq(qemu_notirq, irq, 0);
 }
 
-static void qemu_splitirq(void *opaque, int line, int level)
-{
-    struct IRQState **irq = opaque;
-    irq[0]->handler(irq[0]->opaque, irq[0]->n, level);
-    irq[1]->handler(irq[1]->opaque, irq[1]->n, level);
-}
-
-qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
-{
-    qemu_irq *s = g_new0(qemu_irq, 2);
-    s[0] = irq1;
-    s[1] = irq2;
-    return qemu_allocate_irq(qemu_splitirq, s, 0);
-}
-
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
 {
     int i;
-- 
2.25.1

From: Hao Wu <wuhaotsh@google.com>

Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
the PWRON STRAP fields in their corresponding module for NPCM7XX.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20220411165842.3912945-2-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_gcr.h
+++ b/include/hw/misc/npcm7xx_gcr.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/memory.h"
 #include "hw/sysbus.h"
 
+/*
+ * NPCM7XX PWRON STRAP bit fields
+ * 12: SPI0 powered by VSBV3 at 1.8V
+ * 11: System flash attached to BMC
+ * 10: BSP alternative pins.
+ * 9:8: Flash UART command route enabled.
+ * 7: Security enabled.
+ * 6: HI-Z state control.
+ * 5: ECC disabled.
+ * 4: Reserved
+ * 3: JTAG2 enabled.
+ * 2:0: CPU and DRAM clock frequency.
+ */
+#define NPCM7XX_PWRON_STRAP_SPI0F18                 BIT(12)
+#define NPCM7XX_PWRON_STRAP_SFAB                    BIT(11)
+#define NPCM7XX_PWRON_STRAP_BSPA                    BIT(10)
+#define NPCM7XX_PWRON_STRAP_FUP(x)                  ((x) << 8)
+#define     FUP_NORM_UART2      3
+#define     FUP_PROG_UART3      2
+#define     FUP_PROG_UART2      1
+#define     FUP_NORM_UART3      0
+#define NPCM7XX_PWRON_STRAP_SECEN                   BIT(7)
+#define NPCM7XX_PWRON_STRAP_HIZ                     BIT(6)
+#define NPCM7XX_PWRON_STRAP_ECC                     BIT(5)
+#define NPCM7XX_PWRON_STRAP_RESERVE1                BIT(4)
+#define NPCM7XX_PWRON_STRAP_J2EN                    BIT(3)
+#define NPCM7XX_PWRON_STRAP_CKFRQ(x)                (x)
+#define     CKFRQ_SKIPINIT      0x000
+#define     CKFRQ_DEFAULT       0x111
+
 /*
  * Number of registers in our device state structure. Don't change this without
  * incrementing the version_id in the vmstate.
-- 
2.25.1

From: Hao Wu <wuhaotsh@google.com>

This patch uses the defined fields to describe PWRON STRAPs for
better readability.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20220411165842.3912945-3-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm7xx_boards.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "sysemu/block-backend.h"
 
-#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
-#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
-#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff
-#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff
-#define MORI_BMC_POWER_ON_STRAPS 0x00001fff
+#define NPCM7XX_POWER_ON_STRAPS_DEFAULT (           \
+        NPCM7XX_PWRON_STRAP_SPI0F18 |               \
+        NPCM7XX_PWRON_STRAP_SFAB |                  \
+        NPCM7XX_PWRON_STRAP_BSPA |                  \
+        NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) |   \
+        NPCM7XX_PWRON_STRAP_SECEN |                 \
+        NPCM7XX_PWRON_STRAP_HIZ |                   \
+        NPCM7XX_PWRON_STRAP_ECC |                   \
+        NPCM7XX_PWRON_STRAP_RESERVE1 |              \
+        NPCM7XX_PWRON_STRAP_J2EN |                  \
+        NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT))
+
+#define NPCM750_EVB_POWER_ON_STRAPS ( \
+        NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN)
+#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
+#define QUANTA_GBS_POWER_ON_STRAPS ( \
+        NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
+#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
+#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
 
 static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
 
-- 
2.25.1