[v5] target/arm: Honor more HCR_EL2 traps

[PATCH v5 00/12] target/arm: Honor more HCR_EL2 traps

Richard Henderson posted 12 patches 5 years, 8 months ago

Diff against v3 v4
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git fetch https://github.com/patchew-project/qemu tags/patchew/20200229012811.24129-1-richard.henderson@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>

target/arm/cpu.h            |   7 +
target/arm/cpu.c            |  12 +-
target/arm/helper.c         | 358 +++++++++++++++++++++++++-----------
tests/tcg/aarch64/pauth-1.c |   2 +-
4 files changed, 262 insertions(+), 117 deletions(-)

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[PATCH v5 00/12] target/arm: Honor more HCR_EL2 traps

Posted by Richard Henderson 5 years, 8 months ago

Changes for v5:
  * Patch 1 was broken for aa32.  Not just the masking vs the "other"
    32-bit register that Peter noticed, but more explicitly in that
    "ri" was dereferenced as NULL -- hcr_write{high,low} did not pass
    along the structure.  Oops.

    Break out a new helper that is passed a starting mask, which is
    used to preserve bits from the "other" 32-bit register.

    Check the aa64 isar registers only if aarch64 is enabled.

  * Add HCR bits from armv8.6.
  * Remove EL2 & EL3 from user-only.

  * Mask hcr_el2 bits that are res0 in aa32.
    This didn't work at first because we weren't configuring SCR_RW
    for user-only, so aarch64-linux-user thought EL2 was aa32, which
    disabled pauth.  Rather than find other corner cases like this,
    I think it makes more sense for user-only to only contend with EL1.

Patches 1-5, 12 require review.


r~


Richard Henderson (12):
  target/arm: Improve masking of HCR/HCR2 RES0 bits
  target/arm: Add HCR_EL2 bit definitions from ARMv8.6
  target/arm: Disable has_el2 and has_el3 for user-only
  target/arm: Remove EL2 and EL3 setup from user-only
  target/arm: Improve masking in arm_hcr_el2_eff
  target/arm: Honor the HCR_EL2.{TVM,TRVM} bits
  target/arm: Honor the HCR_EL2.TSW bit
  target/arm: Honor the HCR_EL2.TACR bit
  target/arm: Honor the HCR_EL2.TPCP bit
  target/arm: Honor the HCR_EL2.TPU bit
  target/arm: Honor the HCR_EL2.TTLB bit
  tests/tcg/aarch64: Add newline in pauth-1 printf

 target/arm/cpu.h            |   7 +
 target/arm/cpu.c            |  12 +-
 target/arm/helper.c         | 358 +++++++++++++++++++++++++-----------
 tests/tcg/aarch64/pauth-1.c |   2 +-
 4 files changed, 262 insertions(+), 117 deletions(-)

-- 
2.20.1

Re: [PATCH v5 00/12] target/arm: Honor more HCR_EL2 traps

Posted by Peter Maydell 5 years, 8 months ago

On Sat, 29 Feb 2020 at 01:28, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Changes for v5:
>   * Patch 1 was broken for aa32.  Not just the masking vs the "other"
>     32-bit register that Peter noticed, but more explicitly in that
>     "ri" was dereferenced as NULL -- hcr_write{high,low} did not pass
>     along the structure.  Oops.
>
>     Break out a new helper that is passed a starting mask, which is
>     used to preserve bits from the "other" 32-bit register.
>
>     Check the aa64 isar registers only if aarch64 is enabled.
>
>   * Add HCR bits from armv8.6.
>   * Remove EL2 & EL3 from user-only.
>
>   * Mask hcr_el2 bits that are res0 in aa32.
>     This didn't work at first because we weren't configuring SCR_RW
>     for user-only, so aarch64-linux-user thought EL2 was aa32, which
>     disabled pauth.  Rather than find other corner cases like this,
>     I think it makes more sense for user-only to only contend with EL1.
>
> Patches 1-5, 12 require review.

Applied to target-arm.next, thanks.

-- PMM