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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f02zxp7l+Sqo1gI6cxnt5pVpIauWmflCG9BwYQEIz+Q=; b=gq+2nEB6tyfr3suuUaJuiFLEN8m1kb2LsIfDX2ppB3XERpvWN0o0Ta5vf0DLZlxshs BREHJsZvV98bBlvrXdZGiMAGIuPTx5xr4QN/l+QRfFHHUnRLCXSlEM7UhxAM6Rxw9MIy 30ULRp743uMLYPFflyx12tJ6TO4FPVm+N3iFQSCKMxwbe8UMTF4ll1YRDkAqrA21pp+k B8wJLfOdGQvSfH1c63nwVWPvg/Zw4Gm4gvo9snbqd2Qn4kZsZliAeAEQsJZo07/WEJYN IIp1HdTZyoi3jmo4we5EGhkK23OtfzPeCkQFEMkWOfY/d5I09xMt11/aTF9YRNjExjtR hkxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f02zxp7l+Sqo1gI6cxnt5pVpIauWmflCG9BwYQEIz+Q=; b=SH1pKHWPPdn82g2Sm+5NuRh+Zvuotx+9zC549B/FM0pWcTc0cIZa303YlJ/aVJIDPe yH/oLiz/IpNPUr3XpcGGfLYuPHETTSc6yZHq6LG+hHpBPQ/FZYomgzfhWVHHMoVutGvG yPDEvsc2MgvHpt8W0Wn+vStq9qoouWl4d4OZ24VNkc3y4Ty9OtUnm9DULob4Qpk0WfTV UHQbXPM6GIWq94gDG+bmoHlokpaF0nx4Js9IBCVIRMRcrmyhkKETkvIjSuF9b4onGfJy 9ujh7OMCabpJAtAGSFh0eDdPiJjzw/EGIvIoDWWWGQ0mUmI5VP05VunYYMApuznJgh1z HF6w== X-Gm-Message-State: APjAAAUVFvuhvFoZTrhT12CURV31voQMhlMu9gc3PulHdb0Rct+GhWdq 1ZKPC28ubG2LmjSMnL72nqLVkwx6hVw= X-Google-Smtp-Source: APXvYqxH7PSKC4OcarpZEGhN7oFImq/RUYYrC+yzfnFAc3KtGTxFJlhTw/jt3SmGCco1/b6pUEAoYg== X-Received: by 2002:a62:f247:: with SMTP id y7mr7062056pfl.5.1582939696093; Fri, 28 Feb 2020 17:28:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 01/12] target/arm: Improve masking of HCR/HCR2 RES0 bits Date: Fri, 28 Feb 2020 17:28:00 -0800 Message-Id: <20200229012811.24129-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Don't merely start with v8.0, handle v7VE as well. Ensure that writes from aarch32 mode do not change bits in the other half of the register. Protect reads of aa64 id registers with ARM_FEATURE_AARCH64. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 38 +++++++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6be9ffa09e..e68e16b85b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5086,11 +5086,15 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[= ] =3D { REGINFO_SENTINEL }; =20 -static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) { ARMCPU *cpu =3D env_archcpu(env); - /* Begin with bits defined in base ARMv8.0. */ - uint64_t valid_mask =3D MAKE_64BIT_MASK(0, 34); + + if (arm_feature(env, ARM_FEATURE_V8)) { + valid_mask |=3D MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ + } else { + valid_mask |=3D MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ + } =20 if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &=3D ~HCR_HCD; @@ -5104,14 +5108,17 @@ static void hcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) */ valid_mask &=3D ~HCR_TSC; } - if (cpu_isar_feature(aa64_vh, cpu)) { - valid_mask |=3D HCR_E2H; - } - if (cpu_isar_feature(aa64_lor, cpu)) { - valid_mask |=3D HCR_TLOR; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - valid_mask |=3D HCR_API | HCR_APK; + + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + if (cpu_isar_feature(aa64_vh, cpu)) { + valid_mask |=3D HCR_E2H; + } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |=3D HCR_TLOR; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + valid_mask |=3D HCR_API | HCR_APK; + } } =20 /* Clear RES0 bits. */ @@ -5143,12 +5150,17 @@ static void hcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) arm_cpu_update_vfiq(cpu); } =20 +static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + do_hcr_write(env, value, 0); +} + static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ value =3D deposit64(env->cp15.hcr_el2, 32, 32, value); - hcr_write(env, NULL, value); + do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); } =20 static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, @@ -5156,7 +5168,7 @@ static void hcr_writelow(CPUARMState *env, const ARMC= PRegInfo *ri, { /* Handle HCR write, i.e. write to low half of HCR_EL2 */ value =3D deposit64(env->cp15.hcr_el2, 0, 32, value); - hcr_write(env, NULL, value); + do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); } =20 /* --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=15dGinytmIYJq1+1xe7e6vb7+URJHdY4dHT+WNni3JI=; b=a6u/iGa1oErJitQ224lJ8kY4ser0SN/V7YDITWcENvTLWsTQkxXuCuSYwECyOT6Fft weW7wJhhublhXfn2yLlcv7ClAxeXHvf73rHlrrKBtHsEZOemLohF6Nzq6q/lqQ2px2Ji xaEoB9G9GB1VqohQrMk5wp///AtQPURef5MY/WY0iaBscjVYIY9yAnzewUenPCrf6uec Thha871GE/H9N0uuYzbEVNkx0kAv1bRbYOVyp1nF3VQQ97uzSOrUJ8IZ89LFjJo+xd4j sWJfFoEqrR6zgw40ouMP+w0jcbAkU8iRNkDvToXe2xEbOCC1klLpoM6xXwA2X05RROAU XncA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=15dGinytmIYJq1+1xe7e6vb7+URJHdY4dHT+WNni3JI=; b=SXMgVpRN8582IEpp6QhwkOdw8q59/MlR7lfWFpVifEmX/Ol5H6pKKGRFsThXQGjIij 3Y0Bs0rdMGA1+YdfiargtmptDiQ93yGVUqetRGiJElib+eNxvy/xi38BoHBkM20gy5F5 U7UuaN2UCQ9egulGVJEmZH9IYPpzF2K1iZIlCLAV+b4o1W8I4hQ4Xq/iHP4DqIsFtF1J y7ux9JXpiwf6XA3+9qo99V9bi92+N9iWYTRJmdPElHayif8jXYV0D/2m0mbjp+vPYLGd ECAgd/2NgvblRMK1/b4FYMER5riBPRvF5hI4bqSxAsBXoXhUYTcplFy3BWdWAOvkYOjf 1tAA== X-Gm-Message-State: APjAAAUJhfncB0RGvIIJb1H04elDtnYGcRXR1EZ3rzpuI/kUz05Di4HL e6FI3gq3LxC/PPHNpDJa4onAzzYSkmw= X-Google-Smtp-Source: APXvYqy9TkuAsCssihXWmiBSR26dvwhgnENeHA60MQxtB3ujLg65Uwsr2qsTouDwFI8sTiAFvUKJkw== X-Received: by 2002:a62:f842:: with SMTP id c2mr7230735pfm.104.1582939697381; Fri, 28 Feb 2020 17:28:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 02/12] target/arm: Add HCR_EL2 bit definitions from ARMv8.6 Date: Fri, 28 Feb 2020 17:28:01 -0800 Message-Id: <20200229012811.24129-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0b84742b66..0ae07a72e4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1410,6 +1410,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define HCR_TERR (1ULL << 36) #define HCR_TEA (1ULL << 37) #define HCR_MIOCNCE (1ULL << 38) +/* RES0 bit 39 */ #define HCR_APK (1ULL << 40) #define HCR_API (1ULL << 41) #define HCR_NV (1ULL << 42) @@ -1418,13 +1419,19 @@ static inline void xpsr_write(CPUARMState *env, uin= t32_t val, uint32_t mask) #define HCR_NV2 (1ULL << 45) #define HCR_FWB (1ULL << 46) #define HCR_FIEN (1ULL << 47) +/* RES0 bit 48 */ #define HCR_TID4 (1ULL << 49) #define HCR_TICAB (1ULL << 50) +#define HCR_AMVOFFEN (1ULL << 51) #define HCR_TOCU (1ULL << 52) +#define HCR_ENSCXT (1ULL << 53) #define HCR_TTLBIS (1ULL << 54) #define HCR_TTLBOS (1ULL << 55) #define HCR_ATA (1ULL << 56) #define HCR_DCT (1ULL << 57) +#define HCR_TID5 (1ULL << 58) +#define HCR_TWEDEN (1ULL << 59) +#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) =20 #define SCR_NS (1U << 0) #define SCR_IRQ (1U << 1) --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582939917; cv=none; d=zohomail.com; s=zohoarc; b=TJ6mu7trT9xHZEzGKpTGY7+tRemHW0MFNvZdkcQdkE/QerXVwTXAlOqEbXVYPIzishVsM5khJ+ouVA/9EuBjDSMBS6eFFESMlcwrdSjJmnCVsq+PXlJndsPb58Ll/oA8WcL44CAajnAqJeTr9GG5K+L1KgsaPd/UMz9xINaRSsM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582939917; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QpMHNZIbcT5PzqjajR8IDp8eTMJQTzdyuvxjhrMoYDc=; b=C5AdYPGRS78AKkSURLdKDscGlSeOpolZowHwFz9jCdosx4aCDLtADOyXUKJg+12n6RlAmJdoIgm3HhqwGdptj0z7jpsKefL53gpK8vNV1IPEp5faQ1btllnN7VOv9jv1HYGjL0ugDqGD4tFdjbbuCSLl0WktUaohQiJCSlu/BqM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582939917937899.7140041038883; Fri, 28 Feb 2020 17:31:57 -0800 (PST) Received: from localhost ([::1]:55890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qyy-0003Lg-Nv for importer@patchew.org; Fri, 28 Feb 2020 20:31:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36985) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qvW-0004kZ-67 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7qvV-00060b-2b for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:22 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:44139) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7qvU-0005z8-SX for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:21 -0500 Received: by mail-pl1-x641.google.com with SMTP id d9so1900247plo.11 for ; Fri, 28 Feb 2020 17:28:19 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QpMHNZIbcT5PzqjajR8IDp8eTMJQTzdyuvxjhrMoYDc=; b=YY2Mz0sznUyzLkAu1ttdhi9ccja2VcdZ72zNGleYvo831HwzPkcs197oPmgr6em6O2 LZJH/O75OrxN2+rDi1nF+8SgvkWTYd5qQpCArvjePBcriTVbzyLidObarP1f4M1+jcn/ Y6PhNuae4pAmb56QmYcCVgpy7FzESM3dM7H5LCOStgueezcuczF2mTSszdceXTpUlYN1 LeupHVsARLhHvRKtTZ7P8LZBoszOakQUg1se3av9J4n95a3xHEMB3joKVLtdQuyH8A+G 3ED8dUat1+2kN1KLcCFtppx8Jf7p7OxzaZqbTqTQWkMOhCRtjuYNG4ZShvVPj+hlc5K0 EXxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QpMHNZIbcT5PzqjajR8IDp8eTMJQTzdyuvxjhrMoYDc=; b=ZNG2fZUWQUIwRKUd2HhY9gdr9ZJhfzd+4tEyl6TnK6jt0G1mosDHsi0xQmtIStzGTJ C7tdOtsDhy0W5sMvfIdxtUjP4gvqiTgrumNqSuqfP7720TSCuiqnu0Ya2WQpQRhR84KT D6TKcytVX1p+/WAaIhQmjbQZLHA9KXcYTR6pwSNEm/mPEJPZP51M1T+Uk9lTWz909JlX TInLYOlfaK3q/JRP45gU8VoXffNk9bmTDDiPjDNQPPRRQqcIr5WSa4SdRlPu2K912Ynx lVmukTpn8wSxqNSBBAe/ts6AiqMh3UpF10rCBqr80LCbRFkad9rUY/VpyVsAK++7oq7m +mCw== X-Gm-Message-State: APjAAAVrzDhwCKKwm9RT5mNM47xm0eCAZAJfsI3YOFeq7VUINDw+EyGn 9jZpPchHb1gVHSmR+a7ekBZWKlcy4kU= X-Google-Smtp-Source: APXvYqwkCjGMdstyhYyogHKj1DoGDKawMt7g65hy7zFiuS6OCr+vn78moluMw3RJ/Ct23OF2b8DJXw== X-Received: by 2002:a17:90b:243:: with SMTP id fz3mr7826522pjb.29.1582939698546; Fri, 28 Feb 2020 17:28:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 03/12] target/arm: Disable has_el2 and has_el3 for user-only Date: Fri, 28 Feb 2020 17:28:02 -0800 Message-Id: <20200229012811.24129-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In arm_cpu_reset, we configure many system registers so that user-only behaves as it should with a minimum of ifdefs. However, we do not set all of the system registers as required for a cpu with EL2 and EL3. Disabling EL2 and EL3 mean that we will not look at those registers, which means that we don't have to worry about configuring them. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e6016e33ce..33c28fe868 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1103,11 +1103,13 @@ static Property arm_cpu_reset_hivecs_property =3D static Property arm_cpu_rvbar_property =3D DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); =20 +#ifndef CONFIG_USER_ONLY static Property arm_cpu_has_el2_property =3D DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); =20 static Property arm_cpu_has_el3_property =3D DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); +#endif =20 static Property arm_cpu_cfgend_property =3D DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); @@ -1222,25 +1224,25 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); } =20 +#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { /* Add the has_el3 state CPU property only if EL3 is allowed. Thi= s will * prevent "has_el3" from existing on CPUs which cannot support EL= 3. */ qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); =20 -#ifndef CONFIG_USER_ONLY object_property_add_link(obj, "secure-memory", TYPE_MEMORY_REGION, (Object **)&cpu->secure_memory, qdev_prop_allow_set_link_before_realize, OBJ_PROP_LINK_STRONG, &error_abort); -#endif } =20 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); } +#endif =20 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { cpu->has_pmu =3D true; --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582939777; cv=none; d=zohomail.com; s=zohoarc; b=QLZdvVytuT4nRdldcdpGg5a3ygb1sq0trsWVr9Bna0FPOgh6S3KBoyLZPjeYUGrH5/ZfjeOEBlfi7JPZkHeMC/4xyxCHKf6NZdh6pziw1FLd49SvKp+MGnBQSBynp5WOXMnNrS38l7822bLUHXOLHSogIR4+uXcOtHvKZ8mZLrM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582939777; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lD3FYS9OIbqt/7rZmxRR9Ucvpf5WCTg8Pk1gx8FKewE=; b=aFCwe74dyD9Ln/H3JmsYXA0TRTbYCN8OJYLS5R3KP9lld0Ju9Ig3JpBhLWM5jUirib/4DxZTXWwH/BqJLEqZVEEFPAfoR4PuYEQ/mxvRKuyPqnfY0n98DNO2k0y9Q/hKY6yymCUi2xaQG8O2aHMDao22cGZ3YKx1nQ3APQXjB9E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582939777211396.6362116812053; Fri, 28 Feb 2020 17:29:37 -0800 (PST) Received: from localhost ([::1]:55794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qwh-0006qQ-Ms for importer@patchew.org; Fri, 28 Feb 2020 20:29:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:36990) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qvW-0004kt-BO for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7qvV-00060k-CJ for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:22 -0500 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:37814) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7qvV-000608-7O for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:21 -0500 Received: by mail-pj1-x1043.google.com with SMTP id o2so67187pjp.2 for ; Fri, 28 Feb 2020 17:28:21 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lD3FYS9OIbqt/7rZmxRR9Ucvpf5WCTg8Pk1gx8FKewE=; b=TvRi+YXcZh9gcJikXK9coMz/2htbtC9rHOisjlUaVrG63xZ3frhynSwcyMQDvAXS34 Nz24MnTDsoq6FtwQbQug/V7b2uj3Rtf+3fqYjn05ctDxwEEPpkqIdE7DZyj3waqix/at t4Ko+cXIJnxvay7RODwZhdmcxaJnT+o9CixVftYyEedMGZiUT0QSjr50+YbyVk7cpXoA VIzow+zV8UU0ocrDttICXwfrfhy93OONuZlm45rZtx/BH1PHXGWQVh1LmXq7ICQCzobe BVHCKX8BQas1pEcstmd4RsMG7ynaarQ+oZEaGqlhbIXULiHZBCUAIXY/2zJv8W1g65LV /pIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lD3FYS9OIbqt/7rZmxRR9Ucvpf5WCTg8Pk1gx8FKewE=; b=aDbNGXANU/fCCi2ovucbUbEK8+IitkeNppYL0f/C7BYizc9kONFt5A/EnsAB6WxTEf 0fDLSn7Kzg/AEAvYahnthHDcfC0rKcg0lQerSwajTqMVtzMFTEv2CgDeq1ZhTlS5ApKp 9b8C6Gjk9bQyUsr7yHmO9NxElagFk3oKm0urAuvujb1qTQcWBzWJ4Lv56wJXIaIvoRbW ixGwLeQdVmst6MsvYskF6YUE9R8RkGVoF4vTmzTQEtdd1MpWFfTgcXRJT7OZjwVJ29Xt MqWt6RR8lWeBda6BBoP9SFt8pWPjr66jqGkMLbkoRhiDp5UQXz3YlmFZwIbeM1+Up09z HZuA== X-Gm-Message-State: APjAAAVROOdH6JdVAWowYOXs4kqZgJew8gOvcYfpvb6NDGr7JduMFuIB 5qo5mErfHyTZDgW2tfx6s5+BcYvp6j8= X-Google-Smtp-Source: APXvYqw5uR3jvCpfNT8/CxYprqUDl+y9pACxnaEH92QuUahNJGDKMn4fR9B5R10iQEqCNVB0piZNGA== X-Received: by 2002:a17:902:523:: with SMTP id 32mr6715470plf.148.1582939699893; Fri, 28 Feb 2020 17:28:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 04/12] target/arm: Remove EL2 and EL3 setup from user-only Date: Fri, 28 Feb 2020 17:28:03 -0800 Message-Id: <20200229012811.24129-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1043 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We have disabled EL2 and EL3 for user-only, which means that these registers "don't exist" and should not be set. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 33c28fe868..af541431e6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -191,19 +191,13 @@ static void arm_cpu_reset(CPUState *s) /* Enable all PAC keys. */ env->cp15.sctlr_el[1] |=3D (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB); - /* Enable all PAC instructions */ - env->cp15.hcr_el2 |=3D HCR_API; - env->cp15.scr_el3 |=3D SCR_API; /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 20, 2, 3); /* and to the SVE instructions */ env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 16, 2, 3); - env->cp15.cptr_el[3] |=3D CPTR_EZ; /* with maximum vector length */ env->vfp.zcr_el[1] =3D cpu_isar_feature(aa64_sve, cpu) ? cpu->sve_max_vq - 1 : 0; - env->vfp.zcr_el[2] =3D env->vfp.zcr_el[1]; - env->vfp.zcr_el[3] =3D env->vfp.zcr_el[1]; /* * Enable TBI0 and TBI1. While the real kernel only enables TBI0, * turning on both here will produce smaller code and otherwise --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582939789; cv=none; d=zohomail.com; s=zohoarc; b=cTZl31uNk8vJ8RM255EKZcaF76jly1oWk3iCkX3hIaV36qMveLMolZH71hWQHVIu/CqMfD6lSGHWzUnZXhJ8N1/MKfKHyMf8YOYOZDEJeau55T7PSBv1RYG0aDBN/BK7uaiv4UOB6JoabunhaRSz9ashsvAGb4rqvXa/BHt1P6c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582939789; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mxAcyusf4U5zXXtEjloBwTbqgFt78dWHMSy3qfj6epQ=; b=CKtd4K6SoZmv88pRUwj8DBnkecHuf2Pv/iHSDHpmyRgVVamFgUGpz+N9p42z5fSMLQILJOXgZZ6Z3mOwJiHW6+8eVyJ4vH7jmSMUU5SGpgVfuQEWPZgpwfGyYyzM7ZlOpdzdS33Z5LN2eoWFySwpMJKIo4kCcntyp8V5QBKBCXk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582939789195882.4520312242934; Fri, 28 Feb 2020 17:29:49 -0800 (PST) Received: from localhost ([::1]:55798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qwt-0007BL-Ox for importer@patchew.org; Fri, 28 Feb 2020 20:29:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37027) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qvX-0004nI-KD for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7qvW-00061c-Hi for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:23 -0500 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:37815) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7qvW-00060v-C9 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:22 -0500 Received: by mail-pj1-x1044.google.com with SMTP id o2so67206pjp.2 for ; Fri, 28 Feb 2020 17:28:22 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mxAcyusf4U5zXXtEjloBwTbqgFt78dWHMSy3qfj6epQ=; b=kC4x9yELE0eX35wwUWRIifYggbo9L7N656Qz267eMcpSg3z+VZP+kzXpacnrDpqAzs NbpnH72gZchXusZ7NXLHwPsAF/ks4ClutNc68Mpz6LEXRETnhFHNIBU+XLJAT8QOFqZ6 mTb/WqfrH8jaf+u9LTeeH+T5FzqYK1CtoDRBuA4DZy19ZDmJA440ood0BCrxs0jYZkVB cvO5Mo87wR3Ty4GjetisAnzlYTIfAygcmOhFEbB7pPsj/XqhmuLr+KHrDKC69xdceCYR XD+csDvBI00NXmgXbhMCx5j3rajWotb8T+UukWjj6LPx1JXkMefbvom0z/thaXyk65Nv WHUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mxAcyusf4U5zXXtEjloBwTbqgFt78dWHMSy3qfj6epQ=; b=YtWl6Nm5u1RbJxX5zQVdsjnGMTMxi7/kDqP6vzCLzkuUOMs5fWV+VOApXtZCWXNzOZ OZAt/tA8t3V5APFTXei3o6C7SZuVEGoM+GDVqMBa8kOKJX0cEwOrWO0La2krUpHWHuKl xmGkXL/mwBpOs1LBBaWMkjAPbAQLacS7oCNr+gBXO6VTiISLv9i8DkDLVCwQ34Tzlfjc o+JzTFTPstH4guVLmlQDtInGF89udtpsuk0YMPB3/skcYoERT26hN38bGoQ35xwrWJc+ K22W9Fm698GAjGTzHKPbvfarJ7JiTafyxjlREj7aV3bLz73a5A5cFQigVGkLmd6oCPz/ 9vhA== X-Gm-Message-State: APjAAAVmy/sEgAnG/2MbMGCNghjzLW6KzTu/ZzQEvBpTHrV2/YzZkUEh RgOc2yl5cAhKlbgnoAYnuD/i4gB5PiY= X-Google-Smtp-Source: APXvYqwpkAshVZF92eAvC29ab0gq8iFGnhR5fbwx1SmUwlAGyRUtmbwtaFpEtV4eg7WmmY4hAw2HYw== X-Received: by 2002:a17:902:8308:: with SMTP id bd8mr6710737plb.210.1582939701020; Fri, 28 Feb 2020 17:28:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 05/12] target/arm: Improve masking in arm_hcr_el2_eff Date: Fri, 28 Feb 2020 17:28:04 -0800 Message-Id: <20200229012811.24129-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Update the {TGE,E2H} =3D=3D '11' masking to ARMv8.6. If EL2 is configured for aarch32, disable all of the bits that are RES0 in aarch32 mode. Signed-off-by: Richard Henderson --- target/arm/helper.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e68e16b85b..ef3f02d194 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5196,14 +5196,37 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) * Since the v8.4 language applies to the entire register, and * appears to be backward compatible, use that. */ - ret =3D 0; - } else if (ret & HCR_TGE) { - /* These bits are up-to-date as of ARMv8.4. */ + return 0; + } + + /* + * For a cpu that supports both aarch64 and aarch32, we can set bits + * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. + * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. + */ + if (!arm_el_is_aa64(env, 2)) { + uint64_t aa32_valid; + + /* + * These bits are up-to-date as of ARMv8.6. + * For HCR, it's easiest to list just the 2 bits that are invalid. + * For HCR2, list those that are valid. + */ + aa32_valid =3D MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); + aa32_valid |=3D (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNC= E | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); + ret &=3D aa32_valid; + } + + if (ret & HCR_TGE) { + /* These bits are up-to-date as of ARMv8.6. */ if (ret & HCR_E2H) { ret &=3D ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | - HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE); + HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | + HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); } else { ret |=3D HCR_FMO | HCR_IMO | HCR_AMO; } --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582939885; cv=none; d=zohomail.com; s=zohoarc; b=a+RzFSdQdFowSlUpy6Gto1ccdbR+Z/N0b4OptEgLD6OV3rmPbF+86K4tH9++cZCOhS42VjZ/z3fJ4YCto798NzMDS7hwW7jHfCANMuvf/BeOU9WKwZVse/85nWDtxKyT9w0REvhEK77MxIwR/zQDl3TUk+H+cfEg/eRolXJbLoI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582939885; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wtHqtEkFJI+2mWFKUf0vqbrWVBZN2VlKX8BKVOAKBhQ=; b=EVRNu4aTRkmjorkMsaiHP9JmZju8PXfoiVwg0L8l3BY8FZL31du6B4wm7L1vowGKYSHJHzwvCmpEOXECBco6JcqFcdGAJMOKrQNiB6dtzVdiJ6EYI4eAc2rJ8+bhfutqXUUX6e7XhTBRzHfVSsfxiMrEobMOK+0h+3z7WSuomBU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582939885234853.3410983967718; Fri, 28 Feb 2020 17:31:25 -0800 (PST) Received: from localhost ([::1]:55884 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qyR-0002MR-UQ for importer@patchew.org; Fri, 28 Feb 2020 20:31:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37064) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qva-0004rf-1H for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7qvY-00063d-2e for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:25 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:41253) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7qvX-00062Y-RO for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:24 -0500 Received: by mail-pg1-x543.google.com with SMTP id b1so2389295pgm.8 for ; Fri, 28 Feb 2020 17:28:23 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wtHqtEkFJI+2mWFKUf0vqbrWVBZN2VlKX8BKVOAKBhQ=; b=kE5h9o2k85UGFlu5CreKubXrnYeX6sAUdyhLI6T14OVgmENYMyKPvIHkL05yblWgQo 5JTGK91cvFagQDS5Je0ORV5UVQqyXB4zYpQzQY5bYhhEnFQAZ/UzCL+kAkQEY40fqGsF XzeDb3a8Vet7GKhJ82Mm/bJny6/aIgEO0+JYYEMBFCYW5o6U/QeT4LekapJKruqtV4wa DDRChmCjjO1cwMf3MIHNK3WGlOuOikckdAuZ8/CW+zLtLLuP6gbKb3/3SBK0KPFI40pc pIZ6PoCfVto2XRpaJm/39Q9RN/lB6D2v1j958W3dMLy2QfMHEv4fa5/2BnPwctFT0lz3 Nmlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wtHqtEkFJI+2mWFKUf0vqbrWVBZN2VlKX8BKVOAKBhQ=; b=qUo3JazY7IiriqLMhQjI3qincmgqYBRn3juxObgNo/IfS9zhdt23CLOqCM9H1i+e47 8HZwcRrQyHsjCwWY7R5WQI5efCpKXYEPfclB0ikqjDGK9KGQnbNon38rY9B4hyGbajzN kC8WHHNo9pt8tP6gcBQqnaFXWHGc3aTEtKyNd+4RCMkmHyARpf/y4NA8eO5lNW6JZJ2c ZdsyyTsr0jX6vNxW1dyUSGRjqcLfP5DtbzSkgNx/Ke+5ke05o3b4DDJF58iuL8+3qGS7 044vHAMaiiaW5qCRtwIBAYJyi8Mo3OLaSzYnxltvY+K3YtdG01e+Bag2tKTzl/gjXrxM ZN5Q== X-Gm-Message-State: APjAAAXJQkWu5gIyHfEWoSJ1xTUYo7u/bQReJzb3nkg4cIV+Tp4U8yXi Z8pfpZwn/nmQoIALV+DEYsB97vlJ1+U= X-Google-Smtp-Source: APXvYqyr+Q5gP70DnHhKtSQVhTO/5obWzUrkziWgGkU435hBa2EOv6Qx/6nMcjm5AON66Ie6EUyY4g== X-Received: by 2002:a63:d845:: with SMTP id k5mr7041765pgj.183.1582939702301; Fri, 28 Feb 2020 17:28:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 06/12] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits Date: Fri, 28 Feb 2020 17:28:05 -0800 Message-Id: <20200229012811.24129-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These bits trap EL1 access to various virtual memory controls. Buglink: https://bugs.launchpad.net/bugs/1855072 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Include TTBCR. v3: Include not_v8_cp_reginfo, lpae_cp_reginfo, CONTEXTIDR_S; exclude not_v7_cp_reginfo (pmm). --- target/arm/helper.c | 82 ++++++++++++++++++++++++++++++--------------- 1 file changed, 55 insertions(+), 27 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ef3f02d194..1f371b0391 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -530,6 +530,19 @@ static CPAccessResult access_tpm(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ +static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1) { + uint64_t trap =3D isread ? HCR_TRVM : HCR_TVM; + if (arm_hcr_el2_eff(env) & trap) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -785,12 +798,14 @@ static const ARMCPRegInfo cp_reginfo[] =3D { */ { .name =3D "CONTEXTIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, { .name =3D "CONTEXTIDR_S", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, REGINFO_SENTINEL @@ -803,7 +818,7 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { /* MMU Domain access control / MPU write buffer control */ { .name =3D "DACR", .cp =3D 15, .opc1 =3D CP_ANY, .crn =3D 3, .crm =3D CP_ANY, .opc2 =3D= CP_ANY, - .access =3D PL1_RW, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, .writefn =3D dacr_write, .raw_writefn =3D raw_write, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), offsetoflow32(CPUARMState, cp15.dacr_ns) } }, @@ -996,7 +1011,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "DMB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 5, .access =3D PL0_W, .type =3D ARM_CP_NOP }, { .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 2, - .access =3D PL1_RW, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ifar_s), offsetof(CPUARMState, cp15.ifar_ns) }, .resetvalue =3D 0, }, @@ -2208,16 +2223,19 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { */ { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* MAIR can just read-as-written because we don't implement caches * and so don't need to care about memory attributes. */ { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[1]), + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue =3D 0 }, { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, @@ -2231,12 +2249,14 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { * handled in the field definitions. */ { .name =3D "MAIR0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, .acce= ss =3D PL1_RW, + .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair0_s), offsetof(CPUARMState, cp15.mair0_ns) }, .resetfn =3D arm_cp_reset_ignore }, { .name =3D "MAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, .acce= ss =3D PL1_RW, + .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair1_s), offsetof(CPUARMState, cp15.mair1_ns) }, .resetfn =3D arm_cp_reset_ignore }, @@ -3886,20 +3906,21 @@ static void vttbr_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_= ALIAS, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dfsr_s), offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, { .name =3D "IFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, - .access =3D PL1_RW, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.ifsr_s), offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, { .name =3D "DFAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.dfar_s), offsetof(CPUARMState, cp15.dfar_ns) } }, { .name =3D "FAR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[1]), + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, REGINFO_SENTINEL }; @@ -3907,25 +3928,29 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = =3D { static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .writefn =3D vmsa_tcr_el12_write, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_tcr_el12_write, .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, .writefn =3D vmsa_ttbcr_= write, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_ALIAS, .writefn =3D vmsa_ttbcr_write, .raw_writefn =3D vmsa_ttbcr_raw_write, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tcr_el[3]), offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, @@ -3937,7 +3962,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { */ static const ARMCPRegInfo ttbcr2_reginfo =3D { .name =3D "TTBCR2", .cp =3D 15, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .= opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, }; @@ -4157,23 +4183,25 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { /* NOP AMAIR0/1 */ { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "PAR", .cp =3D 15, .crm =3D 7, .opc1 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_64BIT, .resetvalue =3D 0, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.par_s), offsetof(CPUARMState, cp15.par_ns)} }, { .name =3D "TTBR0", .cp =3D 15, .crm =3D 2, .opc1 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, .writefn =3D vmsa_ttbr_write, }, { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, .writefn =3D vmsa_ttbr_write, }, @@ -4888,7 +4916,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .type =3D ARM_CP_NOP, .access =3D PL1_W }, /* MMU Domain access control / MPU write buffer control */ { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, .writefn =3D dacr_write, .raw_writefn =3D raw_write, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), offsetoflow32(CPUARMState, cp15.dacr_ns) } }, @@ -7765,7 +7793,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo sctlr =3D { .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns) }, .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582940001; cv=none; d=zohomail.com; s=zohoarc; b=n8PmLf8Qa00ZKLDju/QK56h0N0CXng+sbl0UztLgzC/ZMyZKF7JGOH3OKhPEzn/HZ+VeudAhc/MSsbAtG9V5IXKrukdLE/Wfq60rdUKtPcqyFRE3+vPaXPjntULZvs0Fxa3a0FUIqRP9q//UO3yYh7ADzoLBhwKecy9b4k0VExI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582940001; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4ajglCXwTcimWMRoub0cmqXlu4Sl0gLTr8uSkY1gHjo=; b=U49uLiCgXYxcJSjfjfW6AjRlBXqBL7T4Knr2uTp+/7ywaao0Dbe+a+/OseC8LP9tUg9AESt9h9S4JRPZGTK0ec7f/O3yJ+0w+Niev4i1OIR11muuYlBSM3+nzT5cbcquvRobOD8fKkB6+oO+yNqqSup4/gV7VBhsaUJwUJ8ELCQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582940001457187.11357972875885; Fri, 28 Feb 2020 17:33:21 -0800 (PST) Received: from localhost ([::1]:55936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7r0K-0005YI-61 for importer@patchew.org; Fri, 28 Feb 2020 20:33:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37099) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qvc-0004uW-2n for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7qvZ-00064y-Qb for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:27 -0500 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:43891) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7qvZ-00063s-3R for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:25 -0500 Received: by mail-pl1-x642.google.com with SMTP id p11so1898731plq.10 for ; Fri, 28 Feb 2020 17:28:24 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4ajglCXwTcimWMRoub0cmqXlu4Sl0gLTr8uSkY1gHjo=; b=PjYVbNuYXVZoO+Mh/NKpUDUhSzgPCyft37XZStvJiaTAIM1YCc5dFu3SipLwyMAKx7 MCZWF6PZms87SW5nHBZyqJNEGX4PSNPXXdIijvbNcW9LBy8YEaXYbkCuyBvNN0tg6kc+ yBpt7khsm31kTgPzDNntZyRfAi8HCeymDo0Xu6W7oA3dEkfGWAGsXLiDh4K4Y4eGJg6k aCEGzl872u5UgCehWevbnapogNuwwxAHuW73yCSsJsAcTFf1UEGAcThkdrytO/tHtHjk hNf+s75ia5bP7qgDj2XpHUS5u3tA/zwIK/UGaTHoEWTGxO1UK2rAs0hh2xHfHMyPhq4L lkaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4ajglCXwTcimWMRoub0cmqXlu4Sl0gLTr8uSkY1gHjo=; b=QLdkMTqWvvw2onn9hTMuave2cK/20QbnKwNemJ3IDeXEZ6Kgau5jgw++ZeZtHDx7ih BOzpW1WCmlj5fvpm6XbLh6K2FS4aK5vHByK6t2mso6AgTjEF8mLhPz5uVS5bcfUGRUml tXYupJQadv6iRvu6WhrmKFEwlHWsduWERaRGY5ETo0HHZNAyi8MwF4ilMGjfHvXBt7tx neu2e6BX0fwclSWfwtoucvEnV34TCHnxjGDfSTeIwGI48JAXDsxYLiA0kiAOo1QLMzkJ mlo8QI91ZQlbYzJpfZcI6f9B4Pu5+0Y1dPmqhwtcOZmDAPy6zApm3xKL6CBvIUoVNJN8 MAqA== X-Gm-Message-State: APjAAAW9CtEXpXgZ9MmMb3UdOiKnI3PQkks5+Ti2v7mOdaZSHzF54S5L NhoHiCyGXMbLm7v9br7EbHBNeIcaWzU= X-Google-Smtp-Source: APXvYqwxjT8WmpcNfaZyO3zhxj2SVC+RytPu1JKr760+clemVJNOwvIRn4us2FuIzC9Pk8kwaSKz2A== X-Received: by 2002:a17:902:bf41:: with SMTP id u1mr6547110pls.207.1582939703650; Fri, 28 Feb 2020 17:28:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 07/12] target/arm: Honor the HCR_EL2.TSW bit Date: Fri, 28 Feb 2020 17:28:06 -0800 Message-Id: <20200229012811.24129-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" These bits trap EL1 access to set/way cache maintenance insns. Buglink: https://bugs.launchpad.net/bugs/1863685 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1f371b0391..ddef3d7dc3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -543,6 +543,16 @@ static CPAccessResult access_tvm_trvm(CPUARMState *env= , const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TSW. */ +static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -4704,14 +4714,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, @@ -4722,7 +4732,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, @@ -4903,17 +4913,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, /* MMU Domain access control / MPU write buffer control */ { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ohQYIa+ztFNnbKsJpZfcxKi5WgxlXIdIZEVtzv1Cd+Q=; b=iF5RAbD4McjE5ael1cVN0Dr06ePAj0CVJWs6KjQDBEMVLZZr0/wMSLsCz5Sxu2Y9Kq /snTikKt/jQjIlLOD2e+h3T/f3hzE1B5DR5Oor1MvMavAIjwJN9sIqJglaNHnTxSvkL/ RKmlF47g0KKO64CH4ChVnThi/ayvdCtPdFCMlOkyjaMyQU8nhtDvVzXl8oLFpvtD6V13 I1FUaKm9PkRTUuqpAJwNCvo6paooZi93s3smwCDru+SHmCfLssrQ+20HBh2FEssQS8dr S2QhTJHNzJlS2APpmscgVtL5ZyZVtSdEzfTbK94noapuwjBxY21IEgaXvNFR6Rzo4AKJ obew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ohQYIa+ztFNnbKsJpZfcxKi5WgxlXIdIZEVtzv1Cd+Q=; b=jjZqtHhp5vh6itH0VqBpWTw6xrCA+pBfDQTR5tlu2R9OH8ycE6dRz4Ns80uJ3zQtTD upGPTKm0fuUOuSahzsFmO4+i/e3eLNtiEcvSSQ6xyUna1iZGz3Cu5N0HAhM1Wyg8+0Ky 9EW1Ylm7oQmny5dP9tj9GGdgWugnXOXL1bkYoRvFa0yX3HeFLI3qiJgSogsBUsElTGZg mdnqlqAq5KvA+xJjsjS2x7RjxUMsrLS18HeCBfl5Unl/Bai5BcVQptBeYq+MXHeY4M7U RRjtMcSnVNCByMPoja4naApOV6mxxa/6rDIoV63ebefp17e1ZAAgS82Za+l1fIfsh/ds tE7w== X-Gm-Message-State: APjAAAX6r/N9PU4m70ilRlBiapu1GLcYySz9+wgN7Gw5YXYgftAsRlBU MfXclPFYPonsbxp5E39s+GAcGuYLAPE= X-Google-Smtp-Source: APXvYqwmvAXsrvzNmoC7aQPN09WZy6WS73irdMp5VIKVAt4IjCGbACSQ5ZehhY2le38nqQ0NQFnSBg== X-Received: by 2002:a65:6843:: with SMTP id q3mr7346064pgt.269.1582939704957; Fri, 28 Feb 2020 17:28:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 08/12] target/arm: Honor the HCR_EL2.TACR bit Date: Fri, 28 Feb 2020 17:28:07 -0800 Message-Id: <20200229012811.24129-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to the auxiliary control registers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ddef3d7dc3..2c06ac8d02 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -553,6 +553,16 @@ static CPAccessResult access_tsw(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TACR. */ +static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TACR))= { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -6961,8 +6971,8 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { static const ARMCPRegInfo actlr2_hactlr2_reginfo[] =3D { { .name =3D "ACTLR2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tacr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, .access =3D PL2_RW, .type =3D ARM_CP_CONST, @@ -7718,8 +7728,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo auxcr_reginfo[] =3D { { .name =3D "ACTLR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->reset_auxcr }, + .access =3D PL1_RW, .accessfn =3D access_tacr, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->reset_auxcr }, { .name =3D "ACTLR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582940001; cv=none; d=zohomail.com; s=zohoarc; b=WiIFs40+75MrcmAINUr/YkjXalfU+EX7ITHWeAsvnHhGc9qftBez5Rvan+jazxq3TjYXRGTbnWyAnG/+AeRiglYoNsXcf2GyIwZ8B5UtPMBxs24lpMDKQUzWBVfprYri5G1q2L6bYph+HCeUZp8iLZowgoXtgUru/SBBFOo6OD4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582940001; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pnBsdmgd+K1Yf7h5c1j8apGf/ntIFnarc7b46/SCqJo=; b=eiLvKueLn23svZTprMsz2IlkGuQBeHvIgttQOZNmJ+9WaMa4eC5Z7wN3TC3qRSxk4WCFz+SfVFphaeIB6B0B2pIMx+X24wug8nd3lmuiSPul0lS4J5eXLKM31V/C9RGcmxqcjwZXf/qyu3sxHIk5SWWO/DyoPdnhPyc2wwZJTgI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582940001529771.8433030335013; Fri, 28 Feb 2020 17:33:21 -0800 (PST) Received: from localhost ([::1]:55940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7r0K-0005Yj-Ch for importer@patchew.org; Fri, 28 Feb 2020 20:33:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37145) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qvd-0004wC-UO for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7qvc-00066U-95 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:29 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:40960) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7qvc-00065m-1p for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:28 -0500 Received: by mail-pf1-x444.google.com with SMTP id j9so2588854pfa.8 for ; Fri, 28 Feb 2020 17:28:27 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pnBsdmgd+K1Yf7h5c1j8apGf/ntIFnarc7b46/SCqJo=; b=QBuCvpGzy1XivFgp2aDM3fsm+2gH6Fl0PX8pu1kV41V77kWcY9sUpwrkX15ZFcbRcw zGXkN3wkBtzNoyogNyqJeKA9PNaaTEICnvyKZJwMiGLEvbcewhOzWiqGzK8gy1tgUHGy fenHV+zqcl5fH2ypRZ8oXvWu4jQ8g9Dr8NhH+2G+dbb4Ha4nasGT8lnm2Xe2DClqFVS6 OKBqoQb4SocdD1aNzmwqtPqJLlgY2bdrqJRILqruCRmca4Vluvsu8EXS3GPldYWILuJL RjwJbYj41JavXRFzzoRMgv0Wj8fPvsmy2pT0zPeks3DF8JlfR65FZhP0b1euVbj+uzS6 GFMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pnBsdmgd+K1Yf7h5c1j8apGf/ntIFnarc7b46/SCqJo=; b=Tx/y9PvjFCEWYIkxRkeunzuxft0lMGVPtOiz3+8ap4ais4xe0kHho096km8WrpI1jq vsD5BCZMZBz+KoXSHnkgsNnSmtEbVi2sXhYAgueJy8WoFyiXtBIphxBm0HHUq5vVbzah Ks8ln2uDU/7zyFYuZC8ZjYdBrDBVE7vHLHsAZgThxC0bFe6KoG7MfKnHXhrmpzIgRHcu b06tx5w4hbTVM9m8GmvrJ+/gqgDVlbN7R6mvb4/ZpTAIvopsdPb+vJ1d7RYaM2wNbI8j lTRW9Lb+q6VSB9Eme3e2VWEnK4PIzzvT6g4t8bFa0fcRQE1etwlyX4Yp+leQOMkU9eWS RA5Q== X-Gm-Message-State: APjAAAUkn2Sk4we3+1OqfHGuqD4bQB/lFMBbWbWGRQhVjPItmxhUi86O kEwS8HWWUPSrfokCQLLZ3NcP14nFEDY= X-Google-Smtp-Source: APXvYqwbSWejBPElwCVYERYm+LeGFISrz4Mw1NstlsTTEiO92YUvFlIXX0myjV8EbGHP+pU/I7E5sQ== X-Received: by 2002:aa7:93a6:: with SMTP id x6mr7236480pff.72.1582939706213; Fri, 28 Feb 2020 17:28:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 09/12] target/arm: Honor the HCR_EL2.TPCP bit Date: Fri, 28 Feb 2020 17:28:08 -0800 Message-Id: <20200229012811.24129-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to cache maintenance insns that operate to the point of coherency or persistence. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Fix el0 fallthru (pmm). --- target/arm/helper.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2c06ac8d02..e87a76c6f5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4314,6 +4314,28 @@ static CPAccessResult aa64_cacheop_access(CPUARMStat= e *env, return CP_ACCESS_OK; } =20 +static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Coherency or Persistence... */ + switch (arm_current_el(env)) { + case 0: + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { + return CP_ACCESS_TRAP; + } + /* fall through */ + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPCP) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ @@ -4721,14 +4743,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, + .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, @@ -4739,7 +4762,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, @@ -4921,17 +4944,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, /* MMU Domain access control / MPU write buffer control */ @@ -6750,7 +6773,7 @@ static const ARMCPRegInfo dcpop_reg[] =3D { { .name =3D "DC_CVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_access, .writefn =3D dccvap_writefn }, + .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, REGINFO_SENTINEL }; =20 @@ -6758,7 +6781,7 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { { .name =3D "DC_CVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_access, .writefn =3D dccvap_writefn }, + .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, REGINFO_SENTINEL }; #endif /*CONFIG_USER_ONLY*/ --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=efqTpSOjpSCCNnyOhAFLjdUflto9CJ4CEmzuEd6bw/4=; b=KSKJdm1MWHzP4+FvHsH/rsgi5SDI7HyZ06m1p5Ow1bNKKarULv0AuXB938wRximmtJ X42qmN0Royp3cbfS9oqQ7jS1ykjwNf0bWFbvwFs/PTb100ZA6YKyUt8rVMqzWZ/daJ30 vZDRLE3o2YOMa/qsJAHvwJsLaNVbmfx8K+LDOzonydZlBhwOllKKtCGLzA3pERtvoc38 92X8DSLdbxcU7os87CCZzwRNL3gIrJs3arlNCwaMUDb4Cic8IyST74yEkvKbJg9U+hdx JcKAQYmaU9ZH0dGxcD1hFmqwFPtHtHETPKFT9Xkj5+G5ur3x5nGVk+a9vCrACYmTTQy/ pJFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=efqTpSOjpSCCNnyOhAFLjdUflto9CJ4CEmzuEd6bw/4=; b=Q1kFeNF4oudOa3QlyCAyowgQfSH22SyE07ZAg+aKIwDSbT/qmD697k5ACIiuiSrEy2 03S1ZTCiOot2+GfWhjM6UA/t9TUCf6J4wK6ruODfTUwM9Fme5aDDwr3Grp+rAuptrVXZ pQIU9/GAWuGEPD0WxoYAk/oyDl0MjyJb5menQB+e+9D6zzGynDmRYJ1XVNoWULFnp0P1 rXsrpii2i0OGnO5Gwo9JpTCklTa0RahXKHaSOa6kqJa3vRJwpYy+DmUGipEiOMAZDfjW eJy8UfbhYTpQC9Y4W1qGB2Vib9LaGT0womAyEQXYDWWWc8M/KIOC5AA1Onp7Gx69LieO AXcw== X-Gm-Message-State: APjAAAWcQAXRAdzcHvlo+SIIVpgH7ob37v9Z1YCyW3KeOdFN9nfhdQBd Ygx3DrvFvsCgwZK6838bwHWpO7EltNo= X-Google-Smtp-Source: APXvYqzjEqvjGJG9lUlXsNrC9eXXePkg+s9beHuvoW0unbqLXhgpHnXQ/TMOamJxljwUFBTUsN9TFA== X-Received: by 2002:a17:902:b7c2:: with SMTP id v2mr6204491plz.54.1582939707425; Fri, 28 Feb 2020 17:28:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 10/12] target/arm: Honor the HCR_EL2.TPU bit Date: Fri, 28 Feb 2020 17:28:09 -0800 Message-Id: <20200229012811.24129-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to cache maintenance insns that operate to the point of unification. There are no longer any references to plain aa64_cacheop_access, so remove it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Fix el0 fallthru (pmm). --- target/arm/helper.c | 53 +++++++++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e87a76c6f5..40faa70cb7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4301,19 +4301,6 @@ static const ARMCPRegInfo uao_reginfo =3D { .readfn =3D aa64_uao_read, .writefn =3D aa64_uao_write }; =20 -static CPAccessResult aa64_cacheop_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless - * SCTLR_EL1.UCI is set. - */ - if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -4336,6 +4323,28 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARM= State *env, return CP_ACCESS_OK; } =20 +static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Unification... */ + switch (arm_current_el(env)) { + case 0: + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { + return CP_ACCESS_TRAP; + } + /* fall through */ + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPU) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ @@ -4733,14 +4742,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* Cache ops: all NOPs since we don't emulate caches */ { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, @@ -4758,7 +4769,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, @@ -4932,13 +4943,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D tlbiipas2_is_write }, /* 32 bit cache operations */ { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "BPIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "ICIALLU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "ICIMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "BPIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, @@ -4952,7 +4963,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tJiUGzvYuoPuLk2QE0BCekDbY5+UySrzDOvHDIAIJYQ=; b=TzI2+ptrLaBOMBwL7ZVHvMwS7/PgSNAAT2STHQGL8rnda3G4X9kOGtBwrFDjiZntsi ogt+UIygL8rFO+zUGCGUVC4sOgO15541uHQSY/QD2BZHM3C/5ZOvFQuPxRWnH6C6rNWE 2scWi95BjQxW1Olv0NDg5WzSNDz6gic2Sw1AdsZvZn177dTTaUDSGhuQ9BUstzPuF4uZ LVGX0ICma7TjarSMHzka/8S1eii+oicwJDbLALt6ZbaUBoYTGTMCHpK6sfAcdQmwqyWE OPFP6D8rhkZPOuzrcDT5qqcd06bSvopuQXGgT7Qccge9AMjdu6EJ7DWkFiX+VXhFUAHr 0oXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tJiUGzvYuoPuLk2QE0BCekDbY5+UySrzDOvHDIAIJYQ=; b=m/cEWVPtm6VJg9mE2kWvwo6eJ+C3m5ucofSU25sjxhdJZFcmnILCSfIWWU1/+dJAxV DjsARUzin0c4qAQqnoBmfziaImzG7F9I8oxZeDj4Yo/L46031b783By5dag2zxTK8Msq BNaf9EYj/VDsIvRlDd9wmbB9a1bAazQRk5zIX5PqhrRrNdjOC5QLLhPY7w2/fm4YZJjN YOHj4K+gPW2qAJWD7Vwvxa1UG1pBEKG0bLfG4k+xFSxHTgfMPuhZ/9VUgpM1M9MoInPZ gAOHsswZ8cABmqJzIXCfWwMh5ml1MClgsTPUHsOqJw2qWNx/ZN+p1iip+Fn9PGdwOqJz 5gOg== X-Gm-Message-State: ANhLgQ23S9B6thLM+RmDmnU0dd+adceR5Bgu3w+6uxe0+tDaPndjR8BI Z66ygc1AghofzEgnVt1pRLrY5yxbsI4= X-Google-Smtp-Source: ADFU+vvMdjJgd9HNkQ8L5C3on6xFcDqNO8kuuR3UpEQEqo8HZJEHZtR9fsGDyhfDJQue2QVrhv3EtA== X-Received: by 2002:a05:6a00:2d3:: with SMTP id b19mr4066314pft.2.1582939708659; Fri, 28 Feb 2020 17:28:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 11/12] target/arm: Honor the HCR_EL2.TTLB bit Date: Fri, 28 Feb 2020 17:28:10 -0800 Message-Id: <20200229012811.24129-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to tlb maintenance insns. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 85 +++++++++++++++++++++++++++++---------------- 1 file changed, 55 insertions(+), 30 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 40faa70cb7..2f148e0dc2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -563,6 +563,16 @@ static CPAccessResult access_tacr(CPUARMState *env, co= nst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TTLB. */ +static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TTLB))= { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -2285,41 +2295,53 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, /* 32 bit ITLB invalidates */ { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, { .name =3D "ITLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "ITLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 5, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, /* 32 bit DTLB invalidates */ { .name =3D "DTLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, { .name =3D "DTLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "DTLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 6, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, /* 32 bit TLB invalidates */ { .name =3D "TLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, { .name =3D "TLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "TLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimvaa_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimvaa_write }, REGINFO_SENTINEL }; =20 static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { /* 32 bit TLB invalidates, Inner Shareable */ { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_is_= write }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_is_write }, { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_is_= write }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_is_write }, { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbiasid_is_write }, { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_is_write }, REGINFO_SENTINEL }; @@ -4780,51 +4802,51 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1_write }, { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1_write }, { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, @@ -4910,14 +4932,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { #endif /* TLB invalidate last level of translation table walk */ { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_is_= write }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_is_write }, { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_is_write }, { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimvaa_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimvaa_write }, { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, .writefn =3D tlbimva_hyp_write }, --=20 2.20.1 From nobody Thu Nov 13 17:44:03 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582940109; cv=none; d=zohomail.com; s=zohoarc; b=JeXfeLL6iFqWUAiTlSbc9kTzvu42WH0TnpnvwvbFy9m3Xy7hvTS1/6+KvtnQ4QeIFRtaAJN7e4L8n2DFaCUpiClczRCOSpEZf6EPsU1KspdqUe5vOuUu4mFbnE3UUT7tGotdVa/0ZHJxi0YzqN0OcKP+pFvwIbw1gJPgailiD7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582940109; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=46JVchtXjykCWqulQO2w6tf7omk6UGW3sCrnOh12e0E=; b=kOgdI5KTf8X1fLte36+4VvzPk7/qn2+4SJ6l/iPNjPt18BEPhrXCP+xOVMfnS/UiMoqaPsL72O6FxnwiBciXKy4Up62Zt6oCd9DxhDtp+1uOAPDWwRQOJbA2zg0YnjJZobDvWPIaB0NHGO+BgXtGskDVHt87spqH5YuVlBndWlg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582940109270862.6968117494254; Fri, 28 Feb 2020 17:35:09 -0800 (PST) Received: from localhost ([::1]:55980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7r20-0007sp-Cy for importer@patchew.org; Fri, 28 Feb 2020 20:35:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37202) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7qvg-0004zO-Ib for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7qvf-00068t-HX for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:32 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:32777) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7qvf-00068F-Bh for qemu-devel@nongnu.org; Fri, 28 Feb 2020 20:28:31 -0500 Received: by mail-pg1-x544.google.com with SMTP id 6so2406195pgk.0 for ; Fri, 28 Feb 2020 17:28:31 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=46JVchtXjykCWqulQO2w6tf7omk6UGW3sCrnOh12e0E=; b=BoymvsOD3qbq0L3fy/L2uRDzKeSoq5LrhJya1oN22KEaREmQ1/Itn49gglufn9laO6 B+7CWTE4z5NUgz/+Zwb9y+0TQt0FY4fGlfiqzqwR1gWu+qfWyiSb/MAoBJ35RHBSiiAY kkyp2k2o2bmAgM+9w9xtPZ/TsgM2EFXD+UifSuiV0YcOaYaC5e6YM0O08Q9KaMUBjkb8 SdSJq80tD6c69j5yFYcChUv0Jtg+6EZq/T1MH9KHl84HB0GnIpQLPjzE62JIhKHpXPrY nfl6r6eff3L5iPG5dPoTTI4cFT9LDAWmyByvILK1qPGhpKwdCUluy8C9sgR9viHGirrv Cqvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=46JVchtXjykCWqulQO2w6tf7omk6UGW3sCrnOh12e0E=; b=QjV0Elb7lNv+SHrh/gQusVtJvG0RMtU1xVNGx7B5BIheO/zLIxjObgXkPa5IKjR3yV XQwTYjjqBi2RMagERdt7fpCD6cEYnF+jh/ORs9XElUBaN7XgCEXJqKIQl+6hddS1IDUT lLVZhWQOE41HTDS7WIJffNasGzTF4/8GkHhajIZ7269JCZcBRy0Qw01M3tXvSHkvE8IV pWXUDuOGvqxPz9m/k0a30yHiCRoSwUTNUlMGOadqml+ksx33cC++4V0Hqk2QRkmj6MSj D3IA8xtLMJTqxKA3rVoH4GJG2oN5nFNXzpHDPi17BVvtLDaBIzPRIINHtb25Vcg74bes 1WxQ== X-Gm-Message-State: APjAAAVhEVPPAq9CbUdJWB2id5qs4JKjsxL8tiigAFYd5zoHeQdRh/40 fOXa6EgH2QthNGnTOem8xgMTFWmAaHo= X-Google-Smtp-Source: APXvYqxNbk7QHZqLzA8PZ56XbX3nena+9Mj48dMaZcAqkXlzrVGevQISRvkBk8WRXR6CM+r5LncGnQ== X-Received: by 2002:a63:4a47:: with SMTP id j7mr7310472pgl.196.1582939710052; Fri, 28 Feb 2020 17:28:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 12/12] tests/tcg/aarch64: Add newline in pauth-1 printf Date: Fri, 28 Feb 2020 17:28:11 -0800 Message-Id: <20200229012811.24129-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Make the output just a bit prettier when running by hand. Cc: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- tests/tcg/aarch64/pauth-1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tcg/aarch64/pauth-1.c b/tests/tcg/aarch64/pauth-1.c index ea0984ea82..d3878cbeb6 100644 --- a/tests/tcg/aarch64/pauth-1.c +++ b/tests/tcg/aarch64/pauth-1.c @@ -29,7 +29,7 @@ int main() } =20 perc =3D (float) count / (float) (TESTS * 2); - printf("Ptr Check: %0.2f%%", perc * 100.0); + printf("Ptr Check: %0.2f%%\n", perc * 100.0); assert(perc > 0.95); return 0; } --=20 2.20.1