1 | v1->v2 changes: dropped the last 6 patches from rth as there's | 1 | Massively slimmed down v2: MemTag broke bsd-user, and the npcm7xx |
---|---|---|---|
2 | a problem with one of them that's too complicated to try to | 2 | ethernet device failed 'make check' on big-endian hosts. |
3 | fix up. | ||
4 | 3 | ||
5 | thanks | ||
6 | -- PMM | 4 | -- PMM |
7 | 5 | ||
8 | The following changes since commit a8c6af67e1e8d460e2c6e87070807e0a02c0fec2: | 6 | The following changes since commit 83339e21d05c824ebc9131d644f25c23d0e41ecf: |
9 | 7 | ||
10 | Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200221' into staging (2020-02-21 14:20:42 +0000) | 8 | Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2021-02-10 15:42:20 +0000) |
11 | 9 | ||
12 | are available in the Git repository at: | 10 | are available in the Git repository at: |
13 | 11 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200221-1 | 12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210211-1 |
15 | 13 | ||
16 | for you to fetch changes up to 9eb4f58918a851fb46895fd9b7ce579afeac9d02: | 14 | for you to fetch changes up to d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621: |
17 | 15 | ||
18 | target/arm: Set MVFR0.FPSP for ARMv5 cpus (2020-02-21 16:07:03 +0000) | 16 | target/arm: Correctly initialize MDCR_EL2.HPMN (2021-02-11 19:48:09 +0000) |
19 | 17 | ||
20 | ---------------------------------------------------------------- | 18 | ---------------------------------------------------------------- |
21 | target-arm queue: | 19 | target-arm queue: |
22 | * aspeed/scu: Implement chip ID register | 20 | * Correctly initialize MDCR_EL2.HPMN |
23 | * hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register | 21 | * versal: Use nr_apu_cpus in favor of hard coding 2 |
24 | * mainstone: Make providing flash images non-mandatory | 22 | * accel/tcg: Add URL of clang bug to comment about our workaround |
25 | * z2: Make providing flash images non-mandatory | 23 | * Add support for FEAT_DIT, Data Independent Timing |
26 | * Fix failures to flush SVE high bits after AdvSIMD INS/ZIP/UZP/TRN/TBL/TBX/EXT | 24 | * Remove GPIO from unimplemented NPCM7XX |
27 | * Minor performance improvement: spend less time recalculating hflags values | 25 | * Fix SCR RES1 handling |
28 | * Code cleanup to isar_feature function tests | 26 | * Don't migrate CPUARMState.features |
29 | * Implement ARMv8.1-PMU and ARMv8.4-PMU extensions | ||
30 | * Bugfix: correct handling of PMCR_EL0.LC bit | ||
31 | * Bugfix: correct definition of PMCRDP | ||
32 | * Correctly implement ACTLR2, HACTLR2 | ||
33 | * allwinner: Wire up USB ports | ||
34 | * Vectorize emulation of USHL, SSHL, PMUL* | ||
35 | * xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd | ||
36 | * sh4: Fix PCI ISA IO memory subregion | ||
37 | 27 | ||
38 | ---------------------------------------------------------------- | 28 | ---------------------------------------------------------------- |
39 | Francisco Iglesias (1): | 29 | Aaron Lindsay (1): |
40 | xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd | 30 | target/arm: Don't migrate CPUARMState.features |
41 | 31 | ||
42 | Guenter Roeck (6): | 32 | Daniel Müller (1): |
43 | mainstone: Make providing flash images non-mandatory | 33 | target/arm: Correctly initialize MDCR_EL2.HPMN |
44 | z2: Make providing flash images non-mandatory | ||
45 | hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file | ||
46 | hcd-ehci: Introduce "companion-enable" sysbus property | ||
47 | arm: allwinner: Wire up USB ports | ||
48 | sh4: Fix PCI ISA IO memory subregion | ||
49 | 34 | ||
50 | Joel Stanley (2): | 35 | Edgar E. Iglesias (1): |
51 | aspeed/scu: Create separate write callbacks | 36 | hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2 |
52 | aspeed/scu: Implement chip ID register | ||
53 | 37 | ||
54 | Peter Maydell (21): | 38 | Hao Wu (1): |
55 | target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers | 39 | hw/arm: Remove GPIO from unimplemented NPCM7XX |
56 | target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan | ||
57 | target/arm: Add isar_feature_any_fp16 and document naming/usage conventions | ||
58 | target/arm: Define and use any_predinv isar_feature test | ||
59 | target/arm: Factor out PMU register definitions | ||
60 | target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 | ||
61 | target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field | ||
62 | target/arm: Define an aa32_pmu_8_1 isar feature test function | ||
63 | target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks | ||
64 | target/arm: Stop assuming DBGDIDR always exists | ||
65 | target/arm: Move DBGDIDR into ARMISARegisters | ||
66 | target/arm: Read debug-related ID registers from KVM | ||
67 | target/arm: Implement ARMv8.1-PMU extension | ||
68 | target/arm: Implement ARMv8.4-PMU extension | ||
69 | target/arm: Provide ARMv8.4-PMU in '-cpu max' | ||
70 | target/arm: Correct definition of PMCRDP | ||
71 | target/arm: Correct handling of PMCR_EL0.LC bit | ||
72 | target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks | ||
73 | target/arm: Use isar_feature function for testing AA32HPD feature | ||
74 | target/arm: Use FIELD_EX32 for testing 32-bit fields | ||
75 | target/arm: Correctly implement ACTLR2, HACTLR2 | ||
76 | 40 | ||
77 | Philippe Mathieu-Daudé (1): | 41 | Mike Nawrocki (1): |
78 | hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register | 42 | target/arm: Fix SCR RES1 handling |
79 | 43 | ||
80 | Richard Henderson (15): | 44 | Peter Maydell (2): |
81 | target/arm: Flush high bits of sve register after AdvSIMD EXT | 45 | arm: Update infocenter.arm.com URLs |
82 | target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX | 46 | accel/tcg: Add URL of clang bug to comment about our workaround |
83 | target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN | ||
84 | target/arm: Flush high bits of sve register after AdvSIMD INS | ||
85 | target/arm: Use bit 55 explicitly for pauth | ||
86 | target/arm: Fix select for aa64_va_parameters_both | ||
87 | target/arm: Remove ttbr1_valid check from get_phys_addr_lpae | ||
88 | target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid | ||
89 | target/arm: Vectorize USHL and SSHL | ||
90 | target/arm: Convert PMUL.8 to gvec | ||
91 | target/arm: Convert PMULL.64 to gvec | ||
92 | target/arm: Convert PMULL.8 to gvec | ||
93 | target/arm: Rename isar_feature_aa32_simd_r32 | ||
94 | target/arm: Use isar_feature_aa32_simd_r32 more places | ||
95 | target/arm: Set MVFR0.FPSP for ARMv5 cpus | ||
96 | 47 | ||
97 | hw/usb/hcd-ohci.h | 16 ++ | 48 | Rebecca Cran (4): |
98 | include/hw/arm/allwinner-a10.h | 6 + | 49 | target/arm: Add support for FEAT_DIT, Data Independent Timing |
99 | target/arm/cpu.h | 145 ++++++++++--- | 50 | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate |
100 | target/arm/helper-sve.h | 2 + | 51 | target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU |
101 | target/arm/helper.h | 21 +- | 52 | target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPU |
102 | target/arm/internals.h | 47 ++++- | ||
103 | target/arm/translate.h | 6 + | ||
104 | hw/arm/allwinner-a10.c | 43 ++++ | ||
105 | hw/arm/mainstone.c | 11 +- | ||
106 | hw/arm/z2.c | 6 - | ||
107 | hw/intc/armv7m_nvic.c | 10 +- | ||
108 | hw/misc/aspeed_scu.c | 93 ++++++-- | ||
109 | hw/misc/iotkit-secctl.c | 2 +- | ||
110 | hw/sh4/sh_pci.c | 11 +- | ||
111 | hw/ssi/xilinx_spips.c | 2 +- | ||
112 | hw/usb/hcd-ehci-sysbus.c | 2 + | ||
113 | hw/usb/hcd-ohci.c | 15 -- | ||
114 | linux-user/elfload.c | 4 +- | ||
115 | target/arm/cpu.c | 169 +++++++-------- | ||
116 | target/arm/cpu64.c | 58 +++-- | ||
117 | target/arm/debug_helper.c | 6 +- | ||
118 | target/arm/helper.c | 468 +++++++++++++++++++++++------------------ | ||
119 | target/arm/kvm32.c | 25 +++ | ||
120 | target/arm/kvm64.c | 46 ++++ | ||
121 | target/arm/neon_helper.c | 117 ----------- | ||
122 | target/arm/pauth_helper.c | 3 +- | ||
123 | target/arm/translate-a64.c | 92 ++++---- | ||
124 | target/arm/translate-vfp.inc.c | 53 ++--- | ||
125 | target/arm/translate.c | 356 ++++++++++++++++++++++++++----- | ||
126 | target/arm/vec_helper.c | 211 +++++++++++++++++++ | ||
127 | target/arm/vfp_helper.c | 2 +- | ||
128 | 31 files changed, 1377 insertions(+), 671 deletions(-) | ||
129 | 53 | ||
54 | include/hw/dma/pl080.h | 7 ++-- | ||
55 | include/hw/misc/arm_integrator_debug.h | 2 +- | ||
56 | include/hw/ssi/pl022.h | 5 ++- | ||
57 | target/arm/cpu.h | 17 ++++++++ | ||
58 | target/arm/internals.h | 6 +++ | ||
59 | accel/tcg/cpu-exec.c | 25 +++++++++--- | ||
60 | hw/arm/aspeed_ast2600.c | 2 +- | ||
61 | hw/arm/musca.c | 4 +- | ||
62 | hw/arm/npcm7xx.c | 8 ---- | ||
63 | hw/arm/xlnx-versal.c | 4 +- | ||
64 | hw/misc/arm_integrator_debug.c | 2 +- | ||
65 | hw/timer/arm_timer.c | 7 ++-- | ||
66 | target/arm/cpu.c | 4 ++ | ||
67 | target/arm/cpu64.c | 5 +++ | ||
68 | target/arm/helper-a64.c | 27 +++++++++++-- | ||
69 | target/arm/helper.c | 71 +++++++++++++++++++++++++++------- | ||
70 | target/arm/machine.c | 2 +- | ||
71 | target/arm/op_helper.c | 9 +---- | ||
72 | target/arm/translate-a64.c | 12 ++++++ | ||
73 | 19 files changed, 164 insertions(+), 55 deletions(-) | ||
74 | diff view generated by jsdifflib |