| 1 | v1->v2 changes: dropped the last 6 patches from rth as there's | 1 | v2: drop pvpanic-pci patches. |
|---|---|---|---|
| 2 | a problem with one of them that's too complicated to try to | ||
| 3 | fix up. | ||
| 4 | 2 | ||
| 5 | thanks | 3 | The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c: |
| 6 | -- PMM | ||
| 7 | 4 | ||
| 8 | The following changes since commit a8c6af67e1e8d460e2c6e87070807e0a02c0fec2: | 5 | Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000) |
| 9 | |||
| 10 | Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200221' into staging (2020-02-21 14:20:42 +0000) | ||
| 11 | 6 | ||
| 12 | are available in the Git repository at: | 7 | are available in the Git repository at: |
| 13 | 8 | ||
| 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200221-1 | 9 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1 |
| 15 | 10 | ||
| 16 | for you to fetch changes up to 9eb4f58918a851fb46895fd9b7ce579afeac9d02: | 11 | for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8: |
| 17 | 12 | ||
| 18 | target/arm: Set MVFR0.FPSP for ARMv5 cpus (2020-02-21 16:07:03 +0000) | 13 | docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000) |
| 19 | 14 | ||
| 20 | ---------------------------------------------------------------- | 15 | ---------------------------------------------------------------- |
| 21 | target-arm queue: | 16 | target-arm queue: |
| 22 | * aspeed/scu: Implement chip ID register | 17 | * Implement IMPDEF pauth algorithm |
| 23 | * hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register | 18 | * Support ARMv8.4-SEL2 |
| 24 | * mainstone: Make providing flash images non-mandatory | 19 | * Fix bug where we were truncating predicate vector lengths in SVE insns |
| 25 | * z2: Make providing flash images non-mandatory | 20 | * npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 26 | * Fix failures to flush SVE high bits after AdvSIMD INS/ZIP/UZP/TRN/TBL/TBX/EXT | 21 | * target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 27 | * Minor performance improvement: spend less time recalculating hflags values | 22 | * docs: Build and install all the docs in a single manual |
| 28 | * Code cleanup to isar_feature function tests | ||
| 29 | * Implement ARMv8.1-PMU and ARMv8.4-PMU extensions | ||
| 30 | * Bugfix: correct handling of PMCR_EL0.LC bit | ||
| 31 | * Bugfix: correct definition of PMCRDP | ||
| 32 | * Correctly implement ACTLR2, HACTLR2 | ||
| 33 | * allwinner: Wire up USB ports | ||
| 34 | * Vectorize emulation of USHL, SSHL, PMUL* | ||
| 35 | * xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd | ||
| 36 | * sh4: Fix PCI ISA IO memory subregion | ||
| 37 | 23 | ||
| 38 | ---------------------------------------------------------------- | 24 | ---------------------------------------------------------------- |
| 39 | Francisco Iglesias (1): | 25 | Gan Qixin (1): |
| 40 | xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd | 26 | npcm7xx_adc-test: Fix memleak in adc_qom_set |
| 41 | 27 | ||
| 42 | Guenter Roeck (6): | 28 | Peter Maydell (1): |
| 43 | mainstone: Make providing flash images non-mandatory | 29 | docs: Build and install all the docs in a single manual |
| 44 | z2: Make providing flash images non-mandatory | ||
| 45 | hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file | ||
| 46 | hcd-ehci: Introduce "companion-enable" sysbus property | ||
| 47 | arm: allwinner: Wire up USB ports | ||
| 48 | sh4: Fix PCI ISA IO memory subregion | ||
| 49 | |||
| 50 | Joel Stanley (2): | ||
| 51 | aspeed/scu: Create separate write callbacks | ||
| 52 | aspeed/scu: Implement chip ID register | ||
| 53 | |||
| 54 | Peter Maydell (21): | ||
| 55 | target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers | ||
| 56 | target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan | ||
| 57 | target/arm: Add isar_feature_any_fp16 and document naming/usage conventions | ||
| 58 | target/arm: Define and use any_predinv isar_feature test | ||
| 59 | target/arm: Factor out PMU register definitions | ||
| 60 | target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 | ||
| 61 | target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field | ||
| 62 | target/arm: Define an aa32_pmu_8_1 isar feature test function | ||
| 63 | target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks | ||
| 64 | target/arm: Stop assuming DBGDIDR always exists | ||
| 65 | target/arm: Move DBGDIDR into ARMISARegisters | ||
| 66 | target/arm: Read debug-related ID registers from KVM | ||
| 67 | target/arm: Implement ARMv8.1-PMU extension | ||
| 68 | target/arm: Implement ARMv8.4-PMU extension | ||
| 69 | target/arm: Provide ARMv8.4-PMU in '-cpu max' | ||
| 70 | target/arm: Correct definition of PMCRDP | ||
| 71 | target/arm: Correct handling of PMCR_EL0.LC bit | ||
| 72 | target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks | ||
| 73 | target/arm: Use isar_feature function for testing AA32HPD feature | ||
| 74 | target/arm: Use FIELD_EX32 for testing 32-bit fields | ||
| 75 | target/arm: Correctly implement ACTLR2, HACTLR2 | ||
| 76 | 30 | ||
| 77 | Philippe Mathieu-Daudé (1): | 31 | Philippe Mathieu-Daudé (1): |
| 78 | hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register | 32 | target/arm/m_helper: Silence GCC 10 maybe-uninitialized error |
| 79 | 33 | ||
| 80 | Richard Henderson (15): | 34 | Richard Henderson (7): |
| 81 | target/arm: Flush high bits of sve register after AdvSIMD EXT | 35 | target/arm: Implement an IMPDEF pauth algorithm |
| 82 | target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX | 36 | target/arm: Add cpu properties to control pauth |
| 83 | target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN | 37 | target/arm: Use object_property_add_bool for "sve" property |
| 84 | target/arm: Flush high bits of sve register after AdvSIMD INS | 38 | target/arm: Introduce PREDDESC field definitions |
| 85 | target/arm: Use bit 55 explicitly for pauth | 39 | target/arm: Update PFIRST, PNEXT for pred_desc |
| 86 | target/arm: Fix select for aa64_va_parameters_both | 40 | target/arm: Update ZIP, UZP, TRN for pred_desc |
| 87 | target/arm: Remove ttbr1_valid check from get_phys_addr_lpae | 41 | target/arm: Update REV, PUNPK for pred_desc |
| 88 | target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid | ||
| 89 | target/arm: Vectorize USHL and SSHL | ||
| 90 | target/arm: Convert PMUL.8 to gvec | ||
| 91 | target/arm: Convert PMULL.64 to gvec | ||
| 92 | target/arm: Convert PMULL.8 to gvec | ||
| 93 | target/arm: Rename isar_feature_aa32_simd_r32 | ||
| 94 | target/arm: Use isar_feature_aa32_simd_r32 more places | ||
| 95 | target/arm: Set MVFR0.FPSP for ARMv5 cpus | ||
| 96 | 42 | ||
| 97 | hw/usb/hcd-ohci.h | 16 ++ | 43 | Rémi Denis-Courmont (19): |
| 98 | include/hw/arm/allwinner-a10.h | 6 + | 44 | target/arm: remove redundant tests |
| 99 | target/arm/cpu.h | 145 ++++++++++--- | 45 | target/arm: add arm_is_el2_enabled() helper |
| 100 | target/arm/helper-sve.h | 2 + | 46 | target/arm: use arm_is_el2_enabled() where applicable |
| 101 | target/arm/helper.h | 21 +- | 47 | target/arm: use arm_hcr_el2_eff() where applicable |
| 102 | target/arm/internals.h | 47 ++++- | 48 | target/arm: factor MDCR_EL2 common handling |
| 103 | target/arm/translate.h | 6 + | 49 | target/arm: Define isar_feature function to test for presence of SEL2 |
| 104 | hw/arm/allwinner-a10.c | 43 ++++ | 50 | target/arm: add 64-bit S-EL2 to EL exception table |
| 105 | hw/arm/mainstone.c | 11 +- | 51 | target/arm: add MMU stage 1 for Secure EL2 |
| 106 | hw/arm/z2.c | 6 - | 52 | target/arm: add ARMv8.4-SEL2 system registers |
| 107 | hw/intc/armv7m_nvic.c | 10 +- | 53 | target/arm: handle VMID change in secure state |
| 108 | hw/misc/aspeed_scu.c | 93 ++++++-- | 54 | target/arm: do S1_ptw_translate() before address space lookup |
| 109 | hw/misc/iotkit-secctl.c | 2 +- | 55 | target/arm: translate NS bit in page-walks |
| 110 | hw/sh4/sh_pci.c | 11 +- | 56 | target/arm: generalize 2-stage page-walk condition |
| 111 | hw/ssi/xilinx_spips.c | 2 +- | 57 | target/arm: secure stage 2 translation regime |
| 112 | hw/usb/hcd-ehci-sysbus.c | 2 + | 58 | target/arm: set HPFAR_EL2.NS on secure stage 2 faults |
| 113 | hw/usb/hcd-ohci.c | 15 -- | 59 | target/arm: revector to run-time pick target EL |
| 114 | linux-user/elfload.c | 4 +- | 60 | target/arm: Implement SCR_EL2.EEL2 |
| 115 | target/arm/cpu.c | 169 +++++++-------- | 61 | target/arm: enable Secure EL2 in max CPU |
| 116 | target/arm/cpu64.c | 58 +++-- | 62 | target/arm: refactor vae1_tlbmask() |
| 117 | target/arm/debug_helper.c | 6 +- | ||
| 118 | target/arm/helper.c | 468 +++++++++++++++++++++++------------------ | ||
| 119 | target/arm/kvm32.c | 25 +++ | ||
| 120 | target/arm/kvm64.c | 46 ++++ | ||
| 121 | target/arm/neon_helper.c | 117 ----------- | ||
| 122 | target/arm/pauth_helper.c | 3 +- | ||
| 123 | target/arm/translate-a64.c | 92 ++++---- | ||
| 124 | target/arm/translate-vfp.inc.c | 53 ++--- | ||
| 125 | target/arm/translate.c | 356 ++++++++++++++++++++++++++----- | ||
| 126 | target/arm/vec_helper.c | 211 +++++++++++++++++++ | ||
| 127 | target/arm/vfp_helper.c | 2 +- | ||
| 128 | 31 files changed, 1377 insertions(+), 671 deletions(-) | ||
| 129 | 63 | ||
| 64 | docs/conf.py | 46 ++++- | ||
| 65 | docs/devel/conf.py | 15 -- | ||
| 66 | docs/index.html.in | 17 -- | ||
| 67 | docs/interop/conf.py | 28 --- | ||
| 68 | docs/meson.build | 64 +++--- | ||
| 69 | docs/specs/conf.py | 16 -- | ||
| 70 | docs/system/arm/cpu-features.rst | 21 ++ | ||
| 71 | docs/system/conf.py | 28 --- | ||
| 72 | docs/tools/conf.py | 37 ---- | ||
| 73 | docs/user/conf.py | 15 -- | ||
| 74 | include/qemu/xxhash.h | 98 +++++++++ | ||
| 75 | target/arm/cpu-param.h | 2 +- | ||
| 76 | target/arm/cpu.h | 107 ++++++++-- | ||
| 77 | target/arm/internals.h | 45 +++++ | ||
| 78 | target/arm/cpu.c | 23 ++- | ||
| 79 | target/arm/cpu64.c | 65 ++++-- | ||
| 80 | target/arm/helper-a64.c | 8 +- | ||
| 81 | target/arm/helper.c | 414 ++++++++++++++++++++++++++------------- | ||
| 82 | target/arm/m_helper.c | 2 +- | ||
| 83 | target/arm/monitor.c | 1 + | ||
| 84 | target/arm/op_helper.c | 4 +- | ||
| 85 | target/arm/pauth_helper.c | 27 ++- | ||
| 86 | target/arm/sve_helper.c | 33 ++-- | ||
| 87 | target/arm/tlb_helper.c | 3 + | ||
| 88 | target/arm/translate-a64.c | 4 + | ||
| 89 | target/arm/translate-sve.c | 31 ++- | ||
| 90 | target/arm/translate.c | 36 +++- | ||
| 91 | tests/qtest/arm-cpu-features.c | 13 ++ | ||
| 92 | tests/qtest/npcm7xx_adc-test.c | 1 + | ||
| 93 | .gitlab-ci.yml | 4 +- | ||
| 94 | 30 files changed, 770 insertions(+), 438 deletions(-) | ||
| 95 | delete mode 100644 docs/devel/conf.py | ||
| 96 | delete mode 100644 docs/index.html.in | ||
| 97 | delete mode 100644 docs/interop/conf.py | ||
| 98 | delete mode 100644 docs/specs/conf.py | ||
| 99 | delete mode 100644 docs/system/conf.py | ||
| 100 | delete mode 100644 docs/tools/conf.py | ||
| 101 | delete mode 100644 docs/user/conf.py | ||
| 102 | diff view generated by jsdifflib |