Big pullreq this week, since it's got RTH's PAN/UAO/ATS1E1 implementation in it, and also Philippe's raspi board model cleanup patchset, as well as a scattering of smaller stuff. -- PMM The following changes since commit 7ce9ce89930ce260af839fb3e3e5f9101f5c69a0: Merge remote-tracking branch 'remotes/kraxel/tags/ui-20200212-pull-request' into staging (2020-02-13 11:06:32 +0000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200213 for you to fetch changes up to dc7a88d0810ad272bdcd2e0869359af78fdd9114: target/arm: Implement ARMv8.1-VMID16 extension (2020-02-13 14:30:51 +0000) ---------------------------------------------------------------- target-arm queue: * i.MX: Fix inverted sense of register bits in watchdog timer * i.MX: Add support for WDT on i.MX6 * arm/virt: cleanups to ACPI tables * Implement ARMv8.1-VMID16 extension * Implement ARMv8.1-PAN * Implement ARMv8.2-UAO * Implement ARMv8.2-ATS1E1 * ast2400/2500/2600: Wire up EHCI controllers * hw/char/exynos4210_uart: Fix memleaks in exynos4210_uart_init * hw/arm/raspi: Clean up the board code ---------------------------------------------------------------- Chen Qun (1): hw/char/exynos4210_uart: Fix memleaks in exynos4210_uart_init Guenter Roeck (2): hw/arm: ast2400/ast2500: Wire up EHCI controllers hw/arm: ast2600: Wire up EHCI controllers Heyi Guo (7): bios-tables-test: prepare to change ARM virt ACPI DSDT arm/virt/acpi: remove meaningless sub device "RP0" from PCI0 arm/virt/acpi: remove _ADR from devices identified by _HID arm/acpi: fix PCI _PRT definition arm/acpi: fix duplicated _UID of PCI interrupt link devices arm/acpi: simplify the description of PCI _CRS virt/acpi: update golden masters for DSDT update Peter Maydell (1): target/arm: Implement ARMv8.1-VMID16 extension Philippe Mathieu-Daudé (13): hw/arm/raspi: Use BCM2708 machine type with pre Device Tree kernels hw/arm/raspi: Correct the board descriptions hw/arm/raspi: Extract the version from the board revision hw/arm/raspi: Extract the RAM size from the board revision hw/arm/raspi: Extract the processor type from the board revision hw/arm/raspi: Trivial code movement hw/arm/raspi: Make machines children of abstract RaspiMachineClass hw/arm/raspi: Make board_rev a field of RaspiMachineClass hw/arm/raspi: Let class_init() directly call raspi_machine_init() hw/arm/raspi: Set default RAM size to size encoded in board revision hw/arm/raspi: Extract the board model from the board revision hw/arm/raspi: Use a unique raspi_machine_class_init() method hw/arm/raspi: Extract the cores count from the board revision Richard Henderson (20): target/arm: Add arm_mmu_idx_is_stage1_of_2 target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled target/arm: Add isar_feature tests for PAN + ATS1E1 target/arm: Move LOR regdefs to file scope target/arm: Split out aarch32_cpsr_valid_mask target/arm: Mask CPSR_J when Jazelle is not enabled target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return target/arm: Remove CPSR_RESERVED target/arm: Introduce aarch64_pstate_valid_mask target/arm: Update MSR access for PAN target/arm: Update arm_mmu_idx_el for PAN target/arm: Enforce PAN semantics in get_S1prot target/arm: Set PAN bit as required on exception entry target/arm: Implement ATS1E1 system registers target/arm: Enable ARMv8.2-ATS1E1 in -cpu max target/arm: Add ID_AA64MMFR2_EL1 target/arm: Update MSR access to UAO target/arm: Implement UAO semantics target/arm: Enable ARMv8.2-UAO in -cpu max Roman Kapl (2): i.MX: Fix inverted register bits in wdt code. i.MX: Add support for WDT on i.MX6 include/hw/arm/aspeed_soc.h | 6 + include/hw/arm/fsl-imx6.h | 3 + target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 95 ++++++++--- target/arm/internals.h | 85 ++++++++++ hw/arm/aspeed_ast2600.c | 23 +++ hw/arm/aspeed_soc.c | 25 +++ hw/arm/fsl-imx6.c | 21 +++ hw/arm/raspi.c | 190 ++++++++++++++++------ hw/arm/virt-acpi-build.c | 25 +-- hw/char/exynos4210_uart.c | 5 +- hw/misc/imx2_wdt.c | 2 +- target/arm/cpu.c | 4 + target/arm/cpu64.c | 10 ++ target/arm/helper-a64.c | 6 +- target/arm/helper.c | 327 +++++++++++++++++++++++++++++--------- target/arm/kvm64.c | 2 + target/arm/op_helper.c | 14 +- target/arm/translate-a64.c | 31 ++++ target/arm/translate.c | 42 +++-- tests/data/acpi/virt/DSDT | Bin 18462 -> 5307 bytes tests/data/acpi/virt/DSDT.memhp | Bin 19799 -> 6644 bytes tests/data/acpi/virt/DSDT.numamem | Bin 18462 -> 5307 bytes 23 files changed, 731 insertions(+), 187 deletions(-) From: Roman Kapl <rka@sysgo.com> Documentation says for WDA '0: Assert WDOG output.' and for SRS '0: Assert system reset signal.'. Signed-off-by: Roman Kapl <rka@sysgo.com> Message-id: 20200207095409.11227-1-rka@sysgo.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/misc/imx2_wdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/imx2_wdt.c b/hw/misc/imx2_wdt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/imx2_wdt.c +++ b/hw/misc/imx2_wdt.c @@ -XXX,XX +XXX,XX @@ static void imx2_wdt_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size) { if (addr == IMX2_WDT_WCR && - (value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) { + (~value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) { watchdog_perform_action(); } } -- 2.20.1 From: Roman Kapl <rka@sysgo.com> Uses the i.MX2 rudimentary watchdog driver. Signed-off-by: Roman Kapl <rka@sysgo.com> Message-id: 20200207095529.11309-1-rka@sysgo.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: removed accidental duplicate #include line] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/fsl-imx6.h | 3 +++ hw/arm/fsl-imx6.c | 21 +++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -XXX,XX +XXX,XX @@ #include "hw/cpu/a9mpcore.h" #include "hw/misc/imx6_ccm.h" #include "hw/misc/imx6_src.h" +#include "hw/misc/imx2_wdt.h" #include "hw/char/imx_serial.h" #include "hw/timer/imx_gpt.h" #include "hw/timer/imx_epit.h" @@ -XXX,XX +XXX,XX @@ #define FSL_IMX6_NUM_GPIOS 7 #define FSL_IMX6_NUM_ESDHCS 4 #define FSL_IMX6_NUM_ECSPIS 5 +#define FSL_IMX6_NUM_WDTS 2 typedef struct FslIMX6State { /*< private >*/ @@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6State { IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS]; SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS]; IMXSPIState spi[FSL_IMX6_NUM_ECSPIS]; + IMX2WdtState wdt[FSL_IMX6_NUM_WDTS]; IMXFECState eth; MemoryRegion rom; MemoryRegion caam; diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj) sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI); } + for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { + snprintf(name, NAME_SIZE, "wdt%d", i); + sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]), + TYPE_IMX2_WDT); + } + sysbus_init_child_obj(obj, "eth", &s->eth, sizeof(s->eth), TYPE_IMX_ENET); } @@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_ENET_MAC_1588_IRQ)); + /* + * Watchdog + */ + for (i = 0; i < FSL_IMX6_NUM_WDTS; i++) { + static const hwaddr FSL_IMX6_WDOGn_ADDR[FSL_IMX6_NUM_WDTS] = { + FSL_IMX6_WDOG1_ADDR, + FSL_IMX6_WDOG2_ADDR, + }; + + object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", + &error_abort); + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); + } + /* ROM memory */ memory_region_init_rom(&s->rom, NULL, "imx6.rom", FSL_IMX6_ROM_SIZE, &err); -- 2.20.1 From: Heyi Guo <guoheyi@huawei.com> We are going to change ARM virt ACPI DSDT table, which will cause make check to fail, so temporarily add related golden masters to ignore list. Signed-off-by: Heyi Guo <guoheyi@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20200204014325.16279-2-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,4 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/DSDT", +"tests/data/acpi/virt/DSDT.memhp", +"tests/data/acpi/virt/DSDT.numamem", -- 2.20.1 From: Heyi Guo <guoheyi@huawei.com> The sub device "RP0" under PCI0 in ACPI/DSDT does not contain any method or property other than "_ADR", so it is safe to remove it. Signed-off-by: Heyi Guo <guoheyi@huawei.com> Acked-by: "Michael S. Tsirkin" <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20200204014325.16279-3-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt-acpi-build.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, aml_append(method, aml_return(buf)); aml_append(dev, method); - Aml *dev_rp0 = aml_device("%s", "RP0"); - aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); - aml_append(dev, dev_rp0); - Aml *dev_res0 = aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); crs = aml_resource_template(); -- 2.20.1 From: Heyi Guo <guoheyi@huawei.com> According to ACPI spec, _ADR should be used for device on a bus that has a standard enumeration algorithm, but not for device which is on system bus and must be enumerated by OSPM. And it is not recommended to contain both _HID and _ADR in a single device. See ACPI 6.3, section 6.1, top of page 343: A device object must contain either an _HID object or an _ADR object, but should not contain both. (https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf) Signed-off-by: Heyi Guo <guoheyi@huawei.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20200204014325.16279-4-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt-acpi-build.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, AML_EXCLUSIVE, &uart_irq, 1)); aml_append(dev, aml_name_decl("_CRS", crs)); - /* The _ADR entry is used to link this device to the UART described - * in the SPCR table, i.e. SPCR.base_address.address == _ADR. - */ - aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base))); - aml_append(scope, dev); } @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); aml_append(dev, aml_name_decl("_SEG", aml_int(0))); aml_append(dev, aml_name_decl("_BBN", aml_int(0))); - aml_append(dev, aml_name_decl("_ADR", aml_int(0))); aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); aml_append(dev, aml_name_decl("_CCA", aml_int(1))); @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, { Aml *dev = aml_device("GPO0"); aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061"))); - aml_append(dev, aml_name_decl("_ADR", aml_int(0))); aml_append(dev, aml_name_decl("_UID", aml_int(0))); Aml *crs = aml_resource_template(); @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_power_button(Aml *scope) { Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C"))); - aml_append(dev, aml_name_decl("_ADR", aml_int(0))); aml_append(dev, aml_name_decl("_UID", aml_int(0))); aml_append(scope, dev); } -- 2.20.1 From: Heyi Guo <guoheyi@huawei.com> The address field in each _PRT mapping package should be constructed with high word for device# and low word for function#, so it is wrong to use bus_no as the high word. The existing code adds a bunch useless entries with device #s above 31. Enumerate all possible slots (i.e. PCI_SLOT_MAX) instead. Signed-off-by: Heyi Guo <guoheyi@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20200204014325.16279-5-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt-acpi-build.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, { int ecam_id = VIRT_ECAM_ID(highmem_ecam); Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; - int i, bus_no; + int i, slot_no; hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base; hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size; hwaddr base_pio = memmap[VIRT_PCIE_PIO].base; @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, aml_append(dev, aml_name_decl("_CCA", aml_int(1))); /* Declare the PCI Routing Table. */ - Aml *rt_pkg = aml_varpackage(nr_pcie_buses * PCI_NUM_PINS); - for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) { + Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); + for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) { for (i = 0; i < PCI_NUM_PINS; i++) { - int gsi = (i + bus_no) % PCI_NUM_PINS; + int gsi = (i + slot_no) % PCI_NUM_PINS; Aml *pkg = aml_package(4); - aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF)); + aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); aml_append(pkg, aml_int(i)); aml_append(pkg, aml_name("GSI%d", gsi)); aml_append(pkg, aml_int(0)); -- 2.20.1 From: Heyi Guo <guoheyi@huawei.com> Using _UID of 0 for all PCI interrupt link devices absolutely violates the spec. Simply increase one by one. Signed-off-by: Heyi Guo <guoheyi@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20200204014325.16279-6-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt-acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, uint32_t irqs = irq + i; Aml *dev_gsi = aml_device("GSI%d", i); aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); - aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0))); + aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); crs = aml_resource_template(); aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, -- 2.20.1 From: Heyi Guo <guoheyi@huawei.com> The original code defines a named object for the resource template but then returns the resource template object itself; the resulted output is like below: Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings { Name (RBUF, ResourceTemplate () { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity 0x0000, // Range Minimum 0x00FF, // Range Maximum 0x0000, // Translation Offset 0x0100, // Length ,, ) ...... }) Return (ResourceTemplate () { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity 0x0000, // Range Minimum 0x00FF, // Range Maximum 0x0000, // Translation Offset 0x0100, // Length ,, ) ...... }) } So the named object "RBUF" is actually useless. The more natural way is to return RBUF instead, or simply drop RBUF definition. Choose the latter one to simplify the code. Signed-off-by: Heyi Guo <guoheyi@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20200204014325.16279-7-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/virt-acpi-build.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, size_mmio_high)); } - aml_append(method, aml_name_decl("RBUF", rbuf)); aml_append(method, aml_return(rbuf)); aml_append(dev, method); -- 2.20.1 From: Heyi Guo <guoheyi@huawei.com> Differences between disassembled ASL files: @@ -XXX,XX +XXX,XX @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of DSDT, Thu Jan 23 16:00:04 2020 + * Disassembly of DSDT.new, Thu Jan 23 16:47:12 2020 * * Original Table Header: * Signature "DSDT" - * Length 0x0000481E (18462) + * Length 0x000014BB (5307) * Revision 0x02 - * Checksum 0x60 + * Checksum 0xD1 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) 0x00000021, } }) - Name (_ADR, 0x09000000) // _ADR: Address } Device (FLS0) @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment Name (_BBN, Zero) // _BBN: BIOS Bus Number - Name (_ADR, Zero) // _ADR: Address Name (_UID, "PCI0") // _UID: Unique ID Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String Name (_CCA, One) // _CCA: Cache Coherency Attribute - Name (_PRT, Package (0x0400) // _PRT: PCI Routing Table + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table { Package (0x04) { @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) 0x03, GSI2, Zero - }, - - Package (0x04) - { - 0x0020FFFF, - Zero, - GSI0, - Zero - }, - - *Omit the other (4 * (256 - 32) - 2) packages* - - Package (0x04) - { - 0x00FFFFFF, - 0x03, - GSI2, - Zero } }) Device (GSI0) @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) Device (GSI1) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID - Name (_UID, Zero) // _UID: Unique ID + Name (_UID, One) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) Device (GSI2) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID - Name (_UID, Zero) // _UID: Unique ID + Name (_UID, 0x02) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) Device (GSI3) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID - Name (_UID, Zero) // _UID: Unique ID + Name (_UID, 0x03) // _UID: Unique ID Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings { - Name (RBUF, ResourceTemplate () - { - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, // Granularity - 0x0000, // Range Minimum - 0x00FF, // Range Maximum - 0x0000, // Translation Offset - 0x0100, // Length - ,, ) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x00000000, // Granularity - 0x10000000, // Range Minimum - 0x3EFEFFFF, // Range Maximum - 0x00000000, // Translation Offset - 0x2EFF0000, // Length - ,, , AddressRangeMemory, TypeStatic) - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x00000000, // Granularity - 0x00000000, // Range Minimum - 0x0000FFFF, // Range Maximum - 0x3EFF0000, // Translation Offset - 0x00010000, // Length - ,, , TypeStatic, DenseTranslation) - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, - 0x0000000000000000, // Granularity - 0x0000008000000000, // Range Minimum - 0x000000FFFFFFFFFF, // Range Maximum - 0x0000000000000000, // Translation Offset - 0x0000008000000000, // Length - ,, , AddressRangeMemory, TypeStatic) - }) Return (ResourceTemplate () { WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) }) } - Device (RP0) - { - Name (_ADR, Zero) // _ADR: Address - } - Device (RES0) { Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID @@ -XXX,XX +XXX,XX @@ DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) Device (PWRB) { Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID - Name (_ADR, Zero) // _ADR: Address Name (_UID, Zero) // _UID: Unique ID } } The differences between the two versions of DSDT.memhp are almost the same as the above, except for total length and checksum. DSDT.numamem binary is just the same with DSDT on virt machine, so we don't show the differences again. Signed-off-by: Heyi Guo <guoheyi@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20200204014325.16279-8-guoheyi@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- tests/qtest/bios-tables-test-allowed-diff.h | 3 --- tests/data/acpi/virt/DSDT | Bin 18462 -> 5307 bytes tests/data/acpi/virt/DSDT.memhp | Bin 19799 -> 6644 bytes tests/data/acpi/virt/DSDT.numamem | Bin 18462 -> 5307 bytes 4 files changed, 3 deletions(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index XXXXXXX..XXXXXXX 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,4 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/virt/DSDT", -"tests/data/acpi/virt/DSDT.memhp", -"tests/data/acpi/virt/DSDT.numamem", diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT index XXXXXXX..XXXXXXX 100644 GIT binary patch delta 156 zcmbO?fpNDcmrJlq$Zin^2BwP>xulufJQ*iyC^K43^tIeLL4lLWeZ}O>oO+X=b6T<Z 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z){Y%iGN7e)Qd8c{Fs8N@EuJ$q)=9tW^BX58s$=t-TT8<`sg0!sac$wRw~Pn>0Sn~0 A00000 -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> Use a common predicate for querying stage1-ness. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/internals.h | 18 ++++++++++++++++++ target/arm/helper.c | 8 +++----- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); #endif +/** + * arm_mmu_idx_is_stage1_of_2: + * @mmu_idx: The ARMMMUIdx to test + * + * Return true if @mmu_idx is a NOTLB mmu_idx that is the + * first stage of a two stage regime. + */ +static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + return true; + default: + return false; + } +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, bool take_exc = false; if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) - && (mmu_idx == ARMMMUIdx_Stage1_E1 || - mmu_idx == ARMMMUIdx_Stage1_E0)) { + && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* * Synchronous stage 2 fault on an access made as part of the * translation table walk for AT S1E0* or AT S1E1* insn @@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_disabled(CPUARMState *env, } } - if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1)) { + if ((env->cp15.hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1) && + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa; -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> To implement PAN, we will want to swap, for short periods of time, to a different privileged mmu_idx. In addition, we cannot do this with flushing alone, because the AT* instructions have both PAN and PAN-less versions. Add the ARMMMUIdx*_PAN constants where necessary next to the corresponding ARMMMUIdx* constant. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 33 ++++++++++++++------- target/arm/internals.h | 9 ++++++ target/arm/helper.c | 60 +++++++++++++++++++++++++++++++------- target/arm/translate-a64.c | 3 ++ target/arm/translate.c | 2 ++ 6 files changed, 87 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -XXX,XX +XXX,XX @@ # define TARGET_PAGE_BITS_MIN 10 #endif -#define NB_MMU_MODES 9 +#define NB_MMU_MODES 12 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); * 5. we want to be able to use the TLB for accesses done as part of a * stage1 page table walk, rather than having to walk the stage2 page * table over and over. + * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access + * Never (PAN) bit within PSTATE. * * This gives us the following list of cases: * * NS EL0 EL1&0 stage 1+2 (aka NS PL0) * NS EL1 EL1&0 stage 1+2 (aka NS PL1) + * NS EL1 EL1&0 stage 1+2 +PAN * NS EL0 EL2&0 - * NS EL2 EL2&0 + * NS EL2 EL2&0 +PAN * NS EL2 (aka NS PL2) * S EL0 EL1&0 (aka S PL0) * S EL1 EL1&0 (not used if EL3 is 32 bit) + * S EL1 EL1&0 +PAN * S EL3 (aka S PL1) * NS EL1&0 stage 2 * - * for a total of 9 different mmu_idx. + * for a total of 12 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish NS EL0 and NS EL1 (and @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A, - ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A, - ARMMMUIdx_E2 = 3 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2 = 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_0 = 5 | ARM_MMU_IDX_A, - ARMMMUIdx_SE10_1 = 6 | ARM_MMU_IDX_A, - ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A, + ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A, + ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2 = 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A, /* * These are not allocated TLBs and are used only for AT system @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx { */ ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB, /* * M-profile. @@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit { TO_CORE_BIT(E10_0), TO_CORE_BIT(E20_0), TO_CORE_BIT(E10_1), + TO_CORE_BIT(E10_1_PAN), TO_CORE_BIT(E2), TO_CORE_BIT(E20_2), + TO_CORE_BIT(E20_2_PAN), TO_CORE_BIT(SE10_0), TO_CORE_BIT(SE10_1), + TO_CORE_BIT(SE10_1_PAN), TO_CORE_BIT(SE3), TO_CORE_BIT(Stage2), diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: return true; default: return false; @@ -XXX,XX +XXX,XX @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: @@ -XXX,XX +XXX,XX @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_SE3: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: @@ -XXX,XX +XXX,XX @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: return true; default: return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2); } @@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2); } @@ -XXX,XX +XXX,XX @@ static int gt_phys_redir_timeridx(CPUARMState *env) switch (arm_mmu_idx(env)) { case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: return GTIMER_HYP; default: return GTIMER_PHYS; @@ -XXX,XX +XXX,XX @@ static int gt_virt_redir_timeridx(CPUARMState *env) switch (arm_mmu_idx(env)) { case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: return GTIMER_HYPVIRT; default: return GTIMER_VIRT; @@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, format64 = arm_s1_regime_using_lpae_format(env, mmu_idx); if (arm_feature(env, ARM_FEATURE_EL2)) { - if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) { + if (mmu_idx == ARMMMUIdx_E10_0 || + mmu_idx == ARMMMUIdx_E10_1 || + mmu_idx == ARMMMUIdx_E10_1_PAN) { format64 |= env->cp15.hcr_el2 & (HCR_VM | HCR_DC); } else { format64 |= arm_current_el(env) == 2; @@ -XXX,XX +XXX,XX @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, if (extract64(raw_read(env, ri) ^ value, 48, 16) && (arm_hcr_el2_eff(env) & HCR_E2H)) { tlb_flush_by_mmuidx(env_cpu(env), - ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0); + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0); } raw_write(env, ri, value); } @@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, if (raw_read(env, ri) != value) { tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2); raw_write(env, ri, value); @@ -XXX,XX +XXX,XX @@ static int vae1_tlbmask(CPUARMState *env) { /* Since we exclude secure first, we may read HCR_EL2 directly. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; + return ARMMMUIdxBit_SE10_1 | + ARMMMUIdxBit_SE10_1_PAN | + ARMMMUIdxBit_SE10_0; } else if ((env->cp15.hcr_el2 & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { - return ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0; + return ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; } else { - return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; + return ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; } } @@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env) * stage 1 translations. */ if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | ARMMMUIdxBit_SE10_0; + return ARMMMUIdxBit_SE10_1 | + ARMMMUIdxBit_SE10_1_PAN | + ARMMMUIdxBit_SE10_0; } else if (arm_feature(env, ARM_FEATURE_EL2)) { - return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_Stage2; + return ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_Stage2; } else { - return ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_0; + return ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; } } static int e2_tlbmask(CPUARMState *env) { /* TODO: ARMv8.4-SecEL2 */ - return ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E2; + return ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2; } static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -XXX,XX +XXX,XX @@ static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E20_0: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: case ARMMMUIdx_Stage2: case ARMMMUIdx_E2: return 2; @@ -XXX,XX +XXX,XX @@ static uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_SE10_0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) return ARMMMUIdx_Stage1_E0; case ARMMMUIdx_E10_1: return ARMMMUIdx_Stage1_E1; + case ARMMMUIdx_E10_1_PAN: + return ARMMMUIdx_Stage1_E1_PAN; default: return mmu_idx; } @@ -XXX,XX +XXX,XX @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) return false; case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: g_assert_not_reached(); } } @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, target_ulong *page_size, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { - if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) { + if (mmu_idx == ARMMMUIdx_E10_0 || + mmu_idx == ARMMMUIdx_E10_1 || + mmu_idx == ARMMMUIdx_E10_1_PAN) { /* Call ourselves recursively to do the stage 1 and then stage 2 * translations. */ @@ -XXX,XX +XXX,XX @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARMMMUIdx_SE10_0: return 0; case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: return 1; case ARMMMUIdx_E2: case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: return 2; case ARMMMUIdx_SE3: return 3; @@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, /* TODO: ARMv8.2-UAO */ switch (mmu_idx) { case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: /* TODO: ARMv8.3-NV */ flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); break; case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: /* TODO: ARMv8.4-SecEL2 */ /* * Note that E20_2 is gated by HCR_EL2.E2H == 1, but E20_0 is diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -XXX,XX +XXX,XX @@ static int get_a64_user_mem_index(DisasContext *s) */ switch (useridx) { case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: useridx = ARMMMUIdx_E10_0; break; case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: useridx = ARMMMUIdx_E20_0; break; case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: useridx = ARMMMUIdx_SE10_0; break; default: diff --git a/target/arm/translate.c b/target/arm/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s) case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */ case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_E10_0); case ARMMMUIdx_SE3: case ARMMMUIdx_SE10_0: case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0); case ARMMMUIdx_MUser: case ARMMMUIdx_MPriv: -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> Include definitions for all of the bits in ID_MMFR3. We already have a definition for ID_AA64MMFR1.PAN. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) +FIELD(ID_MMFR3, CMAINTVA, 0, 4) +FIELD(ID_MMFR3, CMAINTSW, 4, 4) +FIELD(ID_MMFR3, BPMAINT, 8, 4) +FIELD(ID_MMFR3, MAINTBCST, 12, 4) +FIELD(ID_MMFR3, PAN, 16, 4) +FIELD(ID_MMFR3, COHWALK, 20, 4) +FIELD(ID_MMFR3, CMEMSZ, 24, 4) +FIELD(ID_MMFR3, SUPERSEC, 28, 4) + FIELD(ID_MMFR4, SPECSEI, 0, 4) FIELD(ID_MMFR4, AC2, 4, 4) FIELD(ID_MMFR4, XNX, 8, 4) @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4; } +static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0; +} + +static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2; +} + /* * 64-bit feature tests via id registers. */ @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; } +static inline bool isar_feature_aa64_pan(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0; +} + +static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> For static const regdefs, file scope is preferred. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 57 +++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env, return access_lor_ns(env); } +/* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ +static const ARMCPRegInfo lor_reginfo[] = { + { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, + .access = PL1_RW, .accessfn = access_lor_other, + .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, + .access = PL1_R, .accessfn = access_lorid, + .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + #ifdef TARGET_AARCH64 static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (cpu_isar_feature(aa64_lor, cpu)) { - /* - * A trivial implementation of ARMv8.1-LOR leaves all of these - * registers fixed at 0, which indicates that there are zero - * supported Limited Ordering regions. - */ - static const ARMCPRegInfo lor_reginfo[] = { - { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3, - .access = PL1_RW, .accessfn = access_lor_other, - .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7, - .access = PL1_R, .accessfn = access_lorid, - .type = ARM_CP_CONST, .resetvalue = 0 }, - REGINFO_SENTINEL - }; define_arm_cp_regs(cpu, lor_reginfo); } -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> Split this helper out of msr_mask in translate.c. At the same time, transform the negative reductive logic to positive accumulative logic. It will be usable along the exception paths. While touching msr_mask, fix up formatting. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200208125816.14954-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/internals.h | 21 +++++++++++++++++++++ target/arm/translate.c | 40 +++++++++++++++++----------------------- 2 files changed, 38 insertions(+), 23 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) } } +static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, + const ARMISARegisters *id) +{ + uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J; + + if ((features >> ARM_FEATURE_V4T) & 1) { + valid |= CPSR_T; + } + if ((features >> ARM_FEATURE_V5) & 1) { + valid |= CPSR_Q; /* V5TE in reality*/ + } + if ((features >> ARM_FEATURE_V6) & 1) { + valid |= CPSR_E | CPSR_GE; + } + if ((features >> ARM_FEATURE_THUMB2) & 1) { + valid |= CPSR_IT; + } + + return valid; +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/translate.c b/target/arm/translate.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -XXX,XX +XXX,XX @@ static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y) /* Return the mask of PSR bits set by a MSR instruction. */ static uint32_t msr_mask(DisasContext *s, int flags, int spsr) { - uint32_t mask; + uint32_t mask = 0; - mask = 0; - if (flags & (1 << 0)) + if (flags & (1 << 0)) { mask |= 0xff; - if (flags & (1 << 1)) + } + if (flags & (1 << 1)) { mask |= 0xff00; - if (flags & (1 << 2)) + } + if (flags & (1 << 2)) { mask |= 0xff0000; - if (flags & (1 << 3)) + } + if (flags & (1 << 3)) { mask |= 0xff000000; + } - /* Mask out undefined bits. */ - mask &= ~CPSR_RESERVED; - if (!arm_dc_feature(s, ARM_FEATURE_V4T)) { - mask &= ~CPSR_T; - } - if (!arm_dc_feature(s, ARM_FEATURE_V5)) { - mask &= ~CPSR_Q; /* V5TE in reality*/ - } - if (!arm_dc_feature(s, ARM_FEATURE_V6)) { - mask &= ~(CPSR_E | CPSR_GE); - } - if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { - mask &= ~CPSR_IT; - } - /* Mask out execution state and reserved bits. */ + /* Mask out undefined and reserved bits. */ + mask &= aarch32_cpsr_valid_mask(s->features, s->isar); + + /* Mask out execution state. */ if (!spsr) { - mask &= ~(CPSR_EXEC | CPSR_RESERVED); + mask &= ~CPSR_EXEC; } + /* Mask out privileged bits. */ - if (IS_USER(s)) + if (IS_USER(s)) { mask &= CPSR_USER; + } return mask; } -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> The J bit signals Jazelle mode, and so of course is RES0 when the feature is not enabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200208125816.14954-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/internals.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, const ARMISARegisters *id) { - uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J; + uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV; if ((features >> ARM_FEATURE_V4T) & 1) { valid |= CPSR_T; @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, if ((features >> ARM_FEATURE_THUMB2) & 1) { valid |= CPSR_IT; } + if (isar_feature_jazelle(id)) { + valid |= CPSR_J; + } return valid; } -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> CPSR_ERET_MASK was a useless renaming of CPSR_RESERVED. The function also takes into account bits that the cpu does not support. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 2 -- target/arm/op_helper.c | 5 ++++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE) /* Execution state bits. MRS read as zero, MSR writes ignored. */ #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL) -/* Mask of bits which may be set by exception return copying them from SPSR */ -#define CPSR_ERET_MASK (~CPSR_RESERVED) /* Bit definitions for M profile XPSR. Most are the same as CPSR. */ #define XPSR_EXCP 0x1ffU diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -XXX,XX +XXX,XX @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) /* Write the CPSR for a 32-bit exception return */ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { + uint32_t mask; + qemu_mutex_lock_iothread(); arm_call_pre_el_change_hook(env_archcpu(env)); qemu_mutex_unlock_iothread(); - cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); + mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar); + cpsr_write(env, val, mask, CPSRWriteExceptionReturn); /* Generated code has already stored the new PC value, but * without masking out its low bits, because which bits need -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> Using ~0 as the mask on the aarch64->aarch32 exception return was not even as correct as the CPSR_ERET_MASK that we had used on the aarch32->aarch32 exception return. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper-a64.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) { int cur_el = arm_current_el(env); unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el); - uint32_t spsr = env->banked_spsr[spsr_idx]; + uint32_t mask, spsr = env->banked_spsr[spsr_idx]; int new_el; bool return_to_aa64 = (spsr & PSTATE_nRW) == 0; @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) * will sort the register banks out for us, and we've already * caught all the bad-mode cases in el_from_spsr(). */ - cpsr_write(env, spsr, ~0, CPSRWriteRaw); + mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar); + cpsr_write(env, spsr, mask, CPSRWriteRaw); if (!arm_singlestep_active(env)) { env->uncached_cpsr &= ~PSTATE_SS; } -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> The only remaining use was in op_helper.c. Use PSTATE_SS directly, and move the commentary so that it is more obvious what is going on. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200208125816.14954-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 6 ------ target/arm/op_helper.c | 9 ++++++++- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) -/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in - * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use - * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32, - * where it is live state but not accessible to the AArch32 code. - */ -#define CPSR_RESERVED (0x7U << 21) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -XXX,XX +XXX,XX @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) uint32_t HELPER(cpsr_read)(CPUARMState *env) { - return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED); + /* + * We store the ARMv8 PSTATE.SS bit in env->uncached_cpsr. + * This is convenient for populating SPSR_ELx, but must be + * hidden from aarch32 mode, where it is not visible. + * + * TODO: ARMv8.4-DIT -- need to move SS somewhere else. + */ + return cpsr_read(env) & ~(CPSR_EXEC | PSTATE_SS); } void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> Use this along the exception return path, where we previously accepted any values. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/internals.h | 12 ++++++++++++ target/arm/helper-a64.c | 1 + 2 files changed, 13 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, return valid; } +static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) +{ + uint32_t valid; + + valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV; + if (isar_feature_aa64_bti(id)) { + valid |= PSTATE_BTYPE; + } + + return valid; +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) cur_el, new_el, env->regs[15]); } else { env->aarch64 = 1; + spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar); pstate_write(env, spsr); if (!arm_singlestep_active(env)) { env->pstate &= ~PSTATE_SS; -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> For aarch64, there's a dedicated msr (imm, reg) insn. For aarch32, this is done via msr to cpsr. Writes from el0 are ignored, which is already handled by the CPSR_USER mask. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 6 ++++++ target/arm/helper.c | 21 +++++++++++++++++++++ target/arm/translate-a64.c | 14 ++++++++++++++ 4 files changed, 43 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); #define CPSR_IT_2_7 (0xfc00U) #define CPSR_GE (0xfU << 16) #define CPSR_IL (1U << 20) +#define CPSR_PAN (1U << 22) #define CPSR_J (1U << 24) #define CPSR_IT_0_1 (3U << 25) #define CPSR_Q (1U << 27) @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_PAN (1U << 22) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, if (isar_feature_jazelle(id)) { valid |= CPSR_J; } + if (isar_feature_aa32_pan(id)) { + valid |= CPSR_PAN; + } return valid; } @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) if (isar_feature_aa64_bti(id)) { valid |= PSTATE_BTYPE; } + if (isar_feature_aa64_pan(id)) { + valid |= PSTATE_PAN; + } return valid; } diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, env->daif = value & PSTATE_DAIF; } +static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_PAN; +} + +static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate = (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); +} + +static const ARMCPRegInfo pan_reginfo = { + .name = "PAN", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 3, + .type = ARM_CP_NO_RAW, .access = PL1_RW, + .readfn = aa64_pan_read, .writefn = aa64_pan_write +}; + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_lor, cpu)) { define_arm_cp_regs(cpu, lor_reginfo); } + if (cpu_isar_feature(aa64_pan, cpu)) { + define_one_arm_cp_reg(cpu, &pan_reginfo); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { define_arm_cp_regs(cpu, vhe_reginfo); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_NEXT; break; + case 0x04: /* PAN */ + if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_PAN); + } else { + clear_pstate_bits(PSTATE_PAN); + } + t1 = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + case 0x05: /* SPSel */ if (s->current_el == 0) { goto do_unallocated; -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> Examine the PAN bit for EL1, EL2, and Secure EL1 to determine if it applies. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) return ARMMMUIdx_E10_0; case 1: if (arm_is_secure_below_el3(env)) { + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_SE10_1_PAN; + } return ARMMMUIdx_SE10_1; } + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_E10_1_PAN; + } return ARMMMUIdx_E10_1; case 2: /* TODO: ARMv8.4-SecEL2 */ /* Note that TGE does not apply at EL2. */ if ((env->cp15.hcr_el2 & HCR_E2H) && arm_el_is_aa64(env, 2)) { + if (env->pstate & PSTATE_PAN) { + return ARMMMUIdx_E20_2_PAN; + } return ARMMMUIdx_E20_2; } return ARMMMUIdx_E2; -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> If we have a PAN-enforcing mmu_idx, set prot == 0 if user_rw != 0. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/internals.h | 13 +++++++++++++ target/arm/helper.c | 3 +++ 2 files changed, 16 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) } } +static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE10_1_PAN: + return true; + default: + return false; + } +} + /* Return the FSR value for a debug exception (watchpoint, hardware * breakpoint or BKPT insn) targeting the specified exception level. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, if (is_user) { prot_rw = user_rw; } else { + if (user_rw && regime_is_pan(env, mmu_idx)) { + return 0; + } prot_rw = simple_ap_to_rw_prot_is_user(ap, false); } -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> The PAN bit is preserved, or set as per SCTLR_ELx.SPAN, plus several other conditions listed in the ARM ARM. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200208125816.14954-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 53 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, uint32_t mask, uint32_t offset, uint32_t newpc) { + int new_el; + /* Change the CPU state so as to actually take the exception. */ switch_mode(env, new_mode); + new_el = arm_current_el(env); + /* * For exceptions taken to AArch32 we must clear the SS bit in both * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now. @@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; /* Set new mode endianness */ env->uncached_cpsr &= ~CPSR_E; - if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { + if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { env->uncached_cpsr |= CPSR_E; } /* J and IL must always be cleared for exception entry */ @@ -XXX,XX +XXX,XX @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0; env->elr_el[2] = env->regs[15]; } else { + /* CPSR.PAN is normally preserved preserved unless... */ + if (cpu_isar_feature(aa64_pan, env_archcpu(env))) { + switch (new_el) { + case 3: + if (!arm_is_secure_below_el3(env)) { + /* ... the target is EL3, from non-secure state. */ + env->uncached_cpsr &= ~CPSR_PAN; + break; + } + /* ... the target is EL3, from secure state ... */ + /* fall through */ + case 1: + /* ... the target is EL1 and SCTLR.SPAN is 0. */ + if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { + env->uncached_cpsr |= CPSR_PAN; + } + break; + } + } /* * this is a lie, as there was no c1_sys on V4T/V5, but who cares * and we should just guard the thumb mode on V4 @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) unsigned int new_el = env->exception.target_el; target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); + unsigned int old_mode; unsigned int cur_el = arm_current_el(env); /* @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) } if (is_a64(env)) { - env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env); + old_mode = pstate_read(env); aarch64_save_sp(env, arm_current_el(env)); env->elr_el[new_el] = env->pc; } else { - env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); + old_mode = cpsr_read(env); env->elr_el[new_el] = env->regs[15]; aarch64_sync_32_to_64(env); env->condexec_bits = 0; } + env->banked_spsr[aarch64_banked_spsr_index(new_el)] = old_mode; + qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); + if (cpu_isar_feature(aa64_pan, cpu)) { + /* The value of PSTATE.PAN is normally preserved, except when ... */ + new_mode |= old_mode & PSTATE_PAN; + switch (new_el) { + case 2: + /* ... the target is EL2 with HCR_EL2.{E2H,TGE} == '11' ... */ + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) + != (HCR_E2H | HCR_TGE)) { + break; + } + /* fall through */ + case 1: + /* ... the target is EL1 ... */ + /* ... and SCTLR_ELx.SPAN == 0, then set to 1. */ + if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) == 0) { + new_mode |= PSTATE_PAN; + } + break; + } + } + pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el); -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> This is a minor enhancement over ARMv8.1-PAN. The *_PAN mmu_idx are used with the existing do_ats_write. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 56 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) switch (ri->opc2 & 6) { case 0: - /* stage 1 current state PL1: ATS1CPR, ATS1CPW */ + /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */ switch (el) { case 3: mmu_idx = ARMMMUIdx_SE3; break; case 2: - mmu_idx = ARMMMUIdx_Stage1_E1; - break; + g_assert(!secure); /* TODO: ARMv8.4-SecEL2 */ + /* fall through */ case 1: - mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) { + mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN + : ARMMMUIdx_Stage1_E1_PAN); + } else { + mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + } break; default: g_assert_not_reached(); @@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, switch (ri->opc2 & 6) { case 0: switch (ri->opc1) { - case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ + if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) { + mmu_idx = (secure ? ARMMMUIdx_SE10_1_PAN + : ARMMMUIdx_Stage1_E1_PAN); + } else { + mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_Stage1_E1; + } break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx = ARMMMUIdx_E2; @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vhe_reginfo[] = { REGINFO_SENTINEL }; +#ifndef CONFIG_USER_ONLY +static const ARMCPRegInfo ats1e1_reginfo[] = { + { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, + { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write64 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo ats1cp_reginfo[] = { + { .name = "ATS1CPRP", + .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 0, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write }, + { .name = "ATS1CPWP", + .cp = 15, .opc1 = 0, .crn = 7, .crm = 9, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn = ats_write }, + REGINFO_SENTINEL +}; +#endif + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pan, cpu)) { define_one_arm_cp_reg(cpu, &pan_reginfo); } +#ifndef CONFIG_USER_ONLY + if (cpu_isar_feature(aa64_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1e1_reginfo); + } + if (cpu_isar_feature(aa32_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1cp_reginfo); + } +#endif if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { define_arm_cp_regs(cpu, vhe_reginfo); -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> This includes enablement of ARMv8.1-PAN. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.c | 4 ++++ target/arm/cpu64.c | 5 +++++ 2 files changed, 9 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 = t; + t = cpu->id_mmfr3; + t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->id_mmfr3 = t; + t = cpu->id_mmfr4; t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ cpu->id_mmfr4 = t; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ cpu->isar.id_aa64mmfr1 = t; /* Replicate the same data to the 32-bit id registers. */ @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 = u; + u = cpu->id_mmfr3; + u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->id_mmfr3 = u; + /* * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, * so do not set MVFR1.FPHP. Strictly speaking this is not legal, -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> Add definitions for all of the fields, up to ARMv8.5. Convert the existing RESERVED register to a full register. Query KVM for the value of the register for the host. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 17 +++++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -XXX,XX +XXX,XX @@ struct ARMCPU { uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64mmfr2; } isar; uint32_t midr; uint32_t revidr; @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64MMFR2, CNP, 0, 4) +FIELD(ID_AA64MMFR2, UAO, 4, 4) +FIELD(ID_AA64MMFR2, LSM, 8, 4) +FIELD(ID_AA64MMFR2, IESB, 12, 4) +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) +FIELD(ID_AA64MMFR2, NV, 24, 4) +FIELD(ID_AA64MMFR2, ST, 28, 4) +FIELD(ID_AA64MMFR2, AT, 32, 4) +FIELD(ID_AA64MMFR2, IDS, 36, 4) +FIELD(ID_AA64MMFR2, FWB, 40, 4) +FIELD(ID_AA64MMFR2, TTL, 48, 4) +FIELD(ID_AA64MMFR2, BBM, 52, 4) +FIELD(ID_AA64MMFR2, EVT, 56, 4) +FIELD(ID_AA64MMFR2, E0PD, 60, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64mmfr1 }, - { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr2 }, { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 7, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); /* * Note that if AArch32 support is not present in the host, -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu.h | 6 ++++++ target/arm/internals.h | 3 +++ target/arm/helper.c | 21 +++++++++++++++++++++ target/arm/translate-a64.c | 14 ++++++++++++++ 4 files changed, 44 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) #define PSTATE_PAN (1U << 22) +#define PSTATE_UAO (1U << 23) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; } +static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) if (isar_feature_aa64_pan(id)) { valid |= PSTATE_PAN; } + if (isar_feature_aa64_uao(id)) { + valid |= PSTATE_UAO; + } return valid; } diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pan_reginfo = { .readfn = aa64_pan_read, .writefn = aa64_pan_write }; +static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_UAO; +} + +static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); +} + +static const ARMCPRegInfo uao_reginfo = { + .name = "UAO", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4, + .type = ARM_CP_NO_RAW, .access = PL1_RW, + .readfn = aa64_uao_read, .writefn = aa64_uao_write +}; + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, ats1cp_reginfo); } #endif + if (cpu_isar_feature(aa64_uao, cpu)) { + define_one_arm_cp_reg(cpu, &uao_reginfo); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { define_arm_cp_regs(cpu, vhe_reginfo); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_NEXT; break; + case 0x03: /* UAO */ + if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_UAO); + } else { + clear_pstate_bits(PSTATE_UAO); + } + t1 = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, t1); + tcg_temp_free_i32(t1); + break; + case 0x04: /* PAN */ if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { goto do_unallocated; -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> We need only override the current condition under which TBFLAG_A64.UNPRIV is set. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 41 +++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, } /* Compute the condition for using AccType_UNPRIV for LDTR et al. */ - /* TODO: ARMv8.2-UAO */ - switch (mmu_idx) { - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - /* TODO: ARMv8.3-NV */ - flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); - break; - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - /* TODO: ARMv8.4-SecEL2 */ - /* - * Note that E20_2 is gated by HCR_EL2.E2H == 1, but E20_0 is - * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. - */ - if (env->cp15.hcr_el2 & HCR_TGE) { + if (!(env->pstate & PSTATE_UAO)) { + switch (mmu_idx) { + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: + /* TODO: ARMv8.3-NV */ flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + break; + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + /* TODO: ARMv8.4-SecEL2 */ + /* + * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is + * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR. + */ + if (env->cp15.hcr_el2 & HCR_TGE) { + flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1); + } + break; + default: + break; } - break; - default: - break; } return rebuild_hflags_common(env, fp_el, mmu_idx, flags); -- 2.20.1 From: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200208125816.14954-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ cpu->isar.id_aa64mmfr1 = t; + t = cpu->isar.id_aa64mmfr2; + t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); + cpu->isar.id_aa64mmfr2 = t; + /* Replicate the same data to the 32-bit id registers. */ u = cpu->isar.id_isar5; u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ -- 2.20.1 From: Guenter Roeck <linux@roeck-us.net> Initialize EHCI controllers on AST2400 and AST2500 using the existing TYPE_PLATFORM_EHCI. After this change, booting ast2500-evb into Linux successfully instantiates a USB interface. ehci-platform 1e6a3000.usb: EHCI Host Controller ehci-platform 1e6a3000.usb: new USB bus registered, assigned bus number 1 ehci-platform 1e6a3000.usb: irq 21, io mem 0x1e6a3000 ehci-platform 1e6a3000.usb: USB 2.0 started, EHCI 1.00 usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.05 usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 usb usb1: Product: EHCI Host Controller Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200206183437.3979-1-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/aspeed_soc.h | 6 ++++++ hw/arm/aspeed_soc.c | 25 +++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -XXX,XX +XXX,XX @@ #include "target/arm/cpu.h" #include "hw/gpio/aspeed_gpio.h" #include "hw/sd/aspeed_sdhci.h" +#include "hw/usb/hcd-ehci.h" #define ASPEED_SPIS_NUM 2 +#define ASPEED_EHCIS_NUM 2 #define ASPEED_WDTS_NUM 4 #define ASPEED_CPUS_NUM 2 #define ASPEED_MACS_NUM 4 @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCState { AspeedXDMAState xdma; AspeedSMCState fmc; AspeedSMCState spi[ASPEED_SPIS_NUM]; + EHCISysBusState ehci[ASPEED_EHCIS_NUM]; AspeedSDMCState sdmc; AspeedWDTState wdt[ASPEED_WDTS_NUM]; FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; @@ -XXX,XX +XXX,XX @@ typedef struct AspeedSoCClass { uint32_t silicon_rev; uint64_t sram_size; int spis_num; + int ehcis_num; int wdts_num; int macs_num; const int *irqmap; @@ -XXX,XX +XXX,XX @@ enum { ASPEED_FMC, ASPEED_SPI1, ASPEED_SPI2, + ASPEED_EHCI1, + ASPEED_EHCI2, ASPEED_VIC, ASPEED_SDMC, ASPEED_SCU, diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { [ASPEED_IOMEM] = 0x1E600000, [ASPEED_FMC] = 0x1E620000, [ASPEED_SPI1] = 0x1E630000, + [ASPEED_EHCI1] = 0x1E6A1000, [ASPEED_VIC] = 0x1E6C0000, [ASPEED_SDMC] = 0x1E6E0000, [ASPEED_SCU] = 0x1E6E2000, @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2500_memmap[] = { [ASPEED_FMC] = 0x1E620000, [ASPEED_SPI1] = 0x1E630000, [ASPEED_SPI2] = 0x1E631000, + [ASPEED_EHCI1] = 0x1E6A1000, + [ASPEED_EHCI2] = 0x1E6A3000, [ASPEED_VIC] = 0x1E6C0000, [ASPEED_SDMC] = 0x1E6E0000, [ASPEED_SCU] = 0x1E6E2000, @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2400_irqmap[] = { [ASPEED_UART5] = 10, [ASPEED_VUART] = 8, [ASPEED_FMC] = 19, + [ASPEED_EHCI1] = 5, + [ASPEED_EHCI2] = 13, [ASPEED_SDMC] = 0, [ASPEED_SCU] = 21, [ASPEED_ADC] = 31, @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj) sizeof(s->spi[i]), typename); } + for (i = 0; i < sc->ehcis_num; i++) { + sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]), + sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI); + } + snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), typename); @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) s->spi[i].ctrl->flash_window_base); } + /* EHCI */ + for (i = 0; i < sc->ehcis_num; i++) { + object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, + sc->memmap[ASPEED_EHCI1 + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, + aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); + } + /* SDMC - SDRAM Memory Controller */ object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); if (err) { @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) sc->silicon_rev = AST2400_A1_SILICON_REV; sc->sram_size = 0x8000; sc->spis_num = 1; + sc->ehcis_num = 1; sc->wdts_num = 2; sc->macs_num = 2; sc->irqmap = aspeed_soc_ast2400_irqmap; @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) sc->silicon_rev = AST2500_A1_SILICON_REV; sc->sram_size = 0x9000; sc->spis_num = 2; + sc->ehcis_num = 2; sc->wdts_num = 3; sc->macs_num = 2; sc->irqmap = aspeed_soc_ast2500_irqmap; -- 2.20.1 From: Guenter Roeck <linux@roeck-us.net> Initialize EHCI controllers on AST2600 using the existing TYPE_PLATFORM_EHCI. After this change, booting ast2600-evb into Linux successfully instantiates a USB interface after the necessary changes are made to its devicetree files. ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver ehci-platform: EHCI generic platform driver ehci-platform 1e6a3000.usb: EHCI Host Controller ehci-platform 1e6a3000.usb: new USB bus registered, assigned bus number 1 ehci-platform 1e6a3000.usb: irq 25, io mem 0x1e6a3000 ehci-platform 1e6a3000.usb: USB 2.0 started, EHCI 1.00 usb usb1: Manufacturer: Linux 5.5.0-09825-ga0802f2d0ef5-dirty ehci_hcd usb 1-1: new high-speed USB device number 2 using ehci-platform Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200207174548.9087-1-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/aspeed_ast2600.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_FMC] = 0x1E620000, [ASPEED_SPI1] = 0x1E630000, [ASPEED_SPI2] = 0x1E641000, + [ASPEED_EHCI1] = 0x1E6A1000, + [ASPEED_EHCI2] = 0x1E6A3000, [ASPEED_MII1] = 0x1E650000, [ASPEED_MII2] = 0x1E650008, [ASPEED_MII3] = 0x1E650010, @@ -XXX,XX +XXX,XX @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_ADC] = 78, [ASPEED_XDMA] = 6, [ASPEED_SDHCI] = 43, + [ASPEED_EHCI1] = 5, + [ASPEED_EHCI2] = 9, [ASPEED_EMMC] = 15, [ASPEED_GPIO] = 40, [ASPEED_GPIO_1_8V] = 11, @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_init(Object *obj) sizeof(s->spi[i]), typename); } + for (i = 0; i < sc->ehcis_num; i++) { + sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]), + sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI); + } + snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), typename); @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) s->spi[i].ctrl->flash_window_base); } + /* EHCI */ + for (i = 0; i < sc->ehcis_num; i++) { + object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, + sc->memmap[ASPEED_EHCI1 + i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, + aspeed_soc_get_irq(s, ASPEED_EHCI1 + i)); + } + /* SDMC - SDRAM Memory Controller */ object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err); if (err) { @@ -XXX,XX +XXX,XX @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) sc->silicon_rev = AST2600_A0_SILICON_REV; sc->sram_size = 0x10000; sc->spis_num = 2; + sc->ehcis_num = 2; sc->wdts_num = 4; sc->macs_num = 4; sc->irqmap = aspeed_soc_ast2600_irqmap; -- 2.20.1 From: Chen Qun <kuhn.chenqun@huawei.com> It's easy to reproduce as follow: virsh qemu-monitor-command vm1 --pretty '{"execute": "device-list-properties", "arguments":{"typename":"exynos4210.uart"}}' ASAN shows memory leak stack: #1 0xfffd896d71cb in g_malloc0 (/lib64/libglib-2.0.so.0+0x571cb) #2 0xaaad270beee3 in timer_new_full /qemu/include/qemu/timer.h:530 #3 0xaaad270beee3 in timer_new /qemu/include/qemu/timer.h:551 #4 0xaaad270beee3 in timer_new_ns /qemu/include/qemu/timer.h:569 #5 0xaaad270beee3 in exynos4210_uart_init /qemu/hw/char/exynos4210_uart.c:677 #6 0xaaad275c8f4f in object_initialize_with_type /qemu/qom/object.c:516 #7 0xaaad275c91bb in object_new_with_type /qemu/qom/object.c:684 #8 0xaaad2755df2f in qmp_device_list_properties /qemu/qom/qom-qmp-cmds.c:152 Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200213025603.149432-1-kuhn.chenqun@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/char/exynos4210_uart.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index XXXXXXX..XXXXXXX 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_init(Object *obj) SysBusDevice *dev = SYS_BUS_DEVICE(obj); Exynos4210UartState *s = EXYNOS4210_UART(dev); - s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, - exynos4210_uart_timeout_int, s); s->wordtime = NANOSECONDS_PER_SECOND * 10 / 9600; /* memory mapping */ @@ -XXX,XX +XXX,XX @@ static void exynos4210_uart_realize(DeviceState *dev, Error **errp) { Exynos4210UartState *s = EXYNOS4210_UART(dev); + s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + exynos4210_uart_timeout_int, s); + qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive, exynos4210_uart_receive, exynos4210_uart_event, NULL, s, NULL, true); -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> When booting without device tree, the Linux kernels uses the $R1 register to determine the machine type. The list of values is registered at [1]. There are two entries for the Raspberry Pi: - https://www.arm.linux.org.uk/developer/machines/list.php?mid=3138 name: MACH_TYPE_BCM2708 value: 0xc42 (3138) status: Active, not mainlined date: 15 Oct 2010 - https://www.arm.linux.org.uk/developer/machines/list.php?mid=4828 name: MACH_TYPE_BCM2835 value: 4828 status: Active, mainlined date: 6 Dec 2013 QEMU always used the non-mainlined type MACH_TYPE_BCM2708. The value 0xc43 is registered to 'MX51_GGC' (processor i.MX51), and 0xc44 to 'Western Digital Sharespace NAS' (processor Marvell 88F5182). The Raspberry Pi foundation bootloader only sets the BCM2708 machine type, see [2] or [3]: 133 9: 134 mov r0, #0 135 ldr r1, =3138 @ BCM2708 machine id 136 ldr r2, atags @ ATAGS 137 bx r4 U-Boot only uses MACH_TYPE_BCM2708 (see [4]): 25 /* 26 * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, 27 * so 2708 has historically been used rather than a dedicated 2835 ID. 28 * 29 * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation 30 * chose to use someone else's previously registered machine ID (3139, MX51_GGC) 31 * rather than obtaining a valid ID:-/ 32 * 33 * For the bcm2837, hopefully a machine type is not needed, since everything 34 * is DT. 35 */ While the definition MACH_BCM2709 with value 0xc43 was introduced in a commit described "Add 2709 platform for Raspberry Pi 2" out of the mainline Linux kernel, it does not seem used, and the platform is introduced with Device Tree support anyway (see [5] and [6]). Remove the unused values (0xc43 introduced in commit 1df7d1f9303aef "raspi: add raspberry pi 2 machine" and 0xc44 in commit bade58166f4 "raspi: Raspberry Pi 3 support"), keeping only MACH_TYPE_BCM2708. [1] https://www.arm.linux.org.uk/developer/machines/ [2] https://github.com/raspberrypi/tools/blob/920c7ed2e/armstubs/armstub7.S#L135 [3] https://github.com/raspberrypi/tools/blob/49719d554/armstubs/armstub7.S#L64 [4] https://gitlab.denx.de/u-boot/u-boot/blob/v2015.04/include/configs/rpi-common.h#L18 [5] https://github.com/raspberrypi/linux/commit/d9fac63adac#diff-6722037d79570df5b392a49e0e006573R526 [6] http://lists.infradead.org/pipermail/linux-rpi-kernel/2015-February/001268.html Cc: Zoltán Baldaszti <bztemail@gmail.com> Cc: Pekka Enberg <penberg@iki.fi> Cc: Stephen Warren <swarren@nvidia.com> Cc: Kshitij Soni <kshitij.soni@broadcom.com> Cc: Michael Chan <michael.chan@broadcom.com> Cc: Andrew Baumann <Andrew.Baumann@microsoft.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20200208165645.15657-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ -/* Table of Linux board IDs for different Pi versions */ -static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; +/* Registered machine type (matches RPi Foundation bootloader and U-Boot) */ +#define MACH_TYPE_BCM2708 3138 typedef struct RasPiState { BCM283XState soc; @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) static struct arm_boot_info binfo; int r; - binfo.board_id = raspi_boardid[version]; + binfo.board_id = MACH_TYPE_BCM2708; binfo.ram_size = ram_size; binfo.nb_cpus = machine->smp.cpus; -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> We hardcode the board revision as 0xa21041 for the raspi2, and 0xa02082 for the raspi3: 166 static void raspi_init(MachineState *machine, int version) 167 { ... 194 int board_rev = version == 3 ? 0xa02082 : 0xa21041; These revision codes are for the 2B and 3B models, see: https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md Correct the board description. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200208165645.15657-3-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static void raspi2_init(MachineState *machine) static void raspi2_machine_init(MachineClass *mc) { - mc->desc = "Raspberry Pi 2"; + mc->desc = "Raspberry Pi 2B"; mc->init = raspi2_init; mc->block_default_type = IF_SD; mc->no_parallel = 1; @@ -XXX,XX +XXX,XX @@ static void raspi3_init(MachineState *machine) static void raspi3_machine_init(MachineClass *mc) { - mc->desc = "Raspberry Pi 3"; + mc->desc = "Raspberry Pi 3B"; mc->init = raspi3_init; mc->block_default_type = IF_SD; mc->no_parallel = 1; -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> The board revision encode the board version. Add a helper to extract the version, and use it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200208165645.15657-4-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ #include "qapi/error.h" #include "cpu.h" #include "hw/arm/bcm2836.h" +#include "hw/registerfields.h" #include "qemu/error-report.h" #include "hw/boards.h" #include "hw/loader.h" @@ -XXX,XX +XXX,XX @@ typedef struct RasPiState { MemoryRegion ram; } RasPiState; +/* + * Board revision codes: + * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/ + */ +FIELD(REV_CODE, REVISION, 0, 4); +FIELD(REV_CODE, TYPE, 4, 8); +FIELD(REV_CODE, PROCESSOR, 12, 4); +FIELD(REV_CODE, MANUFACTURER, 16, 4); +FIELD(REV_CODE, MEMORY_SIZE, 20, 3); +FIELD(REV_CODE, STYLE, 23, 1); + +static int board_processor_id(uint32_t board_rev) +{ + assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ + return FIELD_EX32(board_rev, REV_CODE, PROCESSOR); +} + +static int board_version(uint32_t board_rev) +{ + return board_processor_id(board_rev) + 1; +} + static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) { static const uint32_t smpboot[] = { @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo); } -static void raspi_init(MachineState *machine, int version) +static void raspi_init(MachineState *machine, uint32_t board_rev) { RasPiState *s = g_new0(RasPiState, 1); + int version = board_version(board_rev); uint32_t vcram_size; DriveInfo *di; BlockBackend *blk; @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) /* Setup the SOC */ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), &error_abort); - int board_rev = version == 3 ? 0xa02082 : 0xa21041; object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", &error_abort); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort); @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version) static void raspi2_init(MachineState *machine) { - raspi_init(machine, 2); + raspi_init(machine, 0xa21041); } static void raspi2_machine_init(MachineClass *mc) @@ -XXX,XX +XXX,XX @@ DEFINE_MACHINE("raspi2", raspi2_machine_init) #ifdef TARGET_AARCH64 static void raspi3_init(MachineState *machine) { - raspi_init(machine, 3); + raspi_init(machine, 0xa02082); } static void raspi3_machine_init(MachineClass *mc) -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> The board revision encode the amount of RAM. Add a helper to extract the RAM size, and use it. Since the amount of RAM is fixed (it is impossible to physically modify to have more or less RAM), do not allow sizes different than the one anounced by the manufacturer. Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200208165645.15657-5-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/cutils.h" #include "qapi/error.h" #include "cpu.h" #include "hw/arm/bcm2836.h" @@ -XXX,XX +XXX,XX @@ FIELD(REV_CODE, MANUFACTURER, 16, 4); FIELD(REV_CODE, MEMORY_SIZE, 20, 3); FIELD(REV_CODE, STYLE, 23, 1); +static uint64_t board_ram_size(uint32_t board_rev) +{ + assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ + return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE); +} + static int board_processor_id(uint32_t board_rev) { assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, uint32_t board_rev) { RasPiState *s = g_new0(RasPiState, 1); int version = board_version(board_rev); + uint64_t ram_size = board_ram_size(board_rev); uint32_t vcram_size; DriveInfo *di; BlockBackend *blk; BusState *bus; DeviceState *carddev; - if (machine->ram_size > 1 * GiB) { - error_report("Requested ram size is too large for this machine: " - "maximum is 1GB"); + if (machine->ram_size != ram_size) { + char *size_str = size_to_str(ram_size); + error_report("Invalid RAM size, should be %s", size_str); + g_free(size_str); exit(1); } -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> The board revision encode the processor type. Add a helper to extract the type, and use it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200208165645.15657-6-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static int board_version(uint32_t board_rev) return board_processor_id(board_rev) + 1; } +static const char *board_soc_type(uint32_t board_rev) +{ + static const char *soc_types[] = { + NULL, TYPE_BCM2836, TYPE_BCM2837, + }; + int proc_id = board_processor_id(board_rev); + + if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) { + error_report("Unsupported processor id '%d' (board revision: 0x%x)", + proc_id, board_rev); + exit(1); + } + return soc_types[proc_id]; +} + static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) { static const uint32_t smpboot[] = { @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, uint32_t board_rev) } object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), - version == 3 ? TYPE_BCM2837 : TYPE_BCM2836, - &error_abort, NULL); + board_soc_type(board_rev), &error_abort, NULL); /* Allocate and map RAM */ memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram", -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> There is no point in creating the SoC object before allocating the RAM. Move the call to keep all the SoC-related calls together. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200208165645.15657-7-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, uint32_t board_rev) exit(1); } - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), - board_soc_type(board_rev), &error_abort, NULL); - /* Allocate and map RAM */ memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram", machine->ram_size); @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, uint32_t board_rev) memory_region_add_subregion_overlap(get_system_memory(), 0, &s->ram, 0); /* Setup the SOC */ + object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), + board_soc_type(board_rev), &error_abort, NULL); object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), &error_abort); object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> QOM'ify RaspiMachineState. Now machines inherit of RaspiMachineClass. Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200208165645.15657-8-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 56 +++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 7 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */ #define MACH_TYPE_BCM2708 3138 -typedef struct RasPiState { +typedef struct RaspiMachineState { + /*< private >*/ + MachineState parent_obj; + /*< public >*/ BCM283XState soc; MemoryRegion ram; -} RasPiState; +} RaspiMachineState; + +typedef struct RaspiMachineClass { + /*< private >*/ + MachineClass parent_obj; + /*< public >*/ +} RaspiMachineClass; + +#define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") +#define RASPI_MACHINE(obj) \ + OBJECT_CHECK(RaspiMachineState, (obj), TYPE_RASPI_MACHINE) + +#define RASPI_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(RaspiMachineClass, (klass), TYPE_RASPI_MACHINE) +#define RASPI_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(RaspiMachineClass, (obj), TYPE_RASPI_MACHINE) /* * Board revision codes: @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) static void raspi_init(MachineState *machine, uint32_t board_rev) { - RasPiState *s = g_new0(RasPiState, 1); + RaspiMachineState *s = RASPI_MACHINE(machine); int version = board_version(board_rev); uint64_t ram_size = board_ram_size(board_rev); uint32_t vcram_size; @@ -XXX,XX +XXX,XX @@ static void raspi2_init(MachineState *machine) raspi_init(machine, 0xa21041); } -static void raspi2_machine_init(MachineClass *mc) +static void raspi2_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "Raspberry Pi 2B"; mc->init = raspi2_init; mc->block_default_type = IF_SD; @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_init(MachineClass *mc) mc->default_ram_size = 1 * GiB; mc->ignore_memory_transaction_failures = true; }; -DEFINE_MACHINE("raspi2", raspi2_machine_init) #ifdef TARGET_AARCH64 static void raspi3_init(MachineState *machine) @@ -XXX,XX +XXX,XX @@ static void raspi3_init(MachineState *machine) raspi_init(machine, 0xa02082); } -static void raspi3_machine_init(MachineClass *mc) +static void raspi3_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "Raspberry Pi 3B"; mc->init = raspi3_init; mc->block_default_type = IF_SD; @@ -XXX,XX +XXX,XX @@ static void raspi3_machine_init(MachineClass *mc) mc->default_cpus = BCM283X_NCPUS; mc->default_ram_size = 1 * GiB; } -DEFINE_MACHINE("raspi3", raspi3_machine_init) #endif + +static const TypeInfo raspi_machine_types[] = { + { + .name = MACHINE_TYPE_NAME("raspi2"), + .parent = TYPE_RASPI_MACHINE, + .class_init = raspi2_machine_class_init, +#ifdef TARGET_AARCH64 + }, { + .name = MACHINE_TYPE_NAME("raspi3"), + .parent = TYPE_RASPI_MACHINE, + .class_init = raspi3_machine_class_init, +#endif + }, { + .name = TYPE_RASPI_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(RaspiMachineState), + .class_size = sizeof(RaspiMachineClass), + .abstract = true, + } +}; + +DEFINE_TYPES(raspi_machine_types) -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> We want to have a common class_init(). The only value that matters (and changes) is the board revision. Pass the board_rev as class_data to class_init(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200208165645.15657-9-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ typedef struct RaspiMachineClass { /*< private >*/ MachineClass parent_obj; /*< public >*/ + uint32_t board_rev; } RaspiMachineClass; #define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common") @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo); } -static void raspi_init(MachineState *machine, uint32_t board_rev) +static void raspi_init(MachineState *machine) { + RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine); RaspiMachineState *s = RASPI_MACHINE(machine); + uint32_t board_rev = mc->board_rev; int version = board_version(board_rev); uint64_t ram_size = board_ram_size(board_rev); uint32_t vcram_size; @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, uint32_t board_rev) static void raspi2_init(MachineState *machine) { - raspi_init(machine, 0xa21041); + raspi_init(machine); } static void raspi2_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); + uint32_t board_rev = (uint32_t)(uintptr_t)data; + rmc->board_rev = board_rev; mc->desc = "Raspberry Pi 2B"; mc->init = raspi2_init; mc->block_default_type = IF_SD; @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_class_init(ObjectClass *oc, void *data) #ifdef TARGET_AARCH64 static void raspi3_init(MachineState *machine) { - raspi_init(machine, 0xa02082); + raspi_init(machine); } static void raspi3_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); + uint32_t board_rev = (uint32_t)(uintptr_t)data; + rmc->board_rev = board_rev; mc->desc = "Raspberry Pi 3B"; mc->init = raspi3_init; mc->block_default_type = IF_SD; @@ -XXX,XX +XXX,XX @@ static const TypeInfo raspi_machine_types[] = { .name = MACHINE_TYPE_NAME("raspi2"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi2_machine_class_init, + .class_data = (void *)0xa21041, #ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3"), .parent = TYPE_RASPI_MACHINE, .class_init = raspi3_machine_class_init, + .class_data = (void *)0xa02082, #endif }, { .name = TYPE_RASPI_MACHINE, -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> raspi_machine_init() access to board_rev via RaspiMachineClass. raspi2_init() and raspi3_init() do nothing. Call raspi_machine_init directly. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200208165645.15657-10-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo); } -static void raspi_init(MachineState *machine) +static void raspi_machine_init(MachineState *machine) { RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine); RaspiMachineState *s = RASPI_MACHINE(machine); @@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine) setup_boot(machine, version, machine->ram_size - vcram_size); } -static void raspi2_init(MachineState *machine) -{ - raspi_init(machine); -} - static void raspi2_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_class_init(ObjectClass *oc, void *data) rmc->board_rev = board_rev; mc->desc = "Raspberry Pi 2B"; - mc->init = raspi2_init; + mc->init = raspi_machine_init; mc->block_default_type = IF_SD; mc->no_parallel = 1; mc->no_floppy = 1; @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_class_init(ObjectClass *oc, void *data) }; #ifdef TARGET_AARCH64 -static void raspi3_init(MachineState *machine) -{ - raspi_init(machine); -} - static void raspi3_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -XXX,XX +XXX,XX @@ static void raspi3_machine_class_init(ObjectClass *oc, void *data) rmc->board_rev = board_rev; mc->desc = "Raspberry Pi 3B"; - mc->init = raspi3_init; + mc->init = raspi_machine_init; mc->block_default_type = IF_SD; mc->no_parallel = 1; mc->no_floppy = 1; -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> We added a helper to extract the RAM size from the board revision, and made board_rev a field of RaspiMachineClass. The class_init() can now use the helper to extract from the board revision the board-specific amount of RAM. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200208165645.15657-11-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_class_init(ObjectClass *oc, void *data) mc->max_cpus = BCM283X_NCPUS; mc->min_cpus = BCM283X_NCPUS; mc->default_cpus = BCM283X_NCPUS; - mc->default_ram_size = 1 * GiB; + mc->default_ram_size = board_ram_size(board_rev); mc->ignore_memory_transaction_failures = true; }; @@ -XXX,XX +XXX,XX @@ static void raspi3_machine_class_init(ObjectClass *oc, void *data) mc->max_cpus = BCM283X_NCPUS; mc->min_cpus = BCM283X_NCPUS; mc->default_cpus = BCM283X_NCPUS; - mc->default_ram_size = 1 * GiB; + mc->default_ram_size = board_ram_size(board_rev); } #endif -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> The board revision encode the model type. Add a helper to extract the model, and use it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200208165645.15657-12-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static const char *board_soc_type(uint32_t board_rev) return soc_types[proc_id]; } +static const char *board_type(uint32_t board_rev) +{ + static const char *types[] = { + "A", "B", "A+", "B+", "2B", "Alpha", "CM1", NULL, "3B", "Zero", + "CM3", NULL, "Zero W", "3B+", "3A+", NULL, "CM3+", "4B", + }; + assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */ + int bt = FIELD_EX32(board_rev, REV_CODE, TYPE); + if (bt >= ARRAY_SIZE(types) || !types[bt]) { + return "Unknown"; + } + return types[bt]; +} + static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) { static const uint32_t smpboot[] = { @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_class_init(ObjectClass *oc, void *data) uint32_t board_rev = (uint32_t)(uintptr_t)data; rmc->board_rev = board_rev; - mc->desc = "Raspberry Pi 2B"; + mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev)); mc->init = raspi_machine_init; mc->block_default_type = IF_SD; mc->no_parallel = 1; @@ -XXX,XX +XXX,XX @@ static void raspi3_machine_class_init(ObjectClass *oc, void *data) uint32_t board_rev = (uint32_t)(uintptr_t)data; rmc->board_rev = board_rev; - mc->desc = "Raspberry Pi 3B"; + mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev)); mc->init = raspi_machine_init; mc->block_default_type = IF_SD; mc->no_parallel = 1; -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> With the exception of the ignore_memory_transaction_failures flag set for the raspi2, both machine_class_init() methods are now identical. Merge them to keep a unique method. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200208165645.15657-13-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 31 ++++++------------------------- 1 file changed, 6 insertions(+), 25 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine) setup_boot(machine, version, machine->ram_size - vcram_size); } -static void raspi2_machine_class_init(ObjectClass *oc, void *data) +static void raspi_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); @@ -XXX,XX +XXX,XX @@ static void raspi2_machine_class_init(ObjectClass *oc, void *data) mc->min_cpus = BCM283X_NCPUS; mc->default_cpus = BCM283X_NCPUS; mc->default_ram_size = board_ram_size(board_rev); - mc->ignore_memory_transaction_failures = true; + if (board_version(board_rev) == 2) { + mc->ignore_memory_transaction_failures = true; + } }; -#ifdef TARGET_AARCH64 -static void raspi3_machine_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc); - uint32_t board_rev = (uint32_t)(uintptr_t)data; - - rmc->board_rev = board_rev; - mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev)); - mc->init = raspi_machine_init; - mc->block_default_type = IF_SD; - mc->no_parallel = 1; - mc->no_floppy = 1; - mc->no_cdrom = 1; - mc->max_cpus = BCM283X_NCPUS; - mc->min_cpus = BCM283X_NCPUS; - mc->default_cpus = BCM283X_NCPUS; - mc->default_ram_size = board_ram_size(board_rev); -} -#endif - static const TypeInfo raspi_machine_types[] = { { .name = MACHINE_TYPE_NAME("raspi2"), .parent = TYPE_RASPI_MACHINE, - .class_init = raspi2_machine_class_init, + .class_init = raspi_machine_class_init, .class_data = (void *)0xa21041, #ifdef TARGET_AARCH64 }, { .name = MACHINE_TYPE_NAME("raspi3"), .parent = TYPE_RASPI_MACHINE, - .class_init = raspi3_machine_class_init, + .class_init = raspi_machine_class_init, .class_data = (void *)0xa02082, #endif }, { -- 2.20.1 From: Philippe Mathieu-Daudé <f4bug@amsat.org> The count of ARM cores is encoded in the board revision. Add a helper to extract the number of cores, and use it. This will be helpful when we add the Raspi0/1 that have a single core. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200208165645.15657-14-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message as suggested by Igor] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/raspi.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -XXX,XX +XXX,XX @@ static const char *board_soc_type(uint32_t board_rev) return soc_types[proc_id]; } +static int cores_count(uint32_t board_rev) +{ + static const int soc_cores_count[] = { + 0, BCM283X_NCPUS, BCM283X_NCPUS, + }; + int proc_id = board_processor_id(board_rev); + + if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) { + error_report("Unsupported processor id '%d' (board revision: 0x%x)", + proc_id, board_rev); + exit(1); + } + return soc_cores_count[proc_id]; +} + static const char *board_type(uint32_t board_rev) { static const char *types[] = { @@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data) mc->no_parallel = 1; mc->no_floppy = 1; mc->no_cdrom = 1; - mc->max_cpus = BCM283X_NCPUS; - mc->min_cpus = BCM283X_NCPUS; - mc->default_cpus = BCM283X_NCPUS; + mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev); mc->default_ram_size = board_ram_size(board_rev); if (board_version(board_rev) == 2) { mc->ignore_memory_transaction_failures = true; -- 2.20.1 The ARMv8.1-VMID16 extension extends the VMID from 8 bits to 16 bits: * the ID_AA64MMFR1_EL1.VMIDBits field specifies whether the VMID is 8 or 16 bits * the VMID field in VTTBR_EL2 is extended to 16 bits * VTCR_EL2.VS lets the guest specify whether to use the full 16 bits, or use the backwards-compatible 8 bits For QEMU implementing this is trivial: * we do not track VMIDs in TLB entries, so we never use the VMID field * we treat any write to VTTBR_EL2, not just a change to the VMID field bits, as a "possible VMID change" that causes us to throw away TLB entries, so that code doesn't need changing * we allow the guest to read/write the VTCR_EL2.VS bit already So all that's missing is the ID register part: report that we support VMID16 in our 'max' CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200210120146.17631-1-peter.maydell@linaro.org --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ + t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ cpu->isar.id_aa64mmfr1 = t; t = cpu->isar.id_aa64mmfr2; -- 2.20.1 The following changes since commit b367db48126d4ee14579af6cf5cdbffeb9496627: Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20220127' into staging (2022-01-28 11:05:29 +0000) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220128 for you to fetch changes up to 2c023d3675a3ffb54fc30504dcd715bc6f6e234f: target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp (2022-01-28 14:30:36 +0000) ---------------------------------------------------------------- target-arm queue: * Update copyright dates to 2022 * hw/armv7m: Fix broken VMStateDescription * hw/char/exynos4210_uart: Fix crash on trying to load VM state * rtc: Move RTC function prototypes to their own header * xlnx-versal-virt: Support PMC SLCR * xlnx-versal-virt: Support OSPI flash memory controller * scripts: Explain the difference between linux-headers and standard-headers * target/arm: Log CPU index in 'Taking exception' log * arm_gicv3_its: Various bugfixes and cleanups * arm_gicv3_its: Implement the missing MOVI and MOVALL commands * ast2600: Fix address mapping of second SPI controller * target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp ---------------------------------------------------------------- Andrew Baumann (1): MAINTAINERS: Remove myself (for raspi). Cédric Le Goater (1): hw/arm: ast2600: Fix address mapping of second SPI controller Francisco Iglesias (10): hw/misc: Add a model of Versal's PMC SLCR hw/arm/xlnx-versal: 'Or' the interrupts from the BBRAM and RTC models hw/arm/xlnx-versal: Connect Versal's PMC SLCR include/hw/dma/xlnx_csu_dma: Add in missing includes in the header hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method hw/ssi: Add a model of Xilinx Versal's OSPI flash memory controller hw/arm/xlnx-versal: Connect the OSPI flash memory controller model hw/block/m25p80: Add support for Micron Xccela flash mt35xu01g hw/arm/xlnx-versal-virt: Connect mt35xu01g flashes to the OSPI MAINTAINERS: Add an entry for Xilinx Versal OSPI Peter Maydell (20): Update copyright dates to 2022 hw/armv7m: Fix broken VMStateDescription hw/char/exynos4210_uart: Fix crash on trying to load VM state rtc: Move RTC function prototypes to their own header scripts: Explain the difference between linux-headers and standard-headers target/arm: Log CPU index in 'Taking exception' log hw/intc/arm_gicv3_its: Add tracepoints hw/intc/arm_gicv3: Initialise dma_as in GIC, not ITS hw/intc/arm_gicv3_its: Don't clear GITS_CREADR when GITS_CTLR.ENABLED is set hw/intc/arm_gicv3_its: Don't clear GITS_CWRITER on writes to GITS_CBASER hw/intc/arm_gicv3: Honour GICD_CTLR.EnableGrp1NS for LPIs hw/intc/arm_gicv3_its: Sort ITS command list into numeric order hw/intc/arm_gicv3_redist: Remove unnecessary zero checks hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported hw/intc/arm_gicv3_its: Provide read accessor for translation_ops hw/intc/arm_gicv3_its: Make GITS_BASER<n> RAZ/WI for unimplemented registers hw/intc/arm_gicv3_its: Check table bounds against correct limit hw/intc/arm_gicv3_its: Implement MOVALL hw/intc/arm_gicv3_its: Implement MOVI target/arm: Use correct entrypoint for SVC taken from Hyp to Hyp docs/conf.py | 2 +- hw/intc/gicv3_internal.h | 43 +- include/hw/arm/xlnx-versal.h | 30 +- include/hw/dma/xlnx_csu_dma.h | 24 +- include/hw/intc/arm_gicv3_its_common.h | 1 - include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 78 ++ include/hw/ssi/xlnx-versal-ospi.h | 111 ++ include/qemu-common.h | 5 +- include/sysemu/rtc.h | 58 + target/arm/internals.h | 2 +- hw/arm/armv7m.c | 4 +- hw/arm/aspeed_ast2600.c | 2 +- hw/arm/omap1.c | 2 +- hw/arm/pxa2xx.c | 2 +- hw/arm/strongarm.c | 2 +- hw/arm/xlnx-versal-virt.c | 25 +- hw/arm/xlnx-versal.c | 190 ++- hw/block/m25p80.c | 2 + hw/char/exynos4210_uart.c | 2 +- hw/dma/xlnx_csu_dma.c | 17 + hw/intc/arm_gicv3.c | 1 + hw/intc/arm_gicv3_common.c | 9 + hw/intc/arm_gicv3_its.c | 258 +++- hw/intc/arm_gicv3_redist.c | 115 +- hw/misc/mac_via.c | 2 +- hw/misc/macio/cuda.c | 2 +- hw/misc/macio/pmu.c | 2 +- hw/misc/xlnx-versal-pmc-iou-slcr.c | 1446 ++++++++++++++++++++++ hw/ppc/spapr_rtc.c | 2 +- hw/rtc/allwinner-rtc.c | 2 +- hw/rtc/aspeed_rtc.c | 2 +- hw/rtc/ds1338.c | 2 +- hw/rtc/exynos4210_rtc.c | 2 +- hw/rtc/goldfish_rtc.c | 2 +- hw/rtc/m41t80.c | 2 +- hw/rtc/m48t59.c | 2 +- hw/rtc/mc146818rtc.c | 2 +- hw/rtc/pl031.c | 2 +- hw/rtc/twl92230.c | 2 +- hw/rtc/xlnx-zynqmp-rtc.c | 2 +- hw/s390x/tod-tcg.c | 2 +- hw/scsi/megasas.c | 2 +- hw/ssi/xlnx-versal-ospi.c | 1853 ++++++++++++++++++++++++++++ net/dump.c | 2 +- softmmu/rtc.c | 2 +- target/arm/helper.c | 13 +- target/arm/m_helper.c | 2 +- MAINTAINERS | 7 +- hw/intc/trace-events | 8 + hw/misc/meson.build | 5 +- hw/ssi/meson.build | 1 + scripts/update-linux-headers.sh | 16 + 52 files changed, 4300 insertions(+), 74 deletions(-) create mode 100644 include/hw/misc/xlnx-versal-pmc-iou-slcr.h create mode 100644 include/hw/ssi/xlnx-versal-ospi.h create mode 100644 include/sysemu/rtc.h create mode 100644 hw/misc/xlnx-versal-pmc-iou-slcr.c create mode 100644 hw/ssi/xlnx-versal-ospi.c It's a new year; update the copyright strings for our help/version/about information and for our documentation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220120124713.288303-1-peter.maydell@linaro.org --- docs/conf.py | 2 +- include/qemu-common.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/conf.py b/docs/conf.py index XXXXXXX..XXXXXXX 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -XXX,XX +XXX,XX @@ # General information about the project. project = u'QEMU' -copyright = u'2021, The QEMU Project Developers' +copyright = u'2022, The QEMU Project Developers' author = u'The QEMU Project Developers' # The version info for the project you're documenting, acts as replacement for diff --git a/include/qemu-common.h b/include/qemu-common.h index XXXXXXX..XXXXXXX 100644 --- a/include/qemu-common.h +++ b/include/qemu-common.h @@ -XXX,XX +XXX,XX @@ #define TFR(expr) do { if ((expr) != -1) break; } while (errno == EINTR) /* Copyright string for -version arguments, About dialogs, etc */ -#define QEMU_COPYRIGHT "Copyright (c) 2003-2021 " \ +#define QEMU_COPYRIGHT "Copyright (c) 2003-2022 " \ "Fabrice Bellard and the QEMU Project developers" /* Bug reporting information for --help arguments, About dialogs, etc */ -- 2.25.1 In commit d5093d961585f02 we added a VMStateDescription to the TYPE_ARMV7M object, to handle migration of its Clocks. However a cut-and-paste error meant we used the wrong struct name in the VMSTATE_CLOCK() macro arguments. The result was that attempting a 'savevm' might result in an assertion failure. Cc: qemu-stable@nongnu.org Buglink: https://gitlab.com/qemu-project/qemu/-/issues/803 Fixes: d5093d961585f02 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Ani Sinha <ani@anisinha.ca> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220120151609.433555-1-peter.maydell@linaro.org --- hw/arm/armv7m.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_armv7m = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_CLOCK(refclk, SysTickState), - VMSTATE_CLOCK(cpuclk, SysTickState), + VMSTATE_CLOCK(refclk, ARMv7MState), + VMSTATE_CLOCK(cpuclk, ARMv7MState), VMSTATE_END_OF_LIST() } }; -- 2.25.1 The exynos4210_uart_post_load() function assumes that it is passed the Exynos4210UartState, but it has been attached to the VMStateDescription for the Exynos4210UartFIFO type. The result is a SIGSEGV when attempting to load VM state for any machine type including this device. Fix the bug by attaching the post-load function to the VMSD for the Exynos4210UartState. This is the logical place for it, because the actions it does relate to the entire UART state, not just the FIFO. Thanks to the bug reporter @TrungNguyen1909 for the clear bug description and the suggested fix. Fixes: c9d3396d80fe7ece9b ("hw/char/exynos4210_uart: Implement post_load function") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/638 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220120151648.433736-1-peter.maydell@linaro.org --- hw/char/exynos4210_uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index XXXXXXX..XXXXXXX 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_uart_fifo = { .name = "exynos4210.uart.fifo", .version_id = 1, .minimum_version_id = 1, - .post_load = exynos4210_uart_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32(sp, Exynos4210UartFIFO), VMSTATE_UINT32(rp, Exynos4210UartFIFO), @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_uart = { .name = "exynos4210.uart", .version_id = 1, .minimum_version_id = 1, + .post_load = exynos4210_uart_post_load, .fields = (VMStateField[]) { VMSTATE_STRUCT(rx, Exynos4210UartState, 1, vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO), -- 2.25.1 softmmu/rtc.c defines two public functions: qemu_get_timedate() and qemu_timedate_diff(). Currently we keep the prototypes for these in qemu-common.h, but most files don't need them. Move them to their own header, a new include/sysemu/rtc.h. Since the C files using these two functions did not need to include qemu-common.h for any other reason, we can remove those include lines when we add the include of the new rtc.h. The license for the .h file follows that of the softmmu/rtc.c where both the functions are defined. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- include/qemu-common.h | 3 --- include/sysemu/rtc.h | 58 ++++++++++++++++++++++++++++++++++++++++ hw/arm/omap1.c | 2 +- hw/arm/pxa2xx.c | 2 +- hw/arm/strongarm.c | 2 +- hw/misc/mac_via.c | 2 +- hw/misc/macio/cuda.c | 2 +- hw/misc/macio/pmu.c | 2 +- hw/ppc/spapr_rtc.c | 2 +- hw/rtc/allwinner-rtc.c | 2 +- hw/rtc/aspeed_rtc.c | 2 +- hw/rtc/ds1338.c | 2 +- hw/rtc/exynos4210_rtc.c | 2 +- hw/rtc/goldfish_rtc.c | 2 +- hw/rtc/m41t80.c | 2 +- hw/rtc/m48t59.c | 2 +- hw/rtc/mc146818rtc.c | 2 +- hw/rtc/pl031.c | 2 +- hw/rtc/twl92230.c | 2 +- hw/rtc/xlnx-zynqmp-rtc.c | 2 +- hw/s390x/tod-tcg.c | 2 +- hw/scsi/megasas.c | 2 +- net/dump.c | 2 +- softmmu/rtc.c | 2 +- 24 files changed, 80 insertions(+), 25 deletions(-) create mode 100644 include/sysemu/rtc.h diff --git a/include/qemu-common.h b/include/qemu-common.h index XXXXXXX..XXXXXXX 100644 --- a/include/qemu-common.h +++ b/include/qemu-common.h @@ -XXX,XX +XXX,XX @@ int qemu_main(int argc, char **argv, char **envp); #endif -void qemu_get_timedate(struct tm *tm, int offset); -int qemu_timedate_diff(struct tm *tm); - void *qemu_oom_check(void *ptr); ssize_t qemu_write_full(int fd, const void *buf, size_t count) diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/sysemu/rtc.h @@ -XXX,XX +XXX,XX @@ +/* + * RTC configuration and clock read + * + * Copyright (c) 2003-2021 QEMU contributors + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef SYSEMU_RTC_H +#define SYSEMU_RTC_H + +/** + * qemu_get_timedate: Get the current RTC time + * @tm: struct tm to fill in with RTC time + * @offset: offset in seconds to adjust the RTC time by before + * converting to struct tm format. + * + * This function fills in @tm with the current RTC time, as adjusted + * by @offset (for example, if @offset is 3600 then the returned time/date + * will be one hour further ahead than the current RTC time). + * + * The usual use is by RTC device models, which should call this function + * to find the time/date value that they should return to the guest + * when it reads the RTC registers. + * + * The behaviour of the clock whose value this function returns will + * depend on the -rtc command line option passed by the user. + */ +void qemu_get_timedate(struct tm *tm, int offset); + +/** + * qemu_timedate_diff: Return difference between a struct tm and the RTC + * @tm: struct tm containing the date/time to compare against + * + * Returns the difference in seconds between the RTC clock time + * and the date/time specified in @tm. For example, if @tm specifies + * a timestamp one hour further ahead than the current RTC time + * then this function will return 3600. + */ +int qemu_timedate_diff(struct tm *tm); + +#endif diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -XXX,XX +XXX,XX @@ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qapi/error.h" -#include "qemu-common.h" #include "cpu.h" #include "exec/address-spaces.h" #include "hw/hw.h" @@ -XXX,XX +XXX,XX @@ #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" +#include "sysemu/rtc.h" #include "qemu/range.h" #include "hw/sysbus.h" #include "qemu/cutils.h" diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" @@ -XXX,XX +XXX,XX @@ #include "chardev/char-fe.h" #include "sysemu/blockdev.h" #include "sysemu/qtest.h" +#include "sysemu/rtc.h" #include "qemu/cutils.h" #include "qemu/log.h" #include "qom/object.h" diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "cpu.h" #include "hw/irq.h" #include "hw/qdev-properties.h" @@ -XXX,XX +XXX,XX @@ #include "chardev/char-fe.h" #include "chardev/char-serial.h" #include "sysemu/sysemu.h" +#include "sysemu/rtc.h" #include "hw/ssi/ssi.h" #include "qapi/error.h" #include "qemu/cutils.h" diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "migration/vmstate.h" #include "hw/sysbus.h" #include "hw/irq.h" @@ -XXX,XX +XXX,XX @@ #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" #include "sysemu/block-backend.h" +#include "sysemu/rtc.h" #include "trace.h" #include "qemu/log.h" diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "hw/ppc/mac.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -XXX,XX +XXX,XX @@ #include "qapi/error.h" #include "qemu/timer.h" #include "sysemu/runstate.h" +#include "sysemu/rtc.h" #include "qapi/error.h" #include "qemu/cutils.h" #include "qemu/log.h" diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "hw/ppc/mac.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -XXX,XX +XXX,XX @@ #include "qapi/error.h" #include "qemu/timer.h" #include "sysemu/runstate.h" +#include "sysemu/rtc.h" #include "qapi/error.h" #include "qemu/cutils.h" #include "qemu/log.h" diff --git a/hw/ppc/spapr_rtc.c b/hw/ppc/spapr_rtc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/ppc/spapr_rtc.c +++ b/hw/ppc/spapr_rtc.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/timer.h" #include "sysemu/sysemu.h" +#include "sysemu/rtc.h" #include "hw/ppc/spapr.h" #include "migration/vmstate.h" #include "qapi/error.h" diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/allwinner-rtc.c +++ b/hw/rtc/allwinner-rtc.c @@ -XXX,XX +XXX,XX @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" -#include "qemu-common.h" #include "hw/qdev-properties.h" #include "hw/rtc/allwinner-rtc.h" +#include "sysemu/rtc.h" #include "trace.h" /* RTC registers */ diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/aspeed_rtc.c +++ b/hw/rtc/aspeed_rtc.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "hw/rtc/aspeed_rtc.h" #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/timer.h" +#include "sysemu/rtc.h" #include "trace.h" diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/ds1338.c +++ b/hw/rtc/ds1338.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "hw/i2c/i2c.h" #include "migration/vmstate.h" #include "qemu/bcd.h" #include "qemu/module.h" #include "qom/object.h" +#include "sysemu/rtc.h" /* Size of NVRAM including both the user-accessible area and the * secondary register area. diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/exynos4210_rtc.c +++ b/hw/rtc/exynos4210_rtc.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/log.h" #include "qemu/module.h" #include "hw/sysbus.h" @@ -XXX,XX +XXX,XX @@ #include "hw/arm/exynos4210.h" #include "qom/object.h" +#include "sysemu/rtc.h" #define DEBUG_RTC 0 diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/goldfish_rtc.c +++ b/hw/rtc/goldfish_rtc.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "hw/rtc/goldfish_rtc.h" #include "migration/vmstate.h" #include "hw/irq.h" @@ -XXX,XX +XXX,XX @@ #include "qemu/bitops.h" #include "qemu/timer.h" #include "sysemu/sysemu.h" +#include "sysemu/rtc.h" #include "qemu/cutils.h" #include "qemu/log.h" diff --git a/hw/rtc/m41t80.c b/hw/rtc/m41t80.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/m41t80.c +++ b/hw/rtc/m41t80.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/log.h" #include "qemu/module.h" #include "qemu/timer.h" #include "qemu/bcd.h" #include "hw/i2c/i2c.h" #include "qom/object.h" +#include "sysemu/rtc.h" #define TYPE_M41T80 "m41t80" OBJECT_DECLARE_SIMPLE_TYPE(M41t80State, M41T80) diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/m48t59.c +++ b/hw/rtc/m48t59.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/rtc/m48t59.h" #include "qemu/timer.h" #include "sysemu/runstate.h" +#include "sysemu/rtc.h" #include "sysemu/sysemu.h" #include "hw/sysbus.h" #include "qapi/error.h" diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/cutils.h" #include "qemu/module.h" #include "qemu/bcd.h" @@ -XXX,XX +XXX,XX @@ #include "sysemu/replay.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" +#include "sysemu/rtc.h" #include "hw/rtc/mc146818rtc.h" #include "hw/rtc/mc146818rtc_regs.h" #include "migration/vmstate.h" diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/pl031.c +++ b/hw/rtc/pl031.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "hw/rtc/pl031.h" #include "migration/vmstate.h" #include "hw/irq.h" @@ -XXX,XX +XXX,XX @@ #include "hw/sysbus.h" #include "qemu/timer.h" #include "sysemu/sysemu.h" +#include "sysemu/rtc.h" #include "qemu/cutils.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/twl92230.c +++ b/hw/rtc/twl92230.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/timer.h" #include "hw/i2c/i2c.h" #include "hw/irq.h" #include "migration/qemu-file-types.h" #include "migration/vmstate.h" #include "sysemu/sysemu.h" +#include "sysemu/rtc.h" #include "qemu/bcd.h" #include "qemu/module.h" #include "qom/object.h" diff --git a/hw/rtc/xlnx-zynqmp-rtc.c b/hw/rtc/xlnx-zynqmp-rtc.c index XXXXXXX..XXXXXXX 100644 --- a/hw/rtc/xlnx-zynqmp-rtc.c +++ b/hw/rtc/xlnx-zynqmp-rtc.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "hw/sysbus.h" #include "hw/register.h" #include "qemu/bitops.h" @@ -XXX,XX +XXX,XX @@ #include "hw/irq.h" #include "qemu/cutils.h" #include "sysemu/sysemu.h" +#include "sysemu/rtc.h" #include "trace.h" #include "hw/rtc/xlnx-zynqmp-rtc.h" #include "migration/vmstate.h" diff --git a/hw/s390x/tod-tcg.c b/hw/s390x/tod-tcg.c index XXXXXXX..XXXXXXX 100644 --- a/hw/s390x/tod-tcg.c +++ b/hw/s390x/tod-tcg.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qapi/error.h" #include "hw/s390x/tod.h" #include "qemu/timer.h" @@ -XXX,XX +XXX,XX @@ #include "qemu/module.h" #include "cpu.h" #include "tcg/tcg_s390x.h" +#include "sysemu/rtc.h" static void qemu_s390_tod_get(const S390TODState *td, S390TOD *tod, Error **errp) diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index XXXXXXX..XXXXXXX 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "hw/pci/pci.h" #include "hw/qdev-properties.h" #include "sysemu/dma.h" #include "sysemu/block-backend.h" +#include "sysemu/rtc.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" #include "qemu/iov.h" diff --git a/net/dump.c b/net/dump.c index XXXXXXX..XXXXXXX 100644 --- a/net/dump.c +++ b/net/dump.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "clients.h" #include "qapi/error.h" #include "qemu/error-report.h" @@ -XXX,XX +XXX,XX @@ #include "qapi/visitor.h" #include "net/filter.h" #include "qom/object.h" +#include "sysemu/rtc.h" typedef struct DumpState { int64_t start_ts; diff --git a/softmmu/rtc.c b/softmmu/rtc.c index XXXXXXX..XXXXXXX 100644 --- a/softmmu/rtc.c +++ b/softmmu/rtc.c @@ -XXX,XX +XXX,XX @@ */ #include "qemu/osdep.h" -#include "qemu-common.h" #include "qemu/cutils.h" #include "qapi/error.h" #include "qapi/qmp/qerror.h" @@ -XXX,XX +XXX,XX @@ #include "qom/object.h" #include "sysemu/replay.h" #include "sysemu/sysemu.h" +#include "sysemu/rtc.h" static enum { RTC_BASE_UTC, -- 2.25.1 From: Francisco Iglesias <francisco.iglesias@xilinx.com> Add a model of Versal's PMC SLCR (system-level control registers). Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-2-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 78 ++ hw/misc/xlnx-versal-pmc-iou-slcr.c | 1446 ++++++++++++++++++++ hw/misc/meson.build | 5 +- 3 files changed, 1528 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/xlnx-versal-pmc-iou-slcr.h create mode 100644 hw/misc/xlnx-versal-pmc-iou-slcr.c diff --git a/include/hw/misc/xlnx-versal-pmc-iou-slcr.h b/include/hw/misc/xlnx-versal-pmc-iou-slcr.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/misc/xlnx-versal-pmc-iou-slcr.h @@ -XXX,XX +XXX,XX @@ +/* + * Header file for the Xilinx Versal's PMC IOU SLCR + * + * Copyright (C) 2021 Xilinx Inc + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* + * This is a model of Xilinx Versal's PMC I/O Peripheral Control and Status + * module documented in Versal's Technical Reference manual [1] and the Versal + * ACAP Register reference [2]. + * + * References: + * + * [1] Versal ACAP Technical Reference Manual, + * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf + * + * [2] Versal ACAP Register Reference, + * https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___pmc_iop_slcr.html + * + * QEMU interface: + * + sysbus MMIO region 0: MemoryRegion for the device's registers + * + sysbus IRQ 0: PMC (AXI and APB) parity error interrupt detected by the PMC + * I/O peripherals. + * + sysbus IRQ 1: Device interrupt. + * + Named GPIO output "sd-emmc-sel[0]": Enables 0: SD mode or 1: eMMC mode on + * SD/eMMC controller 0. + * + Named GPIO output "sd-emmc-sel[1]": Enables 0: SD mode or 1: eMMC mode on + * SD/eMMC controller 1. + * + Named GPIO output "qspi-ospi-mux-sel": Selects 0: QSPI linear region or 1: + * OSPI linear region. + * + Named GPIO output "ospi-mux-sel": Selects 0: OSPI Indirect access mode or + * 1: OSPI direct access mode. + */ + +#ifndef XILINX_VERSAL_PMC_IOU_SLCR_H +#define XILINX_VERSAL_PMC_IOU_SLCR_H + +#include "hw/register.h" + +#define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr" + +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalPmcIouSlcr, XILINX_VERSAL_PMC_IOU_SLCR) + +#define XILINX_VERSAL_PMC_IOU_SLCR_R_MAX (0x828 / 4 + 1) + +struct XlnxVersalPmcIouSlcr { + SysBusDevice parent_obj; + MemoryRegion iomem; + qemu_irq irq_parity_imr; + qemu_irq irq_imr; + qemu_irq sd_emmc_sel[2]; + qemu_irq qspi_ospi_mux_sel; + qemu_irq ospi_mux_sel; + + uint32_t regs[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX]; + RegisterInfo regs_info[XILINX_VERSAL_PMC_IOU_SLCR_R_MAX]; +}; + +#endif /* XILINX_VERSAL_PMC_IOU_SLCR_H */ diff --git a/hw/misc/xlnx-versal-pmc-iou-slcr.c b/hw/misc/xlnx-versal-pmc-iou-slcr.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/misc/xlnx-versal-pmc-iou-slcr.c @@ -XXX,XX +XXX,XX @@ +/* + * QEMU model of Versal's PMC IOU SLCR (system level control registers) + * + * Copyright (c) 2021 Xilinx Inc. + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "hw/irq.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/misc/xlnx-versal-pmc-iou-slcr.h" + +#ifndef XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG +#define XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG 0 +#endif + +REG32(MIO_PIN_0, 0x0) + FIELD(MIO_PIN_0, L3_SEL, 7, 3) + FIELD(MIO_PIN_0, L2_SEL, 5, 2) + FIELD(MIO_PIN_0, L1_SEL, 3, 2) + FIELD(MIO_PIN_0, L0_SEL, 1, 2) +REG32(MIO_PIN_1, 0x4) + FIELD(MIO_PIN_1, L3_SEL, 7, 3) + FIELD(MIO_PIN_1, L2_SEL, 5, 2) + FIELD(MIO_PIN_1, L1_SEL, 3, 2) + FIELD(MIO_PIN_1, L0_SEL, 1, 2) +REG32(MIO_PIN_2, 0x8) + FIELD(MIO_PIN_2, L3_SEL, 7, 3) + FIELD(MIO_PIN_2, L2_SEL, 5, 2) + FIELD(MIO_PIN_2, L1_SEL, 3, 2) + FIELD(MIO_PIN_2, L0_SEL, 1, 2) +REG32(MIO_PIN_3, 0xc) + FIELD(MIO_PIN_3, L3_SEL, 7, 3) + FIELD(MIO_PIN_3, L2_SEL, 5, 2) + FIELD(MIO_PIN_3, L1_SEL, 3, 2) + FIELD(MIO_PIN_3, L0_SEL, 1, 2) +REG32(MIO_PIN_4, 0x10) + FIELD(MIO_PIN_4, L3_SEL, 7, 3) + FIELD(MIO_PIN_4, L2_SEL, 5, 2) + FIELD(MIO_PIN_4, L1_SEL, 3, 2) + FIELD(MIO_PIN_4, L0_SEL, 1, 2) +REG32(MIO_PIN_5, 0x14) + FIELD(MIO_PIN_5, L3_SEL, 7, 3) + FIELD(MIO_PIN_5, L2_SEL, 5, 2) + FIELD(MIO_PIN_5, L1_SEL, 3, 2) + FIELD(MIO_PIN_5, L0_SEL, 1, 2) +REG32(MIO_PIN_6, 0x18) + FIELD(MIO_PIN_6, L3_SEL, 7, 3) + FIELD(MIO_PIN_6, L2_SEL, 5, 2) + FIELD(MIO_PIN_6, L1_SEL, 3, 2) + FIELD(MIO_PIN_6, L0_SEL, 1, 2) +REG32(MIO_PIN_7, 0x1c) + FIELD(MIO_PIN_7, L3_SEL, 7, 3) + FIELD(MIO_PIN_7, L2_SEL, 5, 2) + FIELD(MIO_PIN_7, L1_SEL, 3, 2) + FIELD(MIO_PIN_7, L0_SEL, 1, 2) +REG32(MIO_PIN_8, 0x20) + FIELD(MIO_PIN_8, L3_SEL, 7, 3) + FIELD(MIO_PIN_8, L2_SEL, 5, 2) + FIELD(MIO_PIN_8, L1_SEL, 3, 2) + FIELD(MIO_PIN_8, L0_SEL, 1, 2) +REG32(MIO_PIN_9, 0x24) + FIELD(MIO_PIN_9, L3_SEL, 7, 3) + FIELD(MIO_PIN_9, L2_SEL, 5, 2) + FIELD(MIO_PIN_9, L1_SEL, 3, 2) + FIELD(MIO_PIN_9, L0_SEL, 1, 2) +REG32(MIO_PIN_10, 0x28) + FIELD(MIO_PIN_10, L3_SEL, 7, 3) + FIELD(MIO_PIN_10, L2_SEL, 5, 2) + FIELD(MIO_PIN_10, L1_SEL, 3, 2) + FIELD(MIO_PIN_10, L0_SEL, 1, 2) +REG32(MIO_PIN_11, 0x2c) + FIELD(MIO_PIN_11, L3_SEL, 7, 3) + FIELD(MIO_PIN_11, L2_SEL, 5, 2) + FIELD(MIO_PIN_11, L1_SEL, 3, 2) + FIELD(MIO_PIN_11, L0_SEL, 1, 2) +REG32(MIO_PIN_12, 0x30) + FIELD(MIO_PIN_12, L3_SEL, 7, 3) + FIELD(MIO_PIN_12, L2_SEL, 5, 2) + FIELD(MIO_PIN_12, L1_SEL, 3, 2) + FIELD(MIO_PIN_12, L0_SEL, 1, 2) +REG32(MIO_PIN_13, 0x34) + FIELD(MIO_PIN_13, L3_SEL, 7, 3) + FIELD(MIO_PIN_13, L2_SEL, 5, 2) + FIELD(MIO_PIN_13, L1_SEL, 3, 2) + FIELD(MIO_PIN_13, L0_SEL, 1, 2) +REG32(MIO_PIN_14, 0x38) + FIELD(MIO_PIN_14, L3_SEL, 7, 3) + FIELD(MIO_PIN_14, L2_SEL, 5, 2) + FIELD(MIO_PIN_14, L1_SEL, 3, 2) + FIELD(MIO_PIN_14, L0_SEL, 1, 2) +REG32(MIO_PIN_15, 0x3c) + FIELD(MIO_PIN_15, L3_SEL, 7, 3) + FIELD(MIO_PIN_15, L2_SEL, 5, 2) + FIELD(MIO_PIN_15, L1_SEL, 3, 2) + FIELD(MIO_PIN_15, L0_SEL, 1, 2) +REG32(MIO_PIN_16, 0x40) + FIELD(MIO_PIN_16, L3_SEL, 7, 3) + FIELD(MIO_PIN_16, L2_SEL, 5, 2) + FIELD(MIO_PIN_16, L1_SEL, 3, 2) + FIELD(MIO_PIN_16, L0_SEL, 1, 2) +REG32(MIO_PIN_17, 0x44) + FIELD(MIO_PIN_17, L3_SEL, 7, 3) + FIELD(MIO_PIN_17, L2_SEL, 5, 2) + FIELD(MIO_PIN_17, L1_SEL, 3, 2) + FIELD(MIO_PIN_17, L0_SEL, 1, 2) +REG32(MIO_PIN_18, 0x48) + FIELD(MIO_PIN_18, L3_SEL, 7, 3) + FIELD(MIO_PIN_18, L2_SEL, 5, 2) + FIELD(MIO_PIN_18, L1_SEL, 3, 2) + FIELD(MIO_PIN_18, L0_SEL, 1, 2) +REG32(MIO_PIN_19, 0x4c) + FIELD(MIO_PIN_19, L3_SEL, 7, 3) + FIELD(MIO_PIN_19, L2_SEL, 5, 2) + FIELD(MIO_PIN_19, L1_SEL, 3, 2) + FIELD(MIO_PIN_19, L0_SEL, 1, 2) +REG32(MIO_PIN_20, 0x50) + FIELD(MIO_PIN_20, L3_SEL, 7, 3) + FIELD(MIO_PIN_20, L2_SEL, 5, 2) + FIELD(MIO_PIN_20, L1_SEL, 3, 2) + FIELD(MIO_PIN_20, L0_SEL, 1, 2) +REG32(MIO_PIN_21, 0x54) + FIELD(MIO_PIN_21, L3_SEL, 7, 3) + FIELD(MIO_PIN_21, L2_SEL, 5, 2) + FIELD(MIO_PIN_21, L1_SEL, 3, 2) + FIELD(MIO_PIN_21, L0_SEL, 1, 2) +REG32(MIO_PIN_22, 0x58) + FIELD(MIO_PIN_22, L3_SEL, 7, 3) + FIELD(MIO_PIN_22, L2_SEL, 5, 2) + FIELD(MIO_PIN_22, L1_SEL, 3, 2) + FIELD(MIO_PIN_22, L0_SEL, 1, 2) +REG32(MIO_PIN_23, 0x5c) + FIELD(MIO_PIN_23, L3_SEL, 7, 3) + FIELD(MIO_PIN_23, L2_SEL, 5, 2) + FIELD(MIO_PIN_23, L1_SEL, 3, 2) + FIELD(MIO_PIN_23, L0_SEL, 1, 2) +REG32(MIO_PIN_24, 0x60) + FIELD(MIO_PIN_24, L3_SEL, 7, 3) + FIELD(MIO_PIN_24, L2_SEL, 5, 2) + FIELD(MIO_PIN_24, L1_SEL, 3, 2) + FIELD(MIO_PIN_24, L0_SEL, 1, 2) +REG32(MIO_PIN_25, 0x64) + FIELD(MIO_PIN_25, L3_SEL, 7, 3) + FIELD(MIO_PIN_25, L2_SEL, 5, 2) + FIELD(MIO_PIN_25, L1_SEL, 3, 2) + FIELD(MIO_PIN_25, L0_SEL, 1, 2) +REG32(MIO_PIN_26, 0x68) + FIELD(MIO_PIN_26, L3_SEL, 7, 3) + FIELD(MIO_PIN_26, L2_SEL, 5, 2) + FIELD(MIO_PIN_26, L1_SEL, 3, 2) + FIELD(MIO_PIN_26, L0_SEL, 1, 2) +REG32(MIO_PIN_27, 0x6c) + FIELD(MIO_PIN_27, L3_SEL, 7, 3) + FIELD(MIO_PIN_27, L2_SEL, 5, 2) + FIELD(MIO_PIN_27, L1_SEL, 3, 2) + FIELD(MIO_PIN_27, L0_SEL, 1, 2) +REG32(MIO_PIN_28, 0x70) + FIELD(MIO_PIN_28, L3_SEL, 7, 3) + FIELD(MIO_PIN_28, L2_SEL, 5, 2) + FIELD(MIO_PIN_28, L1_SEL, 3, 2) + FIELD(MIO_PIN_28, L0_SEL, 1, 2) +REG32(MIO_PIN_29, 0x74) + FIELD(MIO_PIN_29, L3_SEL, 7, 3) + FIELD(MIO_PIN_29, L2_SEL, 5, 2) + FIELD(MIO_PIN_29, L1_SEL, 3, 2) + FIELD(MIO_PIN_29, L0_SEL, 1, 2) +REG32(MIO_PIN_30, 0x78) + FIELD(MIO_PIN_30, L3_SEL, 7, 3) + FIELD(MIO_PIN_30, L2_SEL, 5, 2) + FIELD(MIO_PIN_30, L1_SEL, 3, 2) + FIELD(MIO_PIN_30, L0_SEL, 1, 2) +REG32(MIO_PIN_31, 0x7c) + FIELD(MIO_PIN_31, L3_SEL, 7, 3) + FIELD(MIO_PIN_31, L2_SEL, 5, 2) + FIELD(MIO_PIN_31, L1_SEL, 3, 2) + FIELD(MIO_PIN_31, L0_SEL, 1, 2) +REG32(MIO_PIN_32, 0x80) + FIELD(MIO_PIN_32, L3_SEL, 7, 3) + FIELD(MIO_PIN_32, L2_SEL, 5, 2) + FIELD(MIO_PIN_32, L1_SEL, 3, 2) + FIELD(MIO_PIN_32, L0_SEL, 1, 2) +REG32(MIO_PIN_33, 0x84) + FIELD(MIO_PIN_33, L3_SEL, 7, 3) + FIELD(MIO_PIN_33, L2_SEL, 5, 2) + FIELD(MIO_PIN_33, L1_SEL, 3, 2) + FIELD(MIO_PIN_33, L0_SEL, 1, 2) +REG32(MIO_PIN_34, 0x88) + FIELD(MIO_PIN_34, L3_SEL, 7, 3) + FIELD(MIO_PIN_34, L2_SEL, 5, 2) + FIELD(MIO_PIN_34, L1_SEL, 3, 2) + FIELD(MIO_PIN_34, L0_SEL, 1, 2) +REG32(MIO_PIN_35, 0x8c) + FIELD(MIO_PIN_35, L3_SEL, 7, 3) + FIELD(MIO_PIN_35, L2_SEL, 5, 2) + FIELD(MIO_PIN_35, L1_SEL, 3, 2) + FIELD(MIO_PIN_35, L0_SEL, 1, 2) +REG32(MIO_PIN_36, 0x90) + FIELD(MIO_PIN_36, L3_SEL, 7, 3) + FIELD(MIO_PIN_36, L2_SEL, 5, 2) + FIELD(MIO_PIN_36, L1_SEL, 3, 2) + FIELD(MIO_PIN_36, L0_SEL, 1, 2) +REG32(MIO_PIN_37, 0x94) + FIELD(MIO_PIN_37, L3_SEL, 7, 3) + FIELD(MIO_PIN_37, L2_SEL, 5, 2) + FIELD(MIO_PIN_37, L1_SEL, 3, 2) + FIELD(MIO_PIN_37, L0_SEL, 1, 2) +REG32(MIO_PIN_38, 0x98) + FIELD(MIO_PIN_38, L3_SEL, 7, 3) + FIELD(MIO_PIN_38, L2_SEL, 5, 2) + FIELD(MIO_PIN_38, L1_SEL, 3, 2) + FIELD(MIO_PIN_38, L0_SEL, 1, 2) +REG32(MIO_PIN_39, 0x9c) + FIELD(MIO_PIN_39, L3_SEL, 7, 3) + FIELD(MIO_PIN_39, L2_SEL, 5, 2) + FIELD(MIO_PIN_39, L1_SEL, 3, 2) + FIELD(MIO_PIN_39, L0_SEL, 1, 2) +REG32(MIO_PIN_40, 0xa0) + FIELD(MIO_PIN_40, L3_SEL, 7, 3) + FIELD(MIO_PIN_40, L2_SEL, 5, 2) + FIELD(MIO_PIN_40, L1_SEL, 3, 2) + FIELD(MIO_PIN_40, L0_SEL, 1, 2) +REG32(MIO_PIN_41, 0xa4) + FIELD(MIO_PIN_41, L3_SEL, 7, 3) + FIELD(MIO_PIN_41, L2_SEL, 5, 2) + FIELD(MIO_PIN_41, L1_SEL, 3, 2) + FIELD(MIO_PIN_41, L0_SEL, 1, 2) +REG32(MIO_PIN_42, 0xa8) + FIELD(MIO_PIN_42, L3_SEL, 7, 3) + FIELD(MIO_PIN_42, L2_SEL, 5, 2) + FIELD(MIO_PIN_42, L1_SEL, 3, 2) + FIELD(MIO_PIN_42, L0_SEL, 1, 2) +REG32(MIO_PIN_43, 0xac) + FIELD(MIO_PIN_43, L3_SEL, 7, 3) + FIELD(MIO_PIN_43, L2_SEL, 5, 2) + FIELD(MIO_PIN_43, L1_SEL, 3, 2) + FIELD(MIO_PIN_43, L0_SEL, 1, 2) +REG32(MIO_PIN_44, 0xb0) + FIELD(MIO_PIN_44, L3_SEL, 7, 3) + FIELD(MIO_PIN_44, L2_SEL, 5, 2) + FIELD(MIO_PIN_44, L1_SEL, 3, 2) + FIELD(MIO_PIN_44, L0_SEL, 1, 2) +REG32(MIO_PIN_45, 0xb4) + FIELD(MIO_PIN_45, L3_SEL, 7, 3) + FIELD(MIO_PIN_45, L2_SEL, 5, 2) + FIELD(MIO_PIN_45, L1_SEL, 3, 2) + FIELD(MIO_PIN_45, L0_SEL, 1, 2) +REG32(MIO_PIN_46, 0xb8) + FIELD(MIO_PIN_46, L3_SEL, 7, 3) + FIELD(MIO_PIN_46, L2_SEL, 5, 2) + FIELD(MIO_PIN_46, L1_SEL, 3, 2) + FIELD(MIO_PIN_46, L0_SEL, 1, 2) +REG32(MIO_PIN_47, 0xbc) + FIELD(MIO_PIN_47, L3_SEL, 7, 3) + FIELD(MIO_PIN_47, L2_SEL, 5, 2) + FIELD(MIO_PIN_47, L1_SEL, 3, 2) + FIELD(MIO_PIN_47, L0_SEL, 1, 2) +REG32(MIO_PIN_48, 0xc0) + FIELD(MIO_PIN_48, L3_SEL, 7, 3) + FIELD(MIO_PIN_48, L2_SEL, 5, 2) + FIELD(MIO_PIN_48, L1_SEL, 3, 2) + FIELD(MIO_PIN_48, L0_SEL, 1, 2) +REG32(MIO_PIN_49, 0xc4) + FIELD(MIO_PIN_49, L3_SEL, 7, 3) + FIELD(MIO_PIN_49, L2_SEL, 5, 2) + FIELD(MIO_PIN_49, L1_SEL, 3, 2) + FIELD(MIO_PIN_49, L0_SEL, 1, 2) +REG32(MIO_PIN_50, 0xc8) + FIELD(MIO_PIN_50, L3_SEL, 7, 3) + FIELD(MIO_PIN_50, L2_SEL, 5, 2) + FIELD(MIO_PIN_50, L1_SEL, 3, 2) + FIELD(MIO_PIN_50, L0_SEL, 1, 2) +REG32(MIO_PIN_51, 0xcc) + FIELD(MIO_PIN_51, L3_SEL, 7, 3) + FIELD(MIO_PIN_51, L2_SEL, 5, 2) + FIELD(MIO_PIN_51, L1_SEL, 3, 2) + FIELD(MIO_PIN_51, L0_SEL, 1, 2) +REG32(BNK0_EN_RX, 0x100) + FIELD(BNK0_EN_RX, BNK0_EN_RX, 0, 26) +REG32(BNK0_SEL_RX0, 0x104) +REG32(BNK0_SEL_RX1, 0x108) + FIELD(BNK0_SEL_RX1, BNK0_SEL_RX, 0, 20) +REG32(BNK0_EN_RX_SCHMITT_HYST, 0x10c) + FIELD(BNK0_EN_RX_SCHMITT_HYST, BNK0_EN_RX_SCHMITT_HYST, 0, 26) +REG32(BNK0_EN_WK_PD, 0x110) + FIELD(BNK0_EN_WK_PD, BNK0_EN_WK_PD, 0, 26) +REG32(BNK0_EN_WK_PU, 0x114) + FIELD(BNK0_EN_WK_PU, BNK0_EN_WK_PU, 0, 26) +REG32(BNK0_SEL_DRV0, 0x118) +REG32(BNK0_SEL_DRV1, 0x11c) + FIELD(BNK0_SEL_DRV1, BNK0_SEL_DRV, 0, 20) +REG32(BNK0_SEL_SLEW, 0x120) + FIELD(BNK0_SEL_SLEW, BNK0_SEL_SLEW, 0, 26) +REG32(BNK0_EN_DFT_OPT_INV, 0x124) + FIELD(BNK0_EN_DFT_OPT_INV, BNK0_EN_DFT_OPT_INV, 0, 26) +REG32(BNK0_EN_PAD2PAD_LOOPBACK, 0x128) + FIELD(BNK0_EN_PAD2PAD_LOOPBACK, BNK0_EN_PAD2PAD_LOOPBACK, 0, 13) +REG32(BNK0_RX_SPARE0, 0x12c) +REG32(BNK0_RX_SPARE1, 0x130) + FIELD(BNK0_RX_SPARE1, BNK0_RX_SPARE, 0, 20) +REG32(BNK0_TX_SPARE0, 0x134) +REG32(BNK0_TX_SPARE1, 0x138) + FIELD(BNK0_TX_SPARE1, BNK0_TX_SPARE, 0, 20) +REG32(BNK0_SEL_EN1P8, 0x13c) + FIELD(BNK0_SEL_EN1P8, BNK0_SEL_EN1P8, 0, 1) +REG32(BNK0_EN_B_POR_DETECT, 0x140) + FIELD(BNK0_EN_B_POR_DETECT, BNK0_EN_B_POR_DETECT, 0, 1) +REG32(BNK0_LPF_BYP_POR_DETECT, 0x144) + FIELD(BNK0_LPF_BYP_POR_DETECT, BNK0_LPF_BYP_POR_DETECT, 0, 1) +REG32(BNK0_EN_LATCH, 0x148) + FIELD(BNK0_EN_LATCH, BNK0_EN_LATCH, 0, 1) +REG32(BNK0_VBG_LPF_BYP_B, 0x14c) + FIELD(BNK0_VBG_LPF_BYP_B, BNK0_VBG_LPF_BYP_B, 0, 1) +REG32(BNK0_EN_AMP_B, 0x150) + FIELD(BNK0_EN_AMP_B, BNK0_EN_AMP_B, 0, 2) +REG32(BNK0_SPARE_BIAS, 0x154) + FIELD(BNK0_SPARE_BIAS, BNK0_SPARE_BIAS, 0, 4) +REG32(BNK0_DRIVER_BIAS, 0x158) + FIELD(BNK0_DRIVER_BIAS, BNK0_DRIVER_BIAS, 0, 15) +REG32(BNK0_VMODE, 0x15c) + FIELD(BNK0_VMODE, BNK0_VMODE, 0, 1) +REG32(BNK0_SEL_AUX_IO_RX, 0x160) + FIELD(BNK0_SEL_AUX_IO_RX, BNK0_SEL_AUX_IO_RX, 0, 26) +REG32(BNK0_EN_TX_HS_MODE, 0x164) + FIELD(BNK0_EN_TX_HS_MODE, BNK0_EN_TX_HS_MODE, 0, 26) +REG32(MIO_MST_TRI0, 0x200) + FIELD(MIO_MST_TRI0, PIN_25_TRI, 25, 1) + FIELD(MIO_MST_TRI0, PIN_24_TRI, 24, 1) + FIELD(MIO_MST_TRI0, PIN_23_TRI, 23, 1) + FIELD(MIO_MST_TRI0, PIN_22_TRI, 22, 1) + FIELD(MIO_MST_TRI0, PIN_21_TRI, 21, 1) + FIELD(MIO_MST_TRI0, PIN_20_TRI, 20, 1) + FIELD(MIO_MST_TRI0, PIN_19_TRI, 19, 1) + FIELD(MIO_MST_TRI0, PIN_18_TRI, 18, 1) + FIELD(MIO_MST_TRI0, PIN_17_TRI, 17, 1) + FIELD(MIO_MST_TRI0, PIN_16_TRI, 16, 1) + FIELD(MIO_MST_TRI0, PIN_15_TRI, 15, 1) + FIELD(MIO_MST_TRI0, PIN_14_TRI, 14, 1) + FIELD(MIO_MST_TRI0, PIN_13_TRI, 13, 1) + FIELD(MIO_MST_TRI0, PIN_12_TRI, 12, 1) + FIELD(MIO_MST_TRI0, PIN_11_TRI, 11, 1) + FIELD(MIO_MST_TRI0, PIN_10_TRI, 10, 1) + FIELD(MIO_MST_TRI0, PIN_09_TRI, 9, 1) + FIELD(MIO_MST_TRI0, PIN_08_TRI, 8, 1) + FIELD(MIO_MST_TRI0, PIN_07_TRI, 7, 1) + FIELD(MIO_MST_TRI0, PIN_06_TRI, 6, 1) + FIELD(MIO_MST_TRI0, PIN_05_TRI, 5, 1) + FIELD(MIO_MST_TRI0, PIN_04_TRI, 4, 1) + FIELD(MIO_MST_TRI0, PIN_03_TRI, 3, 1) + FIELD(MIO_MST_TRI0, PIN_02_TRI, 2, 1) + FIELD(MIO_MST_TRI0, PIN_01_TRI, 1, 1) + FIELD(MIO_MST_TRI0, PIN_00_TRI, 0, 1) +REG32(MIO_MST_TRI1, 0x204) + FIELD(MIO_MST_TRI1, PIN_51_TRI, 25, 1) + FIELD(MIO_MST_TRI1, PIN_50_TRI, 24, 1) + FIELD(MIO_MST_TRI1, PIN_49_TRI, 23, 1) + FIELD(MIO_MST_TRI1, PIN_48_TRI, 22, 1) + FIELD(MIO_MST_TRI1, PIN_47_TRI, 21, 1) + FIELD(MIO_MST_TRI1, PIN_46_TRI, 20, 1) + FIELD(MIO_MST_TRI1, PIN_45_TRI, 19, 1) + FIELD(MIO_MST_TRI1, PIN_44_TRI, 18, 1) + FIELD(MIO_MST_TRI1, PIN_43_TRI, 17, 1) + FIELD(MIO_MST_TRI1, PIN_42_TRI, 16, 1) + FIELD(MIO_MST_TRI1, PIN_41_TRI, 15, 1) + FIELD(MIO_MST_TRI1, PIN_40_TRI, 14, 1) + FIELD(MIO_MST_TRI1, PIN_39_TRI, 13, 1) + FIELD(MIO_MST_TRI1, PIN_38_TRI, 12, 1) + FIELD(MIO_MST_TRI1, PIN_37_TRI, 11, 1) + FIELD(MIO_MST_TRI1, PIN_36_TRI, 10, 1) + FIELD(MIO_MST_TRI1, PIN_35_TRI, 9, 1) + FIELD(MIO_MST_TRI1, PIN_34_TRI, 8, 1) + FIELD(MIO_MST_TRI1, PIN_33_TRI, 7, 1) + FIELD(MIO_MST_TRI1, PIN_32_TRI, 6, 1) + FIELD(MIO_MST_TRI1, PIN_31_TRI, 5, 1) + FIELD(MIO_MST_TRI1, PIN_30_TRI, 4, 1) + FIELD(MIO_MST_TRI1, PIN_29_TRI, 3, 1) + FIELD(MIO_MST_TRI1, PIN_28_TRI, 2, 1) + FIELD(MIO_MST_TRI1, PIN_27_TRI, 1, 1) + FIELD(MIO_MST_TRI1, PIN_26_TRI, 0, 1) +REG32(BNK1_EN_RX, 0x300) + FIELD(BNK1_EN_RX, BNK1_EN_RX, 0, 26) +REG32(BNK1_SEL_RX0, 0x304) +REG32(BNK1_SEL_RX1, 0x308) + FIELD(BNK1_SEL_RX1, BNK1_SEL_RX, 0, 20) +REG32(BNK1_EN_RX_SCHMITT_HYST, 0x30c) + FIELD(BNK1_EN_RX_SCHMITT_HYST, BNK1_EN_RX_SCHMITT_HYST, 0, 26) +REG32(BNK1_EN_WK_PD, 0x310) + FIELD(BNK1_EN_WK_PD, BNK1_EN_WK_PD, 0, 26) +REG32(BNK1_EN_WK_PU, 0x314) + FIELD(BNK1_EN_WK_PU, BNK1_EN_WK_PU, 0, 26) +REG32(BNK1_SEL_DRV0, 0x318) +REG32(BNK1_SEL_DRV1, 0x31c) + FIELD(BNK1_SEL_DRV1, BNK1_SEL_DRV, 0, 20) +REG32(BNK1_SEL_SLEW, 0x320) + FIELD(BNK1_SEL_SLEW, BNK1_SEL_SLEW, 0, 26) +REG32(BNK1_EN_DFT_OPT_INV, 0x324) + FIELD(BNK1_EN_DFT_OPT_INV, BNK1_EN_DFT_OPT_INV, 0, 26) +REG32(BNK1_EN_PAD2PAD_LOOPBACK, 0x328) + FIELD(BNK1_EN_PAD2PAD_LOOPBACK, BNK1_EN_PAD2PAD_LOOPBACK, 0, 13) +REG32(BNK1_RX_SPARE0, 0x32c) +REG32(BNK1_RX_SPARE1, 0x330) + FIELD(BNK1_RX_SPARE1, BNK1_RX_SPARE, 0, 20) +REG32(BNK1_TX_SPARE0, 0x334) +REG32(BNK1_TX_SPARE1, 0x338) + FIELD(BNK1_TX_SPARE1, BNK1_TX_SPARE, 0, 20) +REG32(BNK1_SEL_EN1P8, 0x33c) + FIELD(BNK1_SEL_EN1P8, BNK1_SEL_EN1P8, 0, 1) +REG32(BNK1_EN_B_POR_DETECT, 0x340) + FIELD(BNK1_EN_B_POR_DETECT, BNK1_EN_B_POR_DETECT, 0, 1) +REG32(BNK1_LPF_BYP_POR_DETECT, 0x344) + FIELD(BNK1_LPF_BYP_POR_DETECT, BNK1_LPF_BYP_POR_DETECT, 0, 1) +REG32(BNK1_EN_LATCH, 0x348) + FIELD(BNK1_EN_LATCH, BNK1_EN_LATCH, 0, 1) +REG32(BNK1_VBG_LPF_BYP_B, 0x34c) + FIELD(BNK1_VBG_LPF_BYP_B, BNK1_VBG_LPF_BYP_B, 0, 1) +REG32(BNK1_EN_AMP_B, 0x350) + FIELD(BNK1_EN_AMP_B, BNK1_EN_AMP_B, 0, 2) +REG32(BNK1_SPARE_BIAS, 0x354) + FIELD(BNK1_SPARE_BIAS, BNK1_SPARE_BIAS, 0, 4) +REG32(BNK1_DRIVER_BIAS, 0x358) + FIELD(BNK1_DRIVER_BIAS, BNK1_DRIVER_BIAS, 0, 15) +REG32(BNK1_VMODE, 0x35c) + FIELD(BNK1_VMODE, BNK1_VMODE, 0, 1) +REG32(BNK1_SEL_AUX_IO_RX, 0x360) + FIELD(BNK1_SEL_AUX_IO_RX, BNK1_SEL_AUX_IO_RX, 0, 26) +REG32(BNK1_EN_TX_HS_MODE, 0x364) + FIELD(BNK1_EN_TX_HS_MODE, BNK1_EN_TX_HS_MODE, 0, 26) +REG32(SD0_CLK_CTRL, 0x400) + FIELD(SD0_CLK_CTRL, SDIO0_FBCLK_SEL, 2, 1) + FIELD(SD0_CLK_CTRL, SDIO0_RX_SRC_SEL, 0, 2) +REG32(SD0_CTRL_REG, 0x404) + FIELD(SD0_CTRL_REG, SD0_EMMC_SEL, 0, 1) +REG32(SD0_CONFIG_REG1, 0x410) + FIELD(SD0_CONFIG_REG1, SD0_BASECLK, 7, 8) + FIELD(SD0_CONFIG_REG1, SD0_TUNIGCOUNT, 1, 6) + FIELD(SD0_CONFIG_REG1, SD0_ASYNCWKPENA, 0, 1) +REG32(SD0_CONFIG_REG2, 0x414) + FIELD(SD0_CONFIG_REG2, SD0_SLOTTYPE, 12, 2) + FIELD(SD0_CONFIG_REG2, SD0_ASYCINTR, 11, 1) + FIELD(SD0_CONFIG_REG2, SD0_64BIT, 10, 1) + FIELD(SD0_CONFIG_REG2, SD0_1P8V, 9, 1) + FIELD(SD0_CONFIG_REG2, SD0_3P0V, 8, 1) + FIELD(SD0_CONFIG_REG2, SD0_3P3V, 7, 1) + FIELD(SD0_CONFIG_REG2, SD0_SUSPRES, 6, 1) + FIELD(SD0_CONFIG_REG2, SD0_SDMA, 5, 1) + FIELD(SD0_CONFIG_REG2, SD0_HIGHSPEED, 4, 1) + FIELD(SD0_CONFIG_REG2, SD0_ADMA2, 3, 1) + FIELD(SD0_CONFIG_REG2, SD0_8BIT, 2, 1) + FIELD(SD0_CONFIG_REG2, SD0_MAXBLK, 0, 2) +REG32(SD0_CONFIG_REG3, 0x418) + FIELD(SD0_CONFIG_REG3, SD0_TUNINGSDR50, 10, 1) + FIELD(SD0_CONFIG_REG3, SD0_RETUNETMR, 6, 4) + FIELD(SD0_CONFIG_REG3, SD0_DDRIVER, 5, 1) + FIELD(SD0_CONFIG_REG3, SD0_CDRIVER, 4, 1) + FIELD(SD0_CONFIG_REG3, SD0_ADRIVER, 3, 1) + FIELD(SD0_CONFIG_REG3, SD0_DDR50, 2, 1) + FIELD(SD0_CONFIG_REG3, SD0_SDR104, 1, 1) + FIELD(SD0_CONFIG_REG3, SD0_SDR50, 0, 1) +REG32(SD0_INITPRESET, 0x41c) + FIELD(SD0_INITPRESET, SD0_INITPRESET, 0, 13) +REG32(SD0_DSPPRESET, 0x420) + FIELD(SD0_DSPPRESET, SD0_DSPPRESET, 0, 13) +REG32(SD0_HSPDPRESET, 0x424) + FIELD(SD0_HSPDPRESET, SD0_HSPDPRESET, 0, 13) +REG32(SD0_SDR12PRESET, 0x428) + FIELD(SD0_SDR12PRESET, SD0_SDR12PRESET, 0, 13) +REG32(SD0_SDR25PRESET, 0x42c) + FIELD(SD0_SDR25PRESET, SD0_SDR25PRESET, 0, 13) +REG32(SD0_SDR50PRSET, 0x430) + FIELD(SD0_SDR50PRSET, SD0_SDR50PRESET, 0, 13) +REG32(SD0_SDR104PRST, 0x434) + FIELD(SD0_SDR104PRST, SD0_SDR104PRESET, 0, 13) +REG32(SD0_DDR50PRESET, 0x438) + FIELD(SD0_DDR50PRESET, SD0_DDR50PRESET, 0, 13) +REG32(SD0_MAXCUR1P8, 0x43c) + FIELD(SD0_MAXCUR1P8, SD0_MAXCUR1P8, 0, 8) +REG32(SD0_MAXCUR3P0, 0x440) + FIELD(SD0_MAXCUR3P0, SD0_MAXCUR3P0, 0, 8) +REG32(SD0_MAXCUR3P3, 0x444) + FIELD(SD0_MAXCUR3P3, SD0_MAXCUR3P3, 0, 8) +REG32(SD0_DLL_CTRL, 0x448) + FIELD(SD0_DLL_CTRL, SD0_CLKSTABLE_CFG, 9, 1) + FIELD(SD0_DLL_CTRL, SD0_DLL_CFG, 5, 4) + FIELD(SD0_DLL_CTRL, SD0_DLL_PSDONE, 4, 1) + FIELD(SD0_DLL_CTRL, SD0_DLL_OVF, 3, 1) + FIELD(SD0_DLL_CTRL, SD0_DLL_RST, 2, 1) + FIELD(SD0_DLL_CTRL, SD0_DLL_TESTMODE, 1, 1) + FIELD(SD0_DLL_CTRL, SD0_DLL_LOCK, 0, 1) +REG32(SD0_CDN_CTRL, 0x44c) + FIELD(SD0_CDN_CTRL, SD0_CDN_CTRL, 0, 1) +REG32(SD0_DLL_TEST, 0x450) + FIELD(SD0_DLL_TEST, DLL_DIV, 16, 8) + FIELD(SD0_DLL_TEST, DLL_TX_SEL, 9, 7) + FIELD(SD0_DLL_TEST, DLL_RX_SEL, 0, 9) +REG32(SD0_RX_TUNING_SEL, 0x454) + FIELD(SD0_RX_TUNING_SEL, SD0_RX_SEL, 0, 9) +REG32(SD0_DLL_DIV_MAP0, 0x458) + FIELD(SD0_DLL_DIV_MAP0, DIV_3, 24, 8) + FIELD(SD0_DLL_DIV_MAP0, DIV_2, 16, 8) + FIELD(SD0_DLL_DIV_MAP0, DIV_1, 8, 8) + FIELD(SD0_DLL_DIV_MAP0, DIV_0, 0, 8) +REG32(SD0_DLL_DIV_MAP1, 0x45c) + FIELD(SD0_DLL_DIV_MAP1, DIV_7, 24, 8) + FIELD(SD0_DLL_DIV_MAP1, DIV_6, 16, 8) + FIELD(SD0_DLL_DIV_MAP1, DIV_5, 8, 8) + FIELD(SD0_DLL_DIV_MAP1, DIV_4, 0, 8) +REG32(SD0_IOU_COHERENT_CTRL, 0x460) + FIELD(SD0_IOU_COHERENT_CTRL, SD0_AXI_COH, 0, 4) +REG32(SD0_IOU_INTERCONNECT_ROUTE, 0x464) + FIELD(SD0_IOU_INTERCONNECT_ROUTE, SD0, 0, 1) +REG32(SD0_IOU_RAM, 0x468) + FIELD(SD0_IOU_RAM, EMASA0, 6, 1) + FIELD(SD0_IOU_RAM, EMAB0, 3, 3) + FIELD(SD0_IOU_RAM, EMAA0, 0, 3) +REG32(SD0_IOU_INTERCONNECT_QOS, 0x46c) + FIELD(SD0_IOU_INTERCONNECT_QOS, SD0_QOS, 0, 4) +REG32(SD1_CLK_CTRL, 0x480) + FIELD(SD1_CLK_CTRL, SDIO1_FBCLK_SEL, 1, 1) + FIELD(SD1_CLK_CTRL, SDIO1_RX_SRC_SEL, 0, 1) +REG32(SD1_CTRL_REG, 0x484) + FIELD(SD1_CTRL_REG, SD1_EMMC_SEL, 0, 1) +REG32(SD1_CONFIG_REG1, 0x490) + FIELD(SD1_CONFIG_REG1, SD1_BASECLK, 7, 8) + FIELD(SD1_CONFIG_REG1, SD1_TUNIGCOUNT, 1, 6) + FIELD(SD1_CONFIG_REG1, SD1_ASYNCWKPENA, 0, 1) +REG32(SD1_CONFIG_REG2, 0x494) + FIELD(SD1_CONFIG_REG2, SD1_SLOTTYPE, 12, 2) + FIELD(SD1_CONFIG_REG2, SD1_ASYCINTR, 11, 1) + FIELD(SD1_CONFIG_REG2, SD1_64BIT, 10, 1) + FIELD(SD1_CONFIG_REG2, SD1_1P8V, 9, 1) + FIELD(SD1_CONFIG_REG2, SD1_3P0V, 8, 1) + FIELD(SD1_CONFIG_REG2, SD1_3P3V, 7, 1) + FIELD(SD1_CONFIG_REG2, SD1_SUSPRES, 6, 1) + FIELD(SD1_CONFIG_REG2, SD1_SDMA, 5, 1) + FIELD(SD1_CONFIG_REG2, SD1_HIGHSPEED, 4, 1) + FIELD(SD1_CONFIG_REG2, SD1_ADMA2, 3, 1) + FIELD(SD1_CONFIG_REG2, SD1_8BIT, 2, 1) + FIELD(SD1_CONFIG_REG2, SD1_MAXBLK, 0, 2) +REG32(SD1_CONFIG_REG3, 0x498) + FIELD(SD1_CONFIG_REG3, SD1_TUNINGSDR50, 10, 1) + FIELD(SD1_CONFIG_REG3, SD1_RETUNETMR, 6, 4) + FIELD(SD1_CONFIG_REG3, SD1_DDRIVER, 5, 1) + FIELD(SD1_CONFIG_REG3, SD1_CDRIVER, 4, 1) + FIELD(SD1_CONFIG_REG3, SD1_ADRIVER, 3, 1) + FIELD(SD1_CONFIG_REG3, SD1_DDR50, 2, 1) + FIELD(SD1_CONFIG_REG3, SD1_SDR104, 1, 1) + FIELD(SD1_CONFIG_REG3, SD1_SDR50, 0, 1) +REG32(SD1_INITPRESET, 0x49c) + FIELD(SD1_INITPRESET, SD1_INITPRESET, 0, 13) +REG32(SD1_DSPPRESET, 0x4a0) + FIELD(SD1_DSPPRESET, SD1_DSPPRESET, 0, 13) +REG32(SD1_HSPDPRESET, 0x4a4) + FIELD(SD1_HSPDPRESET, SD1_HSPDPRESET, 0, 13) +REG32(SD1_SDR12PRESET, 0x4a8) + FIELD(SD1_SDR12PRESET, SD1_SDR12PRESET, 0, 13) +REG32(SD1_SDR25PRESET, 0x4ac) + FIELD(SD1_SDR25PRESET, SD1_SDR25PRESET, 0, 13) +REG32(SD1_SDR50PRSET, 0x4b0) + FIELD(SD1_SDR50PRSET, SD1_SDR50PRESET, 0, 13) +REG32(SD1_SDR104PRST, 0x4b4) + FIELD(SD1_SDR104PRST, SD1_SDR104PRESET, 0, 13) +REG32(SD1_DDR50PRESET, 0x4b8) + FIELD(SD1_DDR50PRESET, SD1_DDR50PRESET, 0, 13) +REG32(SD1_MAXCUR1P8, 0x4bc) + FIELD(SD1_MAXCUR1P8, SD1_MAXCUR1P8, 0, 8) +REG32(SD1_MAXCUR3P0, 0x4c0) + FIELD(SD1_MAXCUR3P0, SD1_MAXCUR3P0, 0, 8) +REG32(SD1_MAXCUR3P3, 0x4c4) + FIELD(SD1_MAXCUR3P3, SD1_MAXCUR3P3, 0, 8) +REG32(SD1_DLL_CTRL, 0x4c8) + FIELD(SD1_DLL_CTRL, SD1_CLKSTABLE_CFG, 9, 1) + FIELD(SD1_DLL_CTRL, SD1_DLL_CFG, 5, 4) + FIELD(SD1_DLL_CTRL, SD1_DLL_PSDONE, 4, 1) + FIELD(SD1_DLL_CTRL, SD1_DLL_OVF, 3, 1) + FIELD(SD1_DLL_CTRL, SD1_DLL_RST, 2, 1) + FIELD(SD1_DLL_CTRL, SD1_DLL_TESTMODE, 1, 1) + FIELD(SD1_DLL_CTRL, SD1_DLL_LOCK, 0, 1) +REG32(SD1_CDN_CTRL, 0x4cc) + FIELD(SD1_CDN_CTRL, SD1_CDN_CTRL, 0, 1) +REG32(SD1_DLL_TEST, 0x4d0) + FIELD(SD1_DLL_TEST, DLL_DIV, 16, 8) + FIELD(SD1_DLL_TEST, DLL_TX_SEL, 9, 7) + FIELD(SD1_DLL_TEST, DLL_RX_SEL, 0, 9) +REG32(SD1_RX_TUNING_SEL, 0x4d4) + FIELD(SD1_RX_TUNING_SEL, SD1_RX_SEL, 0, 9) +REG32(SD1_DLL_DIV_MAP0, 0x4d8) + FIELD(SD1_DLL_DIV_MAP0, DIV_3, 24, 8) + FIELD(SD1_DLL_DIV_MAP0, DIV_2, 16, 8) + FIELD(SD1_DLL_DIV_MAP0, DIV_1, 8, 8) + FIELD(SD1_DLL_DIV_MAP0, DIV_0, 0, 8) +REG32(SD1_DLL_DIV_MAP1, 0x4dc) + FIELD(SD1_DLL_DIV_MAP1, DIV_7, 24, 8) + FIELD(SD1_DLL_DIV_MAP1, DIV_6, 16, 8) + FIELD(SD1_DLL_DIV_MAP1, DIV_5, 8, 8) + FIELD(SD1_DLL_DIV_MAP1, DIV_4, 0, 8) +REG32(SD1_IOU_COHERENT_CTRL, 0x4e0) + FIELD(SD1_IOU_COHERENT_CTRL, SD1_AXI_COH, 0, 4) +REG32(SD1_IOU_INTERCONNECT_ROUTE, 0x4e4) + FIELD(SD1_IOU_INTERCONNECT_ROUTE, SD1, 0, 1) +REG32(SD1_IOU_RAM, 0x4e8) + FIELD(SD1_IOU_RAM, EMASA0, 6, 1) + FIELD(SD1_IOU_RAM, EMAB0, 3, 3) + FIELD(SD1_IOU_RAM, EMAA0, 0, 3) +REG32(SD1_IOU_INTERCONNECT_QOS, 0x4ec) + FIELD(SD1_IOU_INTERCONNECT_QOS, SD1_QOS, 0, 4) +REG32(OSPI_QSPI_IOU_AXI_MUX_SEL, 0x504) + FIELD(OSPI_QSPI_IOU_AXI_MUX_SEL, OSPI_MUX_SEL, 1, 1) + FIELD(OSPI_QSPI_IOU_AXI_MUX_SEL, QSPI_OSPI_MUX_SEL, 0, 1) +REG32(QSPI_IOU_COHERENT_CTRL, 0x508) + FIELD(QSPI_IOU_COHERENT_CTRL, QSPI_AXI_COH, 0, 4) +REG32(QSPI_IOU_INTERCONNECT_ROUTE, 0x50c) + FIELD(QSPI_IOU_INTERCONNECT_ROUTE, QSPI, 0, 1) +REG32(QSPI_IOU_RAM, 0x510) + FIELD(QSPI_IOU_RAM, EMASA1, 13, 1) + FIELD(QSPI_IOU_RAM, EMAB1, 10, 3) + FIELD(QSPI_IOU_RAM, EMAA1, 7, 3) + FIELD(QSPI_IOU_RAM, EMASA0, 6, 1) + FIELD(QSPI_IOU_RAM, EMAB0, 3, 3) + FIELD(QSPI_IOU_RAM, EMAA0, 0, 3) +REG32(QSPI_IOU_INTERCONNECT_QOS, 0x514) + FIELD(QSPI_IOU_INTERCONNECT_QOS, QSPI_QOS, 0, 4) +REG32(OSPI_IOU_COHERENT_CTRL, 0x530) + FIELD(OSPI_IOU_COHERENT_CTRL, OSPI_AXI_COH, 0, 4) +REG32(OSPI_IOU_INTERCONNECT_ROUTE, 0x534) + FIELD(OSPI_IOU_INTERCONNECT_ROUTE, OSPI, 0, 1) +REG32(OSPI_IOU_RAM, 0x538) + FIELD(OSPI_IOU_RAM, EMAS0, 5, 1) + FIELD(OSPI_IOU_RAM, EMAW0, 3, 2) + FIELD(OSPI_IOU_RAM, EMA0, 0, 3) +REG32(OSPI_IOU_INTERCONNECT_QOS, 0x53c) + FIELD(OSPI_IOU_INTERCONNECT_QOS, OSPI_QOS, 0, 4) +REG32(OSPI_REFCLK_DLY_CTRL, 0x540) + FIELD(OSPI_REFCLK_DLY_CTRL, DLY1, 3, 2) + FIELD(OSPI_REFCLK_DLY_CTRL, DLY0, 0, 3) +REG32(CUR_PWR_ST, 0x600) + FIELD(CUR_PWR_ST, U2PMU, 0, 2) +REG32(CONNECT_ST, 0x604) + FIELD(CONNECT_ST, U2PMU, 0, 1) +REG32(PW_STATE_REQ, 0x608) + FIELD(PW_STATE_REQ, BIT_1_0, 0, 2) +REG32(HOST_U2_PORT_DISABLE, 0x60c) + FIELD(HOST_U2_PORT_DISABLE, BIT_0, 0, 1) +REG32(DBG_U2PMU, 0x610) +REG32(DBG_U2PMU_EXT1, 0x614) +REG32(DBG_U2PMU_EXT2, 0x618) + FIELD(DBG_U2PMU_EXT2, BIT_67_64, 0, 4) +REG32(PME_GEN_U2PMU, 0x61c) + FIELD(PME_GEN_U2PMU, BIT_0, 0, 1) +REG32(PWR_CONFIG_USB2, 0x620) + FIELD(PWR_CONFIG_USB2, STRAP, 0, 30) +REG32(PHY_HUB, 0x624) + FIELD(PHY_HUB, VBUS_CTRL, 1, 1) + FIELD(PHY_HUB, OVER_CURRENT, 0, 1) +REG32(CTRL, 0x700) + FIELD(CTRL, SLVERR_ENABLE, 0, 1) +REG32(ISR, 0x800) + FIELD(ISR, ADDR_DECODE_ERR, 0, 1) +REG32(IMR, 0x804) + FIELD(IMR, ADDR_DECODE_ERR, 0, 1) +REG32(IER, 0x808) + FIELD(IER, ADDR_DECODE_ERR, 0, 1) +REG32(IDR, 0x80c) + FIELD(IDR, ADDR_DECODE_ERR, 0, 1) +REG32(ITR, 0x810) + FIELD(ITR, ADDR_DECODE_ERR, 0, 1) +REG32(PARITY_ISR, 0x814) + FIELD(PARITY_ISR, PERR_AXI_SD1_IOU, 12, 1) + FIELD(PARITY_ISR, PERR_AXI_SD0_IOU, 11, 1) + FIELD(PARITY_ISR, PERR_AXI_QSPI_IOU, 10, 1) + FIELD(PARITY_ISR, PERR_AXI_OSPI_IOU, 9, 1) + FIELD(PARITY_ISR, PERR_IOU_SD1, 8, 1) + FIELD(PARITY_ISR, PERR_IOU_SD0, 7, 1) + FIELD(PARITY_ISR, PERR_IOU_QSPI1, 6, 1) + FIELD(PARITY_ISR, PERR_IOUSLCR_SECURE_APB, 5, 1) + FIELD(PARITY_ISR, PERR_IOUSLCR_APB, 4, 1) + FIELD(PARITY_ISR, PERR_QSPI0_APB, 3, 1) + FIELD(PARITY_ISR, PERR_OSPI_APB, 2, 1) + FIELD(PARITY_ISR, PERR_I2C_APB, 1, 1) + FIELD(PARITY_ISR, PERR_GPIO_APB, 0, 1) +REG32(PARITY_IMR, 0x818) + FIELD(PARITY_IMR, PERR_AXI_SD1_IOU, 12, 1) + FIELD(PARITY_IMR, PERR_AXI_SD0_IOU, 11, 1) + FIELD(PARITY_IMR, PERR_AXI_QSPI_IOU, 10, 1) + FIELD(PARITY_IMR, PERR_AXI_OSPI_IOU, 9, 1) + FIELD(PARITY_IMR, PERR_IOU_SD1, 8, 1) + FIELD(PARITY_IMR, PERR_IOU_SD0, 7, 1) + FIELD(PARITY_IMR, PERR_IOU_QSPI1, 6, 1) + FIELD(PARITY_IMR, PERR_IOUSLCR_SECURE_APB, 5, 1) + FIELD(PARITY_IMR, PERR_IOUSLCR_APB, 4, 1) + FIELD(PARITY_IMR, PERR_QSPI0_APB, 3, 1) + FIELD(PARITY_IMR, PERR_OSPI_APB, 2, 1) + FIELD(PARITY_IMR, PERR_I2C_APB, 1, 1) + FIELD(PARITY_IMR, PERR_GPIO_APB, 0, 1) +REG32(PARITY_IER, 0x81c) + FIELD(PARITY_IER, PERR_AXI_SD1_IOU, 12, 1) + FIELD(PARITY_IER, PERR_AXI_SD0_IOU, 11, 1) + FIELD(PARITY_IER, PERR_AXI_QSPI_IOU, 10, 1) + FIELD(PARITY_IER, PERR_AXI_OSPI_IOU, 9, 1) + FIELD(PARITY_IER, PERR_IOU_SD1, 8, 1) + FIELD(PARITY_IER, PERR_IOU_SD0, 7, 1) + FIELD(PARITY_IER, PERR_IOU_QSPI1, 6, 1) + FIELD(PARITY_IER, PERR_IOUSLCR_SECURE_APB, 5, 1) + FIELD(PARITY_IER, PERR_IOUSLCR_APB, 4, 1) + FIELD(PARITY_IER, PERR_QSPI0_APB, 3, 1) + FIELD(PARITY_IER, PERR_OSPI_APB, 2, 1) + FIELD(PARITY_IER, PERR_I2C_APB, 1, 1) + FIELD(PARITY_IER, PERR_GPIO_APB, 0, 1) +REG32(PARITY_IDR, 0x820) + FIELD(PARITY_IDR, PERR_AXI_SD1_IOU, 12, 1) + FIELD(PARITY_IDR, PERR_AXI_SD0_IOU, 11, 1) + FIELD(PARITY_IDR, PERR_AXI_QSPI_IOU, 10, 1) + FIELD(PARITY_IDR, PERR_AXI_OSPI_IOU, 9, 1) + FIELD(PARITY_IDR, PERR_IOU_SD1, 8, 1) + FIELD(PARITY_IDR, PERR_IOU_SD0, 7, 1) + FIELD(PARITY_IDR, PERR_IOU_QSPI1, 6, 1) + FIELD(PARITY_IDR, PERR_IOUSLCR_SECURE_APB, 5, 1) + FIELD(PARITY_IDR, PERR_IOUSLCR_APB, 4, 1) + FIELD(PARITY_IDR, PERR_QSPI0_APB, 3, 1) + FIELD(PARITY_IDR, PERR_OSPI_APB, 2, 1) + FIELD(PARITY_IDR, PERR_I2C_APB, 1, 1) + FIELD(PARITY_IDR, PERR_GPIO_APB, 0, 1) +REG32(PARITY_ITR, 0x824) + FIELD(PARITY_ITR, PERR_AXI_SD1_IOU, 12, 1) + FIELD(PARITY_ITR, PERR_AXI_SD0_IOU, 11, 1) + FIELD(PARITY_ITR, PERR_AXI_QSPI_IOU, 10, 1) + FIELD(PARITY_ITR, PERR_AXI_OSPI_IOU, 9, 1) + FIELD(PARITY_ITR, PERR_IOU_SD1, 8, 1) + FIELD(PARITY_ITR, PERR_IOU_SD0, 7, 1) + FIELD(PARITY_ITR, PERR_IOU_QSPI1, 6, 1) + FIELD(PARITY_ITR, PERR_IOUSLCR_SECURE_APB, 5, 1) + FIELD(PARITY_ITR, PERR_IOUSLCR_APB, 4, 1) + FIELD(PARITY_ITR, PERR_QSPI0_APB, 3, 1) + FIELD(PARITY_ITR, PERR_OSPI_APB, 2, 1) + FIELD(PARITY_ITR, PERR_I2C_APB, 1, 1) + FIELD(PARITY_ITR, PERR_GPIO_APB, 0, 1) +REG32(WPROT0, 0x828) + FIELD(WPROT0, ACTIVE, 0, 1) + +static void parity_imr_update_irq(XlnxVersalPmcIouSlcr *s) +{ + bool pending = s->regs[R_PARITY_ISR] & ~s->regs[R_PARITY_IMR]; + qemu_set_irq(s->irq_parity_imr, pending); +} + +static void parity_isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + parity_imr_update_irq(s); +} + +static uint64_t parity_ier_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val = val64; + + s->regs[R_PARITY_IMR] &= ~val; + parity_imr_update_irq(s); + return 0; +} + +static uint64_t parity_idr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val = val64; + + s->regs[R_PARITY_IMR] |= val; + parity_imr_update_irq(s); + return 0; +} + +static uint64_t parity_itr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val = val64; + + s->regs[R_PARITY_ISR] |= val; + parity_imr_update_irq(s); + return 0; +} + +static void imr_update_irq(XlnxVersalPmcIouSlcr *s) +{ + bool pending = s->regs[R_ISR] & ~s->regs[R_IMR]; + qemu_set_irq(s->irq_imr, pending); +} + +static void isr_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + imr_update_irq(s); +} + +static uint64_t ier_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val = val64; + + s->regs[R_IMR] &= ~val; + imr_update_irq(s); + return 0; +} + +static uint64_t idr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val = val64; + + s->regs[R_IMR] |= val; + imr_update_irq(s); + return 0; +} + +static uint64_t itr_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val = val64; + + s->regs[R_ISR] |= val; + imr_update_irq(s); + return 0; +} + +static uint64_t sd0_ctrl_reg_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t prev = ARRAY_FIELD_EX32(s->regs, SD0_CTRL_REG, SD0_EMMC_SEL); + + if (prev != (val64 & R_SD0_CTRL_REG_SD0_EMMC_SEL_MASK)) { + qemu_set_irq(s->sd_emmc_sel[0], !!val64); + } + + return val64; +} + +static uint64_t sd1_ctrl_reg_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t prev = ARRAY_FIELD_EX32(s->regs, SD1_CTRL_REG, SD1_EMMC_SEL); + + if (prev != (val64 & R_SD1_CTRL_REG_SD1_EMMC_SEL_MASK)) { + qemu_set_irq(s->sd_emmc_sel[1], !!val64); + } + + return val64; +} + +static uint64_t ospi_qspi_iou_axi_mux_sel_prew(RegisterInfo *reg, + uint64_t val64) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(reg->opaque); + uint32_t val32 = (uint32_t) val64; + uint8_t ospi_mux_sel = FIELD_EX32(val32, OSPI_QSPI_IOU_AXI_MUX_SEL, + OSPI_MUX_SEL); + uint8_t qspi_ospi_mux_sel = FIELD_EX32(val32, OSPI_QSPI_IOU_AXI_MUX_SEL, + QSPI_OSPI_MUX_SEL); + + if (ospi_mux_sel != + ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL, OSPI_MUX_SEL)) { + qemu_set_irq(s->ospi_mux_sel, !!ospi_mux_sel); + } + + if (qspi_ospi_mux_sel != + ARRAY_FIELD_EX32(s->regs, OSPI_QSPI_IOU_AXI_MUX_SEL, + QSPI_OSPI_MUX_SEL)) { + qemu_set_irq(s->qspi_ospi_mux_sel, !!qspi_ospi_mux_sel); + } + + return val64; +} + +static RegisterAccessInfo pmc_iou_slcr_regs_info[] = { + { .name = "MIO_PIN_0", .addr = A_MIO_PIN_0, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_1", .addr = A_MIO_PIN_1, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_2", .addr = A_MIO_PIN_2, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_3", .addr = A_MIO_PIN_3, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_4", .addr = A_MIO_PIN_4, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_5", .addr = A_MIO_PIN_5, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_6", .addr = A_MIO_PIN_6, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_7", .addr = A_MIO_PIN_7, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_8", .addr = A_MIO_PIN_8, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_9", .addr = A_MIO_PIN_9, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_10", .addr = A_MIO_PIN_10, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_11", .addr = A_MIO_PIN_11, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_12", .addr = A_MIO_PIN_12, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_13", .addr = A_MIO_PIN_13, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_14", .addr = A_MIO_PIN_14, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_15", .addr = A_MIO_PIN_15, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_16", .addr = A_MIO_PIN_16, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_17", .addr = A_MIO_PIN_17, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_18", .addr = A_MIO_PIN_18, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_19", .addr = A_MIO_PIN_19, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_20", .addr = A_MIO_PIN_20, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_21", .addr = A_MIO_PIN_21, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_22", .addr = A_MIO_PIN_22, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_23", .addr = A_MIO_PIN_23, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_24", .addr = A_MIO_PIN_24, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_25", .addr = A_MIO_PIN_25, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_26", .addr = A_MIO_PIN_26, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_27", .addr = A_MIO_PIN_27, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_28", .addr = A_MIO_PIN_28, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_29", .addr = A_MIO_PIN_29, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_30", .addr = A_MIO_PIN_30, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_31", .addr = A_MIO_PIN_31, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_32", .addr = A_MIO_PIN_32, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_33", .addr = A_MIO_PIN_33, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_34", .addr = A_MIO_PIN_34, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_35", .addr = A_MIO_PIN_35, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_36", .addr = A_MIO_PIN_36, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_37", .addr = A_MIO_PIN_37, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_38", .addr = A_MIO_PIN_38, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_39", .addr = A_MIO_PIN_39, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_40", .addr = A_MIO_PIN_40, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_41", .addr = A_MIO_PIN_41, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_42", .addr = A_MIO_PIN_42, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_43", .addr = A_MIO_PIN_43, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_44", .addr = A_MIO_PIN_44, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_45", .addr = A_MIO_PIN_45, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_46", .addr = A_MIO_PIN_46, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_47", .addr = A_MIO_PIN_47, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_48", .addr = A_MIO_PIN_48, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_49", .addr = A_MIO_PIN_49, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_50", .addr = A_MIO_PIN_50, + .rsvd = 0xfffffc01, + },{ .name = "MIO_PIN_51", .addr = A_MIO_PIN_51, + .rsvd = 0xfffffc01, + },{ .name = "BNK0_EN_RX", .addr = A_BNK0_EN_RX, + .reset = 0x3ffffff, + .rsvd = 0xfc000000, + },{ .name = "BNK0_SEL_RX0", .addr = A_BNK0_SEL_RX0, + .reset = 0xffffffff, + },{ .name = "BNK0_SEL_RX1", .addr = A_BNK0_SEL_RX1, + .reset = 0xfffff, + .rsvd = 0xfff00000, + },{ .name = "BNK0_EN_RX_SCHMITT_HYST", .addr = A_BNK0_EN_RX_SCHMITT_HYST, + .rsvd = 0xfc000000, + },{ .name = "BNK0_EN_WK_PD", .addr = A_BNK0_EN_WK_PD, + .rsvd = 0xfc000000, + },{ .name = "BNK0_EN_WK_PU", .addr = A_BNK0_EN_WK_PU, + .reset = 0x3ffffff, + .rsvd = 0xfc000000, + },{ .name = "BNK0_SEL_DRV0", .addr = A_BNK0_SEL_DRV0, + .reset = 0xffffffff, + },{ .name = "BNK0_SEL_DRV1", .addr = A_BNK0_SEL_DRV1, + .reset = 0xfffff, + .rsvd = 0xfff00000, + },{ .name = "BNK0_SEL_SLEW", .addr = A_BNK0_SEL_SLEW, + .rsvd = 0xfc000000, + },{ .name = "BNK0_EN_DFT_OPT_INV", .addr = A_BNK0_EN_DFT_OPT_INV, + .rsvd = 0xfc000000, + },{ .name = "BNK0_EN_PAD2PAD_LOOPBACK", + .addr = A_BNK0_EN_PAD2PAD_LOOPBACK, + .rsvd = 0xffffe000, + },{ .name = "BNK0_RX_SPARE0", .addr = A_BNK0_RX_SPARE0, + },{ .name = "BNK0_RX_SPARE1", .addr = A_BNK0_RX_SPARE1, + .rsvd = 0xfff00000, + },{ .name = "BNK0_TX_SPARE0", .addr = A_BNK0_TX_SPARE0, + },{ .name = "BNK0_TX_SPARE1", .addr = A_BNK0_TX_SPARE1, + .rsvd = 0xfff00000, + },{ .name = "BNK0_SEL_EN1P8", .addr = A_BNK0_SEL_EN1P8, + .rsvd = 0xfffffffe, + },{ .name = "BNK0_EN_B_POR_DETECT", .addr = A_BNK0_EN_B_POR_DETECT, + .rsvd = 0xfffffffe, + },{ .name = "BNK0_LPF_BYP_POR_DETECT", .addr = A_BNK0_LPF_BYP_POR_DETECT, + .reset = 0x1, + .rsvd = 0xfffffffe, + },{ .name = "BNK0_EN_LATCH", .addr = A_BNK0_EN_LATCH, + .rsvd = 0xfffffffe, + },{ .name = "BNK0_VBG_LPF_BYP_B", .addr = A_BNK0_VBG_LPF_BYP_B, + .reset = 0x1, + .rsvd = 0xfffffffe, + },{ .name = "BNK0_EN_AMP_B", .addr = A_BNK0_EN_AMP_B, + .rsvd = 0xfffffffc, + },{ .name = "BNK0_SPARE_BIAS", .addr = A_BNK0_SPARE_BIAS, + .rsvd = 0xfffffff0, + },{ .name = "BNK0_DRIVER_BIAS", .addr = A_BNK0_DRIVER_BIAS, + .rsvd = 0xffff8000, + },{ .name = "BNK0_VMODE", .addr = A_BNK0_VMODE, + .rsvd = 0xfffffffe, + .ro = 0x1, + },{ .name = "BNK0_SEL_AUX_IO_RX", .addr = A_BNK0_SEL_AUX_IO_RX, + .rsvd = 0xfc000000, + },{ .name = "BNK0_EN_TX_HS_MODE", .addr = A_BNK0_EN_TX_HS_MODE, + .rsvd = 0xfc000000, + },{ .name = "MIO_MST_TRI0", .addr = A_MIO_MST_TRI0, + .reset = 0x3ffffff, + .rsvd = 0xfc000000, + },{ .name = "MIO_MST_TRI1", .addr = A_MIO_MST_TRI1, + .reset = 0x3ffffff, + .rsvd = 0xfc000000, + },{ .name = "BNK1_EN_RX", .addr = A_BNK1_EN_RX, + .reset = 0x3ffffff, + .rsvd = 0xfc000000, + },{ .name = "BNK1_SEL_RX0", .addr = A_BNK1_SEL_RX0, + .reset = 0xffffffff, + },{ .name = "BNK1_SEL_RX1", .addr = A_BNK1_SEL_RX1, + .reset = 0xfffff, + .rsvd = 0xfff00000, + },{ .name = "BNK1_EN_RX_SCHMITT_HYST", .addr = A_BNK1_EN_RX_SCHMITT_HYST, + .rsvd = 0xfc000000, + },{ .name = "BNK1_EN_WK_PD", .addr = A_BNK1_EN_WK_PD, + .rsvd = 0xfc000000, + },{ .name = "BNK1_EN_WK_PU", .addr = A_BNK1_EN_WK_PU, + .reset = 0x3ffffff, + .rsvd = 0xfc000000, + },{ .name = "BNK1_SEL_DRV0", .addr = A_BNK1_SEL_DRV0, + .reset = 0xffffffff, + },{ .name = "BNK1_SEL_DRV1", .addr = A_BNK1_SEL_DRV1, + .reset = 0xfffff, + .rsvd = 0xfff00000, + },{ .name = "BNK1_SEL_SLEW", .addr = A_BNK1_SEL_SLEW, + .rsvd = 0xfc000000, + },{ .name = "BNK1_EN_DFT_OPT_INV", .addr = A_BNK1_EN_DFT_OPT_INV, + .rsvd = 0xfc000000, + },{ .name = "BNK1_EN_PAD2PAD_LOOPBACK", + .addr = A_BNK1_EN_PAD2PAD_LOOPBACK, + .rsvd = 0xffffe000, + },{ .name = "BNK1_RX_SPARE0", .addr = A_BNK1_RX_SPARE0, + },{ .name = "BNK1_RX_SPARE1", .addr = A_BNK1_RX_SPARE1, + .rsvd = 0xfff00000, + },{ .name = "BNK1_TX_SPARE0", .addr = A_BNK1_TX_SPARE0, + },{ .name = "BNK1_TX_SPARE1", .addr = A_BNK1_TX_SPARE1, + .rsvd = 0xfff00000, + },{ .name = "BNK1_SEL_EN1P8", .addr = A_BNK1_SEL_EN1P8, + .rsvd = 0xfffffffe, + },{ .name = "BNK1_EN_B_POR_DETECT", .addr = A_BNK1_EN_B_POR_DETECT, + .rsvd = 0xfffffffe, + },{ .name = "BNK1_LPF_BYP_POR_DETECT", .addr = A_BNK1_LPF_BYP_POR_DETECT, + .reset = 0x1, + .rsvd = 0xfffffffe, + },{ .name = "BNK1_EN_LATCH", .addr = A_BNK1_EN_LATCH, + .rsvd = 0xfffffffe, + },{ .name = "BNK1_VBG_LPF_BYP_B", .addr = A_BNK1_VBG_LPF_BYP_B, + .reset = 0x1, + .rsvd = 0xfffffffe, + },{ .name = "BNK1_EN_AMP_B", .addr = A_BNK1_EN_AMP_B, + .rsvd = 0xfffffffc, + },{ .name = "BNK1_SPARE_BIAS", .addr = A_BNK1_SPARE_BIAS, + .rsvd = 0xfffffff0, + },{ .name = "BNK1_DRIVER_BIAS", .addr = A_BNK1_DRIVER_BIAS, + .rsvd = 0xffff8000, + },{ .name = "BNK1_VMODE", .addr = A_BNK1_VMODE, + .rsvd = 0xfffffffe, + .ro = 0x1, + },{ .name = "BNK1_SEL_AUX_IO_RX", .addr = A_BNK1_SEL_AUX_IO_RX, + .rsvd = 0xfc000000, + },{ .name = "BNK1_EN_TX_HS_MODE", .addr = A_BNK1_EN_TX_HS_MODE, + .rsvd = 0xfc000000, + },{ .name = "SD0_CLK_CTRL", .addr = A_SD0_CLK_CTRL, + .rsvd = 0xfffffff8, + },{ .name = "SD0_CTRL_REG", .addr = A_SD0_CTRL_REG, + .rsvd = 0xfffffffe, + .pre_write = sd0_ctrl_reg_prew, + },{ .name = "SD0_CONFIG_REG1", .addr = A_SD0_CONFIG_REG1, + .reset = 0x3250, + .rsvd = 0xffff8000, + },{ .name = "SD0_CONFIG_REG2", .addr = A_SD0_CONFIG_REG2, + .reset = 0xffc, + .rsvd = 0xffffc000, + },{ .name = "SD0_CONFIG_REG3", .addr = A_SD0_CONFIG_REG3, + .reset = 0x407, + .rsvd = 0xfffff800, + },{ .name = "SD0_INITPRESET", .addr = A_SD0_INITPRESET, + .reset = 0x100, + .rsvd = 0xffffe000, + },{ .name = "SD0_DSPPRESET", .addr = A_SD0_DSPPRESET, + .reset = 0x4, + .rsvd = 0xffffe000, + },{ .name = "SD0_HSPDPRESET", .addr = A_SD0_HSPDPRESET, + .reset = 0x2, + .rsvd = 0xffffe000, + },{ .name = "SD0_SDR12PRESET", .addr = A_SD0_SDR12PRESET, + .reset = 0x4, + .rsvd = 0xffffe000, + },{ .name = "SD0_SDR25PRESET", .addr = A_SD0_SDR25PRESET, + .reset = 0x2, + .rsvd = 0xffffe000, + },{ .name = "SD0_SDR50PRSET", .addr = A_SD0_SDR50PRSET, + .reset = 0x1, + .rsvd = 0xffffe000, + },{ .name = "SD0_SDR104PRST", .addr = A_SD0_SDR104PRST, + .rsvd = 0xffffe000, + },{ .name = "SD0_DDR50PRESET", .addr = A_SD0_DDR50PRESET, + .reset = 0x2, + .rsvd = 0xffffe000, + },{ .name = "SD0_MAXCUR1P8", .addr = A_SD0_MAXCUR1P8, + .rsvd = 0xffffff00, + },{ .name = "SD0_MAXCUR3P0", .addr = A_SD0_MAXCUR3P0, + .rsvd = 0xffffff00, + },{ .name = "SD0_MAXCUR3P3", .addr = A_SD0_MAXCUR3P3, + .rsvd = 0xffffff00, + },{ .name = "SD0_DLL_CTRL", .addr = A_SD0_DLL_CTRL, + .reset = 0x1, + .rsvd = 0xfffffc00, + .ro = 0x19, + },{ .name = "SD0_CDN_CTRL", .addr = A_SD0_CDN_CTRL, + .rsvd = 0xfffffffe, + },{ .name = "SD0_DLL_TEST", .addr = A_SD0_DLL_TEST, + .rsvd = 0xff000000, + },{ .name = "SD0_RX_TUNING_SEL", .addr = A_SD0_RX_TUNING_SEL, + .rsvd = 0xfffffe00, + .ro = 0x1ff, + },{ .name = "SD0_DLL_DIV_MAP0", .addr = A_SD0_DLL_DIV_MAP0, + .reset = 0x50505050, + },{ .name = "SD0_DLL_DIV_MAP1", .addr = A_SD0_DLL_DIV_MAP1, + .reset = 0x50505050, + },{ .name = "SD0_IOU_COHERENT_CTRL", .addr = A_SD0_IOU_COHERENT_CTRL, + .rsvd = 0xfffffff0, + },{ .name = "SD0_IOU_INTERCONNECT_ROUTE", + .addr = A_SD0_IOU_INTERCONNECT_ROUTE, + .rsvd = 0xfffffffe, + },{ .name = "SD0_IOU_RAM", .addr = A_SD0_IOU_RAM, + .reset = 0x24, + .rsvd = 0xffffff80, + },{ .name = "SD0_IOU_INTERCONNECT_QOS", + .addr = A_SD0_IOU_INTERCONNECT_QOS, + .rsvd = 0xfffffff0, + },{ .name = "SD1_CLK_CTRL", .addr = A_SD1_CLK_CTRL, + .rsvd = 0xfffffffc, + },{ .name = "SD1_CTRL_REG", .addr = A_SD1_CTRL_REG, + .rsvd = 0xfffffffe, + .pre_write = sd1_ctrl_reg_prew, + },{ .name = "SD1_CONFIG_REG1", .addr = A_SD1_CONFIG_REG1, + .reset = 0x3250, + .rsvd = 0xffff8000, + },{ .name = "SD1_CONFIG_REG2", .addr = A_SD1_CONFIG_REG2, + .reset = 0xffc, + .rsvd = 0xffffc000, + },{ .name = "SD1_CONFIG_REG3", .addr = A_SD1_CONFIG_REG3, + .reset = 0x407, + .rsvd = 0xfffff800, + },{ .name = "SD1_INITPRESET", .addr = A_SD1_INITPRESET, + .reset = 0x100, + .rsvd = 0xffffe000, + },{ .name = "SD1_DSPPRESET", .addr = A_SD1_DSPPRESET, + .reset = 0x4, + .rsvd = 0xffffe000, + },{ .name = "SD1_HSPDPRESET", .addr = A_SD1_HSPDPRESET, + .reset = 0x2, + .rsvd = 0xffffe000, + },{ .name = "SD1_SDR12PRESET", .addr = A_SD1_SDR12PRESET, + .reset = 0x4, + .rsvd = 0xffffe000, + },{ .name = "SD1_SDR25PRESET", .addr = A_SD1_SDR25PRESET, + .reset = 0x2, + .rsvd = 0xffffe000, + },{ .name = "SD1_SDR50PRSET", .addr = A_SD1_SDR50PRSET, + .reset = 0x1, + .rsvd = 0xffffe000, + },{ .name = "SD1_SDR104PRST", .addr = A_SD1_SDR104PRST, + .rsvd = 0xffffe000, + },{ .name = "SD1_DDR50PRESET", .addr = A_SD1_DDR50PRESET, + .reset = 0x2, + .rsvd = 0xffffe000, + },{ .name = "SD1_MAXCUR1P8", .addr = A_SD1_MAXCUR1P8, + .rsvd = 0xffffff00, + },{ .name = "SD1_MAXCUR3P0", .addr = A_SD1_MAXCUR3P0, + .rsvd = 0xffffff00, + },{ .name = "SD1_MAXCUR3P3", .addr = A_SD1_MAXCUR3P3, + .rsvd = 0xffffff00, + },{ .name = "SD1_DLL_CTRL", .addr = A_SD1_DLL_CTRL, + .reset = 0x1, + .rsvd = 0xfffffc00, + .ro = 0x19, + },{ .name = "SD1_CDN_CTRL", .addr = A_SD1_CDN_CTRL, + .rsvd = 0xfffffffe, + },{ .name = "SD1_DLL_TEST", .addr = A_SD1_DLL_TEST, + .rsvd = 0xff000000, + },{ .name = "SD1_RX_TUNING_SEL", .addr = A_SD1_RX_TUNING_SEL, + .rsvd = 0xfffffe00, + .ro = 0x1ff, + },{ .name = "SD1_DLL_DIV_MAP0", .addr = A_SD1_DLL_DIV_MAP0, + .reset = 0x50505050, + },{ .name = "SD1_DLL_DIV_MAP1", .addr = A_SD1_DLL_DIV_MAP1, + .reset = 0x50505050, + },{ .name = "SD1_IOU_COHERENT_CTRL", .addr = A_SD1_IOU_COHERENT_CTRL, + .rsvd = 0xfffffff0, + },{ .name = "SD1_IOU_INTERCONNECT_ROUTE", + .addr = A_SD1_IOU_INTERCONNECT_ROUTE, + .rsvd = 0xfffffffe, + },{ .name = "SD1_IOU_RAM", .addr = A_SD1_IOU_RAM, + .reset = 0x24, + .rsvd = 0xffffff80, + },{ .name = "SD1_IOU_INTERCONNECT_QOS", + .addr = A_SD1_IOU_INTERCONNECT_QOS, + .rsvd = 0xfffffff0, + },{ .name = "OSPI_QSPI_IOU_AXI_MUX_SEL", + .addr = A_OSPI_QSPI_IOU_AXI_MUX_SEL, + .reset = 0x1, + .rsvd = 0xfffffffc, + .pre_write = ospi_qspi_iou_axi_mux_sel_prew, + },{ .name = "QSPI_IOU_COHERENT_CTRL", .addr = A_QSPI_IOU_COHERENT_CTRL, + .rsvd = 0xfffffff0, + },{ .name = "QSPI_IOU_INTERCONNECT_ROUTE", + .addr = A_QSPI_IOU_INTERCONNECT_ROUTE, + .rsvd = 0xfffffffe, + },{ .name = "QSPI_IOU_RAM", .addr = A_QSPI_IOU_RAM, + .reset = 0x1224, + .rsvd = 0xffffc000, + },{ .name = "QSPI_IOU_INTERCONNECT_QOS", + .addr = A_QSPI_IOU_INTERCONNECT_QOS, + .rsvd = 0xfffffff0, + },{ .name = "OSPI_IOU_COHERENT_CTRL", .addr = A_OSPI_IOU_COHERENT_CTRL, + .rsvd = 0xfffffff0, + },{ .name = "OSPI_IOU_INTERCONNECT_ROUTE", + .addr = A_OSPI_IOU_INTERCONNECT_ROUTE, + .rsvd = 0xfffffffe, + },{ .name = "OSPI_IOU_RAM", .addr = A_OSPI_IOU_RAM, + .reset = 0xa, + .rsvd = 0xffffffc0, + },{ .name = "OSPI_IOU_INTERCONNECT_QOS", + .addr = A_OSPI_IOU_INTERCONNECT_QOS, + .rsvd = 0xfffffff0, + },{ .name = "OSPI_REFCLK_DLY_CTRL", .addr = A_OSPI_REFCLK_DLY_CTRL, + .reset = 0x13, + .rsvd = 0xffffffe0, + },{ .name = "CUR_PWR_ST", .addr = A_CUR_PWR_ST, + .rsvd = 0xfffffffc, + .ro = 0x3, + },{ .name = "CONNECT_ST", .addr = A_CONNECT_ST, + .rsvd = 0xfffffffe, + .ro = 0x1, + },{ .name = "PW_STATE_REQ", .addr = A_PW_STATE_REQ, + .rsvd = 0xfffffffc, + },{ .name = "HOST_U2_PORT_DISABLE", .addr = A_HOST_U2_PORT_DISABLE, + .rsvd = 0xfffffffe, + },{ .name = "DBG_U2PMU", .addr = A_DBG_U2PMU, + .ro = 0xffffffff, + },{ .name = "DBG_U2PMU_EXT1", .addr = A_DBG_U2PMU_EXT1, + .ro = 0xffffffff, + },{ .name = "DBG_U2PMU_EXT2", .addr = A_DBG_U2PMU_EXT2, + .rsvd = 0xfffffff0, + .ro = 0xf, + },{ .name = "PME_GEN_U2PMU", .addr = A_PME_GEN_U2PMU, + .rsvd = 0xfffffffe, + .ro = 0x1, + },{ .name = "PWR_CONFIG_USB2", .addr = A_PWR_CONFIG_USB2, + .rsvd = 0xc0000000, + },{ .name = "PHY_HUB", .addr = A_PHY_HUB, + .rsvd = 0xfffffffc, + .ro = 0x2, + },{ .name = "CTRL", .addr = A_CTRL, + },{ .name = "ISR", .addr = A_ISR, + .w1c = 0x1, + .post_write = isr_postw, + },{ .name = "IMR", .addr = A_IMR, + .reset = 0x1, + .ro = 0x1, + },{ .name = "IER", .addr = A_IER, + .pre_write = ier_prew, + },{ .name = "IDR", .addr = A_IDR, + .pre_write = idr_prew, + },{ .name = "ITR", .addr = A_ITR, + .pre_write = itr_prew, + },{ .name = "PARITY_ISR", .addr = A_PARITY_ISR, + .w1c = 0x1fff, + .post_write = parity_isr_postw, + },{ .name = "PARITY_IMR", .addr = A_PARITY_IMR, + .reset = 0x1fff, + .ro = 0x1fff, + },{ .name = "PARITY_IER", .addr = A_PARITY_IER, + .pre_write = parity_ier_prew, + },{ .name = "PARITY_IDR", .addr = A_PARITY_IDR, + .pre_write = parity_idr_prew, + },{ .name = "PARITY_ITR", .addr = A_PARITY_ITR, + .pre_write = parity_itr_prew, + },{ .name = "WPROT0", .addr = A_WPROT0, + .reset = 0x1, + } +}; + +static void xlnx_versal_pmc_iou_slcr_reset_init(Object *obj, ResetType type) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } +} + +static void xlnx_versal_pmc_iou_slcr_reset_hold(Object *obj) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj); + + parity_imr_update_irq(s); + imr_update_irq(s); + + /* + * Setup OSPI_QSPI mux + * By default axi slave interface is enabled for ospi-dma + */ + qemu_set_irq(s->ospi_mux_sel, 0); + qemu_set_irq(s->qspi_ospi_mux_sel, 1); +} + +static const MemoryRegionOps pmc_iou_slcr_ops = { + .read = register_read_memory, + .write = register_write_memory, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void xlnx_versal_pmc_iou_slcr_realize(DeviceState *dev, Error **errp) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(dev); + + qdev_init_gpio_out_named(dev, s->sd_emmc_sel, "sd-emmc-sel", 2); + qdev_init_gpio_out_named(dev, &s->qspi_ospi_mux_sel, + "qspi-ospi-mux-sel", 1); + qdev_init_gpio_out_named(dev, &s->ospi_mux_sel, "ospi-mux-sel", 1); +} + +static void xlnx_versal_pmc_iou_slcr_init(Object *obj) +{ + XlnxVersalPmcIouSlcr *s = XILINX_VERSAL_PMC_IOU_SLCR(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_PMC_IOU_SLCR, + XILINX_VERSAL_PMC_IOU_SLCR_R_MAX * 4); + reg_array = + register_init_block32(DEVICE(obj), pmc_iou_slcr_regs_info, + ARRAY_SIZE(pmc_iou_slcr_regs_info), + s->regs_info, s->regs, + &pmc_iou_slcr_ops, + XILINX_VERSAL_PMC_IOU_SLCR_ERR_DEBUG, + XILINX_VERSAL_PMC_IOU_SLCR_R_MAX * 4); + memory_region_add_subregion(&s->iomem, + 0x0, + &reg_array->mem); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq_parity_imr); + sysbus_init_irq(sbd, &s->irq_imr); +} + +static const VMStateDescription vmstate_pmc_iou_slcr = { + .name = TYPE_XILINX_VERSAL_PMC_IOU_SLCR, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxVersalPmcIouSlcr, + XILINX_VERSAL_PMC_IOU_SLCR_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void xlnx_versal_pmc_iou_slcr_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + dc->realize = xlnx_versal_pmc_iou_slcr_realize; + dc->vmsd = &vmstate_pmc_iou_slcr; + rc->phases.enter = xlnx_versal_pmc_iou_slcr_reset_init; + rc->phases.hold = xlnx_versal_pmc_iou_slcr_reset_hold; +} + +static const TypeInfo xlnx_versal_pmc_iou_slcr_info = { + .name = TYPE_XILINX_VERSAL_PMC_IOU_SLCR, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxVersalPmcIouSlcr), + .class_init = xlnx_versal_pmc_iou_slcr_class_init, + .instance_init = xlnx_versal_pmc_iou_slcr_init, +}; + +static void xlnx_versal_pmc_iou_slcr_register_types(void) +{ + type_register_static(&xlnx_versal_pmc_iou_slcr_info); +} + +type_init(xlnx_versal_pmc_iou_slcr_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index XXXXXXX..XXXXXXX 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( )) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) -softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-xramc.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( + 'xlnx-versal-xramc.c', + 'xlnx-versal-pmc-iou-slcr.c', +)) softmmu_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_syscfg.c')) softmmu_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_syscfg.c')) softmmu_ss.add(when: 'CONFIG_STM32F4XX_EXTI', if_true: files('stm32f4xx_exti.c')) -- 2.25.1 From: Francisco Iglesias <francisco.iglesias@xilinx.com> Add an orgate and 'or' the interrupts from the BBRAM and RTC models. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-3-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/xlnx-versal.h | 5 +++-- hw/arm/xlnx-versal-virt.c | 2 +- hw/arm/xlnx-versal.c | 28 ++++++++++++++++++++++++++-- 3 files changed, 30 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -XXX,XX +XXX,XX @@ struct Versal { XlnxEFuse efuse; XlnxVersalEFuseCtrl efuse_ctrl; XlnxVersalEFuseCache efuse_cache; + + qemu_or_irq apb_irq_orgate; } pmc; struct { @@ -XXX,XX +XXX,XX @@ struct Versal { #define VERSAL_GEM1_WAKE_IRQ_0 59 #define VERSAL_ADMA_IRQ_0 60 #define VERSAL_XRAM_IRQ_0 79 -#define VERSAL_BBRAM_APB_IRQ_0 121 -#define VERSAL_RTC_APB_ERR_IRQ 121 +#define VERSAL_PMC_APB_IRQ 121 #define VERSAL_SD0_IRQ_0 126 #define VERSAL_EFUSE_IRQ 139 #define VERSAL_RTC_ALARM_IRQ 142 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -XXX,XX +XXX,XX @@ static void fdt_add_bbram_node(VersalVirt *s) qemu_fdt_add_subnode(s->fdt, name); qemu_fdt_setprop_cells(s->fdt, name, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, VERSAL_BBRAM_APB_IRQ_0, + GIC_FDT_IRQ_TYPE_SPI, VERSAL_PMC_APB_IRQ, GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop(s->fdt, name, "interrupt-names", interrupt_names, sizeof(interrupt_names)); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -XXX,XX +XXX,XX @@ #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define GEM_REVISION 0x40070106 +#define VERSAL_NUM_PMC_APB_IRQS 2 + static void versal_create_apu_cpus(Versal *s) { int i; @@ -XXX,XX +XXX,XX @@ static void versal_create_sds(Versal *s, qemu_irq *pic) } } +static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic) +{ + DeviceState *orgate; + + /* + * The VERSAL_PMC_APB_IRQ is an 'or' of the interrupts from the following + * models: + * - RTC + * - BBRAM + */ + object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate", + &s->pmc.apb_irq_orgate, TYPE_OR_IRQ); + orgate = DEVICE(&s->pmc.apb_irq_orgate); + object_property_set_int(OBJECT(orgate), + "num-lines", VERSAL_NUM_PMC_APB_IRQS, &error_fatal); + qdev_realize(orgate, NULL, &error_fatal); + qdev_connect_gpio_out(orgate, 0, pic[VERSAL_PMC_APB_IRQ]); +} + static void versal_create_rtc(Versal *s, qemu_irq *pic) { SysBusDevice *sbd; @@ -XXX,XX +XXX,XX @@ static void versal_create_rtc(Versal *s, qemu_irq *pic) * TODO: Connect the ALARM and SECONDS interrupts once our RTC model * supports them. */ - sysbus_connect_irq(sbd, 1, pic[VERSAL_RTC_APB_ERR_IRQ]); + sysbus_connect_irq(sbd, 1, + qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 0)); } static void versal_create_xrams(Versal *s, qemu_irq *pic) @@ -XXX,XX +XXX,XX @@ static void versal_create_bbram(Versal *s, qemu_irq *pic) sysbus_realize(sbd, &error_fatal); memory_region_add_subregion(&s->mr_ps, MM_PMC_BBRAM_CTRL, sysbus_mmio_get_region(sbd, 0)); - sysbus_connect_irq(sbd, 0, pic[VERSAL_BBRAM_APB_IRQ_0]); + sysbus_connect_irq(sbd, 0, + qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 1)); } static void versal_realize_efuse_part(Versal *s, Object *dev, hwaddr base) @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_gems(s, pic); versal_create_admas(s, pic); versal_create_sds(s, pic); + versal_create_pmc_apb_irq_orgate(s, pic); versal_create_rtc(s, pic); versal_create_xrams(s, pic); versal_create_bbram(s, pic); -- 2.25.1 From: Francisco Iglesias <francisco.iglesias@xilinx.com> Connect Versal's PMC SLCR (system-level control registers) model. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-4-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/xlnx-versal.h | 5 +++ hw/arm/xlnx-versal.c | 71 +++++++++++++++++++++++++++++++++++- 2 files changed, 75 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -XXX,XX +XXX,XX @@ #include "hw/misc/xlnx-versal-xramc.h" #include "hw/nvram/xlnx-bbram.h" #include "hw/nvram/xlnx-versal-efuse.h" +#include "hw/misc/xlnx-versal-pmc-iou-slcr.h" #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) @@ -XXX,XX +XXX,XX @@ struct Versal { struct { struct { SDHCIState sd[XLNX_VERSAL_NR_SDS]; + XlnxVersalPmcIouSlcr slcr; } iou; XlnxZynqMPRTC rtc; @@ -XXX,XX +XXX,XX @@ struct Versal { #define MM_FPD_FPD_APU 0xfd5c0000 #define MM_FPD_FPD_APU_SIZE 0x100 +#define MM_PMC_PMC_IOU_SLCR 0xf1060000 +#define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 + #define MM_PMC_SD0 0xf1040000U #define MM_PMC_SD0_SIZE 0x10000 #define MM_PMC_BBRAM_CTRL 0xf11f0000 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -XXX,XX +XXX,XX @@ #include "kvm_arm.h" #include "hw/misc/unimp.h" #include "hw/arm/xlnx-versal.h" +#include "qemu/log.h" +#include "hw/sysbus.h" #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define GEM_REVISION 0x40070106 -#define VERSAL_NUM_PMC_APB_IRQS 2 +#define VERSAL_NUM_PMC_APB_IRQS 3 static void versal_create_apu_cpus(Versal *s) { @@ -XXX,XX +XXX,XX @@ static void versal_create_pmc_apb_irq_orgate(Versal *s, qemu_irq *pic) * models: * - RTC * - BBRAM + * - PMC SLCR */ object_initialize_child(OBJECT(s), "pmc-apb-irq-orgate", &s->pmc.apb_irq_orgate, TYPE_OR_IRQ); @@ -XXX,XX +XXX,XX @@ static void versal_create_efuse(Versal *s, qemu_irq *pic) sysbus_connect_irq(SYS_BUS_DEVICE(ctrl), 0, pic[VERSAL_EFUSE_IRQ]); } +static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic) +{ + SysBusDevice *sbd; + + object_initialize_child(OBJECT(s), "versal-pmc-iou-slcr", &s->pmc.iou.slcr, + TYPE_XILINX_VERSAL_PMC_IOU_SLCR); + + sbd = SYS_BUS_DEVICE(&s->pmc.iou.slcr); + sysbus_realize(sbd, &error_fatal); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_PMC_IOU_SLCR, + sysbus_mmio_get_region(sbd, 0)); + + sysbus_connect_irq(sbd, 0, + qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2)); +} + /* This takes the board allocated linear DDR memory and creates aliases * for each split DDR range/aperture on the Versal address map. */ @@ -XXX,XX +XXX,XX @@ static void versal_unimp_area(Versal *s, const char *name, memory_region_add_subregion(mr, base, mr_dev); } +static void versal_unimp_sd_emmc_sel(void *opaque, int n, int level) +{ + qemu_log_mask(LOG_UNIMP, + "Selecting between enabling SD mode or eMMC mode on " + "controller %d is not yet implemented\n", n); +} + +static void versal_unimp_qspi_ospi_mux_sel(void *opaque, int n, int level) +{ + qemu_log_mask(LOG_UNIMP, + "Selecting between enabling the QSPI or OSPI linear address " + "region is not yet implemented\n"); +} + +static void versal_unimp_irq_parity_imr(void *opaque, int n, int level) +{ + qemu_log_mask(LOG_UNIMP, + "PMC SLCR parity interrupt behaviour " + "is not yet implemented\n"); +} + static void versal_unimp(Versal *s) { + qemu_irq gpio_in; + versal_unimp_area(s, "psm", &s->mr_ps, MM_PSM_START, MM_PSM_END - MM_PSM_START); versal_unimp_area(s, "crl", &s->mr_ps, @@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s) MM_IOU_SCNTR, MM_IOU_SCNTR_SIZE); versal_unimp_area(s, "iou-scntr-seucre", &s->mr_ps, MM_IOU_SCNTRS, MM_IOU_SCNTRS_SIZE); + + qdev_init_gpio_in_named(DEVICE(s), versal_unimp_sd_emmc_sel, + "sd-emmc-sel-dummy", 2); + qdev_init_gpio_in_named(DEVICE(s), versal_unimp_qspi_ospi_mux_sel, + "qspi-ospi-mux-sel-dummy", 1); + qdev_init_gpio_in_named(DEVICE(s), versal_unimp_irq_parity_imr, + "irq-parity-imr-dummy", 1); + + gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 0); + qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 0, + gpio_in); + + gpio_in = qdev_get_gpio_in_named(DEVICE(s), "sd-emmc-sel-dummy", 1); + qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "sd-emmc-sel", 1, + gpio_in); + + gpio_in = qdev_get_gpio_in_named(DEVICE(s), "qspi-ospi-mux-sel-dummy", 0); + qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), + "qspi-ospi-mux-sel", 0, + gpio_in); + + gpio_in = qdev_get_gpio_in_named(DEVICE(s), "irq-parity-imr-dummy", 0); + qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), + SYSBUS_DEVICE_GPIO_IRQ, 0, + gpio_in); } static void versal_realize(DeviceState *dev, Error **errp) @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_xrams(s, pic); versal_create_bbram(s, pic); versal_create_efuse(s, pic); + versal_create_pmc_iou_slcr(s, pic); versal_map_ddr(s); versal_unimp(s); -- 2.25.1 From: Francisco Iglesias <francisco.iglesias@xilinx.com> Add in the missing includes in the header for being able to build the DMA model when reusing it. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-5-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/dma/xlnx_csu_dma.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma/xlnx_csu_dma.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/dma/xlnx_csu_dma.h +++ b/include/hw/dma/xlnx_csu_dma.h @@ -XXX,XX +XXX,XX @@ #ifndef XLNX_CSU_DMA_H #define XLNX_CSU_DMA_H +#include "hw/sysbus.h" +#include "hw/register.h" +#include "hw/ptimer.h" +#include "hw/stream.h" + #define TYPE_XLNX_CSU_DMA "xlnx.csu_dma" #define XLNX_CSU_DMA_R_MAX (0x2c / 4) -- 2.25.1 From: Francisco Iglesias <francisco.iglesias@xilinx.com> An option on real hardware when embedding a DMA engine into a peripheral is to make the peripheral control the engine through a custom DMA control (hardware) interface between the two. Software drivers in this scenario configure and trigger DMA operations through the controlling peripheral's register API (for example, writing a specific bit in a register could propagate down to a transfer start signal on the DMA control interface). At the same time the status, results and interrupts for the transfer might still be intended to be read and caught through the DMA engine's register API (and signals). This patch adds a class 'read' method for allowing to start read transfers from peripherals embedding and controlling the Xilinx CSU DMA engine as in above scenario. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-6-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/dma/xlnx_csu_dma.h | 19 +++++++++++++++++-- hw/dma/xlnx_csu_dma.c | 17 +++++++++++++++++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma/xlnx_csu_dma.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/dma/xlnx_csu_dma.h +++ b/include/hw/dma/xlnx_csu_dma.h @@ -XXX,XX +XXX,XX @@ typedef struct XlnxCSUDMA { RegisterInfo regs_info[XLNX_CSU_DMA_R_MAX]; } XlnxCSUDMA; -#define XLNX_CSU_DMA(obj) \ - OBJECT_CHECK(XlnxCSUDMA, (obj), TYPE_XLNX_CSU_DMA) +OBJECT_DECLARE_TYPE(XlnxCSUDMA, XlnxCSUDMAClass, XLNX_CSU_DMA) + +struct XlnxCSUDMAClass { + SysBusDeviceClass parent_class; + + /* + * read: Start a read transfer on a Xilinx CSU DMA engine + * + * @s: the Xilinx CSU DMA engine to start the transfer on + * @addr: the address to read + * @len: the number of bytes to read at 'addr' + * + * @return a MemTxResult indicating whether the operation succeeded ('len' + * bytes were read) or failed. + */ + MemTxResult (*read)(XlnxCSUDMA *s, hwaddr addr, uint32_t len); +}; #endif diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index XXXXXXX..XXXXXXX 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -XXX,XX +XXX,XX @@ static uint64_t addr_msb_pre_write(RegisterInfo *reg, uint64_t val) return val & R_ADDR_MSB_ADDR_MSB_MASK; } +static MemTxResult xlnx_csu_dma_class_read(XlnxCSUDMA *s, hwaddr addr, + uint32_t len) +{ + RegisterInfo *reg = &s->regs_info[R_SIZE]; + uint64_t we = MAKE_64BIT_MASK(0, 4 * 8); + + s->regs[R_ADDR] = addr; + s->regs[R_ADDR_MSB] = (uint64_t)addr >> 32; + + register_write(reg, len, we, object_get_typename(OBJECT(s)), false); + + return (s->regs[R_SIZE] == 0) ? MEMTX_OK : MEMTX_ERROR; +} + static const RegisterAccessInfo *xlnx_csu_dma_regs_info[] = { #define DMACH_REGINFO(NAME, snd) \ (const RegisterAccessInfo []) { \ @@ -XXX,XX +XXX,XX @@ static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); + XlnxCSUDMAClass *xcdc = XLNX_CSU_DMA_CLASS(klass); dc->reset = xlnx_csu_dma_reset; dc->realize = xlnx_csu_dma_realize; @@ -XXX,XX +XXX,XX @@ static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data) ssc->push = xlnx_csu_dma_stream_push; ssc->can_push = xlnx_csu_dma_stream_can_push; + + xcdc->read = xlnx_csu_dma_class_read; } static void xlnx_csu_dma_init(Object *obj) -- 2.25.1 From: Francisco Iglesias <francisco.iglesias@xilinx.com> Add a model of Xilinx Versal's OSPI flash memory controller. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220121161141.14389-7-francisco.iglesias@xilinx.com [PMM: fixed indent] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/ssi/xlnx-versal-ospi.h | 111 ++ hw/ssi/xlnx-versal-ospi.c | 1853 +++++++++++++++++++++++++++++ hw/ssi/meson.build | 1 + 3 files changed, 1965 insertions(+) create mode 100644 include/hw/ssi/xlnx-versal-ospi.h create mode 100644 hw/ssi/xlnx-versal-ospi.c diff --git a/include/hw/ssi/xlnx-versal-ospi.h b/include/hw/ssi/xlnx-versal-ospi.h new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/include/hw/ssi/xlnx-versal-ospi.h @@ -XXX,XX +XXX,XX @@ +/* + * Header file for the Xilinx Versal's OSPI controller + * + * Copyright (C) 2021 Xilinx Inc + * Written by Francisco Iglesias <francisco.iglesias@xilinx.com> + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* + * This is a model of Xilinx Versal's Octal SPI flash memory controller + * documented in Versal's Technical Reference manual [1] and the Versal ACAP + * Register reference [2]. + * + * References: + * + * [1] Versal ACAP Technical Reference Manual, + * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf + * + * [2] Versal ACAP Register Reference, + * https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___ospi.html + * + * + * QEMU interface: + * + sysbus MMIO region 0: MemoryRegion for the device's registers + * + sysbus MMIO region 1: MemoryRegion for flash memory linear address space + * (data transfer). + * + sysbus IRQ 0: Device interrupt. + * + Named GPIO input "ospi-mux-sel": 0: enables indirect access mode + * and 1: enables direct access mode. + * + Property "dac-with-indac": Allow both direct accesses and indirect + * accesses simultaneously. + * + Property "indac-write-disabled": Disable indirect access writes. + */ + +#ifndef XILINX_VERSAL_OSPI_H +#define XILINX_VERSAL_OSPI_H + +#include "hw/register.h" +#include "hw/ssi/ssi.h" +#include "qemu/fifo8.h" +#include "hw/dma/xlnx_csu_dma.h" + +#define TYPE_XILINX_VERSAL_OSPI "xlnx.versal-ospi" + +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalOspi, XILINX_VERSAL_OSPI) + +#define XILINX_VERSAL_OSPI_R_MAX (0xfc / 4 + 1) + +/* + * Indirect operations + */ +typedef struct IndOp { + uint32_t flash_addr; + uint32_t num_bytes; + uint32_t done_bytes; + bool completed; +} IndOp; + +struct XlnxVersalOspi { + SysBusDevice parent_obj; + + MemoryRegion iomem; + MemoryRegion iomem_dac; + + uint8_t num_cs; + qemu_irq *cs_lines; + + SSIBus *spi; + + Fifo8 rx_fifo; + Fifo8 tx_fifo; + + Fifo8 rx_sram; + Fifo8 tx_sram; + + qemu_irq irq; + + XlnxCSUDMA *dma_src; + bool ind_write_disabled; + bool dac_with_indac; + bool dac_enable; + bool src_dma_inprog; + + IndOp rd_ind_op[2]; + IndOp wr_ind_op[2]; + + uint32_t regs[XILINX_VERSAL_OSPI_R_MAX]; + RegisterInfo regs_info[XILINX_VERSAL_OSPI_R_MAX]; + + /* Maximum inferred membank size is 512 bytes */ + uint8_t stig_membank[512]; +}; + +#endif /* XILINX_VERSAL_OSPI_H */ diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/hw/ssi/xlnx-versal-ospi.c @@ -XXX,XX +XXX,XX @@ +/* + * QEMU model of Xilinx Versal's OSPI controller. + * + * Copyright (c) 2021 Xilinx Inc. + * Written by Francisco Iglesias <francisco.iglesias@xilinx.com> + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "hw/irq.h" +#include "hw/ssi/xlnx-versal-ospi.h" + +#ifndef XILINX_VERSAL_OSPI_ERR_DEBUG +#define XILINX_VERSAL_OSPI_ERR_DEBUG 0 +#endif + +REG32(CONFIG_REG, 0x0) + FIELD(CONFIG_REG, IDLE_FLD, 31, 1) + FIELD(CONFIG_REG, DUAL_BYTE_OPCODE_EN_FLD, 30, 1) + FIELD(CONFIG_REG, CRC_ENABLE_FLD, 29, 1) + FIELD(CONFIG_REG, CONFIG_RESV2_FLD, 26, 3) + FIELD(CONFIG_REG, PIPELINE_PHY_FLD, 25, 1) + FIELD(CONFIG_REG, ENABLE_DTR_PROTOCOL_FLD, 24, 1) + FIELD(CONFIG_REG, ENABLE_AHB_DECODER_FLD, 23, 1) + FIELD(CONFIG_REG, MSTR_BAUD_DIV_FLD, 19, 4) + FIELD(CONFIG_REG, ENTER_XIP_MODE_IMM_FLD, 18, 1) + FIELD(CONFIG_REG, ENTER_XIP_MODE_FLD, 17, 1) + FIELD(CONFIG_REG, ENB_AHB_ADDR_REMAP_FLD, 16, 1) + FIELD(CONFIG_REG, ENB_DMA_IF_FLD, 15, 1) + FIELD(CONFIG_REG, WR_PROT_FLASH_FLD, 14, 1) + FIELD(CONFIG_REG, PERIPH_CS_LINES_FLD, 10, 4) + FIELD(CONFIG_REG, PERIPH_SEL_DEC_FLD, 9, 1) + FIELD(CONFIG_REG, ENB_LEGACY_IP_MODE_FLD, 8, 1) + FIELD(CONFIG_REG, ENB_DIR_ACC_CTLR_FLD, 7, 1) + FIELD(CONFIG_REG, RESET_CFG_FLD, 6, 1) + FIELD(CONFIG_REG, RESET_PIN_FLD, 5, 1) + FIELD(CONFIG_REG, HOLD_PIN_FLD, 4, 1) + FIELD(CONFIG_REG, PHY_MODE_ENABLE_FLD, 3, 1) + FIELD(CONFIG_REG, SEL_CLK_PHASE_FLD, 2, 1) + FIELD(CONFIG_REG, SEL_CLK_POL_FLD, 1, 1) + FIELD(CONFIG_REG, ENB_SPI_FLD, 0, 1) +REG32(DEV_INSTR_RD_CONFIG_REG, 0x4) + FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV5_FLD, 29, 3) + FIELD(DEV_INSTR_RD_CONFIG_REG, DUMMY_RD_CLK_CYCLES_FLD, 24, 5) + FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV4_FLD, 21, 3) + FIELD(DEV_INSTR_RD_CONFIG_REG, MODE_BIT_ENABLE_FLD, 20, 1) + FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV3_FLD, 18, 2) + FIELD(DEV_INSTR_RD_CONFIG_REG, DATA_XFER_TYPE_EXT_MODE_FLD, 16, 2) + FIELD(DEV_INSTR_RD_CONFIG_REG, RD_INSTR_RESV2_FLD, 14, 2) + FIELD(DEV_INSTR_RD_CONFIG_REG, ADDR_XFER_TYPE_STD_MODE_FLD, 12, 2) + FIELD(DEV_INSTR_RD_CONFIG_REG, PRED_DIS_FLD, 11, 1) + FIELD(DEV_INSTR_RD_CONFIG_REG, DDR_EN_FLD, 10, 1) + FIELD(DEV_INSTR_RD_CONFIG_REG, INSTR_TYPE_FLD, 8, 2) + FIELD(DEV_INSTR_RD_CONFIG_REG, RD_OPCODE_NON_XIP_FLD, 0, 8) +REG32(DEV_INSTR_WR_CONFIG_REG, 0x8) + FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV4_FLD, 29, 3) + FIELD(DEV_INSTR_WR_CONFIG_REG, DUMMY_WR_CLK_CYCLES_FLD, 24, 5) + FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV3_FLD, 18, 6) + FIELD(DEV_INSTR_WR_CONFIG_REG, DATA_XFER_TYPE_EXT_MODE_FLD, 16, 2) + FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV2_FLD, 14, 2) + FIELD(DEV_INSTR_WR_CONFIG_REG, ADDR_XFER_TYPE_STD_MODE_FLD, 12, 2) + FIELD(DEV_INSTR_WR_CONFIG_REG, WR_INSTR_RESV1_FLD, 9, 3) + FIELD(DEV_INSTR_WR_CONFIG_REG, WEL_DIS_FLD, 8, 1) + FIELD(DEV_INSTR_WR_CONFIG_REG, WR_OPCODE_FLD, 0, 8) +REG32(DEV_DELAY_REG, 0xc) + FIELD(DEV_DELAY_REG, D_NSS_FLD, 24, 8) + FIELD(DEV_DELAY_REG, D_BTWN_FLD, 16, 8) + FIELD(DEV_DELAY_REG, D_AFTER_FLD, 8, 8) + FIELD(DEV_DELAY_REG, D_INIT_FLD, 0, 8) +REG32(RD_DATA_CAPTURE_REG, 0x10) + FIELD(RD_DATA_CAPTURE_REG, RD_DATA_RESV3_FLD, 20, 12) + FIELD(RD_DATA_CAPTURE_REG, DDR_READ_DELAY_FLD, 16, 4) + FIELD(RD_DATA_CAPTURE_REG, RD_DATA_RESV2_FLD, 9, 7) + FIELD(RD_DATA_CAPTURE_REG, DQS_ENABLE_FLD, 8, 1) + FIELD(RD_DATA_CAPTURE_REG, RD_DATA_RESV1_FLD, 6, 2) + FIELD(RD_DATA_CAPTURE_REG, SAMPLE_EDGE_SEL_FLD, 5, 1) + FIELD(RD_DATA_CAPTURE_REG, DELAY_FLD, 1, 4) + FIELD(RD_DATA_CAPTURE_REG, BYPASS_FLD, 0, 1) +REG32(DEV_SIZE_CONFIG_REG, 0x14) + FIELD(DEV_SIZE_CONFIG_REG, DEV_SIZE_RESV_FLD, 29, 3) + FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS3_FLD, 27, 2) + FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS2_FLD, 25, 2) + FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS1_FLD, 23, 2) + FIELD(DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS0_FLD, 21, 2) + FIELD(DEV_SIZE_CONFIG_REG, BYTES_PER_SUBSECTOR_FLD, 16, 5) + FIELD(DEV_SIZE_CONFIG_REG, BYTES_PER_DEVICE_PAGE_FLD, 4, 12) + FIELD(DEV_SIZE_CONFIG_REG, NUM_ADDR_BYTES_FLD, 0, 4) +REG32(SRAM_PARTITION_CFG_REG, 0x18) + FIELD(SRAM_PARTITION_CFG_REG, SRAM_PARTITION_RESV_FLD, 8, 24) + FIELD(SRAM_PARTITION_CFG_REG, ADDR_FLD, 0, 8) +REG32(IND_AHB_ADDR_TRIGGER_REG, 0x1c) +REG32(DMA_PERIPH_CONFIG_REG, 0x20) + FIELD(DMA_PERIPH_CONFIG_REG, DMA_PERIPH_RESV2_FLD, 12, 20) + FIELD(DMA_PERIPH_CONFIG_REG, NUM_BURST_REQ_BYTES_FLD, 8, 4) + FIELD(DMA_PERIPH_CONFIG_REG, DMA_PERIPH_RESV1_FLD, 4, 4) + FIELD(DMA_PERIPH_CONFIG_REG, NUM_SINGLE_REQ_BYTES_FLD, 0, 4) +REG32(REMAP_ADDR_REG, 0x24) +REG32(MODE_BIT_CONFIG_REG, 0x28) + FIELD(MODE_BIT_CONFIG_REG, RX_CRC_DATA_LOW_FLD, 24, 8) + FIELD(MODE_BIT_CONFIG_REG, RX_CRC_DATA_UP_FLD, 16, 8) + FIELD(MODE_BIT_CONFIG_REG, CRC_OUT_ENABLE_FLD, 15, 1) + FIELD(MODE_BIT_CONFIG_REG, MODE_BIT_RESV1_FLD, 11, 4) + FIELD(MODE_BIT_CONFIG_REG, CHUNK_SIZE_FLD, 8, 3) + FIELD(MODE_BIT_CONFIG_REG, MODE_FLD, 0, 8) +REG32(SRAM_FILL_REG, 0x2c) + FIELD(SRAM_FILL_REG, SRAM_FILL_INDAC_WRITE_FLD, 16, 16) + FIELD(SRAM_FILL_REG, SRAM_FILL_INDAC_READ_FLD, 0, 16) +REG32(TX_THRESH_REG, 0x30) + FIELD(TX_THRESH_REG, TX_THRESH_RESV_FLD, 5, 27) + FIELD(TX_THRESH_REG, LEVEL_FLD, 0, 5) +REG32(RX_THRESH_REG, 0x34) + FIELD(RX_THRESH_REG, RX_THRESH_RESV_FLD, 5, 27) + FIELD(RX_THRESH_REG, LEVEL_FLD, 0, 5) +REG32(WRITE_COMPLETION_CTRL_REG, 0x38) + FIELD(WRITE_COMPLETION_CTRL_REG, POLL_REP_DELAY_FLD, 24, 8) + FIELD(WRITE_COMPLETION_CTRL_REG, POLL_COUNT_FLD, 16, 8) + FIELD(WRITE_COMPLETION_CTRL_REG, ENABLE_POLLING_EXP_FLD, 15, 1) + FIELD(WRITE_COMPLETION_CTRL_REG, DISABLE_POLLING_FLD, 14, 1) + FIELD(WRITE_COMPLETION_CTRL_REG, POLLING_POLARITY_FLD, 13, 1) + FIELD(WRITE_COMPLETION_CTRL_REG, WR_COMP_CTRL_RESV1_FLD, 12, 1) + FIELD(WRITE_COMPLETION_CTRL_REG, POLLING_ADDR_EN_FLD, 11, 1) + FIELD(WRITE_COMPLETION_CTRL_REG, POLLING_BIT_INDEX_FLD, 8, 3) + FIELD(WRITE_COMPLETION_CTRL_REG, OPCODE_FLD, 0, 8) +REG32(NO_OF_POLLS_BEF_EXP_REG, 0x3c) +REG32(IRQ_STATUS_REG, 0x40) + FIELD(IRQ_STATUS_REG, IRQ_STAT_RESV_FLD, 20, 12) + FIELD(IRQ_STATUS_REG, ECC_FAIL_FLD, 19, 1) + FIELD(IRQ_STATUS_REG, TX_CRC_CHUNK_BRK_FLD, 18, 1) + FIELD(IRQ_STATUS_REG, RX_CRC_DATA_VAL_FLD, 17, 1) + FIELD(IRQ_STATUS_REG, RX_CRC_DATA_ERR_FLD, 16, 1) + FIELD(IRQ_STATUS_REG, IRQ_STAT_RESV1_FLD, 15, 1) + FIELD(IRQ_STATUS_REG, STIG_REQ_INT_FLD, 14, 1) + FIELD(IRQ_STATUS_REG, POLL_EXP_INT_FLD, 13, 1) + FIELD(IRQ_STATUS_REG, INDRD_SRAM_FULL_FLD, 12, 1) + FIELD(IRQ_STATUS_REG, RX_FIFO_FULL_FLD, 11, 1) + FIELD(IRQ_STATUS_REG, RX_FIFO_NOT_EMPTY_FLD, 10, 1) + FIELD(IRQ_STATUS_REG, TX_FIFO_FULL_FLD, 9, 1) + FIELD(IRQ_STATUS_REG, TX_FIFO_NOT_FULL_FLD, 8, 1) + FIELD(IRQ_STATUS_REG, RECV_OVERFLOW_FLD, 7, 1) + FIELD(IRQ_STATUS_REG, INDIRECT_XFER_LEVEL_BREACH_FLD, 6, 1) + FIELD(IRQ_STATUS_REG, ILLEGAL_ACCESS_DET_FLD, 5, 1) + FIELD(IRQ_STATUS_REG, PROT_WR_ATTEMPT_FLD, 4, 1) + FIELD(IRQ_STATUS_REG, INDIRECT_TRANSFER_REJECT_FLD, 3, 1) + FIELD(IRQ_STATUS_REG, INDIRECT_OP_DONE_FLD, 2, 1) + FIELD(IRQ_STATUS_REG, UNDERFLOW_DET_FLD, 1, 1) + FIELD(IRQ_STATUS_REG, MODE_M_FAIL_FLD, 0, 1) +REG32(IRQ_MASK_REG, 0x44) + FIELD(IRQ_MASK_REG, IRQ_MASK_RESV_FLD, 20, 12) + FIELD(IRQ_MASK_REG, ECC_FAIL_MASK_FLD, 19, 1) + FIELD(IRQ_MASK_REG, TX_CRC_CHUNK_BRK_MASK_FLD, 18, 1) + FIELD(IRQ_MASK_REG, RX_CRC_DATA_VAL_MASK_FLD, 17, 1) + FIELD(IRQ_MASK_REG, RX_CRC_DATA_ERR_MASK_FLD, 16, 1) + FIELD(IRQ_MASK_REG, IRQ_MASK_RESV1_FLD, 15, 1) + FIELD(IRQ_MASK_REG, STIG_REQ_MASK_FLD, 14, 1) + FIELD(IRQ_MASK_REG, POLL_EXP_INT_MASK_FLD, 13, 1) + FIELD(IRQ_MASK_REG, INDRD_SRAM_FULL_MASK_FLD, 12, 1) + FIELD(IRQ_MASK_REG, RX_FIFO_FULL_MASK_FLD, 11, 1) + FIELD(IRQ_MASK_REG, RX_FIFO_NOT_EMPTY_MASK_FLD, 10, 1) + FIELD(IRQ_MASK_REG, TX_FIFO_FULL_MASK_FLD, 9, 1) + FIELD(IRQ_MASK_REG, TX_FIFO_NOT_FULL_MASK_FLD, 8, 1) + FIELD(IRQ_MASK_REG, RECV_OVERFLOW_MASK_FLD, 7, 1) + FIELD(IRQ_MASK_REG, INDIRECT_XFER_LEVEL_BREACH_MASK_FLD, 6, 1) + FIELD(IRQ_MASK_REG, ILLEGAL_ACCESS_DET_MASK_FLD, 5, 1) + FIELD(IRQ_MASK_REG, PROT_WR_ATTEMPT_MASK_FLD, 4, 1) + FIELD(IRQ_MASK_REG, INDIRECT_TRANSFER_REJECT_MASK_FLD, 3, 1) + FIELD(IRQ_MASK_REG, INDIRECT_OP_DONE_MASK_FLD, 2, 1) + FIELD(IRQ_MASK_REG, UNDERFLOW_DET_MASK_FLD, 1, 1) + FIELD(IRQ_MASK_REG, MODE_M_FAIL_MASK_FLD, 0, 1) +REG32(LOWER_WR_PROT_REG, 0x50) +REG32(UPPER_WR_PROT_REG, 0x54) +REG32(WR_PROT_CTRL_REG, 0x58) + FIELD(WR_PROT_CTRL_REG, WR_PROT_CTRL_RESV_FLD, 2, 30) + FIELD(WR_PROT_CTRL_REG, ENB_FLD, 1, 1) + FIELD(WR_PROT_CTRL_REG, INV_FLD, 0, 1) +REG32(INDIRECT_READ_XFER_CTRL_REG, 0x60) + FIELD(INDIRECT_READ_XFER_CTRL_REG, INDIR_RD_XFER_RESV_FLD, 8, 24) + FIELD(INDIRECT_READ_XFER_CTRL_REG, NUM_IND_OPS_DONE_FLD, 6, 2) + FIELD(INDIRECT_READ_XFER_CTRL_REG, IND_OPS_DONE_STATUS_FLD, 5, 1) + FIELD(INDIRECT_READ_XFER_CTRL_REG, RD_QUEUED_FLD, 4, 1) + FIELD(INDIRECT_READ_XFER_CTRL_REG, SRAM_FULL_FLD, 3, 1) + FIELD(INDIRECT_READ_XFER_CTRL_REG, RD_STATUS_FLD, 2, 1) + FIELD(INDIRECT_READ_XFER_CTRL_REG, CANCEL_FLD, 1, 1) + FIELD(INDIRECT_READ_XFER_CTRL_REG, START_FLD, 0, 1) +REG32(INDIRECT_READ_XFER_WATERMARK_REG, 0x64) +REG32(INDIRECT_READ_XFER_START_REG, 0x68) +REG32(INDIRECT_READ_XFER_NUM_BYTES_REG, 0x6c) +REG32(INDIRECT_WRITE_XFER_CTRL_REG, 0x70) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, INDIR_WR_XFER_RESV2_FLD, 8, 24) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, NUM_IND_OPS_DONE_FLD, 6, 2) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, IND_OPS_DONE_STATUS_FLD, 5, 1) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, WR_QUEUED_FLD, 4, 1) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, INDIR_WR_XFER_RESV1_FLD, 3, 1) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, WR_STATUS_FLD, 2, 1) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, CANCEL_FLD, 1, 1) + FIELD(INDIRECT_WRITE_XFER_CTRL_REG, START_FLD, 0, 1) +REG32(INDIRECT_WRITE_XFER_WATERMARK_REG, 0x74) +REG32(INDIRECT_WRITE_XFER_START_REG, 0x78) +REG32(INDIRECT_WRITE_XFER_NUM_BYTES_REG, 0x7c) +REG32(INDIRECT_TRIGGER_ADDR_RANGE_REG, 0x80) + FIELD(INDIRECT_TRIGGER_ADDR_RANGE_REG, IND_RANGE_RESV1_FLD, 4, 28) + FIELD(INDIRECT_TRIGGER_ADDR_RANGE_REG, IND_RANGE_WIDTH_FLD, 0, 4) +REG32(FLASH_COMMAND_CTRL_MEM_REG, 0x8c) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, FLASH_COMMAND_CTRL_MEM_RESV1_FLD, 29, 3) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_ADDR_FLD, 20, 9) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, FLASH_COMMAND_CTRL_MEM_RESV2_FLD, 19, 1) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, NB_OF_STIG_READ_BYTES_FLD, 16, 3) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_READ_DATA_FLD, 8, 8) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, FLASH_COMMAND_CTRL_MEM_RESV3_FLD, 2, 6) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_REQ_IN_PROGRESS_FLD, 1, 1) + FIELD(FLASH_COMMAND_CTRL_MEM_REG, TRIGGER_MEM_BANK_REQ_FLD, 0, 1) +REG32(FLASH_CMD_CTRL_REG, 0x90) + FIELD(FLASH_CMD_CTRL_REG, CMD_OPCODE_FLD, 24, 8) + FIELD(FLASH_CMD_CTRL_REG, ENB_READ_DATA_FLD, 23, 1) + FIELD(FLASH_CMD_CTRL_REG, NUM_RD_DATA_BYTES_FLD, 20, 3) + FIELD(FLASH_CMD_CTRL_REG, ENB_COMD_ADDR_FLD, 19, 1) + FIELD(FLASH_CMD_CTRL_REG, ENB_MODE_BIT_FLD, 18, 1) + FIELD(FLASH_CMD_CTRL_REG, NUM_ADDR_BYTES_FLD, 16, 2) + FIELD(FLASH_CMD_CTRL_REG, ENB_WRITE_DATA_FLD, 15, 1) + FIELD(FLASH_CMD_CTRL_REG, NUM_WR_DATA_BYTES_FLD, 12, 3) + FIELD(FLASH_CMD_CTRL_REG, NUM_DUMMY_CYCLES_FLD, 7, 5) + FIELD(FLASH_CMD_CTRL_REG, FLASH_CMD_CTRL_RESV1_FLD, 3, 4) + FIELD(FLASH_CMD_CTRL_REG, STIG_MEM_BANK_EN_FLD, 2, 1) + FIELD(FLASH_CMD_CTRL_REG, CMD_EXEC_STATUS_FLD, 1, 1) + FIELD(FLASH_CMD_CTRL_REG, CMD_EXEC_FLD, 0, 1) +REG32(FLASH_CMD_ADDR_REG, 0x94) +REG32(FLASH_RD_DATA_LOWER_REG, 0xa0) +REG32(FLASH_RD_DATA_UPPER_REG, 0xa4) +REG32(FLASH_WR_DATA_LOWER_REG, 0xa8) +REG32(FLASH_WR_DATA_UPPER_REG, 0xac) +REG32(POLLING_FLASH_STATUS_REG, 0xb0) + FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_RSVD_FLD2, 21, 11) + FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_NB_DUMMY, 16, 5) + FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_RSVD_FLD1, 9, 7) + FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_VALID_FLD, 8, 1) + FIELD(POLLING_FLASH_STATUS_REG, DEVICE_STATUS_FLD, 0, 8) +REG32(PHY_CONFIGURATION_REG, 0xb4) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESYNC_FLD, 31, 1) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESET_FLD, 30, 1) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RX_DLL_BYPASS_FLD, 29, 1) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESV2_FLD, 23, 6) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_TX_DLL_DELAY_FLD, 16, 7) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RESV1_FLD, 7, 9) + FIELD(PHY_CONFIGURATION_REG, PHY_CONFIG_RX_DLL_DELAY_FLD, 0, 7) +REG32(PHY_MASTER_CONTROL_REG, 0xb8) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_CONTROL_RESV3_FLD, 25, 7) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_LOCK_MODE_FLD, 24, 1) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_BYPASS_MODE_FLD, 23, 1) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_PHASE_DETECT_SELECTOR_FLD, 20, 3) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_CONTROL_RESV2_FLD, 19, 1) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_NB_INDICATIONS_FLD, 16, 3) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_CONTROL_RESV1_FLD, 7, 9) + FIELD(PHY_MASTER_CONTROL_REG, PHY_MASTER_INITIAL_DELAY_FLD, 0, 7) +REG32(DLL_OBSERVABLE_LOWER_REG, 0xbc) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD, 24, 8) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD, 16, 8) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD, 15, 1) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD, 8, 7) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD, 3, 5) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD, 1, 2) + FIELD(DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD, 0, 1) +REG32(DLL_OBSERVABLE_UPPER_REG, 0xc0) + FIELD(DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE_UPPER_RESV2_FLD, 23, 9) + FIELD(DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD, 16, 7) + FIELD(DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE_UPPER_RESV1_FLD, 7, 9) + FIELD(DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD, 0, 7) +REG32(OPCODE_EXT_LOWER_REG, 0xe0) + FIELD(OPCODE_EXT_LOWER_REG, EXT_READ_OPCODE_FLD, 24, 8) + FIELD(OPCODE_EXT_LOWER_REG, EXT_WRITE_OPCODE_FLD, 16, 8) + FIELD(OPCODE_EXT_LOWER_REG, EXT_POLL_OPCODE_FLD, 8, 8) + FIELD(OPCODE_EXT_LOWER_REG, EXT_STIG_OPCODE_FLD, 0, 8) +REG32(OPCODE_EXT_UPPER_REG, 0xe4) + FIELD(OPCODE_EXT_UPPER_REG, WEL_OPCODE_FLD, 24, 8) + FIELD(OPCODE_EXT_UPPER_REG, EXT_WEL_OPCODE_FLD, 16, 8) + FIELD(OPCODE_EXT_UPPER_REG, OPCODE_EXT_UPPER_RESV1_FLD, 0, 16) +REG32(MODULE_ID_REG, 0xfc) + FIELD(MODULE_ID_REG, FIX_PATCH_FLD, 24, 8) + FIELD(MODULE_ID_REG, MODULE_ID_FLD, 8, 16) + FIELD(MODULE_ID_REG, MODULE_ID_RESV_FLD, 2, 6) + FIELD(MODULE_ID_REG, CONF_FLD, 0, 2) + +#define RXFF_SZ 1024 +#define TXFF_SZ 1024 + +#define MAX_RX_DEC_OUT 8 + +#define SZ_512MBIT (512 * 1024 * 1024) +#define SZ_1GBIT (1024 * 1024 * 1024) +#define SZ_2GBIT (2ULL * SZ_1GBIT) +#define SZ_4GBIT (4ULL * SZ_1GBIT) + +#define IS_IND_DMA_START(op) (op->done_bytes == 0) +/* + * Bit field size of R_INDIRECT_WRITE_XFER_CTRL_REG_NUM_IND_OPS_DONE_FLD + * is 2 bits, which can record max of 3 indac operations. + */ +#define IND_OPS_DONE_MAX 3 + +typedef enum { + WREN = 0x6, +} FlashCMD; + +static unsigned int ospi_stig_addr_len(XlnxVersalOspi *s) +{ + /* Num address bytes is NUM_ADDR_BYTES_FLD + 1 */ + return ARRAY_FIELD_EX32(s->regs, + FLASH_CMD_CTRL_REG, NUM_ADDR_BYTES_FLD) + 1; +} + +static unsigned int ospi_stig_wr_data_len(XlnxVersalOspi *s) +{ + /* Num write data bytes is NUM_WR_DATA_BYTES_FLD + 1 */ + return ARRAY_FIELD_EX32(s->regs, + FLASH_CMD_CTRL_REG, NUM_WR_DATA_BYTES_FLD) + 1; +} + +static unsigned int ospi_stig_rd_data_len(XlnxVersalOspi *s) +{ + /* Num read data bytes is NUM_RD_DATA_BYTES_FLD + 1 */ + return ARRAY_FIELD_EX32(s->regs, + FLASH_CMD_CTRL_REG, NUM_RD_DATA_BYTES_FLD) + 1; +} + +/* + * Status bits in R_IRQ_STATUS_REG are set when the event occurs and the + * interrupt is enabled in the mask register ([1] Section 2.3.17) + */ +static void set_irq(XlnxVersalOspi *s, uint32_t set_mask) +{ + s->regs[R_IRQ_STATUS_REG] |= s->regs[R_IRQ_MASK_REG] & set_mask; +} + +static void ospi_update_irq_line(XlnxVersalOspi *s) +{ + qemu_set_irq(s->irq, !!(s->regs[R_IRQ_STATUS_REG] & + s->regs[R_IRQ_MASK_REG])); +} + +static uint8_t ospi_get_wr_opcode(XlnxVersalOspi *s) +{ + return ARRAY_FIELD_EX32(s->regs, + DEV_INSTR_WR_CONFIG_REG, WR_OPCODE_FLD); +} + +static uint8_t ospi_get_rd_opcode(XlnxVersalOspi *s) +{ + return ARRAY_FIELD_EX32(s->regs, + DEV_INSTR_RD_CONFIG_REG, RD_OPCODE_NON_XIP_FLD); +} + +static uint32_t ospi_get_num_addr_bytes(XlnxVersalOspi *s) +{ + /* Num address bytes is NUM_ADDR_BYTES_FLD + 1 */ + return ARRAY_FIELD_EX32(s->regs, + DEV_SIZE_CONFIG_REG, NUM_ADDR_BYTES_FLD) + 1; +} + +static void ospi_stig_membank_req(XlnxVersalOspi *s) +{ + int idx = ARRAY_FIELD_EX32(s->regs, + FLASH_COMMAND_CTRL_MEM_REG, MEM_BANK_ADDR_FLD); + + ARRAY_FIELD_DP32(s->regs, FLASH_COMMAND_CTRL_MEM_REG, + MEM_BANK_READ_DATA_FLD, s->stig_membank[idx]); +} + +static int ospi_stig_membank_rd_bytes(XlnxVersalOspi *s) +{ + int rd_data_fld = ARRAY_FIELD_EX32(s->regs, FLASH_COMMAND_CTRL_MEM_REG, + NB_OF_STIG_READ_BYTES_FLD); + static const int sizes[6] = { 16, 32, 64, 128, 256, 512 }; + return (rd_data_fld < 6) ? sizes[rd_data_fld] : 0; +} + +static uint32_t ospi_get_page_sz(XlnxVersalOspi *s) +{ + return ARRAY_FIELD_EX32(s->regs, + DEV_SIZE_CONFIG_REG, BYTES_PER_DEVICE_PAGE_FLD); +} + +static bool ospi_ind_rd_watermark_enabled(XlnxVersalOspi *s) +{ + return s->regs[R_INDIRECT_READ_XFER_WATERMARK_REG]; +} + +static void ind_op_advance(IndOp *op, unsigned int len) +{ + op->done_bytes += len; + assert(op->done_bytes <= op->num_bytes); + if (op->done_bytes == op->num_bytes) { + op->completed = true; + } +} + +static uint32_t ind_op_next_byte(IndOp *op) +{ + return op->flash_addr + op->done_bytes; +} + +static uint32_t ind_op_end_byte(IndOp *op) +{ + return op->flash_addr + op->num_bytes; +} + +static void ospi_ind_op_next(IndOp *op) +{ + op[0] = op[1]; + op[1].completed = true; +} + +static void ind_op_setup(IndOp *op, uint32_t flash_addr, uint32_t num_bytes) +{ + if (num_bytes & 0x3) { + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI indirect op num bytes not word aligned\n"); + } + op->flash_addr = flash_addr; + op->num_bytes = num_bytes; + op->done_bytes = 0; + op->completed = false; +} + +static bool ospi_ind_op_completed(IndOp *op) +{ + return op->completed; +} + +static bool ospi_ind_op_all_completed(XlnxVersalOspi *s) +{ + return s->rd_ind_op[0].completed && s->wr_ind_op[0].completed; +} + +static void ospi_ind_op_cancel(IndOp *op) +{ + op[0].completed = true; + op[1].completed = true; +} + +static bool ospi_ind_op_add(IndOp *op, Fifo8 *fifo, + uint32_t flash_addr, uint32_t num_bytes) +{ + /* Check if first indirect op has been completed */ + if (op->completed) { + fifo8_reset(fifo); + ind_op_setup(op, flash_addr, num_bytes); + return false; + } + + /* Check if second indirect op has been completed */ + op++; + if (op->completed) { + ind_op_setup(op, flash_addr, num_bytes); + return false; + } + return true; +} + +static void ospi_ind_op_queue_up_rd(XlnxVersalOspi *s) +{ + uint32_t num_bytes = s->regs[R_INDIRECT_READ_XFER_NUM_BYTES_REG]; + uint32_t flash_addr = s->regs[R_INDIRECT_READ_XFER_START_REG]; + bool failed; + + failed = ospi_ind_op_add(s->rd_ind_op, &s->rx_sram, flash_addr, num_bytes); + /* If two already queued set rd reject interrupt */ + if (failed) { + set_irq(s, R_IRQ_STATUS_REG_INDIRECT_TRANSFER_REJECT_FLD_MASK); + } +} + +static void ospi_ind_op_queue_up_wr(XlnxVersalOspi *s) +{ + uint32_t num_bytes = s->regs[R_INDIRECT_WRITE_XFER_NUM_BYTES_REG]; + uint32_t flash_addr = s->regs[R_INDIRECT_WRITE_XFER_START_REG]; + bool failed; + + failed = ospi_ind_op_add(s->wr_ind_op, &s->tx_sram, flash_addr, num_bytes); + /* If two already queued set rd reject interrupt */ + if (failed) { + set_irq(s, R_IRQ_STATUS_REG_INDIRECT_TRANSFER_REJECT_FLD_MASK); + } +} + +static uint64_t flash_sz(XlnxVersalOspi *s, unsigned int cs) +{ + /* Flash sizes in MB */ + static const uint64_t sizes[4] = { SZ_512MBIT / 8, SZ_1GBIT / 8, + SZ_2GBIT / 8, SZ_4GBIT / 8 }; + uint32_t v = s->regs[R_DEV_SIZE_CONFIG_REG]; + + v >>= cs * R_DEV_SIZE_CONFIG_REG_MEM_SIZE_ON_CS0_FLD_LENGTH; + return sizes[FIELD_EX32(v, DEV_SIZE_CONFIG_REG, MEM_SIZE_ON_CS0_FLD)]; +} + +static unsigned int ospi_get_block_sz(XlnxVersalOspi *s) +{ + unsigned int block_fld = ARRAY_FIELD_EX32(s->regs, + DEV_SIZE_CONFIG_REG, + BYTES_PER_SUBSECTOR_FLD); + return 1 << block_fld; +} + +static unsigned int flash_blocks(XlnxVersalOspi *s, unsigned int cs) +{ + unsigned int b_sz = ospi_get_block_sz(s); + unsigned int f_sz = flash_sz(s, cs); + + return f_sz / b_sz; +} + +static int ospi_ahb_decoder_cs(XlnxVersalOspi *s, hwaddr addr) +{ + uint64_t end_addr = 0; + int cs; + + for (cs = 0; cs < s->num_cs; cs++) { + end_addr += flash_sz(s, cs); + if (addr < end_addr) { + break; + } + } + + if (cs == s->num_cs) { + /* Address is out of range */ + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI flash address does not fit in configuration\n"); + return -1; + } + return cs; +} + +static void ospi_ahb_decoder_enable_cs(XlnxVersalOspi *s, hwaddr addr) +{ + int cs = ospi_ahb_decoder_cs(s, addr); + + if (cs >= 0) { + for (int i = 0; i < s->num_cs; i++) { + qemu_set_irq(s->cs_lines[i], cs != i); + } + } +} + +static unsigned int single_cs(XlnxVersalOspi *s) +{ + unsigned int field = ARRAY_FIELD_EX32(s->regs, + CONFIG_REG, PERIPH_CS_LINES_FLD); + + /* + * Below one liner is a trick that finds the rightmost zero and makes sure + * all other bits are turned to 1. It is a variant of the 'Isolate the + * rightmost 0-bit' trick found below at the time of writing: + * + * https://emre.me/computer-science/bit-manipulation-tricks/ + * + * 4'bXXX0 -> 4'b1110 + * 4'bXX01 -> 4'b1101 + * 4'bX011 -> 4'b1011 + * 4'b0111 -> 4'b0111 + * 4'b1111 -> 4'b1111 + */ + return (field | ~(field + 1)) & 0xf; +} + +static void ospi_update_cs_lines(XlnxVersalOspi *s) +{ + unsigned int all_cs; + int i; + + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, PERIPH_SEL_DEC_FLD)) { + all_cs = ARRAY_FIELD_EX32(s->regs, CONFIG_REG, PERIPH_CS_LINES_FLD); + } else { + all_cs = single_cs(s); + } + + for (i = 0; i < s->num_cs; i++) { + bool cs = (all_cs >> i) & 1; + + qemu_set_irq(s->cs_lines[i], cs); + } +} + +static void ospi_dac_cs(XlnxVersalOspi *s, hwaddr addr) +{ + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENABLE_AHB_DECODER_FLD)) { + ospi_ahb_decoder_enable_cs(s, addr); + } else { + ospi_update_cs_lines(s); + } +} + +static void ospi_disable_cs(XlnxVersalOspi *s) +{ + int i; + + for (i = 0; i < s->num_cs; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } +} + +static void ospi_flush_txfifo(XlnxVersalOspi *s) +{ + while (!fifo8_is_empty(&s->tx_fifo)) { + uint32_t tx_rx = fifo8_pop(&s->tx_fifo); + + tx_rx = ssi_transfer(s->spi, tx_rx); + fifo8_push(&s->rx_fifo, tx_rx); + } +} + +static void ospi_tx_fifo_push_address_raw(XlnxVersalOspi *s, + uint32_t flash_addr, + unsigned int addr_bytes) +{ + /* Push write address */ + if (addr_bytes == 4) { + fifo8_push(&s->tx_fifo, flash_addr >> 24); + } + if (addr_bytes >= 3) { + fifo8_push(&s->tx_fifo, flash_addr >> 16); + } + if (addr_bytes >= 2) { + fifo8_push(&s->tx_fifo, flash_addr >> 8); + } + fifo8_push(&s->tx_fifo, flash_addr); +} + +static void ospi_tx_fifo_push_address(XlnxVersalOspi *s, uint32_t flash_addr) +{ + /* Push write address */ + int addr_bytes = ospi_get_num_addr_bytes(s); + + ospi_tx_fifo_push_address_raw(s, flash_addr, addr_bytes); +} + +static void ospi_tx_fifo_push_stig_addr(XlnxVersalOspi *s) +{ + uint32_t flash_addr = s->regs[R_FLASH_CMD_ADDR_REG]; + unsigned int addr_bytes = ospi_stig_addr_len(s); + + ospi_tx_fifo_push_address_raw(s, flash_addr, addr_bytes); +} + +static void ospi_tx_fifo_push_rd_op_addr(XlnxVersalOspi *s, uint32_t flash_addr) +{ + uint8_t inst_code = ospi_get_rd_opcode(s); + + fifo8_reset(&s->tx_fifo); + + /* Push read opcode */ + fifo8_push(&s->tx_fifo, inst_code); + + /* Push read address */ + ospi_tx_fifo_push_address(s, flash_addr); +} + +static void ospi_tx_fifo_push_stig_wr_data(XlnxVersalOspi *s) +{ + uint64_t data = s->regs[R_FLASH_WR_DATA_LOWER_REG]; + int wr_data_len = ospi_stig_wr_data_len(s); + int i; + + data |= (uint64_t) s->regs[R_FLASH_WR_DATA_UPPER_REG] << 32; + for (i = 0; i < wr_data_len; i++) { + int shift = i * 8; + fifo8_push(&s->tx_fifo, data >> shift); + } +} + +static void ospi_tx_fifo_push_stig_rd_data(XlnxVersalOspi *s) +{ + int rd_data_len; + int i; + + if (ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, STIG_MEM_BANK_EN_FLD)) { + rd_data_len = ospi_stig_membank_rd_bytes(s); + } else { + rd_data_len = ospi_stig_rd_data_len(s); + } + + /* transmit second part (data) */ + for (i = 0; i < rd_data_len; ++i) { + fifo8_push(&s->tx_fifo, 0); + } +} + +static void ospi_rx_fifo_pop_stig_rd_data(XlnxVersalOspi *s) +{ + int size = ospi_stig_rd_data_len(s); + uint8_t bytes[8] = {}; + int i; + + size = MIN(fifo8_num_used(&s->rx_fifo), size); + + assert(size <= 8); + + for (i = 0; i < size; i++) { + bytes[i] = fifo8_pop(&s->rx_fifo); + } + + s->regs[R_FLASH_RD_DATA_LOWER_REG] = ldl_le_p(bytes); + s->regs[R_FLASH_RD_DATA_UPPER_REG] = ldl_le_p(bytes + 4); +} + +static void ospi_ind_read(XlnxVersalOspi *s, uint32_t flash_addr, uint32_t len) +{ + int i; + + /* Create first section of read cmd */ + ospi_tx_fifo_push_rd_op_addr(s, flash_addr); + + /* transmit first part */ + ospi_update_cs_lines(s); + ospi_flush_txfifo(s); + + fifo8_reset(&s->rx_fifo); + + /* transmit second part (data) */ + for (i = 0; i < len; ++i) { + fifo8_push(&s->tx_fifo, 0); + } + ospi_flush_txfifo(s); + + for (i = 0; i < len; ++i) { + fifo8_push(&s->rx_sram, fifo8_pop(&s->rx_fifo)); + } + + /* done */ + ospi_disable_cs(s); +} + +static unsigned int ospi_dma_burst_size(XlnxVersalOspi *s) +{ + return 1 << ARRAY_FIELD_EX32(s->regs, + DMA_PERIPH_CONFIG_REG, + NUM_BURST_REQ_BYTES_FLD); +} + +static unsigned int ospi_dma_single_size(XlnxVersalOspi *s) +{ + return 1 << ARRAY_FIELD_EX32(s->regs, + DMA_PERIPH_CONFIG_REG, + NUM_SINGLE_REQ_BYTES_FLD); +} + +static void ind_rd_inc_num_done(XlnxVersalOspi *s) +{ + unsigned int done = ARRAY_FIELD_EX32(s->regs, + INDIRECT_READ_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD); + if (done < IND_OPS_DONE_MAX) { + done++; + } + done &= 0x3; + ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD, done); +} + +static void ospi_ind_rd_completed(XlnxVersalOspi *s) +{ + ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, + IND_OPS_DONE_STATUS_FLD, 1); + + ind_rd_inc_num_done(s); + ospi_ind_op_next(s->rd_ind_op); + if (ospi_ind_op_all_completed(s)) { + set_irq(s, R_IRQ_STATUS_REG_INDIRECT_OP_DONE_FLD_MASK); + } +} + +static void ospi_dma_read(XlnxVersalOspi *s) +{ + IndOp *op = s->rd_ind_op; + uint32_t dma_len = op->num_bytes; + uint32_t burst_sz = ospi_dma_burst_size(s); + uint32_t single_sz = ospi_dma_single_size(s); + uint32_t ind_trig_range; + uint32_t remainder; + XlnxCSUDMAClass *xcdc = XLNX_CSU_DMA_GET_CLASS(s->dma_src); + + ind_trig_range = (1 << ARRAY_FIELD_EX32(s->regs, + INDIRECT_TRIGGER_ADDR_RANGE_REG, + IND_RANGE_WIDTH_FLD)); + remainder = dma_len % burst_sz; + remainder = remainder % single_sz; + if (burst_sz > ind_trig_range || single_sz > ind_trig_range || + remainder != 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI DMA burst size / single size config error\n"); + } + + s->src_dma_inprog = true; + if (xcdc->read(s->dma_src, 0, dma_len) != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "OSPI DMA configuration error\n"); + } + s->src_dma_inprog = false; +} + +static void ospi_do_ind_read(XlnxVersalOspi *s) +{ + IndOp *op = s->rd_ind_op; + uint32_t next_b; + uint32_t end_b; + uint32_t len; + bool start_dma = IS_IND_DMA_START(op) && !s->src_dma_inprog; + + /* Continue to read flash until we run out of space in sram */ + while (!ospi_ind_op_completed(op) && + !fifo8_is_full(&s->rx_sram)) { + /* Read reqested number of bytes, max bytes limited to size of sram */ + next_b = ind_op_next_byte(op); + end_b = next_b + fifo8_num_free(&s->rx_sram); + end_b = MIN(end_b, ind_op_end_byte(op)); + + len = end_b - next_b; + ospi_ind_read(s, next_b, len); + ind_op_advance(op, len); + + if (ospi_ind_rd_watermark_enabled(s)) { + ARRAY_FIELD_DP32(s->regs, IRQ_STATUS_REG, + INDIRECT_XFER_LEVEL_BREACH_FLD, 1); + set_irq(s, + R_IRQ_STATUS_REG_INDIRECT_XFER_LEVEL_BREACH_FLD_MASK); + } + + if (!s->src_dma_inprog && + ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DMA_IF_FLD)) { + ospi_dma_read(s); + } + } + + /* Set sram full */ + if (fifo8_num_used(&s->rx_sram) == RXFF_SZ) { + ARRAY_FIELD_DP32(s->regs, + INDIRECT_READ_XFER_CTRL_REG, SRAM_FULL_FLD, 1); + set_irq(s, R_IRQ_STATUS_REG_INDRD_SRAM_FULL_FLD_MASK); + } + + /* Signal completion if done, unless inside recursion via ospi_dma_read */ + if (!ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DMA_IF_FLD) || start_dma) { + if (ospi_ind_op_completed(op)) { + ospi_ind_rd_completed(s); + } + } +} + +/* Transmit write enable instruction */ +static void ospi_transmit_wel(XlnxVersalOspi *s, bool ahb_decoder_cs, + hwaddr addr) +{ + fifo8_reset(&s->tx_fifo); + fifo8_push(&s->tx_fifo, WREN); + + if (ahb_decoder_cs) { + ospi_ahb_decoder_enable_cs(s, addr); + } else { + ospi_update_cs_lines(s); + } + + ospi_flush_txfifo(s); + ospi_disable_cs(s); + + fifo8_reset(&s->rx_fifo); +} + +static void ospi_ind_write(XlnxVersalOspi *s, uint32_t flash_addr, uint32_t len) +{ + bool ahb_decoder_cs = false; + uint8_t inst_code; + int i; + + assert(fifo8_num_used(&s->tx_sram) >= len); + + if (!ARRAY_FIELD_EX32(s->regs, DEV_INSTR_WR_CONFIG_REG, WEL_DIS_FLD)) { + ospi_transmit_wel(s, ahb_decoder_cs, 0); + } + + /* reset fifos */ + fifo8_reset(&s->tx_fifo); + fifo8_reset(&s->rx_fifo); + + /* Push write opcode */ + inst_code = ospi_get_wr_opcode(s); + fifo8_push(&s->tx_fifo, inst_code); + + /* Push write address */ + ospi_tx_fifo_push_address(s, flash_addr); + + /* data */ + for (i = 0; i < len; i++) { + fifo8_push(&s->tx_fifo, fifo8_pop(&s->tx_sram)); + } + + /* transmit */ + ospi_update_cs_lines(s); + ospi_flush_txfifo(s); + + /* done */ + ospi_disable_cs(s); + fifo8_reset(&s->rx_fifo); +} + +static void ind_wr_inc_num_done(XlnxVersalOspi *s) +{ + unsigned int done = ARRAY_FIELD_EX32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD); + if (done < IND_OPS_DONE_MAX) { + done++; + } + done &= 0x3; + ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD, done); +} + +static void ospi_ind_wr_completed(XlnxVersalOspi *s) +{ + ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, + IND_OPS_DONE_STATUS_FLD, 1); + ind_wr_inc_num_done(s); + ospi_ind_op_next(s->wr_ind_op); + /* Set indirect op done interrupt if enabled */ + if (ospi_ind_op_all_completed(s)) { + set_irq(s, R_IRQ_STATUS_REG_INDIRECT_OP_DONE_FLD_MASK); + } +} + +static void ospi_do_indirect_write(XlnxVersalOspi *s) +{ + uint32_t write_watermark = s->regs[R_INDIRECT_WRITE_XFER_WATERMARK_REG]; + uint32_t pagesz = ospi_get_page_sz(s); + uint32_t page_mask = ~(pagesz - 1); + IndOp *op = s->wr_ind_op; + uint32_t next_b; + uint32_t end_b; + uint32_t len; + + /* Write out tx_fifo in maximum page sz chunks */ + while (!ospi_ind_op_completed(op) && fifo8_num_used(&s->tx_sram) > 0) { + next_b = ind_op_next_byte(op); + end_b = next_b + MIN(fifo8_num_used(&s->tx_sram), pagesz); + + /* Dont cross page boundary */ + if ((end_b & page_mask) > next_b) { + end_b &= page_mask; + } + + len = end_b - next_b; + len = MIN(len, op->num_bytes - op->done_bytes); + ospi_ind_write(s, next_b, len); + ind_op_advance(op, len); + } + + /* + * Always set indirect transfer level breached interrupt if enabled + * (write watermark > 0) since the tx_sram always will be emptied + */ + if (write_watermark > 0) { + set_irq(s, R_IRQ_STATUS_REG_INDIRECT_XFER_LEVEL_BREACH_FLD_MASK); + } + + /* Signal completions if done */ + if (ospi_ind_op_completed(op)) { + ospi_ind_wr_completed(s); + } +} + +static void ospi_stig_fill_membank(XlnxVersalOspi *s) +{ + int num_rd_bytes = ospi_stig_membank_rd_bytes(s); + int idx = num_rd_bytes - 8; /* first of last 8 */ + int i; + + for (i = 0; i < num_rd_bytes; i++) { + s->stig_membank[i] = fifo8_pop(&s->rx_fifo); + } + + g_assert((idx + 4) < ARRAY_SIZE(s->stig_membank)); + + /* Fill in lower upper regs */ + s->regs[R_FLASH_RD_DATA_LOWER_REG] = ldl_le_p(&s->stig_membank[idx]); + s->regs[R_FLASH_RD_DATA_UPPER_REG] = ldl_le_p(&s->stig_membank[idx + 4]); +} + +static void ospi_stig_cmd_exec(XlnxVersalOspi *s) +{ + uint8_t inst_code; + + /* Reset fifos */ + fifo8_reset(&s->tx_fifo); + fifo8_reset(&s->rx_fifo); + + /* Push write opcode */ + inst_code = ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, CMD_OPCODE_FLD); + fifo8_push(&s->tx_fifo, inst_code); + + /* Push address if enabled */ + if (ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, ENB_COMD_ADDR_FLD)) { + ospi_tx_fifo_push_stig_addr(s); + } + + /* Enable cs */ + ospi_update_cs_lines(s); + + /* Data */ + if (ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, ENB_WRITE_DATA_FLD)) { + ospi_tx_fifo_push_stig_wr_data(s); + } else if (ARRAY_FIELD_EX32(s->regs, + FLASH_CMD_CTRL_REG, ENB_READ_DATA_FLD)) { + /* transmit first part */ + ospi_flush_txfifo(s); + fifo8_reset(&s->rx_fifo); + ospi_tx_fifo_push_stig_rd_data(s); + } + + /* Transmit */ + ospi_flush_txfifo(s); + ospi_disable_cs(s); + + if (ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, ENB_READ_DATA_FLD)) { + if (ARRAY_FIELD_EX32(s->regs, + FLASH_CMD_CTRL_REG, STIG_MEM_BANK_EN_FLD)) { + ospi_stig_fill_membank(s); + } else { + ospi_rx_fifo_pop_stig_rd_data(s); + } + } +} + +static uint32_t ospi_block_address(XlnxVersalOspi *s, unsigned int block) +{ + unsigned int block_sz = ospi_get_block_sz(s); + unsigned int cs = 0; + uint32_t addr = 0; + + while (cs < s->num_cs && block >= flash_blocks(s, cs)) { + block -= flash_blocks(s, 0); + addr += flash_sz(s, cs); + } + addr += block * block_sz; + return addr; +} + +static uint32_t ospi_get_wr_prot_addr_low(XlnxVersalOspi *s) +{ + unsigned int block = s->regs[R_LOWER_WR_PROT_REG]; + + return ospi_block_address(s, block); +} + +static uint32_t ospi_get_wr_prot_addr_upper(XlnxVersalOspi *s) +{ + unsigned int block = s->regs[R_UPPER_WR_PROT_REG]; + + /* Get address of first block out of defined range */ + return ospi_block_address(s, block + 1); +} + +static bool ospi_is_write_protected(XlnxVersalOspi *s, hwaddr addr) +{ + uint32_t wr_prot_addr_upper = ospi_get_wr_prot_addr_upper(s); + uint32_t wr_prot_addr_low = ospi_get_wr_prot_addr_low(s); + bool in_range = false; + + if (addr >= wr_prot_addr_low && addr < wr_prot_addr_upper) { + in_range = true; + } + + if (ARRAY_FIELD_EX32(s->regs, WR_PROT_CTRL_REG, INV_FLD)) { + in_range = !in_range; + } + return in_range; +} + +static uint64_t ospi_rx_sram_read(XlnxVersalOspi *s, unsigned int size) +{ + uint8_t bytes[8] = {}; + int i; + + if (size < 4 && fifo8_num_used(&s->rx_sram) >= 4) { + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI only last read of internal " + "sram is allowed to be < 32 bits\n"); + } + + size = MIN(fifo8_num_used(&s->rx_sram), size); + + assert(size <= 8); + + for (i = 0; i < size; i++) { + bytes[i] = fifo8_pop(&s->rx_sram); + } + + return ldq_le_p(bytes); +} + +static void ospi_tx_sram_write(XlnxVersalOspi *s, uint64_t value, + unsigned int size) +{ + int i; + for (i = 0; i < size && !fifo8_is_full(&s->tx_sram); i++) { + fifo8_push(&s->tx_sram, value >> 8 * i); + } +} + +static uint64_t ospi_do_dac_read(void *opaque, hwaddr addr, unsigned int size) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(opaque); + uint8_t bytes[8] = {}; + int i; + + /* Create first section of read cmd */ + ospi_tx_fifo_push_rd_op_addr(s, (uint32_t) addr); + + /* Enable cs and transmit first part */ + ospi_dac_cs(s, addr); + ospi_flush_txfifo(s); + + fifo8_reset(&s->rx_fifo); + + /* transmit second part (data) */ + for (i = 0; i < size; ++i) { + fifo8_push(&s->tx_fifo, 0); + } + ospi_flush_txfifo(s); + + /* fill in result */ + size = MIN(fifo8_num_used(&s->rx_fifo), size); + + assert(size <= 8); + + for (i = 0; i < size; i++) { + bytes[i] = fifo8_pop(&s->rx_fifo); + } + + /* done */ + ospi_disable_cs(s); + + return ldq_le_p(bytes); +} + +static void ospi_do_dac_write(void *opaque, + hwaddr addr, + uint64_t value, + unsigned int size) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(opaque); + bool ahb_decoder_cs = ARRAY_FIELD_EX32(s->regs, CONFIG_REG, + ENABLE_AHB_DECODER_FLD); + uint8_t inst_code; + unsigned int i; + + if (!ARRAY_FIELD_EX32(s->regs, DEV_INSTR_WR_CONFIG_REG, WEL_DIS_FLD)) { + ospi_transmit_wel(s, ahb_decoder_cs, addr); + } + + /* reset fifos */ + fifo8_reset(&s->tx_fifo); + fifo8_reset(&s->rx_fifo); + + /* Push write opcode */ + inst_code = ospi_get_wr_opcode(s); + fifo8_push(&s->tx_fifo, inst_code); + + /* Push write address */ + ospi_tx_fifo_push_address(s, addr); + + /* data */ + for (i = 0; i < size; i++) { + fifo8_push(&s->tx_fifo, value >> 8 * i); + } + + /* Enable cs and transmit */ + ospi_dac_cs(s, addr); + ospi_flush_txfifo(s); + ospi_disable_cs(s); + + fifo8_reset(&s->rx_fifo); +} + +static void flash_cmd_ctrl_mem_reg_post_write(RegisterInfo *reg, + uint64_t val) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(reg->opaque); + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_SPI_FLD)) { + if (ARRAY_FIELD_EX32(s->regs, + FLASH_COMMAND_CTRL_MEM_REG, + TRIGGER_MEM_BANK_REQ_FLD)) { + ospi_stig_membank_req(s); + ARRAY_FIELD_DP32(s->regs, FLASH_COMMAND_CTRL_MEM_REG, + TRIGGER_MEM_BANK_REQ_FLD, 0); + } + } +} + +static void flash_cmd_ctrl_reg_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_SPI_FLD) && + ARRAY_FIELD_EX32(s->regs, FLASH_CMD_CTRL_REG, CMD_EXEC_FLD)) { + ospi_stig_cmd_exec(s); + set_irq(s, R_IRQ_STATUS_REG_STIG_REQ_INT_FLD_MASK); + ARRAY_FIELD_DP32(s->regs, FLASH_CMD_CTRL_REG, CMD_EXEC_FLD, 0); + } +} + +static uint64_t ind_wr_dec_num_done(XlnxVersalOspi *s, uint64_t val) +{ + unsigned int done = ARRAY_FIELD_EX32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD); + done--; + done &= 0x3; + val = FIELD_DP32(val, INDIRECT_WRITE_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD, done); + return val; +} + +static bool ind_wr_clearing_op_done(XlnxVersalOspi *s, uint64_t new_val) +{ + bool set_in_reg = ARRAY_FIELD_EX32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, + IND_OPS_DONE_STATUS_FLD); + bool set_in_new_val = FIELD_EX32(new_val, INDIRECT_WRITE_XFER_CTRL_REG, + IND_OPS_DONE_STATUS_FLD); + /* return true if clearing bit */ + return set_in_reg && !set_in_new_val; +} + +static uint64_t ind_wr_xfer_ctrl_reg_pre_write(RegisterInfo *reg, + uint64_t val) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(reg->opaque); + + if (ind_wr_clearing_op_done(s, val)) { + val = ind_wr_dec_num_done(s, val); + } + return val; +} + +static void ind_wr_xfer_ctrl_reg_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(reg->opaque); + + if (s->ind_write_disabled) { + return; + } + + if (ARRAY_FIELD_EX32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, START_FLD)) { + ospi_ind_op_queue_up_wr(s); + ospi_do_indirect_write(s); + ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, START_FLD, 0); + } + + if (ARRAY_FIELD_EX32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, CANCEL_FLD)) { + ospi_ind_op_cancel(s->wr_ind_op); + fifo8_reset(&s->tx_sram); + ARRAY_FIELD_DP32(s->regs, INDIRECT_WRITE_XFER_CTRL_REG, CANCEL_FLD, 0); + } +} + +static uint64_t ind_wr_xfer_ctrl_reg_post_read(RegisterInfo *reg, + uint64_t val) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(reg->opaque); + IndOp *op = s->wr_ind_op; + + /* Check if ind ops is ongoing */ + if (!ospi_ind_op_completed(&op[0])) { + /* Check if two ind ops are queued */ + if (!ospi_ind_op_completed(&op[1])) { + val = FIELD_DP32(val, INDIRECT_WRITE_XFER_CTRL_REG, + WR_QUEUED_FLD, 1); + } + val = FIELD_DP32(val, INDIRECT_WRITE_XFER_CTRL_REG, WR_STATUS_FLD, 1); + } + return val; +} + +static uint64_t ind_rd_dec_num_done(XlnxVersalOspi *s, uint64_t val) +{ + unsigned int done = ARRAY_FIELD_EX32(s->regs, INDIRECT_READ_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD); + done--; + done &= 0x3; + val = FIELD_DP32(val, INDIRECT_READ_XFER_CTRL_REG, + NUM_IND_OPS_DONE_FLD, done); + return val; +} + +static uint64_t ind_rd_xfer_ctrl_reg_pre_write(RegisterInfo *reg, + uint64_t val) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(reg->opaque); + + if (FIELD_EX32(val, INDIRECT_READ_XFER_CTRL_REG, + IND_OPS_DONE_STATUS_FLD)) { + val = ind_rd_dec_num_done(s, val); + val &= ~R_INDIRECT_READ_XFER_CTRL_REG_IND_OPS_DONE_STATUS_FLD_MASK; + } + return val; +} + +static void ind_rd_xfer_ctrl_reg_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, INDIRECT_READ_XFER_CTRL_REG, START_FLD)) { + ospi_ind_op_queue_up_rd(s); + ospi_do_ind_read(s); + ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, START_FLD, 0); + } + + if (ARRAY_FIELD_EX32(s->regs, INDIRECT_READ_XFER_CTRL_REG, CANCEL_FLD)) { + ospi_ind_op_cancel(s->rd_ind_op); + fifo8_reset(&s->rx_sram); + ARRAY_FIELD_DP32(s->regs, INDIRECT_READ_XFER_CTRL_REG, CANCEL_FLD, 0); + } +} + +static uint64_t ind_rd_xfer_ctrl_reg_post_read(RegisterInfo *reg, + uint64_t val) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(reg->opaque); + IndOp *op = s->rd_ind_op; + + /* Check if ind ops is ongoing */ + if (!ospi_ind_op_completed(&op[0])) { + /* Check if two ind ops are queued */ + if (!ospi_ind_op_completed(&op[1])) { + val = FIELD_DP32(val, INDIRECT_READ_XFER_CTRL_REG, + RD_QUEUED_FLD, 1); + } + val = FIELD_DP32(val, INDIRECT_READ_XFER_CTRL_REG, RD_STATUS_FLD, 1); + } + return val; +} + +static uint64_t sram_fill_reg_post_read(RegisterInfo *reg, uint64_t val) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(reg->opaque); + val = ((fifo8_num_used(&s->tx_sram) & 0xFFFF) << 16) | + (fifo8_num_used(&s->rx_sram) & 0xFFFF); + return val; +} + +static uint64_t dll_obs_upper_reg_post_read(RegisterInfo *reg, uint64_t val) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(reg->opaque); + uint32_t rx_dec_out; + + rx_dec_out = FIELD_EX32(val, DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD); + + if (rx_dec_out < MAX_RX_DEC_OUT) { + ARRAY_FIELD_DP32(s->regs, DLL_OBSERVABLE_UPPER_REG, + DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD, + rx_dec_out + 1); + } + + return val; +} + + +static void xlnx_versal_ospi_reset(DeviceState *dev) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(dev); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } + + fifo8_reset(&s->rx_fifo); + fifo8_reset(&s->tx_fifo); + fifo8_reset(&s->rx_sram); + fifo8_reset(&s->tx_sram); + + s->rd_ind_op[0].completed = true; + s->rd_ind_op[1].completed = true; + s->wr_ind_op[0].completed = true; + s->wr_ind_op[1].completed = true; + ARRAY_FIELD_DP32(s->regs, DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD, 1); + ARRAY_FIELD_DP32(s->regs, DLL_OBSERVABLE_LOWER_REG, + DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD, 1); +} + +static RegisterAccessInfo ospi_regs_info[] = { + { .name = "CONFIG_REG", + .addr = A_CONFIG_REG, + .reset = 0x80780081, + .ro = 0x9c000000, + },{ .name = "DEV_INSTR_RD_CONFIG_REG", + .addr = A_DEV_INSTR_RD_CONFIG_REG, + .reset = 0x3, + .ro = 0xe0ecc800, + },{ .name = "DEV_INSTR_WR_CONFIG_REG", + .addr = A_DEV_INSTR_WR_CONFIG_REG, + .reset = 0x2, + .ro = 0xe0fcce00, + },{ .name = "DEV_DELAY_REG", + .addr = A_DEV_DELAY_REG, + },{ .name = "RD_DATA_CAPTURE_REG", + .addr = A_RD_DATA_CAPTURE_REG, + .reset = 0x1, + .ro = 0xfff0fec0, + },{ .name = "DEV_SIZE_CONFIG_REG", + .addr = A_DEV_SIZE_CONFIG_REG, + .reset = 0x101002, + .ro = 0xe0000000, + },{ .name = "SRAM_PARTITION_CFG_REG", + .addr = A_SRAM_PARTITION_CFG_REG, + .reset = 0x80, + .ro = 0xffffff00, + },{ .name = "IND_AHB_ADDR_TRIGGER_REG", + .addr = A_IND_AHB_ADDR_TRIGGER_REG, + },{ .name = "DMA_PERIPH_CONFIG_REG", + .addr = A_DMA_PERIPH_CONFIG_REG, + .ro = 0xfffff0f0, + },{ .name = "REMAP_ADDR_REG", + .addr = A_REMAP_ADDR_REG, + },{ .name = "MODE_BIT_CONFIG_REG", + .addr = A_MODE_BIT_CONFIG_REG, + .reset = 0x200, + .ro = 0xffff7800, + },{ .name = "SRAM_FILL_REG", + .addr = A_SRAM_FILL_REG, + .ro = 0xffffffff, + .post_read = sram_fill_reg_post_read, + },{ .name = "TX_THRESH_REG", + .addr = A_TX_THRESH_REG, + .reset = 0x1, + .ro = 0xffffffe0, + },{ .name = "RX_THRESH_REG", + .addr = A_RX_THRESH_REG, + .reset = 0x1, + .ro = 0xffffffe0, + },{ .name = "WRITE_COMPLETION_CTRL_REG", + .addr = A_WRITE_COMPLETION_CTRL_REG, + .reset = 0x10005, + .ro = 0x1800, + },{ .name = "NO_OF_POLLS_BEF_EXP_REG", + .addr = A_NO_OF_POLLS_BEF_EXP_REG, + .reset = 0xffffffff, + },{ .name = "IRQ_STATUS_REG", + .addr = A_IRQ_STATUS_REG, + .ro = 0xfff08000, + .w1c = 0xf7fff, + },{ .name = "IRQ_MASK_REG", + .addr = A_IRQ_MASK_REG, + .ro = 0xfff08000, + },{ .name = "LOWER_WR_PROT_REG", + .addr = A_LOWER_WR_PROT_REG, + },{ .name = "UPPER_WR_PROT_REG", + .addr = A_UPPER_WR_PROT_REG, + },{ .name = "WR_PROT_CTRL_REG", + .addr = A_WR_PROT_CTRL_REG, + .ro = 0xfffffffc, + },{ .name = "INDIRECT_READ_XFER_CTRL_REG", + .addr = A_INDIRECT_READ_XFER_CTRL_REG, + .ro = 0xffffffd4, + .w1c = 0x08, + .pre_write = ind_rd_xfer_ctrl_reg_pre_write, + .post_write = ind_rd_xfer_ctrl_reg_post_write, + .post_read = ind_rd_xfer_ctrl_reg_post_read, + },{ .name = "INDIRECT_READ_XFER_WATERMARK_REG", + .addr = A_INDIRECT_READ_XFER_WATERMARK_REG, + },{ .name = "INDIRECT_READ_XFER_START_REG", + .addr = A_INDIRECT_READ_XFER_START_REG, + },{ .name = "INDIRECT_READ_XFER_NUM_BYTES_REG", + .addr = A_INDIRECT_READ_XFER_NUM_BYTES_REG, + },{ .name = "INDIRECT_WRITE_XFER_CTRL_REG", + .addr = A_INDIRECT_WRITE_XFER_CTRL_REG, + .ro = 0xffffffdc, + .w1c = 0x20, + .pre_write = ind_wr_xfer_ctrl_reg_pre_write, + .post_write = ind_wr_xfer_ctrl_reg_post_write, + .post_read = ind_wr_xfer_ctrl_reg_post_read, + },{ .name = "INDIRECT_WRITE_XFER_WATERMARK_REG", + .addr = A_INDIRECT_WRITE_XFER_WATERMARK_REG, + .reset = 0xffffffff, + },{ .name = "INDIRECT_WRITE_XFER_START_REG", + .addr = A_INDIRECT_WRITE_XFER_START_REG, + },{ .name = "INDIRECT_WRITE_XFER_NUM_BYTES_REG", + .addr = A_INDIRECT_WRITE_XFER_NUM_BYTES_REG, + },{ .name = "INDIRECT_TRIGGER_ADDR_RANGE_REG", + .addr = A_INDIRECT_TRIGGER_ADDR_RANGE_REG, + .reset = 0x4, + .ro = 0xfffffff0, + },{ .name = "FLASH_COMMAND_CTRL_MEM_REG", + .addr = A_FLASH_COMMAND_CTRL_MEM_REG, + .ro = 0xe008fffe, + .post_write = flash_cmd_ctrl_mem_reg_post_write, + },{ .name = "FLASH_CMD_CTRL_REG", + .addr = A_FLASH_CMD_CTRL_REG, + .ro = 0x7a, + .post_write = flash_cmd_ctrl_reg_post_write, + },{ .name = "FLASH_CMD_ADDR_REG", + .addr = A_FLASH_CMD_ADDR_REG, + },{ .name = "FLASH_RD_DATA_LOWER_REG", + .addr = A_FLASH_RD_DATA_LOWER_REG, + .ro = 0xffffffff, + },{ .name = "FLASH_RD_DATA_UPPER_REG", + .addr = A_FLASH_RD_DATA_UPPER_REG, + .ro = 0xffffffff, + },{ .name = "FLASH_WR_DATA_LOWER_REG", + .addr = A_FLASH_WR_DATA_LOWER_REG, + },{ .name = "FLASH_WR_DATA_UPPER_REG", + .addr = A_FLASH_WR_DATA_UPPER_REG, + },{ .name = "POLLING_FLASH_STATUS_REG", + .addr = A_POLLING_FLASH_STATUS_REG, + .ro = 0xfff0ffff, + },{ .name = "PHY_CONFIGURATION_REG", + .addr = A_PHY_CONFIGURATION_REG, + .reset = 0x40000000, + .ro = 0x1f80ff80, + },{ .name = "PHY_MASTER_CONTROL_REG", + .addr = A_PHY_MASTER_CONTROL_REG, + .reset = 0x800000, + .ro = 0xfe08ff80, + },{ .name = "DLL_OBSERVABLE_LOWER_REG", + .addr = A_DLL_OBSERVABLE_LOWER_REG, + .ro = 0xffffffff, + },{ .name = "DLL_OBSERVABLE_UPPER_REG", + .addr = A_DLL_OBSERVABLE_UPPER_REG, + .ro = 0xffffffff, + .post_read = dll_obs_upper_reg_post_read, + },{ .name = "OPCODE_EXT_LOWER_REG", + .addr = A_OPCODE_EXT_LOWER_REG, + .reset = 0x13edfa00, + },{ .name = "OPCODE_EXT_UPPER_REG", + .addr = A_OPCODE_EXT_UPPER_REG, + .reset = 0x6f90000, + .ro = 0xffff, + },{ .name = "MODULE_ID_REG", + .addr = A_MODULE_ID_REG, + .reset = 0x300, + .ro = 0xffffffff, + } +}; + +/* Return dev-obj from reg-region created by register_init_block32 */ +static XlnxVersalOspi *xilinx_ospi_of_mr(void *mr_accessor) +{ + RegisterInfoArray *reg_array = mr_accessor; + Object *dev; + + dev = reg_array->mem.owner; + assert(dev); + + return XILINX_VERSAL_OSPI(dev); +} + +static void ospi_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + XlnxVersalOspi *s = xilinx_ospi_of_mr(opaque); + + register_write_memory(opaque, addr, value, size); + ospi_update_irq_line(s); +} + +static const MemoryRegionOps ospi_ops = { + .read = register_read_memory, + .write = ospi_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static uint64_t ospi_indac_read(void *opaque, unsigned int size) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(opaque); + uint64_t ret = ospi_rx_sram_read(s, size); + + if (!ospi_ind_op_completed(s->rd_ind_op)) { + ospi_do_ind_read(s); + } + return ret; +} + +static void ospi_indac_write(void *opaque, uint64_t value, unsigned int size) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(opaque); + + g_assert(!s->ind_write_disabled); + + if (!ospi_ind_op_completed(s->wr_ind_op)) { + ospi_tx_sram_write(s, value, size); + ospi_do_indirect_write(s); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI wr into indac area while no ongoing indac wr\n"); + } +} + +static bool is_inside_indac_range(XlnxVersalOspi *s, hwaddr addr) +{ + uint32_t range_start; + uint32_t range_end; + + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DMA_IF_FLD)) { + return true; + } + + range_start = s->regs[R_IND_AHB_ADDR_TRIGGER_REG]; + range_end = range_start + + (1 << ARRAY_FIELD_EX32(s->regs, + INDIRECT_TRIGGER_ADDR_RANGE_REG, + IND_RANGE_WIDTH_FLD)); + + addr += s->regs[R_IND_AHB_ADDR_TRIGGER_REG] & 0xF0000000; + + return addr >= range_start && addr < range_end; +} + +static bool ospi_is_indac_active(XlnxVersalOspi *s) +{ + /* + * When dac and indac cannot be active at the same time, + * return true when dac is disabled. + */ + return s->dac_with_indac || !s->dac_enable; +} + +static uint64_t ospi_dac_read(void *opaque, hwaddr addr, unsigned int size) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(opaque); + + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_SPI_FLD)) { + if (ospi_is_indac_active(s) && + is_inside_indac_range(s, addr)) { + return ospi_indac_read(s, size); + } + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DIR_ACC_CTLR_FLD) + && s->dac_enable) { + if (ARRAY_FIELD_EX32(s->regs, + CONFIG_REG, ENB_AHB_ADDR_REMAP_FLD)) { + addr += s->regs[R_REMAP_ADDR_REG]; + } + return ospi_do_dac_read(opaque, addr, size); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB rd while DAC disabled\n"); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB rd while OSPI disabled\n"); + } + + return 0; +} + +static void ospi_dac_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(opaque); + + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_SPI_FLD)) { + if (ospi_is_indac_active(s) && + !s->ind_write_disabled && + is_inside_indac_range(s, addr)) { + return ospi_indac_write(s, value, size); + } + if (ARRAY_FIELD_EX32(s->regs, CONFIG_REG, ENB_DIR_ACC_CTLR_FLD) && + s->dac_enable) { + if (ARRAY_FIELD_EX32(s->regs, + CONFIG_REG, ENB_AHB_ADDR_REMAP_FLD)) { + addr += s->regs[R_REMAP_ADDR_REG]; + } + /* Check if addr is write protected */ + if (ARRAY_FIELD_EX32(s->regs, WR_PROT_CTRL_REG, ENB_FLD) && + ospi_is_write_protected(s, addr)) { + set_irq(s, R_IRQ_STATUS_REG_PROT_WR_ATTEMPT_FLD_MASK); + ospi_update_irq_line(s); + qemu_log_mask(LOG_GUEST_ERROR, + "OSPI writing into write protected area\n"); + return; + } + ospi_do_dac_write(opaque, addr, value, size); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB wr while DAC disabled\n"); + } + } else { + qemu_log_mask(LOG_GUEST_ERROR, "OSPI AHB wr while OSPI disabled\n"); + } +} + +static const MemoryRegionOps ospi_dac_ops = { + .read = ospi_dac_read, + .write = ospi_dac_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void ospi_update_dac_status(void *opaque, int n, int level) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(opaque); + + s->dac_enable = level; +} + +static void xlnx_versal_ospi_realize(DeviceState *dev, Error **errp) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + s->num_cs = 4; + s->spi = ssi_create_bus(dev, "spi0"); + s->cs_lines = g_new0(qemu_irq, s->num_cs); + for (int i = 0; i < s->num_cs; ++i) { + sysbus_init_irq(sbd, &s->cs_lines[i]); + } + + fifo8_create(&s->rx_fifo, RXFF_SZ); + fifo8_create(&s->tx_fifo, TXFF_SZ); + fifo8_create(&s->rx_sram, RXFF_SZ); + fifo8_create(&s->tx_sram, TXFF_SZ); +} + +static void xlnx_versal_ospi_init(Object *obj) +{ + XlnxVersalOspi *s = XILINX_VERSAL_OSPI(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + DeviceState *dev = DEVICE(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_OSPI, + XILINX_VERSAL_OSPI_R_MAX * 4); + reg_array = + register_init_block32(DEVICE(obj), ospi_regs_info, + ARRAY_SIZE(ospi_regs_info), + s->regs_info, s->regs, + &ospi_ops, + XILINX_VERSAL_OSPI_ERR_DEBUG, + XILINX_VERSAL_OSPI_R_MAX * 4); + memory_region_add_subregion(&s->iomem, 0x0, &reg_array->mem); + sysbus_init_mmio(sbd, &s->iomem); + + memory_region_init_io(&s->iomem_dac, obj, &ospi_dac_ops, s, + TYPE_XILINX_VERSAL_OSPI "-dac", 0x20000000); + sysbus_init_mmio(sbd, &s->iomem_dac); + + sysbus_init_irq(sbd, &s->irq); + + object_property_add_link(obj, "dma-src", TYPE_XLNX_CSU_DMA, + (Object **)&s->dma_src, + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG); + + qdev_init_gpio_in_named(dev, ospi_update_dac_status, "ospi-mux-sel", 1); +} + +static const VMStateDescription vmstate_ind_op = { + .name = "OSPIIndOp", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(flash_addr, IndOp), + VMSTATE_UINT32(num_bytes, IndOp), + VMSTATE_UINT32(done_bytes, IndOp), + VMSTATE_BOOL(completed, IndOp), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_xlnx_versal_ospi = { + .name = TYPE_XILINX_VERSAL_OSPI, + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_FIFO8(rx_fifo, XlnxVersalOspi), + VMSTATE_FIFO8(tx_fifo, XlnxVersalOspi), + VMSTATE_FIFO8(rx_sram, XlnxVersalOspi), + VMSTATE_FIFO8(tx_sram, XlnxVersalOspi), + VMSTATE_BOOL(ind_write_disabled, XlnxVersalOspi), + VMSTATE_BOOL(dac_with_indac, XlnxVersalOspi), + VMSTATE_BOOL(dac_enable, XlnxVersalOspi), + VMSTATE_BOOL(src_dma_inprog, XlnxVersalOspi), + VMSTATE_STRUCT_ARRAY(rd_ind_op, XlnxVersalOspi, 2, 1, + vmstate_ind_op, IndOp), + VMSTATE_STRUCT_ARRAY(wr_ind_op, XlnxVersalOspi, 2, 1, + vmstate_ind_op, IndOp), + VMSTATE_UINT32_ARRAY(regs, XlnxVersalOspi, XILINX_VERSAL_OSPI_R_MAX), + VMSTATE_UINT8_ARRAY(stig_membank, XlnxVersalOspi, 512), + VMSTATE_END_OF_LIST(), + } +}; + +static Property xlnx_versal_ospi_properties[] = { + DEFINE_PROP_BOOL("dac-with-indac", XlnxVersalOspi, dac_with_indac, false), + DEFINE_PROP_BOOL("indac-write-disabled", XlnxVersalOspi, + ind_write_disabled, false), + DEFINE_PROP_END_OF_LIST(), +}; + +static void xlnx_versal_ospi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = xlnx_versal_ospi_reset; + dc->realize = xlnx_versal_ospi_realize; + dc->vmsd = &vmstate_xlnx_versal_ospi; + device_class_set_props(dc, xlnx_versal_ospi_properties); +} + +static const TypeInfo xlnx_versal_ospi_info = { + .name = TYPE_XILINX_VERSAL_OSPI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XlnxVersalOspi), + .class_init = xlnx_versal_ospi_class_init, + .instance_init = xlnx_versal_ospi_init, +}; + +static void xlnx_versal_ospi_register_types(void) +{ + type_register_static(&xlnx_versal_ospi_info); +} + +type_init(xlnx_versal_ospi_register_types) diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build index XXXXXXX..XXXXXXX 100644 --- a/hw/ssi/meson.build +++ b/hw/ssi/meson.build @@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SSI', if_true: files('ssi.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_SPI', if_true: files('stm32f2xx_spi.c')) softmmu_ss.add(when: 'CONFIG_XILINX_SPI', if_true: files('xilinx_spi.c')) softmmu_ss.add(when: 'CONFIG_XILINX_SPIPS', if_true: files('xilinx_spips.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-ospi.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_spi.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_spi.c')) -- 2.25.1 From: Francisco Iglesias <francisco.iglesias@xilinx.com> Connect the OSPI flash memory controller model (including the source and destination DMA). Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220121161141.14389-8-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/arm/xlnx-versal.h | 20 ++++++++ hw/arm/xlnx-versal.c | 93 ++++++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -XXX,XX +XXX,XX @@ #include "hw/misc/xlnx-versal-xramc.h" #include "hw/nvram/xlnx-bbram.h" #include "hw/nvram/xlnx-versal-efuse.h" +#include "hw/ssi/xlnx-versal-ospi.h" +#include "hw/dma/xlnx_csu_dma.h" #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" #define TYPE_XLNX_VERSAL "xlnx-versal" @@ -XXX,XX +XXX,XX @@ struct Versal { struct { SDHCIState sd[XLNX_VERSAL_NR_SDS]; XlnxVersalPmcIouSlcr slcr; + + struct { + XlnxVersalOspi ospi; + XlnxCSUDMA dma_src; + XlnxCSUDMA dma_dst; + MemoryRegion linear_mr; + qemu_or_irq irq_orgate; + } ospi; } iou; XlnxZynqMPRTC rtc; @@ -XXX,XX +XXX,XX @@ struct Versal { #define VERSAL_ADMA_IRQ_0 60 #define VERSAL_XRAM_IRQ_0 79 #define VERSAL_PMC_APB_IRQ 121 +#define VERSAL_OSPI_IRQ 124 #define VERSAL_SD0_IRQ_0 126 #define VERSAL_EFUSE_IRQ 139 #define VERSAL_RTC_ALARM_IRQ 142 @@ -XXX,XX +XXX,XX @@ struct Versal { #define MM_PMC_PMC_IOU_SLCR 0xf1060000 #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 +#define MM_PMC_OSPI 0xf1010000 +#define MM_PMC_OSPI_SIZE 0x10000 + +#define MM_PMC_OSPI_DAC 0xc0000000 +#define MM_PMC_OSPI_DAC_SIZE 0x20000000 + +#define MM_PMC_OSPI_DMA_DST 0xf1011800 +#define MM_PMC_OSPI_DMA_SRC 0xf1011000 + #define MM_PMC_SD0 0xf1040000U #define MM_PMC_SD0_SIZE 0x10000 #define MM_PMC_BBRAM_CTRL 0xf11f0000 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -XXX,XX +XXX,XX @@ #define GEM_REVISION 0x40070106 #define VERSAL_NUM_PMC_APB_IRQS 3 +#define NUM_OSPI_IRQ_LINES 3 static void versal_create_apu_cpus(Versal *s) { @@ -XXX,XX +XXX,XX @@ static void versal_create_pmc_iou_slcr(Versal *s, qemu_irq *pic) qdev_get_gpio_in(DEVICE(&s->pmc.apb_irq_orgate), 2)); } +static void versal_create_ospi(Versal *s, qemu_irq *pic) +{ + SysBusDevice *sbd; + MemoryRegion *mr_dac; + qemu_irq ospi_mux_sel; + DeviceState *orgate; + + memory_region_init(&s->pmc.iou.ospi.linear_mr, OBJECT(s), + "versal-ospi-linear-mr" , MM_PMC_OSPI_DAC_SIZE); + + object_initialize_child(OBJECT(s), "versal-ospi", &s->pmc.iou.ospi.ospi, + TYPE_XILINX_VERSAL_OSPI); + + mr_dac = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 1); + memory_region_add_subregion(&s->pmc.iou.ospi.linear_mr, 0x0, mr_dac); + + /* Create the OSPI destination DMA */ + object_initialize_child(OBJECT(s), "versal-ospi-dma-dst", + &s->pmc.iou.ospi.dma_dst, + TYPE_XLNX_CSU_DMA); + + object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_dst), + "dma", OBJECT(get_system_memory()), + &error_abort); + + sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst); + sysbus_realize(sbd, &error_fatal); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_DST, + sysbus_mmio_get_region(sbd, 0)); + + /* Create the OSPI source DMA */ + object_initialize_child(OBJECT(s), "versal-ospi-dma-src", + &s->pmc.iou.ospi.dma_src, + TYPE_XLNX_CSU_DMA); + + object_property_set_bool(OBJECT(&s->pmc.iou.ospi.dma_src), "is-dst", + false, &error_abort); + + object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), + "dma", OBJECT(mr_dac), &error_abort); + + object_property_set_link(OBJECT(&s->pmc.iou.ospi.dma_src), + "stream-connected-dma", + OBJECT(&s->pmc.iou.ospi.dma_dst), + &error_abort); + + sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src); + sysbus_realize(sbd, &error_fatal); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DMA_SRC, + sysbus_mmio_get_region(sbd, 0)); + + /* Realize the OSPI */ + object_property_set_link(OBJECT(&s->pmc.iou.ospi.ospi), "dma-src", + OBJECT(&s->pmc.iou.ospi.dma_src), &error_abort); + + sbd = SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi); + sysbus_realize(sbd, &error_fatal); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI, + sysbus_mmio_get_region(sbd, 0)); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_OSPI_DAC, + &s->pmc.iou.ospi.linear_mr); + + /* ospi_mux_sel */ + ospi_mux_sel = qdev_get_gpio_in_named(DEVICE(&s->pmc.iou.ospi.ospi), + "ospi-mux-sel", 0); + qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), "ospi-mux-sel", 0, + ospi_mux_sel); + + /* OSPI irq */ + object_initialize_child(OBJECT(s), "ospi-irq-orgate", + &s->pmc.iou.ospi.irq_orgate, TYPE_OR_IRQ); + object_property_set_int(OBJECT(&s->pmc.iou.ospi.irq_orgate), + "num-lines", NUM_OSPI_IRQ_LINES, &error_fatal); + + orgate = DEVICE(&s->pmc.iou.ospi.irq_orgate); + qdev_realize(orgate, NULL, &error_fatal); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.ospi), 0, + qdev_get_gpio_in(orgate, 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_src), 0, + qdev_get_gpio_in(orgate, 1)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pmc.iou.ospi.dma_dst), 0, + qdev_get_gpio_in(orgate, 2)); + + qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); +} + /* This takes the board allocated linear DDR memory and creates aliases * for each split DDR range/aperture on the Versal address map. */ @@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_bbram(s, pic); versal_create_efuse(s, pic); versal_create_pmc_iou_slcr(s, pic); + versal_create_ospi(s, pic); versal_map_ddr(s); versal_unimp(s); -- 2.25.1 From: Francisco Iglesias <francisco.iglesias@xilinx.com> Add support for Micron Xccela flash mt35xu01g. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220121161141.14389-9-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/block/m25p80.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index XXXXXXX..XXXXXXX 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -XXX,XX +XXX,XX @@ static const FlashPartInfo known_devices[] = { { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) }, { INFO("n25q512ax3", 0x20ba20, 0x1000, 64 << 10, 1024, ER_4K) }, { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) }, + { INFO_STACKED("mt35xu01g", 0x2c5b1b, 0x104100, 128 << 10, 1024, + ER_4K | ER_32K, 2) }, { INFO_STACKED("n25q00", 0x20ba21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, -- 2.25.1 From: Francisco Iglesias <francisco.iglesias@xilinx.com> Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory controller. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220121161141.14389-10-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/xlnx-versal-virt.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -XXX,XX +XXX,XX @@ #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") OBJECT_DECLARE_SIMPLE_TYPE(VersalVirt, XLNX_VERSAL_VIRT_MACHINE) +#define XLNX_VERSAL_NUM_OSPI_FLASH 4 + struct VersalVirt { MachineState parent_obj; @@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine) exit(EXIT_FAILURE); } } + + for (i = 0; i < XLNX_VERSAL_NUM_OSPI_FLASH; i++) { + BusState *spi_bus; + DeviceState *flash_dev; + qemu_irq cs_line; + DriveInfo *dinfo = drive_get(IF_MTD, 0, i); + + spi_bus = qdev_get_child_bus(DEVICE(&s->soc.pmc.iou.ospi), "spi0"); + + flash_dev = qdev_new("mt35xu01g"); + if (dinfo) { + qdev_prop_set_drive_err(flash_dev, "drive", + blk_by_legacy_dinfo(dinfo), &error_fatal); + } + qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); + + cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.pmc.iou.ospi), + i + 1, cs_line); + } } static void versal_virt_machine_instance_init(Object *obj) -- 2.25.1 From: Francisco Iglesias <francisco.iglesias@xilinx.com> List myself as maintainer for the Xilinx Versal OSPI controller. Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220121161141.14389-11-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: hw/display/dpcd.c F: include/hw/display/dpcd.h F: docs/system/arm/xlnx-versal-virt.rst +Xilinx Versal OSPI +M: Francisco Iglesias <francisco.iglesias@xilinx.com> +S: Maintained +F: hw/ssi/xlnx-versal-ospi.c +F: include/hw/ssi/xlnx-versal-ospi.h + ARM ACPI Subsystem M: Shannon Zhao <shannon.zhaosl@gmail.com> L: qemu-arm@nongnu.org -- 2.25.1 From: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: MW4PR21MB1940E8BB52F4053C943B1FCD9E219@MW4PR21MB1940.namprd21.prod.outlook.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index XXXXXXX..XXXXXXX 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -XXX,XX +XXX,XX @@ F: docs/system/arm/palm.rst Raspberry Pi M: Peter Maydell <peter.maydell@linaro.org> -R: Andrew Baumann <Andrew.Baumann@microsoft.com> R: Philippe Mathieu-Daudé <f4bug@amsat.org> L: qemu-arm@nongnu.org S: Odd Fixes -- 2.25.1 If you don't know it, it's hard to figure out the difference between the linux-headers folder and the include/standard-headers folder. So let's add a short explanation to clarify the difference. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> --- scripts/update-linux-headers.sh | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh index XXXXXXX..XXXXXXX 100755 --- a/scripts/update-linux-headers.sh +++ b/scripts/update-linux-headers.sh @@ -XXX,XX +XXX,XX @@ # # This work is licensed under the terms of the GNU GPL version 2. # See the COPYING file in the top-level directory. +# +# The script will copy the headers into two target folders: +# +# - linux-headers/ for files that are required for compiling for a +# Linux host. Generally we have these so we can use kernel structs +# and defines that are more recent than the headers that might be +# installed on the host system. Usually this script can do simple +# file copies for these headers. +# +# - include/standard-headers/ for files that are used for guest +# device emulation and are required on all hosts. For instance, we +# get our definitions of the virtio structures from the Linux +# kernel headers, but we need those definitions regardless of which +# host OS we are building for. This script has to be careful to +# sanitize the headers to remove any use of Linux-specifics such as +# types like "__u64". This work is done in the cp_portable function. tmpdir=$(mktemp -d) linux="$1" -- 2.25.1 In an SMP system it can be unclear which CPU is taking an exception; add the CPU index (which is the same value used in the TCG 'Trace %d:' logging) to the "Taking exception" log line to clarify it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-2-peter.maydell@linaro.org --- target/arm/internals.h | 2 +- target/arm/helper.c | 9 ++++++--- target/arm/m_helper.c | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index XXXXXXX..XXXXXXX 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address, ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) __attribute__((nonnull)); -void arm_log_exception(int idx); +void arm_log_exception(CPUState *cs); #endif /* !CONFIG_USER_ONLY */ diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, return target_el; } -void arm_log_exception(int idx) +void arm_log_exception(CPUState *cs) { + int idx = cs->exception_index; + if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *exc = NULL; static const char * const excnames[] = { @@ -XXX,XX +XXX,XX @@ void arm_log_exception(int idx) if (!exc) { exc = "unknown"; } - qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); + qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s] on CPU %d\n", + idx, exc, cs->cpu_index); } } @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) assert(!arm_feature(env, ARM_FEATURE_M)); - arm_log_exception(cs->exception_index); + arm_log_exception(cs); qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env), new_el); if (qemu_loglevel_mask(CPU_LOG_INT) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) uint32_t lr; bool ignore_stackfaults; - arm_log_exception(cs->exception_index); + arm_log_exception(cs); /* * For exceptions we just mark as pending on the NVIC, and let that -- 2.25.1 The ITS currently has no tracepoints; add a minimal set that allows basic monitoring of guest register accesses and reading of commands from the command queue. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-3-peter.maydell@linaro.org --- hw/intc/arm_gicv3_its.c | 11 +++++++++++ hw/intc/trace-events | 8 ++++++++ 2 files changed, 19 insertions(+) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -XXX,XX +XXX,XX @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "trace.h" #include "hw/qdev-properties.h" #include "hw/intc/arm_gicv3_its_common.h" #include "gicv3_internal.h" @@ -XXX,XX +XXX,XX @@ static void process_cmdq(GICv3ITSState *s) cmd = (data & CMD_MASK); + trace_gicv3_its_process_command(rd_offset, cmd); + switch (cmd) { case GITS_CMD_INT: result = process_its_cmd(s, data, cq_offset, INTERRUPT); @@ -XXX,XX +XXX,XX @@ static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset, bool result = true; uint32_t devid = 0; + trace_gicv3_its_translation_write(offset, data, size, attrs.requester_id); + switch (offset) { case GITS_TRANSLATER: if (s->ctlr & R_GITS_CTLR_ENABLED_MASK) { @@ -XXX,XX +XXX,XX @@ static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data, qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read at offset " TARGET_FMT_plx "size %u\n", __func__, offset, size); + trace_gicv3_its_badread(offset, size); /* * The spec requires that reserved registers are RAZ/WI; * so use false returns from leaf functions as a way to @@ -XXX,XX +XXX,XX @@ static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data, * the caller, or we'll cause a spurious guest data abort. */ *data = 0; + } else { + trace_gicv3_its_read(offset, *data, size); } return MEMTX_OK; } @@ -XXX,XX +XXX,XX @@ static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data, qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write at offset " TARGET_FMT_plx "size %u\n", __func__, offset, size); + trace_gicv3_its_badwrite(offset, data, size); /* * The spec requires that reserved registers are RAZ/WI; * so use false returns from leaf functions as a way to * trigger the guest-error logging but don't return it to * the caller, or we'll cause a spurious guest data abort. */ + } else { + trace_gicv3_its_write(offset, data, size); } return MEMTX_OK; } diff --git a/hw/intc/trace-events b/hw/intc/trace-events index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -XXX,XX +XXX,XX @@ gicv3_redist_badwrite(uint32_t cpu, uint64_t offset, uint64_t data, unsigned siz gicv3_redist_set_irq(uint32_t cpu, int irq, int level) "GICv3 redistributor 0x%x interrupt %d level changed to %d" gicv3_redist_send_sgi(uint32_t cpu, int irq) "GICv3 redistributor 0x%x pending SGI %d" +# arm_gicv3_its.c +gicv3_its_read(uint64_t offset, uint64_t data, unsigned size) "GICv3 ITS read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +gicv3_its_badread(uint64_t offset, unsigned size) "GICv3 ITS read: offset 0x%" PRIx64 " size %u: error" +gicv3_its_write(uint64_t offset, uint64_t data, unsigned size) "GICv3 ITS write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" +gicv3_its_badwrite(uint64_t offset, uint64_t data, unsigned size) "GICv3 ITS write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u: error" +gicv3_its_translation_write(uint64_t offset, uint64_t data, unsigned size, uint32_t requester_id) "GICv3 ITS TRANSLATER write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u requester_id 0x%x" +gicv3_its_process_command(uint32_t rd_offset, uint8_t cmd) "GICv3 ITS: processing command at offset 0x%x: 0x%x" + # armv7m_nvic.c nvic_recompute_state(int vectpending, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d vectpending_prio %d exception_prio %d" nvic_recompute_state_secure(int vectpending, bool vectpending_is_s_banked, int vectpending_prio, int exception_prio) "NVIC state recomputed: vectpending %d is_s_banked %d vectpending_prio %d exception_prio %d" -- 2.25.1 In our implementation, all ITSes connected to a GIC share a single AddressSpace, which we keep in the GICv3State::dma_as field and initialized based on the GIC's 'sysmem' property. The right place to set it up by calling address_space_init() is therefore in the GIC's realize method, not the ITS's realize. This fixes a theoretical bug where QEMU hangs on startup if the board model creates two ITSes connected to the same GIC -- we would call address_space_init() twice on the same AddressSpace*, which creates an infinite loop in the QTAILQ that softmmu/memory.c uses to store its list of AddressSpaces and causes any subsequent attempt to iterate through that list to loop forever. There aren't any board models like that in the tree at the moment, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-4-peter.maydell@linaro.org --- hw/intc/arm_gicv3_common.c | 5 +++++ hw/intc/arm_gicv3_its.c | 3 --- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_realize(DeviceState *dev, Error **errp) return; } + if (s->lpi_enable) { + address_space_init(&s->dma_as, s->dma, + "gicv3-its-sysmem"); + } + s->cpu = g_new0(GICv3CPUState, s->num_cpu); for (i = 0; i < s->num_cpu; i++) { diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -XXX,XX +XXX,XX @@ static void gicv3_arm_its_realize(DeviceState *dev, Error **errp) gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops); - address_space_init(&s->gicv3->dma_as, s->gicv3->dma, - "gicv3-its-sysmem"); - /* set the ITS default features supported */ s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL, 1); s->typer = FIELD_DP64(s->typer, GITS_TYPER, ITT_ENTRY_SIZE, -- 2.25.1 The current ITS code clears GITS_CREADR when GITS_CTLR.ENABLED is set. This is not correct -- guest code can validly clear ENABLED and then set it again and expect the ITS to continue processing where it left off. Remove the erroneous assignment. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-5-peter.maydell@linaro.org --- hw/intc/arm_gicv3_its.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -XXX,XX +XXX,XX @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, s->ctlr |= R_GITS_CTLR_ENABLED_MASK; extract_table_params(s); extract_cmdq_params(s); - s->creadr = 0; process_cmdq(s); } else { s->ctlr &= ~R_GITS_CTLR_ENABLED_MASK; -- 2.25.1 The ITS specification says that when the guest writes to GITS_CBASER this causes GITS_CREADR to be cleared. However it does not have an equivalent clause for GITS_CWRITER. (This is because GITS_CREADR is read-only, but GITS_CWRITER is writable and the guest can initialize it.) Remove the code that clears GITS_CWRITER on GITS_CBASER writes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-6-peter.maydell@linaro.org --- hw/intc/arm_gicv3_its.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -XXX,XX +XXX,XX @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { s->cbaser = deposit64(s->cbaser, 0, 32, value); s->creadr = 0; - s->cwriter = s->creadr; } break; case GITS_CBASER + 4: @@ -XXX,XX +XXX,XX @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { s->cbaser = deposit64(s->cbaser, 32, 32, value); s->creadr = 0; - s->cwriter = s->creadr; } break; case GITS_CWRITER: @@ -XXX,XX +XXX,XX @@ static bool its_writell(GICv3ITSState *s, hwaddr offset, if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { s->cbaser = value; s->creadr = 0; - s->cwriter = s->creadr; } break; case GITS_CWRITER: -- 2.25.1 The GICD_CTLR distributor register has enable bits which control whether the different interrupt groups (Group 0, Non-secure Group 1 and Secure Group 1) are forwarded to the CPU. We get this right for traditional interrupts, but forgot to account for it when adding LPIs. LPIs are always Group 1 NS and if the EnableGrp1NS bit is not set we must not forward them to the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-7-peter.maydell@linaro.org --- hw/intc/arm_gicv3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -XXX,XX +XXX,XX @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs) } if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable && + (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) && (cs->hpplpi.prio != 0xff)) { if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) { cs->hppi.irq = cs->hpplpi.irq; -- 2.25.1 The list of #defines for the ITS command packet numbers is neither in alphabetical nor numeric order. Sort it into numeric order. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-8-peter.maydell@linaro.org --- hw/intc/gicv3_internal.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -XXX,XX +XXX,XX @@ FIELD(GITS_TYPER, CIL, 36, 1) #define CMD_MASK 0xff /* ITS Commands */ -#define GITS_CMD_CLEAR 0x04 -#define GITS_CMD_DISCARD 0x0F #define GITS_CMD_INT 0x03 -#define GITS_CMD_MAPC 0x09 +#define GITS_CMD_CLEAR 0x04 +#define GITS_CMD_SYNC 0x05 #define GITS_CMD_MAPD 0x08 -#define GITS_CMD_MAPI 0x0B +#define GITS_CMD_MAPC 0x09 #define GITS_CMD_MAPTI 0x0A +#define GITS_CMD_MAPI 0x0B #define GITS_CMD_INV 0x0C #define GITS_CMD_INVALL 0x0D -#define GITS_CMD_SYNC 0x05 +#define GITS_CMD_DISCARD 0x0F /* MAPC command fields */ #define ICID_LENGTH 16 -- 2.25.1 The ITS-related parts of the redistributor code make some checks for whether registers like GICR_PROPBASER and GICR_PENDBASER are zero. There is no requirement in the specification for treating zeroes in these address registers specially -- they contain guest physical addresses and it is entirely valid (if unusual) for the guest to choose to put the tables they address at guest physical address zero. We use these values only to calculate guest addresses, and attempts by the guest to use a bad address will be handled by the address_space_* functions which we use to do the loads and stores. Remove the unnecessary checks. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-9-peter.maydell@linaro.org --- hw/intc/arm_gicv3_redist.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -XXX,XX +XXX,XX @@ void gicv3_redist_update_lpi_only(GICv3CPUState *cs) idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS), GICD_TYPER_IDBITS); - if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !cs->gicr_propbaser || - !cs->gicr_pendbaser) { + if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { return; } @@ -XXX,XX +XXX,XX @@ void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level) idbits = MIN(FIELD_EX64(cs->gicr_propbaser, GICR_PROPBASER, IDBITS), GICD_TYPER_IDBITS); - if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || !cs->gicr_propbaser || - !cs->gicr_pendbaser || (irq > (1ULL << (idbits + 1)) - 1) || - irq < GICV3_LPI_INTID_START) { + if (!(cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || + (irq > (1ULL << (idbits + 1)) - 1) || irq < GICV3_LPI_INTID_START) { return; } -- 2.25.1 The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate that the GICR_CTLR.EnableLPIs bit can be written to 0 to disable LPIs (as opposed to allowing LPIs to be enabled but not subsequently disabled). Our implementation permits this, so advertise it by setting CES to 1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-10-peter.maydell@linaro.org --- hw/intc/gicv3_internal.h | 1 + hw/intc/arm_gicv3_common.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -XXX,XX +XXX,XX @@ #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) #define GICR_CTLR_ENABLE_LPIS (1U << 0) +#define GICR_CTLR_CES (1U << 1) #define GICR_CTLR_RWP (1U << 3) #define GICR_CTLR_DPG0 (1U << 24) #define GICR_CTLR_DPG1NS (1U << 25) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -XXX,XX +XXX,XX @@ static void arm_gicv3_common_reset(DeviceState *dev) cs->level = 0; cs->gicr_ctlr = 0; + if (s->lpi_enable) { + /* Our implementation supports clearing GICR_CTLR.EnableLPIs */ + cs->gicr_ctlr |= GICR_CTLR_CES; + } cs->gicr_statusr[GICV3_S] = 0; cs->gicr_statusr[GICV3_NS] = 0; cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep; -- 2.25.1 The MemoryRegionOps gicv3_its_translation_ops currently provides only a .write_with_attrs function, because the only register in this region is the write-only GITS_TRANSLATER. However, if you don't provide a read function and the guest tries reading from this memory region, QEMU will crash because memory_region_read_with_attrs_accessor() calls a NULL pointer. Add a read function which always returns 0, to cover both bogus attempts to read GITS_TRANSLATER and also reads from the rest of the region, which is documented to be reserved, RES0. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-11-peter.maydell@linaro.org --- hw/intc/arm_gicv3_its.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -XXX,XX +XXX,XX @@ static void extract_cmdq_params(GICv3ITSState *s) } } +static MemTxResult gicv3_its_translation_read(void *opaque, hwaddr offset, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + /* + * GITS_TRANSLATER is write-only, and all other addresses + * in the interrupt translation space frame are RES0. + */ + *data = 0; + return MEMTX_OK; +} + static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset, uint64_t data, unsigned size, MemTxAttrs attrs) @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps gicv3_its_control_ops = { }; static const MemoryRegionOps gicv3_its_translation_ops = { + .read_with_attrs = gicv3_its_translation_read, .write_with_attrs = gicv3_its_translation_write, .valid.min_access_size = 2, .valid.max_access_size = 4, -- 2.25.1 The ITS has a bank of 8 GITS_BASER<n> registers, which allow the guest to specify the base address of various data tables. Each register has a read-only type field indicating which table it is for and a read-write field where the guest can write in the base address (among other things). We currently allow the guest to write the writeable fields for all eight registers, even if the type field is 0 indicating "Unimplemented". This means the guest can provoke QEMU into asserting by writing an address into one of these unimplemented base registers, which bypasses the "if (!value) continue" check in extract_table_params() and lets us hit the assertion that the type field is one of the permitted table types. Prevent the assertion by not allowing the guest to write to the unimplemented base registers. This means their value will remain 0 and extract_table_params() will ignore them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-12-peter.maydell@linaro.org --- hw/intc/arm_gicv3_its.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -XXX,XX +XXX,XX @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { index = (offset - GITS_BASER) / 8; + if (s->baser[index] == 0) { + /* Unimplemented GITS_BASERn: RAZ/WI */ + break; + } if (offset & 7) { value <<= 32; value &= ~GITS_BASER_RO_MASK; @@ -XXX,XX +XXX,XX @@ static bool its_writell(GICv3ITSState *s, hwaddr offset, */ if (!(s->ctlr & R_GITS_CTLR_ENABLED_MASK)) { index = (offset - GITS_BASER) / 8; + if (s->baser[index] == 0) { + /* Unimplemented GITS_BASERn: RAZ/WI */ + break; + } s->baser[index] &= GITS_BASER_RO_MASK; s->baser[index] |= (value & ~GITS_BASER_RO_MASK); } -- 2.25.1 Currently when we fill in a TableDesc based on the value the guest has written to the GITS_BASER<n> register, we calculate both: * num_entries : the number of entries in the table, constrained by the amount of memory the guest has given it * num_ids : the number of IDs we support for this table, constrained by the implementation choices and the architecture (eg DeviceIDs are 16 bits, so num_ids is 1 << 16) When validating ITS commands, however, we check only num_ids, thus allowing a broken guest to specify table entries that index off the end of it. This will only corrupt guest memory, but the ITS is supposed to reject such commands as invalid. Instead of calculating both num_entries and num_ids, set num_entries to the minimum of the two limits, and check that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-13-peter.maydell@linaro.org --- include/hw/intc/arm_gicv3_its_common.h | 1 - hw/intc/arm_gicv3_its.c | 18 +++++++++--------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/include/hw/intc/arm_gicv3_its_common.h b/include/hw/intc/arm_gicv3_its_common.h index XXXXXXX..XXXXXXX 100644 --- a/include/hw/intc/arm_gicv3_its_common.h +++ b/include/hw/intc/arm_gicv3_its_common.h @@ -XXX,XX +XXX,XX @@ typedef struct { uint16_t entry_sz; uint32_t page_sz; uint32_t num_entries; - uint32_t num_ids; uint64_t base_addr; } TableDesc; diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_its_cmd(GICv3ITSState *s, uint64_t value, eventid = (value & EVENTID_MASK); - if (devid >= s->dt.num_ids) { + if (devid >= s->dt.num_entries) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid command attributes: devid %d>=%d", - __func__, devid, s->dt.num_ids); + __func__, devid, s->dt.num_entries); return CMD_CONTINUE; } @@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_its_cmd(GICv3ITSState *s, uint64_t value, return CMD_CONTINUE; } - if (icid >= s->ct.num_ids) { + if (icid >= s->ct.num_entries) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid ICID 0x%x in ITE (table corrupted?)\n", __func__, icid); @@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapti(GICv3ITSState *s, uint64_t value, icid = value & ICID_MASK; - if (devid >= s->dt.num_ids) { + if (devid >= s->dt.num_entries) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid command attributes: devid %d>=%d", - __func__, devid, s->dt.num_ids); + __func__, devid, s->dt.num_entries); return CMD_CONTINUE; } @@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapti(GICv3ITSState *s, uint64_t value, num_eventids = 1ULL << (FIELD_EX64(dte, DTE, SIZE) + 1); num_intids = 1ULL << (GICD_TYPER_IDBITS + 1); - if ((icid >= s->ct.num_ids) + if ((icid >= s->ct.num_entries) || !dte_valid || (eventid >= num_eventids) || (((pIntid < GICV3_LPI_INTID_START) || (pIntid >= num_intids)) && (pIntid != INTID_SPURIOUS))) { @@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapc(GICv3ITSState *s, uint32_t offset) valid = (value & CMD_FIELD_VALID_MASK); - if ((icid >= s->ct.num_ids) || (rdbase >= s->gicv3->num_cpu)) { + if ((icid >= s->ct.num_entries) || (rdbase >= s->gicv3->num_cpu)) { qemu_log_mask(LOG_GUEST_ERROR, "ITS MAPC: invalid collection table attributes " "icid %d rdbase %" PRIu64 "\n", icid, rdbase); @@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapd(GICv3ITSState *s, uint64_t value, valid = (value & CMD_FIELD_VALID_MASK); - if ((devid >= s->dt.num_ids) || + if ((devid >= s->dt.num_entries) || (size > FIELD_EX64(s->typer, GITS_TYPER, IDBITS))) { qemu_log_mask(LOG_GUEST_ERROR, "ITS MAPD: invalid device table attributes " @@ -XXX,XX +XXX,XX @@ static void extract_table_params(GICv3ITSState *s) L1TABLE_ENTRY_SIZE) * (page_sz / td->entry_sz)); } - td->num_ids = 1ULL << idbits; + td->num_entries = MIN(td->num_entries, 1ULL << idbits); } } -- 2.25.1 Implement the ITS MOVALL command, which takes all the pending interrupts on a source redistributor and makes the not-pending on that source redistributor and pending on a destination redistributor. This is a GICv3 ITS command which we forgot to implement. (It is not used by Linux guests.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-14-peter.maydell@linaro.org --- hw/intc/gicv3_internal.h | 16 +++++++++++ hw/intc/arm_gicv3_its.c | 55 ++++++++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_redist.c | 54 +++++++++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -XXX,XX +XXX,XX @@ FIELD(GITS_TYPER, CIL, 36, 1) #define GITS_CMD_MAPI 0x0B #define GITS_CMD_INV 0x0C #define GITS_CMD_INVALL 0x0D +#define GITS_CMD_MOVALL 0x0E #define GITS_CMD_DISCARD 0x0F /* MAPC command fields */ @@ -XXX,XX +XXX,XX @@ FIELD(MAPC, RDBASE, 16, 32) #define L2_TABLE_VALID_MASK CMD_FIELD_VALID_MASK #define TABLE_ENTRY_VALID_MASK (1ULL << 0) +/* MOVALL command fields */ +FIELD(MOVALL_2, RDBASE1, 16, 36) +FIELD(MOVALL_3, RDBASE2, 16, 36) + /* * 12 bytes Interrupt translation Table Entry size * as per Table 5.3 in GICv3 spec @@ -XXX,XX +XXX,XX @@ void gicv3_redist_update_lpi(GICv3CPUState *cs); * an incoming migration has loaded new state. */ void gicv3_redist_update_lpi_only(GICv3CPUState *cs); +/** + * gicv3_redist_movall_lpis: + * @src: source redistributor + * @dest: destination redistributor + * + * Scan the LPI pending table for @src, and for each pending LPI there + * mark it as not-pending for @src and pending for @dest, as required + * by the ITS MOVALL command. + */ +void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest); + void gicv3_redist_send_sgi(GICv3CPUState *cs, int grp, int irq, bool ns); void gicv3_init_cpuif(GICv3State *s); diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_mapd(GICv3ITSState *s, uint64_t value, return update_dte(s, devid, valid, size, itt_addr) ? CMD_CONTINUE : CMD_STALL; } +static ItsCmdResult process_movall(GICv3ITSState *s, uint64_t value, + uint32_t offset) +{ + AddressSpace *as = &s->gicv3->dma_as; + MemTxResult res = MEMTX_OK; + uint64_t rd1, rd2; + + /* No fields in dwords 0 or 1 */ + offset += NUM_BYTES_IN_DW; + offset += NUM_BYTES_IN_DW; + value = address_space_ldq_le(as, s->cq.base_addr + offset, + MEMTXATTRS_UNSPECIFIED, &res); + if (res != MEMTX_OK) { + return CMD_STALL; + } + + rd1 = FIELD_EX64(value, MOVALL_2, RDBASE1); + if (rd1 >= s->gicv3->num_cpu) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: RDBASE1 %" PRId64 + " out of range (must be less than %d)\n", + __func__, rd1, s->gicv3->num_cpu); + return CMD_CONTINUE; + } + + offset += NUM_BYTES_IN_DW; + value = address_space_ldq_le(as, s->cq.base_addr + offset, + MEMTXATTRS_UNSPECIFIED, &res); + if (res != MEMTX_OK) { + return CMD_STALL; + } + + rd2 = FIELD_EX64(value, MOVALL_3, RDBASE2); + if (rd2 >= s->gicv3->num_cpu) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: RDBASE2 %" PRId64 + " out of range (must be less than %d)\n", + __func__, rd2, s->gicv3->num_cpu); + return CMD_CONTINUE; + } + + if (rd1 == rd2) { + /* Move to same target must succeed as a no-op */ + return CMD_CONTINUE; + } + + /* Move all pending LPIs from redistributor 1 to redistributor 2 */ + gicv3_redist_movall_lpis(&s->gicv3->cpu[rd1], &s->gicv3->cpu[rd2]); + + return CMD_CONTINUE; +} + /* * Current implementation blocks until all * commands are processed @@ -XXX,XX +XXX,XX @@ static void process_cmdq(GICv3ITSState *s) gicv3_redist_update_lpi(&s->gicv3->cpu[i]); } break; + case GITS_CMD_MOVALL: + result = process_movall(s, data, cq_offset); + break; default: break; } diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -XXX,XX +XXX,XX @@ void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level) gicv3_redist_lpi_pending(cs, irq, level); } +void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest) +{ + /* + * We must move all pending LPIs from the source redistributor + * to the destination. That is, for every pending LPI X on + * src, we must set it not-pending on src and pending on dest. + * LPIs that are already pending on dest are not cleared. + * + * If LPIs are disabled on dest this is CONSTRAINED UNPREDICTABLE: + * we choose to NOP. If LPIs are disabled on source there's nothing + * to be transferred anyway. + */ + AddressSpace *as = &src->gic->dma_as; + uint64_t idbits; + uint32_t pendt_size; + uint64_t src_baddr, dest_baddr; + int i; + + if (!(src->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || + !(dest->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { + return; + } + + idbits = MIN(FIELD_EX64(src->gicr_propbaser, GICR_PROPBASER, IDBITS), + GICD_TYPER_IDBITS); + idbits = MIN(FIELD_EX64(dest->gicr_propbaser, GICR_PROPBASER, IDBITS), + idbits); + + pendt_size = 1ULL << (idbits + 1); + src_baddr = src->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; + dest_baddr = dest->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; + + for (i = GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) { + uint8_t src_pend, dest_pend; + + address_space_read(as, src_baddr + i, MEMTXATTRS_UNSPECIFIED, + &src_pend, sizeof(src_pend)); + if (!src_pend) { + continue; + } + address_space_read(as, dest_baddr + i, MEMTXATTRS_UNSPECIFIED, + &dest_pend, sizeof(dest_pend)); + dest_pend |= src_pend; + src_pend = 0; + address_space_write(as, src_baddr + i, MEMTXATTRS_UNSPECIFIED, + &src_pend, sizeof(src_pend)); + address_space_write(as, dest_baddr + i, MEMTXATTRS_UNSPECIFIED, + &dest_pend, sizeof(dest_pend)); + } + + gicv3_redist_update_lpi(src); + gicv3_redist_update_lpi(dest); +} + void gicv3_redist_set_irq(GICv3CPUState *cs, int irq, int level) { /* Update redistributor state for a change in an external PPI input line */ -- 2.25.1 Implement the ITS MOVI command. This command specifies a (physical) LPI by DeviceID and EventID and provides a new ICID for it. The ITS must find the interrupt translation table entry for the LPI, which will tell it the old ICID. It then moves the pending state of the LPI from the old redistributor to the new one and updates the ICID field in the translation table entry. This is another GICv3 ITS command that we forgot to implement. Linux does use this one, but only if the guest powers off one of its CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-15-peter.maydell@linaro.org --- hw/intc/gicv3_internal.h | 16 ++++ hw/intc/arm_gicv3_its.c | 146 +++++++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_redist.c | 53 ++++++++++++++ 3 files changed, 215 insertions(+) diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -XXX,XX +XXX,XX @@ FIELD(GITS_TYPER, CIL, 36, 1) #define CMD_MASK 0xff /* ITS Commands */ +#define GITS_CMD_MOVI 0x01 #define GITS_CMD_INT 0x03 #define GITS_CMD_CLEAR 0x04 #define GITS_CMD_SYNC 0x05 @@ -XXX,XX +XXX,XX @@ FIELD(MAPC, RDBASE, 16, 32) FIELD(MOVALL_2, RDBASE1, 16, 36) FIELD(MOVALL_3, RDBASE2, 16, 36) +/* MOVI command fields */ +FIELD(MOVI_0, DEVICEID, 32, 32) +FIELD(MOVI_1, EVENTID, 0, 32) +FIELD(MOVI_2, ICID, 0, 16) + /* * 12 bytes Interrupt translation Table Entry size * as per Table 5.3 in GICv3 spec @@ -XXX,XX +XXX,XX @@ void gicv3_redist_update_lpi(GICv3CPUState *cs); * an incoming migration has loaded new state. */ void gicv3_redist_update_lpi_only(GICv3CPUState *cs); +/** + * gicv3_redist_mov_lpi: + * @src: source redistributor + * @dest: destination redistributor + * @irq: LPI to update + * + * Move the pending state of the specified LPI from @src to @dest, + * as required by the ITS MOVI command. + */ +void gicv3_redist_mov_lpi(GICv3CPUState *src, GICv3CPUState *dest, int irq); /** * gicv3_redist_movall_lpis: * @src: source redistributor diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -XXX,XX +XXX,XX @@ static ItsCmdResult process_movall(GICv3ITSState *s, uint64_t value, return CMD_CONTINUE; } +static ItsCmdResult process_movi(GICv3ITSState *s, uint64_t value, + uint32_t offset) +{ + AddressSpace *as = &s->gicv3->dma_as; + MemTxResult res = MEMTX_OK; + uint32_t devid, eventid, intid; + uint16_t old_icid, new_icid; + uint64_t old_cte, new_cte; + uint64_t old_rdbase, new_rdbase; + uint64_t dte; + bool dte_valid, ite_valid, cte_valid; + uint64_t num_eventids; + IteEntry ite = {}; + + devid = FIELD_EX64(value, MOVI_0, DEVICEID); + + offset += NUM_BYTES_IN_DW; + value = address_space_ldq_le(as, s->cq.base_addr + offset, + MEMTXATTRS_UNSPECIFIED, &res); + if (res != MEMTX_OK) { + return CMD_STALL; + } + eventid = FIELD_EX64(value, MOVI_1, EVENTID); + + offset += NUM_BYTES_IN_DW; + value = address_space_ldq_le(as, s->cq.base_addr + offset, + MEMTXATTRS_UNSPECIFIED, &res); + if (res != MEMTX_OK) { + return CMD_STALL; + } + new_icid = FIELD_EX64(value, MOVI_2, ICID); + + if (devid >= s->dt.num_entries) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: devid %d>=%d", + __func__, devid, s->dt.num_entries); + return CMD_CONTINUE; + } + dte = get_dte(s, devid, &res); + if (res != MEMTX_OK) { + return CMD_STALL; + } + + dte_valid = FIELD_EX64(dte, DTE, VALID); + if (!dte_valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: " + "invalid dte: %"PRIx64" for %d\n", + __func__, dte, devid); + return CMD_CONTINUE; + } + + num_eventids = 1ULL << (FIELD_EX64(dte, DTE, SIZE) + 1); + if (eventid >= num_eventids) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: eventid %d >= %" + PRId64 "\n", + __func__, eventid, num_eventids); + return CMD_CONTINUE; + } + + ite_valid = get_ite(s, eventid, dte, &old_icid, &intid, &res); + if (res != MEMTX_OK) { + return CMD_STALL; + } + + if (!ite_valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: invalid ITE\n", + __func__); + return CMD_CONTINUE; + } + + if (old_icid >= s->ct.num_entries) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid ICID 0x%x in ITE (table corrupted?)\n", + __func__, old_icid); + return CMD_CONTINUE; + } + + if (new_icid >= s->ct.num_entries) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: ICID 0x%x\n", + __func__, new_icid); + return CMD_CONTINUE; + } + + cte_valid = get_cte(s, old_icid, &old_cte, &res); + if (res != MEMTX_OK) { + return CMD_STALL; + } + if (!cte_valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: " + "invalid cte: %"PRIx64"\n", + __func__, old_cte); + return CMD_CONTINUE; + } + + cte_valid = get_cte(s, new_icid, &new_cte, &res); + if (res != MEMTX_OK) { + return CMD_STALL; + } + if (!cte_valid) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid command attributes: " + "invalid cte: %"PRIx64"\n", + __func__, new_cte); + return CMD_CONTINUE; + } + + old_rdbase = FIELD_EX64(old_cte, CTE, RDBASE); + if (old_rdbase >= s->gicv3->num_cpu) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: CTE has invalid rdbase 0x%"PRIx64"\n", + __func__, old_rdbase); + return CMD_CONTINUE; + } + + new_rdbase = FIELD_EX64(new_cte, CTE, RDBASE); + if (new_rdbase >= s->gicv3->num_cpu) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: CTE has invalid rdbase 0x%"PRIx64"\n", + __func__, new_rdbase); + return CMD_CONTINUE; + } + + if (old_rdbase != new_rdbase) { + /* Move the LPI from the old redistributor to the new one */ + gicv3_redist_mov_lpi(&s->gicv3->cpu[old_rdbase], + &s->gicv3->cpu[new_rdbase], + intid); + } + + /* Update the ICID field in the interrupt translation table entry */ + ite.itel = FIELD_DP64(ite.itel, ITE_L, VALID, 1); + ite.itel = FIELD_DP64(ite.itel, ITE_L, INTTYPE, ITE_INTTYPE_PHYSICAL); + ite.itel = FIELD_DP64(ite.itel, ITE_L, INTID, intid); + ite.itel = FIELD_DP64(ite.itel, ITE_L, DOORBELL, INTID_SPURIOUS); + ite.iteh = FIELD_DP32(ite.iteh, ITE_H, ICID, new_icid); + return update_ite(s, eventid, dte, ite) ? CMD_CONTINUE : CMD_STALL; +} + /* * Current implementation blocks until all * commands are processed @@ -XXX,XX +XXX,XX @@ static void process_cmdq(GICv3ITSState *s) gicv3_redist_update_lpi(&s->gicv3->cpu[i]); } break; + case GITS_CMD_MOVI: + result = process_movi(s, data, cq_offset); + break; case GITS_CMD_MOVALL: result = process_movall(s, data, cq_offset); break; diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index XXXXXXX..XXXXXXX 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -XXX,XX +XXX,XX @@ void gicv3_redist_process_lpi(GICv3CPUState *cs, int irq, int level) gicv3_redist_lpi_pending(cs, irq, level); } +void gicv3_redist_mov_lpi(GICv3CPUState *src, GICv3CPUState *dest, int irq) +{ + /* + * Move the specified LPI's pending state from the source redistributor + * to the destination. + * + * If LPIs are disabled on dest this is CONSTRAINED UNPREDICTABLE: + * we choose to NOP. If LPIs are disabled on source there's nothing + * to be transferred anyway. + */ + AddressSpace *as = &src->gic->dma_as; + uint64_t idbits; + uint32_t pendt_size; + uint64_t src_baddr; + uint8_t src_pend; + + if (!(src->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) || + !(dest->gicr_ctlr & GICR_CTLR_ENABLE_LPIS)) { + return; + } + + idbits = MIN(FIELD_EX64(src->gicr_propbaser, GICR_PROPBASER, IDBITS), + GICD_TYPER_IDBITS); + idbits = MIN(FIELD_EX64(dest->gicr_propbaser, GICR_PROPBASER, IDBITS), + idbits); + + pendt_size = 1ULL << (idbits + 1); + if ((irq / 8) >= pendt_size) { + return; + } + + src_baddr = src->gicr_pendbaser & R_GICR_PENDBASER_PHYADDR_MASK; + + address_space_read(as, src_baddr + (irq / 8), + MEMTXATTRS_UNSPECIFIED, &src_pend, sizeof(src_pend)); + if (!extract32(src_pend, irq % 8, 1)) { + /* Not pending on source, nothing to do */ + return; + } + src_pend &= ~(1 << (irq % 8)); + address_space_write(as, src_baddr + (irq / 8), + MEMTXATTRS_UNSPECIFIED, &src_pend, sizeof(src_pend)); + if (irq == src->hpplpi.irq) { + /* + * We just made this LPI not-pending so only need to update + * if it was previously the highest priority pending LPI + */ + gicv3_redist_update_lpi(src); + } + /* Mark it pending on the destination */ + gicv3_redist_lpi_pending(dest, irq, 1); +} + void gicv3_redist_movall_lpis(GICv3CPUState *src, GICv3CPUState *dest) { /* -- 2.25.1 From: Cédric Le Goater <clg@kaod.org> Address should be 0x1E631000 and not 0x1E641000 as initially introduced. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/838 Fixes: f25c0ae1079d ("aspeed/soc: Add AST2600 support") Suggested-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220126083520.4135713-1-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/arm/aspeed_ast2600.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index XXXXXXX..XXXXXXX 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -XXX,XX +XXX,XX @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_DEV_PWM] = 0x1E610000, [ASPEED_DEV_FMC] = 0x1E620000, [ASPEED_DEV_SPI1] = 0x1E630000, - [ASPEED_DEV_SPI2] = 0x1E641000, + [ASPEED_DEV_SPI2] = 0x1E631000, [ASPEED_DEV_EHCI1] = 0x1E6A1000, [ASPEED_DEV_EHCI2] = 0x1E6A3000, [ASPEED_DEV_MII1] = 0x1E650000, -- 2.25.1 The exception caused by an SVC instruction may be taken to AArch32 Hyp mode for two reasons: * HCR.TGE indicates that exceptions from EL0 should trap to EL2 * we were already in Hyp mode The entrypoint in the vector table to be used differs in these two cases: for an exception routed to Hyp mode from EL0, we enter at the common 0x14 "hyp trap" entrypoint. For SVC from Hyp mode to Hyp mode, we enter at the 0x08 (svc/hvc trap) entrypoint. In the v8A Arm ARM pseudocode this is done in AArch32.TakeSVCException. QEMU incorrectly routed both of these exceptions to the 0x14 entrypoint. Correct the entrypoint for SVC from Hyp to Hyp by making use of the existing logic which handles "normal entrypoint for Hyp-to-Hyp, otherwise 0x14" for traps like UNDEF and data/prefetch aborts (reproduced here since it's outside the visible context in the diff for this commit): if (arm_current_el(env) != 2 && addr < 0x14) { addr = 0x14; } Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220117131953.3936137-1-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) * separately here. * * The vector table entry used is always the 0x14 Hyp mode entry point, - * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. + * unless this is an UNDEF/SVC/HVC/abort taken from Hyp to Hyp. * The offset applied to the preferred return address is always zero * (see DDI0487C.a section G1.12.3). * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) addr = 0x04; break; case EXCP_SWI: - addr = 0x14; + addr = 0x08; break; case EXCP_BKPT: /* Fall through to prefetch abort. */ -- 2.25.1