[v2] RISC-V TIME CSR for privileged mode

[PATCH v2 0/2] RISC-V TIME CSR for privileged mode

Anup Patel posted 2 patches 4 years, 3 months ago

Diff against v1 v3
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hw/riscv/sifive_clint.c   |  1 +
target/riscv/cpu.h        |  5 +++
target/riscv/cpu_helper.c |  5 +++
target/riscv/csr.c        | 86 +++++++++++++++++++++++++++++++++++++--
4 files changed, 93 insertions(+), 4 deletions(-)

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[PATCH v2 0/2] RISC-V TIME CSR for privileged mode

Posted by Anup Patel 4 years, 3 months ago

This series adds emulation of TIME CSRs for privileged mode. With
this series, we see approximately 25+% improvement in hackbench
numbers for non-virtualized (or Host) Linux and 40+% improvement
in hackbench numbers for Guest/VM Linux.

These patches are based on mainline/alistair/riscv-hyp-ext-v0.5.1
branch of https://github.com/kvm-riscv/qemu.git and can be found
in riscv_time_csr_v2 branch of same repo.

Changes since v1:
 - Use braces for single-line if-statements

Anup Patel (2):
  target/riscv: Emulate TIME CSRs for privileged mode
  hw/riscv: Provide rdtime callback for TCG in CLINT emulation

 hw/riscv/sifive_clint.c   |  1 +
 target/riscv/cpu.h        |  5 +++
 target/riscv/cpu_helper.c |  5 +++
 target/riscv/csr.c        | 86 +++++++++++++++++++++++++++++++++++++--
 4 files changed, 93 insertions(+), 4 deletions(-)

-- 
2.17.1