[v3] RISC-V TIME CSR for privileged mode

[PATCH v3 0/2] RISC-V TIME CSR for privileged mode

Anup Patel posted 2 patches 4 years, 3 months ago

Diff against v1 v2
Download series mbox

Failed in applying to current master (apply log)

hw/riscv/sifive_clint.c         |  6 ++-
hw/riscv/sifive_e.c             |  2 +-
hw/riscv/sifive_u.c             |  2 +-
hw/riscv/spike.c                |  9 ++--
hw/riscv/virt.c                 |  2 +-
include/hw/riscv/sifive_clint.h |  3 +-
target/riscv/cpu.h              |  5 ++
target/riscv/cpu_helper.c       |  5 ++
target/riscv/csr.c              | 86 +++++++++++++++++++++++++++++++--
9 files changed, 108 insertions(+), 12 deletions(-)

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[PATCH v3 0/2] RISC-V TIME CSR for privileged mode

Posted by Anup Patel 4 years, 3 months ago

This series adds emulation of TIME CSRs for privileged mode. With
this series, we see approximately 25+% improvement in hackbench
numbers for non-virtualized (or Host) Linux and 40+% improvement
in hackbench numbers for Guest/VM Linux.

These patches are based on mainline/alistair/riscv-hyp-ext-v0.5.1
branch of https://github.com/kvm-riscv/qemu.git and can be found
in riscv_time_csr_v3 branch of same repo.

Changes since v2:
 - Register CLINT rdtime callback only for QEMU RISC-V virt machine

Changes since v1:
 - Use braces for single-line if-statements

Anup Patel (2):
  target/riscv: Emulate TIME CSRs for privileged mode
  hw/riscv: Provide rdtime callback for TCG in CLINT emulation

 hw/riscv/sifive_clint.c         |  6 ++-
 hw/riscv/sifive_e.c             |  2 +-
 hw/riscv/sifive_u.c             |  2 +-
 hw/riscv/spike.c                |  9 ++--
 hw/riscv/virt.c                 |  2 +-
 include/hw/riscv/sifive_clint.h |  3 +-
 target/riscv/cpu.h              |  5 ++
 target/riscv/cpu_helper.c       |  5 ++
 target/riscv/csr.c              | 86 +++++++++++++++++++++++++++++++--
 9 files changed, 108 insertions(+), 12 deletions(-)

-- 
2.17.1

Re: [PATCH v3 0/2] RISC-V TIME CSR for privileged mode

Posted by Palmer Dabbelt 4 years, 2 months ago

On Sun, 02 Feb 2020 05:42:15 PST (-0800), Anup Patel wrote:
> This series adds emulation of TIME CSRs for privileged mode. With
> this series, we see approximately 25+% improvement in hackbench
> numbers for non-virtualized (or Host) Linux and 40+% improvement
> in hackbench numbers for Guest/VM Linux.
>
> These patches are based on mainline/alistair/riscv-hyp-ext-v0.5.1
> branch of https://github.com/kvm-riscv/qemu.git and can be found
> in riscv_time_csr_v3 branch of same repo.
>
> Changes since v2:
>  - Register CLINT rdtime callback only for QEMU RISC-V virt machine
>
> Changes since v1:
>  - Use braces for single-line if-statements
>
> Anup Patel (2):
>   target/riscv: Emulate TIME CSRs for privileged mode
>   hw/riscv: Provide rdtime callback for TCG in CLINT emulation
>
>  hw/riscv/sifive_clint.c         |  6 ++-
>  hw/riscv/sifive_e.c             |  2 +-
>  hw/riscv/sifive_u.c             |  2 +-
>  hw/riscv/spike.c                |  9 ++--
>  hw/riscv/virt.c                 |  2 +-
>  include/hw/riscv/sifive_clint.h |  3 +-
>  target/riscv/cpu.h              |  5 ++
>  target/riscv/cpu_helper.c       |  5 ++
>  target/riscv/csr.c              | 86 +++++++++++++++++++++++++++++++--
>  9 files changed, 108 insertions(+), 12 deletions(-)

This is queued for the next pull request.

Thanks!