Series comparison

-[PULL 0/7] target-arm queue
+[PULL 00/24] target-arm queue
-Target-arm queue for rc2 -- just some minor bugfixes.
+Hi; here's the latest round of arm patches. I have included also
 my patchset for the RTC devices to avoid keeping time_t and
 time_t diffs in 32-bit variables.
 thanks
 -- PMM
-The following changes since commit 6e5d4999c761ffa082f60d72a14e5c953515b417:
+The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:
-  Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-11-19' into staging (2019-11-19 11:29:01 +0000)
+  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191119
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831
-for you to fetch changes up to 04c9c81b8fa2ee33f59a26265700fae6fc646062:
+for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:
-  target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY (2019-11-19 13:20:28 +0000)
+  hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
+ * Some of the preliminary patches for Cortex-A710 support
- * Relax r13 restriction for ldrex/strex for v8.0
+ * i.MX7 and i.MX6UL refactoring
- * Do not reject rt == rt2 for strexd
+ * Implement SRC device for i.MX7
- * net/cadence_gem: Set PHY autonegotiation restart status
+ * Catch illegal-exception-return from EL3 with bad NSE/NS
- * ssi: xilinx_spips: Skip spi bus update for a few register writes
+ * Use 64-bit offsets for holding time_t differences in RTC devices
- * pl031: Expose RTCICR as proper WC register
+ * Model correct number of MPU regions for an505, an521, an524 boards
 ----------------------------------------------------------------
-Alexander Graf (1):
+Alex Bennée (1):
-      pl031: Expose RTCICR as proper WC register
+      target/arm: properly document FEAT_CRC32
-Linus Ziegert (1):
+Jean-Christophe Dubois (6):
-      net/cadence_gem: Set PHY autonegotiation restart status
+      Remove i.MX7 IOMUX GPR device from i.MX6UL
       Refactor i.MX6UL processor code
       Add i.MX6UL missing devices.
       Refactor i.MX7 processor code
       Add i.MX7 missing TZ devices and memory regions
       Add i.MX7 SRC device implementation
-Richard Henderson (4):
+Peter Maydell (8):
-      target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller
+      target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
-      target/arm: Do not reject rt == rt2 for strexd
+      hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
-      target/arm: Relax r13 restriction for ldrex/strex for v8.0
+      hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
-      target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
+      hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
       rtc: Use time_t for passing and returning time offsets
       target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
       hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
       hw/arm: Set number of MPU regions correctly for an505, an521, an524
-Sai Pavan Boddu (1):
+Richard Henderson (9):
-      ssi: xilinx_spips: Skip spi bus update for a few register writes
+      target/arm: Reduce dcz_blocksize to uint8_t
       target/arm: Allow cpu to configure GM blocksize
       target/arm: Support more GM blocksizes
       target/arm: When tag memory is not present, set MTE=1
       target/arm: Introduce make_ccsidr64
       target/arm: Apply access checks to neoverse-n1 special registers
       target/arm: Apply access checks to neoverse-v1 special registers
       target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
       target/arm: Implement FEAT_HPDS2 as a no-op
- target/arm/cpu.h       |   5 +--
+ docs/system/arm/emulation.rst  |   2 +
- hw/net/cadence_gem.c   |   9 ++--
+ include/hw/arm/armsse.h        |   5 +
- hw/rtc/pl031.c         |   6 +--
+ include/hw/arm/armv7m.h        |   8 +
- hw/ssi/xilinx_spips.c  |  22 ++++++++--
+ include/hw/arm/fsl-imx6ul.h    | 158 ++++++++++++++++---
- target/arm/cpu64.c     |  15 -------
+ include/hw/arm/fsl-imx7.h      | 338 ++++++++++++++++++++++++++++++-----------
- target/arm/helper.c    |   9 +++-
+ include/hw/misc/imx7_src.h     |  66 ++++++++
- target/arm/m_helper.c  | 114 ++++++++++++++++++++++++++++++-------------------
+ include/hw/rtc/aspeed_rtc.h    |   2 +-
- target/arm/translate.c |  14 +++---
+ include/sysemu/rtc.h           |   4 +-
-files changed, 113 insertions(+), 81 deletions(-)
+ target/arm/cpregs.h            |   2 +
  target/arm/cpu.h               |   5 +-
  target/arm/internals.h         |   6 -
  target/arm/tcg/translate.h     |   2 +
  hw/arm/armsse.c                |  16 ++
  hw/arm/armv7m.c                |  21 +++
  hw/arm/fsl-imx6ul.c            | 174 +++++++++++++--------
  hw/arm/fsl-imx7.c              | 201 +++++++++++++++++++-----
  hw/arm/mps2-tz.c               |  29 ++++
  hw/misc/imx7_src.c             | 276 +++++++++++++++++++++++++++++++++
  hw/rtc/aspeed_rtc.c            |   5 +-
  hw/rtc/m48t59.c                |   2 +-
  hw/rtc/twl92230.c              |   4 +-
  softmmu/rtc.c                  |   4 +-
  target/arm/cpu.c               | 207 ++++++++++++++-----------
  target/arm/helper.c            |  15 +-
  target/arm/tcg/cpu32.c         |   2 +-
  target/arm/tcg/cpu64.c         | 102 +++++++++----
  target/arm/tcg/helper-a64.c    |   9 ++
  target/arm/tcg/mte_helper.c    |  90 ++++++++---
  target/arm/tcg/translate-a64.c |   5 +-
  hw/misc/meson.build            |   1 +
  hw/misc/trace-events           |   4 +
 files changed, 1393 insertions(+), 372 deletions(-)
  create mode 100644 include/hw/misc/imx7_src.h
  create mode 100644 hw/misc/imx7_src.c

-[PULL 7/7] target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
+[PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t
 From: Richard Henderson <richard.henderson@linaro.org>
-Simply moving the non-stub helper_v7m_mrs/msr outside of
+This value is only 4 bits wide.
 !CONFIG_USER_ONLY is not an option, because of all of the
 other system-mode helpers that are called.
-But we can split out a few subroutines to handle the few
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 EL0 accessible registers without duplicating code.
 Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20191118194916.3670-1-richard.henderson@linaro.org
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-[PMM: deleted now-redundant comment; added a default case
+Message-id: 20230811214031.171020-2-richard.henderson@linaro.org
  to switch in v7m_msr helper]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h      |   2 +
+ target/arm/cpu.h | 3 ++-
- target/arm/m_helper.c | 114 ++++++++++++++++++++++++++----------------
+file changed, 2 insertions(+), 1 deletion(-)
 files changed, 73 insertions(+), 43 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
-     if (mask & XPSR_GE) {
+     bool prop_lpa2;
-         env->GE = (val & XPSR_GE) >> 16;
-     }
+     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
-+#ifndef CONFIG_USER_ONLY
+-    uint32_t dcz_blocksize;
-     if (mask & XPSR_T) {
++    uint8_t dcz_blocksize;
          env->thumb = ((val & XPSR_T) != 0);
      }
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
          /* Note that this only happens on exception exit */
          write_v7m_exception(env, val & XPSR_EXCP);
      }
 +#endif
  }
  #define HCR_VM        (1ULL << 0)
 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/m_helper.c
 +++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
  #include "exec/cpu_ldst.h"
  #endif
 +static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
 +                         uint32_t reg, uint32_t val)
 +{
 +    /* Only APSR is actually writable */
 +    if (!(reg & 4)) {
 +        uint32_t apsrmask = 0;
 +
-+        if (mask & 8) {
+     uint64_t rvbar_prop; /* Property/input signals.  */
-+            apsrmask |= XPSR_NZCV | XPSR_Q;
-+        }
+     /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
 +        if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
 +            apsrmask |= XPSR_GE;
 +        }
 +        xpsr_write(env, val, apsrmask);
 +    }
 +}
 +
 +static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
 +{
 +    uint32_t mask = 0;
 +
 +    if ((reg & 1) && el) {
 +        mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
 +    }
 +    if (!(reg & 4)) {
 +        mask |= XPSR_NZCV | XPSR_Q; /* APSR */
 +        if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
 +            mask |= XPSR_GE;
 +        }
 +    }
 +    /* EPSR reads as zero */
 +    return xpsr_read(env) & mask;
 +}
 +
 +static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
 +{
 +    uint32_t value = env->v7m.control[secure];
 +
 +    if (!secure) {
 +        /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
 +        value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK;
 +    }
 +    return value;
 +}
 +
  #ifdef CONFIG_USER_ONLY
 -/* These should probably raise undefined insn exceptions.  */
 -void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
 +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
  {
 -    ARMCPU *cpu = env_archcpu(env);
 +    uint32_t mask = extract32(maskreg, 8, 4);
 +    uint32_t reg = extract32(maskreg, 0, 8);
 -    cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
 +    switch (reg) {
 +    case 0 ... 7: /* xPSR sub-fields */
 +        v7m_msr_xpsr(env, mask, reg, val);
 +        break;
 +    case 20: /* CONTROL */
 +        /* There are no sub-fields that are actually writable from EL0. */
 +        break;
 +    default:
 +        /* Unprivileged writes to other registers are ignored */
 +        break;
 +    }
  }
  uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
  {
 -    ARMCPU *cpu = env_archcpu(env);
 -
 -    cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
 -    return 0;
 +    switch (reg) {
 +    case 0 ... 7: /* xPSR sub-fields */
 +        return v7m_mrs_xpsr(env, reg, 0);
 +    case 20: /* CONTROL */
 +        return v7m_mrs_control(env, 0);
 +    default:
 +        /* Unprivileged reads others as zero.  */
 +        return 0;
 +    }
  }
  void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
  uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
  {
 -    uint32_t mask;
      unsigned el = arm_current_el(env);
      /* First handle registers which unprivileged can read */
 -
      switch (reg) {
      case 0 ... 7: /* xPSR sub-fields */
 -        mask = 0;
 -        if ((reg & 1) && el) {
 -            mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
 -        }
 -        if (!(reg & 4)) {
 -            mask |= XPSR_NZCV | XPSR_Q; /* APSR */
 -            if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
 -                mask |= XPSR_GE;
 -            }
 -        }
 -        /* EPSR reads as zero */
 -        return xpsr_read(env) & mask;
 -        break;
 +        return v7m_mrs_xpsr(env, reg, el);
      case 20: /* CONTROL */
 -    {
 -        uint32_t value = env->v7m.control[env->v7m.secure];
 -        if (!env->v7m.secure) {
 -            /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
 -            value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK;
 -        }
 -        return value;
 -    }
 +        return v7m_mrs_control(env, env->v7m.secure);
      case 0x94: /* CONTROL_NS */
          /*
           * We have to handle this here because unprivileged Secure code
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
      switch (reg) {
      case 0 ... 7: /* xPSR sub-fields */
 -        /* only APSR is actually writable */
 -        if (!(reg & 4)) {
 -            uint32_t apsrmask = 0;
 -
 -            if (mask & 8) {
 -                apsrmask |= XPSR_NZCV | XPSR_Q;
 -            }
 -            if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
 -                apsrmask |= XPSR_GE;
 -            }
 -            xpsr_write(env, val, apsrmask);
 -        }
 +        v7m_msr_xpsr(env, mask, reg, val);
          break;
      case 8: /* MSP */
          if (v7m_using_psp(env)) {
 --
-.20.1
+.34.1

-[PULL 2/7] target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller
+[PULL 02/24] target/arm: Allow cpu to configure GM blocksize
 From: Richard Henderson <richard.henderson@linaro.org>
-Coverity reports, in sve_zcr_get_valid_len,
+Previously we hard-coded the blocksize with GMID_EL1_BS.
+But the value we choose for -cpu max does not match the
-"Subtract operation overflows on operands
+value that cortex-a710 uses.
-arm_cpu_vq_map_next_smaller(cpu, start_vq + 1U) and 1U"
+Mirror the way we handle dcz_blocksize.
-First, the aarch32 stub version of arm_cpu_vq_map_next_smaller,
-returning 0, does exactly what Coverity reports.  Remove it.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Second, the aarch64 version of arm_cpu_vq_map_next_smaller has
 a set of asserts, but they don't cover the case in question.
 Further, there is a fair amount of extra arithmetic needed to
 convert from the 0-based zcr register, to the 1-base vq form,
 to the 0-based bitmap, and back again.  This can be simplified
 by leaving the value in the 0-based form.
 Finally, use test_bit to simplify the common case, where the
 length in the zcr registers is in fact a supported length.
 Reported-by: Coverity (CID 1407217)
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Andrew Jones <drjones@redhat.com>
+Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
 Message-id: 20191118091414.19440-1-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h    |  3 ---
+ target/arm/cpu.h               |  2 ++
- target/arm/cpu64.c  | 15 ---------------
+ target/arm/internals.h         |  6 -----
- target/arm/helper.c |  9 +++++++--
+ target/arm/tcg/translate.h     |  2 ++
-files changed, 7 insertions(+), 20 deletions(-)
+ target/arm/helper.c            | 11 +++++---
  target/arm/tcg/cpu64.c         |  1 +
  target/arm/tcg/mte_helper.c    | 46 ++++++++++++++++++++++------------
  target/arm/tcg/translate-a64.c |  5 ++--
 files changed, 45 insertions(+), 28 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ typedef struct {
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
- #ifdef TARGET_AARCH64
- # define ARM_MAX_VQ    16
+     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
- void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
+     uint8_t dcz_blocksize;
--uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);
++    /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
- #else
++    uint8_t gm_blocksize;
- # define ARM_MAX_VQ    1
- static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
+     uint64_t rvbar_prop; /* Property/input signals.  */
--static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
--{ return 0; }
+diff --git a/target/arm/internals.h b/target/arm/internals.h
- #endif
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/internals.h
- typedef struct ARMVectorReg {
++++ b/target/arm/internals.h
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
+ #endif /* !CONFIG_USER_ONLY */
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
+-/*
-     cpu->sve_max_vq = max_vq;
+- * The log2 of the words in the tag block, for GMID_EL1.BS.
- }
+- * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
+- */
--uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
+-#define GMID_EL1_BS  6
 -{
 -    uint32_t bitnum;
 -
--    /*
+ /*
--     * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
+  * SVE predicates are 1/8 the size of SVE vectors, and cannot use
--     * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
+  * the same simd_desc() encoding due to restrictions on size.
--     * function always returns the next smaller than the input.
+diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
--     */
+index XXXXXXX..XXXXXXX 100644
--    assert(vq && vq <= ARM_MAX_VQ + 1);
+--- a/target/arm/tcg/translate.h
--
++++ b/target/arm/tcg/translate.h
--    bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
+@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
--    return bitnum == vq - 1 ? 0 : bitnum + 1;
+     int8_t btype;
--}
+     /* A copy of cpu->dcz_blocksize. */
--
+     uint8_t dcz_blocksize;
- static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
++    /* A copy of cpu->gm_blocksize. */
-                                    void *opaque, Error **errp)
++    uint8_t gm_blocksize;
- {
+     /* True if this page is guarded.  */
      bool guarded_page;
      /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
+       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
- static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
+       .access = PL1_RW, .accessfn = access_mte,
        .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
 -    { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
 -      .access = PL1_R, .accessfn = access_aa64_tid5,
 -      .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
      { .name = "TCO", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
        .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
       * then define only a RAZ/WI version of PSTATE.TCO.
       */
      if (cpu_isar_feature(aa64_mte, cpu)) {
 +        ARMCPRegInfo gmid_reginfo = {
 +            .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
 +            .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
 +            .access = PL1_R, .accessfn = access_aa64_tid5,
 +            .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
 +        };
 +        define_one_arm_cp_reg(cpu, &gmid_reginfo);
          define_arm_cp_regs(cpu, mte_reginfo);
          define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
      } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/cpu64.c
 +++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
      cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
      cpu->dcz_blocksize = 7; /*  512 bytes */
  #endif
 +    cpu->gm_blocksize = 6;  /*  256 bytes */
      cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
      cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/mte_helper.c
 +++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
      }
  }
 -#define LDGM_STGM_SIZE  (4 << GMID_EL1_BS)
 -
  uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
  {
--    uint32_t start_vq = (start_len & 0xf) + 1;
+     int mmu_idx = cpu_mmu_index(env, false);
-+    uint32_t end_len;
+     uintptr_t ra = GETPC();
++    int gm_bs = env_archcpu(env)->gm_blocksize;
--    return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1;
++    int gm_bs_bytes = 4 << gm_bs;
-+    end_len = start_len &= 0xf;
+     void *tag_mem;
-+    if (!test_bit(start_len, cpu->sve_vq_map)) {
-+        end_len = find_last_bit(cpu->sve_vq_map, start_len);
+-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
-+        assert(end_len < start_len);
++    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
      /* Trap if accessing an invalid page.  */
      tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
 +                                 gm_bs_bytes, MMU_DATA_LOAD,
 +                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
      /* The tag is squashed to zero if the page does not support tags.  */
      if (!tag_mem) {
          return 0;
      }
 -    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
      /*
 -     * We are loading 64-bits worth of tags.  The ordering of elements
 -     * within the word corresponds to a 64-bit little-endian operation.
 +     * The ordering of elements within the word corresponds to
 +     * a little-endian operation.
       */
 -    return ldq_le_p(tag_mem);
 +    switch (gm_bs) {
 +    case 6:
 +        /* 256 bytes -> 16 tags -> 64 result bits */
 +        return ldq_le_p(tag_mem);
 +    default:
 +        /* cpu configured with unsupported gm blocksize. */
 +        g_assert_not_reached();
 +    }
-+    return end_len;
  }
- /*
+ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
  {
      int mmu_idx = cpu_mmu_index(env, false);
      uintptr_t ra = GETPC();
 +    int gm_bs = env_archcpu(env)->gm_blocksize;
 +    int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 -    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
 +    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
      /* Trap if accessing an invalid page.  */
      tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
 -                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
 +                                 gm_bs_bytes, MMU_DATA_LOAD,
 +                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
      /*
       * Tag store only happens if the page support tags,
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
          return;
      }
 -    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
      /*
 -     * We are storing 64-bits worth of tags.  The ordering of elements
 -     * within the word corresponds to a 64-bit little-endian operation.
 +     * The ordering of elements within the word corresponds to
 +     * a little-endian operation.
       */
 -    stq_le_p(tag_mem, val);
 +    switch (gm_bs) {
 +    case 6:
 +        stq_le_p(tag_mem, val);
 +        break;
 +    default:
 +        /* cpu configured with unsupported gm blocksize. */
 +        g_assert_not_reached();
 +    }
  }
  void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/translate-a64.c
 +++ b/target/arm/tcg/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
          gen_helper_stgm(cpu_env, addr, tcg_rt);
      } else {
          MMUAccessType acc = MMU_DATA_STORE;
 -        int size = 4 << GMID_EL1_BS;
 +        int size = 4 << s->gm_blocksize;
          clean_addr = clean_data_tbi(s, addr);
          tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
          gen_helper_ldgm(tcg_rt, cpu_env, addr);
      } else {
          MMUAccessType acc = MMU_DATA_LOAD;
 -        int size = 4 << GMID_EL1_BS;
 +        int size = 4 << s->gm_blocksize;
          clean_addr = clean_data_tbi(s, addr);
          tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
      dc->cp_regs = arm_cpu->cp_regs;
      dc->features = env->features;
      dc->dcz_blocksize = arm_cpu->dcz_blocksize;
 +    dc->gm_blocksize = arm_cpu->gm_blocksize;
  #ifdef CONFIG_USER_ONLY
      /* In sve_probe_page, we assume TBI is enabled. */
 --
-.20.1
+.34.1

-[PULL 5/7] target/arm: Do not reject rt == rt2 for strexd
+[PULL 03/24] target/arm: Support more GM blocksizes
 From: Richard Henderson <richard.henderson@linaro.org>
-There was too much cut and paste between ldrexd and strexd,
+Support all of the easy GM block sizes.
-as ldrexd does prohibit two output registers the same.
+Use direct memory operations, since the pointers are aligned.
-Fixes: af288228995
+While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
-Reported-by: Michael Goffioul <michael.goffioul@gmail.com>
+an atomic store of one nibble.  This is not difficult, but there
 is also no point in supporting it until required.
 Note that cortex-a710 sets GM blocksize to match its cacheline
 size of 64 bytes.  I expect many implementations will also
 match the cacheline, which makes 16 bytes very unlikely.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20191117090621.32425-2-richard.henderson@linaro.org
-Reviewed-by: Robert Foley <robert.foley@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.c | 2 +-
+ target/arm/cpu.c            | 18 +++++++++---
-file changed, 1 insertion(+), 1 deletion(-)
+ target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
 files changed, 62 insertions(+), 12 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/target/arm/cpu.c
-+++ b/target/arm/translate.c
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-         || (s->thumb && (a->rd == 13 || a->rt == 13))
+                                        ID_PFR1, VIRTUALIZATION, 0);
-         || (mop == MO_64
+     }
-             && (a->rt2 == 15
--                || a->rd == a->rt2 || a->rt == a->rt2
++    if (cpu_isar_feature(aa64_mte, cpu)) {
-+                || a->rd == a->rt2
++        /*
-                 || (s->thumb && a->rt2 == 13)))) {
++         * The architectural range of GM blocksize is 2-6, however qemu
-         unallocated_encoding(s);
++         * doesn't support blocksize of 2 (see HELPER(ldgm)).
-         return true;
++         */
 +        if (tcg_enabled()) {
 +            assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
 +        }
 +
  #ifndef CONFIG_USER_ONLY
 -    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
          /*
           * Disable the MTE feature bits if we do not have tag-memory
           * provided by the machine.
           */
 -        cpu->isar.id_aa64pfr1 =
 -            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
 -    }
 +        if (cpu->tag_memory == NULL) {
 +            cpu->isar.id_aa64pfr1 =
 +                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
 +        }
  #endif
 +    }
      if (tcg_enabled()) {
          /*
 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/mte_helper.c
 +++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
      int gm_bs = env_archcpu(env)->gm_blocksize;
      int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 +    uint64_t ret;
 +    int shift;
      ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
      /*
       * The ordering of elements within the word corresponds to
 -     * a little-endian operation.
 +     * a little-endian operation.  Computation of shift comes from
 +     *
 +     *     index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
 +     *     data<index*4+3:index*4> = tag
 +     *
 +     * Because of the alignment of ptr above, BS=6 has shift=0.
 +     * All memory operations are aligned.  Defer support for BS=2,
 +     * requiring insertion or extraction of a nibble, until we
 +     * support a cpu that requires it.
       */
      switch (gm_bs) {
 +    case 3:
 +        /* 32 bytes -> 2 tags -> 8 result bits */
 +        ret = *(uint8_t *)tag_mem;
 +        break;
 +    case 4:
 +        /* 64 bytes -> 4 tags -> 16 result bits */
 +        ret = cpu_to_le16(*(uint16_t *)tag_mem);
 +        break;
 +    case 5:
 +        /* 128 bytes -> 8 tags -> 32 result bits */
 +        ret = cpu_to_le32(*(uint32_t *)tag_mem);
 +        break;
      case 6:
          /* 256 bytes -> 16 tags -> 64 result bits */
 -        return ldq_le_p(tag_mem);
 +        return cpu_to_le64(*(uint64_t *)tag_mem);
      default:
 -        /* cpu configured with unsupported gm blocksize. */
 +        /*
 +         * CPU configured with unsupported/invalid gm blocksize.
 +         * This is detected early in arm_cpu_realizefn.
 +         */
          g_assert_not_reached();
      }
 +    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
 +    return ret << shift;
  }
  void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
      int gm_bs = env_archcpu(env)->gm_blocksize;
      int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 +    int shift;
      ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
          return;
      }
 -    /*
 -     * The ordering of elements within the word corresponds to
 -     * a little-endian operation.
 -     */
 +    /* See LDGM for comments on BS and on shift.  */
 +    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
 +    val >>= shift;
      switch (gm_bs) {
 +    case 3:
 +        /* 32 bytes -> 2 tags -> 8 result bits */
 +        *(uint8_t *)tag_mem = val;
 +        break;
 +    case 4:
 +        /* 64 bytes -> 4 tags -> 16 result bits */
 +        *(uint16_t *)tag_mem = cpu_to_le16(val);
 +        break;
 +    case 5:
 +        /* 128 bytes -> 8 tags -> 32 result bits */
 +        *(uint32_t *)tag_mem = cpu_to_le32(val);
 +        break;
      case 6:
 -        stq_le_p(tag_mem, val);
 +        /* 256 bytes -> 16 tags -> 64 result bits */
 +        *(uint64_t *)tag_mem = cpu_to_le64(val);
          break;
      default:
          /* cpu configured with unsupported gm blocksize. */
 --
-.20.1
+.34.1

-[PULL 6/7] target/arm: Relax r13 restriction for ldrex/strex for v8.0
+[PULL 04/24] target/arm: When tag memory is not present, set MTE=1
 From: Richard Henderson <richard.henderson@linaro.org>
-Armv8-A removes UNPREDICTABLE for R13 for these cases.
+When the cpu support MTE, but the system does not, reduce cpu
 support to user instructions at EL0 instead of completely
 disabling MTE.  If we encounter a cpu implementation which does
 something else, we can revisit this setting.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20191117090621.32425-3-richard.henderson@linaro.org
-[PMM: changed ENABLE_ARCH_8 checks to check a new bool 'v8a',
- since these cases are still UNPREDICTABLE for v8M]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.c | 12 ++++++++----
+ target/arm/cpu.c | 7 ++++---
-file changed, 8 insertions(+), 4 deletions(-)
+file changed, 4 insertions(+), 3 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/target/arm/cpu.c
-+++ b/target/arm/translate.c
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static bool trans_SWPB(DisasContext *s, arg_SWP *a)
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
- static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
- {
+ #ifndef CONFIG_USER_ONLY
-     TCGv_i32 addr;
+         /*
-+    /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
+-         * Disable the MTE feature bits if we do not have tag-memory
-+    bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
+-         * provided by the machine.
++         * If we do not have tag-memory provided by the machine,
-     /* We UNDEF for these UNPREDICTABLE cases.  */
++         * reduce MTE support to instructions enabled at EL0.
-     if (a->rd == 15 || a->rn == 15 || a->rt == 15
++         * This matches Cortex-A710 BROADCASTMTE input being LOW.
-         || a->rd == a->rn || a->rd == a->rt
+          */
--        || (s->thumb && (a->rd == 13 || a->rt == 13))
+         if (cpu->tag_memory == NULL) {
-+        || (!v8a && s->thumb && (a->rd == 13 || a->rt == 13))
+             cpu->isar.id_aa64pfr1 =
-         || (mop == MO_64
+-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
-             && (a->rt2 == 15
++                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
-                 || a->rd == a->rt2
+         }
--                || (s->thumb && a->rt2 == 13)))) {
+ #endif
 +                || (!v8a && s->thumb && a->rt2 == 13)))) {
          unallocated_encoding(s);
          return true;
      }
@@ -XXX,XX +XXX,XX @@ static bool trans_STLH(DisasContext *s, arg_STL *a)
  static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq)
  {
      TCGv_i32 addr;
 +    /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
 +    bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
      /* We UNDEF for these UNPREDICTABLE cases.  */
      if (a->rn == 15 || a->rt == 15
 -        || (s->thumb && a->rt == 13)
 +        || (!v8a && s->thumb && a->rt == 13)
          || (mop == MO_64
              && (a->rt2 == 15 || a->rt == a->rt2
 -                || (s->thumb && a->rt2 == 13)))) {
 +                || (!v8a && s->thumb && a->rt2 == 13)))) {
          unallocated_encoding(s);
          return true;
      }
 --
-.20.1
+.34.1

-New patch
+[PULL 05/24] target/arm: Introduce make_ccsidr64
+From: Richard Henderson <richard.henderson@linaro.org>
+Do not hard-code the constants for Neoverse V1.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
+file changed, 32 insertions(+), 16 deletions(-)
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/module.h"
+ #include "qapi/visitor.h"
+ #include "hw/qdev-properties.h"
++#include "qemu/units.h"
+ #include "internals.h"
+ #include "cpregs.h"
++static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
++                              unsigned cachesize)
++{
++    unsigned lg_linesize = ctz32(linesize);
++    unsigned sets;
++
++    /*
++     * The 64-bit CCSIDR_EL1 format is:
++     *   [55:32] number of sets - 1
++     *   [23:3]  associativity - 1
++     *   [2:0]   log2(linesize) - 4
++     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
++     */
++    assert(assoc != 0);
++    assert(is_power_of_2(linesize));
++    assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
++
++    /* sets * associativity * linesize == cachesize. */
++    sets = cachesize / (assoc * linesize);
++    assert(cachesize % (assoc * linesize) == 0);
++
++    return ((uint64_t)(sets - 1) << 32)
++         | ((assoc - 1) << 3)
++         | (lg_linesize - 4);
++}
++
+ static void aarch64_a35_initfn(Object *obj)
+ {
+     ARMCPU *cpu = ARM_CPU(obj);
+@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
+      * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
+      * but also says it implements CCIDX, which means they should be
+      * 64-bit format. So we here use values which are based on the textual
+-     * information in chapter 2 of the TRM (and on the fact that
+-     * sets * associativity * linesize == cachesize).
+-     *
+-     * The 64-bit CCSIDR_EL1 format is:
+-     *   [55:32] number of sets - 1
+-     *   [23:3]  associativity - 1
+-     *   [2:0]   log2(linesize) - 4
+-     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
+-     *
+-     * L1: 4-way set associative 64-byte line size, total size 64K,
+-     * so sets is 256.
++     * information in chapter 2 of the TRM:
+      *
++     * L1: 4-way set associative 64-byte line size, total size 64K.
+      * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
+-     * We pick 1MB, so this has 2048 sets.
+-     *
+      * L3: No L3 (this matches the CLIDR_EL1 value).
+      */
+-    cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
+-    cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
+-    cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
++    cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
++    cpu->ccsidr[1] = cpu->ccsidr[0];                 /* L1 icache */
++    cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB);  /* L2 cache */
+     /* From 3.2.115 SCTLR_EL3 */
+     cpu->reset_sctlr = 0x30c50838;
+--
+.34.1

-New patch
+[PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers
+From: Richard Henderson <richard.henderson@linaro.org>
+Access to many of the special registers is enabled or disabled
+by ACTLR_EL[23], which we implement as constant 0, which means
+that all writes outside EL3 should trap.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpregs.h    |  2 ++
+ target/arm/helper.c    |  4 ++--
+ target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
+files changed, 41 insertions(+), 11 deletions(-)
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpregs.h
++++ b/target/arm/cpregs.h
+@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+ #endif
++CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
++
+ #endif /* TARGET_ARM_CPREGS_H */
+diff --git a/target/arm/helper.c b/target/arm/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/helper.c
++++ b/target/arm/helper.c
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
+ }
+ /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM.  */
+-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
+-                                      bool isread)
++CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
++                               bool isread)
+ {
+     if (arm_current_el(env) == 1) {
+         uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
+     /* TODO:  Add A64FX specific HPC extension registers */
+ }
++static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
++                                     bool read)
++{
++    if (!read) {
++        int el = arm_current_el(env);
++
++        /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
++        if (el < 2 && arm_is_el2_enabled(env)) {
++            return CP_ACCESS_TRAP_EL2;
++        }
++        /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
++        if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
++            return CP_ACCESS_TRAP_EL3;
++        }
++    }
++    return CP_ACCESS_OK;
++}
++
+ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+     { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      /* Traps and enables are the same as for TCR_EL1. */
++      .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
+     { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
+       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     /*
+      * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
+      * (and in particular its system registers).
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
+     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
++      .accessfn = access_actlr_w },
+     { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
+       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+     { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+ };
+ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
+--
+.34.1

-New patch
+[PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers
+From: Richard Henderson <richard.henderson@linaro.org>
+There is only one additional EL1 register modeled, which
+also needs to use access_actlr_w.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/tcg/cpu64.c | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
+ static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
+     { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
+       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+--
+.34.1

-New patch
+[PULL 08/24] target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
+From: Richard Henderson <richard.henderson@linaro.org>
+Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
+external to the cpu, which is out of scope for QEMU.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.c | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+         /* FEAT_SPE (Statistical Profiling Extension) */
+         cpu->isar.id_aa64dfr0 =
+             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
++        /* FEAT_TRBE (Trace Buffer Extension) */
++        cpu->isar.id_aa64dfr0 =
++            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
+         /* FEAT_TRF (Self-hosted Trace Extension) */
+         cpu->isar.id_aa64dfr0 =
+             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
+--
+.34.1

-New patch
+[PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op
+From: Richard Henderson <richard.henderson@linaro.org>
+This feature allows the operating system to set TCR_ELx.HWU*
+to allow the implementation to use the PBHA bits from the
+block and page descriptors for for IMPLEMENTATION DEFINED
+purposes.  Since QEMU has no need to use these bits, we may
+simply ignore them.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ docs/system/arm/emulation.rst | 1 +
+ target/arm/tcg/cpu32.c        | 2 +-
+ target/arm/tcg/cpu64.c        | 2 +-
+files changed, 3 insertions(+), 2 deletions(-)
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/emulation.rst
++++ b/docs/system/arm/emulation.rst
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+ - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
+ - FEAT_HCX (Support for the HCRX_EL2 register)
+ - FEAT_HPDS (Hierarchical permission disables)
++- FEAT_HPDS2 (Translation table page-based hardware attributes)
+ - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
+ - FEAT_IDST (ID space trap handling)
+ - FEAT_IESB (Implicit error synchronization event)
+diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu32.c
++++ b/target/arm/tcg/cpu32.c
+@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
+     cpu->isar.id_mmfr3 = t;
+     t = cpu->isar.id_mmfr4;
+-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
++    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
+     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
+     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
+     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
+     t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
+     t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
+-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
++    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2);     /* FEAT_HPDS2 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
+     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
+--
+.34.1

-[PULL 4/7] net/cadence_gem: Set PHY autonegotiation restart status
+[PULL 10/24] target/arm: properly document FEAT_CRC32
-From: Linus Ziegert <linus.ziegert+qemu@holoplot.com>
+From: Alex Bennée <alex.bennee@linaro.org>
-The Linux kernel PHY driver sets AN_RESTART in the BMCR of the
+This is a mandatory feature for Armv8.1 architectures but we don't
-PHY when autonegotiation is started.
+state the feature clearly in our emulation list. Also include
-Recently the kernel started to read back the PHY's AN_RESTART
+FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
 bit and now checks whether the autonegotiation is complete and
 the bit was cleared [1]. Otherwise the link status is down.
-The emulated PHY needs to clear AN_RESTART immediately to inform
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-the kernel driver about the completion of autonegotiation phase.
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
 [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c36757eb9dee
 Signed-off-by: Linus Ziegert <linus.ziegert+qemu@holoplot.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Message-id: 20191104181604.21943-1-linus.ziegert+qemu@holoplot.com
 Cc: qemu-stable@nongnu.org
+Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
+[PMM: pluralize 'instructions' in docs]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/net/cadence_gem.c | 9 +++++----
+ docs/system/arm/emulation.rst | 1 +
-file changed, 5 insertions(+), 4 deletions(-)
+ target/arm/tcg/cpu64.c        | 2 +-
 files changed, 2 insertions(+), 1 deletion(-)
-diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/hw/net/cadence_gem.c
+--- a/docs/system/arm/emulation.rst
-+++ b/hw/net/cadence_gem.c
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
- #define PHY_REG_EXT_PHYSPCFC_ST   27
+ - FEAT_BBM at level 2 (Translation table break-before-make levels)
- #define PHY_REG_CABLE_DIAG   28
+ - FEAT_BF16 (AArch64 BFloat16 instructions)
+ - FEAT_BTI (Branch Target Identification)
--#define PHY_REG_CONTROL_RST  0x8000
++- FEAT_CRC32 (CRC32 instructions)
--#define PHY_REG_CONTROL_LOOP 0x4000
+ - FEAT_CSV2 (Cache speculation variant 2)
--#define PHY_REG_CONTROL_ANEG 0x1000
+ - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
-+#define PHY_REG_CONTROL_RST       0x8000
+ - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
-+#define PHY_REG_CONTROL_LOOP      0x4000
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
-+#define PHY_REG_CONTROL_ANEG      0x1000
+index XXXXXXX..XXXXXXX 100644
-+#define PHY_REG_CONTROL_ANRESTART 0x0200
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
- #define PHY_REG_STATUS_LINK     0x0004
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
- #define PHY_REG_STATUS_ANEGCMPL 0x0020
+     t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
-@@ -XXX,XX +XXX,XX @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
+     t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
-         }
+     t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
-         if (val & PHY_REG_CONTROL_ANEG) {
+-    t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
-             /* Complete autonegotiation immediately */
++    t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);    /* FEAT_CRC32 */
--            val &= ~PHY_REG_CONTROL_ANEG;
+     t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
-+            val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART);
+     t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
-             s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
+     t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
          }
          if (val & PHY_REG_CONTROL_LOOP) {
 --
-.20.1
+.34.1

-New patch
+[PULL 11/24] Remove i.MX7 IOMUX GPR device from i.MX6UL
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
+In particular, register 22 is not present on i.MX6UL and this is actualy
+The only register that is really emulated in the i.MX7 IOMUX GPR device.
+Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
+as an unimplemented device at the same bus adress and the 2 instantiations
+were actualy colliding. So we go back to the unimplemented device for now.
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx6ul.h |  2 --
+ hw/arm/fsl-imx6ul.c         | 11 -----------
+files changed, 13 deletions(-)
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/misc/imx6ul_ccm.h"
+ #include "hw/misc/imx6_src.h"
+ #include "hw/misc/imx7_snvs.h"
+-#include "hw/misc/imx7_gpr.h"
+ #include "hw/intc/imx_gpcv2.h"
+ #include "hw/watchdog/wdt_imx2.h"
+ #include "hw/gpio/imx_gpio.h"
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
+     IMX6SRCState       src;
+     IMX7SNVSState      snvs;
+     IMXGPCv2State      gpcv2;
+-    IMX7GPRState       gpr;
+     IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
+     IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
+     IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx6ul.c
++++ b/hw/arm/fsl-imx6ul.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+      */
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
+-    /*
+-     * GPR
+-     */
+-    object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
+-
+     /*
+      * GPIOs 1 to 5
+      */
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX6UL_WDOGn_IRQ[i]));
+     }
+-    /*
+-     * GPR
+-     */
+-    sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
+-
+     /*
+      * SDMA
+      */
+--
+.34.1

-New patch
+[PULL 12/24] Refactor i.MX6UL processor code
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
+* Use those newly defined named constants whenever possible.
+* Standardize the way we init a familly of unimplemented devices
+  - SAI
+  - PWM
+  - CAN
+* Add/rework few comments
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
+ hw/arm/fsl-imx6ul.c         | 147 ++++++++++++++++++++++-----------
+files changed, 232 insertions(+), 71 deletions(-)
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/memory.h"
+ #include "cpu.h"
+ #include "qom/object.h"
++#include "qemu/units.h"
+ #define TYPE_FSL_IMX6UL "fsl-imx6ul"
+ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
+     FSL_IMX6UL_NUM_ADCS         = 2,
+     FSL_IMX6UL_NUM_USB_PHYS     = 2,
+     FSL_IMX6UL_NUM_USBS         = 2,
++    FSL_IMX6UL_NUM_SAIS         = 3,
++    FSL_IMX6UL_NUM_CANS         = 2,
++    FSL_IMX6UL_NUM_PWMS         = 4,
+ };
+ struct FslIMX6ULState {
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
+ enum FslIMX6ULMemoryMap {
+     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
+-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
++    FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
+     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
+-    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
+-    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
+-    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
+-    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
++    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
+-    /* AIPS-2 */
++    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
++    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
++
++    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
++    FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
++
++    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
++    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
++
++    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
++    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
++
++    /* AIPS-2 Begin */
+     FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
++
+     FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
++
+     FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
+     FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
+     FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
+     FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
++
+     FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
++
+     FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
++    FSL_IMX6UL_QSPI_SIZE            = 0x500,
++
+     FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
++    FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
++
+     FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
++    FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
++
+     FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
++    FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
++
+     FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
++    FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
++
+     FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
++    FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
++    FSL_IMX6UL_LCDIF_SIZE           = 0x100,
++
+     FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
++    FSL_IMX6UL_CSI_SIZE             = 0x100,
++
+     FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
++    FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
++    FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
++
+     FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
++    FSL_IMX6UL_EIM_SIZE             = 0x100,
++
+     FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
++
+     FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
++    FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
++
+     FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
++    FSL_IMX6UL_ROMCP_SIZE           = 0x300,
++
+     FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
+     FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
+     FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
++
+     FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
+     FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
++    FSL_IMX6UL_ADCn_SIZE            = 0x100,
++
+     FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
+     FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
+-    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
+-    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
+-    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
+-    FSL_IMX6UL_USBO2_USB_ADDR       = 0x02184000,
+-    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
+-    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
+-    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
+-    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
+-    /* AIPS-1 */
++    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
++    FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
++
++    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
++
++    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
++    FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
++    FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
++
++    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
++    FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
++
++    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
++    FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
++
++    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
++    FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
++
++    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
++    FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
++    /* AIPS-2 End */
++
++    /* AIPS-1 Begin */
+     FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
+     FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
+     FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
+     FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
++
+     FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
++    FSL_IMX6UL_SDMA_SIZE            = 0x300,
++
+     FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
++
+     FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
++    FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
++
+     FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
++    FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
++
+     FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
++
+     FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
++
+     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
+     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
++
+     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
++
+     FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
+-    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
+     FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
+-    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
++
+     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
++    FSL_IMX6UL_ANALOG_SIZE          = 0x300,
++
+     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
++
+     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
+     FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
++
+     FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
++    FSL_IMX6UL_KPP_SIZE             = 0x10,
++
+     FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
++
+     FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
++    FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
++
+     FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
+     FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
+     FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
+     FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
+     FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
++
+     FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
++
+     FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
+     FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
++    FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
++
+     FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
+     FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
+     FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
+     FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
++    FSL_IMX6UL_PWMn_SIZE            = 0x20,
++
+     FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
++    FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
++
+     FSL_IMX6UL_BEE_ADDR             = 0x02044000,
++    FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
++    FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
++
+     FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
++    FSL_IMX6UL_SPBA_SIZE            = 0x100,
++
+     FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
++    FSL_IMX6UL_ASRC_SIZE            = 0x100,
++
+     FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
+     FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
+     FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
++    FSL_IMX6UL_SAIn_SIZE            = 0x200,
++
+     FSL_IMX6UL_UART8_ADDR           = 0x02024000,
+     FSL_IMX6UL_UART1_ADDR           = 0x02020000,
+     FSL_IMX6UL_UART7_ADDR           = 0x02018000,
++
+     FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
+     FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
+     FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
+     FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
++
+     FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
++    FSL_IMX6UL_SPDIF_SIZE           = 0x100,
++    /* AIPS-1 End */
++
++    FSL_IMX6UL_BCH_ADDR             = 0x01808000,
++    FSL_IMX6UL_BCH_SIZE             = 0x200,
++
++    FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
++    FSL_IMX6UL_GPMI_SIZE            = 0x200,
+     FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
+-    FSL_IMX6UL_APBH_DMA_SIZE        = (32 * 1024),
++    FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
+     FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
+     FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
+-    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = 0x00060000,
++    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
++
+     FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
+-    FSL_IMX6UL_OCRAM_MEM_SIZE       = 0x00020000,
++    FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
++
+     FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
+-    FSL_IMX6UL_CAAM_MEM_SIZE        = 0x00008000,
++    FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
++
+     FSL_IMX6UL_ROM_ADDR             = 0x00000000,
+-    FSL_IMX6UL_ROM_SIZE             = 0x00018000,
++    FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
+ };
+ enum FslIMX6ULIRQs {
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx6ul.c
++++ b/hw/arm/fsl-imx6ul.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
+     /*
+-     * GPIOs 1 to 5
++     * GPIOs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
+         snprintf(name, NAME_SIZE, "gpio%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * GPT 1, 2
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
+         snprintf(name, NAME_SIZE, "gpt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * EPIT 1, 2
++     * EPITs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
+         snprintf(name, NAME_SIZE, "epit%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * eCSPI
++     * eCSPIs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
+         snprintf(name, NAME_SIZE, "spi%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * I2C
++     * I2Cs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
+         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
+         snprintf(name, NAME_SIZE, "uart%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
+         snprintf(name, NAME_SIZE, "eth%d", i);
+         object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
+     }
+-    /* USB */
++    /*
++     * USB PHYs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+         snprintf(name, NAME_SIZE, "usbphy%d", i);
+         object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
+     }
++
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+         snprintf(name, NAME_SIZE, "usb%d", i);
+         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
+     }
+     /*
+-     * SDHCI
++     * SDHCIs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+         snprintf(name, NAME_SIZE, "usdhc%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
+         snprintf(name, NAME_SIZE, "wdt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+      * A7MPCORE DAP
+      */
+     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
+-                                0x100000);
++                                FSL_IMX6UL_A7MPCORE_DAP_SIZE);
+     /*
+-     * GPT 1, 2
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
+         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * EPIT 1, 2
++     * EPITs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
+         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * GPIO
++     * GPIOs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
+         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * IOMUXC and IOMUXC_GPR
++     * IOMUXC
+      */
+-    for (i = 0; i < 1; i++) {
+-        static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
+-            FSL_IMX6UL_IOMUXC_ADDR,
+-            FSL_IMX6UL_IOMUXC_GPR_ADDR,
+-        };
+-
+-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
+-        create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
+-    }
++    create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
++                                FSL_IMX6UL_IOMUXC_SIZE);
++    create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
++                                FSL_IMX6UL_IOMUXC_GPR_SIZE);
+     /*
+      * CCM
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
+-    /* Initialize all ECSPI */
++    /*
++     * ECSPIs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
+         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
+             FSL_IMX6UL_ECSPI1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * I2C
++     * I2Cs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
+         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
+         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      *
+      * We must use two loops since phy_connected affects the other interface
+      * and we have to set all properties before calling sysbus_realize().
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
+     }
+-    /* USB */
++    /*
++     * USB PHYs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
++        static const hwaddr
++                     FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
++            FSL_IMX6UL_USBPHY1_ADDR,
++            FSL_IMX6UL_USBPHY2_ADDR,
++        };
++
+         sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
+         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+-                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
++                        FSL_IMX6UL_USB_PHYn_ADDR[i]);
+     }
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
++        static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
++            FSL_IMX6UL_USBO2_USB1_ADDR,
++            FSL_IMX6UL_USBO2_USB2_ADDR,
++        };
++
+         static const int FSL_IMX6UL_USBn_IRQ[] = {
+             FSL_IMX6UL_USB1_IRQ,
+             FSL_IMX6UL_USB2_IRQ,
+         };
++
+         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
+         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+-                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
++                        FSL_IMX6UL_USB02_USBn_ADDR[i]);
+         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                                             FSL_IMX6UL_USBn_IRQ[i]));
+     }
+     /*
+-     * USDHC
++     * USDHCs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
+         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+             FSL_IMX6UL_WDOG2_ADDR,
+             FSL_IMX6UL_WDOG3_ADDR,
+         };
++
+         static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
+             FSL_IMX6UL_WDOG1_IRQ,
+             FSL_IMX6UL_WDOG2_IRQ,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     /*
+      * SDMA
+      */
+-    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
++    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
++                                FSL_IMX6UL_SDMA_SIZE);
+     /*
+-     * SAI (Audio SSI (Synchronous Serial Interface))
++     * SAIs (Audio SSI (Synchronous Serial Interface))
+      */
+-    create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
+-    create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
+-    create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
++        static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
++            FSL_IMX6UL_SAI1_ADDR,
++            FSL_IMX6UL_SAI2_ADDR,
++            FSL_IMX6UL_SAI3_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "sai%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
++                                    FSL_IMX6UL_SAIn_SIZE);
++    }
+     /*
+-     * PWM
++     * PWMs
+      */
+-    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
+-    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
+-    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
+-    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
++        static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
++            FSL_IMX6UL_PWM1_ADDR,
++            FSL_IMX6UL_PWM2_ADDR,
++            FSL_IMX6UL_PWM3_ADDR,
++            FSL_IMX6UL_PWM4_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "pwm%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
++                                    FSL_IMX6UL_PWMn_SIZE);
++    }
+     /*
+      * Audio ASRC (asynchronous sample rate converter)
+      */
+-    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
++    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
++                                FSL_IMX6UL_ASRC_SIZE);
+     /*
+-     * CAN
++     * CANs
+      */
+-    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
+-    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
++        static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
++            FSL_IMX6UL_CAN1_ADDR,
++            FSL_IMX6UL_CAN2_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "can%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
++                                    FSL_IMX6UL_CANn_SIZE);
++    }
+     /*
+      * APHB_DMA
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+         };
+         snprintf(name, NAME_SIZE, "adc%d", i);
+-        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
++        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
++                                    FSL_IMX6UL_ADCn_SIZE);
+     }
+     /*
+      * LCD
+      */
+-    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
++    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
++                                FSL_IMX6UL_LCDIF_SIZE);
+     /*
+      * ROM memory
+--
+.34.1

-[PULL 1/7] pl031: Expose RTCICR as proper WC register
+[PULL 13/24] Add i.MX6UL missing devices.
-From: Alexander Graf <graf@amazon.com>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-The current PL031 RTCICR register implementation always clears the
+* Add TZASC as unimplemented device.
-IRQ pending status on a register write, regardless of the value the
+  - Allow bare metal application to access this (unimplemented) device
-guest writes.
+* Add CSU as unimplemented device.
   - Allow bare metal application to access this (unimplemented) device
 * Add 4 missing PWM devices
-To justify that behavior, it references the ARM926EJ-S Development
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-Chip Reference Manual (DDI0287B) and indicates that said document
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-states that any write clears the internal IRQ state.  It is indeed
+Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
 true that in section 11.1 this document says:
   "The interrupt is cleared by writing any data value to the
    interrupt clear register RTCICR".
 However, later in section 11.2.2 it contradicts itself by saying:
   "Writing 1 to bit 0 of RTCICR clears the RTCINTR flag."
 The latter statement matches the PL031 TRM (DDI0224C), which says:
   "Writing 1 to bit position 0 clears the corresponding interrupt.
    Writing 0 has no effect."
 Let's assume that the self-contradictory DDI0287B is in error, and
 follow the reference manual for the device itself, by making the
 register write-one-to-clear.
 Reported-by: Hendrik Borghorst <hborghor@amazon.de>
 Signed-off-by: Alexander Graf <graf@amazon.com>
 Message-id: 20191104115228.30745-1-graf@amazon.com
 [PMM: updated commit message to note that DDI0287B says two
  conflicting things]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/rtc/pl031.c | 6 +-----
+ include/hw/arm/fsl-imx6ul.h |  2 +-
-file changed, 1 insertion(+), 5 deletions(-)
+ hw/arm/fsl-imx6ul.c         | 16 ++++++++++++++++
 files changed, 17 insertions(+), 1 deletion(-)
-diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/rtc/pl031.c
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/hw/rtc/pl031.c
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ static void pl031_write(void * opaque, hwaddr offset,
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
-         pl031_update(s);
+     FSL_IMX6UL_NUM_USBS         = 2,
-         break;
+     FSL_IMX6UL_NUM_SAIS         = 3,
-     case RTC_ICR:
+     FSL_IMX6UL_NUM_CANS         = 2,
--        /* The PL031 documentation (DDI0224B) states that the interrupt is
+-    FSL_IMX6UL_NUM_PWMS         = 4,
--           cleared when bit 0 of the written value is set.  However the
++    FSL_IMX6UL_NUM_PWMS         = 8,
--           arm926e documentation (DDI0287B) states that the interrupt is
+ };
--           cleared when any value is written.  */
--        s->is = 0;
+ struct FslIMX6ULState {
-+        s->is &= ~value;
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
-         pl031_update(s);
+index XXXXXXX..XXXXXXX 100644
-         break;
+--- a/hw/arm/fsl-imx6ul.c
-     case RTC_CR:
++++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
              FSL_IMX6UL_PWM2_ADDR,
              FSL_IMX6UL_PWM3_ADDR,
              FSL_IMX6UL_PWM4_ADDR,
 +            FSL_IMX6UL_PWM5_ADDR,
 +            FSL_IMX6UL_PWM6_ADDR,
 +            FSL_IMX6UL_PWM7_ADDR,
 +            FSL_IMX6UL_PWM8_ADDR,
          };
          snprintf(name, NAME_SIZE, "pwm%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
                                  FSL_IMX6UL_LCDIF_SIZE);
 +    /*
 +     * CSU
 +     */
 +    create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
 +                                FSL_IMX6UL_CSU_SIZE);
 +
 +    /*
 +     * TZASC
 +     */
 +    create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
 +                                FSL_IMX6UL_TZASC_SIZE);
 +
      /*
       * ROM memory
       */
 --
-.20.1
+.34.1

-New patch
+[PULL 14/24] Refactor i.MX7 processor code
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
+* Use those newly defined named constants whenever possible.
+* Standardize the way we init a familly of unimplemented devices
+  - SAI
+  - PWM
+  - CAN
+* Add/rework few comments
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
+ hw/arm/fsl-imx7.c         | 130 ++++++++++-----
+files changed, 335 insertions(+), 125 deletions(-)
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx7.h
++++ b/include/hw/arm/fsl-imx7.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/misc/imx7_ccm.h"
+ #include "hw/misc/imx7_snvs.h"
+ #include "hw/misc/imx7_gpr.h"
+-#include "hw/misc/imx6_src.h"
+ #include "hw/watchdog/wdt_imx2.h"
+ #include "hw/gpio/imx_gpio.h"
+ #include "hw/char/imx_serial.h"
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/usb/chipidea.h"
+ #include "cpu.h"
+ #include "qom/object.h"
++#include "qemu/units.h"
+ #define TYPE_FSL_IMX7 "fsl-imx7"
+ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
+@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
+     FSL_IMX7_NUM_ECSPIS       = 4,
+     FSL_IMX7_NUM_USBS         = 3,
+     FSL_IMX7_NUM_ADCS         = 2,
++    FSL_IMX7_NUM_SAIS         = 3,
++    FSL_IMX7_NUM_CANS         = 2,
++    FSL_IMX7_NUM_PWMS         = 4,
+ };
+ struct FslIMX7State {
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
+ enum FslIMX7MemoryMap {
+     FSL_IMX7_MMDC_ADDR            = 0x80000000,
+-    FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
++    FSL_IMX7_MMDC_SIZE            = (2 * GiB),
+-    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
+-    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
+-    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
+-    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
+-    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
+-    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
+-    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
++    FSL_IMX7_QSPI1_MEM_ADDR       = 0x60000000,
++    FSL_IMX7_QSPI1_MEM_SIZE       = (256 * MiB),
+-    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
++    FSL_IMX7_PCIE1_MEM_ADDR       = 0x40000000,
++    FSL_IMX7_PCIE1_MEM_SIZE       = (256 * MiB),
+-    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
+-    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
+-    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
+-    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
++    FSL_IMX7_QSPI1_RX_BUF_ADDR    = 0x34000000,
++    FSL_IMX7_QSPI1_RX_BUF_SIZE    = (32 * MiB),
+-    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
++    /* PCIe Peripherals */
++    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
+-    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
+-    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
+-    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
+-    FSL_IMX7_GPT4_ADDR            = 0x30300000,
++    /* MMAP Peripherals */
++    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
++    FSL_IMX7_DMA_APBH_SIZE        = 0x8000,
+-    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
+-    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
+-    FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
++    /* GPV configuration */
++    FSL_IMX7_GPV6_ADDR            = 0x32600000,
++    FSL_IMX7_GPV5_ADDR            = 0x32500000,
++    FSL_IMX7_GPV4_ADDR            = 0x32400000,
++    FSL_IMX7_GPV3_ADDR            = 0x32300000,
++    FSL_IMX7_GPV2_ADDR            = 0x32200000,
++    FSL_IMX7_GPV1_ADDR            = 0x32100000,
++    FSL_IMX7_GPV0_ADDR            = 0x32000000,
++    FSL_IMX7_GPVn_SIZE            = (1 * MiB),
+-    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
+-    FSL_IMX7_OCOTP_SIZE           = 0x10000,
++    /* Arm Peripherals */
++    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
+-    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
+-    FSL_IMX7_SNVS_ADDR            = 0x30370000,
+-    FSL_IMX7_CCM_ADDR             = 0x30380000,
++    /* AIPS-3 Begin */
+-    FSL_IMX7_SRC_ADDR             = 0x30390000,
+-    FSL_IMX7_SRC_SIZE             = 0x1000,
++    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
++    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
+-    FSL_IMX7_ADC1_ADDR            = 0x30610000,
+-    FSL_IMX7_ADC2_ADDR            = 0x30620000,
+-    FSL_IMX7_ADCn_SIZE            = 0x1000,
++    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
++    FSL_IMX7_SDMA_SIZE            = (4 * KiB),
+-    FSL_IMX7_PWM1_ADDR            = 0x30660000,
+-    FSL_IMX7_PWM2_ADDR            = 0x30670000,
+-    FSL_IMX7_PWM3_ADDR            = 0x30680000,
+-    FSL_IMX7_PWM4_ADDR            = 0x30690000,
+-    FSL_IMX7_PWMn_SIZE            = 0x10000,
++    FSL_IMX7_EIM_ADDR             = 0x30BC0000,
++    FSL_IMX7_EIM_SIZE             = (4 * KiB),
+-    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
+-    FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
++    FSL_IMX7_QSPI_ADDR            = 0x30BB0000,
++    FSL_IMX7_QSPI_SIZE            = 0x8000,
+-    FSL_IMX7_GPC_ADDR             = 0x303A0000,
++    FSL_IMX7_SIM2_ADDR            = 0x30BA0000,
++    FSL_IMX7_SIM1_ADDR            = 0x30B90000,
++    FSL_IMX7_SIMn_SIZE            = (4 * KiB),
++
++    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
++    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
++    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
++
++    FSL_IMX7_USB3_ADDR            = 0x30B30000,
++    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
++    FSL_IMX7_USB2_ADDR            = 0x30B20000,
++    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
++    FSL_IMX7_USB1_ADDR            = 0x30B10000,
++    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
++    FSL_IMX7_USBMISCn_SIZE        = 0x200,
++
++    FSL_IMX7_USB_PL301_ADDR       = 0x30AD0000,
++    FSL_IMX7_USB_PL301_SIZE       = (64 * KiB),
++
++    FSL_IMX7_SEMAPHORE_HS_ADDR    = 0x30AC0000,
++    FSL_IMX7_SEMAPHORE_HS_SIZE    = (64 * KiB),
++
++    FSL_IMX7_MUB_ADDR             = 0x30AB0000,
++    FSL_IMX7_MUA_ADDR             = 0x30AA0000,
++    FSL_IMX7_MUn_SIZE             = (KiB),
++
++    FSL_IMX7_UART7_ADDR           = 0x30A90000,
++    FSL_IMX7_UART6_ADDR           = 0x30A80000,
++    FSL_IMX7_UART5_ADDR           = 0x30A70000,
++    FSL_IMX7_UART4_ADDR           = 0x30A60000,
++
++    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
++    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
++    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
++    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
++
++    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
++    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
++    FSL_IMX7_CANn_SIZE            = (4 * KiB),
++
++    FSL_IMX7_AIPS3_CONF_ADDR      = 0x309F0000,
++    FSL_IMX7_AIPS3_CONF_SIZE      = (64 * KiB),
+     FSL_IMX7_CAAM_ADDR            = 0x30900000,
+-    FSL_IMX7_CAAM_SIZE            = 0x40000,
++    FSL_IMX7_CAAM_SIZE            = (256 * KiB),
+-    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
+-    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
+-    FSL_IMX7_CANn_SIZE            = 0x10000,
++    FSL_IMX7_SPBA_ADDR            = 0x308F0000,
++    FSL_IMX7_SPBA_SIZE            = (4 * KiB),
+-    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
+-    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
+-    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
+-    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
++    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
++    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
++    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
++    FSL_IMX7_SAIn_SIZE            = (4 * KiB),
+-    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
+-    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
+-    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
+-    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
+-
+-    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
+-    FSL_IMX7_LCDIF_SIZE           = 0x1000,
+-
+-    FSL_IMX7_UART1_ADDR           = 0x30860000,
++    FSL_IMX7_UART3_ADDR           = 0x30880000,
+     /*
+      * Some versions of the reference manual claim that UART2 is @
+      * 0x30870000, but experiments with HW + DT files in upstream
+@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
+      * actually located @ 0x30890000
+      */
+     FSL_IMX7_UART2_ADDR           = 0x30890000,
+-    FSL_IMX7_UART3_ADDR           = 0x30880000,
+-    FSL_IMX7_UART4_ADDR           = 0x30A60000,
+-    FSL_IMX7_UART5_ADDR           = 0x30A70000,
+-    FSL_IMX7_UART6_ADDR           = 0x30A80000,
+-    FSL_IMX7_UART7_ADDR           = 0x30A90000,
++    FSL_IMX7_UART1_ADDR           = 0x30860000,
+-    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
+-    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
+-    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
+-    FSL_IMX7_SAIn_SIZE            = 0x10000,
++    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
++    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
++    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
++    FSL_IMX7_ECSPIn_SIZE          = (4 * KiB),
+-    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
+-    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
++    /* AIPS-3 End */
+-    FSL_IMX7_USB1_ADDR            = 0x30B10000,
+-    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
+-    FSL_IMX7_USB2_ADDR            = 0x30B20000,
+-    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
+-    FSL_IMX7_USB3_ADDR            = 0x30B30000,
+-    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
+-    FSL_IMX7_USBMISCn_SIZE        = 0x200,
++    /* AIPS-2 Begin */
+-    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
+-    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
+-    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
++    FSL_IMX7_AXI_DEBUG_MON_ADDR   = 0x307E0000,
++    FSL_IMX7_AXI_DEBUG_MON_SIZE   = (64 * KiB),
+-    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
+-    FSL_IMX7_SDMA_SIZE            = 0x1000,
++    FSL_IMX7_PERFMON2_ADDR        = 0x307D0000,
++    FSL_IMX7_PERFMON1_ADDR        = 0x307C0000,
++    FSL_IMX7_PERFMONn_SIZE        = (64 * KiB),
++
++    FSL_IMX7_DDRC_ADDR            = 0x307A0000,
++    FSL_IMX7_DDRC_SIZE            = (4 * KiB),
++
++    FSL_IMX7_DDRC_PHY_ADDR        = 0x30790000,
++    FSL_IMX7_DDRC_PHY_SIZE        = (4 * KiB),
++
++    FSL_IMX7_TZASC_ADDR           = 0x30780000,
++    FSL_IMX7_TZASC_SIZE           = (64 * KiB),
++
++    FSL_IMX7_MIPI_DSI_ADDR        = 0x30760000,
++    FSL_IMX7_MIPI_DSI_SIZE        = (4 * KiB),
++
++    FSL_IMX7_MIPI_CSI_ADDR        = 0x30750000,
++    FSL_IMX7_MIPI_CSI_SIZE        = 0x4000,
++
++    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
++    FSL_IMX7_LCDIF_SIZE           = 0x8000,
++
++    FSL_IMX7_CSI_ADDR             = 0x30710000,
++    FSL_IMX7_CSI_SIZE             = (4 * KiB),
++
++    FSL_IMX7_PXP_ADDR             = 0x30700000,
++    FSL_IMX7_PXP_SIZE             = 0x4000,
++
++    FSL_IMX7_EPDC_ADDR            = 0x306F0000,
++    FSL_IMX7_EPDC_SIZE            = (4 * KiB),
++
++    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
++    FSL_IMX7_PCIE_PHY_SIZE        = (4 * KiB),
++
++    FSL_IMX7_SYSCNT_CTRL_ADDR     = 0x306C0000,
++    FSL_IMX7_SYSCNT_CMP_ADDR      = 0x306B0000,
++    FSL_IMX7_SYSCNT_RD_ADDR       = 0x306A0000,
++
++    FSL_IMX7_PWM4_ADDR            = 0x30690000,
++    FSL_IMX7_PWM3_ADDR            = 0x30680000,
++    FSL_IMX7_PWM2_ADDR            = 0x30670000,
++    FSL_IMX7_PWM1_ADDR            = 0x30660000,
++    FSL_IMX7_PWMn_SIZE            = (4 * KiB),
++
++    FSL_IMX7_FlEXTIMER2_ADDR      = 0x30650000,
++    FSL_IMX7_FlEXTIMER1_ADDR      = 0x30640000,
++    FSL_IMX7_FLEXTIMERn_SIZE      = (4 * KiB),
++
++    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
++
++    FSL_IMX7_ADC2_ADDR            = 0x30620000,
++    FSL_IMX7_ADC1_ADDR            = 0x30610000,
++    FSL_IMX7_ADCn_SIZE            = (4 * KiB),
++
++    FSL_IMX7_AIPS2_CONF_ADDR      = 0x305F0000,
++    FSL_IMX7_AIPS2_CONF_SIZE      = (64 * KiB),
++
++    /* AIPS-2 End */
++
++    /* AIPS-1 Begin */
++
++    FSL_IMX7_CSU_ADDR             = 0x303E0000,
++    FSL_IMX7_CSU_SIZE             = (64 * KiB),
++
++    FSL_IMX7_RDC_ADDR             = 0x303D0000,
++    FSL_IMX7_RDC_SIZE             = (4 * KiB),
++
++    FSL_IMX7_SEMAPHORE2_ADDR      = 0x303C0000,
++    FSL_IMX7_SEMAPHORE1_ADDR      = 0x303B0000,
++    FSL_IMX7_SEMAPHOREn_SIZE      = (4 * KiB),
++
++    FSL_IMX7_GPC_ADDR             = 0x303A0000,
++
++    FSL_IMX7_SRC_ADDR             = 0x30390000,
++    FSL_IMX7_SRC_SIZE             = (4 * KiB),
++
++    FSL_IMX7_CCM_ADDR             = 0x30380000,
++
++    FSL_IMX7_SNVS_HP_ADDR         = 0x30370000,
++
++    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
++
++    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
++    FSL_IMX7_OCOTP_SIZE           = 0x10000,
++
++    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
++    FSL_IMX7_IOMUXC_GPR_SIZE      = (4 * KiB),
++
++    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
++    FSL_IMX7_IOMUXC_SIZE          = (4 * KiB),
++
++    FSL_IMX7_KPP_ADDR             = 0x30320000,
++    FSL_IMX7_KPP_SIZE             = (4 * KiB),
++
++    FSL_IMX7_ROMCP_ADDR           = 0x30310000,
++    FSL_IMX7_ROMCP_SIZE           = (4 * KiB),
++
++    FSL_IMX7_GPT4_ADDR            = 0x30300000,
++    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
++    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
++    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
++
++    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
++    FSL_IMX7_IOMUXC_LPSR_SIZE     = (4 * KiB),
++
++    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
++    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
++    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
++    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
++
++    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
++
++    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
++    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
++    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
++    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
++    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
++    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
++    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
++
++    FSL_IMX7_AIPS1_CONF_ADDR      = 0x301F0000,
++    FSL_IMX7_AIPS1_CONF_SIZE      = (64 * KiB),
+-    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
+     FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
++    FSL_IMX7_A7MPCORE_DAP_SIZE    = (1 * MiB),
+-    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
+-    FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
++    /* AIPS-1 End */
+-    FSL_IMX7_GPR_ADDR             = 0x30340000,
++    FSL_IMX7_EIM_CS0_ADDR         = 0x28000000,
++    FSL_IMX7_EIM_CS0_SIZE         = (128 * MiB),
+-    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
+-    FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
++    FSL_IMX7_OCRAM_PXP_ADDR       = 0x00940000,
++    FSL_IMX7_OCRAM_PXP_SIZE       = (32 * KiB),
++
++    FSL_IMX7_OCRAM_EPDC_ADDR      = 0x00920000,
++    FSL_IMX7_OCRAM_EPDC_SIZE      = (128 * KiB),
++
++    FSL_IMX7_OCRAM_MEM_ADDR       = 0x00900000,
++    FSL_IMX7_OCRAM_MEM_SIZE       = (128 * KiB),
++
++    FSL_IMX7_TCMU_ADDR            = 0x00800000,
++    FSL_IMX7_TCMU_SIZE            = (32 * KiB),
++
++    FSL_IMX7_TCML_ADDR            = 0x007F8000,
++    FSL_IMX7_TCML_SIZE            = (32 * KiB),
++
++    FSL_IMX7_OCRAM_S_ADDR         = 0x00180000,
++    FSL_IMX7_OCRAM_S_SIZE         = (32 * KiB),
++
++    FSL_IMX7_CAAM_MEM_ADDR        = 0x00100000,
++    FSL_IMX7_CAAM_MEM_SIZE        = (32 * KiB),
++
++    FSL_IMX7_ROM_ADDR             = 0x00000000,
++    FSL_IMX7_ROM_SIZE             = (96 * KiB),
+ };
+ enum FslIMX7IRQs {
+diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx7.c
++++ b/hw/arm/fsl-imx7.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+     char name[NAME_SIZE];
+     int i;
++    /*
++     * CPUs
++     */
+     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
+         snprintf(name, NAME_SIZE, "cpu%d", i);
+         object_initialize_child(obj, name, &s->cpu[i],
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+                             TYPE_A15MPCORE_PRIV);
+     /*
+-     * GPIOs 1 to 7
++     * GPIOs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
+         snprintf(name, NAME_SIZE, "gpio%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+     }
+     /*
+-     * GPT1, 2, 3, 4
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
+         snprintf(name, NAME_SIZE, "gpt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+      */
+     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
++    /*
++     * ECSPIs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
+         snprintf(name, NAME_SIZE, "spi%d", i + 1);
+         object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
+     }
+-
++    /*
++     * I2Cs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
+         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
+         object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
+             snprintf(name, NAME_SIZE, "uart%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      */
+     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
+             snprintf(name, NAME_SIZE, "eth%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+     }
+     /*
+-     * SDHCI
++     * SDHCIs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
+             snprintf(name, NAME_SIZE, "usdhc%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
+             snprintf(name, NAME_SIZE, "wdt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
+      */
+     object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
++    /*
++     * PCIE
++     */
+     object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
+         snprintf(name, NAME_SIZE, "usb%d", i);
+         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+         return;
+     }
++    /*
++     * CPUs
++     */
+     for (i = 0; i < smp_cpus; i++) {
+         o = OBJECT(&s->cpu[i]);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+      * A7MPCORE DAP
+      */
+     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
+-                                0x100000);
++                                FSL_IMX7_A7MPCORE_DAP_SIZE);
+     /*
+-     * GPT1, 2, 3, 4
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
+         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX7_GPTn_IRQ[i]));
+     }
++    /*
++     * GPIOs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
+         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
+             FSL_IMX7_GPIO1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     /*
+      * IOMUXC and IOMUXC_LPSR
+      */
+-    for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
+-        static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
+-            FSL_IMX7_IOMUXC_ADDR,
+-            FSL_IMX7_IOMUXC_LPSR_ADDR,
+-        };
+-
+-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
+-        create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
+-                                    FSL_IMX7_IOMUXCn_SIZE);
+-    }
++    create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
++                                FSL_IMX7_IOMUXC_SIZE);
++    create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
++                                FSL_IMX7_IOMUXC_LPSR_SIZE);
+     /*
+      * CCM
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
+-    /* Initialize all ECSPI */
++    /*
++     * ECSPIs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
+         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
+             FSL_IMX7_ECSPI1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX7_SPIn_IRQ[i]));
+     }
++    /*
++     * I2Cs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
+         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
+             FSL_IMX7_I2C1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
+         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      *
+      * We must use two loops since phy_connected affects the other interface
+      * and we have to set all properties before calling sysbus_realize().
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * USDHC
++     * USDHCs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
+         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+      * SNVS
+      */
+     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
+     /*
+      * SRC
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
+         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
+     /*
+-     * PWM
++     * PWMs
+      */
+-    create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
+-    create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
+-    create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
+-    create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
++    for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
++        static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
++            FSL_IMX7_PWM1_ADDR,
++            FSL_IMX7_PWM2_ADDR,
++            FSL_IMX7_PWM3_ADDR,
++            FSL_IMX7_PWM4_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "pwm%d", i);
++        create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
++                                    FSL_IMX7_PWMn_SIZE);
++    }
+     /*
+-     * CAN
++     * CANs
+      */
+-    create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
+-    create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
++    for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
++        static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
++            FSL_IMX7_CAN1_ADDR,
++            FSL_IMX7_CAN2_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "can%d", i);
++        create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
++                                    FSL_IMX7_CANn_SIZE);
++    }
+     /*
+-     * SAI (Audio SSI (Synchronous Serial Interface))
++     * SAIs (Audio SSI (Synchronous Serial Interface))
+      */
+-    create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
+-    create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
+-    create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
++    for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
++        static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
++            FSL_IMX7_SAI1_ADDR,
++            FSL_IMX7_SAI2_ADDR,
++            FSL_IMX7_SAI3_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "sai%d", i);
++        create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
++                                    FSL_IMX7_SAIn_SIZE);
++    }
+     /*
+      * OCOTP
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
+                                 FSL_IMX7_OCOTP_SIZE);
++    /*
++     * GPR
++     */
+     sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
++    /*
++     * PCIE
++     */
+     sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
+-
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
+         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
+             FSL_IMX7_USBMISC1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+      */
+     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
+                                 FSL_IMX7_PCIE_PHY_SIZE);
++
+ }
+ static Property fsl_imx7_properties[] = {
+--
+.34.1

-[PULL 3/7] ssi: xilinx_spips: Skip spi bus update for a few register writes
+[PULL 15/24] Add i.MX7 missing TZ devices and memory regions
-From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-A few configuration register writes need not update the spi bus state, so just
+* Add TZASC as unimplemented device.
-return after the register write.
+  - Allow bare metal application to access this (unimplemented) device
 * Add CSU as unimplemented device.
   - Allow bare metal application to access this (unimplemented) device
 * Add various memory segments
   - OCRAM
   - OCRAM EPDC
   - OCRAM PXP
   - OCRAM S
   - ROM
   - CAAM
-Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
 Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
 Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 Message-id: 1573830705-14579-1-git-send-email-sai.pavan.boddu@xilinx.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++----
+ include/hw/arm/fsl-imx7.h |  7 +++++
-file changed, 18 insertions(+), 4 deletions(-)
+ hw/arm/fsl-imx7.c         | 63 +++++++++++++++++++++++++++++++++++++++
 files changed, 70 insertions(+)
-diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/ssi/xilinx_spips.c
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/hw/ssi/xilinx_spips.c
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
- #define R_GPIO              (0x30 / 4)
+     IMX7GPRState       gpr;
- #define R_LPBK_DLY_ADJ      (0x38 / 4)
+     ChipideaState      usb[FSL_IMX7_NUM_USBS];
- #define R_LPBK_DLY_ADJ_RESET (0x33)
+     DesignwarePCIEHost pcie;
-+#define R_IOU_TAPDLY_BYPASS (0x3C / 4)
++    MemoryRegion       rom;
- #define R_TXD1              (0x80 / 4)
++    MemoryRegion       caam;
- #define R_TXD2              (0x84 / 4)
++    MemoryRegion       ocram;
- #define R_TXD3              (0x88 / 4)
++    MemoryRegion       ocram_epdc;
-@@ -XXX,XX +XXX,XX @@
++    MemoryRegion       ocram_pxp;
- #define R_LQSPI_STS         (0xA4 / 4)
++    MemoryRegion       ocram_s;
- #define LQSPI_STS_WR_RECVD      (1 << 1)
++
+     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
-+#define R_DUMMY_CYCLE_EN    (0xC8 / 4)
+     bool               phy_connected[FSL_IMX7_NUM_ETHS];
-+#define R_ECO               (0xF8 / 4)
+ };
- #define R_MOD_ID            (0xFC / 4)
+diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
+index XXXXXXX..XXXXXXX 100644
- #define R_GQSPI_SELECT          (0x144 / 4)
+--- a/hw/arm/fsl-imx7.c
-@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
++++ b/hw/arm/fsl-imx7.c
- {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
-     int mask = ~0;
+     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
-     XilinxSPIPS *s = opaque;
+                                 FSL_IMX7_PCIE_PHY_SIZE);
-+    bool try_flush = true;
++    /*
-     DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
++     * CSU
-     addr >>= 2;
++     */
-@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
++    create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
-         tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,
++                                FSL_IMX7_CSU_SIZE);
-                       s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
++
-         goto no_reg_update;
++    /*
-+    /* Skip SPI bus update for below registers writes */
++     * TZASC
-+    case R_GPIO:
++     */
-+    case R_LPBK_DLY_ADJ:
++    create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
-+    case R_IOU_TAPDLY_BYPASS:
++                                FSL_IMX7_TZASC_SIZE);
-+    case R_DUMMY_CYCLE_EN:
++
-+    case R_ECO:
++    /*
-+        try_flush = false;
++     * OCRAM memory
-+        break;
++     */
-     }
++    memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
-     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
++                           FSL_IMX7_OCRAM_MEM_SIZE,
- no_reg_update:
++                           &error_abort);
--    xilinx_spips_update_cs_lines(s);
++    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
--    xilinx_spips_check_flush(s);
++                                &s->ocram);
--    xilinx_spips_update_cs_lines(s);
++
--    xilinx_spips_update_ixr(s);
++    /*
-+    if (try_flush) {
++     * OCRAM EPDC memory
-+        xilinx_spips_update_cs_lines(s);
++     */
-+        xilinx_spips_check_flush(s);
++    memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
-+        xilinx_spips_update_cs_lines(s);
++                           FSL_IMX7_OCRAM_EPDC_SIZE,
-+        xilinx_spips_update_ixr(s);
++                           &error_abort);
-+    }
++    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
 +                                &s->ocram_epdc);
 +
 +    /*
 +     * OCRAM PXP memory
 +     */
 +    memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
 +                           FSL_IMX7_OCRAM_PXP_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
 +                                &s->ocram_pxp);
 +
 +    /*
 +     * OCRAM_S memory
 +     */
 +    memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
 +                           FSL_IMX7_OCRAM_S_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
 +                                &s->ocram_s);
 +
 +    /*
 +     * ROM memory
 +     */
 +    memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
 +                           FSL_IMX7_ROM_SIZE, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
 +                                &s->rom);
 +
 +    /*
 +     * CAAM memory
 +     */
 +    memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
 +                           FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
 +                                &s->caam);
  }
- static const MemoryRegionOps spips_ops = {
+ static Property fsl_imx7_properties[] = {
 --
-.20.1
+.34.1

-New patch
+[PULL 16/24] Add i.MX7 SRC device implementation
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
 The SRC device is normally used to start the secondary CPU.
 When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
 is installing at boot time and therefore the fact that the SRC device is
 unimplemented is hidden as Qemu respond directly to PSCI requets without
 using the SRC device.
 But if you try to run a more bare metal application (maybe uboot itself),
 then it is not possible to start the secondary CPU as the SRC is an
 unimplemented device.
 This patch adds the ability to start the secondary CPU through the SRC
 device so that you can use this feature in bare metal applications.
 Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  include/hw/arm/fsl-imx7.h  |   3 +-
  include/hw/misc/imx7_src.h |  66 +++++++++
  hw/arm/fsl-imx7.c          |   8 +-
  hw/misc/imx7_src.c         | 276 +++++++++++++++++++++++++++++++++++++
  hw/misc/meson.build        |   1 +
  hw/misc/trace-events       |   4 +
 files changed, 356 insertions(+), 2 deletions(-)
  create mode 100644 include/hw/misc/imx7_src.h
  create mode 100644 hw/misc/imx7_src.c
 diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/fsl-imx7.h
 +++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
  #include "hw/misc/imx7_ccm.h"
  #include "hw/misc/imx7_snvs.h"
  #include "hw/misc/imx7_gpr.h"
 +#include "hw/misc/imx7_src.h"
  #include "hw/watchdog/wdt_imx2.h"
  #include "hw/gpio/imx_gpio.h"
  #include "hw/char/imx_serial.h"
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
      IMX7CCMState       ccm;
      IMX7AnalogState    analog;
      IMX7SNVSState      snvs;
 +    IMX7SRCState       src;
      IMXGPCv2State      gpcv2;
      IMXSPIState        spi[FSL_IMX7_NUM_ECSPIS];
      IMXI2CState        i2c[FSL_IMX7_NUM_I2CS];
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
      FSL_IMX7_GPC_ADDR             = 0x303A0000,
      FSL_IMX7_SRC_ADDR             = 0x30390000,
 -    FSL_IMX7_SRC_SIZE             = (4 * KiB),
      FSL_IMX7_CCM_ADDR             = 0x30380000,
 diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/imx7_src.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * IMX7 System Reset Controller
 + *
 + * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
 +#ifndef IMX7_SRC_H
 +#define IMX7_SRC_H
 +
 +#include "hw/sysbus.h"
 +#include "qemu/bitops.h"
 +#include "qom/object.h"
 +
 +#define SRC_SCR 0
 +#define SRC_A7RCR0 1
 +#define SRC_A7RCR1 2
 +#define SRC_M4RCR 3
 +#define SRC_ERCR 5
 +#define SRC_HSICPHY_RCR 7
 +#define SRC_USBOPHY1_RCR 8
 +#define SRC_USBOPHY2_RCR 9
 +#define SRC_MPIPHY_RCR 10
 +#define SRC_PCIEPHY_RCR 11
 +#define SRC_SBMR1 22
 +#define SRC_SRSR 23
 +#define SRC_SISR 26
 +#define SRC_SIMR 27
 +#define SRC_SBMR2 28
 +#define SRC_GPR1 29
 +#define SRC_GPR2 30
 +#define SRC_GPR3 31
 +#define SRC_GPR4 32
 +#define SRC_GPR5 33
 +#define SRC_GPR6 34
 +#define SRC_GPR7 35
 +#define SRC_GPR8 36
 +#define SRC_GPR9 37
 +#define SRC_GPR10 38
 +#define SRC_MAX 39
 +
 +/* SRC_A7SCR1 */
 +#define R_CORE1_ENABLE_SHIFT     1
 +#define R_CORE1_ENABLE_LENGTH    1
 +/* SRC_A7SCR0 */
 +#define R_CORE1_RST_SHIFT        5
 +#define R_CORE1_RST_LENGTH       1
 +#define R_CORE0_RST_SHIFT        4
 +#define R_CORE0_RST_LENGTH       1
 +
 +#define TYPE_IMX7_SRC "imx7.src"
 +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC)
 +
 +struct IMX7SRCState {
 +    /* <private> */
 +    SysBusDevice parent_obj;
 +
 +    /* <public> */
 +    MemoryRegion iomem;
 +
 +    uint32_t regs[SRC_MAX];
 +};
 +
 +#endif /* IMX7_SRC_H */
 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx7.c
 +++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
       */
      object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 +    /*
 +     * SRC
 +     */
 +    object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC);
 +
      /*
       * ECSPIs
       */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      /*
       * SRC
       */
 -    create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
      /*
       * Watchdogs
 diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/imx7_src.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * IMX7 System Reset Controller
 + *
 + * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + *
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/misc/imx7_src.h"
 +#include "migration/vmstate.h"
 +#include "qemu/bitops.h"
 +#include "qemu/log.h"
 +#include "qemu/main-loop.h"
 +#include "qemu/module.h"
 +#include "target/arm/arm-powerctl.h"
 +#include "hw/core/cpu.h"
 +#include "hw/registerfields.h"
 +
 +#include "trace.h"
 +
 +static const char *imx7_src_reg_name(uint32_t reg)
 +{
 +    static char unknown[20];
 +
 +    switch (reg) {
 +    case SRC_SCR:
 +        return "SRC_SCR";
 +    case SRC_A7RCR0:
 +        return "SRC_A7RCR0";
 +    case SRC_A7RCR1:
 +        return "SRC_A7RCR1";
 +    case SRC_M4RCR:
 +        return "SRC_M4RCR";
 +    case SRC_ERCR:
 +        return "SRC_ERCR";
 +    case SRC_HSICPHY_RCR:
 +        return "SRC_HSICPHY_RCR";
 +    case SRC_USBOPHY1_RCR:
 +        return "SRC_USBOPHY1_RCR";
 +    case SRC_USBOPHY2_RCR:
 +        return "SRC_USBOPHY2_RCR";
 +    case SRC_PCIEPHY_RCR:
 +        return "SRC_PCIEPHY_RCR";
 +    case SRC_SBMR1:
 +        return "SRC_SBMR1";
 +    case SRC_SRSR:
 +        return "SRC_SRSR";
 +    case SRC_SISR:
 +        return "SRC_SISR";
 +    case SRC_SIMR:
 +        return "SRC_SIMR";
 +    case SRC_SBMR2:
 +        return "SRC_SBMR2";
 +    case SRC_GPR1:
 +        return "SRC_GPR1";
 +    case SRC_GPR2:
 +        return "SRC_GPR2";
 +    case SRC_GPR3:
 +        return "SRC_GPR3";
 +    case SRC_GPR4:
 +        return "SRC_GPR4";
 +    case SRC_GPR5:
 +        return "SRC_GPR5";
 +    case SRC_GPR6:
 +        return "SRC_GPR6";
 +    case SRC_GPR7:
 +        return "SRC_GPR7";
 +    case SRC_GPR8:
 +        return "SRC_GPR8";
 +    case SRC_GPR9:
 +        return "SRC_GPR9";
 +    case SRC_GPR10:
 +        return "SRC_GPR10";
 +    default:
 +        sprintf(unknown, "%u ?", reg);
 +        return unknown;
 +    }
 +}
 +
 +static const VMStateDescription vmstate_imx7_src = {
 +    .name = TYPE_IMX7_SRC,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +static void imx7_src_reset(DeviceState *dev)
 +{
 +    IMX7SRCState *s = IMX7_SRC(dev);
 +
 +    memset(s->regs, 0, sizeof(s->regs));
 +
 +    /* Set reset values */
 +    s->regs[SRC_SCR] = 0xA0;
 +    s->regs[SRC_SRSR] = 0x1;
 +    s->regs[SRC_SIMR] = 0x1F;
 +}
 +
 +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    uint32_t value = 0;
 +    IMX7SRCState *s = (IMX7SRCState *)opaque;
 +    uint32_t index = offset >> 2;
 +
 +    if (index < SRC_MAX) {
 +        value = s->regs[index];
 +    } else {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
 +    }
 +
 +    trace_imx7_src_read(imx7_src_reg_name(index), value);
 +
 +    return value;
 +}
 +
 +
 +/*
 + * The reset is asynchronous so we need to defer clearing the reset
 + * bit until the work is completed.
 + */
 +
 +struct SRCSCRResetInfo {
 +    IMX7SRCState *s;
 +    uint32_t reset_bit;
 +};
 +
 +static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
 +{
 +    struct SRCSCRResetInfo *ri = data.host_ptr;
 +    IMX7SRCState *s = ri->s;
 +
 +    assert(qemu_mutex_iothread_locked());
 +
 +    s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0);
 +
 +    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
 +
 +    g_free(ri);
 +}
 +
 +static void imx7_defer_clear_reset_bit(uint32_t cpuid,
 +                                       IMX7SRCState *s,
 +                                       uint32_t reset_shift)
 +{
 +    struct SRCSCRResetInfo *ri;
 +    CPUState *cpu = arm_get_cpu_by_id(cpuid);
 +
 +    if (!cpu) {
 +        return;
 +    }
 +
 +    ri = g_new(struct SRCSCRResetInfo, 1);
 +    ri->s = s;
 +    ri->reset_bit = reset_shift;
 +
 +    async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri));
 +}
 +
 +
 +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value,
 +                           unsigned size)
 +{
 +    IMX7SRCState *s = (IMX7SRCState *)opaque;
 +    uint32_t index = offset >> 2;
 +    long unsigned int change_mask;
 +    uint32_t current_value = value;
 +
 +    if (index >= SRC_MAX) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
 +        return;
 +    }
 +
 +    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
 +
 +    change_mask = s->regs[index] ^ (uint32_t)current_value;
 +
 +    switch (index) {
 +    case SRC_A7RCR0:
 +        if (FIELD_EX32(change_mask, CORE0, RST)) {
 +            arm_reset_cpu(0);
 +            imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT);
 +        }
 +        if (FIELD_EX32(change_mask, CORE1, RST)) {
 +            arm_reset_cpu(1);
 +            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
 +        }
 +        s->regs[index] = current_value;
 +        break;
 +    case SRC_A7RCR1:
 +        /*
 +         * On real hardware when the system reset controller starts a
 +         * secondary CPU it runs through some boot ROM code which reads
 +         * the SRC_GPRX registers controlling the start address and branches
 +         * to it.
 +         * Here we are taking a short cut and branching directly to the
 +         * requested address (we don't want to run the boot ROM code inside
 +         * QEMU)
 +         */
 +        if (FIELD_EX32(change_mask, CORE1, ENABLE)) {
 +            if (FIELD_EX32(current_value, CORE1, ENABLE)) {
 +                /* CORE 1 is brought up */
 +                arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
 +                               3, false);
 +            } else {
 +                /* CORE 1 is shut down */
 +                arm_set_cpu_off(1);
 +            }
 +            /* We clear the reset bits as the processor changed state */
 +            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
 +            clear_bit(R_CORE1_RST_SHIFT, &change_mask);
 +        }
 +        s->regs[index] = current_value;
 +        break;
 +    default:
 +        s->regs[index] = current_value;
 +        break;
 +    }
 +}
 +
 +static const struct MemoryRegionOps imx7_src_ops = {
 +    .read = imx7_src_read,
 +    .write = imx7_src_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .valid = {
 +        /*
 +         * Our device would not work correctly if the guest was doing
 +         * unaligned access. This might not be a limitation on the real
 +         * device but in practice there is no reason for a guest to access
 +         * this device unaligned.
 +         */
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +        .unaligned = false,
 +    },
 +};
 +
 +static void imx7_src_realize(DeviceState *dev, Error **errp)
 +{
 +    IMX7SRCState *s = IMX7_SRC(dev);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s,
 +                          TYPE_IMX7_SRC, 0x1000);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 +}
 +
 +static void imx7_src_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = imx7_src_realize;
 +    dc->reset = imx7_src_reset;
 +    dc->vmsd = &vmstate_imx7_src;
 +    dc->desc = "i.MX6 System Reset Controller";
 +}
 +
 +static const TypeInfo imx7_src_info = {
 +    .name          = TYPE_IMX7_SRC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(IMX7SRCState),
 +    .class_init    = imx7_src_class_init,
 +};
 +
 +static void imx7_src_register_types(void)
 +{
 +    type_register_static(&imx7_src_info);
 +}
 +
 +type_init(imx7_src_register_types)
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files(
    'imx6_src.c',
    'imx6ul_ccm.c',
    'imx7_ccm.c',
 +  'imx7_src.c',
    'imx7_gpr.c',
    'imx7_snvs.c',
    'imx_ccm.c',
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d"
  ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
  ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
 +# imx7_src.c
 +imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
 +imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
 +
  # iotkit-sysinfo.c
  iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
  iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 --
 .34.1

-New patch
+[PULL 17/24] target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
+The architecture requires (R_TYTWB) that an attempt to return from EL3
+when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
+enforces that the CPU can't ever be executing below EL3 with the
+NSE,NS bits indicating an invalid security state.)
+We were missing this check; add it.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
+---
+ target/arm/tcg/helper-a64.c | 9 +++++++++
+file changed, 9 insertions(+)
+diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/helper-a64.c
++++ b/target/arm/tcg/helper-a64.c
+@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
+         spsr &= ~PSTATE_SS;
+     }
++    /*
++     * FEAT_RME forbids return from EL3 with an invalid security state.
++     * We don't need an explicit check for FEAT_RME here because we enforce
++     * in scr_write() that you can't set the NSE bit without it.
++     */
++    if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
++        goto illegal_return;
++    }
++
+     new_el = el_from_spsr(spsr);
+     if (new_el == -1) {
+         goto illegal_return;
+--
+.34.1

-New patch
+[PULL 18/24] hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
+In the m48t59 device we almost always use 64-bit arithmetic when
+dealing with time_t deltas.  The one exception is in set_alarm(),
+which currently uses a plain 'int' to hold the difference between two
+time_t values.  Switch to int64_t instead to avoid any possible
+overflow issues.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+---
+ hw/rtc/m48t59.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/rtc/m48t59.c
++++ b/hw/rtc/m48t59.c
+@@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque)
+ static void set_alarm(M48t59State *NVRAM)
+ {
+-    int diff;
++    int64_t diff;
+     if (NVRAM->alrm_timer != NULL) {
+         timer_del(NVRAM->alrm_timer);
+         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
+--
+.34.1

-New patch
+[PULL 19/24] hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
+In the twl92230 device, use int64_t for the two state fields
+sec_offset and alm_sec, because we set these to values that
+are either time_t or differences between two time_t values.
+These fields aren't saved in vmstate anywhere, so we can
+safely widen them.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+---
+ hw/rtc/twl92230.c | 4 ++--
+file changed, 2 insertions(+), 2 deletions(-)
+diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/rtc/twl92230.c
++++ b/hw/rtc/twl92230.c
+@@ -XXX,XX +XXX,XX @@ struct MenelausState {
+         struct tm tm;
+         struct tm new;
+         struct tm alm;
+-        int sec_offset;
+-        int alm_sec;
++        int64_t sec_offset;
++        int64_t alm_sec;
+         int next_comp;
+     } rtc;
+     uint16_t rtc_next_vmstate;
+--
+.34.1

-New patch
+[PULL 20/24] hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
+In the aspeed_rtc device we store a difference between two time_t
+values in an 'int'. This is not really correct when time_t could
+be 64 bits. Enlarge the field to 'int64_t'.
+This is a migration compatibility break for the aspeed boards.
+While we are changing the vmstate, remove the accidental
+duplicate of the offset field.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
+---
+ include/hw/rtc/aspeed_rtc.h | 2 +-
+ hw/rtc/aspeed_rtc.c         | 5 ++---
+files changed, 3 insertions(+), 4 deletions(-)
+diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/rtc/aspeed_rtc.h
++++ b/include/hw/rtc/aspeed_rtc.h
+@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
+     qemu_irq irq;
+     uint32_t reg[0x18];
+-    int offset;
++    int64_t offset;
+ };
+diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/rtc/aspeed_rtc.c
++++ b/hw/rtc/aspeed_rtc.c
+@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
+ static const VMStateDescription vmstate_aspeed_rtc = {
+     .name = TYPE_ASPEED_RTC,
+-    .version_id = 1,
++    .version_id = 2,
+     .fields = (VMStateField[]) {
+         VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
+-        VMSTATE_INT32(offset, AspeedRtcState),
+-        VMSTATE_INT32(offset, AspeedRtcState),
++        VMSTATE_INT64(offset, AspeedRtcState),
+         VMSTATE_END_OF_LIST()
+     }
+ };
+--
+.34.1

-New patch
+[PULL 21/24] rtc: Use time_t for passing and returning time offsets
+The functions qemu_get_timedate() and qemu_timedate_diff() take
+and return a time offset as an integer. Coverity points out that
+means that when an RTC device implementation holds an offset
+as a time_t, as the m48t59 does, the time_t will get truncated.
+(CID 1507157, 1517772).
+The functions work with time_t internally, so make them use that type
+in their APIs.
+Note that this won't help any Y2038 issues where either the device
+model itself is keeping the offset in a 32-bit integer, or where the
+hardware under emulation has Y2038 or other rollover problems.  If we
+missed any cases of the former then hopefully Coverity will warn us
+about them since after this patch we'd be truncating a time_t in
+assignments from qemu_timedate_diff().)
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+---
+ include/sysemu/rtc.h | 4 ++--
+ softmmu/rtc.c        | 4 ++--
+files changed, 4 insertions(+), 4 deletions(-)
+diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/sysemu/rtc.h
++++ b/include/sysemu/rtc.h
+@@ -XXX,XX +XXX,XX @@
+  * The behaviour of the clock whose value this function returns will
+  * depend on the -rtc command line option passed by the user.
+  */
+-void qemu_get_timedate(struct tm *tm, int offset);
++void qemu_get_timedate(struct tm *tm, time_t offset);
+ /**
+  * qemu_timedate_diff: Return difference between a struct tm and the RTC
+@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
+  * a timestamp one hour further ahead than the current RTC time
+  * then this function will return 3600.
+  */
+-int qemu_timedate_diff(struct tm *tm);
++time_t qemu_timedate_diff(struct tm *tm);
+ #endif
+diff --git a/softmmu/rtc.c b/softmmu/rtc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/softmmu/rtc.c
++++ b/softmmu/rtc.c
+@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
+     return value;
+ }
+-void qemu_get_timedate(struct tm *tm, int offset)
++void qemu_get_timedate(struct tm *tm, time_t offset)
+ {
+     time_t ti = qemu_ref_timedate(rtc_clock);
+@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
+     }
+ }
+-int qemu_timedate_diff(struct tm *tm)
++time_t qemu_timedate_diff(struct tm *tm)
+ {
+     time_t seconds;
+--
+.34.1

-New patch
+[PULL 22/24] target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
+Where architecturally one ARM_FEATURE_X flag implies another
 ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
 set Y for it.  Currently we do this in two places -- we set a few
 flags in arm_cpu_post_init() because we need them to decide which
 properties to create on the CPU object, and then we do the rest in
 arm_cpu_realizefn().  However, this is fragile, because it's easy to
 add a new property and not notice that this means that an X-implies-Y
 check now has to move from realize to post-init.
 As a specific example, the pmsav7-dregion property is conditional
 on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
 on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
 rely on V8-implies-V7, which doesn't happen until the realizefn.
 Move all of these X-implies-Y checks into a new function, which
 we call at the top of arm_cpu_post_init(), so the feature bits
 are available at that point.
 This does now give us the reverse issue, that if there's a feature
 bit which is enabled or disabled by the setting of a property then
 then X-implies-Y features that are dependent on that property need to
 be in realize, not in this new function.  But the only one of those
 is the "EL3 implies VBAR" which is already in the right place, so
 putting things this way round seems better to me.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
 ---
  target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
 file changed, 97 insertions(+), 82 deletions(-)
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
        NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
  }
 +static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
 +{
 +    CPUARMState *env = &cpu->env;
 +    bool no_aa32 = false;
 +
 +    /*
 +     * Some features automatically imply others: set the feature
 +     * bits explicitly for these cases.
 +     */
 +
 +    if (arm_feature(env, ARM_FEATURE_M)) {
 +        set_feature(env, ARM_FEATURE_PMSA);
 +    }
 +
 +    if (arm_feature(env, ARM_FEATURE_V8)) {
 +        if (arm_feature(env, ARM_FEATURE_M)) {
 +            set_feature(env, ARM_FEATURE_V7);
 +        } else {
 +            set_feature(env, ARM_FEATURE_V7VE);
 +        }
 +    }
 +
 +    /*
 +     * There exist AArch64 cpus without AArch32 support.  When KVM
 +     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
 +     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
 +     * As a general principle, we also do not make ID register
 +     * consistency checks anywhere unless using TCG, because only
 +     * for TCG would a consistency-check failure be a QEMU bug.
 +     */
 +    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 +    }
 +
 +    if (arm_feature(env, ARM_FEATURE_V7VE)) {
 +        /*
 +         * v7 Virtualization Extensions. In real hardware this implies
 +         * EL2 and also the presence of the Security Extensions.
 +         * For QEMU, for backwards-compatibility we implement some
 +         * CPUs or CPU configs which have no actual EL2 or EL3 but do
 +         * include the various other features that V7VE implies.
 +         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 +         * Security Extensions is ARM_FEATURE_EL3.
 +         */
 +        assert(!tcg_enabled() || no_aa32 ||
 +               cpu_isar_feature(aa32_arm_div, cpu));
 +        set_feature(env, ARM_FEATURE_LPAE);
 +        set_feature(env, ARM_FEATURE_V7);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V7)) {
 +        set_feature(env, ARM_FEATURE_VAPA);
 +        set_feature(env, ARM_FEATURE_THUMB2);
 +        set_feature(env, ARM_FEATURE_MPIDR);
 +        if (!arm_feature(env, ARM_FEATURE_M)) {
 +            set_feature(env, ARM_FEATURE_V6K);
 +        } else {
 +            set_feature(env, ARM_FEATURE_V6);
 +        }
 +
 +        /*
 +         * Always define VBAR for V7 CPUs even if it doesn't exist in
 +         * non-EL3 configs. This is needed by some legacy boards.
 +         */
 +        set_feature(env, ARM_FEATURE_VBAR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V6K)) {
 +        set_feature(env, ARM_FEATURE_V6);
 +        set_feature(env, ARM_FEATURE_MVFR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V6)) {
 +        set_feature(env, ARM_FEATURE_V5);
 +        if (!arm_feature(env, ARM_FEATURE_M)) {
 +            assert(!tcg_enabled() || no_aa32 ||
 +                   cpu_isar_feature(aa32_jazelle, cpu));
 +            set_feature(env, ARM_FEATURE_AUXCR);
 +        }
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V5)) {
 +        set_feature(env, ARM_FEATURE_V4T);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_LPAE)) {
 +        set_feature(env, ARM_FEATURE_V7MP);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 +        set_feature(env, ARM_FEATURE_CBAR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 +        !arm_feature(env, ARM_FEATURE_M)) {
 +        set_feature(env, ARM_FEATURE_THUMB_DSP);
 +    }
 +}
 +
  void arm_cpu_post_init(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
 -    /* M profile implies PMSA. We have to do this here rather than
 -     * in realize with the other feature-implication checks because
 -     * we look at the PMSA bit to see if we should add some properties.
 +    /*
 +     * Some features imply others. Figure this out now, because we
 +     * are going to look at the feature bits in deciding which
 +     * properties to add.
       */
 -    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
 -        set_feature(&cpu->env, ARM_FEATURE_PMSA);
 -    }
 +    arm_cpu_propagate_feature_implications(cpu);
      if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
          arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
      CPUARMState *env = &cpu->env;
      int pagebits;
      Error *local_err = NULL;
 -    bool no_aa32 = false;
      /* Use pc-relative instructions in system-mode */
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          cpu->isar.id_isar3 = u;
      }
 -    /* Some features automatically imply others: */
 -    if (arm_feature(env, ARM_FEATURE_V8)) {
 -        if (arm_feature(env, ARM_FEATURE_M)) {
 -            set_feature(env, ARM_FEATURE_V7);
 -        } else {
 -            set_feature(env, ARM_FEATURE_V7VE);
 -        }
 -    }
 -
 -    /*
 -     * There exist AArch64 cpus without AArch32 support.  When KVM
 -     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
 -     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
 -     * As a general principle, we also do not make ID register
 -     * consistency checks anywhere unless using TCG, because only
 -     * for TCG would a consistency-check failure be a QEMU bug.
 -     */
 -    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 -        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 -    }
 -
 -    if (arm_feature(env, ARM_FEATURE_V7VE)) {
 -        /* v7 Virtualization Extensions. In real hardware this implies
 -         * EL2 and also the presence of the Security Extensions.
 -         * For QEMU, for backwards-compatibility we implement some
 -         * CPUs or CPU configs which have no actual EL2 or EL3 but do
 -         * include the various other features that V7VE implies.
 -         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 -         * Security Extensions is ARM_FEATURE_EL3.
 -         */
 -        assert(!tcg_enabled() || no_aa32 ||
 -               cpu_isar_feature(aa32_arm_div, cpu));
 -        set_feature(env, ARM_FEATURE_LPAE);
 -        set_feature(env, ARM_FEATURE_V7);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V7)) {
 -        set_feature(env, ARM_FEATURE_VAPA);
 -        set_feature(env, ARM_FEATURE_THUMB2);
 -        set_feature(env, ARM_FEATURE_MPIDR);
 -        if (!arm_feature(env, ARM_FEATURE_M)) {
 -            set_feature(env, ARM_FEATURE_V6K);
 -        } else {
 -            set_feature(env, ARM_FEATURE_V6);
 -        }
 -
 -        /* Always define VBAR for V7 CPUs even if it doesn't exist in
 -         * non-EL3 configs. This is needed by some legacy boards.
 -         */
 -        set_feature(env, ARM_FEATURE_VBAR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V6K)) {
 -        set_feature(env, ARM_FEATURE_V6);
 -        set_feature(env, ARM_FEATURE_MVFR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V6)) {
 -        set_feature(env, ARM_FEATURE_V5);
 -        if (!arm_feature(env, ARM_FEATURE_M)) {
 -            assert(!tcg_enabled() || no_aa32 ||
 -                   cpu_isar_feature(aa32_jazelle, cpu));
 -            set_feature(env, ARM_FEATURE_AUXCR);
 -        }
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V5)) {
 -        set_feature(env, ARM_FEATURE_V4T);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_LPAE)) {
 -        set_feature(env, ARM_FEATURE_V7MP);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 -        set_feature(env, ARM_FEATURE_CBAR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 -        !arm_feature(env, ARM_FEATURE_M)) {
 -        set_feature(env, ARM_FEATURE_THUMB_DSP);
 -    }
      /*
       * We rely on no XScale CPU having VFP so we can use the same bits in the
 --
 .34.1

-New patch
+[PULL 23/24] hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
+M-profile CPUs generally allow configuration of the number of MPU
+regions that they have.  We don't currently model this, so our
+implementations of some of the board models provide CPUs with the
+wrong number of regions.  RTOSes like Zephyr that hardcode the
+expected number of regions may therefore not run on the model if they
+are set up to run on real hardware.
+Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
+matching the ability of hardware to configure the number of Secure
+and NonSecure regions separately.  Our actual CPU implementation
+doesn't currently support that, and it happens that none of the MPS
+boards we model set the number of regions differently for Secure vs
+NonSecure, so we provide an interface to the boards and SoCs that
+won't need to change if we ever do add that functionality in future,
+but make it an error to configure the two properties to different
+values.
+(The property name on the CPU is the somewhat misnamed-for-M-profile
+"pmsav7-dregion", so we don't follow that naming convention for
+the properties here. The TRM doesn't say what the CPU configuration
+variable names are, so we pick something, and follow the lowercase
+convention we already have for properties here.)
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
+---
+ include/hw/arm/armv7m.h |  8 ++++++++
+ hw/arm/armv7m.c         | 21 +++++++++++++++++++++
+files changed, 29 insertions(+)
+diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/armv7m.h
++++ b/include/hw/arm/armv7m.h
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
+  * + Property "vfp": enable VFP (forwarded to CPU object)
+  * + Property "dsp": enable DSP (forwarded to CPU object)
+  * + Property "enable-bitband": expose bitbanded IO
++ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
++ *   to CPU object pmsav7-dregion property; default is whatever the default
++ *   for the CPU is)
++ * + Property "mpu-s-regions": number of Secure MPU regions (default is
++ *   whatever the default for the CPU is; must currently be set to the same
++ *   value as mpu-ns-regions if the CPU implements the Security Extension)
+  * + Clock input "refclk" is the external reference clock for the systick timers
+  * + Clock input "cpuclk" is the main CPU clock
+  */
+@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
+     Object *idau;
+     uint32_t init_svtor;
+     uint32_t init_nsvtor;
++    uint32_t mpu_ns_regions;
++    uint32_t mpu_s_regions;
+     bool enable_bitband;
+     bool start_powered_off;
+     bool vfp;
+diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/armv7m.c
++++ b/hw/arm/armv7m.c
+@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
+         }
+     }
++    /*
++     * Real M-profile hardware can be configured with a different number of
++     * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
++     * support that yet, so catch attempts to select that.
++     */
++    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
++        s->mpu_ns_regions != s->mpu_s_regions) {
++        error_setg(errp,
++                   "mpu-ns-regions and mpu-s-regions properties must have the same value");
++        return;
++    }
++    if (s->mpu_ns_regions != UINT_MAX &&
++        object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
++        if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
++                                      s->mpu_ns_regions, errp)) {
++            return;
++        }
++    }
++
+     /*
+      * Tell the CPU where the NVIC is; it will fail realize if it doesn't
+      * have one. Similarly, tell the NVIC where its CPU is.
+@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
+                      false),
+     DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
+     DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
++    DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
++    DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
+     DEFINE_PROP_END_OF_LIST(),
+ };
+--
+.34.1

-New patch
+[PULL 24/24] hw/arm: Set number of MPU regions correctly for an505, an521, an524
+The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
 MPS2/MPS3 FPGA images don't override these except in the case of
 AN547, which uses 16 MPU regions.
 Define properties on the ARMSSE object for the MPU regions (using the
 same names as the documented RTL configuration settings, and
 following the pattern we already have for this device of using
 all-caps names as the RTL does), and set them in the board code.
 We don't actually need to override the default except on AN547,
 but it's simpler code to have the board code set them always
 rather than tracking which board subtypes want to set them to
 a non-default value separately from what that value is.
 Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
 we now correctly use 8 MPU regions, while mps3-an547 stays at its
 current 16 regions.
 It's possible some guest code wrongly depended on the previous
 incorrectly modeled number of memory regions. (Such guest code
 should ideally check the number of regions via the MPU_TYPE
 register.) The old behaviour can be obtained with additional
 -global arguments to QEMU:
 For mps2-an521 and mps2-an524:
  -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16
 For mps2-an505:
  -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16
 NB that the way the implementation allows this use of -global
 is slightly fragile: if the board code explicitly sets the
 properties on the sse-200 object, this overrides the -global
 command line option. So we rely on:
  - the boards that need fixing all happen to use the SSE defaults
  - we can write the board code to only set the property if it
    is different from the default, rather than having all boards
    explicitly set the property
  - the board that does need to use a non-default value happens
    to need to set it to the same value (16) we previously used
 This works, but there are some kinds of refactoring of the
 mps2-tz.c code that would break the support for -global here.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
 ---
  include/hw/arm/armsse.h |  5 +++++
  hw/arm/armsse.c         | 16 ++++++++++++++++
  hw/arm/mps2-tz.c        | 29 +++++++++++++++++++++++++++++
 files changed, 50 insertions(+)
 diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/armsse.h
 +++ b/include/hw/arm/armsse.h
@@ -XXX,XX +XXX,XX @@
   *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
   *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
   *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
 + *  + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
 + *    which set the number of MPU regions on the CPUs. If there is only one
 + *    CPU the CPU1 properties are not present.
   *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
   *    which are wired to its NVIC lines 32 .. n+32
   *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
      uint32_t exp_numirq;
      uint32_t sram_addr_width;
      uint32_t init_svtor;
 +    uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
 +    uint32_t cpu_mpu_s[SSE_MAX_CPUS];
      bool cpu_fpu[SSE_MAX_CPUS];
      bool cpu_dsp[SSE_MAX_CPUS];
  };
 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/armsse.c
 +++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
      DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
      DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
      DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
 +    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
 +    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
      DEFINE_PROP_END_OF_LIST()
  };
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
      DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
      DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
      DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
 +    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
 +    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
 +    DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
 +    DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
      DEFINE_PROP_END_OF_LIST()
  };
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
      DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
      DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
      DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
 +    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
 +    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
      DEFINE_PROP_END_OF_LIST()
  };
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                  return;
              }
          }
 +        if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
 +                                      s->cpu_mpu_ns[i], errp)) {
 +            return;
 +        }
 +        if (!object_property_set_uint(cpuobj, "mpu-s-regions",
 +                                      s->cpu_mpu_s[i], errp)) {
 +            return;
 +        }
          if (i > 0) {
              memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/mps2-tz.c
 +++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
      int uart_overflow_irq; /* number of the combined UART overflow IRQ */
      uint32_t init_svtor; /* init-svtor setting for SSE */
      uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
 +    uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
 +    uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
 +    uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
 +    uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
      const RAMInfo *raminfo;
      const char *armsse_type;
      uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
  #define MPS3_DDR_SIZE (2 * GiB)
  #endif
 +/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
 +#define MPU_REGION_DEFAULT UINT32_MAX
 +
  static const uint32_t an505_oscclk[] = {
      40000000,
      24580000,
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                               OBJECT(system_memory), &error_abort);
      qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
      qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
 +    if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
 +        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
 +    }
 +    if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
 +        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
 +    }
 +    if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
 +        if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
 +            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
 +        }
 +        if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
 +            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
 +        }
 +    }
      qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
      qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
      qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
      IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
 +    MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
      mc->init = mps2tz_common_init;
      mc->reset = mps2_machine_reset;
      iic->check = mps2_tz_idau_check;
 +
 +    /* Most machines leave these at the SSE defaults */
 +    mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
 +    mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
 +    mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
 +    mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
  }
  static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
      mmc->numirq = 96;
      mmc->uart_overflow_irq = 48;
      mmc->init_svtor = 0x00000000;
 +    mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
      mmc->sram_addr_width = 21;
      mmc->raminfo = an547_raminfo;
      mmc->armsse_type = TYPE_SSE300;
 --
 .34.1

Target-arm queue for rc2 -- just some minor bugfixes.

thanks
-- PMM

The following changes since commit 6e5d4999c761ffa082f60d72a14e5c953515b417:

Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-11-19' into staging (2019-11-19 11:29:01 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191119

for you to fetch changes up to 04c9c81b8fa2ee33f59a26265700fae6fc646062:

target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY (2019-11-19 13:20:28 +0000)

----------------------------------------------------------------
target-arm queue:
 * Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
 * Relax r13 restriction for ldrex/strex for v8.0
 * Do not reject rt == rt2 for strexd
 * net/cadence_gem: Set PHY autonegotiation restart status
 * ssi: xilinx_spips: Skip spi bus update for a few register writes
 * pl031: Expose RTCICR as proper WC register

----------------------------------------------------------------
Alexander Graf (1):
      pl031: Expose RTCICR as proper WC register

Linus Ziegert (1):
      net/cadence_gem: Set PHY autonegotiation restart status

Richard Henderson (4):
      target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller
      target/arm: Do not reject rt == rt2 for strexd
      target/arm: Relax r13 restriction for ldrex/strex for v8.0
      target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY

Sai Pavan Boddu (1):
      ssi: xilinx_spips: Skip spi bus update for a few register writes

From: Alexander Graf <graf@amazon.com>

The current PL031 RTCICR register implementation always clears the
IRQ pending status on a register write, regardless of the value the
guest writes.

To justify that behavior, it references the ARM926EJ-S Development
Chip Reference Manual (DDI0287B) and indicates that said document
states that any write clears the internal IRQ state.  It is indeed
true that in section 11.1 this document says:

"The interrupt is cleared by writing any data value to the
   interrupt clear register RTCICR".

However, later in section 11.2.2 it contradicts itself by saying:

"Writing 1 to bit 0 of RTCICR clears the RTCINTR flag."

The latter statement matches the PL031 TRM (DDI0224C), which says:

"Writing 1 to bit position 0 clears the corresponding interrupt.
   Writing 0 has no effect."

Let's assume that the self-contradictory DDI0287B is in error, and
follow the reference manual for the device itself, by making the
register write-one-to-clear.

Reported-by: Hendrik Borghorst <hborghor@amazon.de>
Signed-off-by: Alexander Graf <graf@amazon.com>
Message-id: 20191104115228.30745-1-graf@amazon.com
[PMM: updated commit message to note that DDI0287B says two
 conflicting things]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/rtc/pl031.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/rtc/pl031.c
+++ b/hw/rtc/pl031.c
@@ -XXX,XX +XXX,XX @@ static void pl031_write(void * opaque, hwaddr offset,
         pl031_update(s);
         break;
     case RTC_ICR:
-        /* The PL031 documentation (DDI0224B) states that the interrupt is
-           cleared when bit 0 of the written value is set.  However the
-           arm926e documentation (DDI0287B) states that the interrupt is
-           cleared when any value is written.  */
-        s->is = 0;
+        s->is &= ~value;
         pl031_update(s);
         break;
     case RTC_CR:
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Coverity reports, in sve_zcr_get_valid_len,

"Subtract operation overflows on operands
arm_cpu_vq_map_next_smaller(cpu, start_vq + 1U) and 1U"

First, the aarch32 stub version of arm_cpu_vq_map_next_smaller,
returning 0, does exactly what Coverity reports.  Remove it.

Second, the aarch64 version of arm_cpu_vq_map_next_smaller has
a set of asserts, but they don't cover the case in question.
Further, there is a fair amount of extra arithmetic needed to
convert from the 0-based zcr register, to the 1-base vq form,
to the 0-based bitmap, and back again.  This can be simplified
by leaving the value in the 0-based form.

Finally, use test_bit to simplify the common case, where the
length in the zcr registers is in fact a supported length.

Reported-by: Coverity (CID 1407217)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20191118091414.19440-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h    |  3 ---
 target/arm/cpu64.c  | 15 ---------------
 target/arm/helper.c |  9 +++++++--
 3 files changed, 7 insertions(+), 20 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ typedef struct {
 #ifdef TARGET_AARCH64
 # define ARM_MAX_VQ    16
 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
-uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);
 #else
 # define ARM_MAX_VQ    1
 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
-static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
-{ return 0; }
 #endif
 
 typedef struct ARMVectorReg {
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
     cpu->sve_max_vq = max_vq;
 }
 
-uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
-{
-    uint32_t bitnum;
-
-    /*
-     * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
-     * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
-     * function always returns the next smaller than the input.
-     */
-    assert(vq && vq <= ARM_MAX_VQ + 1);
-
-    bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
-    return bitnum == vq - 1 ? 0 : bitnum + 1;
-}
-
 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
                                    void *opaque, Error **errp)
 {
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
 
 static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
 {
-    uint32_t start_vq = (start_len & 0xf) + 1;
+    uint32_t end_len;
 
-    return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1;
+    end_len = start_len &= 0xf;
+    if (!test_bit(start_len, cpu->sve_vq_map)) {
+        end_len = find_last_bit(cpu->sve_vq_map, start_len);
+        assert(end_len < start_len);
+    }
+    return end_len;
 }
 
 /*
-- 
2.20.1

From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

A few configuration register writes need not update the spi bus state, so just
return after the register write.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1573830705-14579-1-git-send-email-sai.pavan.boddu@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -XXX,XX +XXX,XX @@
 #define R_GPIO              (0x30 / 4)
 #define R_LPBK_DLY_ADJ      (0x38 / 4)
 #define R_LPBK_DLY_ADJ_RESET (0x33)
+#define R_IOU_TAPDLY_BYPASS (0x3C / 4)
 #define R_TXD1              (0x80 / 4)
 #define R_TXD2              (0x84 / 4)
 #define R_TXD3              (0x88 / 4)
@@ -XXX,XX +XXX,XX @@
 #define R_LQSPI_STS         (0xA4 / 4)
 #define LQSPI_STS_WR_RECVD      (1 << 1)
 
+#define R_DUMMY_CYCLE_EN    (0xC8 / 4)
+#define R_ECO               (0xF8 / 4)
 #define R_MOD_ID            (0xFC / 4)
 
 #define R_GQSPI_SELECT          (0x144 / 4)
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
 {
     int mask = ~0;
     XilinxSPIPS *s = opaque;
+    bool try_flush = true;
 
     DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
     addr >>= 2;
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
         tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,
                       s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
         goto no_reg_update;
+    /* Skip SPI bus update for below registers writes */
+    case R_GPIO:
+    case R_LPBK_DLY_ADJ:
+    case R_IOU_TAPDLY_BYPASS:
+    case R_DUMMY_CYCLE_EN:
+    case R_ECO:
+        try_flush = false;
+        break;
     }
     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
 no_reg_update:
-    xilinx_spips_update_cs_lines(s);
-    xilinx_spips_check_flush(s);
-    xilinx_spips_update_cs_lines(s);
-    xilinx_spips_update_ixr(s);
+    if (try_flush) {
+        xilinx_spips_update_cs_lines(s);
+        xilinx_spips_check_flush(s);
+        xilinx_spips_update_cs_lines(s);
+        xilinx_spips_update_ixr(s);
+    }
 }
 
 static const MemoryRegionOps spips_ops = {
-- 
2.20.1

From: Linus Ziegert <linus.ziegert+qemu@holoplot.com>

The Linux kernel PHY driver sets AN_RESTART in the BMCR of the
PHY when autonegotiation is started.
Recently the kernel started to read back the PHY's AN_RESTART
bit and now checks whether the autonegotiation is complete and
the bit was cleared [1]. Otherwise the link status is down.

The emulated PHY needs to clear AN_RESTART immediately to inform
the kernel driver about the completion of autonegotiation phase.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c36757eb9dee

Signed-off-by: Linus Ziegert <linus.ziegert+qemu@holoplot.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20191104181604.21943-1-linus.ziegert+qemu@holoplot.com
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/net/cadence_gem.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -XXX,XX +XXX,XX @@
 #define PHY_REG_EXT_PHYSPCFC_ST   27
 #define PHY_REG_CABLE_DIAG   28
 
-#define PHY_REG_CONTROL_RST  0x8000
-#define PHY_REG_CONTROL_LOOP 0x4000
-#define PHY_REG_CONTROL_ANEG 0x1000
+#define PHY_REG_CONTROL_RST       0x8000
+#define PHY_REG_CONTROL_LOOP      0x4000
+#define PHY_REG_CONTROL_ANEG      0x1000
+#define PHY_REG_CONTROL_ANRESTART 0x0200
 
 #define PHY_REG_STATUS_LINK     0x0004
 #define PHY_REG_STATUS_ANEGCMPL 0x0020
@@ -XXX,XX +XXX,XX @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
         }
         if (val & PHY_REG_CONTROL_ANEG) {
             /* Complete autonegotiation immediately */
-            val &= ~PHY_REG_CONTROL_ANEG;
+            val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART);
             s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
         }
         if (val & PHY_REG_CONTROL_LOOP) {
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

There was too much cut and paste between ldrexd and strexd,
as ldrexd does prohibit two output registers the same.

Fixes: af288228995
Reported-by: Michael Goffioul <michael.goffioul@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191117090621.32425-2-richard.henderson@linaro.org
Reviewed-by: Robert Foley <robert.foley@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
         || (s->thumb && (a->rd == 13 || a->rt == 13))
         || (mop == MO_64
             && (a->rt2 == 15
-                || a->rd == a->rt2 || a->rt == a->rt2
+                || a->rd == a->rt2
                 || (s->thumb && a->rt2 == 13)))) {
         unallocated_encoding(s);
         return true;
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Armv8-A removes UNPREDICTABLE for R13 for these cases.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191117090621.32425-3-richard.henderson@linaro.org
[PMM: changed ENABLE_ARCH_8 checks to check a new bool 'v8a',
 since these cases are still UNPREDICTABLE for v8M]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_SWPB(DisasContext *s, arg_SWP *a)
 static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
 {
     TCGv_i32 addr;
+    /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
+    bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
 
     /* We UNDEF for these UNPREDICTABLE cases.  */
     if (a->rd == 15 || a->rn == 15 || a->rt == 15
         || a->rd == a->rn || a->rd == a->rt
-        || (s->thumb && (a->rd == 13 || a->rt == 13))
+        || (!v8a && s->thumb && (a->rd == 13 || a->rt == 13))
         || (mop == MO_64
             && (a->rt2 == 15
                 || a->rd == a->rt2
-                || (s->thumb && a->rt2 == 13)))) {
+                || (!v8a && s->thumb && a->rt2 == 13)))) {
         unallocated_encoding(s);
         return true;
     }
@@ -XXX,XX +XXX,XX @@ static bool trans_STLH(DisasContext *s, arg_STL *a)
 static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq)
 {
     TCGv_i32 addr;
+    /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
+    bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
 
     /* We UNDEF for these UNPREDICTABLE cases.  */
     if (a->rn == 15 || a->rt == 15
-        || (s->thumb && a->rt == 13)
+        || (!v8a && s->thumb && a->rt == 13)
         || (mop == MO_64
             && (a->rt2 == 15 || a->rt == a->rt2
-                || (s->thumb && a->rt2 == 13)))) {
+                || (!v8a && s->thumb && a->rt2 == 13)))) {
         unallocated_encoding(s);
         return true;
     }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Simply moving the non-stub helper_v7m_mrs/msr outside of
!CONFIG_USER_ONLY is not an option, because of all of the
other system-mode helpers that are called.

But we can split out a few subroutines to handle the few
EL0 accessible registers without duplicating code.

Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191118194916.3670-1-richard.henderson@linaro.org
[PMM: deleted now-redundant comment; added a default case
 to switch in v7m_msr helper]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h      |   2 +
 target/arm/m_helper.c | 114 ++++++++++++++++++++++++++----------------
 2 files changed, 73 insertions(+), 43 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
     if (mask & XPSR_GE) {
         env->GE = (val & XPSR_GE) >> 16;
     }
+#ifndef CONFIG_USER_ONLY
     if (mask & XPSR_T) {
         env->thumb = ((val & XPSR_T) != 0);
     }
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
         /* Note that this only happens on exception exit */
         write_v7m_exception(env, val & XPSR_EXCP);
     }
+#endif
 }
 
 #define HCR_VM        (1ULL << 0)
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@
 #include "exec/cpu_ldst.h"
 #endif
 
+static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
+                         uint32_t reg, uint32_t val)
+{
+    /* Only APSR is actually writable */
+    if (!(reg & 4)) {
+        uint32_t apsrmask = 0;
+
+        if (mask & 8) {
+            apsrmask |= XPSR_NZCV | XPSR_Q;
+        }
+        if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
+            apsrmask |= XPSR_GE;
+        }
+        xpsr_write(env, val, apsrmask);
+    }
+}
+
+static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
+{
+    uint32_t mask = 0;
+
+    if ((reg & 1) && el) {
+        mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
+    }
+    if (!(reg & 4)) {
+        mask |= XPSR_NZCV | XPSR_Q; /* APSR */
+        if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
+            mask |= XPSR_GE;
+        }
+    }
+    /* EPSR reads as zero */
+    return xpsr_read(env) & mask;
+}
+
+static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
+{
+    uint32_t value = env->v7m.control[secure];
+
+    if (!secure) {
+        /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
+        value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK;
+    }
+    return value;
+}
+
 #ifdef CONFIG_USER_ONLY
 
-/* These should probably raise undefined insn exceptions.  */
-void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
 {
-    ARMCPU *cpu = env_archcpu(env);
+    uint32_t mask = extract32(maskreg, 8, 4);
+    uint32_t reg = extract32(maskreg, 0, 8);
 
-    cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
+    switch (reg) {
+    case 0 ... 7: /* xPSR sub-fields */
+        v7m_msr_xpsr(env, mask, reg, val);
+        break;
+    case 20: /* CONTROL */
+        /* There are no sub-fields that are actually writable from EL0. */
+        break;
+    default:
+        /* Unprivileged writes to other registers are ignored */
+        break;
+    }
 }
 
 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
 {
-    ARMCPU *cpu = env_archcpu(env);
-
-    cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
-    return 0;
+    switch (reg) {
+    case 0 ... 7: /* xPSR sub-fields */
+        return v7m_mrs_xpsr(env, reg, 0);
+    case 20: /* CONTROL */
+        return v7m_mrs_control(env, 0);
+    default:
+        /* Unprivileged reads others as zero.  */
+        return 0;
+    }
 }
 
 void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
 
 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
 {
-    uint32_t mask;
     unsigned el = arm_current_el(env);
 
     /* First handle registers which unprivileged can read */
-
     switch (reg) {
     case 0 ... 7: /* xPSR sub-fields */
-        mask = 0;
-        if ((reg & 1) && el) {
-            mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
-        }
-        if (!(reg & 4)) {
-            mask |= XPSR_NZCV | XPSR_Q; /* APSR */
-            if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
-                mask |= XPSR_GE;
-            }
-        }
-        /* EPSR reads as zero */
-        return xpsr_read(env) & mask;
-        break;
+        return v7m_mrs_xpsr(env, reg, el);
     case 20: /* CONTROL */
-    {
-        uint32_t value = env->v7m.control[env->v7m.secure];
-        if (!env->v7m.secure) {
-            /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
-            value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK;
-        }
-        return value;
-    }
+        return v7m_mrs_control(env, env->v7m.secure);
     case 0x94: /* CONTROL_NS */
         /*
          * We have to handle this here because unprivileged Secure code
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
 
     switch (reg) {
     case 0 ... 7: /* xPSR sub-fields */
-        /* only APSR is actually writable */
-        if (!(reg & 4)) {
-            uint32_t apsrmask = 0;
-
-            if (mask & 8) {
-                apsrmask |= XPSR_NZCV | XPSR_Q;
-            }
-            if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
-                apsrmask |= XPSR_GE;
-            }
-            xpsr_write(env, val, apsrmask);
-        }
+        v7m_msr_xpsr(env, mask, reg, val);
         break;
     case 8: /* MSP */
         if (v7m_using_psp(env)) {
-- 
2.20.1

Hi; here's the latest round of arm patches. I have included also
my patchset for the RTC devices to avoid keeping time_t and
time_t diffs in 32-bit variables.

thanks
-- PMM

The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:

Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831

for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:

hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)

----------------------------------------------------------------
target-arm queue:
 * Some of the preliminary patches for Cortex-A710 support
 * i.MX7 and i.MX6UL refactoring
 * Implement SRC device for i.MX7
 * Catch illegal-exception-return from EL3 with bad NSE/NS
 * Use 64-bit offsets for holding time_t differences in RTC devices
 * Model correct number of MPU regions for an505, an521, an524 boards

----------------------------------------------------------------
Alex Bennée (1):
      target/arm: properly document FEAT_CRC32

Jean-Christophe Dubois (6):
      Remove i.MX7 IOMUX GPR device from i.MX6UL
      Refactor i.MX6UL processor code
      Add i.MX6UL missing devices.
      Refactor i.MX7 processor code
      Add i.MX7 missing TZ devices and memory regions
      Add i.MX7 SRC device implementation

Peter Maydell (8):
      target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
      hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
      hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
      hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
      rtc: Use time_t for passing and returning time offsets
      target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
      hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
      hw/arm: Set number of MPU regions correctly for an505, an521, an524

Richard Henderson (9):
      target/arm: Reduce dcz_blocksize to uint8_t
      target/arm: Allow cpu to configure GM blocksize
      target/arm: Support more GM blocksizes
      target/arm: When tag memory is not present, set MTE=1
      target/arm: Introduce make_ccsidr64
      target/arm: Apply access checks to neoverse-n1 special registers
      target/arm: Apply access checks to neoverse-v1 special registers
      target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
      target/arm: Implement FEAT_HPDS2 as a no-op

From: Richard Henderson <richard.henderson@linaro.org>

Previously we hard-coded the blocksize with GMID_EL1_BS.
But the value we choose for -cpu max does not match the
value that cortex-a710 uses.

Mirror the way we handle dcz_blocksize.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h               |  2 ++
 target/arm/internals.h         |  6 -----
 target/arm/tcg/translate.h     |  2 ++
 target/arm/helper.c            | 11 +++++---
 target/arm/tcg/cpu64.c         |  1 +
 target/arm/tcg/mte_helper.c    | 46 ++++++++++++++++++++++------------
 target/arm/tcg/translate-a64.c |  5 ++--
 7 files changed, 45 insertions(+), 28 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
 
     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
     uint8_t dcz_blocksize;
+    /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
+    uint8_t gm_blocksize;
 
     uint64_t rvbar_prop; /* Property/input signals.  */
 
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
 
 #endif /* !CONFIG_USER_ONLY */
 
-/*
- * The log2 of the words in the tag block, for GMID_EL1.BS.
- * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
- */
-#define GMID_EL1_BS  6
-
 /*
  * SVE predicates are 1/8 the size of SVE vectors, and cannot use
  * the same simd_desc() encoding due to restrictions on size.
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     int8_t btype;
     /* A copy of cpu->dcz_blocksize. */
     uint8_t dcz_blocksize;
+    /* A copy of cpu->gm_blocksize. */
+    uint8_t gm_blocksize;
     /* True if this page is guarded.  */
     bool guarded_page;
     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
       .access = PL1_RW, .accessfn = access_mte,
       .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
-    { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
-      .access = PL1_R, .accessfn = access_aa64_tid5,
-      .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
     { .name = "TCO", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
       .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      * then define only a RAZ/WI version of PSTATE.TCO.
      */
     if (cpu_isar_feature(aa64_mte, cpu)) {
+        ARMCPRegInfo gmid_reginfo = {
+            .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
+            .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
+            .access = PL1_R, .accessfn = access_aa64_tid5,
+            .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
+        };
+        define_one_arm_cp_reg(cpu, &gmid_reginfo);
         define_arm_cp_regs(cpu, mte_reginfo);
         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
     } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
     cpu->dcz_blocksize = 7; /*  512 bytes */
 #endif
+    cpu->gm_blocksize = 6;  /*  256 bytes */
 
     cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
     cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
     }
 }
 
-#define LDGM_STGM_SIZE  (4 << GMID_EL1_BS)
-
 uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 {
     int mmu_idx = cpu_mmu_index(env, false);
     uintptr_t ra = GETPC();
+    int gm_bs = env_archcpu(env)->gm_blocksize;
+    int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
 
-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
+    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
     /* Trap if accessing an invalid page.  */
     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
+                                 gm_bs_bytes, MMU_DATA_LOAD,
+                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
 
     /* The tag is squashed to zero if the page does not support tags.  */
     if (!tag_mem) {
         return 0;
     }
 
-    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
     /*
-     * We are loading 64-bits worth of tags.  The ordering of elements
-     * within the word corresponds to a 64-bit little-endian operation.
+     * The ordering of elements within the word corresponds to
+     * a little-endian operation.
      */
-    return ldq_le_p(tag_mem);
+    switch (gm_bs) {
+    case 6:
+        /* 256 bytes -> 16 tags -> 64 result bits */
+        return ldq_le_p(tag_mem);
+    default:
+        /* cpu configured with unsupported gm blocksize. */
+        g_assert_not_reached();
+    }
 }
 
 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
 {
     int mmu_idx = cpu_mmu_index(env, false);
     uintptr_t ra = GETPC();
+    int gm_bs = env_archcpu(env)->gm_blocksize;
+    int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
 
-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
+    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
     /* Trap if accessing an invalid page.  */
     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
+                                 gm_bs_bytes, MMU_DATA_LOAD,
+                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
 
     /*
      * Tag store only happens if the page support tags,
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
         return;
     }
 
-    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
     /*
-     * We are storing 64-bits worth of tags.  The ordering of elements
-     * within the word corresponds to a 64-bit little-endian operation.
+     * The ordering of elements within the word corresponds to
+     * a little-endian operation.
      */
-    stq_le_p(tag_mem, val);
+    switch (gm_bs) {
+    case 6:
+        stq_le_p(tag_mem, val);
+        break;
+    default:
+        /* cpu configured with unsupported gm blocksize. */
+        g_assert_not_reached();
+    }
 }
 
 void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
         gen_helper_stgm(cpu_env, addr, tcg_rt);
     } else {
         MMUAccessType acc = MMU_DATA_STORE;
-        int size = 4 << GMID_EL1_BS;
+        int size = 4 << s->gm_blocksize;
 
         clean_addr = clean_data_tbi(s, addr);
         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
         gen_helper_ldgm(tcg_rt, cpu_env, addr);
     } else {
         MMUAccessType acc = MMU_DATA_LOAD;
-        int size = 4 << GMID_EL1_BS;
+        int size = 4 << s->gm_blocksize;
 
         clean_addr = clean_data_tbi(s, addr);
         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->cp_regs = arm_cpu->cp_regs;
     dc->features = env->features;
     dc->dcz_blocksize = arm_cpu->dcz_blocksize;
+    dc->gm_blocksize = arm_cpu->gm_blocksize;
 
 #ifdef CONFIG_USER_ONLY
     /* In sve_probe_page, we assume TBI is enabled. */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Support all of the easy GM block sizes.
Use direct memory operations, since the pointers are aligned.

While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
an atomic store of one nibble.  This is not difficult, but there
is also no point in supporting it until required.

Note that cortex-a710 sets GM blocksize to match its cacheline
size of 64 bytes.  I expect many implementations will also
match the cacheline, which makes 16 bytes very unlikely.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c            | 18 +++++++++---
 target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
 2 files changed, 62 insertions(+), 12 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
                                        ID_PFR1, VIRTUALIZATION, 0);
     }
 
+    if (cpu_isar_feature(aa64_mte, cpu)) {
+        /*
+         * The architectural range of GM blocksize is 2-6, however qemu
+         * doesn't support blocksize of 2 (see HELPER(ldgm)).
+         */
+        if (tcg_enabled()) {
+            assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
+        }
+
 #ifndef CONFIG_USER_ONLY
-    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
         /*
          * Disable the MTE feature bits if we do not have tag-memory
          * provided by the machine.
          */
-        cpu->isar.id_aa64pfr1 =
-            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
-    }
+        if (cpu->tag_memory == NULL) {
+            cpu->isar.id_aa64pfr1 =
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+        }
 #endif
+    }
 
     if (tcg_enabled()) {
         /*
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
     int gm_bs = env_archcpu(env)->gm_blocksize;
     int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
+    uint64_t ret;
+    int shift;
 
     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 
     /*
      * The ordering of elements within the word corresponds to
-     * a little-endian operation.
+     * a little-endian operation.  Computation of shift comes from
+     *
+     *     index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
+     *     data<index*4+3:index*4> = tag
+     *
+     * Because of the alignment of ptr above, BS=6 has shift=0.
+     * All memory operations are aligned.  Defer support for BS=2,
+     * requiring insertion or extraction of a nibble, until we
+     * support a cpu that requires it.
      */
     switch (gm_bs) {
+    case 3:
+        /* 32 bytes -> 2 tags -> 8 result bits */
+        ret = *(uint8_t *)tag_mem;
+        break;
+    case 4:
+        /* 64 bytes -> 4 tags -> 16 result bits */
+        ret = cpu_to_le16(*(uint16_t *)tag_mem);
+        break;
+    case 5:
+        /* 128 bytes -> 8 tags -> 32 result bits */
+        ret = cpu_to_le32(*(uint32_t *)tag_mem);
+        break;
     case 6:
         /* 256 bytes -> 16 tags -> 64 result bits */
-        return ldq_le_p(tag_mem);
+        return cpu_to_le64(*(uint64_t *)tag_mem);
     default:
-        /* cpu configured with unsupported gm blocksize. */
+        /*
+         * CPU configured with unsupported/invalid gm blocksize.
+         * This is detected early in arm_cpu_realizefn.
+         */
         g_assert_not_reached();
     }
+    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
+    return ret << shift;
 }
 
 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
     int gm_bs = env_archcpu(env)->gm_blocksize;
     int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
+    int shift;
 
     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
         return;
     }
 
-    /*
-     * The ordering of elements within the word corresponds to
-     * a little-endian operation.
-     */
+    /* See LDGM for comments on BS and on shift.  */
+    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
+    val >>= shift;
     switch (gm_bs) {
+    case 3:
+        /* 32 bytes -> 2 tags -> 8 result bits */
+        *(uint8_t *)tag_mem = val;
+        break;
+    case 4:
+        /* 64 bytes -> 4 tags -> 16 result bits */
+        *(uint16_t *)tag_mem = cpu_to_le16(val);
+        break;
+    case 5:
+        /* 128 bytes -> 8 tags -> 32 result bits */
+        *(uint32_t *)tag_mem = cpu_to_le32(val);
+        break;
     case 6:
-        stq_le_p(tag_mem, val);
+        /* 256 bytes -> 16 tags -> 64 result bits */
+        *(uint64_t *)tag_mem = cpu_to_le64(val);
         break;
     default:
         /* cpu configured with unsupported gm blocksize. */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

When the cpu support MTE, but the system does not, reduce cpu
support to user instructions at EL0 instead of completely
disabling MTE.  If we encounter a cpu implementation which does
something else, we can revisit this setting.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
 #ifndef CONFIG_USER_ONLY
         /*
-         * Disable the MTE feature bits if we do not have tag-memory
-         * provided by the machine.
+         * If we do not have tag-memory provided by the machine,
+         * reduce MTE support to instructions enabled at EL0.
+         * This matches Cortex-A710 BROADCASTMTE input being LOW.
          */
         if (cpu->tag_memory == NULL) {
             cpu->isar.id_aa64pfr1 =
-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
         }
 #endif
     }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Do not hard-code the constants for Neoverse V1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
 1 file changed, 32 insertions(+), 16 deletions(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
+#include "qemu/units.h"
 #include "internals.h"
 #include "cpregs.h"
 
+static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
+                              unsigned cachesize)
+{
+    unsigned lg_linesize = ctz32(linesize);
+    unsigned sets;
+
+    /*
+     * The 64-bit CCSIDR_EL1 format is:
+     *   [55:32] number of sets - 1
+     *   [23:3]  associativity - 1
+     *   [2:0]   log2(linesize) - 4
+     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
+     */
+    assert(assoc != 0);
+    assert(is_power_of_2(linesize));
+    assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
+
+    /* sets * associativity * linesize == cachesize. */
+    sets = cachesize / (assoc * linesize);
+    assert(cachesize % (assoc * linesize) == 0);
+
+    return ((uint64_t)(sets - 1) << 32)
+         | ((assoc - 1) << 3)
+         | (lg_linesize - 4);
+}
+
 static void aarch64_a35_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
      * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
      * but also says it implements CCIDX, which means they should be
      * 64-bit format. So we here use values which are based on the textual
-     * information in chapter 2 of the TRM (and on the fact that
-     * sets * associativity * linesize == cachesize).
-     *
-     * The 64-bit CCSIDR_EL1 format is:
-     *   [55:32] number of sets - 1
-     *   [23:3]  associativity - 1
-     *   [2:0]   log2(linesize) - 4
-     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
-     *
-     * L1: 4-way set associative 64-byte line size, total size 64K,
-     * so sets is 256.
+     * information in chapter 2 of the TRM:
      *
+     * L1: 4-way set associative 64-byte line size, total size 64K.
      * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
-     * We pick 1MB, so this has 2048 sets.
-     *
      * L3: No L3 (this matches the CLIDR_EL1 value).
      */
-    cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
+    cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
+    cpu->ccsidr[1] = cpu->ccsidr[0];                 /* L1 icache */
+    cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB);  /* L2 cache */
 
     /* From 3.2.115 SCTLR_EL3 */
     cpu->reset_sctlr = 0x30c50838;
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Access to many of the special registers is enabled or disabled
by ACTLR_EL[23], which we implement as constant 0, which means
that all writes outside EL3 should trap.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h    |  2 ++
 target/arm/helper.c    |  4 ++--
 target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
 3 files changed, 41 insertions(+), 11 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 #endif
 
+CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
+
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
 }
 
 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM.  */
-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
-                                      bool isread)
+CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
+                               bool isread)
 {
     if (arm_current_el(env) == 1) {
         uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
     /* TODO:  Add A64FX specific HPC extension registers */
 }
 
+static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
+                                     bool read)
+{
+    if (!read) {
+        int el = arm_current_el(env);
+
+        /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
+        if (el < 2 && arm_is_el2_enabled(env)) {
+            return CP_ACCESS_TRAP_EL2;
+        }
+        /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
+        if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
+            return CP_ACCESS_TRAP_EL3;
+        }
+    }
+    return CP_ACCESS_OK;
+}
+
 static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
     { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      /* Traps and enables are the same as for TCR_EL1. */
+      .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
     { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     /*
      * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
      * (and in particular its system registers).
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
+      .accessfn = access_actlr_w },
     { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
 };
 
 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

There is only one additional EL1 register modeled, which
also needs to use access_actlr_w.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
 static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
     { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
external to the cpu, which is out of scope for QEMU.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         /* FEAT_SPE (Statistical Profiling Extension) */
         cpu->isar.id_aa64dfr0 =
             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
+        /* FEAT_TRBE (Trace Buffer Extension) */
+        cpu->isar.id_aa64dfr0 =
+            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
         /* FEAT_TRF (Self-hosted Trace Extension) */
         cpu->isar.id_aa64dfr0 =
             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This feature allows the operating system to set TCR_ELx.HWU*
to allow the implementation to use the PBHA bits from the
block and page descriptors for for IMPLEMENTATION DEFINED
purposes.  Since QEMU has no need to use these bits, we may
simply ignore them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu32.c        | 2 +-
 target/arm/tcg/cpu64.c        | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
 - FEAT_HCX (Support for the HCRX_EL2 register)
 - FEAT_HPDS (Hierarchical permission disables)
+- FEAT_HPDS2 (Translation table page-based hardware attributes)
 - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
 - FEAT_IDST (ID space trap handling)
 - FEAT_IESB (Implicit error synchronization event)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
     cpu->isar.id_mmfr3 = t;
 
     t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
     t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
+    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2);     /* FEAT_HPDS2 */
     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

This is a mandatory feature for Armv8.1 architectures but we don't
state the feature clearly in our emulation list. Also include
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
Cc: qemu-stable@nongnu.org
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
[PMM: pluralize 'instructions' in docs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu64.c        | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

From: Jean-Christophe Dubois <jcd@tribudubois.net>

i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
In particular, register 22 is not present on i.MX6UL and this is actualy
The only register that is really emulated in the i.MX7 IOMUX GPR device.

Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
as an unimplemented device at the same bus adress and the 2 instantiations
were actualy colliding. So we go back to the unimplemented device for now.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 --
 hw/arm/fsl-imx6ul.c         | 11 -----------
 2 files changed, 13 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx6ul_ccm.h"
 #include "hw/misc/imx6_src.h"
 #include "hw/misc/imx7_snvs.h"
-#include "hw/misc/imx7_gpr.h"
 #include "hw/intc/imx_gpcv2.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "hw/gpio/imx_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
     IMX6SRCState       src;
     IMX7SNVSState      snvs;
     IMXGPCv2State      gpcv2;
-    IMX7GPRState       gpr;
     IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
     IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
     IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      */
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
-    /*
-     * GPR
-     */
-    object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
-
     /*
      * GPIOs 1 to 5
      */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_WDOGn_IRQ[i]));
     }
 
-    /*
-     * GPR
-     */
-    sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
-
     /*
      * SDMA
      */
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
 hw/arm/fsl-imx6ul.c         | 147 ++++++++++++++++++++++-----------
 2 files changed, 232 insertions(+), 71 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/memory.h"
 #include "cpu.h"
 #include "qom/object.h"
+#include "qemu/units.h"
 
 #define TYPE_FSL_IMX6UL "fsl-imx6ul"
 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_ADCS         = 2,
     FSL_IMX6UL_NUM_USB_PHYS     = 2,
     FSL_IMX6UL_NUM_USBS         = 2,
+    FSL_IMX6UL_NUM_SAIS         = 3,
+    FSL_IMX6UL_NUM_CANS         = 2,
+    FSL_IMX6UL_NUM_PWMS         = 4,
 };
 
 struct FslIMX6ULState {
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
 
 enum FslIMX6ULMemoryMap {
     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
 
     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
-    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
-    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
-    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
-    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
 
-    /* AIPS-2 */
+    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
+    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
+
+    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
+    FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
+
+    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
+    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
+
+    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
+
+    /* AIPS-2 Begin */
     FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
+
     FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
+
     FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
     FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
     FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
     FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
+
     FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
+
     FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
+    FSL_IMX6UL_QSPI_SIZE            = 0x500,
+
     FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
+    FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
+
     FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
+    FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
+
     FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
+    FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
+
     FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
+    FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
+
     FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
+    FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
+    FSL_IMX6UL_LCDIF_SIZE           = 0x100,
+
     FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
+    FSL_IMX6UL_CSI_SIZE             = 0x100,
+
     FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
+    FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
+    FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
+
     FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
+    FSL_IMX6UL_EIM_SIZE             = 0x100,
+
     FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
+
     FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
+    FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
+
     FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
+    FSL_IMX6UL_ROMCP_SIZE           = 0x300,
+
     FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
     FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
     FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
+
     FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
     FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
+    FSL_IMX6UL_ADCn_SIZE            = 0x100,
+
     FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
     FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
-    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
-    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
-    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
-    FSL_IMX6UL_USBO2_USB_ADDR       = 0x02184000,
-    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
-    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
-    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
-    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
 
-    /* AIPS-1 */
+    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
+    FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
+
+    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
+
+    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
+    FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
+    FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
+
+    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
+    FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
+
+    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
+    FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
+
+    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
+    FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
+
+    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
+    FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
+    /* AIPS-2 End */
+
+    /* AIPS-1 Begin */
     FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
     FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
     FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
     FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
+
     FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
+    FSL_IMX6UL_SDMA_SIZE            = 0x300,
+
     FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
+
     FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
+    FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
+
     FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
+    FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
+
     FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
+
     FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
+
     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
+
     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
+
     FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
-    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
     FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
-    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
+
     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
+    FSL_IMX6UL_ANALOG_SIZE          = 0x300,
+
     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
+
     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
     FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
+
     FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
+    FSL_IMX6UL_KPP_SIZE             = 0x10,
+
     FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
+
     FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
+    FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
+
     FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
     FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
     FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
     FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
     FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
+
     FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
+
     FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
     FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
+    FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
+
     FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
     FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
     FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
     FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
+    FSL_IMX6UL_PWMn_SIZE            = 0x20,
+
     FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
+    FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
+
     FSL_IMX6UL_BEE_ADDR             = 0x02044000,
+    FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
+    FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
+
     FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
+    FSL_IMX6UL_SPBA_SIZE            = 0x100,
+
     FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
+    FSL_IMX6UL_ASRC_SIZE            = 0x100,
+
     FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
     FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
     FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
+    FSL_IMX6UL_SAIn_SIZE            = 0x200,
+
     FSL_IMX6UL_UART8_ADDR           = 0x02024000,
     FSL_IMX6UL_UART1_ADDR           = 0x02020000,
     FSL_IMX6UL_UART7_ADDR           = 0x02018000,
+
     FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
     FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
     FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
     FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
+
     FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
+    FSL_IMX6UL_SPDIF_SIZE           = 0x100,
+    /* AIPS-1 End */
+
+    FSL_IMX6UL_BCH_ADDR             = 0x01808000,
+    FSL_IMX6UL_BCH_SIZE             = 0x200,
+
+    FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
+    FSL_IMX6UL_GPMI_SIZE            = 0x200,
 
     FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
-    FSL_IMX6UL_APBH_DMA_SIZE        = (32 * 1024),
+    FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
 
     FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
 
     FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
-    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = 0x00060000,
+    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
+
     FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
-    FSL_IMX6UL_OCRAM_MEM_SIZE       = 0x00020000,
+    FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
+
     FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
-    FSL_IMX6UL_CAAM_MEM_SIZE        = 0x00008000,
+    FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
+
     FSL_IMX6UL_ROM_ADDR             = 0x00000000,
-    FSL_IMX6UL_ROM_SIZE             = 0x00018000,
+    FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
 };
 
 enum FslIMX6ULIRQs {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
     /*
-     * GPIOs 1 to 5
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * GPT 1, 2
+     * GPTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * EPIT 1, 2
+     * EPITs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
         snprintf(name, NAME_SIZE, "epit%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * eCSPI
+     * eCSPIs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * I2C
+     * I2Cs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
         snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      */
     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
         snprintf(name, NAME_SIZE, "eth%d", i);
         object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
     }
 
-    /* USB */
+    /*
+     * USB PHYs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
         snprintf(name, NAME_SIZE, "usbphy%d", i);
         object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
     }
+
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
         snprintf(name, NAME_SIZE, "usb%d", i);
         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
     }
 
     /*
-     * SDHCI
+     * SDHCIs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
         snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
         snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      * A7MPCORE DAP
      */
     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
-                                0x100000);
+                                FSL_IMX6UL_A7MPCORE_DAP_SIZE);
 
     /*
-     * GPT 1, 2
+     * GPTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * EPIT 1, 2
+     * EPITs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * GPIO
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * IOMUXC and IOMUXC_GPR
+     * IOMUXC
      */
-    for (i = 0; i < 1; i++) {
-        static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
-            FSL_IMX6UL_IOMUXC_ADDR,
-            FSL_IMX6UL_IOMUXC_GPR_ADDR,
-        };
-
-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
-        create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
-    }
+    create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
+                                FSL_IMX6UL_IOMUXC_SIZE);
+    create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
+                                FSL_IMX6UL_IOMUXC_GPR_SIZE);
 
     /*
      * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
 
-    /* Initialize all ECSPI */
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
             FSL_IMX6UL_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * I2C
+     * I2Cs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      *
      * We must use two loops since phy_connected affects the other interface
      * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
     }
 
-    /* USB */
+    /*
+     * USB PHYs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+        static const hwaddr
+                     FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
+            FSL_IMX6UL_USBPHY1_ADDR,
+            FSL_IMX6UL_USBPHY2_ADDR,
+        };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
-                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
+                        FSL_IMX6UL_USB_PHYn_ADDR[i]);
     }
 
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+        static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
+            FSL_IMX6UL_USBO2_USB1_ADDR,
+            FSL_IMX6UL_USBO2_USB2_ADDR,
+        };
+
         static const int FSL_IMX6UL_USBn_IRQ[] = {
             FSL_IMX6UL_USB1_IRQ,
             FSL_IMX6UL_USB2_IRQ,
         };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
-                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
+                        FSL_IMX6UL_USB02_USBn_ADDR[i]);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
                                             FSL_IMX6UL_USBn_IRQ[i]));
     }
 
     /*
-     * USDHC
+     * USDHCs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_WDOG2_ADDR,
             FSL_IMX6UL_WDOG3_ADDR,
         };
+
         static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
             FSL_IMX6UL_WDOG1_IRQ,
             FSL_IMX6UL_WDOG2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     /*
      * SDMA
      */
-    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
+    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
+                                FSL_IMX6UL_SDMA_SIZE);
 
     /*
-     * SAI (Audio SSI (Synchronous Serial Interface))
+     * SAIs (Audio SSI (Synchronous Serial Interface))
      */
-    create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
-    create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
-    create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
+        static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
+            FSL_IMX6UL_SAI1_ADDR,
+            FSL_IMX6UL_SAI2_ADDR,
+            FSL_IMX6UL_SAI3_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "sai%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
+                                    FSL_IMX6UL_SAIn_SIZE);
+    }
 
     /*
-     * PWM
+     * PWMs
      */
-    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
-    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
-    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
-    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
+        static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
+            FSL_IMX6UL_PWM1_ADDR,
+            FSL_IMX6UL_PWM2_ADDR,
+            FSL_IMX6UL_PWM3_ADDR,
+            FSL_IMX6UL_PWM4_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "pwm%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
+                                    FSL_IMX6UL_PWMn_SIZE);
+    }
 
     /*
      * Audio ASRC (asynchronous sample rate converter)
      */
-    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
+    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
+                                FSL_IMX6UL_ASRC_SIZE);
 
     /*
-     * CAN
+     * CANs
      */
-    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
-    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
+        static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
+            FSL_IMX6UL_CAN1_ADDR,
+            FSL_IMX6UL_CAN2_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "can%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
+                                    FSL_IMX6UL_CANn_SIZE);
+    }
 
     /*
      * APHB_DMA
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
         };
 
         snprintf(name, NAME_SIZE, "adc%d", i);
-        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
+        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
+                                    FSL_IMX6UL_ADCn_SIZE);
     }
 
     /*
      * LCD
      */
-    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
+    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
+                                FSL_IMX6UL_LCDIF_SIZE);
 
     /*
      * ROM memory
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add TZASC as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add 4 missing PWM devices

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 +-
 hw/arm/fsl-imx6ul.c         | 16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_USBS         = 2,
     FSL_IMX6UL_NUM_SAIS         = 3,
     FSL_IMX6UL_NUM_CANS         = 2,
-    FSL_IMX6UL_NUM_PWMS         = 4,
+    FSL_IMX6UL_NUM_PWMS         = 8,
 };
 
 struct FslIMX6ULState {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_PWM2_ADDR,
             FSL_IMX6UL_PWM3_ADDR,
             FSL_IMX6UL_PWM4_ADDR,
+            FSL_IMX6UL_PWM5_ADDR,
+            FSL_IMX6UL_PWM6_ADDR,
+            FSL_IMX6UL_PWM7_ADDR,
+            FSL_IMX6UL_PWM8_ADDR,
         };
 
         snprintf(name, NAME_SIZE, "pwm%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
                                 FSL_IMX6UL_LCDIF_SIZE);
 
+    /*
+     * CSU
+     */
+    create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
+                                FSL_IMX6UL_CSU_SIZE);
+
+    /*
+     * TZASC
+     */
+    create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
+                                FSL_IMX6UL_TZASC_SIZE);
+
     /*
      * ROM memory
      */
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
 hw/arm/fsl-imx7.c         | 130 ++++++++++-----
 2 files changed, 335 insertions(+), 125 deletions(-)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx7_ccm.h"
 #include "hw/misc/imx7_snvs.h"
 #include "hw/misc/imx7_gpr.h"
-#include "hw/misc/imx6_src.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "hw/gpio/imx_gpio.h"
 #include "hw/char/imx_serial.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/usb/chipidea.h"
 #include "cpu.h"
 #include "qom/object.h"
+#include "qemu/units.h"
 
 #define TYPE_FSL_IMX7 "fsl-imx7"
 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
     FSL_IMX7_NUM_ECSPIS       = 4,
     FSL_IMX7_NUM_USBS         = 3,
     FSL_IMX7_NUM_ADCS         = 2,
+    FSL_IMX7_NUM_SAIS         = 3,
+    FSL_IMX7_NUM_CANS         = 2,
+    FSL_IMX7_NUM_PWMS         = 4,
 };
 
 struct FslIMX7State {
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
 
 enum FslIMX7MemoryMap {
     FSL_IMX7_MMDC_ADDR            = 0x80000000,
-    FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX7_MMDC_SIZE            = (2 * GiB),
 
-    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
-    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
-    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
-    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
-    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
-    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
-    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
+    FSL_IMX7_QSPI1_MEM_ADDR       = 0x60000000,
+    FSL_IMX7_QSPI1_MEM_SIZE       = (256 * MiB),
 
-    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+    FSL_IMX7_PCIE1_MEM_ADDR       = 0x40000000,
+    FSL_IMX7_PCIE1_MEM_SIZE       = (256 * MiB),
 
-    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
-    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
-    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
-    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
+    FSL_IMX7_QSPI1_RX_BUF_ADDR    = 0x34000000,
+    FSL_IMX7_QSPI1_RX_BUF_SIZE    = (32 * MiB),
 
-    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
+    /* PCIe Peripherals */
+    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 
-    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
-    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
-    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
-    FSL_IMX7_GPT4_ADDR            = 0x30300000,
+    /* MMAP Peripherals */
+    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
+    FSL_IMX7_DMA_APBH_SIZE        = 0x8000,
 
-    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
-    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
-    FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
+    /* GPV configuration */
+    FSL_IMX7_GPV6_ADDR            = 0x32600000,
+    FSL_IMX7_GPV5_ADDR            = 0x32500000,
+    FSL_IMX7_GPV4_ADDR            = 0x32400000,
+    FSL_IMX7_GPV3_ADDR            = 0x32300000,
+    FSL_IMX7_GPV2_ADDR            = 0x32200000,
+    FSL_IMX7_GPV1_ADDR            = 0x32100000,
+    FSL_IMX7_GPV0_ADDR            = 0x32000000,
+    FSL_IMX7_GPVn_SIZE            = (1 * MiB),
 
-    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
-    FSL_IMX7_OCOTP_SIZE           = 0x10000,
+    /* Arm Peripherals */
+    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
 
-    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
-    FSL_IMX7_SNVS_ADDR            = 0x30370000,
-    FSL_IMX7_CCM_ADDR             = 0x30380000,
+    /* AIPS-3 Begin */
 
-    FSL_IMX7_SRC_ADDR             = 0x30390000,
-    FSL_IMX7_SRC_SIZE             = 0x1000,
+    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
+    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 
-    FSL_IMX7_ADC1_ADDR            = 0x30610000,
-    FSL_IMX7_ADC2_ADDR            = 0x30620000,
-    FSL_IMX7_ADCn_SIZE            = 0x1000,
+    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
+    FSL_IMX7_SDMA_SIZE            = (4 * KiB),
 
-    FSL_IMX7_PWM1_ADDR            = 0x30660000,
-    FSL_IMX7_PWM2_ADDR            = 0x30670000,
-    FSL_IMX7_PWM3_ADDR            = 0x30680000,
-    FSL_IMX7_PWM4_ADDR            = 0x30690000,
-    FSL_IMX7_PWMn_SIZE            = 0x10000,
+    FSL_IMX7_EIM_ADDR             = 0x30BC0000,
+    FSL_IMX7_EIM_SIZE             = (4 * KiB),
 
-    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
-    FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
+    FSL_IMX7_QSPI_ADDR            = 0x30BB0000,
+    FSL_IMX7_QSPI_SIZE            = 0x8000,
 
-    FSL_IMX7_GPC_ADDR             = 0x303A0000,
+    FSL_IMX7_SIM2_ADDR            = 0x30BA0000,
+    FSL_IMX7_SIM1_ADDR            = 0x30B90000,
+    FSL_IMX7_SIMn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
+    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
+    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
+
+    FSL_IMX7_USB3_ADDR            = 0x30B30000,
+    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
+    FSL_IMX7_USB2_ADDR            = 0x30B20000,
+    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
+    FSL_IMX7_USB1_ADDR            = 0x30B10000,
+    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
+    FSL_IMX7_USBMISCn_SIZE        = 0x200,
+
+    FSL_IMX7_USB_PL301_ADDR       = 0x30AD0000,
+    FSL_IMX7_USB_PL301_SIZE       = (64 * KiB),
+
+    FSL_IMX7_SEMAPHORE_HS_ADDR    = 0x30AC0000,
+    FSL_IMX7_SEMAPHORE_HS_SIZE    = (64 * KiB),
+
+    FSL_IMX7_MUB_ADDR             = 0x30AB0000,
+    FSL_IMX7_MUA_ADDR             = 0x30AA0000,
+    FSL_IMX7_MUn_SIZE             = (KiB),
+
+    FSL_IMX7_UART7_ADDR           = 0x30A90000,
+    FSL_IMX7_UART6_ADDR           = 0x30A80000,
+    FSL_IMX7_UART5_ADDR           = 0x30A70000,
+    FSL_IMX7_UART4_ADDR           = 0x30A60000,
+
+    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
+    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
+    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
+    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
+
+    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
+    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
+    FSL_IMX7_CANn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_AIPS3_CONF_ADDR      = 0x309F0000,
+    FSL_IMX7_AIPS3_CONF_SIZE      = (64 * KiB),
 
     FSL_IMX7_CAAM_ADDR            = 0x30900000,
-    FSL_IMX7_CAAM_SIZE            = 0x40000,
+    FSL_IMX7_CAAM_SIZE            = (256 * KiB),
 
-    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
-    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
-    FSL_IMX7_CANn_SIZE            = 0x10000,
+    FSL_IMX7_SPBA_ADDR            = 0x308F0000,
+    FSL_IMX7_SPBA_SIZE            = (4 * KiB),
 
-    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
-    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
-    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
-    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
+    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
+    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
+    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
+    FSL_IMX7_SAIn_SIZE            = (4 * KiB),
 
-    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
-    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
-    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
-    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
-
-    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
-    FSL_IMX7_LCDIF_SIZE           = 0x1000,
-
-    FSL_IMX7_UART1_ADDR           = 0x30860000,
+    FSL_IMX7_UART3_ADDR           = 0x30880000,
     /*
      * Some versions of the reference manual claim that UART2 is @
      * 0x30870000, but experiments with HW + DT files in upstream
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
      * actually located @ 0x30890000
      */
     FSL_IMX7_UART2_ADDR           = 0x30890000,
-    FSL_IMX7_UART3_ADDR           = 0x30880000,
-    FSL_IMX7_UART4_ADDR           = 0x30A60000,
-    FSL_IMX7_UART5_ADDR           = 0x30A70000,
-    FSL_IMX7_UART6_ADDR           = 0x30A80000,
-    FSL_IMX7_UART7_ADDR           = 0x30A90000,
+    FSL_IMX7_UART1_ADDR           = 0x30860000,
 
-    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
-    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
-    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
-    FSL_IMX7_SAIn_SIZE            = 0x10000,
+    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
+    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
+    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
+    FSL_IMX7_ECSPIn_SIZE          = (4 * KiB),
 
-    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
-    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
+    /* AIPS-3 End */
 
-    FSL_IMX7_USB1_ADDR            = 0x30B10000,
-    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
-    FSL_IMX7_USB2_ADDR            = 0x30B20000,
-    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
-    FSL_IMX7_USB3_ADDR            = 0x30B30000,
-    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
-    FSL_IMX7_USBMISCn_SIZE        = 0x200,
+    /* AIPS-2 Begin */
 
-    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
-    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
-    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
+    FSL_IMX7_AXI_DEBUG_MON_ADDR   = 0x307E0000,
+    FSL_IMX7_AXI_DEBUG_MON_SIZE   = (64 * KiB),
 
-    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
-    FSL_IMX7_SDMA_SIZE            = 0x1000,
+    FSL_IMX7_PERFMON2_ADDR        = 0x307D0000,
+    FSL_IMX7_PERFMON1_ADDR        = 0x307C0000,
+    FSL_IMX7_PERFMONn_SIZE        = (64 * KiB),
+
+    FSL_IMX7_DDRC_ADDR            = 0x307A0000,
+    FSL_IMX7_DDRC_SIZE            = (4 * KiB),
+
+    FSL_IMX7_DDRC_PHY_ADDR        = 0x30790000,
+    FSL_IMX7_DDRC_PHY_SIZE        = (4 * KiB),
+
+    FSL_IMX7_TZASC_ADDR           = 0x30780000,
+    FSL_IMX7_TZASC_SIZE           = (64 * KiB),
+
+    FSL_IMX7_MIPI_DSI_ADDR        = 0x30760000,
+    FSL_IMX7_MIPI_DSI_SIZE        = (4 * KiB),
+
+    FSL_IMX7_MIPI_CSI_ADDR        = 0x30750000,
+    FSL_IMX7_MIPI_CSI_SIZE        = 0x4000,
+
+    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
+    FSL_IMX7_LCDIF_SIZE           = 0x8000,
+
+    FSL_IMX7_CSI_ADDR             = 0x30710000,
+    FSL_IMX7_CSI_SIZE             = (4 * KiB),
+
+    FSL_IMX7_PXP_ADDR             = 0x30700000,
+    FSL_IMX7_PXP_SIZE             = 0x4000,
+
+    FSL_IMX7_EPDC_ADDR            = 0x306F0000,
+    FSL_IMX7_EPDC_SIZE            = (4 * KiB),
+
+    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
+    FSL_IMX7_PCIE_PHY_SIZE        = (4 * KiB),
+
+    FSL_IMX7_SYSCNT_CTRL_ADDR     = 0x306C0000,
+    FSL_IMX7_SYSCNT_CMP_ADDR      = 0x306B0000,
+    FSL_IMX7_SYSCNT_RD_ADDR       = 0x306A0000,
+
+    FSL_IMX7_PWM4_ADDR            = 0x30690000,
+    FSL_IMX7_PWM3_ADDR            = 0x30680000,
+    FSL_IMX7_PWM2_ADDR            = 0x30670000,
+    FSL_IMX7_PWM1_ADDR            = 0x30660000,
+    FSL_IMX7_PWMn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_FlEXTIMER2_ADDR      = 0x30650000,
+    FSL_IMX7_FlEXTIMER1_ADDR      = 0x30640000,
+    FSL_IMX7_FLEXTIMERn_SIZE      = (4 * KiB),
+
+    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
+
+    FSL_IMX7_ADC2_ADDR            = 0x30620000,
+    FSL_IMX7_ADC1_ADDR            = 0x30610000,
+    FSL_IMX7_ADCn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_AIPS2_CONF_ADDR      = 0x305F0000,
+    FSL_IMX7_AIPS2_CONF_SIZE      = (64 * KiB),
+
+    /* AIPS-2 End */
+
+    /* AIPS-1 Begin */
+
+    FSL_IMX7_CSU_ADDR             = 0x303E0000,
+    FSL_IMX7_CSU_SIZE             = (64 * KiB),
+
+    FSL_IMX7_RDC_ADDR             = 0x303D0000,
+    FSL_IMX7_RDC_SIZE             = (4 * KiB),
+
+    FSL_IMX7_SEMAPHORE2_ADDR      = 0x303C0000,
+    FSL_IMX7_SEMAPHORE1_ADDR      = 0x303B0000,
+    FSL_IMX7_SEMAPHOREn_SIZE      = (4 * KiB),
+
+    FSL_IMX7_GPC_ADDR             = 0x303A0000,
+
+    FSL_IMX7_SRC_ADDR             = 0x30390000,
+    FSL_IMX7_SRC_SIZE             = (4 * KiB),
+
+    FSL_IMX7_CCM_ADDR             = 0x30380000,
+
+    FSL_IMX7_SNVS_HP_ADDR         = 0x30370000,
+
+    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
+
+    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
+    FSL_IMX7_OCOTP_SIZE           = 0x10000,
+
+    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
+    FSL_IMX7_IOMUXC_GPR_SIZE      = (4 * KiB),
+
+    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
+    FSL_IMX7_IOMUXC_SIZE          = (4 * KiB),
+
+    FSL_IMX7_KPP_ADDR             = 0x30320000,
+    FSL_IMX7_KPP_SIZE             = (4 * KiB),
+
+    FSL_IMX7_ROMCP_ADDR           = 0x30310000,
+    FSL_IMX7_ROMCP_SIZE           = (4 * KiB),
+
+    FSL_IMX7_GPT4_ADDR            = 0x30300000,
+    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
+    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
+    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
+
+    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
+    FSL_IMX7_IOMUXC_LPSR_SIZE     = (4 * KiB),
+
+    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
+    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
+    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
+    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
+
+    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+
+    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
+    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
+    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
+    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
+    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
+    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
+    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
+
+    FSL_IMX7_AIPS1_CONF_ADDR      = 0x301F0000,
+    FSL_IMX7_AIPS1_CONF_SIZE      = (64 * KiB),
 
-    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
     FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
+    FSL_IMX7_A7MPCORE_DAP_SIZE    = (1 * MiB),
 
-    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
-    FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
+    /* AIPS-1 End */
 
-    FSL_IMX7_GPR_ADDR             = 0x30340000,
+    FSL_IMX7_EIM_CS0_ADDR         = 0x28000000,
+    FSL_IMX7_EIM_CS0_SIZE         = (128 * MiB),
 
-    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
-    FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
+    FSL_IMX7_OCRAM_PXP_ADDR       = 0x00940000,
+    FSL_IMX7_OCRAM_PXP_SIZE       = (32 * KiB),
+
+    FSL_IMX7_OCRAM_EPDC_ADDR      = 0x00920000,
+    FSL_IMX7_OCRAM_EPDC_SIZE      = (128 * KiB),
+
+    FSL_IMX7_OCRAM_MEM_ADDR       = 0x00900000,
+    FSL_IMX7_OCRAM_MEM_SIZE       = (128 * KiB),
+
+    FSL_IMX7_TCMU_ADDR            = 0x00800000,
+    FSL_IMX7_TCMU_SIZE            = (32 * KiB),
+
+    FSL_IMX7_TCML_ADDR            = 0x007F8000,
+    FSL_IMX7_TCML_SIZE            = (32 * KiB),
+
+    FSL_IMX7_OCRAM_S_ADDR         = 0x00180000,
+    FSL_IMX7_OCRAM_S_SIZE         = (32 * KiB),
+
+    FSL_IMX7_CAAM_MEM_ADDR        = 0x00100000,
+    FSL_IMX7_CAAM_MEM_SIZE        = (32 * KiB),
+
+    FSL_IMX7_ROM_ADDR             = 0x00000000,
+    FSL_IMX7_ROM_SIZE             = (96 * KiB),
 };
 
 enum FslIMX7IRQs {
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     char name[NAME_SIZE];
     int i;
 
+    /*
+     * CPUs
+     */
     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
         snprintf(name, NAME_SIZE, "cpu%d", i);
         object_initialize_child(obj, name, &s->cpu[i],
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
                             TYPE_A15MPCORE_PRIV);
 
     /*
-     * GPIOs 1 to 7
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * GPT1, 2, 3, 4
+     * GPTs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      */
     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
         object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
     }
 
-
+    /*
+     * I2Cs
+     */
     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
         object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
             snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      */
     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
             snprintf(name, NAME_SIZE, "eth%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * SDHCI
+     * SDHCIs
      */
     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
             snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
             snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      */
     object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
 
+    /*
+     * PCIE
+     */
     object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
         snprintf(name, NAME_SIZE, "usb%d", i);
         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    /*
+     * CPUs
+     */
     for (i = 0; i < smp_cpus; i++) {
         o = OBJECT(&s->cpu[i]);
 
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      * A7MPCORE DAP
      */
     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
-                                0x100000);
+                                FSL_IMX7_A7MPCORE_DAP_SIZE);
 
     /*
-     * GPT1, 2, 3, 4
+     * GPTs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX7_GPTn_IRQ[i]));
     }
 
+    /*
+     * GPIOs
+     */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
             FSL_IMX7_GPIO1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     /*
      * IOMUXC and IOMUXC_LPSR
      */
-    for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
-        static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
-            FSL_IMX7_IOMUXC_ADDR,
-            FSL_IMX7_IOMUXC_LPSR_ADDR,
-        };
-
-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
-        create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
-                                    FSL_IMX7_IOMUXCn_SIZE);
-    }
+    create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
+                                FSL_IMX7_IOMUXC_SIZE);
+    create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
+                                FSL_IMX7_IOMUXC_LPSR_SIZE);
 
     /*
      * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
 
-    /* Initialize all ECSPI */
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
             FSL_IMX7_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX7_SPIn_IRQ[i]));
     }
 
+    /*
+     * I2Cs
+     */
     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
             FSL_IMX7_I2C1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      *
      * We must use two loops since phy_connected affects the other interface
      * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * USDHC
+     * USDHCs
      */
     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      * SNVS
      */
     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
 
     /*
      * SRC
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
 
     /*
-     * PWM
+     * PWMs
      */
-    create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
+        static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
+            FSL_IMX7_PWM1_ADDR,
+            FSL_IMX7_PWM2_ADDR,
+            FSL_IMX7_PWM3_ADDR,
+            FSL_IMX7_PWM4_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "pwm%d", i);
+        create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
+                                    FSL_IMX7_PWMn_SIZE);
+    }
 
     /*
-     * CAN
+     * CANs
      */
-    create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
-    create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
+        static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
+            FSL_IMX7_CAN1_ADDR,
+            FSL_IMX7_CAN2_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "can%d", i);
+        create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
+                                    FSL_IMX7_CANn_SIZE);
+    }
 
     /*
-     * SAI (Audio SSI (Synchronous Serial Interface))
+     * SAIs (Audio SSI (Synchronous Serial Interface))
      */
-    create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
-    create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
-    create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
+        static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
+            FSL_IMX7_SAI1_ADDR,
+            FSL_IMX7_SAI2_ADDR,
+            FSL_IMX7_SAI3_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "sai%d", i);
+        create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
+                                    FSL_IMX7_SAIn_SIZE);
+    }
 
     /*
      * OCOTP
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
                                 FSL_IMX7_OCOTP_SIZE);
 
+    /*
+     * GPR
+     */
     sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
 
+    /*
+     * PCIE
+     */
     sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
 
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
 
-
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
             FSL_IMX7_USBMISC1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      */
     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                 FSL_IMX7_PCIE_PHY_SIZE);
+
 }
 
 static Property fsl_imx7_properties[] = {
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h |  7 +++++
 hw/arm/fsl-imx7.c         | 63 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
     IMX7GPRState       gpr;
     ChipideaState      usb[FSL_IMX7_NUM_USBS];
     DesignwarePCIEHost pcie;
+    MemoryRegion       rom;
+    MemoryRegion       caam;
+    MemoryRegion       ocram;
+    MemoryRegion       ocram_epdc;
+    MemoryRegion       ocram_pxp;
+    MemoryRegion       ocram_s;
+
     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
     bool               phy_connected[FSL_IMX7_NUM_ETHS];
 };
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                 FSL_IMX7_PCIE_PHY_SIZE);
 
+    /*
+     * CSU
+     */
+    create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
+                                FSL_IMX7_CSU_SIZE);
+
+    /*
+     * TZASC
+     */
+    create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
+                                FSL_IMX7_TZASC_SIZE);
+
+    /*
+     * OCRAM memory
+     */
+    memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
+                           FSL_IMX7_OCRAM_MEM_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
+                                &s->ocram);
+
+    /*
+     * OCRAM EPDC memory
+     */
+    memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
+                           FSL_IMX7_OCRAM_EPDC_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
+                                &s->ocram_epdc);
+
+    /*
+     * OCRAM PXP memory
+     */
+    memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
+                           FSL_IMX7_OCRAM_PXP_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
+                                &s->ocram_pxp);
+
+    /*
+     * OCRAM_S memory
+     */
+    memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
+                           FSL_IMX7_OCRAM_S_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
+                                &s->ocram_s);
+
+    /*
+     * ROM memory
+     */
+    memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
+                           FSL_IMX7_ROM_SIZE, &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
+                                &s->rom);
+
+    /*
+     * CAAM memory
+     */
+    memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
+                           FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
+                                &s->caam);
 }
 
 static Property fsl_imx7_properties[] = {
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

The SRC device is normally used to start the secondary CPU.

When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
is installing at boot time and therefore the fact that the SRC device is
unimplemented is hidden as Qemu respond directly to PSCI requets without
using the SRC device.

But if you try to run a more bare metal application (maybe uboot itself),
then it is not possible to start the secondary CPU as the SRC is an
unimplemented device.

This patch adds the ability to start the secondary CPU through the SRC
device so that you can use this feature in bare metal applications.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h  |   3 +-
 include/hw/misc/imx7_src.h |  66 +++++++++
 hw/arm/fsl-imx7.c          |   8 +-
 hw/misc/imx7_src.c         | 276 +++++++++++++++++++++++++++++++++++++
 hw/misc/meson.build        |   1 +
 hw/misc/trace-events       |   4 +
 6 files changed, 356 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/imx7_src.h
 create mode 100644 hw/misc/imx7_src.c

The architecture requires (R_TYTWB) that an attempt to return from EL3
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
enforces that the CPU can't ever be executing below EL3 with the
NSE,NS bits indicating an invalid security state.)

We were missing this check; add it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
---
 target/arm/tcg/helper-a64.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
         spsr &= ~PSTATE_SS;
     }
 
+    /*
+     * FEAT_RME forbids return from EL3 with an invalid security state.
+     * We don't need an explicit check for FEAT_RME here because we enforce
+     * in scr_write() that you can't set the NSE bit without it.
+     */
+    if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
+        goto illegal_return;
+    }
+
     new_el = el_from_spsr(spsr);
     if (new_el == -1) {
         goto illegal_return;
-- 
2.34.1

In the aspeed_rtc device we store a difference between two time_t
values in an 'int'. This is not really correct when time_t could
be 64 bits. Enlarge the field to 'int64_t'.

This is a migration compatibility break for the aspeed boards.
While we are changing the vmstate, remove the accidental
duplicate of the offset field.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/rtc/aspeed_rtc.h | 2 +-
 hw/rtc/aspeed_rtc.c         | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/rtc/aspeed_rtc.h
+++ b/include/hw/rtc/aspeed_rtc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
     qemu_irq irq;
 
     uint32_t reg[0x18];
-    int offset;
+    int64_t offset;
 
 };
 
diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/rtc/aspeed_rtc.c
+++ b/hw/rtc/aspeed_rtc.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
 
 static const VMStateDescription vmstate_aspeed_rtc = {
     .name = TYPE_ASPEED_RTC,
-    .version_id = 1,
+    .version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
-        VMSTATE_INT32(offset, AspeedRtcState),
-        VMSTATE_INT32(offset, AspeedRtcState),
+        VMSTATE_INT64(offset, AspeedRtcState),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
2.34.1

The functions qemu_get_timedate() and qemu_timedate_diff() take
and return a time offset as an integer. Coverity points out that
means that when an RTC device implementation holds an offset
as a time_t, as the m48t59 does, the time_t will get truncated.
(CID 1507157, 1517772).

The functions work with time_t internally, so make them use that type
in their APIs.

Note that this won't help any Y2038 issues where either the device
model itself is keeping the offset in a 32-bit integer, or where the
hardware under emulation has Y2038 or other rollover problems.  If we
missed any cases of the former then hopefully Coverity will warn us
about them since after this patch we'd be truncating a time_t in
assignments from qemu_timedate_diff().)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/sysemu/rtc.h | 4 ++--
 softmmu/rtc.c        | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/rtc.h
+++ b/include/sysemu/rtc.h
@@ -XXX,XX +XXX,XX @@
  * The behaviour of the clock whose value this function returns will
  * depend on the -rtc command line option passed by the user.
  */
-void qemu_get_timedate(struct tm *tm, int offset);
+void qemu_get_timedate(struct tm *tm, time_t offset);
 
 /**
  * qemu_timedate_diff: Return difference between a struct tm and the RTC
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
  * a timestamp one hour further ahead than the current RTC time
  * then this function will return 3600.
  */
-int qemu_timedate_diff(struct tm *tm);
+time_t qemu_timedate_diff(struct tm *tm);
 
 #endif
diff --git a/softmmu/rtc.c b/softmmu/rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/softmmu/rtc.c
+++ b/softmmu/rtc.c
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
     return value;
 }
 
-void qemu_get_timedate(struct tm *tm, int offset)
+void qemu_get_timedate(struct tm *tm, time_t offset)
 {
     time_t ti = qemu_ref_timedate(rtc_clock);
 
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
     }
 }
 
-int qemu_timedate_diff(struct tm *tm)
+time_t qemu_timedate_diff(struct tm *tm)
 {
     time_t seconds;
 
-- 
2.34.1

Where architecturally one ARM_FEATURE_X flag implies another
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
set Y for it.  Currently we do this in two places -- we set a few
flags in arm_cpu_post_init() because we need them to decide which
properties to create on the CPU object, and then we do the rest in
arm_cpu_realizefn().  However, this is fragile, because it's easy to
add a new property and not notice that this means that an X-implies-Y
check now has to move from realize to post-init.

As a specific example, the pmsav7-dregion property is conditional
on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
rely on V8-implies-V7, which doesn't happen until the realizefn.

Move all of these X-implies-Y checks into a new function, which
we call at the top of arm_cpu_post_init(), so the feature bits
are available at that point.

This does now give us the reverse issue, that if there's a feature
bit which is enabled or disabled by the setting of a property then
then X-implies-Y features that are dependent on that property need to
be in realize, not in this new function.  But the only one of those
is the "EL3 implies VBAR" which is already in the right place, so
putting things this way round seems better to me.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
---
 target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
 1 file changed, 97 insertions(+), 82 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
       NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
 }
 
+static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
+{
+    CPUARMState *env = &cpu->env;
+    bool no_aa32 = false;
+
+    /*
+     * Some features automatically imply others: set the feature
+     * bits explicitly for these cases.
+     */
+
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_PMSA);
+    }
+
+    if (arm_feature(env, ARM_FEATURE_V8)) {
+        if (arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V7);
+        } else {
+            set_feature(env, ARM_FEATURE_V7VE);
+        }
+    }
+
+    /*
+     * There exist AArch64 cpus without AArch32 support.  When KVM
+     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
+     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
+     * As a general principle, we also do not make ID register
+     * consistency checks anywhere unless using TCG, because only
+     * for TCG would a consistency-check failure be a QEMU bug.
+     */
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
+    }
+
+    if (arm_feature(env, ARM_FEATURE_V7VE)) {
+        /*
+         * v7 Virtualization Extensions. In real hardware this implies
+         * EL2 and also the presence of the Security Extensions.
+         * For QEMU, for backwards-compatibility we implement some
+         * CPUs or CPU configs which have no actual EL2 or EL3 but do
+         * include the various other features that V7VE implies.
+         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
+         * Security Extensions is ARM_FEATURE_EL3.
+         */
+        assert(!tcg_enabled() || no_aa32 ||
+               cpu_isar_feature(aa32_arm_div, cpu));
+        set_feature(env, ARM_FEATURE_LPAE);
+        set_feature(env, ARM_FEATURE_V7);
+    }
+    if (arm_feature(env, ARM_FEATURE_V7)) {
+        set_feature(env, ARM_FEATURE_VAPA);
+        set_feature(env, ARM_FEATURE_THUMB2);
+        set_feature(env, ARM_FEATURE_MPIDR);
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V6K);
+        } else {
+            set_feature(env, ARM_FEATURE_V6);
+        }
+
+        /*
+         * Always define VBAR for V7 CPUs even if it doesn't exist in
+         * non-EL3 configs. This is needed by some legacy boards.
+         */
+        set_feature(env, ARM_FEATURE_VBAR);
+    }
+    if (arm_feature(env, ARM_FEATURE_V6K)) {
+        set_feature(env, ARM_FEATURE_V6);
+        set_feature(env, ARM_FEATURE_MVFR);
+    }
+    if (arm_feature(env, ARM_FEATURE_V6)) {
+        set_feature(env, ARM_FEATURE_V5);
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            assert(!tcg_enabled() || no_aa32 ||
+                   cpu_isar_feature(aa32_jazelle, cpu));
+            set_feature(env, ARM_FEATURE_AUXCR);
+        }
+    }
+    if (arm_feature(env, ARM_FEATURE_V5)) {
+        set_feature(env, ARM_FEATURE_V4T);
+    }
+    if (arm_feature(env, ARM_FEATURE_LPAE)) {
+        set_feature(env, ARM_FEATURE_V7MP);
+    }
+    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
+        set_feature(env, ARM_FEATURE_CBAR);
+    }
+    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
+        !arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_THUMB_DSP);
+    }
+}
+
 void arm_cpu_post_init(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
-    /* M profile implies PMSA. We have to do this here rather than
-     * in realize with the other feature-implication checks because
-     * we look at the PMSA bit to see if we should add some properties.
+    /*
+     * Some features imply others. Figure this out now, because we
+     * are going to look at the feature bits in deciding which
+     * properties to add.
      */
-    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
-        set_feature(&cpu->env, ARM_FEATURE_PMSA);
-    }
+    arm_cpu_propagate_feature_implications(cpu);
 
     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     CPUARMState *env = &cpu->env;
     int pagebits;
     Error *local_err = NULL;
-    bool no_aa32 = false;
 
     /* Use pc-relative instructions in system-mode */
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         cpu->isar.id_isar3 = u;
     }
 
-    /* Some features automatically imply others: */
-    if (arm_feature(env, ARM_FEATURE_V8)) {
-        if (arm_feature(env, ARM_FEATURE_M)) {
-            set_feature(env, ARM_FEATURE_V7);
-        } else {
-            set_feature(env, ARM_FEATURE_V7VE);
-        }
-    }
-
-    /*
-     * There exist AArch64 cpus without AArch32 support.  When KVM
-     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
-     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
-     * As a general principle, we also do not make ID register
-     * consistency checks anywhere unless using TCG, because only
-     * for TCG would a consistency-check failure be a QEMU bug.
-     */
-    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
-        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
-    }
-
-    if (arm_feature(env, ARM_FEATURE_V7VE)) {
-        /* v7 Virtualization Extensions. In real hardware this implies
-         * EL2 and also the presence of the Security Extensions.
-         * For QEMU, for backwards-compatibility we implement some
-         * CPUs or CPU configs which have no actual EL2 or EL3 but do
-         * include the various other features that V7VE implies.
-         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
-         * Security Extensions is ARM_FEATURE_EL3.
-         */
-        assert(!tcg_enabled() || no_aa32 ||
-               cpu_isar_feature(aa32_arm_div, cpu));
-        set_feature(env, ARM_FEATURE_LPAE);
-        set_feature(env, ARM_FEATURE_V7);
-    }
-    if (arm_feature(env, ARM_FEATURE_V7)) {
-        set_feature(env, ARM_FEATURE_VAPA);
-        set_feature(env, ARM_FEATURE_THUMB2);
-        set_feature(env, ARM_FEATURE_MPIDR);
-        if (!arm_feature(env, ARM_FEATURE_M)) {
-            set_feature(env, ARM_FEATURE_V6K);
-        } else {
-            set_feature(env, ARM_FEATURE_V6);
-        }
-
-        /* Always define VBAR for V7 CPUs even if it doesn't exist in
-         * non-EL3 configs. This is needed by some legacy boards.
-         */
-        set_feature(env, ARM_FEATURE_VBAR);
-    }
-    if (arm_feature(env, ARM_FEATURE_V6K)) {
-        set_feature(env, ARM_FEATURE_V6);
-        set_feature(env, ARM_FEATURE_MVFR);
-    }
-    if (arm_feature(env, ARM_FEATURE_V6)) {
-        set_feature(env, ARM_FEATURE_V5);
-        if (!arm_feature(env, ARM_FEATURE_M)) {
-            assert(!tcg_enabled() || no_aa32 ||
-                   cpu_isar_feature(aa32_jazelle, cpu));
-            set_feature(env, ARM_FEATURE_AUXCR);
-        }
-    }
-    if (arm_feature(env, ARM_FEATURE_V5)) {
-        set_feature(env, ARM_FEATURE_V4T);
-    }
-    if (arm_feature(env, ARM_FEATURE_LPAE)) {
-        set_feature(env, ARM_FEATURE_V7MP);
-    }
-    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
-        set_feature(env, ARM_FEATURE_CBAR);
-    }
-    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
-        !arm_feature(env, ARM_FEATURE_M)) {
-        set_feature(env, ARM_FEATURE_THUMB_DSP);
-    }
 
     /*
      * We rely on no XScale CPU having VFP so we can use the same bits in the
-- 
2.34.1

M-profile CPUs generally allow configuration of the number of MPU
regions that they have.  We don't currently model this, so our
implementations of some of the board models provide CPUs with the
wrong number of regions.  RTOSes like Zephyr that hardcode the
expected number of regions may therefore not run on the model if they
are set up to run on real hardware.

Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
matching the ability of hardware to configure the number of Secure
and NonSecure regions separately.  Our actual CPU implementation
doesn't currently support that, and it happens that none of the MPS
boards we model set the number of regions differently for Secure vs
NonSecure, so we provide an interface to the boards and SoCs that
won't need to change if we ever do add that functionality in future,
but make it an error to configure the two properties to different
values.

(The property name on the CPU is the somewhat misnamed-for-M-profile
"pmsav7-dregion", so we don't follow that naming convention for
the properties here. The TRM doesn't say what the CPU configuration
variable names are, so we pick something, and follow the lowercase
convention we already have for properties here.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
---
 include/hw/arm/armv7m.h |  8 ++++++++
 hw/arm/armv7m.c         | 21 +++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
  * + Property "vfp": enable VFP (forwarded to CPU object)
  * + Property "dsp": enable DSP (forwarded to CPU object)
  * + Property "enable-bitband": expose bitbanded IO
+ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
+ *   to CPU object pmsav7-dregion property; default is whatever the default
+ *   for the CPU is)
+ * + Property "mpu-s-regions": number of Secure MPU regions (default is
+ *   whatever the default for the CPU is; must currently be set to the same
+ *   value as mpu-ns-regions if the CPU implements the Security Extension)
  * + Clock input "refclk" is the external reference clock for the systick timers
  * + Clock input "cpuclk" is the main CPU clock
  */
@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
     Object *idau;
     uint32_t init_svtor;
     uint32_t init_nsvtor;
+    uint32_t mpu_ns_regions;
+    uint32_t mpu_s_regions;
     bool enable_bitband;
     bool start_powered_off;
     bool vfp;
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
         }
     }
 
+    /*
+     * Real M-profile hardware can be configured with a different number of
+     * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
+     * support that yet, so catch attempts to select that.
+     */
+    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
+        s->mpu_ns_regions != s->mpu_s_regions) {
+        error_setg(errp,
+                   "mpu-ns-regions and mpu-s-regions properties must have the same value");
+        return;
+    }
+    if (s->mpu_ns_regions != UINT_MAX &&
+        object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
+        if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
+                                      s->mpu_ns_regions, errp)) {
+            return;
+        }
+    }
+
     /*
      * Tell the CPU where the NVIC is; it will fail realize if it doesn't
      * have one. Similarly, tell the NVIC where its CPU is.
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
                      false),
     DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
     DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
+    DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
+    DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.34.1

The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
MPS2/MPS3 FPGA images don't override these except in the case of
AN547, which uses 16 MPU regions.

Define properties on the ARMSSE object for the MPU regions (using the
same names as the documented RTL configuration settings, and
following the pattern we already have for this device of using
all-caps names as the RTL does), and set them in the board code.

We don't actually need to override the default except on AN547,
but it's simpler code to have the board code set them always
rather than tracking which board subtypes want to set them to
a non-default value separately from what that value is.

Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
we now correctly use 8 MPU regions, while mps3-an547 stays at its
current 16 regions.

It's possible some guest code wrongly depended on the previous
incorrectly modeled number of memory regions. (Such guest code
should ideally check the number of regions via the MPU_TYPE
register.) The old behaviour can be obtained with additional
-global arguments to QEMU:

For mps2-an521 and mps2-an524:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16

For mps2-an505:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16

NB that the way the implementation allows this use of -global
is slightly fragile: if the board code explicitly sets the
properties on the sse-200 object, this overrides the -global
command line option. So we rely on:
 - the boards that need fixing all happen to use the SSE defaults
 - we can write the board code to only set the property if it
   is different from the default, rather than having all boards
   explicitly set the property
 - the board that does need to use a non-default value happens
   to need to set it to the same value (16) we previously used
This works, but there are some kinds of refactoring of the
mps2-tz.c code that would break the support for -global here.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
---
 include/hw/arm/armsse.h |  5 +++++
 hw/arm/armsse.c         | 16 ++++++++++++++++
 hw/arm/mps2-tz.c        | 29 +++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -XXX,XX +XXX,XX @@
  *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
  *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
  *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
+ *  + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
+ *    which set the number of MPU regions on the CPUs. If there is only one
+ *    CPU the CPU1 properties are not present.
  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
  *    which are wired to its NVIC lines 32 .. n+32
  *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
     uint32_t exp_numirq;
     uint32_t sram_addr_width;
     uint32_t init_svtor;
+    uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
+    uint32_t cpu_mpu_s[SSE_MAX_CPUS];
     bool cpu_fpu[SSE_MAX_CPUS];
     bool cpu_dsp[SSE_MAX_CPUS];
 };
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
     DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
     DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
+    DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
+    DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                 return;
             }
         }
+        if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
+                                      s->cpu_mpu_ns[i], errp)) {
+            return;
+        }
+        if (!object_property_set_uint(cpuobj, "mpu-s-regions",
+                                      s->cpu_mpu_s[i], errp)) {
+            return;
+        }
 
         if (i > 0) {
             memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
     int uart_overflow_irq; /* number of the combined UART overflow IRQ */
     uint32_t init_svtor; /* init-svtor setting for SSE */
     uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
+    uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
+    uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
+    uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
+    uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
     const RAMInfo *raminfo;
     const char *armsse_type;
     uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
 #define MPS3_DDR_SIZE (2 * GiB)
 #endif
 
+/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
+#define MPU_REGION_DEFAULT UINT32_MAX
+
 static const uint32_t an505_oscclk[] = {
     40000000,
     24580000,
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                              OBJECT(system_memory), &error_abort);
     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
     qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
+    if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
+        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
+    }
+    if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
+        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
+    }
+    if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
+        if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
+            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
+        }
+        if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
+            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
+        }
+    }
     qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
     qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
     qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
+    MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 
     mc->init = mps2tz_common_init;
     mc->reset = mps2_machine_reset;
     iic->check = mps2_tz_idau_check;
+
+    /* Most machines leave these at the SSE defaults */
+    mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
+    mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
+    mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
+    mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
 }
 
 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
     mmc->numirq = 96;
     mmc->uart_overflow_irq = 48;
     mmc->init_svtor = 0x00000000;
+    mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
     mmc->sram_addr_width = 21;
     mmc->raminfo = an547_raminfo;
     mmc->armsse_type = TYPE_SSE300;
-- 
2.34.1