Series comparison

-[PULL 0/9] target-arm queue
+[PULL 00/31] target-arm queue
-target-arm queue: nothing major here, but no point
+First arm pullreq for 7.1. The bulk of this is the qemu_split_irq
-sitting on them waiting for more stuff to come along.
+removal.
 I have enough stuff in my to-review queue that I expect to do another
 pullreq early next week, but 31 patches is enough to not hang on to.
 thanks
 -- PMM
-The following changes since commit 1329132d28bf14b9508f7a1f04a2c63422bc3f99:
+The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b:
-  Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2019-09-26 16:14:03 +0100)
+  Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging (2022-04-20 16:43:11 -0700)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190927
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220421
-for you to fetch changes up to e4e34855e658b78ecac50a651cc847662ff02cfd:
+for you to fetch changes up to 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6:
-  hw/arm/boot: Use the IEC binary prefix definitions (2019-09-27 11:44:39 +0100)
+  hw/arm: Use bit fields for NPCM7XX PWRON STRAPs (2022-04-21 11:37:05 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * Fix the CBAR register implementation for Cortex-A53,
+ * hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
-   Cortex-A57, Cortex-A72
+ * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
- * Fix direct booting of Linux kernels on emulated CPUs
+ * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s
-   which have an AArch32 EL3 (incorrect NSACR settings
+ * xlnx-zynqmp: Connect 4 TTC timers
-   meant they could not access the FPU)
+ * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq
- * semihosting cleanup: do more work at translate time
+ * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
-   and less work at runtime
+ * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
  * hw/core/irq: remove unused 'qemu_irq_split' function
  * npcm7xx: use symbolic constants for PWRON STRAP bit fields
  * virt: document impact of gic-version on max CPUs
 ----------------------------------------------------------------
-Alex Bennée (6):
+Edgar E. Iglesias (6):
-      tests/tcg: clean-up some comments after the de-tangling
+      timer: cadence_ttc: Break out header file to allow embedding
-      target/arm: handle M-profile semihosting at translate time
+      hw/arm/xlnx-zynqmp: Connect 4 TTC timers
-      target/arm: handle A-profile semihosting at translate time
+      hw/arm: versal: Create an APU CPU Cluster
-      target/arm: remove run time semihosting checks
+      hw/arm: versal: Add the Cortex-R5Fs
-      target/arm: remove run-time semihosting checks for linux-user
+      hw/misc: Add a model of the Xilinx Versal CRL
-      tests/tcg: add linux-user semihosting smoke test for ARM
+      hw/arm: versal: Connect the CRL
-Luc Michel (1):
+Hao Wu (2):
-      target/arm: fix CBAR register for AArch64 CPUs
+      hw/misc: Add PWRON STRAP bit fields in GCR module
       hw/arm: Use bit fields for NPCM7XX PWRON STRAPs
-Peter Maydell (1):
+Heinrich Schuchardt (1):
-      hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
+      hw/arm/virt: impact of gic-version on max CPUs
-Philippe Mathieu-Daudé (1):
+Peter Maydell (19):
-      hw/arm/boot: Use the IEC binary prefix definitions
+      hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
       hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device
       hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
       hw/arm/exynos4210: Put a9mpcore device into state struct
       hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct
       hw/arm/exynos4210: Coalesce board_irqs and irq_table
       hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
       hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
       hw/arm/exynos4210: Put external GIC into state struct
       hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
       hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c
       hw/arm/exynos4210: Delete unused macro definitions
       hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
       hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines
       hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
       hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
       hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
       hw/arm/exynos4210: Put combiners into state struct
       hw/arm/exynos4210: Drop Exynos4210Irq struct
- tests/tcg/Makefile.target         |   7 ++-
+Zongyuan Li (3):
- tests/tcg/aarch64/Makefile.target |   8 ++-
+      hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
- tests/tcg/arm/Makefile.target     |  20 ++++---
+      hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
- linux-user/arm/target_syscall.h   |   3 -
+      hw/core/irq: remove unused 'qemu_irq_split' function
  hw/arm/boot.c                     |  12 ++--
  linux-user/arm/cpu_loop.c         |   3 -
  target/arm/helper.c               | 115 +++++++++++++-------------------------
  target/arm/m_helper.c             |  18 ++----
  target/arm/translate.c            |  30 ++++++++--
  tests/tcg/arm/semihosting.c       |  45 +++++++++++++++
 files changed, 146 insertions(+), 115 deletions(-)
  create mode 100644 tests/tcg/arm/semihosting.c
+ docs/system/arm/virt.rst              |   4 +-
+ include/hw/arm/exynos4210.h           |  50 ++--
+ include/hw/arm/xlnx-versal.h          |  16 ++
+ include/hw/arm/xlnx-zynqmp.h          |   4 +
+ include/hw/intc/exynos4210_combiner.h |  57 +++++
+ include/hw/intc/exynos4210_gic.h      |  43 ++++
+ include/hw/irq.h                      |   5 -
+ include/hw/misc/npcm7xx_gcr.h         |  30 +++
+ include/hw/misc/xlnx-versal-crl.h     | 235 +++++++++++++++++++
+ include/hw/timer/cadence_ttc.h        |  54 +++++
+ hw/arm/exynos4210.c                   | 430 ++++++++++++++++++++++++++++++----
+ hw/arm/npcm7xx_boards.c               |  24 +-
+ hw/arm/realview.c                     |  33 ++-
+ hw/arm/stellaris.c                    |  15 +-
+ hw/arm/virt.c                         |   7 +
+ hw/arm/xlnx-versal-virt.c             |   6 +-
+ hw/arm/xlnx-versal.c                  |  99 +++++++-
+ hw/arm/xlnx-zynqmp.c                  |  22 ++
+ hw/core/irq.c                         |  15 --
+ hw/intc/exynos4210_combiner.c         | 108 +--------
+ hw/intc/exynos4210_gic.c              | 344 +--------------------------
+ hw/misc/xlnx-versal-crl.c             | 421 +++++++++++++++++++++++++++++++++
+ hw/timer/cadence_ttc.c                |  32 +--
+ MAINTAINERS                           |   2 +-
+ hw/misc/meson.build                   |   1 +
+files changed, 1457 insertions(+), 600 deletions(-)
+ create mode 100644 include/hw/intc/exynos4210_combiner.h
+ create mode 100644 include/hw/intc/exynos4210_gic.h
+ create mode 100644 include/hw/misc/xlnx-versal-crl.h
+ create mode 100644 include/hw/timer/cadence_ttc.h
+ create mode 100644 hw/misc/xlnx-versal-crl.c

-New patch
+[PULL 01/31] hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
+It's not possible to provide the guest with the Security extensions
+(TrustZone) when using KVM or HVF, because the hardware
+virtualization extensions don't permit running EL3 guest code.
+However, we weren't checking for this combination, with the result
+that QEMU would assert if you tried it:
+$ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none
+Unexpected error in object_property_find_err() at ../../qom/object.c:1304:
+qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found
+Aborted
+Check for this combination of options and report an error, in the
+same way we already do for attempts to give a KVM or HVF guest the
+Virtualization or MTE extensions. Now we will report:
+qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404155301.566542-1-peter.maydell@linaro.org
+---
+ hw/arm/virt.c | 7 +++++++
+file changed, 7 insertions(+)
+diff --git a/hw/arm/virt.c b/hw/arm/virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/virt.c
++++ b/hw/arm/virt.c
+@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
+         exit(1);
+     }
++    if (vms->secure && (kvm_enabled() || hvf_enabled())) {
++        error_report("mach-virt: %s does not support providing "
++                     "Security extensions (TrustZone) to the guest CPU",
++                     kvm_enabled() ? "KVM" : "HVF");
++        exit(1);
++    }
++
+     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
+         error_report("mach-virt: %s does not support providing "
+                      "Virtualization extensions to the guest CPU",
+--
+.25.1

-New patch
+[PULL 02/31] timer: cadence_ttc: Break out header file to allow embedding
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
+Break out header file to allow embedding of the the TTC.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Luc Michel <luc@lmichel.fr>
+Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++
+ hw/timer/cadence_ttc.c         | 32 ++------------------
+files changed, 56 insertions(+), 30 deletions(-)
+ create mode 100644 include/hw/timer/cadence_ttc.h
+diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/timer/cadence_ttc.h
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Xilinx Zynq cadence TTC model
++ *
++ * Copyright (c) 2011 Xilinx Inc.
++ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
++ * Copyright (c) 2012 PetaLogix Pty Ltd.
++ * Written By Haibing Ma
++ *            M. Habib
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++#ifndef HW_TIMER_CADENCE_TTC_H
++#define HW_TIMER_CADENCE_TTC_H
++
++#include "hw/sysbus.h"
++#include "qemu/timer.h"
++
++typedef struct {
++    QEMUTimer *timer;
++    int freq;
++
++    uint32_t reg_clock;
++    uint32_t reg_count;
++    uint32_t reg_value;
++    uint16_t reg_interval;
++    uint16_t reg_match[3];
++    uint32_t reg_intr;
++    uint32_t reg_intr_en;
++    uint32_t reg_event_ctrl;
++    uint32_t reg_event;
++
++    uint64_t cpu_time;
++    unsigned int cpu_time_valid;
++
++    qemu_irq irq;
++} CadenceTimerState;
++
++#define TYPE_CADENCE_TTC "cadence_ttc"
++OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
++
++struct CadenceTTCState {
++    SysBusDevice parent_obj;
++
++    MemoryRegion iomem;
++    CadenceTimerState timer[3];
++};
++
++#endif
+diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/timer/cadence_ttc.c
++++ b/hw/timer/cadence_ttc.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/timer.h"
+ #include "qom/object.h"
++#include "hw/timer/cadence_ttc.h"
++
+ #ifdef CADENCE_TTC_ERR_DEBUG
+ #define DB_PRINT(...) do { \
+     fprintf(stderr,  ": %s: ", __func__); \
+@@ -XXX,XX +XXX,XX @@
+ #define CLOCK_CTRL_PS_EN    0x00000001
+ #define CLOCK_CTRL_PS_V     0x0000001e
+-typedef struct {
+-    QEMUTimer *timer;
+-    int freq;
+-
+-    uint32_t reg_clock;
+-    uint32_t reg_count;
+-    uint32_t reg_value;
+-    uint16_t reg_interval;
+-    uint16_t reg_match[3];
+-    uint32_t reg_intr;
+-    uint32_t reg_intr_en;
+-    uint32_t reg_event_ctrl;
+-    uint32_t reg_event;
+-
+-    uint64_t cpu_time;
+-    unsigned int cpu_time_valid;
+-
+-    qemu_irq irq;
+-} CadenceTimerState;
+-
+-#define TYPE_CADENCE_TTC "cadence_ttc"
+-OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
+-
+-struct CadenceTTCState {
+-    SysBusDevice parent_obj;
+-
+-    MemoryRegion iomem;
+-    CadenceTimerState timer[3];
+-};
+-
+ static void cadence_timer_update(CadenceTimerState *s)
+ {
+     qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
+--
+.25.1

-New patch
+[PULL 03/31] hw/arm/xlnx-zynqmp: Connect 4 TTC timers
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
+Connect the 4 TTC timers on the ZynqMP.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Luc Michel <luc@lmichel.fr>
+Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/xlnx-zynqmp.h |  4 ++++
+ hw/arm/xlnx-zynqmp.c         | 22 ++++++++++++++++++++++
+files changed, 26 insertions(+)
+diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/xlnx-zynqmp.h
++++ b/include/hw/arm/xlnx-zynqmp.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/or-irq.h"
+ #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
+ #include "hw/misc/xlnx-zynqmp-crf.h"
++#include "hw/timer/cadence_ttc.h"
+ #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
+ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
+ #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
+                                   XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
++#define XLNX_ZYNQMP_NUM_TTC 4
++
+ /*
+  * Unimplemented mmio regions needed to boot some images.
+  */
+@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
+     qemu_or_irq qspi_irq_orgate;
+     XlnxZynqMPAPUCtrl apu_ctrl;
+     XlnxZynqMPCRF crf;
++    CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
+     char *boot_cpu;
+     ARMCPU *boot_cpu_ptr;
+diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/xlnx-zynqmp.c
++++ b/hw/arm/xlnx-zynqmp.c
+@@ -XXX,XX +XXX,XX @@
+ #define APU_ADDR            0xfd5c0000
+ #define APU_IRQ             153
++#define TTC0_ADDR           0xFF110000
++#define TTC0_IRQ            36
++
+ #define IPI_ADDR            0xFF300000
+ #define IPI_IRQ             64
+@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
+     sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
+ }
++static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
++{
++    SysBusDevice *sbd;
++    int i, irq;
++
++    for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
++        object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
++                                TYPE_CADENCE_TTC);
++        sbd = SYS_BUS_DEVICE(&s->ttc[i]);
++
++        sysbus_realize(sbd, &error_fatal);
++        sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
++        for (irq = 0; irq < 3; irq++) {
++            sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
++        }
++    }
++}
++
+ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
+ {
+     static const struct UnimpInfo {
+@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
+     xlnx_zynqmp_create_efuse(s, gic_spi);
+     xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
+     xlnx_zynqmp_create_crf(s, gic_spi);
++    xlnx_zynqmp_create_ttc(s, gic_spi);
+     xlnx_zynqmp_create_unimp_mmio(s);
+     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
+--
+.25.1

-New patch
+[PULL 04/31] hw/arm: versal: Create an APU CPU Cluster
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
+Create an APU CPU Cluster. This is in preparation to add the RPU.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
+Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/xlnx-versal.h | 2 ++
+ hw/arm/xlnx-versal.c         | 9 ++++++++-
+files changed, 10 insertions(+), 1 deletion(-)
+diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/xlnx-versal.h
++++ b/include/hw/arm/xlnx-versal.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "hw/arm/boot.h"
++#include "hw/cpu/cluster.h"
+ #include "hw/or-irq.h"
+ #include "hw/sd/sdhci.h"
+ #include "hw/intc/arm_gicv3.h"
+@@ -XXX,XX +XXX,XX @@ struct Versal {
+     struct {
+         struct {
+             MemoryRegion mr;
++            CPUClusterState cluster;
+             ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
+             GICv3State gic;
+         } apu;
+diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/xlnx-versal.c
++++ b/hw/arm/xlnx-versal.c
+@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
+ {
+     int i;
++    object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster,
++                            TYPE_CPU_CLUSTER);
++    qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0);
++
+     for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
+         Object *obj;
+-        object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
++        object_initialize_child(OBJECT(&s->fpd.apu.cluster),
++                                "apu-cpu[*]", &s->fpd.apu.cpu[i],
+                                 XLNX_VERSAL_ACPU_TYPE);
+         obj = OBJECT(&s->fpd.apu.cpu[i]);
+         if (i) {
+@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
+                                  &error_abort);
+         qdev_realize(DEVICE(obj), NULL, &error_fatal);
+     }
++
++    qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal);
+ }
+ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
+--
+.25.1

-New patch
+[PULL 05/31] hw/arm: versal: Add the Cortex-R5Fs
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
+Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit)
+subsystem.
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
+Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/xlnx-versal.h | 10 ++++++++++
+ hw/arm/xlnx-versal-virt.c    |  6 +++---
+ hw/arm/xlnx-versal.c         | 36 ++++++++++++++++++++++++++++++++++++
+files changed, 49 insertions(+), 3 deletions(-)
+diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/xlnx-versal.h
++++ b/include/hw/arm/xlnx-versal.h
+@@ -XXX,XX +XXX,XX @@
+ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
+ #define XLNX_VERSAL_NR_ACPUS   2
++#define XLNX_VERSAL_NR_RCPUS   2
+ #define XLNX_VERSAL_NR_UARTS   2
+ #define XLNX_VERSAL_NR_GEMS    2
+ #define XLNX_VERSAL_NR_ADMAS   8
+@@ -XXX,XX +XXX,XX @@ struct Versal {
+             VersalUsb2 usb;
+         } iou;
++        /* Real-time Processing Unit.  */
++        struct {
++            MemoryRegion mr;
++            MemoryRegion mr_ps_alias;
++
++            CPUClusterState cluster;
++            ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
++        } rpu;
++
+         struct {
+             qemu_or_irq irq_orgate;
+             XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
+diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/xlnx-versal-virt.c
++++ b/hw/arm/xlnx-versal-virt.c
+@@ -XXX,XX +XXX,XX @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
+     mc->desc = "Xilinx Versal Virtual development board";
+     mc->init = versal_virt_init;
+-    mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
+-    mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
+-    mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
++    mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
++    mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
++    mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
+     mc->no_cdrom = true;
+     mc->default_ram_id = "ddr";
+ }
+diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/xlnx-versal.c
++++ b/hw/arm/xlnx-versal.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
++#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
+ #define GEM_REVISION        0x40070106
+ #define VERSAL_NUM_PMC_APB_IRQS 3
+@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
+     }
+ }
++static void versal_create_rpu_cpus(Versal *s)
++{
++    int i;
++
++    object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster,
++                            TYPE_CPU_CLUSTER);
++    qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1);
++
++    for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
++        Object *obj;
++
++        object_initialize_child(OBJECT(&s->lpd.rpu.cluster),
++                                "rpu-cpu[*]", &s->lpd.rpu.cpu[i],
++                                XLNX_VERSAL_RCPU_TYPE);
++        obj = OBJECT(&s->lpd.rpu.cpu[i]);
++        object_property_set_bool(obj, "start-powered-off", true,
++                                 &error_abort);
++
++        object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort);
++        object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu),
++                                &error_abort);
++        object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr),
++                                 &error_abort);
++        qdev_realize(DEVICE(obj), NULL, &error_fatal);
++    }
++
++    qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal);
++}
++
+ static void versal_create_uarts(Versal *s, qemu_irq *pic)
+ {
+     int i;
+@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
+     versal_create_apu_cpus(s);
+     versal_create_apu_gic(s, pic);
++    versal_create_rpu_cpus(s);
+     versal_create_uarts(s, pic);
+     versal_create_usbs(s, pic);
+     versal_create_gems(s, pic);
+@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
+     memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
+     memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
++    memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0,
++                                        &s->lpd.rpu.mr_ps_alias, 0);
+ }
+ static void versal_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void versal_init(Object *obj)
+     Versal *s = XLNX_VERSAL(obj);
+     memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
++    memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX);
+     memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
++    memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s),
++                             "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX);
+ }
+ static Property versal_properties[] = {
+--
+.25.1

-[PULL 7/9] tests/tcg: add linux-user semihosting smoke test for ARM
+[PULL 06/31] hw/misc: Add a model of the Xilinx Versal CRL
-From: Alex Bennée <alex.bennee@linaro.org>
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
-We already use semihosting for the system stuff so this is a simple
+Add a model of the Xilinx Versal CRL.
 smoke test to ensure we are working OK on linux-user.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
-Message-id: 20190913151845.12582-7-alex.bennee@linaro.org
+Reviewed-by: Frederic Konrad <fkonrad@amd.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
 Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/tcg/aarch64/Makefile.target |  5 ++++
+ include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++
- tests/tcg/arm/Makefile.target     |  5 ++++
+ hw/misc/xlnx-versal-crl.c         | 421 ++++++++++++++++++++++++++++++
- tests/tcg/arm/semihosting.c       | 45 +++++++++++++++++++++++++++++++
+ hw/misc/meson.build               |   1 +
-files changed, 55 insertions(+)
+files changed, 657 insertions(+)
- create mode 100644 tests/tcg/arm/semihosting.c
+ create mode 100644 include/hw/misc/xlnx-versal-crl.h
  create mode 100644 hw/misc/xlnx-versal-crl.c
-diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
+diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/tcg/aarch64/Makefile.target
 +++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
  AARCH64_TESTS += pauth-1 pauth-2
  run-pauth-%: QEMU_OPTS += -cpu max
 +# Semihosting smoke test for linux-user
 +AARCH64_TESTS += semihosting
 +run-semihosting: semihosting
 +    $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)")
 +
  TESTS += $(AARCH64_TESTS)
 diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/tcg/arm/Makefile.target
 +++ b/tests/tcg/arm/Makefile.target
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
      $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
      $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
 +# Semihosting smoke test for linux-user
 +ARM_TESTS += semihosting
 +run-semihosting: semihosting
 +    $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)")
 +
  TESTS += $(ARM_TESTS)
  # On ARM Linux only supports 4k pages
 diff --git a/tests/tcg/arm/semihosting.c b/tests/tcg/arm/semihosting.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
-+++ b/tests/tcg/arm/semihosting.c
++++ b/include/hw/misc/xlnx-versal-crl.h
 @@ -XXX,XX +XXX,XX @@
 +/*
-+ * linux-user semihosting checks
++ * QEMU model of the Clock-Reset-LPD (CRL).
 + *
-+ * Copyright (c) 2019
++ * Copyright (c) 2022 Xilinx Inc.
-+ * Written by Alex Bennée <alex.bennee@linaro.org>
++ * SPDX-License-Identifier: GPL-2.0-or-later
 + *
-+ * SPDX-License-Identifier: GPL-3.0-or-later
++ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
 + */
-+
++#ifndef HW_MISC_XLNX_VERSAL_CRL_H
-+#include <stdint.h>
++#define HW_MISC_XLNX_VERSAL_CRL_H
 +
-+#define SYS_WRITE0      0x04
++#include "hw/sysbus.h"
-+#define SYS_REPORTEXC   0x18
++#include "hw/register.h"
-+
++#include "target/arm/cpu.h"
-+void __semi_call(uintptr_t type, uintptr_t arg0)
++
-+{
++#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl"
-+#if defined(__arm__)
++OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
-+    register uintptr_t t asm("r0") = type;
++
-+    register uintptr_t a0 asm("r1") = arg0;
++REG32(ERR_CTRL, 0x0)
-+    asm("svc 0xab"
++    FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
-+        : /* no return */
++REG32(IR_STATUS, 0x4)
-+        : "r" (t), "r" (a0));
++    FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
-+#else
++REG32(IR_MASK, 0x8)
-+    register uintptr_t t asm("x0") = type;
++    FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
-+    register uintptr_t a0 asm("x1") = arg0;
++REG32(IR_ENABLE, 0xc)
-+    asm("hlt 0xf000"
++    FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
-+        : /* no return */
++REG32(IR_DISABLE, 0x10)
-+        : "r" (t), "r" (a0));
++    FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
 +REG32(WPROT, 0x1c)
 +    FIELD(WPROT, ACTIVE, 0, 1)
 +REG32(PLL_CLK_OTHER_DMN, 0x20)
 +    FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
 +REG32(RPLL_CTRL, 0x40)
 +    FIELD(RPLL_CTRL, POST_SRC, 24, 3)
 +    FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
 +    FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2)
 +    FIELD(RPLL_CTRL, FBDIV, 8, 8)
 +    FIELD(RPLL_CTRL, BYPASS, 3, 1)
 +    FIELD(RPLL_CTRL, RESET, 0, 1)
 +REG32(RPLL_CFG, 0x44)
 +    FIELD(RPLL_CFG, LOCK_DLY, 25, 7)
 +    FIELD(RPLL_CFG, LOCK_CNT, 13, 10)
 +    FIELD(RPLL_CFG, LFHF, 10, 2)
 +    FIELD(RPLL_CFG, CP, 5, 4)
 +    FIELD(RPLL_CFG, RES, 0, 4)
 +REG32(RPLL_FRAC_CFG, 0x48)
 +    FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1)
 +    FIELD(RPLL_FRAC_CFG, SEED, 22, 3)
 +    FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1)
 +    FIELD(RPLL_FRAC_CFG, ORDER, 18, 1)
 +    FIELD(RPLL_FRAC_CFG, DATA, 0, 16)
 +REG32(PLL_STATUS, 0x50)
 +    FIELD(PLL_STATUS, RPLL_STABLE, 2, 1)
 +    FIELD(PLL_STATUS, RPLL_LOCK, 0, 1)
 +REG32(RPLL_TO_XPD_CTRL, 0x100)
 +    FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1)
 +    FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
 +REG32(LPD_TOP_SWITCH_CTRL, 0x104)
 +    FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
 +    FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1)
 +    FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
 +    FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
 +REG32(LPD_LSBUS_CTRL, 0x108)
 +    FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1)
 +    FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10)
 +    FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3)
 +REG32(CPU_R5_CTRL, 0x10c)
 +    FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1)
 +    FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1)
 +    FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1)
 +    FIELD(CPU_R5_CTRL, CLKACT, 25, 1)
 +    FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10)
 +    FIELD(CPU_R5_CTRL, SRCSEL, 0, 3)
 +REG32(IOU_SWITCH_CTRL, 0x114)
 +    FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1)
 +    FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10)
 +    FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3)
 +REG32(GEM0_REF_CTRL, 0x118)
 +    FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1)
 +    FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1)
 +    FIELD(GEM0_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3)
 +REG32(GEM1_REF_CTRL, 0x11c)
 +    FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1)
 +    FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1)
 +    FIELD(GEM1_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3)
 +REG32(GEM_TSU_REF_CTRL, 0x120)
 +    FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3)
 +REG32(USB0_BUS_REF_CTRL, 0x124)
 +    FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3)
 +REG32(UART0_REF_CTRL, 0x128)
 +    FIELD(UART0_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(UART0_REF_CTRL, SRCSEL, 0, 3)
 +REG32(UART1_REF_CTRL, 0x12c)
 +    FIELD(UART1_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(UART1_REF_CTRL, SRCSEL, 0, 3)
 +REG32(SPI0_REF_CTRL, 0x130)
 +    FIELD(SPI0_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3)
 +REG32(SPI1_REF_CTRL, 0x134)
 +    FIELD(SPI1_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3)
 +REG32(CAN0_REF_CTRL, 0x138)
 +    FIELD(CAN0_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3)
 +REG32(CAN1_REF_CTRL, 0x13c)
 +    FIELD(CAN1_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3)
 +REG32(I2C0_REF_CTRL, 0x140)
 +    FIELD(I2C0_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3)
 +REG32(I2C1_REF_CTRL, 0x144)
 +    FIELD(I2C1_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3)
 +REG32(DBG_LPD_CTRL, 0x148)
 +    FIELD(DBG_LPD_CTRL, CLKACT, 25, 1)
 +    FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10)
 +    FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3)
 +REG32(TIMESTAMP_REF_CTRL, 0x14c)
 +    FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
 +REG32(CRL_SAFETY_CHK, 0x150)
 +REG32(PSM_REF_CTRL, 0x154)
 +    FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(PSM_REF_CTRL, SRCSEL, 0, 3)
 +REG32(DBG_TSTMP_CTRL, 0x158)
 +    FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1)
 +    FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10)
 +    FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
 +REG32(CPM_TOPSW_REF_CTRL, 0x15c)
 +    FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3)
 +REG32(USB3_DUAL_REF_CTRL, 0x160)
 +    FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1)
 +    FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10)
 +    FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3)
 +REG32(RST_CPU_R5, 0x300)
 +    FIELD(RST_CPU_R5, RESET_PGE, 4, 1)
 +    FIELD(RST_CPU_R5, RESET_AMBA, 2, 1)
 +    FIELD(RST_CPU_R5, RESET_CPU1, 1, 1)
 +    FIELD(RST_CPU_R5, RESET_CPU0, 0, 1)
 +REG32(RST_ADMA, 0x304)
 +    FIELD(RST_ADMA, RESET, 0, 1)
 +REG32(RST_GEM0, 0x308)
 +    FIELD(RST_GEM0, RESET, 0, 1)
 +REG32(RST_GEM1, 0x30c)
 +    FIELD(RST_GEM1, RESET, 0, 1)
 +REG32(RST_SPARE, 0x310)
 +    FIELD(RST_SPARE, RESET, 0, 1)
 +REG32(RST_USB0, 0x314)
 +    FIELD(RST_USB0, RESET, 0, 1)
 +REG32(RST_UART0, 0x318)
 +    FIELD(RST_UART0, RESET, 0, 1)
 +REG32(RST_UART1, 0x31c)
 +    FIELD(RST_UART1, RESET, 0, 1)
 +REG32(RST_SPI0, 0x320)
 +    FIELD(RST_SPI0, RESET, 0, 1)
 +REG32(RST_SPI1, 0x324)
 +    FIELD(RST_SPI1, RESET, 0, 1)
 +REG32(RST_CAN0, 0x328)
 +    FIELD(RST_CAN0, RESET, 0, 1)
 +REG32(RST_CAN1, 0x32c)
 +    FIELD(RST_CAN1, RESET, 0, 1)
 +REG32(RST_I2C0, 0x330)
 +    FIELD(RST_I2C0, RESET, 0, 1)
 +REG32(RST_I2C1, 0x334)
 +    FIELD(RST_I2C1, RESET, 0, 1)
 +REG32(RST_DBG_LPD, 0x338)
 +    FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1)
 +    FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1)
 +    FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1)
 +    FIELD(RST_DBG_LPD, RESET, 0, 1)
 +REG32(RST_GPIO, 0x33c)
 +    FIELD(RST_GPIO, RESET, 0, 1)
 +REG32(RST_TTC, 0x344)
 +    FIELD(RST_TTC, TTC3_RESET, 3, 1)
 +    FIELD(RST_TTC, TTC2_RESET, 2, 1)
 +    FIELD(RST_TTC, TTC1_RESET, 1, 1)
 +    FIELD(RST_TTC, TTC0_RESET, 0, 1)
 +REG32(RST_TIMESTAMP, 0x348)
 +    FIELD(RST_TIMESTAMP, RESET, 0, 1)
 +REG32(RST_SWDT, 0x34c)
 +    FIELD(RST_SWDT, RESET, 0, 1)
 +REG32(RST_OCM, 0x350)
 +    FIELD(RST_OCM, RESET, 0, 1)
 +REG32(RST_IPI, 0x354)
 +    FIELD(RST_IPI, RESET, 0, 1)
 +REG32(RST_SYSMON, 0x358)
 +    FIELD(RST_SYSMON, SEQ_RST, 1, 1)
 +    FIELD(RST_SYSMON, CFG_RST, 0, 1)
 +REG32(RST_FPD, 0x360)
 +    FIELD(RST_FPD, SRST, 1, 1)
 +    FIELD(RST_FPD, POR, 0, 1)
 +REG32(PSM_RST_MODE, 0x370)
 +    FIELD(PSM_RST_MODE, WAKEUP, 2, 1)
 +    FIELD(PSM_RST_MODE, RST_MODE, 0, 2)
 +
 +#define CRL_R_MAX (R_PSM_RST_MODE + 1)
 +
 +#define RPU_MAX_CPU 2
 +
 +struct XlnxVersalCRL {
 +    SysBusDevice parent_obj;
 +    qemu_irq irq;
 +
 +    struct {
 +        ARMCPU *cpu_r5[RPU_MAX_CPU];
 +        DeviceState *adma[8];
 +        DeviceState *uart[2];
 +        DeviceState *gem[2];
 +        DeviceState *usb;
 +    } cfg;
 +
 +    RegisterInfoArray *reg_array;
 +    uint32_t regs[CRL_R_MAX];
 +    RegisterInfo regs_info[CRL_R_MAX];
 +};
 +#endif
-+}
+diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
-+
+new file mode 100644
-+int main(int argc, char *argv[argc])
+index XXXXXXX..XXXXXXX
-+{
+--- /dev/null
-+#if defined(__arm__)
++++ b/hw/misc/xlnx-versal-crl.c
-+    uintptr_t exit_code = 0x20026;
+@@ -XXX,XX +XXX,XX @@
-+#else
++/*
-+    uintptr_t exit_block[2] = {0x20026, 0};
++ * QEMU model of the Clock-Reset-LPD (CRL).
-+    uintptr_t exit_code = (uintptr_t) &exit_block;
++ *
 + * Copyright (c) 2022 Advanced Micro Devices, Inc.
 + * SPDX-License-Identifier: GPL-2.0-or-later
 + *
 + * Written by Edgar E. Iglesias <edgar.iglesias@amd.com>
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qapi/error.h"
 +#include "qemu/log.h"
 +#include "qemu/bitops.h"
 +#include "migration/vmstate.h"
 +#include "hw/qdev-properties.h"
 +#include "hw/sysbus.h"
 +#include "hw/irq.h"
 +#include "hw/register.h"
 +#include "hw/resettable.h"
 +
 +#include "target/arm/arm-powerctl.h"
 +#include "hw/misc/xlnx-versal-crl.h"
 +
 +#ifndef XLNX_VERSAL_CRL_ERR_DEBUG
 +#define XLNX_VERSAL_CRL_ERR_DEBUG 0
 +#endif
 +
-+    __semi_call(SYS_WRITE0, (uintptr_t) "Hello World");
++static void crl_update_irq(XlnxVersalCRL *s)
-+    __semi_call(SYS_REPORTEXC, exit_code);
++{
-+    /* if we get here we failed */
++    bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
-+    return -1;
++    qemu_set_irq(s->irq, pending);
 +}
 +
 +static void crl_status_postw(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +    crl_update_irq(s);
 +}
 +
 +static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +    uint32_t val = val64;
 +
 +    s->regs[R_IR_MASK] &= ~val;
 +    crl_update_irq(s);
 +    return 0;
 +}
 +
 +static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +    uint32_t val = val64;
 +
 +    s->regs[R_IR_MASK] |= val;
 +    crl_update_irq(s);
 +    return 0;
 +}
 +
 +static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev,
 +                          bool rst_old, bool rst_new)
 +{
 +    device_cold_reset(dev);
 +}
 +
 +static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu,
 +                          bool rst_old, bool rst_new)
 +{
 +    if (rst_new) {
 +        arm_set_cpu_off(armcpu->mp_affinity);
 +    } else {
 +        arm_set_cpu_on_and_reset(armcpu->mp_affinity);
 +    }
 +}
 +
 +#define REGFIELD_RESET(type, s, reg, f, new_val, dev) {     \
 +    bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f);       \
 +    bool new_f = FIELD_EX32(new_val, reg, f);               \
 +                                                            \
 +    /* Detect edges.  */                                    \
 +    if (dev && old_f != new_f) {                            \
 +        crl_reset_ ## type(s, dev, old_f, new_f);           \
 +    }                                                       \
 +}
 +
 +static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]);
 +    REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]);
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +    int i;
 +
 +    /* A single register fans out to all ADMA reset inputs.  */
 +    for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) {
 +        REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]);
 +    }
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]);
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]);
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]);
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]);
 +    return val64;
 +}
 +
 +static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
 +
 +    REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb);
 +    return val64;
 +}
 +
 +static const RegisterAccessInfo crl_regs_info[] = {
 +    {   .name = "ERR_CTRL",  .addr = A_ERR_CTRL,
 +    },{ .name = "IR_STATUS",  .addr = A_IR_STATUS,
 +        .w1c = 0x1,
 +        .post_write = crl_status_postw,
 +    },{ .name = "IR_MASK",  .addr = A_IR_MASK,
 +        .reset = 0x1,
 +        .ro = 0x1,
 +    },{ .name = "IR_ENABLE",  .addr = A_IR_ENABLE,
 +        .pre_write = crl_enable_prew,
 +    },{ .name = "IR_DISABLE",  .addr = A_IR_DISABLE,
 +        .pre_write = crl_disable_prew,
 +    },{ .name = "WPROT",  .addr = A_WPROT,
 +    },{ .name = "PLL_CLK_OTHER_DMN",  .addr = A_PLL_CLK_OTHER_DMN,
 +        .reset = 0x1,
 +        .rsvd = 0xe,
 +    },{ .name = "RPLL_CTRL",  .addr = A_RPLL_CTRL,
 +        .reset = 0x24809,
 +        .rsvd = 0xf88c00f6,
 +    },{ .name = "RPLL_CFG",  .addr = A_RPLL_CFG,
 +        .reset = 0x2000000,
 +        .rsvd = 0x1801210,
 +    },{ .name = "RPLL_FRAC_CFG",  .addr = A_RPLL_FRAC_CFG,
 +        .rsvd = 0x7e330000,
 +    },{ .name = "PLL_STATUS",  .addr = A_PLL_STATUS,
 +        .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
 +                 R_PLL_STATUS_RPLL_LOCK_MASK,
 +        .rsvd = 0xfa,
 +        .ro = 0x5,
 +    },{ .name = "RPLL_TO_XPD_CTRL",  .addr = A_RPLL_TO_XPD_CTRL,
 +        .reset = 0x2000100,
 +        .rsvd = 0xfdfc00ff,
 +    },{ .name = "LPD_TOP_SWITCH_CTRL",  .addr = A_LPD_TOP_SWITCH_CTRL,
 +        .reset = 0x6000300,
 +        .rsvd = 0xf9fc00f8,
 +    },{ .name = "LPD_LSBUS_CTRL",  .addr = A_LPD_LSBUS_CTRL,
 +        .reset = 0x2000800,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "CPU_R5_CTRL",  .addr = A_CPU_R5_CTRL,
 +        .reset = 0xe000300,
 +        .rsvd = 0xe1fc00f8,
 +    },{ .name = "IOU_SWITCH_CTRL",  .addr = A_IOU_SWITCH_CTRL,
 +        .reset = 0x2000500,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "GEM0_REF_CTRL",  .addr = A_GEM0_REF_CTRL,
 +        .reset = 0xe000a00,
 +        .rsvd = 0xf1fc00f8,
 +    },{ .name = "GEM1_REF_CTRL",  .addr = A_GEM1_REF_CTRL,
 +        .reset = 0xe000a00,
 +        .rsvd = 0xf1fc00f8,
 +    },{ .name = "GEM_TSU_REF_CTRL",  .addr = A_GEM_TSU_REF_CTRL,
 +        .reset = 0x300,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "USB0_BUS_REF_CTRL",  .addr = A_USB0_BUS_REF_CTRL,
 +        .reset = 0x2001900,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "UART0_REF_CTRL",  .addr = A_UART0_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "UART1_REF_CTRL",  .addr = A_UART1_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "SPI0_REF_CTRL",  .addr = A_SPI0_REF_CTRL,
 +        .reset = 0x600,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "SPI1_REF_CTRL",  .addr = A_SPI1_REF_CTRL,
 +        .reset = 0x600,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "CAN0_REF_CTRL",  .addr = A_CAN0_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "CAN1_REF_CTRL",  .addr = A_CAN1_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "I2C0_REF_CTRL",  .addr = A_I2C0_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "I2C1_REF_CTRL",  .addr = A_I2C1_REF_CTRL,
 +        .reset = 0xc00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "DBG_LPD_CTRL",  .addr = A_DBG_LPD_CTRL,
 +        .reset = 0x300,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "TIMESTAMP_REF_CTRL",  .addr = A_TIMESTAMP_REF_CTRL,
 +        .reset = 0x2000c00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "CRL_SAFETY_CHK",  .addr = A_CRL_SAFETY_CHK,
 +    },{ .name = "PSM_REF_CTRL",  .addr = A_PSM_REF_CTRL,
 +        .reset = 0xf04,
 +        .rsvd = 0xfffc00f8,
 +    },{ .name = "DBG_TSTMP_CTRL",  .addr = A_DBG_TSTMP_CTRL,
 +        .reset = 0x300,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "CPM_TOPSW_REF_CTRL",  .addr = A_CPM_TOPSW_REF_CTRL,
 +        .reset = 0x300,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "USB3_DUAL_REF_CTRL",  .addr = A_USB3_DUAL_REF_CTRL,
 +        .reset = 0x3c00,
 +        .rsvd = 0xfdfc00f8,
 +    },{ .name = "RST_CPU_R5",  .addr = A_RST_CPU_R5,
 +        .reset = 0x17,
 +        .rsvd = 0x8,
 +        .pre_write = crl_rst_r5_prew,
 +    },{ .name = "RST_ADMA",  .addr = A_RST_ADMA,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_adma_prew,
 +    },{ .name = "RST_GEM0",  .addr = A_RST_GEM0,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_gem0_prew,
 +    },{ .name = "RST_GEM1",  .addr = A_RST_GEM1,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_gem1_prew,
 +    },{ .name = "RST_SPARE",  .addr = A_RST_SPARE,
 +        .reset = 0x1,
 +    },{ .name = "RST_USB0",  .addr = A_RST_USB0,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_usb_prew,
 +    },{ .name = "RST_UART0",  .addr = A_RST_UART0,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_uart0_prew,
 +    },{ .name = "RST_UART1",  .addr = A_RST_UART1,
 +        .reset = 0x1,
 +        .pre_write = crl_rst_uart1_prew,
 +    },{ .name = "RST_SPI0",  .addr = A_RST_SPI0,
 +        .reset = 0x1,
 +    },{ .name = "RST_SPI1",  .addr = A_RST_SPI1,
 +        .reset = 0x1,
 +    },{ .name = "RST_CAN0",  .addr = A_RST_CAN0,
 +        .reset = 0x1,
 +    },{ .name = "RST_CAN1",  .addr = A_RST_CAN1,
 +        .reset = 0x1,
 +    },{ .name = "RST_I2C0",  .addr = A_RST_I2C0,
 +        .reset = 0x1,
 +    },{ .name = "RST_I2C1",  .addr = A_RST_I2C1,
 +        .reset = 0x1,
 +    },{ .name = "RST_DBG_LPD",  .addr = A_RST_DBG_LPD,
 +        .reset = 0x33,
 +        .rsvd = 0xcc,
 +    },{ .name = "RST_GPIO",  .addr = A_RST_GPIO,
 +        .reset = 0x1,
 +    },{ .name = "RST_TTC",  .addr = A_RST_TTC,
 +        .reset = 0xf,
 +    },{ .name = "RST_TIMESTAMP",  .addr = A_RST_TIMESTAMP,
 +        .reset = 0x1,
 +    },{ .name = "RST_SWDT",  .addr = A_RST_SWDT,
 +        .reset = 0x1,
 +    },{ .name = "RST_OCM",  .addr = A_RST_OCM,
 +    },{ .name = "RST_IPI",  .addr = A_RST_IPI,
 +    },{ .name = "RST_FPD",  .addr = A_RST_FPD,
 +        .reset = 0x3,
 +    },{ .name = "PSM_RST_MODE",  .addr = A_PSM_RST_MODE,
 +        .reset = 0x1,
 +        .rsvd = 0xf8,
 +    }
 +};
 +
 +static void crl_reset_enter(Object *obj, ResetType type)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
 +    unsigned int i;
 +
 +    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
 +        register_reset(&s->regs_info[i]);
 +    }
 +}
 +
 +static void crl_reset_hold(Object *obj)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
 +
 +    crl_update_irq(s);
 +}
 +
 +static const MemoryRegionOps crl_ops = {
 +    .read = register_read_memory,
 +    .write = register_write_memory,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid = {
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +    },
 +};
 +
 +static void crl_init(Object *obj)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    int i;
 +
 +    s->reg_array =
 +        register_init_block32(DEVICE(obj), crl_regs_info,
 +                              ARRAY_SIZE(crl_regs_info),
 +                              s->regs_info, s->regs,
 +                              &crl_ops,
 +                              XLNX_VERSAL_CRL_ERR_DEBUG,
 +                              CRL_R_MAX * 4);
 +    sysbus_init_mmio(sbd, &s->reg_array->mem);
 +    sysbus_init_irq(sbd, &s->irq);
 +
 +    for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) {
 +        object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU,
 +                                 (Object **)&s->cfg.cpu_r5[i],
 +                                 qdev_prop_allow_set_link_before_realize,
 +                                 OBJ_PROP_LINK_STRONG);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) {
 +        object_property_add_link(obj, "adma[*]", TYPE_DEVICE,
 +                                 (Object **)&s->cfg.adma[i],
 +                                 qdev_prop_allow_set_link_before_realize,
 +                                 OBJ_PROP_LINK_STRONG);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) {
 +        object_property_add_link(obj, "uart[*]", TYPE_DEVICE,
 +                                 (Object **)&s->cfg.uart[i],
 +                                 qdev_prop_allow_set_link_before_realize,
 +                                 OBJ_PROP_LINK_STRONG);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) {
 +        object_property_add_link(obj, "gem[*]", TYPE_DEVICE,
 +                                 (Object **)&s->cfg.gem[i],
 +                                 qdev_prop_allow_set_link_before_realize,
 +                                 OBJ_PROP_LINK_STRONG);
 +    }
 +
 +    object_property_add_link(obj, "usb", TYPE_DEVICE,
 +                             (Object **)&s->cfg.gem[i],
 +                             qdev_prop_allow_set_link_before_realize,
 +                             OBJ_PROP_LINK_STRONG);
 +}
 +
 +static void crl_finalize(Object *obj)
 +{
 +    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
 +    register_finalize_block(s->reg_array);
 +}
 +
 +static const VMStateDescription vmstate_crl = {
 +    .name = TYPE_XLNX_VERSAL_CRL,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX),
 +        VMSTATE_END_OF_LIST(),
 +    }
 +};
 +
 +static void crl_class_init(ObjectClass *klass, void *data)
 +{
 +    ResettableClass *rc = RESETTABLE_CLASS(klass);
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->vmsd = &vmstate_crl;
 +
 +    rc->phases.enter = crl_reset_enter;
 +    rc->phases.hold = crl_reset_hold;
 +}
 +
 +static const TypeInfo crl_info = {
 +    .name          = TYPE_XLNX_VERSAL_CRL,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(XlnxVersalCRL),
 +    .class_init    = crl_class_init,
 +    .instance_init = crl_init,
 +    .instance_finalize = crl_finalize,
 +};
 +
 +static void crl_register_types(void)
 +{
 +    type_register_static(&crl_info);
 +}
 +
 +type_init(crl_register_types)
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
  softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
  specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
  specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
 +specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
  softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
    'xlnx-versal-xramc.c',
    'xlnx-versal-pmc-iou-slcr.c',
 --
-.20.1
+.25.1

-[PULL 4/9] target/arm: handle A-profile semihosting at translate time
+[PULL 07/31] hw/arm: versal: Connect the CRL
-From: Alex Bennée <alex.bennee@linaro.org>
+From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
-As for the other semihosting calls we can resolve this at translate
+Connect the CRL (Clock Reset LPD) to the Versal SoC.
 time.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Frederic Konrad <fkonrad@amd.com>
-Message-id: 20190913151845.12582-4-alex.bennee@linaro.org
+Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
 Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.c | 19 +++++++++++++++----
+ include/hw/arm/xlnx-versal.h |  4 +++
-file changed, 15 insertions(+), 4 deletions(-)
+ hw/arm/xlnx-versal.c         | 54 ++++++++++++++++++++++++++++++++++--
 files changed, 56 insertions(+), 2 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/include/hw/arm/xlnx-versal.h
-+++ b/target/arm/translate.c
++++ b/include/hw/arm/xlnx-versal.h
-@@ -XXX,XX +XXX,XX @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
+@@ -XXX,XX +XXX,XX @@
  #include "hw/nvram/xlnx-versal-efuse.h"
  #include "hw/ssi/xlnx-versal-ospi.h"
  #include "hw/dma/xlnx_csu_dma.h"
 +#include "hw/misc/xlnx-versal-crl.h"
  #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
  #define TYPE_XLNX_VERSAL "xlnx-versal"
@@ -XXX,XX +XXX,XX @@ struct Versal {
              qemu_or_irq irq_orgate;
              XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
          } xram;
 +
 +        XlnxVersalCRL crl;
      } lpd;
      /* The Platform Management Controller subsystem.  */
@@ -XXX,XX +XXX,XX @@ struct Versal {
  #define VERSAL_TIMER_NS_EL1_IRQ     14
  #define VERSAL_TIMER_NS_EL2_IRQ     10
 +#define VERSAL_CRL_IRQ             10
  #define VERSAL_UART0_IRQ_0         18
  #define VERSAL_UART1_IRQ_0         19
  #define VERSAL_USB0_IRQ_0          22
 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal.c
 +++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_ospi(Versal *s, qemu_irq *pic)
      qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
  }
- /*
++static void versal_create_crl(Versal *s, qemu_irq *pic)
-- * Supervisor call
++{
-+ * Supervisor call - both T32 & A32 come here so we need to check
++    SysBusDevice *sbd;
-+ * which mode we are in when checking for semihosting.
++    int i;
 +
 +    object_initialize_child(OBJECT(s), "crl", &s->lpd.crl,
 +                            TYPE_XLNX_VERSAL_CRL);
 +    sbd = SYS_BUS_DEVICE(&s->lpd.crl);
 +
 +    for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
 +        g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i);
 +
 +        object_property_set_link(OBJECT(&s->lpd.crl),
 +                                 name, OBJECT(&s->lpd.rpu.cpu[i]),
 +                                 &error_abort);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
 +        g_autofree gchar *name = g_strdup_printf("gem[%d]", i);
 +
 +        object_property_set_link(OBJECT(&s->lpd.crl),
 +                                 name, OBJECT(&s->lpd.iou.gem[i]),
 +                                 &error_abort);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
 +        g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
 +
 +        object_property_set_link(OBJECT(&s->lpd.crl),
 +                                 name, OBJECT(&s->lpd.iou.adma[i]),
 +                                 &error_abort);
 +    }
 +
 +    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
 +        g_autofree gchar *name = g_strdup_printf("uart[%d]", i);
 +
 +        object_property_set_link(OBJECT(&s->lpd.crl),
 +                                 name, OBJECT(&s->lpd.iou.uart[i]),
 +                                 &error_abort);
 +    }
 +
 +    object_property_set_link(OBJECT(&s->lpd.crl),
 +                             "usb", OBJECT(&s->lpd.iou.usb),
 +                             &error_abort);
 +
 +    sysbus_realize(sbd, &error_fatal);
 +    memory_region_add_subregion(&s->mr_ps, MM_CRL,
 +                                sysbus_mmio_get_region(sbd, 0));
 +    sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]);
 +}
 +
  /* This takes the board allocated linear DDR memory and creates aliases
   * for each split DDR range/aperture on the Versal address map.
   */
+@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
- static bool trans_SVC(DisasContext *s, arg_SVC *a)
- {
+     versal_unimp_area(s, "psm", &s->mr_ps,
--    gen_set_pc_im(s, s->base.pc_next);
+                         MM_PSM_START, MM_PSM_END - MM_PSM_START);
--    s->svc_imm = a->imm;
+-    versal_unimp_area(s, "crl", &s->mr_ps,
--    s->base.is_jmp = DISAS_SWI;
+-                        MM_CRL, MM_CRL_SIZE);
-+    const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456;
+     versal_unimp_area(s, "crf", &s->mr_ps,
-+
+                         MM_FPD_CRF, MM_FPD_CRF_SIZE);
-+    if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() &&
+     versal_unimp_area(s, "apu", &s->mr_ps,
-+#ifndef CONFIG_USER_ONLY
+@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
-+        !IS_USER(s) &&
+     versal_create_efuse(s, pic);
-+#endif
+     versal_create_pmc_iou_slcr(s, pic);
-+        (a->imm == semihost_imm)) {
+     versal_create_ospi(s, pic);
-+        gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
++    versal_create_crl(s, pic);
-+    } else {
+     versal_map_ddr(s);
-+        gen_set_pc_im(s, s->base.pc_next);
+     versal_unimp(s);
 +        s->svc_imm = a->imm;
 +        s->base.is_jmp = DISAS_SWI;
 +    }
      return true;
  }
 --
-.20.1
+.25.1

-New patch
+[PULL 08/31] hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device
+The Exynos4210 SoC device currently uses a custom device
+"exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ
+line.  We have a standard TYPE_OR_IRQ device for this now, so use
+that instead.
+(This is a migration compatibility break, but that is OK for this
+machine type.)
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-2-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  1 +
+ hw/arm/exynos4210.c         | 31 ++++++++++++++++---------------
+files changed, 17 insertions(+), 15 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
+     MemoryRegion bootreg_mem;
+     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
+     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
++    qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+ };
+ #define TYPE_EXYNOS4210_SOC "exynos4210"
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+ {
+     Exynos4210State *s = EXYNOS4210_SOC(socdev);
+     MemoryRegion *system_mem = get_system_memory();
+-    qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
+     SysBusDevice *busdev;
+     DeviceState *dev, *uart[4], *pl330[3];
+     int i, n;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     /* IRQ Gate */
+     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
+-        dev = qdev_new("exynos4210.irq_gate");
+-        qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
+-        sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+-        /* Get IRQ Gate input in gate_irq */
+-        for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
+-            gate_irq[i][n] = qdev_get_gpio_in(dev, n);
+-        }
+-        busdev = SYS_BUS_DEVICE(dev);
+-
+-        /* Connect IRQ Gate output to CPU's IRQ line */
+-        sysbus_connect_irq(busdev, 0,
+-                           qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
++        DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
++        object_property_set_int(OBJECT(orgate), "num-lines",
++                                EXYNOS4210_IRQ_GATE_NINPUTS,
++                                &error_abort);
++        qdev_realize(orgate, NULL, &error_abort);
++        qdev_connect_gpio_out(orgate, 0,
++                              qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
+     }
+     /* Private memory region and Internal GIC */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     sysbus_realize_and_unref(busdev, &error_fatal);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
+     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
+-        sysbus_connect_irq(busdev, n, gate_irq[n][0]);
++        sysbus_connect_irq(busdev, n,
++                           qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
+     }
+     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
+         s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     /* Map Distributer interface */
+     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
+     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
+-        sysbus_connect_irq(busdev, n, gate_irq[n][1]);
++        sysbus_connect_irq(busdev, n,
++                           qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
+     }
+     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
+         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
+         object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
+         g_free(name);
+     }
++
++    for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
++        g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
++        object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
++    }
+ }
+ static void exynos4210_class_init(ObjectClass *klass, void *data)
+--
+.25.1

-New patch
+[PULL 09/31] hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
+Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can
+delete the device entirely.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
+Message-id: 20220404154658.565020-3-peter.maydell@linaro.org
+---
+ hw/intc/exynos4210_gic.c | 107 ---------------------------------------
+file changed, 107 deletions(-)
+diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_gic.c
++++ b/hw/intc/exynos4210_gic.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_register_types(void)
+ }
+ type_init(exynos4210_gic_register_types)
+-
+-/* IRQ OR Gate struct.
+- *
+- * This device models an OR gate. There are n_in input qdev gpio lines and one
+- * output sysbus IRQ line. The output IRQ level is formed as OR between all
+- * gpio inputs.
+- */
+-
+-#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
+-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE)
+-
+-struct Exynos4210IRQGateState {
+-    SysBusDevice parent_obj;
+-
+-    uint32_t n_in;      /* inputs amount */
+-    uint32_t *level;    /* input levels */
+-    qemu_irq out;       /* output IRQ */
+-};
+-
+-static Property exynos4210_irq_gate_properties[] = {
+-    DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
+-    DEFINE_PROP_END_OF_LIST(),
+-};
+-
+-static const VMStateDescription vmstate_exynos4210_irq_gate = {
+-    .name = "exynos4210.irq_gate",
+-    .version_id = 2,
+-    .minimum_version_id = 2,
+-    .fields = (VMStateField[]) {
+-        VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in),
+-        VMSTATE_END_OF_LIST()
+-    }
+-};
+-
+-/* Process a change in IRQ input. */
+-static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
+-{
+-    Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque;
+-    uint32_t i;
+-
+-    assert(irq < s->n_in);
+-
+-    s->level[irq] = level;
+-
+-    for (i = 0; i < s->n_in; i++) {
+-        if (s->level[i] >= 1) {
+-            qemu_irq_raise(s->out);
+-            return;
+-        }
+-    }
+-
+-    qemu_irq_lower(s->out);
+-}
+-
+-static void exynos4210_irq_gate_reset(DeviceState *d)
+-{
+-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);
+-
+-    memset(s->level, 0, s->n_in * sizeof(*s->level));
+-}
+-
+-/*
+- * IRQ Gate initialization.
+- */
+-static void exynos4210_irq_gate_init(Object *obj)
+-{
+-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj);
+-    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+-
+-    sysbus_init_irq(sbd, &s->out);
+-}
+-
+-static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp)
+-{
+-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);
+-
+-    /* Allocate general purpose input signals and connect a handler to each of
+-     * them */
+-    qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);
+-
+-    s->level = g_malloc0(s->n_in * sizeof(*s->level));
+-}
+-
+-static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
+-{
+-    DeviceClass *dc = DEVICE_CLASS(klass);
+-
+-    dc->reset = exynos4210_irq_gate_reset;
+-    dc->vmsd = &vmstate_exynos4210_irq_gate;
+-    device_class_set_props(dc, exynos4210_irq_gate_properties);
+-    dc->realize = exynos4210_irq_gate_realize;
+-}
+-
+-static const TypeInfo exynos4210_irq_gate_info = {
+-    .name          = TYPE_EXYNOS4210_IRQ_GATE,
+-    .parent        = TYPE_SYS_BUS_DEVICE,
+-    .instance_size = sizeof(Exynos4210IRQGateState),
+-    .instance_init = exynos4210_irq_gate_init,
+-    .class_init    = exynos4210_irq_gate_class_init,
+-};
+-
+-static void exynos4210_irq_gate_register_types(void)
+-{
+-    type_register_static(&exynos4210_irq_gate_info);
+-}
+-
+-type_init(exynos4210_irq_gate_register_types)
+--
+.25.1

-New patch
+[PULL 10/31] hw/arm/exynos4210: Put a9mpcore device into state struct
+The exynos4210 SoC mostly creates its child devices as if it were
+board code.  This includes the a9mpcore object.  Switch that to a
+new-style "embedded in the state struct" creation, because in the
+next commit we're going to want to refer to the object again further
+down in the exynos4210_realize() function.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-4-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  2 ++
+ hw/arm/exynos4210.c         | 11 ++++++-----
+files changed, 8 insertions(+), 5 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/or-irq.h"
+ #include "hw/sysbus.h"
++#include "hw/cpu/a9mpcore.h"
+ #include "target/arm/cpu-qom.h"
+ #include "qom/object.h"
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
+     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
+     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
+     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
++    A9MPPrivState a9mpcore;
+ };
+ #define TYPE_EXYNOS4210_SOC "exynos4210"
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     }
+     /* Private memory region and Internal GIC */
+-    dev = qdev_new(TYPE_A9MPCORE_PRIV);
+-    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
+-    busdev = SYS_BUS_DEVICE(dev);
+-    sysbus_realize_and_unref(busdev, &error_fatal);
++    qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
++    busdev = SYS_BUS_DEVICE(&s->a9mpcore);
++    sysbus_realize(busdev, &error_fatal);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
+     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
+         sysbus_connect_irq(busdev, n,
+                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
+     }
+     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
+-        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
++        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
+     }
+     /* Cache controller */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
+         g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
+         object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
+     }
++
++    object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
+ }
+ static void exynos4210_class_init(ObjectClass *klass, void *data)
+--
+.25.1

-New patch
+[PULL 11/31] hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct
+The only time we use the int_gic_irq[] array in the Exynos4210Irq
+struct is in the exynos4210_realize() function: we initialize it with
+the GPIO inputs of the a9mpcore device, and then a bit later on we
+connect those to the outputs of the internal combiner.  Now that the
+a9mpcore object is easily accessible as s->a9mpcore we can make the
+connection directly from one device to the other without going via
+this array.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-5-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h | 1 -
+ hw/arm/exynos4210.c         | 6 ++----
+files changed, 2 insertions(+), 5 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ typedef struct Exynos4210Irq {
+     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
+-    qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
+     qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
+     qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+ } Exynos4210Irq;
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+         sysbus_connect_irq(busdev, n,
+                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
+     }
+-    for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
+-        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
+-    }
+     /* Cache controller */
+     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     busdev = SYS_BUS_DEVICE(dev);
+     sysbus_realize_and_unref(busdev, &error_fatal);
+     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+-        sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
++        sysbus_connect_irq(busdev, n,
++                           qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
+     }
+     exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
+--
+.25.1

-New patch
+[PULL 12/31] hw/arm/exynos4210: Coalesce board_irqs and irq_table
+The exynos4210 code currently has two very similar arrays of IRQs:
+ * board_irqs is a field of the Exynos4210Irq struct which is filled
+   in by exynos4210_init_board_irqs() with the appropriate qemu_irqs
+   for each IRQ the board/SoC can assert
+ * irq_table is a set of qemu_irqs pointed to from the
+   Exynos4210State struct.  It's allocated in exynos4210_init_irq,
+   and the only behaviour these irqs have is that they pass on the
+   level to the equivalent board_irqs[] irq
+The extra indirection through irq_table is unnecessary, so coalesce
+these into a single irq_table[] array as a direct field in
+Exynos4210State which exynos4210_init_board_irqs() fills in.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-6-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  8 ++------
+ hw/arm/exynos4210.c         |  6 +-----
+ hw/intc/exynos4210_gic.c    | 32 ++++++++------------------------
+files changed, 11 insertions(+), 35 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
+     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
+     qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
+-    qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+ } Exynos4210Irq;
+ struct Exynos4210State {
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
+     /*< public >*/
+     ARMCPU *cpu[EXYNOS4210_NCPUS];
+     Exynos4210Irq irqs;
+-    qemu_irq *irq_table;
++    qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     MemoryRegion chipid_mem;
+     MemoryRegion iram_mem;
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
+ void exynos4210_write_secondary(ARMCPU *cpu,
+         const struct arm_boot_info *info);
+-/* Initialize exynos4210 IRQ subsystem stub */
+-qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
+-
+ /* Initialize board IRQs.
+  * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
+-void exynos4210_init_board_irqs(Exynos4210Irq *s);
++void exynos4210_init_board_irqs(Exynos4210State *s);
+ /* Get IRQ number from exynos4210 IRQ subsystem stub.
+  * To identify IRQ source use internal combiner group and bit number
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
+     }
+-    /*** IRQs ***/
+-
+-    s->irq_table = exynos4210_init_irq(&s->irqs);
+-
+     /* IRQ Gate */
+     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
+         DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
+     /* Initialize board IRQs. */
+-    exynos4210_init_board_irqs(&s->irqs);
++    exynos4210_init_board_irqs(s);
+     /*** Memory ***/
+diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_gic.c
++++ b/hw/intc/exynos4210_gic.c
+@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+ #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
+ #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
+-static void exynos4210_irq_handler(void *opaque, int irq, int level)
+-{
+-    Exynos4210Irq *s = (Exynos4210Irq *)opaque;
+-
+-    /* Bypass */
+-    qemu_set_irq(s->board_irqs[irq], level);
+-}
+-
+-/*
+- * Initialize exynos4210 IRQ subsystem stub.
+- */
+-qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
+-{
+-    return qemu_allocate_irqs(exynos4210_irq_handler, s,
+-            EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
+-}
+-
+ /*
+  * Initialize board IRQs.
+  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
+  */
+-void exynos4210_init_board_irqs(Exynos4210Irq *s)
++void exynos4210_init_board_irqs(Exynos4210State *s)
+ {
+     uint32_t grp, bit, irq_id, n;
++    Exynos4210Irq *is = &s->irqs;
+     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+         irq_id = 0;
+@@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
+             irq_id = EXT_GIC_ID_MCT_G1;
+         }
+         if (irq_id) {
+-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
+-                    s->ext_gic_irq[irq_id-32]);
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_gic_irq[irq_id - 32]);
+         } else {
+-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
+-                    s->ext_combiner_irq[n]);
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_combiner_irq[n]);
+         }
+     }
+     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
+@@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
+                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
+         if (irq_id) {
+-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
+-                    s->ext_gic_irq[irq_id-32]);
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_gic_irq[irq_id - 32]);
+         }
+     }
+ }
+--
+.25.1

-New patch
+[PULL 13/31] hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
+Fix a missing set of spaces around '-' in the definition of
+combiner_grp_to_gic_id[]. We're about to move this code, so
+fix the style issue first to keep checkpatch happy with the
+code-motion patch.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-7-peter.maydell@linaro.org
+---
+ hw/intc/exynos4210_gic.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_gic.c
++++ b/hw/intc/exynos4210_gic.c
+@@ -XXX,XX +XXX,XX @@ enum ExtInt {
+  */
+ static const uint32_t
+-combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
++combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+     /* int combiner groups 16-19 */
+     { }, { }, { }, { },
+     /* int combiner group 20 */
+--
+.25.1

-New patch
+[PULL 14/31] hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
+The function exynos4210_init_board_irqs() currently lives in
+exynos4210_gic.c, but it isn't really part of the exynos4210.gic
+device -- it is a function that implements (some of) the wiring up of
+interrupts between the SoC's GIC and combiner components.  This means
+it fits better in exynos4210.c, which is the SoC-level code.  Move it
+there. Similarly, exynos4210_git_irq() is used almost only in the
+SoC-level code, so move it too.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-8-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |   4 -
+ hw/arm/exynos4210.c         | 202 +++++++++++++++++++++++++++++++++++
+ hw/intc/exynos4210_gic.c    | 204 ------------------------------------
+files changed, 202 insertions(+), 208 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
+ void exynos4210_write_secondary(ARMCPU *cpu,
+         const struct arm_boot_info *info);
+-/* Initialize board IRQs.
+- * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
+-void exynos4210_init_board_irqs(Exynos4210State *s);
+-
+ /* Get IRQ number from exynos4210 IRQ subsystem stub.
+  * To identify IRQ source use internal combiner group and bit number
+  *  grp - group number
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@
+ #define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
+ #define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
++enum ExtGicId {
++    EXT_GIC_ID_MDMA_LCD0 = 66,
++    EXT_GIC_ID_PDMA0,
++    EXT_GIC_ID_PDMA1,
++    EXT_GIC_ID_TIMER0,
++    EXT_GIC_ID_TIMER1,
++    EXT_GIC_ID_TIMER2,
++    EXT_GIC_ID_TIMER3,
++    EXT_GIC_ID_TIMER4,
++    EXT_GIC_ID_MCT_L0,
++    EXT_GIC_ID_WDT,
++    EXT_GIC_ID_RTC_ALARM,
++    EXT_GIC_ID_RTC_TIC,
++    EXT_GIC_ID_GPIO_XB,
++    EXT_GIC_ID_GPIO_XA,
++    EXT_GIC_ID_MCT_L1,
++    EXT_GIC_ID_IEM_APC,
++    EXT_GIC_ID_IEM_IEC,
++    EXT_GIC_ID_NFC,
++    EXT_GIC_ID_UART0,
++    EXT_GIC_ID_UART1,
++    EXT_GIC_ID_UART2,
++    EXT_GIC_ID_UART3,
++    EXT_GIC_ID_UART4,
++    EXT_GIC_ID_MCT_G0,
++    EXT_GIC_ID_I2C0,
++    EXT_GIC_ID_I2C1,
++    EXT_GIC_ID_I2C2,
++    EXT_GIC_ID_I2C3,
++    EXT_GIC_ID_I2C4,
++    EXT_GIC_ID_I2C5,
++    EXT_GIC_ID_I2C6,
++    EXT_GIC_ID_I2C7,
++    EXT_GIC_ID_SPI0,
++    EXT_GIC_ID_SPI1,
++    EXT_GIC_ID_SPI2,
++    EXT_GIC_ID_MCT_G1,
++    EXT_GIC_ID_USB_HOST,
++    EXT_GIC_ID_USB_DEVICE,
++    EXT_GIC_ID_MODEMIF,
++    EXT_GIC_ID_HSMMC0,
++    EXT_GIC_ID_HSMMC1,
++    EXT_GIC_ID_HSMMC2,
++    EXT_GIC_ID_HSMMC3,
++    EXT_GIC_ID_SDMMC,
++    EXT_GIC_ID_MIPI_CSI_4LANE,
++    EXT_GIC_ID_MIPI_DSI_4LANE,
++    EXT_GIC_ID_MIPI_CSI_2LANE,
++    EXT_GIC_ID_MIPI_DSI_2LANE,
++    EXT_GIC_ID_ONENAND_AUDI,
++    EXT_GIC_ID_ROTATOR,
++    EXT_GIC_ID_FIMC0,
++    EXT_GIC_ID_FIMC1,
++    EXT_GIC_ID_FIMC2,
++    EXT_GIC_ID_FIMC3,
++    EXT_GIC_ID_JPEG,
++    EXT_GIC_ID_2D,
++    EXT_GIC_ID_PCIe,
++    EXT_GIC_ID_MIXER,
++    EXT_GIC_ID_HDMI,
++    EXT_GIC_ID_HDMI_I2C,
++    EXT_GIC_ID_MFC,
++    EXT_GIC_ID_TVENC,
++};
++
++enum ExtInt {
++    EXT_GIC_ID_EXTINT0 = 48,
++    EXT_GIC_ID_EXTINT1,
++    EXT_GIC_ID_EXTINT2,
++    EXT_GIC_ID_EXTINT3,
++    EXT_GIC_ID_EXTINT4,
++    EXT_GIC_ID_EXTINT5,
++    EXT_GIC_ID_EXTINT6,
++    EXT_GIC_ID_EXTINT7,
++    EXT_GIC_ID_EXTINT8,
++    EXT_GIC_ID_EXTINT9,
++    EXT_GIC_ID_EXTINT10,
++    EXT_GIC_ID_EXTINT11,
++    EXT_GIC_ID_EXTINT12,
++    EXT_GIC_ID_EXTINT13,
++    EXT_GIC_ID_EXTINT14,
++    EXT_GIC_ID_EXTINT15
++};
++
++/*
++ * External GIC sources which are not from External Interrupt Combiner or
++ * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
++ * which is INTG16 in Internal Interrupt Combiner.
++ */
++
++static const uint32_t
++combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
++    /* int combiner groups 16-19 */
++    { }, { }, { }, { },
++    /* int combiner group 20 */
++    { 0, EXT_GIC_ID_MDMA_LCD0 },
++    /* int combiner group 21 */
++    { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
++    /* int combiner group 22 */
++    { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
++            EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
++    /* int combiner group 23 */
++    { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
++    /* int combiner group 24 */
++    { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
++    /* int combiner group 25 */
++    { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
++    /* int combiner group 26 */
++    { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
++            EXT_GIC_ID_UART4 },
++    /* int combiner group 27 */
++    { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
++            EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
++            EXT_GIC_ID_I2C7 },
++    /* int combiner group 28 */
++    { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
++    /* int combiner group 29 */
++    { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
++     EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
++    /* int combiner group 30 */
++    { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
++    /* int combiner group 31 */
++    { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
++    /* int combiner group 32 */
++    { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
++    /* int combiner group 33 */
++    { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
++    /* int combiner group 34 */
++    { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
++    /* int combiner group 35 */
++    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    /* int combiner group 36 */
++    { EXT_GIC_ID_MIXER },
++    /* int combiner group 37 */
++    { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
++     EXT_GIC_ID_EXTINT7 },
++    /* groups 38-50 */
++    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
++    /* int combiner group 51 */
++    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    /* group 52 */
++    { },
++    /* int combiner group 53 */
++    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    /* groups 54-63 */
++    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
++};
++
++/*
++ * Initialize board IRQs.
++ * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
++ */
++static void exynos4210_init_board_irqs(Exynos4210State *s)
++{
++    uint32_t grp, bit, irq_id, n;
++    Exynos4210Irq *is = &s->irqs;
++
++    for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
++        irq_id = 0;
++        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
++                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
++            /* MCT_G0 is passed to External GIC */
++            irq_id = EXT_GIC_ID_MCT_G0;
++        }
++        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
++                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
++            /* MCT_G1 is passed to External and GIC */
++            irq_id = EXT_GIC_ID_MCT_G1;
++        }
++        if (irq_id) {
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_gic_irq[irq_id - 32]);
++        } else {
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_combiner_irq[n]);
++        }
++    }
++    for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
++        /* these IDs are passed to Internal Combiner and External GIC */
++        grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
++        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
++        irq_id = combiner_grp_to_gic_id[grp -
++                     EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
++
++        if (irq_id) {
++            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
++                    is->ext_gic_irq[irq_id - 32]);
++        }
++    }
++}
++
++/*
++ * Get IRQ number from exynos4210 IRQ subsystem stub.
++ * To identify IRQ source use internal combiner group and bit number
++ *  grp - group number
++ *  bit - bit number inside group
++ */
++uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
++{
++    return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
++}
++
+ static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
+x09, 0x00, 0x00, 0x00 };
+diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_gic.c
++++ b/hw/intc/exynos4210_gic.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/arm/exynos4210.h"
+ #include "qom/object.h"
+-enum ExtGicId {
+-    EXT_GIC_ID_MDMA_LCD0 = 66,
+-    EXT_GIC_ID_PDMA0,
+-    EXT_GIC_ID_PDMA1,
+-    EXT_GIC_ID_TIMER0,
+-    EXT_GIC_ID_TIMER1,
+-    EXT_GIC_ID_TIMER2,
+-    EXT_GIC_ID_TIMER3,
+-    EXT_GIC_ID_TIMER4,
+-    EXT_GIC_ID_MCT_L0,
+-    EXT_GIC_ID_WDT,
+-    EXT_GIC_ID_RTC_ALARM,
+-    EXT_GIC_ID_RTC_TIC,
+-    EXT_GIC_ID_GPIO_XB,
+-    EXT_GIC_ID_GPIO_XA,
+-    EXT_GIC_ID_MCT_L1,
+-    EXT_GIC_ID_IEM_APC,
+-    EXT_GIC_ID_IEM_IEC,
+-    EXT_GIC_ID_NFC,
+-    EXT_GIC_ID_UART0,
+-    EXT_GIC_ID_UART1,
+-    EXT_GIC_ID_UART2,
+-    EXT_GIC_ID_UART3,
+-    EXT_GIC_ID_UART4,
+-    EXT_GIC_ID_MCT_G0,
+-    EXT_GIC_ID_I2C0,
+-    EXT_GIC_ID_I2C1,
+-    EXT_GIC_ID_I2C2,
+-    EXT_GIC_ID_I2C3,
+-    EXT_GIC_ID_I2C4,
+-    EXT_GIC_ID_I2C5,
+-    EXT_GIC_ID_I2C6,
+-    EXT_GIC_ID_I2C7,
+-    EXT_GIC_ID_SPI0,
+-    EXT_GIC_ID_SPI1,
+-    EXT_GIC_ID_SPI2,
+-    EXT_GIC_ID_MCT_G1,
+-    EXT_GIC_ID_USB_HOST,
+-    EXT_GIC_ID_USB_DEVICE,
+-    EXT_GIC_ID_MODEMIF,
+-    EXT_GIC_ID_HSMMC0,
+-    EXT_GIC_ID_HSMMC1,
+-    EXT_GIC_ID_HSMMC2,
+-    EXT_GIC_ID_HSMMC3,
+-    EXT_GIC_ID_SDMMC,
+-    EXT_GIC_ID_MIPI_CSI_4LANE,
+-    EXT_GIC_ID_MIPI_DSI_4LANE,
+-    EXT_GIC_ID_MIPI_CSI_2LANE,
+-    EXT_GIC_ID_MIPI_DSI_2LANE,
+-    EXT_GIC_ID_ONENAND_AUDI,
+-    EXT_GIC_ID_ROTATOR,
+-    EXT_GIC_ID_FIMC0,
+-    EXT_GIC_ID_FIMC1,
+-    EXT_GIC_ID_FIMC2,
+-    EXT_GIC_ID_FIMC3,
+-    EXT_GIC_ID_JPEG,
+-    EXT_GIC_ID_2D,
+-    EXT_GIC_ID_PCIe,
+-    EXT_GIC_ID_MIXER,
+-    EXT_GIC_ID_HDMI,
+-    EXT_GIC_ID_HDMI_I2C,
+-    EXT_GIC_ID_MFC,
+-    EXT_GIC_ID_TVENC,
+-};
+-
+-enum ExtInt {
+-    EXT_GIC_ID_EXTINT0 = 48,
+-    EXT_GIC_ID_EXTINT1,
+-    EXT_GIC_ID_EXTINT2,
+-    EXT_GIC_ID_EXTINT3,
+-    EXT_GIC_ID_EXTINT4,
+-    EXT_GIC_ID_EXTINT5,
+-    EXT_GIC_ID_EXTINT6,
+-    EXT_GIC_ID_EXTINT7,
+-    EXT_GIC_ID_EXTINT8,
+-    EXT_GIC_ID_EXTINT9,
+-    EXT_GIC_ID_EXTINT10,
+-    EXT_GIC_ID_EXTINT11,
+-    EXT_GIC_ID_EXTINT12,
+-    EXT_GIC_ID_EXTINT13,
+-    EXT_GIC_ID_EXTINT14,
+-    EXT_GIC_ID_EXTINT15
+-};
+-
+-/*
+- * External GIC sources which are not from External Interrupt Combiner or
+- * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
+- * which is INTG16 in Internal Interrupt Combiner.
+- */
+-
+-static const uint32_t
+-combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+-    /* int combiner groups 16-19 */
+-    { }, { }, { }, { },
+-    /* int combiner group 20 */
+-    { 0, EXT_GIC_ID_MDMA_LCD0 },
+-    /* int combiner group 21 */
+-    { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
+-    /* int combiner group 22 */
+-    { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
+-            EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
+-    /* int combiner group 23 */
+-    { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
+-    /* int combiner group 24 */
+-    { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
+-    /* int combiner group 25 */
+-    { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
+-    /* int combiner group 26 */
+-    { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
+-            EXT_GIC_ID_UART4 },
+-    /* int combiner group 27 */
+-    { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
+-            EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
+-            EXT_GIC_ID_I2C7 },
+-    /* int combiner group 28 */
+-    { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
+-    /* int combiner group 29 */
+-    { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
+-     EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
+-    /* int combiner group 30 */
+-    { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
+-    /* int combiner group 31 */
+-    { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
+-    /* int combiner group 32 */
+-    { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
+-    /* int combiner group 33 */
+-    { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
+-    /* int combiner group 34 */
+-    { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
+-    /* int combiner group 35 */
+-    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+-    /* int combiner group 36 */
+-    { EXT_GIC_ID_MIXER },
+-    /* int combiner group 37 */
+-    { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
+-     EXT_GIC_ID_EXTINT7 },
+-    /* groups 38-50 */
+-    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
+-    /* int combiner group 51 */
+-    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+-    /* group 52 */
+-    { },
+-    /* int combiner group 53 */
+-    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+-    /* groups 54-63 */
+-    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
+-};
+-
+ #define EXYNOS4210_GIC_NIRQ 160
+ #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE     0x10000
+@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+ #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
+ #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
+-/*
+- * Initialize board IRQs.
+- * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
+- */
+-void exynos4210_init_board_irqs(Exynos4210State *s)
+-{
+-    uint32_t grp, bit, irq_id, n;
+-    Exynos4210Irq *is = &s->irqs;
+-
+-    for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+-        irq_id = 0;
+-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
+-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
+-            /* MCT_G0 is passed to External GIC */
+-            irq_id = EXT_GIC_ID_MCT_G0;
+-        }
+-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
+-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
+-            /* MCT_G1 is passed to External and GIC */
+-            irq_id = EXT_GIC_ID_MCT_G1;
+-        }
+-        if (irq_id) {
+-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_gic_irq[irq_id - 32]);
+-        } else {
+-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_combiner_irq[n]);
+-        }
+-    }
+-    for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
+-        /* these IDs are passed to Internal Combiner and External GIC */
+-        grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
+-        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
+-        irq_id = combiner_grp_to_gic_id[grp -
+-                     EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
+-
+-        if (irq_id) {
+-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_gic_irq[irq_id - 32]);
+-        }
+-    }
+-}
+-
+-/*
+- * Get IRQ number from exynos4210 IRQ subsystem stub.
+- * To identify IRQ source use internal combiner group and bit number
+- *  grp - group number
+- *  bit - bit number inside group
+- */
+-uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
+-{
+-    return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
+-}
+-
+-/********* GIC part *********/
+-
+ #define TYPE_EXYNOS4210_GIC "exynos4210.gic"
+ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
+--
+.25.1

-New patch
+[PULL 15/31] hw/arm/exynos4210: Put external GIC into state struct
+Switch the creation of the external GIC to the new-style "embedded in
+state struct" approach, so we can easily refer to the object
+elsewhere during realize.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-9-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h      |  2 ++
+ include/hw/intc/exynos4210_gic.h | 43 ++++++++++++++++++++++++++++++++
+ hw/arm/exynos4210.c              | 10 ++++----
+ hw/intc/exynos4210_gic.c         | 17 ++-----------
+ MAINTAINERS                      |  2 +-
+files changed, 53 insertions(+), 21 deletions(-)
+ create mode 100644 include/hw/intc/exynos4210_gic.h
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/or-irq.h"
+ #include "hw/sysbus.h"
+ #include "hw/cpu/a9mpcore.h"
++#include "hw/intc/exynos4210_gic.h"
+ #include "target/arm/cpu-qom.h"
+ #include "qom/object.h"
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
+     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
+     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+     A9MPPrivState a9mpcore;
++    Exynos4210GicState ext_gic;
+ };
+ #define TYPE_EXYNOS4210_SOC "exynos4210"
+diff --git a/include/hw/intc/exynos4210_gic.h b/include/hw/intc/exynos4210_gic.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/intc/exynos4210_gic.h
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
++ *
++ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
++ * All rights reserved.
++ *
++ * Evgeny Voevodin <e.voevodin@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++#ifndef HW_INTC_EXYNOS4210_GIC_H
++#define HW_INTC_EXYNOS4210_GIC_H
++
++#include "hw/sysbus.h"
++
++#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
++OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
++
++#define EXYNOS4210_GIC_NCPUS 2
++
++struct Exynos4210GicState {
++    SysBusDevice parent_obj;
++
++    MemoryRegion cpu_container;
++    MemoryRegion dist_container;
++    MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS];
++    MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS];
++    uint32_t num_cpu;
++    DeviceState *gic;
++};
++
++#endif
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
+     /* External GIC */
+-    dev = qdev_new("exynos4210.gic");
+-    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
+-    busdev = SYS_BUS_DEVICE(dev);
+-    sysbus_realize_and_unref(busdev, &error_fatal);
++    qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
++    busdev = SYS_BUS_DEVICE(&s->ext_gic);
++    sysbus_realize(busdev, &error_fatal);
+     /* Map CPU interface */
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
+     /* Map Distributer interface */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
+     }
+     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
+-        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
++        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
+     }
+     /* Internal Interrupt Combiner */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
+     }
+     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
++    object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
+ }
+ static void exynos4210_class_init(ObjectClass *klass, void *data)
+diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_gic.c
++++ b/hw/intc/exynos4210_gic.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/module.h"
+ #include "hw/irq.h"
+ #include "hw/qdev-properties.h"
++#include "hw/intc/exynos4210_gic.h"
+ #include "hw/arm/exynos4210.h"
+ #include "qom/object.h"
+@@ -XXX,XX +XXX,XX @@
+ #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
+ #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
+-#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
+-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
+-
+-struct Exynos4210GicState {
+-    SysBusDevice parent_obj;
+-
+-    MemoryRegion cpu_container;
+-    MemoryRegion dist_container;
+-    MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
+-    MemoryRegion dist_alias[EXYNOS4210_NCPUS];
+-    uint32_t num_cpu;
+-    DeviceState *gic;
+-};
+-
+ static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
+ {
+     Exynos4210GicState *s = (Exynos4210GicState *)opaque;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp)
+      * enough room for the cpu numbers.  gcc 9.2.1 on 32-bit x86
+      * doesn't figure this out, otherwise and gives spurious warnings.
+      */
+-    assert(n <= EXYNOS4210_NCPUS);
++    assert(n <= EXYNOS4210_GIC_NCPUS);
+     for (i = 0; i < n; i++) {
+         /* Map CPU interface per SMP Core */
+         sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
+diff --git a/MAINTAINERS b/MAINTAINERS
+index XXXXXXX..XXXXXXX 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
+ L: qemu-arm@nongnu.org
+ S: Odd Fixes
+ F: hw/*/exynos*
+-F: include/hw/arm/exynos4210.h
++F: include/hw/*/exynos*
+ Calxeda Highbank
+ M: Rob Herring <robh@kernel.org>
+--
+.25.1

-New patch
+[PULL 16/31] hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
+The only time we use the ext_gic_irq[] array in the Exynos4210Irq
+struct is during realize of the SoC -- we initialize it with the
+input IRQs of the external GIC device, and then connect those to
+outputs of other devices further on in realize (including in the
+exynos4210_init_board_irqs() function).  Now that the ext_gic object
+is easily accessible as s->ext_gic we can make the connections
+directly from one device to the other without going via this array.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-10-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  1 -
+ hw/arm/exynos4210.c         | 12 ++++++------
+files changed, 6 insertions(+), 7 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ typedef struct Exynos4210Irq {
+     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
+-    qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
+ } Exynos4210Irq;
+ struct Exynos4210State {
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+ {
+     uint32_t grp, bit, irq_id, n;
+     Exynos4210Irq *is = &s->irqs;
++    DeviceState *extgicdev = DEVICE(&s->ext_gic);
+     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+         irq_id = 0;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+         }
+         if (irq_id) {
+             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_gic_irq[irq_id - 32]);
++                                             qdev_get_gpio_in(extgicdev,
++                                                              irq_id - 32));
+         } else {
+             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                     is->ext_combiner_irq[n]);
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+         if (irq_id) {
+             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_gic_irq[irq_id - 32]);
++                                             qdev_get_gpio_in(extgicdev,
++                                                              irq_id - 32));
+         }
+     }
+ }
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+         sysbus_connect_irq(busdev, n,
+                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
+     }
+-    for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
+-        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
+-    }
+     /* Internal Interrupt Combiner */
+     dev = qdev_new("exynos4210.combiner");
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     busdev = SYS_BUS_DEVICE(dev);
+     sysbus_realize_and_unref(busdev, &error_fatal);
+     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+-        sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
++        sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
+     }
+     exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
+--
+.25.1

-New patch
+[PULL 17/31] hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c
+The function exynos4210_combiner_get_gpioin() currently lives in
+exynos4210_combiner.c, but it isn't really part of the combiner
+device itself -- it is a function that implements the wiring up of
+some interrupt sources to multiple combiner inputs.  Move it to live
+with the other SoC-level code in exynos4210.c, along with a few
+macros previously defined in exynos4210.h which are now used only
+in exynos4210.c.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-11-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h   | 11 -----
+ hw/arm/exynos4210.c           | 82 +++++++++++++++++++++++++++++++++++
+ hw/intc/exynos4210_combiner.c | 77 --------------------------------
+files changed, 82 insertions(+), 88 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ   \
+     (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
+-#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit)  ((grp)*8 + (bit))
+-#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq)       ((irq) / 8)
+-#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
+-    ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
+-
+ /* IRQs number for external and internal GIC */
+ #define EXYNOS4210_EXT_GIC_NIRQ     (160-32)
+ #define EXYNOS4210_INT_GIC_NIRQ     64
+@@ -XXX,XX +XXX,XX @@ void exynos4210_write_secondary(ARMCPU *cpu,
+  *  bit - bit number inside group */
+ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
+-/*
+- * Get Combiner input GPIO into irqs structure
+- */
+-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
+-        int ext);
+-
+ /*
+  * exynos4210 UART
+  */
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
+ };
++#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit)  ((grp) * 8 + (bit))
++#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq)       ((irq) / 8)
++#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
++    ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
++
+ /*
+  * Initialize board IRQs.
+  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
+@@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
+     return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
+ }
++/*
++ * Get Combiner input GPIO into irqs structure
++ */
++static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
++                                           DeviceState *dev, int ext)
++{
++    int n;
++    int bit;
++    int max;
++    qemu_irq *irq;
++
++    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
++        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
++    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
++
++    /*
++     * Some IRQs of Int/External Combiner are going to two Combiners groups,
++     * so let split them.
++     */
++    for (n = 0; n < max; n++) {
++
++        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
++
++        switch (n) {
++        /* MDNIE_LCD1 INTG1 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
++            continue;
++
++        /* TMU INTG3 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
++            continue;
++
++        /* LCD1 INTG12 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
++            continue;
++
++        /* Multi-Core Timer INTG12 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
++               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
++            continue;
++
++        /* Multi-Core Timer INTG35 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
++            continue;
++
++        /* Multi-Core Timer INTG51 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
++            continue;
++
++        /* Multi-Core Timer INTG53 */
++        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
++             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
++            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
++                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
++            continue;
++        }
++
++        irq[n] = qdev_get_gpio_in(dev, n);
++    }
++}
++
+ static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
+x09, 0x00, 0x00, 0x00 };
+diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_combiner.c
++++ b/hw/intc/exynos4210_combiner.c
+@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_combiner = {
+     }
+ };
+-/*
+- * Get Combiner input GPIO into irqs structure
+- */
+-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
+-        int ext)
+-{
+-    int n;
+-    int bit;
+-    int max;
+-    qemu_irq *irq;
+-
+-    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
+-        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
+-    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
+-
+-    /*
+-     * Some IRQs of Int/External Combiner are going to two Combiners groups,
+-     * so let split them.
+-     */
+-    for (n = 0; n < max; n++) {
+-
+-        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
+-
+-        switch (n) {
+-        /* MDNIE_LCD1 INTG1 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
+-            continue;
+-
+-        /* TMU INTG3 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
+-            continue;
+-
+-        /* LCD1 INTG12 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
+-            continue;
+-
+-        /* Multi-Core Timer INTG12 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
+-               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+-            continue;
+-
+-        /* Multi-Core Timer INTG35 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+-            continue;
+-
+-        /* Multi-Core Timer INTG51 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+-            continue;
+-
+-        /* Multi-Core Timer INTG53 */
+-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
+-             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
+-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+-            continue;
+-        }
+-
+-        irq[n] = qdev_get_gpio_in(dev, n);
+-    }
+-}
+-
+ static uint64_t
+ exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
+ {
+--
+.25.1

-New patch
+[PULL 18/31] hw/arm/exynos4210: Delete unused macro definitions
+Delete a couple of #defines which are never used.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-12-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h | 4 ----
+file changed, 4 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ   \
+     (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
+-/* IRQs number for external and internal GIC */
+-#define EXYNOS4210_EXT_GIC_NIRQ     (160-32)
+-#define EXYNOS4210_INT_GIC_NIRQ     64
+-
+ #define EXYNOS4210_I2C_NUMBER               9
+ #define EXYNOS4210_NUM_DMA      3
+--
+.25.1

-New patch
+[PULL 19/31] hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
+In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device
+instead of qemu_irq_split().
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-13-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  9 ++++++++
+ hw/arm/exynos4210.c         | 41 +++++++++++++++++++++++++++++--------
+files changed, 42 insertions(+), 8 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "hw/cpu/a9mpcore.h"
+ #include "hw/intc/exynos4210_gic.h"
++#include "hw/core/split-irq.h"
+ #include "target/arm/cpu-qom.h"
+ #include "qom/object.h"
+@@ -XXX,XX +XXX,XX @@
+ #define EXYNOS4210_NUM_DMA      3
++/*
++ * We need one splitter for every external combiner input, plus
++ * one for every non-zero entry in combiner_grp_to_gic_id[].
++ * We'll assert in exynos4210_init_board_irqs() if this is wrong.
++ */
++#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
++
+ typedef struct Exynos4210Irq {
+     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
+     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+     A9MPPrivState a9mpcore;
+     Exynos4210GicState ext_gic;
++    SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
+ };
+ #define TYPE_EXYNOS4210_SOC "exynos4210"
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+     uint32_t grp, bit, irq_id, n;
+     Exynos4210Irq *is = &s->irqs;
+     DeviceState *extgicdev = DEVICE(&s->ext_gic);
++    int splitcount = 0;
++    DeviceState *splitter;
+     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+         irq_id = 0;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+             /* MCT_G1 is passed to External and GIC */
+             irq_id = EXT_GIC_ID_MCT_G1;
+         }
++
++        assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
++        splitter = DEVICE(&s->splitter[splitcount]);
++        qdev_prop_set_uint16(splitter, "num-lines", 2);
++        qdev_realize(splitter, NULL, &error_abort);
++        splitcount++;
++        s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
++        qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
+         if (irq_id) {
+-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                                             qdev_get_gpio_in(extgicdev,
+-                                                              irq_id - 32));
++            qdev_connect_gpio_out(splitter, 1,
++                                  qdev_get_gpio_in(extgicdev, irq_id - 32));
+         } else {
+-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                    is->ext_combiner_irq[n]);
++            qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
+         }
+     }
+     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
+         if (irq_id) {
+-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+-                                             qdev_get_gpio_in(extgicdev,
+-                                                              irq_id - 32));
++            assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
++            splitter = DEVICE(&s->splitter[splitcount]);
++            qdev_prop_set_uint16(splitter, "num-lines", 2);
++            qdev_realize(splitter, NULL, &error_abort);
++            splitcount++;
++            s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
++            qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
++            qdev_connect_gpio_out(splitter, 1,
++                                  qdev_get_gpio_in(extgicdev, irq_id - 32));
+         }
+     }
++    /*
++     * We check this here to avoid a more obscure assert later when
++     * qdev_assert_realized_properly() checks that we realized every
++     * child object we initialized.
++     */
++    assert(splitcount == EXYNOS4210_NUM_SPLITTERS);
+ }
+ /*
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
+         object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
+     }
++    for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
++        g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
++        object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ);
++    }
++
+     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
+     object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
+ }
+--
+.25.1

-[PULL 8/9] hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
+[PULL 20/31] hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines
-If we're booting a Linux kernel directly into Non-Secure
+In exynos4210_init_board_irqs(), the loop that handles IRQ lines that
-state on a CPU which has Secure state, then make sure we
+are in a range that applies to the internal combiner only creates a
-set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed
+splitter for those interrupts which go to both the internal combiner
-to access the FPU. Otherwise an AArch32 kernel will UNDEF as
+and to the external GIC, but it does nothing at all for the
-soon as it tries to use the FPU.
+interrupts which don't go to the external GIC, leaving the
 irq_table[] array element empty for those.  (This will result in
 those interrupts simply being lost, not in a QEMU crash.)
-It used to not matter that we didn't do this until commit
+I don't have a reliable datasheet for this SoC, but since we do wire
-fc1120a7f5f2d4b6, where we implemented actually honouring
+up one interrupt line in this category (the HDMI I2C device on
-these NSACR bits.
+interrupt 16,1), this seems like it must be a bug in the existing
 QEMU code.  Fill in the irq_table[] entries where we're not splitting
 the IRQ to both the internal combiner and the external GIC with the
 IRQ line of the internal combiner.  (That is, these IRQ lines go to
 just one device, not multiple.)
-The problem only exists for CPUs where EL3 is AArch32; the
+This bug didn't have any visible guest effects because the only
-equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to
+implemented device that was affected was the HDMI I2C controller,
-not trap, 1 to trap", so the reset value of the register
+and we never connect any I2C devices to that bus.
 permits NS access, unlike NSACR.
-Fixes: fc1120a7f5
-Fixes: https://bugs.launchpad.net/qemu/+bug/1844597
-Cc: qemu-stable@nongnu.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190920174039.3916-1-peter.maydell@linaro.org
+Message-id: 20220404154658.565020-14-peter.maydell@linaro.org
 ---
- hw/arm/boot.c | 2 ++
+ hw/arm/exynos4210.c | 2 ++
 file changed, 2 insertions(+)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/hw/arm/exynos4210.c
-+++ b/hw/arm/boot.c
++++ b/hw/arm/exynos4210.c
-@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
-                     (cs != first_cpu || !info->secure_board_setup)) {
+             qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
-                     /* Linux expects non-secure state */
+             qdev_connect_gpio_out(splitter, 1,
-                     env->cp15.scr_el3 |= SCR_NS;
+                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
-+                    /* Set NSACR.{CP11,CP10} so NS can access the FPU */
++        } else {
-+                    env->cp15.nsacr |= 3 << 10;
++            s->irq_table[n] = is->int_combiner_irq[n];
-                 }
+         }
-             }
+     }
+     /*
 --
-.20.1
+.25.1

-New patch
+[PULL 21/31] hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
+Currently for the interrupts MCT_G0 and MCT_G1 which are
+the only ones in the input range of the external combiner
+and which are also wired to the external GIC, we connect
+them only to the internal combiner and the external GIC.
+This seems likely to be a bug, as all other interrupts
+which are in the input range of both combiners are
+connected to both combiners. (The fact that the code in
+exynos4210_combiner_get_gpioin() is also trying to wire
+up these inputs on both combiners also suggests this.)
+Wire these interrupts up to both combiners, like the rest.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-15-peter.maydell@linaro.org
+---
+ hw/arm/exynos4210.c | 7 +++----
+file changed, 3 insertions(+), 4 deletions(-)
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+         assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
+         splitter = DEVICE(&s->splitter[splitcount]);
+-        qdev_prop_set_uint16(splitter, "num-lines", 2);
++        qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2);
+         qdev_realize(splitter, NULL, &error_abort);
+         splitcount++;
+         s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
+         qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
++        qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
+         if (irq_id) {
+-            qdev_connect_gpio_out(splitter, 1,
++            qdev_connect_gpio_out(splitter, 2,
+                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
+-        } else {
+-            qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
+         }
+     }
+     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
+--
+.25.1

-New patch
+[PULL 22/31] hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
+The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0
+and EXT_GIC_ID_MCT_G1 multiple times. This means that we will
+connect multiple IRQs up to the same external GIC input, which
+is not permitted. We do the same thing in the code in
+exynos4210_init_board_irqs() because the conditionals selecting
+an irq_id in the first loop match multiple interrupt IDs.
+Overall we do this for interrupt IDs
+(1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0
+and
+(1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1
+These correspond to the cases for the multi-core timer that we are
+wiring up to multiple inputs on the combiner in
+exynos4210_combiner_get_gpioin().  That code already deals with all
+these interrupt IDs being the same input source, so we don't need to
+connect the external GIC interrupt for any of them except the first
+(1, 4) and (1, 5). Remove the array entries and conditionals which
+were incorrectly causing us to wire up extra lines.
+This bug didn't cause any visible effects, because we only connect
+up a device to the "primary" ID values (1, 4) and (1, 5), so the
+extra lines would never be set to a level.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-16-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  2 +-
+ hw/arm/exynos4210.c         | 12 +++++-------
+files changed, 6 insertions(+), 8 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+  * one for every non-zero entry in combiner_grp_to_gic_id[].
+  * We'll assert in exynos4210_init_board_irqs() if this is wrong.
+  */
+-#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
++#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
+ typedef struct Exynos4210Irq {
+     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+     /* int combiner group 34 */
+     { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
+     /* int combiner group 35 */
+-    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    { 0, 0, 0, EXT_GIC_ID_MCT_L1 },
+     /* int combiner group 36 */
+     { EXT_GIC_ID_MIXER },
+     /* int combiner group 37 */
+@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+     /* groups 38-50 */
+     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
+     /* int combiner group 51 */
+-    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    { EXT_GIC_ID_MCT_L0 },
+     /* group 52 */
+     { },
+     /* int combiner group 53 */
+-    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
++    { EXT_GIC_ID_WDT },
+     /* groups 54-63 */
+     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
+ };
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+         irq_id = 0;
+-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
+-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
++        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) {
+             /* MCT_G0 is passed to External GIC */
+             irq_id = EXT_GIC_ID_MCT_G0;
+         }
+-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
+-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
++        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) {
+             /* MCT_G1 is passed to External and GIC */
+             irq_id = EXT_GIC_ID_MCT_G1;
+         }
+--
+.25.1

-New patch
+[PULL 23/31] hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
+At this point, the function exynos4210_init_board_irqs() splits input
 IRQ lines to connect them to the input combiner, output combiner and
 external GIC.  The function exynos4210_combiner_get_gpioin() splits
 some of the combiner input lines further to connect them to multiple
 different inputs on the combiner.
 Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a
 configurable number of outputs, we can do all this in one place, by
 making exynos4210_init_board_irqs() add extra outputs to the splitter
 device when it must be connected to more than one input on each
 combiner.
 We do this with a new data structure, the combinermap, which is an
 array each of whose elements is a list of the interrupt IDs on the
 combiner which must be tied together.  As we loop through each
 interrupt ID, if we find that it is the first one in one of these
 lists, we configure the splitter device with eonugh extra outputs and
 wire them up to the other interrupt IDs in the list.
 Conveniently, for all the cases where this is necessary, the
 lowest-numbered interrupt ID in each group is in the range of the
 external combiner, so we only need to code for this in the first of
 the two loops in exynos4210_init_board_irqs().
 The old code in exynos4210_combiner_get_gpioin() which is being
 deleted here had several problems which don't exist in the new code
 in its handling of the multi-core timer interrupts:
  (1) the case labels specified bits 4 ... 8, but bit '8' doesn't
      exist; these should have been 4 ... 7
  (2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]
      multiple times as the input of several different splitters,
      which isn't allowed
  (3) in an apparent cut-and-paste error, the cases for all the
      multi-core timer inputs used "bit + 4" even though the
      bit range for the case was (intended to be) 4 ... 7, which
      meant it was looking at non-existent bits 8 ... 11.
 None of these exist in the new code.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20220404154658.565020-17-peter.maydell@linaro.org
 ---
  include/hw/arm/exynos4210.h |   6 +-
  hw/arm/exynos4210.c         | 178 +++++++++++++++++++++++-------------
 files changed, 119 insertions(+), 65 deletions(-)
 diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/exynos4210.h
 +++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
  /*
   * We need one splitter for every external combiner input, plus
 - * one for every non-zero entry in combiner_grp_to_gic_id[].
 + * one for every non-zero entry in combiner_grp_to_gic_id[],
 + * minus one for every external combiner ID in second or later
 + * places in a combinermap[] line.
   * We'll assert in exynos4210_init_board_irqs() if this is wrong.
   */
 -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
 +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
  typedef struct Exynos4210Irq {
      qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/exynos4210.c
 +++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
  #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
      ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
 +/*
 + * Some interrupt lines go to multiple combiner inputs.
 + * This data structure defines those: each array element is
 + * a list of combiner inputs which are connected together;
 + * the one with the smallest interrupt ID value must be first.
 + * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being
 + * wired to anything so we can use 0 as a terminator.
 + */
 +#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B)
 +#define IRQNONE 0
 +
 +#define COMBINERMAP_SIZE 16
 +
 +static const int combinermap[COMBINERMAP_SIZE][6] = {
 +    /* MDNIE_LCD1 */
 +    { IRQNO(0, 4), IRQNO(1, 0), IRQNONE },
 +    { IRQNO(0, 5), IRQNO(1, 1), IRQNONE },
 +    { IRQNO(0, 6), IRQNO(1, 2), IRQNONE },
 +    { IRQNO(0, 7), IRQNO(1, 3), IRQNONE },
 +    /* TMU */
 +    { IRQNO(2, 4), IRQNO(3, 4), IRQNONE },
 +    { IRQNO(2, 5), IRQNO(3, 5), IRQNONE },
 +    { IRQNO(2, 6), IRQNO(3, 6), IRQNONE },
 +    { IRQNO(2, 7), IRQNO(3, 7), IRQNONE },
 +    /* LCD1 */
 +    { IRQNO(11, 4), IRQNO(12, 0), IRQNONE },
 +    { IRQNO(11, 5), IRQNO(12, 1), IRQNONE },
 +    { IRQNO(11, 6), IRQNO(12, 2), IRQNONE },
 +    { IRQNO(11, 7), IRQNO(12, 3), IRQNONE },
 +    /* Multi-core timer */
 +    { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE },
 +    { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE },
 +    { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE },
 +    { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE },
 +};
 +
 +#undef IRQNO
 +
 +static const int *combinermap_entry(int irq)
 +{
 +    /*
 +     * If the interrupt number passed in is the first entry in some
 +     * line of the combinermap, return a pointer to that line;
 +     * otherwise return NULL.
 +     */
 +    int i;
 +    for (i = 0; i < COMBINERMAP_SIZE; i++) {
 +        if (combinermap[i][0] == irq) {
 +            return combinermap[i];
 +        }
 +    }
 +    return NULL;
 +}
 +
 +static int mapline_size(const int *mapline)
 +{
 +    /* Return number of entries in this mapline in total */
 +    int i = 0;
 +
 +    if (!mapline) {
 +        /* Not in the map? IRQ goes to exactly one combiner input */
 +        return 1;
 +    }
 +    while (*mapline != IRQNONE) {
 +        mapline++;
 +        i++;
 +    }
 +    return i;
 +}
 +
  /*
   * Initialize board IRQs.
   * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
      DeviceState *extgicdev = DEVICE(&s->ext_gic);
      int splitcount = 0;
      DeviceState *splitter;
 +    const int *mapline;
 +    int numlines, splitin, in;
      for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
          irq_id = 0;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
              irq_id = EXT_GIC_ID_MCT_G1;
          }
 +        if (s->irq_table[n]) {
 +            /*
 +             * This must be some non-first entry in a combinermap line,
 +             * and we've already filled it in.
 +             */
 +            continue;
 +        }
 +        mapline = combinermap_entry(n);
 +        /*
 +         * We need to connect the IRQ to multiple inputs on both combiners
 +         * and possibly also to the external GIC.
 +         */
 +        numlines = 2 * mapline_size(mapline);
 +        if (irq_id) {
 +            numlines++;
 +        }
          assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
          splitter = DEVICE(&s->splitter[splitcount]);
 -        qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2);
 +        qdev_prop_set_uint16(splitter, "num-lines", numlines);
          qdev_realize(splitter, NULL, &error_abort);
          splitcount++;
 -        s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
 -        qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
 -        qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
 +
 +        in = n;
 +        splitin = 0;
 +        for (;;) {
 +            s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
 +            qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]);
 +            qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]);
 +            splitin += 2;
 +            if (!mapline) {
 +                break;
 +            }
 +            mapline++;
 +            in = *mapline;
 +            if (in == IRQNONE) {
 +                break;
 +            }
 +        }
          if (irq_id) {
 -            qdev_connect_gpio_out(splitter, 2,
 +            qdev_connect_gpio_out(splitter, splitin,
                                    qdev_get_gpio_in(extgicdev, irq_id - 32));
          }
      }
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
          irq_id = combiner_grp_to_gic_id[grp -
                       EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
 +        if (s->irq_table[n]) {
 +            /*
 +             * This must be some non-first entry in a combinermap line,
 +             * and we've already filled it in.
 +             */
 +            continue;
 +        }
 +
          if (irq_id) {
              assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
              splitter = DEVICE(&s->splitter[splitcount]);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
                                             DeviceState *dev, int ext)
  {
      int n;
 -    int bit;
      int max;
      qemu_irq *irq;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
          EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
      irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
 -    /*
 -     * Some IRQs of Int/External Combiner are going to two Combiners groups,
 -     * so let split them.
 -     */
      for (n = 0; n < max; n++) {
 -
 -        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
 -
 -        switch (n) {
 -        /* MDNIE_LCD1 INTG1 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
 -            continue;
 -
 -        /* TMU INTG3 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
 -            continue;
 -
 -        /* LCD1 INTG12 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
 -            continue;
 -
 -        /* Multi-Core Timer INTG12 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
 -               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 -            continue;
 -
 -        /* Multi-Core Timer INTG35 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 -            continue;
 -
 -        /* Multi-Core Timer INTG51 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 -            continue;
 -
 -        /* Multi-Core Timer INTG53 */
 -        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
 -             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
 -            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
 -                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
 -            continue;
 -        }
 -
          irq[n] = qdev_get_gpio_in(dev, n);
      }
  }
 --
 .25.1

-New patch
+[PULL 24/31] hw/arm/exynos4210: Put combiners into state struct
+Switch the creation of the combiner devices to the new-style
+"embedded in state struct" approach, so we can easily refer
+to the object elsewhere during realize.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-18-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h           |  3 ++
+ include/hw/intc/exynos4210_combiner.h | 57 +++++++++++++++++++++++++++
+ hw/arm/exynos4210.c                   | 20 +++++-----
+ hw/intc/exynos4210_combiner.c         | 31 +--------------
+files changed, 72 insertions(+), 39 deletions(-)
+ create mode 100644 include/hw/intc/exynos4210_combiner.h
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "hw/cpu/a9mpcore.h"
+ #include "hw/intc/exynos4210_gic.h"
++#include "hw/intc/exynos4210_combiner.h"
+ #include "hw/core/split-irq.h"
+ #include "target/arm/cpu-qom.h"
+ #include "qom/object.h"
+@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
+     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+     A9MPPrivState a9mpcore;
+     Exynos4210GicState ext_gic;
++    Exynos4210CombinerState int_combiner;
++    Exynos4210CombinerState ext_combiner;
+     SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
+ };
+diff --git a/include/hw/intc/exynos4210_combiner.h b/include/hw/intc/exynos4210_combiner.h
+new file mode 100644
+index XXXXXXX..XXXXXXX
+--- /dev/null
++++ b/include/hw/intc/exynos4210_combiner.h
+@@ -XXX,XX +XXX,XX @@
++/*
++ * Samsung exynos4210 Interrupt Combiner
++ *
++ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
++ * All rights reserved.
++ *
++ * Evgeny Voevodin <e.voevodin@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
++ * See the GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef HW_INTC_EXYNOS4210_COMBINER
++#define HW_INTC_EXYNOS4210_COMBINER
++
++#include "hw/sysbus.h"
++
++/*
++ * State for each output signal of internal combiner
++ */
++typedef struct CombinerGroupState {
++    uint8_t src_mask;            /* 1 - source enabled, 0 - disabled */
++    uint8_t src_pending;        /* Pending source interrupts before masking */
++} CombinerGroupState;
++
++#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
++OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
++
++/* Number of groups and total number of interrupts for the internal combiner */
++#define IIC_NGRP 64
++#define IIC_NIRQ (IIC_NGRP * 8)
++#define IIC_REGSET_SIZE 0x41
++
++struct Exynos4210CombinerState {
++    SysBusDevice parent_obj;
++
++    MemoryRegion iomem;
++
++    struct CombinerGroupState group[IIC_NGRP];
++    uint32_t reg_set[IIC_REGSET_SIZE];
++    uint32_t icipsr[2];
++    uint32_t external;          /* 1 means that this combiner is external */
++
++    qemu_irq output_irq[IIC_NGRP];
++};
++
++#endif
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     }
+     /* Internal Interrupt Combiner */
+-    dev = qdev_new("exynos4210.combiner");
+-    busdev = SYS_BUS_DEVICE(dev);
+-    sysbus_realize_and_unref(busdev, &error_fatal);
++    busdev = SYS_BUS_DEVICE(&s->int_combiner);
++    sysbus_realize(busdev, &error_fatal);
+     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+         sysbus_connect_irq(busdev, n,
+                            qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
+     }
+-    exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
++    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
+     /* External Interrupt Combiner */
+-    dev = qdev_new("exynos4210.combiner");
+-    qdev_prop_set_uint32(dev, "external", 1);
+-    busdev = SYS_BUS_DEVICE(dev);
+-    sysbus_realize_and_unref(busdev, &error_fatal);
++    qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1);
++    busdev = SYS_BUS_DEVICE(&s->ext_combiner);
++    sysbus_realize(busdev, &error_fatal);
+     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
+     }
+-    exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
++    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
+     /* Initialize board IRQs. */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
+     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
+     object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
++    object_initialize_child(obj, "int-combiner", &s->int_combiner,
++                            TYPE_EXYNOS4210_COMBINER);
++    object_initialize_child(obj, "ext-combiner", &s->ext_combiner,
++                            TYPE_EXYNOS4210_COMBINER);
+ }
+ static void exynos4210_class_init(ObjectClass *klass, void *data)
+diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/intc/exynos4210_combiner.c
++++ b/hw/intc/exynos4210_combiner.c
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
+ #include "migration/vmstate.h"
+ #include "qemu/module.h"
+-
++#include "hw/intc/exynos4210_combiner.h"
+ #include "hw/arm/exynos4210.h"
+ #include "hw/hw.h"
+ #include "hw/irq.h"
+@@ -XXX,XX +XXX,XX @@
+ #define DPRINTF(fmt, ...) do {} while (0)
+ #endif
+-#define    IIC_NGRP        64            /* Internal Interrupt Combiner
+-                                            Groups number */
+-#define    IIC_NIRQ        (IIC_NGRP * 8)/* Internal Interrupt Combiner
+-                                            Interrupts number */
+ #define IIC_REGION_SIZE    0x108         /* Size of memory mapped region */
+-#define IIC_REGSET_SIZE    0x41
+-
+-/*
+- * State for each output signal of internal combiner
+- */
+-typedef struct CombinerGroupState {
+-    uint8_t src_mask;            /* 1 - source enabled, 0 - disabled */
+-    uint8_t src_pending;        /* Pending source interrupts before masking */
+-} CombinerGroupState;
+-
+-#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
+-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
+-
+-struct Exynos4210CombinerState {
+-    SysBusDevice parent_obj;
+-
+-    MemoryRegion iomem;
+-
+-    struct CombinerGroupState group[IIC_NGRP];
+-    uint32_t reg_set[IIC_REGSET_SIZE];
+-    uint32_t icipsr[2];
+-    uint32_t external;          /* 1 means that this combiner is external */
+-
+-    qemu_irq output_irq[IIC_NGRP];
+-};
+ static const VMStateDescription vmstate_exynos4210_combiner_group_state = {
+     .name = "exynos4210.combiner.groupstate",
+--
+.25.1

-New patch
+[PULL 25/31] hw/arm/exynos4210: Drop Exynos4210Irq struct
+The only time we use the int_combiner_irq[] and ext_combiner_irq[]
+arrays in the Exynos4210Irq struct is during realize of the SoC -- we
+initialize them with the input IRQs of the combiner devices, and then
+connect those to outputs of other devices in
+exynos4210_init_board_irqs().  Now that the combiner objects are
+easily accessible as s->int_combiner and s->ext_combiner we can make
+the connections directly from one device to the other without going
+via these arrays.
+Since these are the only two remaining elements of Exynos4210Irq,
+we can remove that struct entirely.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220404154658.565020-19-peter.maydell@linaro.org
+---
+ include/hw/arm/exynos4210.h |  6 ------
+ hw/arm/exynos4210.c         | 34 ++++++++--------------------------
+files changed, 8 insertions(+), 32 deletions(-)
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/exynos4210.h
++++ b/include/hw/arm/exynos4210.h
+@@ -XXX,XX +XXX,XX @@
+  */
+ #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
+-typedef struct Exynos4210Irq {
+-    qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+-    qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
+-} Exynos4210Irq;
+-
+ struct Exynos4210State {
+     /*< private >*/
+     SysBusDevice parent_obj;
+     /*< public >*/
+     ARMCPU *cpu[EXYNOS4210_NCPUS];
+-    Exynos4210Irq irqs;
+     qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
+     MemoryRegion chipid_mem;
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/exynos4210.c
++++ b/hw/arm/exynos4210.c
+@@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline)
+ static void exynos4210_init_board_irqs(Exynos4210State *s)
+ {
+     uint32_t grp, bit, irq_id, n;
+-    Exynos4210Irq *is = &s->irqs;
+     DeviceState *extgicdev = DEVICE(&s->ext_gic);
++    DeviceState *intcdev = DEVICE(&s->int_combiner);
++    DeviceState *extcdev = DEVICE(&s->ext_combiner);
+     int splitcount = 0;
+     DeviceState *splitter;
+     const int *mapline;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+         splitin = 0;
+         for (;;) {
+             s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
+-            qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]);
+-            qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]);
++            qdev_connect_gpio_out(splitter, splitin,
++                                  qdev_get_gpio_in(intcdev, in));
++            qdev_connect_gpio_out(splitter, splitin + 1,
++                                  qdev_get_gpio_in(extcdev, in));
+             splitin += 2;
+             if (!mapline) {
+                 break;
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
+             qdev_realize(splitter, NULL, &error_abort);
+             splitcount++;
+             s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
+-            qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
++            qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n));
+             qdev_connect_gpio_out(splitter, 1,
+                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
+         } else {
+-            s->irq_table[n] = is->int_combiner_irq[n];
++            s->irq_table[n] = qdev_get_gpio_in(intcdev, n);
+         }
+     }
+     /*
+@@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
+     return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
+ }
+-/*
+- * Get Combiner input GPIO into irqs structure
+- */
+-static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
+-                                           DeviceState *dev, int ext)
+-{
+-    int n;
+-    int max;
+-    qemu_irq *irq;
+-
+-    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
+-        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
+-    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
+-
+-    for (n = 0; n < max; n++) {
+-        irq[n] = qdev_get_gpio_in(dev, n);
+-    }
+-}
+-
+ static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
+x09, 0x00, 0x00, 0x00 };
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+         sysbus_connect_irq(busdev, n,
+                            qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
+     }
+-    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
+     /* External Interrupt Combiner */
+@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
+     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
+         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
+     }
+-    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1);
+     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
+     /* Initialize board IRQs. */
+--
+.25.1

-[PULL 9/9] hw/arm/boot: Use the IEC binary prefix definitions
+[PULL 26/31] hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+From: Zongyuan Li <zongyuan.li@smartx.com>
-IEC binary prefixes ease code review: the unit is explicit.
+Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com
 Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
 Reviewed-by: Thomas Huth <thuth@redhat.com>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190923131108.21459-1-philmd@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/boot.c | 10 +++++-----
+ hw/arm/realview.c | 33 ++++++++++++++++++++++++---------
-file changed, 5 insertions(+), 5 deletions(-)
+file changed, 24 insertions(+), 9 deletions(-)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/hw/arm/realview.c b/hw/arm/realview.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/hw/arm/realview.c
-+++ b/hw/arm/boot.c
++++ b/hw/arm/realview.c
-@@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
+@@ -XXX,XX +XXX,XX @@
-         goto fail;
+ #include "hw/sysbus.h"
-     }
+ #include "hw/arm/boot.h"
+ #include "hw/arm/primecell.h"
--    if (scells < 2 && binfo->ram_size >= (1ULL << 32)) {
++#include "hw/core/split-irq.h"
-+    if (scells < 2 && binfo->ram_size >= 4 * GiB) {
+ #include "hw/net/lan9118.h"
-         /* This is user error so deserves a friendlier error message
+ #include "hw/net/smc91c111.h"
-          * than the failure of setprop_sized_cells would provide
+ #include "hw/pci/pci.h"
-          */
++#include "hw/qdev-core.h"
-@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
+ #include "net/net.h"
-      * we might still make a bad choice here.
+ #include "sysemu/sysemu.h"
  #include "hw/boards.h"
@@ -XXX,XX +XXX,XX @@ static const int realview_board_id[] = {
 x76d
  };
 +static void split_irq_from_named(DeviceState *src, const char* outname,
 +                                 qemu_irq out1, qemu_irq out2) {
 +    DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
 +
 +    qdev_prop_set_uint32(splitter, "num-lines", 2);
 +
 +    qdev_realize_and_unref(splitter, NULL, &error_fatal);
 +
 +    qdev_connect_gpio_out(splitter, 0, out1);
 +    qdev_connect_gpio_out(splitter, 1, out2);
 +    qdev_connect_gpio_out_named(src, outname, 0,
 +                                qdev_get_gpio_in(splitter, 0));
 +}
 +
  static void realview_init(MachineState *machine,
                            enum realview_board_type board_type)
  {
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
      DeviceState *dev, *sysctl, *gpio2, *pl041;
      SysBusDevice *busdev;
      qemu_irq pic[64];
 -    qemu_irq mmc_irq[2];
      PCIBus *pci_bus = NULL;
      NICInfo *nd;
      DriveInfo *dinfo;
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
       * and the PL061 has them the other way about. Also the card
       * detect line is inverted.
       */
-     info->initrd_start = info->loader_start +
+-    mmc_irq[0] = qemu_irq_split(
--        MIN(info->ram_size / 2, 128 * 1024 * 1024);
+-        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
-+        MIN(info->ram_size / 2, 128 * MiB);
+-        qdev_get_gpio_in(gpio2, 1));
-     if (image_high_addr) {
+-    mmc_irq[1] = qemu_irq_split(
-         info->initrd_start = MAX(info->initrd_start, image_high_addr);
+-        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
-     }
+-        qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
-@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
+-    qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]);
-                  *
+-    qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]);
-                  * Let's play safe and prealign it to 2MB to give us some space.
++    split_irq_from_named(dev, "card-read-only",
-                  */
++                   qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
--                align = 2 * 1024 * 1024;
++                   qdev_get_gpio_in(gpio2, 1));
-+                align = 2 * MiB;
++
-             } else {
++    split_irq_from_named(dev, "card-inserted",
-                 /*
++                   qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
-                  * Some 32bit kernels will trash anything in the 4K page the
++                   qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
-                  * initrd ends in, so make sure the DTB isn't caught up in that.
++
-                  */
+     dinfo = drive_get(IF_SD, 0, 0);
--                align = 4096;
+     if (dinfo) {
-+                align = 4 * KiB;
+         DeviceState *card;
              }
              /* Place the DTB after the initrd in memory with alignment. */
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
                  info->loader_start + KERNEL_ARGS_ADDR;
              fixupcontext[FIXUP_ARGPTR_HI] =
                  (info->loader_start + KERNEL_ARGS_ADDR) >> 32;
 -            if (info->ram_size >= (1ULL << 32)) {
 +            if (info->ram_size >= 4 * GiB) {
                  error_report("RAM size must be less than 4GB to boot"
                               " Linux kernel using ATAGS (try passing a device tree"
                               " using -dtb)");
 --
-.20.1
+.25.1

-[PULL 2/9] tests/tcg: clean-up some comments after the de-tangling
+[PULL 27/31] hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Zongyuan Li <zongyuan.li@smartx.com>
-These were missed in the recent de-tangling so have been updated to be
+Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
 more actuate. I've also built up ARM_TESTS in a manner similar to
 AARCH64_TESTS for better consistency.
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20190913151845.12582-2-alex.bennee@linaro.org
+Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- tests/tcg/Makefile.target         |  7 +++++--
+ hw/arm/stellaris.c | 15 +++++++++++++--
- tests/tcg/aarch64/Makefile.target |  3 ++-
+file changed, 13 insertions(+), 2 deletions(-)
  tests/tcg/arm/Makefile.target     | 15 ++++++++-------
 files changed, 15 insertions(+), 10 deletions(-)
-diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
+diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
---- a/tests/tcg/Makefile.target
+--- a/hw/arm/stellaris.c
-+++ b/tests/tcg/Makefile.target
++++ b/hw/arm/stellaris.c
-@@ -XXX,XX +XXX,XX @@ TIMEOUT=15
+@@ -XXX,XX +XXX,XX @@
- endif
+ #include "qemu/osdep.h"
- ifdef CONFIG_USER_ONLY
+ #include "qapi/error.h"
--# The order we include is important. We include multiarch, base arch
++#include "hw/core/split-irq.h"
--# and finally arch if it's not the same as base arch.
+ #include "hw/sysbus.h"
-+# The order we include is important. We include multiarch first and
+ #include "hw/sd/sd.h"
-+# then the target. If there are common tests shared between
+ #include "hw/ssi/ssi.h"
-+# sub-targets (e.g. ARM & AArch64) then it is up to
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
-+# $(TARGET_NAME)/Makefile.target to include the common parent
+             DeviceState *ssddev;
-+# architecture in its VPATH.
+             DriveInfo *dinfo;
- -include $(SRC_PATH)/tests/tcg/multiarch/Makefile.target
+             DeviceState *carddev;
- -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.target
++            DeviceState *gpio_d_splitter;
+             BlockBackend *blk;
-diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
-index XXXXXXX..XXXXXXX 100644
+             /*
---- a/tests/tcg/aarch64/Makefile.target
+@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
-+++ b/tests/tcg/aarch64/Makefile.target
+                                    &error_fatal);
-@@ -XXX,XX +XXX,XX @@ VPATH         += $(ARM_SRC)
- AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
+             ssddev = ssi_create_peripheral(bus, "ssd0323");
- VPATH         += $(AARCH64_SRC)
+-            gpio_out[GPIO_D][0] = qemu_irq_split(
+-                    qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
 -# we don't build any other ARM test
 +# Float-convert Tests
  AARCH64_TESTS=fcvt
  fcvt: LDFLAGS+=-lm
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
      $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)")
      $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref)
 +# Pauth Tests
  AARCH64_TESTS += pauth-1 pauth-2
  run-pauth-%: QEMU_OPTS += -cpu max
 diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
 index XXXXXXX..XXXXXXX 100644
 --- a/tests/tcg/arm/Makefile.target
 +++ b/tests/tcg/arm/Makefile.target
@@ -XXX,XX +XXX,XX @@ ARM_SRC=$(SRC_PATH)/tests/tcg/arm
  # Set search path for all sources
  VPATH         += $(ARM_SRC)
 -ARM_TESTS=hello-arm test-arm-iwmmxt
 -
 -TESTS += $(ARM_TESTS) fcvt
 -
 +# Basic Hello World
 +ARM_TESTS = hello-arm
  hello-arm: CFLAGS+=-marm -ffreestanding
  hello-arm: LDFLAGS+=-nostdlib
 +# IWMXT floating point extensions
 +ARM_TESTS += test-arm-iwmmxt
  test-arm-iwmmxt: CFLAGS+=-marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16
  test-arm-iwmmxt: test-arm-iwmmxt.S
      $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)
 -ifeq ($(TARGET_NAME), arm)
 +# Float-convert Tests
 +ARM_TESTS += fcvt
  fcvt: LDFLAGS+=-lm
  # fcvt: CFLAGS+=-march=armv8.2-a+fp16 -mfpu=neon-fp-armv8
 -
  run-fcvt: fcvt
      $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
      $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
 -endif
 +
-+TESTS += $(ARM_TESTS)
++            gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
++            qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
- # On ARM Linux only supports 4k pages
++            qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
- EXTRA_RUNS+=run-test-mmap-4096
++            qdev_connect_gpio_out(
 +                    gpio_d_splitter, 0,
 +                    qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0));
 +            qdev_connect_gpio_out(
 +                    gpio_d_splitter, 1,
                      qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
 +            gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0);
 +
              gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
              /* Make sure the select pin is high.  */
 --
-.20.1
+.25.1

-[PULL 5/9] target/arm: remove run time semihosting checks
+[PULL 28/31] hw/core/irq: remove unused 'qemu_irq_split' function
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Zongyuan Li <zongyuan.li@smartx.com>
-Now we do all our checking and use a common EXCP_SEMIHOST for
+Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
-semihosting operations we can make helper code a lot simpler.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20190913151845.12582-5-alex.bennee@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 96 +++++++++++----------------------------------
+ include/hw/irq.h |  5 -----
-file changed, 22 insertions(+), 74 deletions(-)
+ hw/core/irq.c    | 15 ---------------
 files changed, 20 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/include/hw/irq.h b/include/hw/irq.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/include/hw/irq.h
-+++ b/target/arm/helper.c
++++ b/include/hw/irq.h
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq);
-                   new_el, env->pc, pstate_read(env));
+ /* Returns a new IRQ with opposite polarity.  */
  qemu_irq qemu_irq_invert(qemu_irq irq);
 -/* Returns a new IRQ which feeds into both the passed IRQs.
 - * It's probably better to use the TYPE_SPLIT_IRQ device instead.
 - */
 -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
 -
  /* For internal use in qtest.  Similar to qemu_irq_split, but operating
     on an existing vector of qemu_irq.  */
  void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
 diff --git a/hw/core/irq.c b/hw/core/irq.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/core/irq.c
 +++ b/hw/core/irq.c
@@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_invert(qemu_irq irq)
      return qemu_allocate_irq(qemu_notirq, irq, 0);
  }
--static inline bool check_for_semihosting(CPUState *cs)
+-static void qemu_splitirq(void *opaque, int line, int level)
 -{
-+/*
+-    struct IRQState **irq = opaque;
-+ * Do semihosting call and set the appropriate return value. All the
+-    irq[0]->handler(irq[0]->opaque, irq[0]->n, level);
-+ * permission and validity checks have been done at translate time.
+-    irq[1]->handler(irq[1]->opaque, irq[1]->n, level);
-+ *
+-}
 + * We only see semihosting exceptions in TCG only as they are not
 + * trapped to the hypervisor in KVM.
 + */
  #ifdef CONFIG_TCG
 -    /* Check whether this exception is a semihosting call; if so
 -     * then handle it and return true; otherwise return false.
 -     */
 +static void handle_semihosting(CPUState *cs)
 +{
      ARMCPU *cpu = ARM_CPU(cs);
      CPUARMState *env = &cpu->env;
      if (is_a64(env)) {
 -        if (cs->exception_index == EXCP_SEMIHOST) {
 -            /* This is always the 64-bit semihosting exception.
 -             * The "is this usermode" and "is semihosting enabled"
 -             * checks have been done at translate time.
 -             */
 -            qemu_log_mask(CPU_LOG_INT,
 -                          "...handling as semihosting call 0x%" PRIx64 "\n",
 -                          env->xregs[0]);
 -            env->xregs[0] = do_arm_semihosting(env);
 -            return true;
 -        }
 -        return false;
 +        qemu_log_mask(CPU_LOG_INT,
 +                      "...handling as semihosting call 0x%" PRIx64 "\n",
 +                      env->xregs[0]);
 +        env->xregs[0] = do_arm_semihosting(env);
      } else {
 -        uint32_t imm;
 -
--        /* Only intercept calls from privileged modes, to provide some
+-qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
--         * semblance of security.
+-{
--         */
+-    qemu_irq *s = g_new0(qemu_irq, 2);
--        if (cs->exception_index != EXCP_SEMIHOST &&
+-    s[0] = irq1;
--            (!semihosting_enabled() ||
+-    s[1] = irq2;
--             ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) {
+-    return qemu_allocate_irq(qemu_splitirq, s, 0);
--            return false;
+-}
 -        }
 -
--        switch (cs->exception_index) {
+ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
--        case EXCP_SEMIHOST:
+ {
--            /* This is always a semihosting call; the "is this usermode"
+     int i;
 -             * and "is semihosting enabled" checks have been done at
 -             * translate time.
 -             */
 -            break;
 -        case EXCP_SWI:
 -            /* Check for semihosting interrupt.  */
 -            if (env->thumb) {
 -                imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
 -                    & 0xff;
 -                if (imm == 0xab) {
 -                    break;
 -                }
 -            } else {
 -                imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
 -                    & 0xffffff;
 -                if (imm == 0x123456) {
 -                    break;
 -                }
 -            }
 -            return false;
 -        case EXCP_BKPT:
 -            /* See if this is a semihosting syscall.  */
 -            if (env->thumb) {
 -                imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
 -                    & 0xff;
 -                if (imm == 0xab) {
 -                    env->regs[15] += 2;
 -                    break;
 -                }
 -            }
 -            return false;
 -        default:
 -            return false;
 -        }
 -
          qemu_log_mask(CPU_LOG_INT,
                        "...handling as semihosting call 0x%x\n",
                        env->regs[0]);
          env->regs[0] = do_arm_semihosting(env);
 -        return true;
      }
 -#else
 -    return false;
 -#endif
  }
 +#endif
  /* Handle a CPU exception for A and R profile CPUs.
   * Do any appropriate logging, handle PSCI calls, and then hand off
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
          return;
      }
 -    /* Semihosting semantics depend on the register width of the
 -     * code that caused the exception, not the target exception level,
 -     * so must be handled here.
 +    /*
 +     * Semihosting semantics depend on the register width of the code
 +     * that caused the exception, not the target exception level, so
 +     * must be handled here.
       */
 -    if (check_for_semihosting(cs)) {
 +#ifdef CONFIG_TCG
 +    if (cs->exception_index == EXCP_SEMIHOST) {
 +        handle_semihosting(cs);
          return;
      }
 +#endif
      /* Hooks may change global state so BQL should be held, also the
       * BQL needs to be held for any modification of
 --
-.20.1
+.25.1

-[PULL 1/9] target/arm: fix CBAR register for AArch64 CPUs
+[PULL 29/31] hw/arm/virt: impact of gic-version on max CPUs
-From: Luc Michel <luc.michel@greensocs.com>
+From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
-For AArch64 CPUs with a CBAR register, we have two views for it:
+Describe that the gic-version influences the maximum number of CPUs.
   - in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the
     full 64 bits CBAR value
   - in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0)
     returns a 32 bits view such that:
       CBAR = CBAR_EL1[31:18] 0..0 CBAR_EL1[43:32]
-This commit fixes the current implementation where:
+Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
-  - CBAR_EL1 was returning the 32 bits view instead of the full 64 bits
+Message-id: 20220413231456.35811-1-heinrich.schuchardt@canonical.com
-    value,
+[PMM: minor punctuation tweaks]
   - CBAR was returning a truncated 32 bits version of the full 64 bits
     one, instead of the 32 bits view
   - CBAR was declared as cp15, opc1=4, CRn=15, CRm=0, opc2=0, which is
     the CBAR register found in the ARMv7 Cortex-Ax CPUs, but not in
     ARMv8 CPUs.
 Signed-off-by: Luc Michel <luc.michel@greensocs.com>
 Message-id: 20190912110103.1417887-1-luc.michel@greensocs.com
 [PMM: Added a comment about the two different kinds of CBAR]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/helper.c | 19 ++++++++++++++++---
+ docs/system/arm/virt.rst | 4 ++--
-file changed, 16 insertions(+), 3 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/docs/system/arm/virt.rst
-+++ b/target/arm/helper.c
++++ b/docs/system/arm/virt.rst
-@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
+@@ -XXX,XX +XXX,XX @@ gic-version
-     }
+   Valid values are:
-     if (arm_feature(env, ARM_FEATURE_CBAR)) {
+   ``2``
-+        /*
+-    GICv2
-+         * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
++    GICv2. Note that this limits the number of CPUs to 8.
-+         * There are two flavours:
+   ``3``
-+         *  (1) older 32-bit only cores have a simple 32-bit CBAR
+-    GICv3
-+         *  (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
++    GICv3. This allows up to 512 CPUs.
-+         *      32-bit register visible to AArch32 at a different encoding
+   ``host``
-+         *      to the "flavour 1" register and with the bits rearranged to
+     Use the same GIC version the host provides, when using KVM
-+         *      be able to squash a 64-bit address into the 32-bit view.
+   ``max``
 +         * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
 +         * in future if we support AArch32-only configs of some of the
 +         * AArch64 cores we might need to add a specific feature flag
 +         * to indicate cores with "flavour 2" CBAR.
 +         */
          if (arm_feature(env, ARM_FEATURE_AARCH64)) {
              /* 32 bit view is [31:18] 0...0 [43:32]. */
              uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
              ARMCPRegInfo cbar_reginfo[] = {
                  { .name = "CBAR",
                    .type = ARM_CP_CONST,
 -                  .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
 -                  .access = PL1_R, .resetvalue = cpu->reset_cbar },
 +                  .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0,
 +                  .access = PL1_R, .resetvalue = cbar32 },
                  { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
                    .type = ARM_CP_CONST,
                    .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
 -                  .access = PL1_R, .resetvalue = cbar32 },
 +                  .access = PL1_R, .resetvalue = cpu->reset_cbar },
                  REGINFO_SENTINEL
              };
              /* We don't implement a r/w 64 bit CBAR currently */
 --
-.20.1
+.25.1

-[PULL 6/9] target/arm: remove run-time semihosting checks for linux-user
+[PULL 30/31] hw/misc: Add PWRON STRAP bit fields in GCR module
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Hao Wu <wuhaotsh@google.com>
-Now we do all our checking at translate time we can make cpu_loop a
+Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
-little bit simpler. We also introduce a simple linux-user semihosting
+the PWRON STRAP fields in their corresponding module for NPCM7XX.
 test case to defend the functionality. The out-of-tree softmmu based
 semihosting tests are still more comprehensive.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
-Message-id: 20190913151845.12582-6-alex.bennee@linaro.org
+Reviewed-by: Patrick Venture <venture@google.com>
 Message-id: 20220411165842.3912945-2-wuhaotsh@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- linux-user/arm/target_syscall.h | 3 ---
+ include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++
- linux-user/arm/cpu_loop.c       | 3 ---
+file changed, 30 insertions(+)
 files changed, 6 deletions(-)
-diff --git a/linux-user/arm/target_syscall.h b/linux-user/arm/target_syscall.h
+diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/arm/target_syscall.h
+--- a/include/hw/misc/npcm7xx_gcr.h
-+++ b/linux-user/arm/target_syscall.h
++++ b/include/hw/misc/npcm7xx_gcr.h
-@@ -XXX,XX +XXX,XX @@ struct target_pt_regs {
+@@ -XXX,XX +XXX,XX @@
- #define ARM_NR_set_tls      (ARM_NR_BASE + 5)
+ #include "exec/memory.h"
- #define ARM_NR_get_tls    (ARM_NR_BASE + 6)
+ #include "hw/sysbus.h"
--#define ARM_NR_semihosting      0x123456
++/*
--#define ARM_NR_thumb_semihosting  0xAB
++ * NPCM7XX PWRON STRAP bit fields
--
++ * 12: SPI0 powered by VSBV3 at 1.8V
- #if defined(TARGET_WORDS_BIGENDIAN)
++ * 11: System flash attached to BMC
- #define UNAME_MACHINE "armv5teb"
++ * 10: BSP alternative pins.
- #else
++ * 9:8: Flash UART command route enabled.
-diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
++ * 7: Security enabled.
-index XXXXXXX..XXXXXXX 100644
++ * 6: HI-Z state control.
---- a/linux-user/arm/cpu_loop.c
++ * 5: ECC disabled.
-+++ b/linux-user/arm/cpu_loop.c
++ * 4: Reserved
-@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
++ * 3: JTAG2 enabled.
++ * 2:0: CPU and DRAM clock frequency.
-                 if (n == ARM_NR_cacheflush) {
++ */
-                     /* nop */
++#define NPCM7XX_PWRON_STRAP_SPI0F18                 BIT(12)
--                } else if (n == ARM_NR_semihosting
++#define NPCM7XX_PWRON_STRAP_SFAB                    BIT(11)
--                           || n == ARM_NR_thumb_semihosting) {
++#define NPCM7XX_PWRON_STRAP_BSPA                    BIT(10)
--                    env->regs[0] = do_arm_semihosting (env);
++#define NPCM7XX_PWRON_STRAP_FUP(x)                  ((x) << 8)
-                 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
++#define     FUP_NORM_UART2      3
-                     /* linux syscall */
++#define     FUP_PROG_UART3      2
-                     if (env->thumb || n == 0) {
++#define     FUP_PROG_UART2      1
 +#define     FUP_NORM_UART3      0
 +#define NPCM7XX_PWRON_STRAP_SECEN                   BIT(7)
 +#define NPCM7XX_PWRON_STRAP_HIZ                     BIT(6)
 +#define NPCM7XX_PWRON_STRAP_ECC                     BIT(5)
 +#define NPCM7XX_PWRON_STRAP_RESERVE1                BIT(4)
 +#define NPCM7XX_PWRON_STRAP_J2EN                    BIT(3)
 +#define NPCM7XX_PWRON_STRAP_CKFRQ(x)                (x)
 +#define     CKFRQ_SKIPINIT      0x000
 +#define     CKFRQ_DEFAULT       0x111
 +
  /*
   * Number of registers in our device state structure. Don't change this without
   * incrementing the version_id in the vmstate.
 --
-.20.1
+.25.1

-[PULL 3/9] target/arm: handle M-profile semihosting at translate time
+[PULL 31/31] hw/arm: Use bit fields for NPCM7XX PWRON STRAPs
-From: Alex Bennée <alex.bennee@linaro.org>
+From: Hao Wu <wuhaotsh@google.com>
-We do this for other semihosting calls so we might as well do it for
+This patch uses the defined fields to describe PWRON STRAPs for
-M-profile as well.
+better readability.
-Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
+Signed-off-by: Hao Wu <wuhaotsh@google.com>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Patrick Venture <venture@google.com>
-Message-id: 20190913151845.12582-3-alex.bennee@linaro.org
+Message-id: 20220411165842.3912945-3-wuhaotsh@google.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/m_helper.c  | 18 ++++++------------
+ hw/arm/npcm7xx_boards.c | 24 +++++++++++++++++++-----
- target/arm/translate.c | 11 ++++++++++-
+file changed, 19 insertions(+), 5 deletions(-)
 files changed, 16 insertions(+), 13 deletions(-)
-diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
+diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/m_helper.c
+--- a/hw/arm/npcm7xx_boards.c
-+++ b/target/arm/m_helper.c
++++ b/hw/arm/npcm7xx_boards.c
-@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
+@@ -XXX,XX +XXX,XX @@
-             break;
+ #include "sysemu/sysemu.h"
-         }
+ #include "sysemu/block-backend.h"
-         break;
-+    case EXCP_SEMIHOST:
+-#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
-+        qemu_log_mask(CPU_LOG_INT,
+-#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
-+                      "...handling as semihosting call 0x%x\n",
+-#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff
-+                      env->regs[0]);
+-#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff
-+        env->regs[0] = do_arm_semihosting(env);
+-#define MORI_BMC_POWER_ON_STRAPS 0x00001fff
-+        return;
++#define NPCM7XX_POWER_ON_STRAPS_DEFAULT (           \
-     case EXCP_BKPT:
++        NPCM7XX_PWRON_STRAP_SPI0F18 |               \
--        if (semihosting_enabled()) {
++        NPCM7XX_PWRON_STRAP_SFAB |                  \
--            int nr;
++        NPCM7XX_PWRON_STRAP_BSPA |                  \
--            nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
++        NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) |   \
--            if (nr == 0xab) {
++        NPCM7XX_PWRON_STRAP_SECEN |                 \
--                env->regs[15] += 2;
++        NPCM7XX_PWRON_STRAP_HIZ |                   \
--                qemu_log_mask(CPU_LOG_INT,
++        NPCM7XX_PWRON_STRAP_ECC |                   \
--                              "...handling as semihosting call 0x%x\n",
++        NPCM7XX_PWRON_STRAP_RESERVE1 |              \
--                              env->regs[0]);
++        NPCM7XX_PWRON_STRAP_J2EN |                  \
--                env->regs[0] = do_arm_semihosting(env);
++        NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT))
--                return;
++
--            }
++#define NPCM750_EVB_POWER_ON_STRAPS ( \
--        }
++        NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN)
-         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
++#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
-         break;
++#define QUANTA_GBS_POWER_ON_STRAPS ( \
-     case EXCP_IRQ:
++        NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
++#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
-index XXXXXXX..XXXXXXX 100644
++#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
+ static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
@@ -XXX,XX +XXX,XX @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a)
      if (!ENABLE_ARCH_5) {
          return false;
      }
 -    gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
 +    if (arm_dc_feature(s, ARM_FEATURE_M) &&
 +        semihosting_enabled() &&
 +#ifndef CONFIG_USER_ONLY
 +        !IS_USER(s) &&
 +#endif
 +        (a->imm == 0xab)) {
 +        gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
 +    } else {
 +        gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
 +    }
      return true;
  }
 --
-.20.1
+.25.1

target-arm queue: nothing major here, but no point
sitting on them waiting for more stuff to come along.

thanks
-- PMM

The following changes since commit 1329132d28bf14b9508f7a1f04a2c63422bc3f99:

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2019-09-26 16:14:03 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190927

for you to fetch changes up to e4e34855e658b78ecac50a651cc847662ff02cfd:

hw/arm/boot: Use the IEC binary prefix definitions (2019-09-27 11:44:39 +0100)

----------------------------------------------------------------
target-arm queue:
 * Fix the CBAR register implementation for Cortex-A53,
   Cortex-A57, Cortex-A72
 * Fix direct booting of Linux kernels on emulated CPUs
   which have an AArch32 EL3 (incorrect NSACR settings
   meant they could not access the FPU)
 * semihosting cleanup: do more work at translate time
   and less work at runtime

----------------------------------------------------------------
Alex Bennée (6):
      tests/tcg: clean-up some comments after the de-tangling
      target/arm: handle M-profile semihosting at translate time
      target/arm: handle A-profile semihosting at translate time
      target/arm: remove run time semihosting checks
      target/arm: remove run-time semihosting checks for linux-user
      tests/tcg: add linux-user semihosting smoke test for ARM

Luc Michel (1):
      target/arm: fix CBAR register for AArch64 CPUs

Peter Maydell (1):
      hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots

Philippe Mathieu-Daudé (1):
      hw/arm/boot: Use the IEC binary prefix definitions

tests/tcg/Makefile.target         |   7 ++-
 tests/tcg/aarch64/Makefile.target |   8 ++-
 tests/tcg/arm/Makefile.target     |  20 ++++---
 linux-user/arm/target_syscall.h   |   3 -
 hw/arm/boot.c                     |  12 ++--
 linux-user/arm/cpu_loop.c         |   3 -
 target/arm/helper.c               | 115 +++++++++++++-------------------------
 target/arm/m_helper.c             |  18 ++----
 target/arm/translate.c            |  30 ++++++++--
 tests/tcg/arm/semihosting.c       |  45 +++++++++++++++
 10 files changed, 146 insertions(+), 115 deletions(-)
 create mode 100644 tests/tcg/arm/semihosting.c

From: Luc Michel <luc.michel@greensocs.com>

For AArch64 CPUs with a CBAR register, we have two views for it:
  - in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the
    full 64 bits CBAR value
  - in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0)
    returns a 32 bits view such that:
      CBAR = CBAR_EL1[31:18] 0..0 CBAR_EL1[43:32]

This commit fixes the current implementation where:
  - CBAR_EL1 was returning the 32 bits view instead of the full 64 bits
    value,
  - CBAR was returning a truncated 32 bits version of the full 64 bits
    one, instead of the 32 bits view
  - CBAR was declared as cp15, opc1=4, CRn=15, CRm=0, opc2=0, which is
    the CBAR register found in the ARMv7 Cortex-Ax CPUs, but not in
    ARMv8 CPUs.

Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20190912110103.1417887-1-luc.michel@greensocs.com
[PMM: Added a comment about the two different kinds of CBAR]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
     }
 
     if (arm_feature(env, ARM_FEATURE_CBAR)) {
+        /*
+         * CBAR is IMPDEF, but common on Arm Cortex-A implementations.
+         * There are two flavours:
+         *  (1) older 32-bit only cores have a simple 32-bit CBAR
+         *  (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a
+         *      32-bit register visible to AArch32 at a different encoding
+         *      to the "flavour 1" register and with the bits rearranged to
+         *      be able to squash a 64-bit address into the 32-bit view.
+         * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but
+         * in future if we support AArch32-only configs of some of the
+         * AArch64 cores we might need to add a specific feature flag
+         * to indicate cores with "flavour 2" CBAR.
+         */
         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
             /* 32 bit view is [31:18] 0...0 [43:32]. */
             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
             ARMCPRegInfo cbar_reginfo[] = {
                 { .name = "CBAR",
                   .type = ARM_CP_CONST,
-                  .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
-                  .access = PL1_R, .resetvalue = cpu->reset_cbar },
+                  .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0,
+                  .access = PL1_R, .resetvalue = cbar32 },
                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
                   .type = ARM_CP_CONST,
                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
-                  .access = PL1_R, .resetvalue = cbar32 },
+                  .access = PL1_R, .resetvalue = cpu->reset_cbar },
                 REGINFO_SENTINEL
             };
             /* We don't implement a r/w 64 bit CBAR currently */
-- 
2.20.1

From: Alex Bennée <alex.bennee@linaro.org>

These were missed in the recent de-tangling so have been updated to be
more actuate. I've also built up ARM_TESTS in a manner similar to
AARCH64_TESTS for better consistency.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190913151845.12582-2-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/tcg/Makefile.target         |  7 +++++--
 tests/tcg/aarch64/Makefile.target |  3 ++-
 tests/tcg/arm/Makefile.target     | 15 ++++++++-------
 3 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/Makefile.target
+++ b/tests/tcg/Makefile.target
@@ -XXX,XX +XXX,XX @@ TIMEOUT=15
 endif
 
 ifdef CONFIG_USER_ONLY
-# The order we include is important. We include multiarch, base arch
-# and finally arch if it's not the same as base arch.
+# The order we include is important. We include multiarch first and
+# then the target. If there are common tests shared between
+# sub-targets (e.g. ARM & AArch64) then it is up to
+# $(TARGET_NAME)/Makefile.target to include the common parent
+# architecture in its VPATH.
 -include $(SRC_PATH)/tests/tcg/multiarch/Makefile.target
 -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.target
 
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ VPATH 		+= $(ARM_SRC)
 AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
 VPATH 		+= $(AARCH64_SRC)
 
-# we don't build any other ARM test
+# Float-convert Tests
 AARCH64_TESTS=fcvt
 
 fcvt: LDFLAGS+=-lm
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
 	$(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)")
 	$(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref)
 
+# Pauth Tests
 AARCH64_TESTS += pauth-1 pauth-2
 run-pauth-%: QEMU_OPTS += -cpu max
 
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/arm/Makefile.target
+++ b/tests/tcg/arm/Makefile.target
@@ -XXX,XX +XXX,XX @@ ARM_SRC=$(SRC_PATH)/tests/tcg/arm
 # Set search path for all sources
 VPATH 		+= $(ARM_SRC)
 
-ARM_TESTS=hello-arm test-arm-iwmmxt
-
-TESTS += $(ARM_TESTS) fcvt
-
+# Basic Hello World
+ARM_TESTS = hello-arm
 hello-arm: CFLAGS+=-marm -ffreestanding
 hello-arm: LDFLAGS+=-nostdlib
 
+# IWMXT floating point extensions
+ARM_TESTS += test-arm-iwmmxt
 test-arm-iwmmxt: CFLAGS+=-marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16
 test-arm-iwmmxt: test-arm-iwmmxt.S
 	$(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)
 
-ifeq ($(TARGET_NAME), arm)
+# Float-convert Tests
+ARM_TESTS += fcvt
 fcvt: LDFLAGS+=-lm
 # fcvt: CFLAGS+=-march=armv8.2-a+fp16 -mfpu=neon-fp-armv8
-
 run-fcvt: fcvt
 	$(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
 	$(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
-endif
+
+TESTS += $(ARM_TESTS)
 
 # On ARM Linux only supports 4k pages
 EXTRA_RUNS+=run-test-mmap-4096
-- 
2.20.1

From: Alex Bennée <alex.bennee@linaro.org>

We do this for other semihosting calls so we might as well do it for
M-profile as well.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190913151845.12582-3-alex.bennee@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/m_helper.c  | 18 ++++++------------
 target/arm/translate.c | 11 ++++++++++-
 2 files changed, 16 insertions(+), 13 deletions(-)

diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
             break;
         }
         break;
+    case EXCP_SEMIHOST:
+        qemu_log_mask(CPU_LOG_INT,
+                      "...handling as semihosting call 0x%x\n",
+                      env->regs[0]);
+        env->regs[0] = do_arm_semihosting(env);
+        return;
     case EXCP_BKPT:
-        if (semihosting_enabled()) {
-            int nr;
-            nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
-            if (nr == 0xab) {
-                env->regs[15] += 2;
-                qemu_log_mask(CPU_LOG_INT,
-                              "...handling as semihosting call 0x%x\n",
-                              env->regs[0]);
-                env->regs[0] = do_arm_semihosting(env);
-                return;
-            }
-        }
         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);
         break;
     case EXCP_IRQ:
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a)
     if (!ENABLE_ARCH_5) {
         return false;
     }
-    gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
+    if (arm_dc_feature(s, ARM_FEATURE_M) &&
+        semihosting_enabled() &&
+#ifndef CONFIG_USER_ONLY
+        !IS_USER(s) &&
+#endif
+        (a->imm == 0xab)) {
+        gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
+    } else {
+        gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false));
+    }
     return true;
 }
 
-- 
2.20.1

From: Alex Bennée <alex.bennee@linaro.org>

As for the other semihosting calls we can resolve this at translate
time.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190913151845.12582-4-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a)
 }
 
 /*
- * Supervisor call
+ * Supervisor call - both T32 & A32 come here so we need to check
+ * which mode we are in when checking for semihosting.
  */
 
 static bool trans_SVC(DisasContext *s, arg_SVC *a)
 {
-    gen_set_pc_im(s, s->base.pc_next);
-    s->svc_imm = a->imm;
-    s->base.is_jmp = DISAS_SWI;
+    const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456;
+
+    if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() &&
+#ifndef CONFIG_USER_ONLY
+        !IS_USER(s) &&
+#endif
+        (a->imm == semihost_imm)) {
+        gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
+    } else {
+        gen_set_pc_im(s, s->base.pc_next);
+        s->svc_imm = a->imm;
+        s->base.is_jmp = DISAS_SWI;
+    }
     return true;
 }
 
-- 
2.20.1

From: Alex Bennée <alex.bennee@linaro.org>

Now we do all our checking and use a common EXCP_SEMIHOST for
semihosting operations we can make helper code a lot simpler.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190913151845.12582-5-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 96 +++++++++++----------------------------------
 1 file changed, 22 insertions(+), 74 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
                   new_el, env->pc, pstate_read(env));
 }
 
-static inline bool check_for_semihosting(CPUState *cs)
-{
+/*
+ * Do semihosting call and set the appropriate return value. All the
+ * permission and validity checks have been done at translate time.
+ *
+ * We only see semihosting exceptions in TCG only as they are not
+ * trapped to the hypervisor in KVM.
+ */
 #ifdef CONFIG_TCG
-    /* Check whether this exception is a semihosting call; if so
-     * then handle it and return true; otherwise return false.
-     */
+static void handle_semihosting(CPUState *cs)
+{
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
 
     if (is_a64(env)) {
-        if (cs->exception_index == EXCP_SEMIHOST) {
-            /* This is always the 64-bit semihosting exception.
-             * The "is this usermode" and "is semihosting enabled"
-             * checks have been done at translate time.
-             */
-            qemu_log_mask(CPU_LOG_INT,
-                          "...handling as semihosting call 0x%" PRIx64 "\n",
-                          env->xregs[0]);
-            env->xregs[0] = do_arm_semihosting(env);
-            return true;
-        }
-        return false;
+        qemu_log_mask(CPU_LOG_INT,
+                      "...handling as semihosting call 0x%" PRIx64 "\n",
+                      env->xregs[0]);
+        env->xregs[0] = do_arm_semihosting(env);
     } else {
-        uint32_t imm;
-
-        /* Only intercept calls from privileged modes, to provide some
-         * semblance of security.
-         */
-        if (cs->exception_index != EXCP_SEMIHOST &&
-            (!semihosting_enabled() ||
-             ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) {
-            return false;
-        }
-
-        switch (cs->exception_index) {
-        case EXCP_SEMIHOST:
-            /* This is always a semihosting call; the "is this usermode"
-             * and "is semihosting enabled" checks have been done at
-             * translate time.
-             */
-            break;
-        case EXCP_SWI:
-            /* Check for semihosting interrupt.  */
-            if (env->thumb) {
-                imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
-                    & 0xff;
-                if (imm == 0xab) {
-                    break;
-                }
-            } else {
-                imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
-                    & 0xffffff;
-                if (imm == 0x123456) {
-                    break;
-                }
-            }
-            return false;
-        case EXCP_BKPT:
-            /* See if this is a semihosting syscall.  */
-            if (env->thumb) {
-                imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
-                    & 0xff;
-                if (imm == 0xab) {
-                    env->regs[15] += 2;
-                    break;
-                }
-            }
-            return false;
-        default:
-            return false;
-        }
-
         qemu_log_mask(CPU_LOG_INT,
                       "...handling as semihosting call 0x%x\n",
                       env->regs[0]);
         env->regs[0] = do_arm_semihosting(env);
-        return true;
     }
-#else
-    return false;
-#endif
 }
+#endif
 
 /* Handle a CPU exception for A and R profile CPUs.
  * Do any appropriate logging, handle PSCI calls, and then hand off
@@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs)
         return;
     }
 
-    /* Semihosting semantics depend on the register width of the
-     * code that caused the exception, not the target exception level,
-     * so must be handled here.
+    /*
+     * Semihosting semantics depend on the register width of the code
+     * that caused the exception, not the target exception level, so
+     * must be handled here.
      */
-    if (check_for_semihosting(cs)) {
+#ifdef CONFIG_TCG
+    if (cs->exception_index == EXCP_SEMIHOST) {
+        handle_semihosting(cs);
         return;
     }
+#endif
 
     /* Hooks may change global state so BQL should be held, also the
      * BQL needs to be held for any modification of
-- 
2.20.1

From: Alex Bennée <alex.bennee@linaro.org>

Now we do all our checking at translate time we can make cpu_loop a
little bit simpler. We also introduce a simple linux-user semihosting
test case to defend the functionality. The out-of-tree softmmu based
semihosting tests are still more comprehensive.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20190913151845.12582-6-alex.bennee@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/arm/target_syscall.h | 3 ---
 linux-user/arm/cpu_loop.c       | 3 ---
 2 files changed, 6 deletions(-)

diff --git a/linux-user/arm/target_syscall.h b/linux-user/arm/target_syscall.h
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/arm/target_syscall.h
+++ b/linux-user/arm/target_syscall.h
@@ -XXX,XX +XXX,XX @@ struct target_pt_regs {
 #define ARM_NR_set_tls	  (ARM_NR_BASE + 5)
 #define ARM_NR_get_tls    (ARM_NR_BASE + 6)
 
-#define ARM_NR_semihosting	  0x123456
-#define ARM_NR_thumb_semihosting  0xAB
-
 #if defined(TARGET_WORDS_BIGENDIAN)
 #define UNAME_MACHINE "armv5teb"
 #else
diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/arm/cpu_loop.c
+++ b/linux-user/arm/cpu_loop.c
@@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env)
 
                 if (n == ARM_NR_cacheflush) {
                     /* nop */
-                } else if (n == ARM_NR_semihosting
-                           || n == ARM_NR_thumb_semihosting) {
-                    env->regs[0] = do_arm_semihosting (env);
                 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
                     /* linux syscall */
                     if (env->thumb || n == 0) {
-- 
2.20.1

From: Alex Bennée <alex.bennee@linaro.org>

We already use semihosting for the system stuff so this is a simple
smoke test to ensure we are working OK on linux-user.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20190913151845.12582-7-alex.bennee@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 tests/tcg/aarch64/Makefile.target |  5 ++++
 tests/tcg/arm/Makefile.target     |  5 ++++
 tests/tcg/arm/semihosting.c       | 45 +++++++++++++++++++++++++++++++
 3 files changed, 55 insertions(+)
 create mode 100644 tests/tcg/arm/semihosting.c

diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
 AARCH64_TESTS += pauth-1 pauth-2
 run-pauth-%: QEMU_OPTS += -cpu max
 
+# Semihosting smoke test for linux-user
+AARCH64_TESTS += semihosting
+run-semihosting: semihosting
+	$(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)")
+
 TESTS += $(AARCH64_TESTS)
diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target
index XXXXXXX..XXXXXXX 100644
--- a/tests/tcg/arm/Makefile.target
+++ b/tests/tcg/arm/Makefile.target
@@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt
 	$(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)")
 	$(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref)
 
+# Semihosting smoke test for linux-user
+ARM_TESTS += semihosting
+run-semihosting: semihosting
+	$(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)")
+
 TESTS += $(ARM_TESTS)
 
 # On ARM Linux only supports 4k pages
diff --git a/tests/tcg/arm/semihosting.c b/tests/tcg/arm/semihosting.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/tests/tcg/arm/semihosting.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * linux-user semihosting checks
+ *
+ * Copyright (c) 2019
+ * Written by Alex Bennée <alex.bennee@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-3.0-or-later
+ */
+
+#include <stdint.h>
+
+#define SYS_WRITE0      0x04
+#define SYS_REPORTEXC   0x18
+
+void __semi_call(uintptr_t type, uintptr_t arg0)
+{
+#if defined(__arm__)
+    register uintptr_t t asm("r0") = type;
+    register uintptr_t a0 asm("r1") = arg0;
+    asm("svc 0xab"
+        : /* no return */
+        : "r" (t), "r" (a0));
+#else
+    register uintptr_t t asm("x0") = type;
+    register uintptr_t a0 asm("x1") = arg0;
+    asm("hlt 0xf000"
+        : /* no return */
+        : "r" (t), "r" (a0));
+#endif
+}
+
+int main(int argc, char *argv[argc])
+{
+#if defined(__arm__)
+    uintptr_t exit_code = 0x20026;
+#else
+    uintptr_t exit_block[2] = {0x20026, 0};
+    uintptr_t exit_code = (uintptr_t) &exit_block;
+#endif
+
+    __semi_call(SYS_WRITE0, (uintptr_t) "Hello World");
+    __semi_call(SYS_REPORTEXC, exit_code);
+    /* if we get here we failed */
+    return -1;
+}
-- 
2.20.1

If we're booting a Linux kernel directly into Non-Secure
state on a CPU which has Secure state, then make sure we
set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed
to access the FPU. Otherwise an AArch32 kernel will UNDEF as
soon as it tries to use the FPU.

It used to not matter that we didn't do this until commit
fc1120a7f5f2d4b6, where we implemented actually honouring
these NSACR bits.

The problem only exists for CPUs where EL3 is AArch32; the
equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to
not trap, 1 to trap", so the reset value of the register
permits NS access, unlike NSACR.

Fixes: fc1120a7f5
Fixes: https://bugs.launchpad.net/qemu/+bug/1844597
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190920174039.3916-1-peter.maydell@linaro.org
---
 hw/arm/boot.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
                     (cs != first_cpu || !info->secure_board_setup)) {
                     /* Linux expects non-secure state */
                     env->cp15.scr_el3 |= SCR_NS;
+                    /* Set NSACR.{CP11,CP10} so NS can access the FPU */
+                    env->cp15.nsacr |= 3 << 10;
                 }
             }
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

IEC binary prefixes ease code review: the unit is explicit.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190923131108.21459-1-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/boot.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
         goto fail;
     }
 
-    if (scells < 2 && binfo->ram_size >= (1ULL << 32)) {
+    if (scells < 2 && binfo->ram_size >= 4 * GiB) {
         /* This is user error so deserves a friendlier error message
          * than the failure of setprop_sized_cells would provide
          */
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
      * we might still make a bad choice here.
      */
     info->initrd_start = info->loader_start +
-        MIN(info->ram_size / 2, 128 * 1024 * 1024);
+        MIN(info->ram_size / 2, 128 * MiB);
     if (image_high_addr) {
         info->initrd_start = MAX(info->initrd_start, image_high_addr);
     }
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
                  *
                  * Let's play safe and prealign it to 2MB to give us some space.
                  */
-                align = 2 * 1024 * 1024;
+                align = 2 * MiB;
             } else {
                 /*
                  * Some 32bit kernels will trash anything in the 4K page the
                  * initrd ends in, so make sure the DTB isn't caught up in that.
                  */
-                align = 4096;
+                align = 4 * KiB;
             }
 
             /* Place the DTB after the initrd in memory with alignment. */
@@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
                 info->loader_start + KERNEL_ARGS_ADDR;
             fixupcontext[FIXUP_ARGPTR_HI] =
                 (info->loader_start + KERNEL_ARGS_ADDR) >> 32;
-            if (info->ram_size >= (1ULL << 32)) {
+            if (info->ram_size >= 4 * GiB) {
                 error_report("RAM size must be less than 4GB to boot"
                              " Linux kernel using ATAGS (try passing a device tree"
                              " using -dtb)");
-- 
2.20.1

First arm pullreq for 7.1. The bulk of this is the qemu_split_irq
removal.

I have enough stuff in my to-review queue that I expect to do another
pullreq early next week, but 31 patches is enough to not hang on to.

thanks
-- PMM

The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b:

Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging (2022-04-20 16:43:11 -0700)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220421

for you to fetch changes up to 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6:

hw/arm: Use bit fields for NPCM7XX PWRON STRAPs (2022-04-21 11:37:05 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
 * versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
 * versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s
 * xlnx-zynqmp: Connect 4 TTC timers
 * exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq
 * realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
 * stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
 * hw/core/irq: remove unused 'qemu_irq_split' function
 * npcm7xx: use symbolic constants for PWRON STRAP bit fields
 * virt: document impact of gic-version on max CPUs

----------------------------------------------------------------
Edgar E. Iglesias (6):
      timer: cadence_ttc: Break out header file to allow embedding
      hw/arm/xlnx-zynqmp: Connect 4 TTC timers
      hw/arm: versal: Create an APU CPU Cluster
      hw/arm: versal: Add the Cortex-R5Fs
      hw/misc: Add a model of the Xilinx Versal CRL
      hw/arm: versal: Connect the CRL

Hao Wu (2):
      hw/misc: Add PWRON STRAP bit fields in GCR module
      hw/arm: Use bit fields for NPCM7XX PWRON STRAPs

Heinrich Schuchardt (1):
      hw/arm/virt: impact of gic-version on max CPUs

Peter Maydell (19):
      hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
      hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device
      hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
      hw/arm/exynos4210: Put a9mpcore device into state struct
      hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct
      hw/arm/exynos4210: Coalesce board_irqs and irq_table
      hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
      hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
      hw/arm/exynos4210: Put external GIC into state struct
      hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
      hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c
      hw/arm/exynos4210: Delete unused macro definitions
      hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
      hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines
      hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
      hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
      hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
      hw/arm/exynos4210: Put combiners into state struct
      hw/arm/exynos4210: Drop Exynos4210Irq struct

Zongyuan Li (3):
      hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
      hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
      hw/core/irq: remove unused 'qemu_irq_split' function

docs/system/arm/virt.rst              |   4 +-
 include/hw/arm/exynos4210.h           |  50 ++--
 include/hw/arm/xlnx-versal.h          |  16 ++
 include/hw/arm/xlnx-zynqmp.h          |   4 +
 include/hw/intc/exynos4210_combiner.h |  57 +++++
 include/hw/intc/exynos4210_gic.h      |  43 ++++
 include/hw/irq.h                      |   5 -
 include/hw/misc/npcm7xx_gcr.h         |  30 +++
 include/hw/misc/xlnx-versal-crl.h     | 235 +++++++++++++++++++
 include/hw/timer/cadence_ttc.h        |  54 +++++
 hw/arm/exynos4210.c                   | 430 ++++++++++++++++++++++++++++++----
 hw/arm/npcm7xx_boards.c               |  24 +-
 hw/arm/realview.c                     |  33 ++-
 hw/arm/stellaris.c                    |  15 +-
 hw/arm/virt.c                         |   7 +
 hw/arm/xlnx-versal-virt.c             |   6 +-
 hw/arm/xlnx-versal.c                  |  99 +++++++-
 hw/arm/xlnx-zynqmp.c                  |  22 ++
 hw/core/irq.c                         |  15 --
 hw/intc/exynos4210_combiner.c         | 108 +--------
 hw/intc/exynos4210_gic.c              | 344 +--------------------------
 hw/misc/xlnx-versal-crl.c             | 421 +++++++++++++++++++++++++++++++++
 hw/timer/cadence_ttc.c                |  32 +--
 MAINTAINERS                           |   2 +-
 hw/misc/meson.build                   |   1 +
 25 files changed, 1457 insertions(+), 600 deletions(-)
 create mode 100644 include/hw/intc/exynos4210_combiner.h
 create mode 100644 include/hw/intc/exynos4210_gic.h
 create mode 100644 include/hw/misc/xlnx-versal-crl.h
 create mode 100644 include/hw/timer/cadence_ttc.h
 create mode 100644 hw/misc/xlnx-versal-crl.c

It's not possible to provide the guest with the Security extensions
(TrustZone) when using KVM or HVF, because the hardware
virtualization extensions don't permit running EL3 guest code.
However, we weren't checking for this combination, with the result
that QEMU would assert if you tried it:

$ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none
Unexpected error in object_property_find_err() at ../../qom/object.c:1304:
qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found
Aborted

Check for this combination of options and report an error, in the
same way we already do for attempts to give a KVM or HVF guest the
Virtualization or MTE extensions. Now we will report:

qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404155301.566542-1-peter.maydell@linaro.org
---
 hw/arm/virt.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
         exit(1);
     }
 
+    if (vms->secure && (kvm_enabled() || hvf_enabled())) {
+        error_report("mach-virt: %s does not support providing "
+                     "Security extensions (TrustZone) to the guest CPU",
+                     kvm_enabled() ? "KVM" : "HVF");
+        exit(1);
+    }
+
     if (vms->virt && (kvm_enabled() || hvf_enabled())) {
         error_report("mach-virt: %s does not support providing "
                      "Virtualization extensions to the guest CPU",
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Break out header file to allow embedding of the the TTC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++
 hw/timer/cadence_ttc.c         | 32 ++------------------
 2 files changed, 56 insertions(+), 30 deletions(-)
 create mode 100644 include/hw/timer/cadence_ttc.h

diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/timer/cadence_ttc.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Xilinx Zynq cadence TTC model
+ *
+ * Copyright (c) 2011 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written By Haibing Ma
+ *            M. Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef HW_TIMER_CADENCE_TTC_H
+#define HW_TIMER_CADENCE_TTC_H
+
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+
+typedef struct {
+    QEMUTimer *timer;
+    int freq;
+
+    uint32_t reg_clock;
+    uint32_t reg_count;
+    uint32_t reg_value;
+    uint16_t reg_interval;
+    uint16_t reg_match[3];
+    uint32_t reg_intr;
+    uint32_t reg_intr_en;
+    uint32_t reg_event_ctrl;
+    uint32_t reg_event;
+
+    uint64_t cpu_time;
+    unsigned int cpu_time_valid;
+
+    qemu_irq irq;
+} CadenceTimerState;
+
+#define TYPE_CADENCE_TTC "cadence_ttc"
+OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
+
+struct CadenceTTCState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+    CadenceTimerState timer[3];
+};
+
+#endif
diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/timer/cadence_ttc.c
+++ b/hw/timer/cadence_ttc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/timer.h"
 #include "qom/object.h"
 
+#include "hw/timer/cadence_ttc.h"
+
 #ifdef CADENCE_TTC_ERR_DEBUG
 #define DB_PRINT(...) do { \
     fprintf(stderr,  ": %s: ", __func__); \
@@ -XXX,XX +XXX,XX @@
 #define CLOCK_CTRL_PS_EN    0x00000001
 #define CLOCK_CTRL_PS_V     0x0000001e
 
-typedef struct {
-    QEMUTimer *timer;
-    int freq;
-
-    uint32_t reg_clock;
-    uint32_t reg_count;
-    uint32_t reg_value;
-    uint16_t reg_interval;
-    uint16_t reg_match[3];
-    uint32_t reg_intr;
-    uint32_t reg_intr_en;
-    uint32_t reg_event_ctrl;
-    uint32_t reg_event;
-
-    uint64_t cpu_time;
-    unsigned int cpu_time_valid;
-
-    qemu_irq irq;
-} CadenceTimerState;
-
-#define TYPE_CADENCE_TTC "cadence_ttc"
-OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
-
-struct CadenceTTCState {
-    SysBusDevice parent_obj;
-
-    MemoryRegion iomem;
-    CadenceTimerState timer[3];
-};
-
 static void cadence_timer_update(CadenceTimerState *s)
 {
     qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Connect the 4 TTC timers on the ZynqMP.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-zynqmp.h |  4 ++++
 hw/arm/xlnx-zynqmp.c         | 22 ++++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/or-irq.h"
 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
 #include "hw/misc/xlnx-zynqmp-crf.h"
+#include "hw/timer/cadence_ttc.h"
 
 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
                                   XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
 
+#define XLNX_ZYNQMP_NUM_TTC 4
+
 /*
  * Unimplemented mmio regions needed to boot some images.
  */
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
     qemu_or_irq qspi_irq_orgate;
     XlnxZynqMPAPUCtrl apu_ctrl;
     XlnxZynqMPCRF crf;
+    CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
 
     char *boot_cpu;
     ARMCPU *boot_cpu_ptr;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -XXX,XX +XXX,XX @@
 #define APU_ADDR            0xfd5c0000
 #define APU_IRQ             153
 
+#define TTC0_ADDR           0xFF110000
+#define TTC0_IRQ            36
+
 #define IPI_ADDR            0xFF300000
 #define IPI_IRQ             64
 
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
     sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
 }
 
+static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
+{
+    SysBusDevice *sbd;
+    int i, irq;
+
+    for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
+        object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
+                                TYPE_CADENCE_TTC);
+        sbd = SYS_BUS_DEVICE(&s->ttc[i]);
+
+        sysbus_realize(sbd, &error_fatal);
+        sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
+        for (irq = 0; irq < 3; irq++) {
+            sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
+        }
+    }
+}
+
 static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
 {
     static const struct UnimpInfo {
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
     xlnx_zynqmp_create_efuse(s, gic_spi);
     xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
     xlnx_zynqmp_create_crf(s, gic_spi);
+    xlnx_zynqmp_create_ttc(s, gic_spi);
     xlnx_zynqmp_create_unimp_mmio(s);
 
     for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Create an APU CPU Cluster. This is in preparation to add the RPU.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h | 2 ++
 hw/arm/xlnx-versal.c         | 9 ++++++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/sysbus.h"
 #include "hw/arm/boot.h"
+#include "hw/cpu/cluster.h"
 #include "hw/or-irq.h"
 #include "hw/sd/sdhci.h"
 #include "hw/intc/arm_gicv3.h"
@@ -XXX,XX +XXX,XX @@ struct Versal {
     struct {
         struct {
             MemoryRegion mr;
+            CPUClusterState cluster;
             ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
             GICv3State gic;
         } apu;
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
 {
     int i;
 
+    object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster,
+                            TYPE_CPU_CLUSTER);
+    qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0);
+
     for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
         Object *obj;
 
-        object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
+        object_initialize_child(OBJECT(&s->fpd.apu.cluster),
+                                "apu-cpu[*]", &s->fpd.apu.cpu[i],
                                 XLNX_VERSAL_ACPU_TYPE);
         obj = OBJECT(&s->fpd.apu.cpu[i]);
         if (i) {
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
                                  &error_abort);
         qdev_realize(DEVICE(obj), NULL, &error_fatal);
     }
+
+    qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal);
 }
 
 static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit)
subsystem.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h | 10 ++++++++++
 hw/arm/xlnx-versal-virt.c    |  6 +++---
 hw/arm/xlnx-versal.c         | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 49 insertions(+), 3 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
 
 #define XLNX_VERSAL_NR_ACPUS   2
+#define XLNX_VERSAL_NR_RCPUS   2
 #define XLNX_VERSAL_NR_UARTS   2
 #define XLNX_VERSAL_NR_GEMS    2
 #define XLNX_VERSAL_NR_ADMAS   8
@@ -XXX,XX +XXX,XX @@ struct Versal {
             VersalUsb2 usb;
         } iou;
 
+        /* Real-time Processing Unit.  */
+        struct {
+            MemoryRegion mr;
+            MemoryRegion mr_ps_alias;
+
+            CPUClusterState cluster;
+            ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
+        } rpu;
+
         struct {
             qemu_or_irq irq_orgate;
             XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -XXX,XX +XXX,XX @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
 
     mc->desc = "Xilinx Versal Virtual development board";
     mc->init = versal_virt_init;
-    mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
-    mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
-    mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
+    mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
+    mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
+    mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
     mc->no_cdrom = true;
     mc->default_ram_id = "ddr";
 }
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 
 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
+#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
 #define GEM_REVISION        0x40070106
 
 #define VERSAL_NUM_PMC_APB_IRQS 3
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
     }
 }
 
+static void versal_create_rpu_cpus(Versal *s)
+{
+    int i;
+
+    object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster,
+                            TYPE_CPU_CLUSTER);
+    qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1);
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
+        Object *obj;
+
+        object_initialize_child(OBJECT(&s->lpd.rpu.cluster),
+                                "rpu-cpu[*]", &s->lpd.rpu.cpu[i],
+                                XLNX_VERSAL_RCPU_TYPE);
+        obj = OBJECT(&s->lpd.rpu.cpu[i]);
+        object_property_set_bool(obj, "start-powered-off", true,
+                                 &error_abort);
+
+        object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort);
+        object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu),
+                                &error_abort);
+        object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr),
+                                 &error_abort);
+        qdev_realize(DEVICE(obj), NULL, &error_fatal);
+    }
+
+    qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal);
+}
+
 static void versal_create_uarts(Versal *s, qemu_irq *pic)
 {
     int i;
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
 
     versal_create_apu_cpus(s);
     versal_create_apu_gic(s, pic);
+    versal_create_rpu_cpus(s);
     versal_create_uarts(s, pic);
     versal_create_usbs(s, pic);
     versal_create_gems(s, pic);
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
 
     memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
     memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
+    memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0,
+                                        &s->lpd.rpu.mr_ps_alias, 0);
 }
 
 static void versal_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void versal_init(Object *obj)
     Versal *s = XLNX_VERSAL(obj);
 
     memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
+    memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX);
     memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
+    memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s),
+                             "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX);
 }
 
 static Property versal_properties[] = {
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Add a model of the Xilinx Versal CRL.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++
 hw/misc/xlnx-versal-crl.c         | 421 ++++++++++++++++++++++++++++++
 hw/misc/meson.build               |   1 +
 3 files changed, 657 insertions(+)
 create mode 100644 include/hw/misc/xlnx-versal-crl.h
 create mode 100644 hw/misc/xlnx-versal-crl.c

diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/xlnx-versal-crl.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU model of the Clock-Reset-LPD (CRL).
+ *
+ * Copyright (c) 2022 Xilinx Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ */
+#ifndef HW_MISC_XLNX_VERSAL_CRL_H
+#define HW_MISC_XLNX_VERSAL_CRL_H
+
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "target/arm/cpu.h"
+
+#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl"
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
+
+REG32(ERR_CTRL, 0x0)
+    FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
+REG32(IR_STATUS, 0x4)
+    FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_MASK, 0x8)
+    FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_ENABLE, 0xc)
+    FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
+REG32(IR_DISABLE, 0x10)
+    FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
+REG32(WPROT, 0x1c)
+    FIELD(WPROT, ACTIVE, 0, 1)
+REG32(PLL_CLK_OTHER_DMN, 0x20)
+    FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
+REG32(RPLL_CTRL, 0x40)
+    FIELD(RPLL_CTRL, POST_SRC, 24, 3)
+    FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
+    FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2)
+    FIELD(RPLL_CTRL, FBDIV, 8, 8)
+    FIELD(RPLL_CTRL, BYPASS, 3, 1)
+    FIELD(RPLL_CTRL, RESET, 0, 1)
+REG32(RPLL_CFG, 0x44)
+    FIELD(RPLL_CFG, LOCK_DLY, 25, 7)
+    FIELD(RPLL_CFG, LOCK_CNT, 13, 10)
+    FIELD(RPLL_CFG, LFHF, 10, 2)
+    FIELD(RPLL_CFG, CP, 5, 4)
+    FIELD(RPLL_CFG, RES, 0, 4)
+REG32(RPLL_FRAC_CFG, 0x48)
+    FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1)
+    FIELD(RPLL_FRAC_CFG, SEED, 22, 3)
+    FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1)
+    FIELD(RPLL_FRAC_CFG, ORDER, 18, 1)
+    FIELD(RPLL_FRAC_CFG, DATA, 0, 16)
+REG32(PLL_STATUS, 0x50)
+    FIELD(PLL_STATUS, RPLL_STABLE, 2, 1)
+    FIELD(PLL_STATUS, RPLL_LOCK, 0, 1)
+REG32(RPLL_TO_XPD_CTRL, 0x100)
+    FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1)
+    FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
+REG32(LPD_TOP_SWITCH_CTRL, 0x104)
+    FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
+    FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1)
+    FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
+    FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
+REG32(LPD_LSBUS_CTRL, 0x108)
+    FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1)
+    FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10)
+    FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3)
+REG32(CPU_R5_CTRL, 0x10c)
+    FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1)
+    FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1)
+    FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1)
+    FIELD(CPU_R5_CTRL, CLKACT, 25, 1)
+    FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10)
+    FIELD(CPU_R5_CTRL, SRCSEL, 0, 3)
+REG32(IOU_SWITCH_CTRL, 0x114)
+    FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1)
+    FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10)
+    FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3)
+REG32(GEM0_REF_CTRL, 0x118)
+    FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1)
+    FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1)
+    FIELD(GEM0_REF_CTRL, CLKACT, 25, 1)
+    FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3)
+REG32(GEM1_REF_CTRL, 0x11c)
+    FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1)
+    FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1)
+    FIELD(GEM1_REF_CTRL, CLKACT, 25, 1)
+    FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3)
+REG32(GEM_TSU_REF_CTRL, 0x120)
+    FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1)
+    FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3)
+REG32(USB0_BUS_REF_CTRL, 0x124)
+    FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1)
+    FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3)
+REG32(UART0_REF_CTRL, 0x128)
+    FIELD(UART0_REF_CTRL, CLKACT, 25, 1)
+    FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(UART0_REF_CTRL, SRCSEL, 0, 3)
+REG32(UART1_REF_CTRL, 0x12c)
+    FIELD(UART1_REF_CTRL, CLKACT, 25, 1)
+    FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(UART1_REF_CTRL, SRCSEL, 0, 3)
+REG32(SPI0_REF_CTRL, 0x130)
+    FIELD(SPI0_REF_CTRL, CLKACT, 25, 1)
+    FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3)
+REG32(SPI1_REF_CTRL, 0x134)
+    FIELD(SPI1_REF_CTRL, CLKACT, 25, 1)
+    FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3)
+REG32(CAN0_REF_CTRL, 0x138)
+    FIELD(CAN0_REF_CTRL, CLKACT, 25, 1)
+    FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3)
+REG32(CAN1_REF_CTRL, 0x13c)
+    FIELD(CAN1_REF_CTRL, CLKACT, 25, 1)
+    FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3)
+REG32(I2C0_REF_CTRL, 0x140)
+    FIELD(I2C0_REF_CTRL, CLKACT, 25, 1)
+    FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3)
+REG32(I2C1_REF_CTRL, 0x144)
+    FIELD(I2C1_REF_CTRL, CLKACT, 25, 1)
+    FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3)
+REG32(DBG_LPD_CTRL, 0x148)
+    FIELD(DBG_LPD_CTRL, CLKACT, 25, 1)
+    FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10)
+    FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3)
+REG32(TIMESTAMP_REF_CTRL, 0x14c)
+    FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
+    FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
+REG32(CRL_SAFETY_CHK, 0x150)
+REG32(PSM_REF_CTRL, 0x154)
+    FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(PSM_REF_CTRL, SRCSEL, 0, 3)
+REG32(DBG_TSTMP_CTRL, 0x158)
+    FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1)
+    FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10)
+    FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
+REG32(CPM_TOPSW_REF_CTRL, 0x15c)
+    FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1)
+    FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3)
+REG32(USB3_DUAL_REF_CTRL, 0x160)
+    FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1)
+    FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10)
+    FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3)
+REG32(RST_CPU_R5, 0x300)
+    FIELD(RST_CPU_R5, RESET_PGE, 4, 1)
+    FIELD(RST_CPU_R5, RESET_AMBA, 2, 1)
+    FIELD(RST_CPU_R5, RESET_CPU1, 1, 1)
+    FIELD(RST_CPU_R5, RESET_CPU0, 0, 1)
+REG32(RST_ADMA, 0x304)
+    FIELD(RST_ADMA, RESET, 0, 1)
+REG32(RST_GEM0, 0x308)
+    FIELD(RST_GEM0, RESET, 0, 1)
+REG32(RST_GEM1, 0x30c)
+    FIELD(RST_GEM1, RESET, 0, 1)
+REG32(RST_SPARE, 0x310)
+    FIELD(RST_SPARE, RESET, 0, 1)
+REG32(RST_USB0, 0x314)
+    FIELD(RST_USB0, RESET, 0, 1)
+REG32(RST_UART0, 0x318)
+    FIELD(RST_UART0, RESET, 0, 1)
+REG32(RST_UART1, 0x31c)
+    FIELD(RST_UART1, RESET, 0, 1)
+REG32(RST_SPI0, 0x320)
+    FIELD(RST_SPI0, RESET, 0, 1)
+REG32(RST_SPI1, 0x324)
+    FIELD(RST_SPI1, RESET, 0, 1)
+REG32(RST_CAN0, 0x328)
+    FIELD(RST_CAN0, RESET, 0, 1)
+REG32(RST_CAN1, 0x32c)
+    FIELD(RST_CAN1, RESET, 0, 1)
+REG32(RST_I2C0, 0x330)
+    FIELD(RST_I2C0, RESET, 0, 1)
+REG32(RST_I2C1, 0x334)
+    FIELD(RST_I2C1, RESET, 0, 1)
+REG32(RST_DBG_LPD, 0x338)
+    FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1)
+    FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1)
+    FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1)
+    FIELD(RST_DBG_LPD, RESET, 0, 1)
+REG32(RST_GPIO, 0x33c)
+    FIELD(RST_GPIO, RESET, 0, 1)
+REG32(RST_TTC, 0x344)
+    FIELD(RST_TTC, TTC3_RESET, 3, 1)
+    FIELD(RST_TTC, TTC2_RESET, 2, 1)
+    FIELD(RST_TTC, TTC1_RESET, 1, 1)
+    FIELD(RST_TTC, TTC0_RESET, 0, 1)
+REG32(RST_TIMESTAMP, 0x348)
+    FIELD(RST_TIMESTAMP, RESET, 0, 1)
+REG32(RST_SWDT, 0x34c)
+    FIELD(RST_SWDT, RESET, 0, 1)
+REG32(RST_OCM, 0x350)
+    FIELD(RST_OCM, RESET, 0, 1)
+REG32(RST_IPI, 0x354)
+    FIELD(RST_IPI, RESET, 0, 1)
+REG32(RST_SYSMON, 0x358)
+    FIELD(RST_SYSMON, SEQ_RST, 1, 1)
+    FIELD(RST_SYSMON, CFG_RST, 0, 1)
+REG32(RST_FPD, 0x360)
+    FIELD(RST_FPD, SRST, 1, 1)
+    FIELD(RST_FPD, POR, 0, 1)
+REG32(PSM_RST_MODE, 0x370)
+    FIELD(PSM_RST_MODE, WAKEUP, 2, 1)
+    FIELD(PSM_RST_MODE, RST_MODE, 0, 2)
+
+#define CRL_R_MAX (R_PSM_RST_MODE + 1)
+
+#define RPU_MAX_CPU 2
+
+struct XlnxVersalCRL {
+    SysBusDevice parent_obj;
+    qemu_irq irq;
+
+    struct {
+        ARMCPU *cpu_r5[RPU_MAX_CPU];
+        DeviceState *adma[8];
+        DeviceState *uart[2];
+        DeviceState *gem[2];
+        DeviceState *usb;
+    } cfg;
+
+    RegisterInfoArray *reg_array;
+    uint32_t regs[CRL_R_MAX];
+    RegisterInfo regs_info[CRL_R_MAX];
+};
+#endif
diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/xlnx-versal-crl.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * QEMU model of the Clock-Reset-LPD (CRL).
+ *
+ * Copyright (c) 2022 Advanced Micro Devices, Inc.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * Written by Edgar E. Iglesias <edgar.iglesias@amd.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/bitops.h"
+#include "migration/vmstate.h"
+#include "hw/qdev-properties.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/register.h"
+#include "hw/resettable.h"
+
+#include "target/arm/arm-powerctl.h"
+#include "hw/misc/xlnx-versal-crl.h"
+
+#ifndef XLNX_VERSAL_CRL_ERR_DEBUG
+#define XLNX_VERSAL_CRL_ERR_DEBUG 0
+#endif
+
+static void crl_update_irq(XlnxVersalCRL *s)
+{
+    bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
+    qemu_set_irq(s->irq, pending);
+}
+
+static void crl_status_postw(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+    crl_update_irq(s);
+}
+
+static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+    uint32_t val = val64;
+
+    s->regs[R_IR_MASK] &= ~val;
+    crl_update_irq(s);
+    return 0;
+}
+
+static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+    uint32_t val = val64;
+
+    s->regs[R_IR_MASK] |= val;
+    crl_update_irq(s);
+    return 0;
+}
+
+static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev,
+                          bool rst_old, bool rst_new)
+{
+    device_cold_reset(dev);
+}
+
+static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu,
+                          bool rst_old, bool rst_new)
+{
+    if (rst_new) {
+        arm_set_cpu_off(armcpu->mp_affinity);
+    } else {
+        arm_set_cpu_on_and_reset(armcpu->mp_affinity);
+    }
+}
+
+#define REGFIELD_RESET(type, s, reg, f, new_val, dev) {     \
+    bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f);       \
+    bool new_f = FIELD_EX32(new_val, reg, f);               \
+                                                            \
+    /* Detect edges.  */                                    \
+    if (dev && old_f != new_f) {                            \
+        crl_reset_ ## type(s, dev, old_f, new_f);           \
+    }                                                       \
+}
+
+static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]);
+    REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]);
+    return val64;
+}
+
+static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+    int i;
+
+    /* A single register fans out to all ADMA reset inputs.  */
+    for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) {
+        REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]);
+    }
+    return val64;
+}
+
+static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]);
+    return val64;
+}
+
+static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]);
+    return val64;
+}
+
+static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]);
+    return val64;
+}
+
+static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]);
+    return val64;
+}
+
+static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
+
+    REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb);
+    return val64;
+}
+
+static const RegisterAccessInfo crl_regs_info[] = {
+    {   .name = "ERR_CTRL",  .addr = A_ERR_CTRL,
+    },{ .name = "IR_STATUS",  .addr = A_IR_STATUS,
+        .w1c = 0x1,
+        .post_write = crl_status_postw,
+    },{ .name = "IR_MASK",  .addr = A_IR_MASK,
+        .reset = 0x1,
+        .ro = 0x1,
+    },{ .name = "IR_ENABLE",  .addr = A_IR_ENABLE,
+        .pre_write = crl_enable_prew,
+    },{ .name = "IR_DISABLE",  .addr = A_IR_DISABLE,
+        .pre_write = crl_disable_prew,
+    },{ .name = "WPROT",  .addr = A_WPROT,
+    },{ .name = "PLL_CLK_OTHER_DMN",  .addr = A_PLL_CLK_OTHER_DMN,
+        .reset = 0x1,
+        .rsvd = 0xe,
+    },{ .name = "RPLL_CTRL",  .addr = A_RPLL_CTRL,
+        .reset = 0x24809,
+        .rsvd = 0xf88c00f6,
+    },{ .name = "RPLL_CFG",  .addr = A_RPLL_CFG,
+        .reset = 0x2000000,
+        .rsvd = 0x1801210,
+    },{ .name = "RPLL_FRAC_CFG",  .addr = A_RPLL_FRAC_CFG,
+        .rsvd = 0x7e330000,
+    },{ .name = "PLL_STATUS",  .addr = A_PLL_STATUS,
+        .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
+                 R_PLL_STATUS_RPLL_LOCK_MASK,
+        .rsvd = 0xfa,
+        .ro = 0x5,
+    },{ .name = "RPLL_TO_XPD_CTRL",  .addr = A_RPLL_TO_XPD_CTRL,
+        .reset = 0x2000100,
+        .rsvd = 0xfdfc00ff,
+    },{ .name = "LPD_TOP_SWITCH_CTRL",  .addr = A_LPD_TOP_SWITCH_CTRL,
+        .reset = 0x6000300,
+        .rsvd = 0xf9fc00f8,
+    },{ .name = "LPD_LSBUS_CTRL",  .addr = A_LPD_LSBUS_CTRL,
+        .reset = 0x2000800,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "CPU_R5_CTRL",  .addr = A_CPU_R5_CTRL,
+        .reset = 0xe000300,
+        .rsvd = 0xe1fc00f8,
+    },{ .name = "IOU_SWITCH_CTRL",  .addr = A_IOU_SWITCH_CTRL,
+        .reset = 0x2000500,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "GEM0_REF_CTRL",  .addr = A_GEM0_REF_CTRL,
+        .reset = 0xe000a00,
+        .rsvd = 0xf1fc00f8,
+    },{ .name = "GEM1_REF_CTRL",  .addr = A_GEM1_REF_CTRL,
+        .reset = 0xe000a00,
+        .rsvd = 0xf1fc00f8,
+    },{ .name = "GEM_TSU_REF_CTRL",  .addr = A_GEM_TSU_REF_CTRL,
+        .reset = 0x300,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "USB0_BUS_REF_CTRL",  .addr = A_USB0_BUS_REF_CTRL,
+        .reset = 0x2001900,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "UART0_REF_CTRL",  .addr = A_UART0_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "UART1_REF_CTRL",  .addr = A_UART1_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "SPI0_REF_CTRL",  .addr = A_SPI0_REF_CTRL,
+        .reset = 0x600,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "SPI1_REF_CTRL",  .addr = A_SPI1_REF_CTRL,
+        .reset = 0x600,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "CAN0_REF_CTRL",  .addr = A_CAN0_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "CAN1_REF_CTRL",  .addr = A_CAN1_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "I2C0_REF_CTRL",  .addr = A_I2C0_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "I2C1_REF_CTRL",  .addr = A_I2C1_REF_CTRL,
+        .reset = 0xc00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "DBG_LPD_CTRL",  .addr = A_DBG_LPD_CTRL,
+        .reset = 0x300,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "TIMESTAMP_REF_CTRL",  .addr = A_TIMESTAMP_REF_CTRL,
+        .reset = 0x2000c00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "CRL_SAFETY_CHK",  .addr = A_CRL_SAFETY_CHK,
+    },{ .name = "PSM_REF_CTRL",  .addr = A_PSM_REF_CTRL,
+        .reset = 0xf04,
+        .rsvd = 0xfffc00f8,
+    },{ .name = "DBG_TSTMP_CTRL",  .addr = A_DBG_TSTMP_CTRL,
+        .reset = 0x300,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "CPM_TOPSW_REF_CTRL",  .addr = A_CPM_TOPSW_REF_CTRL,
+        .reset = 0x300,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "USB3_DUAL_REF_CTRL",  .addr = A_USB3_DUAL_REF_CTRL,
+        .reset = 0x3c00,
+        .rsvd = 0xfdfc00f8,
+    },{ .name = "RST_CPU_R5",  .addr = A_RST_CPU_R5,
+        .reset = 0x17,
+        .rsvd = 0x8,
+        .pre_write = crl_rst_r5_prew,
+    },{ .name = "RST_ADMA",  .addr = A_RST_ADMA,
+        .reset = 0x1,
+        .pre_write = crl_rst_adma_prew,
+    },{ .name = "RST_GEM0",  .addr = A_RST_GEM0,
+        .reset = 0x1,
+        .pre_write = crl_rst_gem0_prew,
+    },{ .name = "RST_GEM1",  .addr = A_RST_GEM1,
+        .reset = 0x1,
+        .pre_write = crl_rst_gem1_prew,
+    },{ .name = "RST_SPARE",  .addr = A_RST_SPARE,
+        .reset = 0x1,
+    },{ .name = "RST_USB0",  .addr = A_RST_USB0,
+        .reset = 0x1,
+        .pre_write = crl_rst_usb_prew,
+    },{ .name = "RST_UART0",  .addr = A_RST_UART0,
+        .reset = 0x1,
+        .pre_write = crl_rst_uart0_prew,
+    },{ .name = "RST_UART1",  .addr = A_RST_UART1,
+        .reset = 0x1,
+        .pre_write = crl_rst_uart1_prew,
+    },{ .name = "RST_SPI0",  .addr = A_RST_SPI0,
+        .reset = 0x1,
+    },{ .name = "RST_SPI1",  .addr = A_RST_SPI1,
+        .reset = 0x1,
+    },{ .name = "RST_CAN0",  .addr = A_RST_CAN0,
+        .reset = 0x1,
+    },{ .name = "RST_CAN1",  .addr = A_RST_CAN1,
+        .reset = 0x1,
+    },{ .name = "RST_I2C0",  .addr = A_RST_I2C0,
+        .reset = 0x1,
+    },{ .name = "RST_I2C1",  .addr = A_RST_I2C1,
+        .reset = 0x1,
+    },{ .name = "RST_DBG_LPD",  .addr = A_RST_DBG_LPD,
+        .reset = 0x33,
+        .rsvd = 0xcc,
+    },{ .name = "RST_GPIO",  .addr = A_RST_GPIO,
+        .reset = 0x1,
+    },{ .name = "RST_TTC",  .addr = A_RST_TTC,
+        .reset = 0xf,
+    },{ .name = "RST_TIMESTAMP",  .addr = A_RST_TIMESTAMP,
+        .reset = 0x1,
+    },{ .name = "RST_SWDT",  .addr = A_RST_SWDT,
+        .reset = 0x1,
+    },{ .name = "RST_OCM",  .addr = A_RST_OCM,
+    },{ .name = "RST_IPI",  .addr = A_RST_IPI,
+    },{ .name = "RST_FPD",  .addr = A_RST_FPD,
+        .reset = 0x3,
+    },{ .name = "PSM_RST_MODE",  .addr = A_PSM_RST_MODE,
+        .reset = 0x1,
+        .rsvd = 0xf8,
+    }
+};
+
+static void crl_reset_enter(Object *obj, ResetType type)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+    unsigned int i;
+
+    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+        register_reset(&s->regs_info[i]);
+    }
+}
+
+static void crl_reset_hold(Object *obj)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+
+    crl_update_irq(s);
+}
+
+static const MemoryRegionOps crl_ops = {
+    .read = register_read_memory,
+    .write = register_write_memory,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+static void crl_init(Object *obj)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    int i;
+
+    s->reg_array =
+        register_init_block32(DEVICE(obj), crl_regs_info,
+                              ARRAY_SIZE(crl_regs_info),
+                              s->regs_info, s->regs,
+                              &crl_ops,
+                              XLNX_VERSAL_CRL_ERR_DEBUG,
+                              CRL_R_MAX * 4);
+    sysbus_init_mmio(sbd, &s->reg_array->mem);
+    sysbus_init_irq(sbd, &s->irq);
+
+    for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) {
+        object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU,
+                                 (Object **)&s->cfg.cpu_r5[i],
+                                 qdev_prop_allow_set_link_before_realize,
+                                 OBJ_PROP_LINK_STRONG);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) {
+        object_property_add_link(obj, "adma[*]", TYPE_DEVICE,
+                                 (Object **)&s->cfg.adma[i],
+                                 qdev_prop_allow_set_link_before_realize,
+                                 OBJ_PROP_LINK_STRONG);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) {
+        object_property_add_link(obj, "uart[*]", TYPE_DEVICE,
+                                 (Object **)&s->cfg.uart[i],
+                                 qdev_prop_allow_set_link_before_realize,
+                                 OBJ_PROP_LINK_STRONG);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) {
+        object_property_add_link(obj, "gem[*]", TYPE_DEVICE,
+                                 (Object **)&s->cfg.gem[i],
+                                 qdev_prop_allow_set_link_before_realize,
+                                 OBJ_PROP_LINK_STRONG);
+    }
+
+    object_property_add_link(obj, "usb", TYPE_DEVICE,
+                             (Object **)&s->cfg.gem[i],
+                             qdev_prop_allow_set_link_before_realize,
+                             OBJ_PROP_LINK_STRONG);
+}
+
+static void crl_finalize(Object *obj)
+{
+    XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
+    register_finalize_block(s->reg_array);
+}
+
+static const VMStateDescription vmstate_crl = {
+    .name = TYPE_XLNX_VERSAL_CRL,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX),
+        VMSTATE_END_OF_LIST(),
+    }
+};
+
+static void crl_class_init(ObjectClass *klass, void *data)
+{
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->vmsd = &vmstate_crl;
+
+    rc->phases.enter = crl_reset_enter;
+    rc->phases.hold = crl_reset_hold;
+}
+
+static const TypeInfo crl_info = {
+    .name          = TYPE_XLNX_VERSAL_CRL,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(XlnxVersalCRL),
+    .class_init    = crl_class_init,
+    .instance_init = crl_init,
+    .instance_finalize = crl_finalize,
+};
+
+static void crl_register_types(void)
+{
+    type_register_static(&crl_info);
+}
+
+type_init(crl_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
 softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
 specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
 specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
+specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
 softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
   'xlnx-versal-xramc.c',
   'xlnx-versal-pmc-iou-slcr.c',
-- 
2.25.1

From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>

Connect the CRL (Clock Reset LPD) to the Versal SoC.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/xlnx-versal.h |  4 +++
 hw/arm/xlnx-versal.c         | 54 ++++++++++++++++++++++++++++++++++--
 2 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/nvram/xlnx-versal-efuse.h"
 #include "hw/ssi/xlnx-versal-ospi.h"
 #include "hw/dma/xlnx_csu_dma.h"
+#include "hw/misc/xlnx-versal-crl.h"
 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
@@ -XXX,XX +XXX,XX @@ struct Versal {
             qemu_or_irq irq_orgate;
             XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
         } xram;
+
+        XlnxVersalCRL crl;
     } lpd;
 
     /* The Platform Management Controller subsystem.  */
@@ -XXX,XX +XXX,XX @@ struct Versal {
 #define VERSAL_TIMER_NS_EL1_IRQ     14
 #define VERSAL_TIMER_NS_EL2_IRQ     10
 
+#define VERSAL_CRL_IRQ             10
 #define VERSAL_UART0_IRQ_0         18
 #define VERSAL_UART1_IRQ_0         19
 #define VERSAL_USB0_IRQ_0          22
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@ static void versal_create_ospi(Versal *s, qemu_irq *pic)
     qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
 }
 
+static void versal_create_crl(Versal *s, qemu_irq *pic)
+{
+    SysBusDevice *sbd;
+    int i;
+
+    object_initialize_child(OBJECT(s), "crl", &s->lpd.crl,
+                            TYPE_XLNX_VERSAL_CRL);
+    sbd = SYS_BUS_DEVICE(&s->lpd.crl);
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
+        g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i);
+
+        object_property_set_link(OBJECT(&s->lpd.crl),
+                                 name, OBJECT(&s->lpd.rpu.cpu[i]),
+                                 &error_abort);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
+        g_autofree gchar *name = g_strdup_printf("gem[%d]", i);
+
+        object_property_set_link(OBJECT(&s->lpd.crl),
+                                 name, OBJECT(&s->lpd.iou.gem[i]),
+                                 &error_abort);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
+        g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
+
+        object_property_set_link(OBJECT(&s->lpd.crl),
+                                 name, OBJECT(&s->lpd.iou.adma[i]),
+                                 &error_abort);
+    }
+
+    for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
+        g_autofree gchar *name = g_strdup_printf("uart[%d]", i);
+
+        object_property_set_link(OBJECT(&s->lpd.crl),
+                                 name, OBJECT(&s->lpd.iou.uart[i]),
+                                 &error_abort);
+    }
+
+    object_property_set_link(OBJECT(&s->lpd.crl),
+                             "usb", OBJECT(&s->lpd.iou.usb),
+                             &error_abort);
+
+    sysbus_realize(sbd, &error_fatal);
+    memory_region_add_subregion(&s->mr_ps, MM_CRL,
+                                sysbus_mmio_get_region(sbd, 0));
+    sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]);
+}
+
 /* This takes the board allocated linear DDR memory and creates aliases
  * for each split DDR range/aperture on the Versal address map.
  */
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
 
     versal_unimp_area(s, "psm", &s->mr_ps,
                         MM_PSM_START, MM_PSM_END - MM_PSM_START);
-    versal_unimp_area(s, "crl", &s->mr_ps,
-                        MM_CRL, MM_CRL_SIZE);
     versal_unimp_area(s, "crf", &s->mr_ps,
                         MM_FPD_CRF, MM_FPD_CRF_SIZE);
     versal_unimp_area(s, "apu", &s->mr_ps,
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_efuse(s, pic);
     versal_create_pmc_iou_slcr(s, pic);
     versal_create_ospi(s, pic);
+    versal_create_crl(s, pic);
     versal_map_ddr(s);
     versal_unimp(s);
 
-- 
2.25.1

The Exynos4210 SoC device currently uses a custom device
"exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ
line.  We have a standard TYPE_OR_IRQ device for this now, so use
that instead.

(This is a migration compatibility break, but that is OK for this
machine type.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-2-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  1 +
 hw/arm/exynos4210.c         | 31 ++++++++++++++++---------------
 2 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     MemoryRegion bootreg_mem;
     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
+    qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
 };
 
 #define TYPE_EXYNOS4210_SOC "exynos4210"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
 {
     Exynos4210State *s = EXYNOS4210_SOC(socdev);
     MemoryRegion *system_mem = get_system_memory();
-    qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
     SysBusDevice *busdev;
     DeviceState *dev, *uart[4], *pl330[3];
     int i, n;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
 
     /* IRQ Gate */
     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
-        dev = qdev_new("exynos4210.irq_gate");
-        qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
-        sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-        /* Get IRQ Gate input in gate_irq */
-        for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
-            gate_irq[i][n] = qdev_get_gpio_in(dev, n);
-        }
-        busdev = SYS_BUS_DEVICE(dev);
-
-        /* Connect IRQ Gate output to CPU's IRQ line */
-        sysbus_connect_irq(busdev, 0,
-                           qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
+        DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
+        object_property_set_int(OBJECT(orgate), "num-lines",
+                                EXYNOS4210_IRQ_GATE_NINPUTS,
+                                &error_abort);
+        qdev_realize(orgate, NULL, &error_abort);
+        qdev_connect_gpio_out(orgate, 0,
+                              qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
     }
 
     /* Private memory region and Internal GIC */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     sysbus_realize_and_unref(busdev, &error_fatal);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
-        sysbus_connect_irq(busdev, n, gate_irq[n][0]);
+        sysbus_connect_irq(busdev, n,
+                           qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
     }
     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
         s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     /* Map Distributer interface */
     sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
-        sysbus_connect_irq(busdev, n, gate_irq[n][1]);
+        sysbus_connect_irq(busdev, n,
+                           qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
     }
     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
         s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
         object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
         g_free(name);
     }
+
+    for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
+        g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
+        object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
+    }
 }
 
 static void exynos4210_class_init(ObjectClass *klass, void *data)
-- 
2.25.1

Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can
delete the device entirely.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220404154658.565020-3-peter.maydell@linaro.org
---
 hw/intc/exynos4210_gic.c | 107 ---------------------------------------
 1 file changed, 107 deletions(-)

diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_register_types(void)
 }
 
 type_init(exynos4210_gic_register_types)
-
-/* IRQ OR Gate struct.
- *
- * This device models an OR gate. There are n_in input qdev gpio lines and one
- * output sysbus IRQ line. The output IRQ level is formed as OR between all
- * gpio inputs.
- */
-
-#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE)
-
-struct Exynos4210IRQGateState {
-    SysBusDevice parent_obj;
-
-    uint32_t n_in;      /* inputs amount */
-    uint32_t *level;    /* input levels */
-    qemu_irq out;       /* output IRQ */
-};
-
-static Property exynos4210_irq_gate_properties[] = {
-    DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
-static const VMStateDescription vmstate_exynos4210_irq_gate = {
-    .name = "exynos4210.irq_gate",
-    .version_id = 2,
-    .minimum_version_id = 2,
-    .fields = (VMStateField[]) {
-        VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in),
-        VMSTATE_END_OF_LIST()
-    }
-};
-
-/* Process a change in IRQ input. */
-static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
-{
-    Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque;
-    uint32_t i;
-
-    assert(irq < s->n_in);
-
-    s->level[irq] = level;
-
-    for (i = 0; i < s->n_in; i++) {
-        if (s->level[i] >= 1) {
-            qemu_irq_raise(s->out);
-            return;
-        }
-    }
-
-    qemu_irq_lower(s->out);
-}
-
-static void exynos4210_irq_gate_reset(DeviceState *d)
-{
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);
-
-    memset(s->level, 0, s->n_in * sizeof(*s->level));
-}
-
-/*
- * IRQ Gate initialization.
- */
-static void exynos4210_irq_gate_init(Object *obj)
-{
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj);
-    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-
-    sysbus_init_irq(sbd, &s->out);
-}
-
-static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp)
-{
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);
-
-    /* Allocate general purpose input signals and connect a handler to each of
-     * them */
-    qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);
-
-    s->level = g_malloc0(s->n_in * sizeof(*s->level));
-}
-
-static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-
-    dc->reset = exynos4210_irq_gate_reset;
-    dc->vmsd = &vmstate_exynos4210_irq_gate;
-    device_class_set_props(dc, exynos4210_irq_gate_properties);
-    dc->realize = exynos4210_irq_gate_realize;
-}
-
-static const TypeInfo exynos4210_irq_gate_info = {
-    .name          = TYPE_EXYNOS4210_IRQ_GATE,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(Exynos4210IRQGateState),
-    .instance_init = exynos4210_irq_gate_init,
-    .class_init    = exynos4210_irq_gate_class_init,
-};
-
-static void exynos4210_irq_gate_register_types(void)
-{
-    type_register_static(&exynos4210_irq_gate_info);
-}
-
-type_init(exynos4210_irq_gate_register_types)
-- 
2.25.1

The exynos4210 SoC mostly creates its child devices as if it were
board code.  This includes the a9mpcore object.  Switch that to a
new-style "embedded in the state struct" creation, because in the
next commit we're going to want to refer to the object again further
down in the exynos4210_realize() function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-4-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  2 ++
 hw/arm/exynos4210.c         | 11 ++++++-----
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 
 #include "hw/or-irq.h"
 #include "hw/sysbus.h"
+#include "hw/cpu/a9mpcore.h"
 #include "target/arm/cpu-qom.h"
 #include "qom/object.h"
 
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+    A9MPPrivState a9mpcore;
 };
 
 #define TYPE_EXYNOS4210_SOC "exynos4210"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     }
 
     /* Private memory region and Internal GIC */
-    dev = qdev_new(TYPE_A9MPCORE_PRIV);
-    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
-    busdev = SYS_BUS_DEVICE(dev);
-    sysbus_realize_and_unref(busdev, &error_fatal);
+    qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
+    busdev = SYS_BUS_DEVICE(&s->a9mpcore);
+    sysbus_realize(busdev, &error_fatal);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
     for (n = 0; n < EXYNOS4210_NCPUS; n++) {
         sysbus_connect_irq(busdev, n,
                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
     }
     for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
-        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
+        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
     }
 
     /* Cache controller */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
         g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
         object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
     }
+
+    object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
 }
 
 static void exynos4210_class_init(ObjectClass *klass, void *data)
-- 
2.25.1

The only time we use the int_gic_irq[] array in the Exynos4210Irq
struct is in the exynos4210_realize() function: we initialize it with
the GPIO inputs of the a9mpcore device, and then a bit later on we
connect those to the outputs of the internal combiner.  Now that the
a9mpcore object is easily accessible as s->a9mpcore we can make the
connection directly from one device to the other without going via
this array.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-5-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h | 1 -
 hw/arm/exynos4210.c         | 6 ++----
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
-    qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
     qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
     qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 } Exynos4210Irq;
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
         sysbus_connect_irq(busdev, n,
                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
     }
-    for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
-        s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
-    }
 
     /* Cache controller */
     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     busdev = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(busdev, &error_fatal);
     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
-        sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
+        sysbus_connect_irq(busdev, n,
+                           qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
     }
     exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
-- 
2.25.1

The exynos4210 code currently has two very similar arrays of IRQs:

* board_irqs is a field of the Exynos4210Irq struct which is filled
   in by exynos4210_init_board_irqs() with the appropriate qemu_irqs
   for each IRQ the board/SoC can assert
 * irq_table is a set of qemu_irqs pointed to from the
   Exynos4210State struct.  It's allocated in exynos4210_init_irq,
   and the only behaviour these irqs have is that they pass on the
   level to the equivalent board_irqs[] irq

The extra indirection through irq_table is unnecessary, so coalesce
these into a single irq_table[] array as a direct field in
Exynos4210State which exynos4210_init_board_irqs() fills in.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-6-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  8 ++------
 hw/arm/exynos4210.c         |  6 +-----
 hw/intc/exynos4210_gic.c    | 32 ++++++++------------------------
 3 files changed, 11 insertions(+), 35 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
     qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
-    qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 } Exynos4210Irq;
 
 struct Exynos4210State {
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     /*< public >*/
     ARMCPU *cpu[EXYNOS4210_NCPUS];
     Exynos4210Irq irqs;
-    qemu_irq *irq_table;
+    qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 
     MemoryRegion chipid_mem;
     MemoryRegion iram_mem;
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
 void exynos4210_write_secondary(ARMCPU *cpu,
         const struct arm_boot_info *info);
 
-/* Initialize exynos4210 IRQ subsystem stub */
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
-
 /* Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
-void exynos4210_init_board_irqs(Exynos4210Irq *s);
+void exynos4210_init_board_irqs(Exynos4210State *s);
 
 /* Get IRQ number from exynos4210 IRQ subsystem stub.
  * To identify IRQ source use internal combiner group and bit number
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
     }
 
-    /*** IRQs ***/
-
-    s->irq_table = exynos4210_init_irq(&s->irqs);
-
     /* IRQ Gate */
     for (i = 0; i < EXYNOS4210_NCPUS; i++) {
         DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 
     /* Initialize board IRQs. */
-    exynos4210_init_board_irqs(&s->irqs);
+    exynos4210_init_board_irqs(s);
 
     /*** Memory ***/
 
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
 #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
 
-static void exynos4210_irq_handler(void *opaque, int irq, int level)
-{
-    Exynos4210Irq *s = (Exynos4210Irq *)opaque;
-
-    /* Bypass */
-    qemu_set_irq(s->board_irqs[irq], level);
-}
-
-/*
- * Initialize exynos4210 IRQ subsystem stub.
- */
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
-{
-    return qemu_allocate_irqs(exynos4210_irq_handler, s,
-            EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
-}
-
 /*
  * Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
  */
-void exynos4210_init_board_irqs(Exynos4210Irq *s)
+void exynos4210_init_board_irqs(Exynos4210State *s)
 {
     uint32_t grp, bit, irq_id, n;
+    Exynos4210Irq *is = &s->irqs;
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
@@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
             irq_id = EXT_GIC_ID_MCT_G1;
         }
         if (irq_id) {
-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
-                    s->ext_gic_irq[irq_id-32]);
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_gic_irq[irq_id - 32]);
         } else {
-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
-                    s->ext_combiner_irq[n]);
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_combiner_irq[n]);
         }
     }
     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
@@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
 
         if (irq_id) {
-            s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
-                    s->ext_gic_irq[irq_id-32]);
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_gic_irq[irq_id - 32]);
         }
     }
 }
-- 
2.25.1

The function exynos4210_init_board_irqs() currently lives in
exynos4210_gic.c, but it isn't really part of the exynos4210.gic
device -- it is a function that implements (some of) the wiring up of
interrupts between the SoC's GIC and combiner components.  This means
it fits better in exynos4210.c, which is the SoC-level code.  Move it
there. Similarly, exynos4210_git_irq() is used almost only in the
SoC-level code, so move it too.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-8-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |   4 -
 hw/arm/exynos4210.c         | 202 +++++++++++++++++++++++++++++++++++
 hw/intc/exynos4210_gic.c    | 204 ------------------------------------
 3 files changed, 202 insertions(+), 208 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
 void exynos4210_write_secondary(ARMCPU *cpu,
         const struct arm_boot_info *info);
 
-/* Initialize board IRQs.
- * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
-void exynos4210_init_board_irqs(Exynos4210State *s);
-
 /* Get IRQ number from exynos4210 IRQ subsystem stub.
  * To identify IRQ source use internal combiner group and bit number
  *  grp - group number
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 #define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
 #define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
 
+enum ExtGicId {
+    EXT_GIC_ID_MDMA_LCD0 = 66,
+    EXT_GIC_ID_PDMA0,
+    EXT_GIC_ID_PDMA1,
+    EXT_GIC_ID_TIMER0,
+    EXT_GIC_ID_TIMER1,
+    EXT_GIC_ID_TIMER2,
+    EXT_GIC_ID_TIMER3,
+    EXT_GIC_ID_TIMER4,
+    EXT_GIC_ID_MCT_L0,
+    EXT_GIC_ID_WDT,
+    EXT_GIC_ID_RTC_ALARM,
+    EXT_GIC_ID_RTC_TIC,
+    EXT_GIC_ID_GPIO_XB,
+    EXT_GIC_ID_GPIO_XA,
+    EXT_GIC_ID_MCT_L1,
+    EXT_GIC_ID_IEM_APC,
+    EXT_GIC_ID_IEM_IEC,
+    EXT_GIC_ID_NFC,
+    EXT_GIC_ID_UART0,
+    EXT_GIC_ID_UART1,
+    EXT_GIC_ID_UART2,
+    EXT_GIC_ID_UART3,
+    EXT_GIC_ID_UART4,
+    EXT_GIC_ID_MCT_G0,
+    EXT_GIC_ID_I2C0,
+    EXT_GIC_ID_I2C1,
+    EXT_GIC_ID_I2C2,
+    EXT_GIC_ID_I2C3,
+    EXT_GIC_ID_I2C4,
+    EXT_GIC_ID_I2C5,
+    EXT_GIC_ID_I2C6,
+    EXT_GIC_ID_I2C7,
+    EXT_GIC_ID_SPI0,
+    EXT_GIC_ID_SPI1,
+    EXT_GIC_ID_SPI2,
+    EXT_GIC_ID_MCT_G1,
+    EXT_GIC_ID_USB_HOST,
+    EXT_GIC_ID_USB_DEVICE,
+    EXT_GIC_ID_MODEMIF,
+    EXT_GIC_ID_HSMMC0,
+    EXT_GIC_ID_HSMMC1,
+    EXT_GIC_ID_HSMMC2,
+    EXT_GIC_ID_HSMMC3,
+    EXT_GIC_ID_SDMMC,
+    EXT_GIC_ID_MIPI_CSI_4LANE,
+    EXT_GIC_ID_MIPI_DSI_4LANE,
+    EXT_GIC_ID_MIPI_CSI_2LANE,
+    EXT_GIC_ID_MIPI_DSI_2LANE,
+    EXT_GIC_ID_ONENAND_AUDI,
+    EXT_GIC_ID_ROTATOR,
+    EXT_GIC_ID_FIMC0,
+    EXT_GIC_ID_FIMC1,
+    EXT_GIC_ID_FIMC2,
+    EXT_GIC_ID_FIMC3,
+    EXT_GIC_ID_JPEG,
+    EXT_GIC_ID_2D,
+    EXT_GIC_ID_PCIe,
+    EXT_GIC_ID_MIXER,
+    EXT_GIC_ID_HDMI,
+    EXT_GIC_ID_HDMI_I2C,
+    EXT_GIC_ID_MFC,
+    EXT_GIC_ID_TVENC,
+};
+
+enum ExtInt {
+    EXT_GIC_ID_EXTINT0 = 48,
+    EXT_GIC_ID_EXTINT1,
+    EXT_GIC_ID_EXTINT2,
+    EXT_GIC_ID_EXTINT3,
+    EXT_GIC_ID_EXTINT4,
+    EXT_GIC_ID_EXTINT5,
+    EXT_GIC_ID_EXTINT6,
+    EXT_GIC_ID_EXTINT7,
+    EXT_GIC_ID_EXTINT8,
+    EXT_GIC_ID_EXTINT9,
+    EXT_GIC_ID_EXTINT10,
+    EXT_GIC_ID_EXTINT11,
+    EXT_GIC_ID_EXTINT12,
+    EXT_GIC_ID_EXTINT13,
+    EXT_GIC_ID_EXTINT14,
+    EXT_GIC_ID_EXTINT15
+};
+
+/*
+ * External GIC sources which are not from External Interrupt Combiner or
+ * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
+ * which is INTG16 in Internal Interrupt Combiner.
+ */
+
+static const uint32_t
+combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
+    /* int combiner groups 16-19 */
+    { }, { }, { }, { },
+    /* int combiner group 20 */
+    { 0, EXT_GIC_ID_MDMA_LCD0 },
+    /* int combiner group 21 */
+    { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
+    /* int combiner group 22 */
+    { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
+            EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
+    /* int combiner group 23 */
+    { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
+    /* int combiner group 24 */
+    { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
+    /* int combiner group 25 */
+    { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
+    /* int combiner group 26 */
+    { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
+            EXT_GIC_ID_UART4 },
+    /* int combiner group 27 */
+    { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
+            EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
+            EXT_GIC_ID_I2C7 },
+    /* int combiner group 28 */
+    { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
+    /* int combiner group 29 */
+    { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
+     EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
+    /* int combiner group 30 */
+    { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
+    /* int combiner group 31 */
+    { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
+    /* int combiner group 32 */
+    { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
+    /* int combiner group 33 */
+    { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
+    /* int combiner group 34 */
+    { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
+    /* int combiner group 35 */
+    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    /* int combiner group 36 */
+    { EXT_GIC_ID_MIXER },
+    /* int combiner group 37 */
+    { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
+     EXT_GIC_ID_EXTINT7 },
+    /* groups 38-50 */
+    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
+    /* int combiner group 51 */
+    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    /* group 52 */
+    { },
+    /* int combiner group 53 */
+    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    /* groups 54-63 */
+    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
+};
+
+/*
+ * Initialize board IRQs.
+ * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
+ */
+static void exynos4210_init_board_irqs(Exynos4210State *s)
+{
+    uint32_t grp, bit, irq_id, n;
+    Exynos4210Irq *is = &s->irqs;
+
+    for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
+        irq_id = 0;
+        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
+                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
+            /* MCT_G0 is passed to External GIC */
+            irq_id = EXT_GIC_ID_MCT_G0;
+        }
+        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
+                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
+            /* MCT_G1 is passed to External and GIC */
+            irq_id = EXT_GIC_ID_MCT_G1;
+        }
+        if (irq_id) {
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_gic_irq[irq_id - 32]);
+        } else {
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_combiner_irq[n]);
+        }
+    }
+    for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
+        /* these IDs are passed to Internal Combiner and External GIC */
+        grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
+        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
+        irq_id = combiner_grp_to_gic_id[grp -
+                     EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
+
+        if (irq_id) {
+            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
+                    is->ext_gic_irq[irq_id - 32]);
+        }
+    }
+}
+
+/*
+ * Get IRQ number from exynos4210 IRQ subsystem stub.
+ * To identify IRQ source use internal combiner group and bit number
+ *  grp - group number
+ *  bit - bit number inside group
+ */
+uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
+{
+    return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
+}
+
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/arm/exynos4210.h"
 #include "qom/object.h"
 
-enum ExtGicId {
-    EXT_GIC_ID_MDMA_LCD0 = 66,
-    EXT_GIC_ID_PDMA0,
-    EXT_GIC_ID_PDMA1,
-    EXT_GIC_ID_TIMER0,
-    EXT_GIC_ID_TIMER1,
-    EXT_GIC_ID_TIMER2,
-    EXT_GIC_ID_TIMER3,
-    EXT_GIC_ID_TIMER4,
-    EXT_GIC_ID_MCT_L0,
-    EXT_GIC_ID_WDT,
-    EXT_GIC_ID_RTC_ALARM,
-    EXT_GIC_ID_RTC_TIC,
-    EXT_GIC_ID_GPIO_XB,
-    EXT_GIC_ID_GPIO_XA,
-    EXT_GIC_ID_MCT_L1,
-    EXT_GIC_ID_IEM_APC,
-    EXT_GIC_ID_IEM_IEC,
-    EXT_GIC_ID_NFC,
-    EXT_GIC_ID_UART0,
-    EXT_GIC_ID_UART1,
-    EXT_GIC_ID_UART2,
-    EXT_GIC_ID_UART3,
-    EXT_GIC_ID_UART4,
-    EXT_GIC_ID_MCT_G0,
-    EXT_GIC_ID_I2C0,
-    EXT_GIC_ID_I2C1,
-    EXT_GIC_ID_I2C2,
-    EXT_GIC_ID_I2C3,
-    EXT_GIC_ID_I2C4,
-    EXT_GIC_ID_I2C5,
-    EXT_GIC_ID_I2C6,
-    EXT_GIC_ID_I2C7,
-    EXT_GIC_ID_SPI0,
-    EXT_GIC_ID_SPI1,
-    EXT_GIC_ID_SPI2,
-    EXT_GIC_ID_MCT_G1,
-    EXT_GIC_ID_USB_HOST,
-    EXT_GIC_ID_USB_DEVICE,
-    EXT_GIC_ID_MODEMIF,
-    EXT_GIC_ID_HSMMC0,
-    EXT_GIC_ID_HSMMC1,
-    EXT_GIC_ID_HSMMC2,
-    EXT_GIC_ID_HSMMC3,
-    EXT_GIC_ID_SDMMC,
-    EXT_GIC_ID_MIPI_CSI_4LANE,
-    EXT_GIC_ID_MIPI_DSI_4LANE,
-    EXT_GIC_ID_MIPI_CSI_2LANE,
-    EXT_GIC_ID_MIPI_DSI_2LANE,
-    EXT_GIC_ID_ONENAND_AUDI,
-    EXT_GIC_ID_ROTATOR,
-    EXT_GIC_ID_FIMC0,
-    EXT_GIC_ID_FIMC1,
-    EXT_GIC_ID_FIMC2,
-    EXT_GIC_ID_FIMC3,
-    EXT_GIC_ID_JPEG,
-    EXT_GIC_ID_2D,
-    EXT_GIC_ID_PCIe,
-    EXT_GIC_ID_MIXER,
-    EXT_GIC_ID_HDMI,
-    EXT_GIC_ID_HDMI_I2C,
-    EXT_GIC_ID_MFC,
-    EXT_GIC_ID_TVENC,
-};
-
-enum ExtInt {
-    EXT_GIC_ID_EXTINT0 = 48,
-    EXT_GIC_ID_EXTINT1,
-    EXT_GIC_ID_EXTINT2,
-    EXT_GIC_ID_EXTINT3,
-    EXT_GIC_ID_EXTINT4,
-    EXT_GIC_ID_EXTINT5,
-    EXT_GIC_ID_EXTINT6,
-    EXT_GIC_ID_EXTINT7,
-    EXT_GIC_ID_EXTINT8,
-    EXT_GIC_ID_EXTINT9,
-    EXT_GIC_ID_EXTINT10,
-    EXT_GIC_ID_EXTINT11,
-    EXT_GIC_ID_EXTINT12,
-    EXT_GIC_ID_EXTINT13,
-    EXT_GIC_ID_EXTINT14,
-    EXT_GIC_ID_EXTINT15
-};
-
-/*
- * External GIC sources which are not from External Interrupt Combiner or
- * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
- * which is INTG16 in Internal Interrupt Combiner.
- */
-
-static const uint32_t
-combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
-    /* int combiner groups 16-19 */
-    { }, { }, { }, { },
-    /* int combiner group 20 */
-    { 0, EXT_GIC_ID_MDMA_LCD0 },
-    /* int combiner group 21 */
-    { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
-    /* int combiner group 22 */
-    { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
-            EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
-    /* int combiner group 23 */
-    { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
-    /* int combiner group 24 */
-    { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
-    /* int combiner group 25 */
-    { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
-    /* int combiner group 26 */
-    { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
-            EXT_GIC_ID_UART4 },
-    /* int combiner group 27 */
-    { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
-            EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
-            EXT_GIC_ID_I2C7 },
-    /* int combiner group 28 */
-    { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
-    /* int combiner group 29 */
-    { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
-     EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
-    /* int combiner group 30 */
-    { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
-    /* int combiner group 31 */
-    { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
-    /* int combiner group 32 */
-    { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
-    /* int combiner group 33 */
-    { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
-    /* int combiner group 34 */
-    { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
-    /* int combiner group 35 */
-    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
-    /* int combiner group 36 */
-    { EXT_GIC_ID_MIXER },
-    /* int combiner group 37 */
-    { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
-     EXT_GIC_ID_EXTINT7 },
-    /* groups 38-50 */
-    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
-    /* int combiner group 51 */
-    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
-    /* group 52 */
-    { },
-    /* int combiner group 53 */
-    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
-    /* groups 54-63 */
-    { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
-};
-
 #define EXYNOS4210_GIC_NIRQ 160
 
 #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE     0x10000
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
 #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
 
-/*
- * Initialize board IRQs.
- * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
- */
-void exynos4210_init_board_irqs(Exynos4210State *s)
-{
-    uint32_t grp, bit, irq_id, n;
-    Exynos4210Irq *is = &s->irqs;
-
-    for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
-        irq_id = 0;
-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
-            /* MCT_G0 is passed to External GIC */
-            irq_id = EXT_GIC_ID_MCT_G0;
-        }
-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
-            /* MCT_G1 is passed to External and GIC */
-            irq_id = EXT_GIC_ID_MCT_G1;
-        }
-        if (irq_id) {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_gic_irq[irq_id - 32]);
-        } else {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_combiner_irq[n]);
-        }
-    }
-    for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
-        /* these IDs are passed to Internal Combiner and External GIC */
-        grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
-        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
-        irq_id = combiner_grp_to_gic_id[grp -
-                     EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
-
-        if (irq_id) {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_gic_irq[irq_id - 32]);
-        }
-    }
-}
-
-/*
- * Get IRQ number from exynos4210 IRQ subsystem stub.
- * To identify IRQ source use internal combiner group and bit number
- *  grp - group number
- *  bit - bit number inside group
- */
-uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
-{
-    return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
-}
-
-/********* GIC part *********/
-
 #define TYPE_EXYNOS4210_GIC "exynos4210.gic"
 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
 
-- 
2.25.1

Switch the creation of the external GIC to the new-style "embedded in
state struct" approach, so we can easily refer to the object
elsewhere during realize.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-9-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h      |  2 ++
 include/hw/intc/exynos4210_gic.h | 43 ++++++++++++++++++++++++++++++++
 hw/arm/exynos4210.c              | 10 ++++----
 hw/intc/exynos4210_gic.c         | 17 ++-----------
 MAINTAINERS                      |  2 +-
 5 files changed, 53 insertions(+), 21 deletions(-)
 create mode 100644 include/hw/intc/exynos4210_gic.h

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/or-irq.h"
 #include "hw/sysbus.h"
 #include "hw/cpu/a9mpcore.h"
+#include "hw/intc/exynos4210_gic.h"
 #include "target/arm/cpu-qom.h"
 #include "qom/object.h"
 
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
     A9MPPrivState a9mpcore;
+    Exynos4210GicState ext_gic;
 };
 
 #define TYPE_EXYNOS4210_SOC "exynos4210"
diff --git a/include/hw/intc/exynos4210_gic.h b/include/hw/intc/exynos4210_gic.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/intc/exynos4210_gic.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
+ *
+ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
+ * All rights reserved.
+ *
+ * Evgeny Voevodin <e.voevodin@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef HW_INTC_EXYNOS4210_GIC_H
+#define HW_INTC_EXYNOS4210_GIC_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
+
+#define EXYNOS4210_GIC_NCPUS 2
+
+struct Exynos4210GicState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion cpu_container;
+    MemoryRegion dist_container;
+    MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS];
+    MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS];
+    uint32_t num_cpu;
+    DeviceState *gic;
+};
+
+#endif
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
 
     /* External GIC */
-    dev = qdev_new("exynos4210.gic");
-    qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
-    busdev = SYS_BUS_DEVICE(dev);
-    sysbus_realize_and_unref(busdev, &error_fatal);
+    qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
+    busdev = SYS_BUS_DEVICE(&s->ext_gic);
+    sysbus_realize(busdev, &error_fatal);
     /* Map CPU interface */
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
     /* Map Distributer interface */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
     }
     for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
-        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
+        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
     }
 
     /* Internal Interrupt Combiner */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
     }
 
     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
+    object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
 }
 
 static void exynos4210_class_init(ObjectClass *klass, void *data)
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "hw/irq.h"
 #include "hw/qdev-properties.h"
+#include "hw/intc/exynos4210_gic.h"
 #include "hw/arm/exynos4210.h"
 #include "qom/object.h"
 
@@ -XXX,XX +XXX,XX @@
 #define EXYNOS4210_GIC_CPU_REGION_SIZE  0x100
 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
 
-#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
-
-struct Exynos4210GicState {
-    SysBusDevice parent_obj;
-
-    MemoryRegion cpu_container;
-    MemoryRegion dist_container;
-    MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
-    MemoryRegion dist_alias[EXYNOS4210_NCPUS];
-    uint32_t num_cpu;
-    DeviceState *gic;
-};
-
 static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
 {
     Exynos4210GicState *s = (Exynos4210GicState *)opaque;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp)
      * enough room for the cpu numbers.  gcc 9.2.1 on 32-bit x86
      * doesn't figure this out, otherwise and gives spurious warnings.
      */
-    assert(n <= EXYNOS4210_NCPUS);
+    assert(n <= EXYNOS4210_GIC_NCPUS);
     for (i = 0; i < n; i++) {
         /* Map CPU interface per SMP Core */
         sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
 L: qemu-arm@nongnu.org
 S: Odd Fixes
 F: hw/*/exynos*
-F: include/hw/arm/exynos4210.h
+F: include/hw/*/exynos*
 
 Calxeda Highbank
 M: Rob Herring <robh@kernel.org>
-- 
2.25.1

The only time we use the ext_gic_irq[] array in the Exynos4210Irq
struct is during realize of the SoC -- we initialize it with the
input IRQs of the external GIC device, and then connect those to
outputs of other devices further on in realize (including in the
exynos4210_init_board_irqs() function).  Now that the ext_gic object
is easily accessible as s->ext_gic we can make the connections
directly from one device to the other without going via this array.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-10-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  1 -
 hw/arm/exynos4210.c         | 12 ++++++------
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
-    qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
 } Exynos4210Irq;
 
 struct Exynos4210State {
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
 {
     uint32_t grp, bit, irq_id, n;
     Exynos4210Irq *is = &s->irqs;
+    DeviceState *extgicdev = DEVICE(&s->ext_gic);
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
         }
         if (irq_id) {
             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_gic_irq[irq_id - 32]);
+                                             qdev_get_gpio_in(extgicdev,
+                                                              irq_id - 32));
         } else {
             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
                     is->ext_combiner_irq[n]);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
 
         if (irq_id) {
             s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_gic_irq[irq_id - 32]);
+                                             qdev_get_gpio_in(extgicdev,
+                                                              irq_id - 32));
         }
     }
 }
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
         sysbus_connect_irq(busdev, n,
                            qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
     }
-    for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
-        s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
-    }
 
     /* Internal Interrupt Combiner */
     dev = qdev_new("exynos4210.combiner");
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     busdev = SYS_BUS_DEVICE(dev);
     sysbus_realize_and_unref(busdev, &error_fatal);
     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
-        sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
+        sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
     }
     exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
-- 
2.25.1

The function exynos4210_combiner_get_gpioin() currently lives in
exynos4210_combiner.c, but it isn't really part of the combiner
device itself -- it is a function that implements the wiring up of
some interrupt sources to multiple combiner inputs.  Move it to live
with the other SoC-level code in exynos4210.c, along with a few
macros previously defined in exynos4210.h which are now used only
in exynos4210.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-11-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h   | 11 -----
 hw/arm/exynos4210.c           | 82 +++++++++++++++++++++++++++++++++++
 hw/intc/exynos4210_combiner.c | 77 --------------------------------
 3 files changed, 82 insertions(+), 88 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ   \
     (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
 
-#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit)  ((grp)*8 + (bit))
-#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq)       ((irq) / 8)
-#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
-    ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
-
 /* IRQs number for external and internal GIC */
 #define EXYNOS4210_EXT_GIC_NIRQ     (160-32)
 #define EXYNOS4210_INT_GIC_NIRQ     64
@@ -XXX,XX +XXX,XX @@ void exynos4210_write_secondary(ARMCPU *cpu,
  *  bit - bit number inside group */
 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
 
-/*
- * Get Combiner input GPIO into irqs structure
- */
-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
-        int ext);
-
 /*
  * exynos4210 UART
  */
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
 };
 
+#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit)  ((grp) * 8 + (bit))
+#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq)       ((irq) / 8)
+#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
+    ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
+
 /*
  * Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
@@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
     return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
 }
 
+/*
+ * Get Combiner input GPIO into irqs structure
+ */
+static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
+                                           DeviceState *dev, int ext)
+{
+    int n;
+    int bit;
+    int max;
+    qemu_irq *irq;
+
+    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
+        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
+    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
+
+    /*
+     * Some IRQs of Int/External Combiner are going to two Combiners groups,
+     * so let split them.
+     */
+    for (n = 0; n < max; n++) {
+
+        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
+
+        switch (n) {
+        /* MDNIE_LCD1 INTG1 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
+            continue;
+
+        /* TMU INTG3 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
+            continue;
+
+        /* LCD1 INTG12 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
+            continue;
+
+        /* Multi-Core Timer INTG12 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
+               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+            continue;
+
+        /* Multi-Core Timer INTG35 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+            continue;
+
+        /* Multi-Core Timer INTG51 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+            continue;
+
+        /* Multi-Core Timer INTG53 */
+        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
+             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
+            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
+                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
+            continue;
+        }
+
+        irq[n] = qdev_get_gpio_in(dev, n);
+    }
+}
+
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_combiner.c
+++ b/hw/intc/exynos4210_combiner.c
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_combiner = {
     }
 };
 
-/*
- * Get Combiner input GPIO into irqs structure
- */
-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
-        int ext)
-{
-    int n;
-    int bit;
-    int max;
-    qemu_irq *irq;
-
-    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
-        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
-    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
-
-    /*
-     * Some IRQs of Int/External Combiner are going to two Combiners groups,
-     * so let split them.
-     */
-    for (n = 0; n < max; n++) {
-
-        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
-
-        switch (n) {
-        /* MDNIE_LCD1 INTG1 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
-            continue;
-
-        /* TMU INTG3 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
-            continue;
-
-        /* LCD1 INTG12 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG12 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
-               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG35 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG51 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG53 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-        }
-
-        irq[n] = qdev_get_gpio_in(dev, n);
-    }
-}
-
 static uint64_t
 exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
 {
-- 
2.25.1

In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device
instead of qemu_irq_split().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-13-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  9 ++++++++
 hw/arm/exynos4210.c         | 41 +++++++++++++++++++++++++++++--------
 2 files changed, 42 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/intc/exynos4210_gic.h"
+#include "hw/core/split-irq.h"
 #include "target/arm/cpu-qom.h"
 #include "qom/object.h"
 
@@ -XXX,XX +XXX,XX @@
 
 #define EXYNOS4210_NUM_DMA      3
 
+/*
+ * We need one splitter for every external combiner input, plus
+ * one for every non-zero entry in combiner_grp_to_gic_id[].
+ * We'll assert in exynos4210_init_board_irqs() if this is wrong.
+ */
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
+
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
     A9MPPrivState a9mpcore;
     Exynos4210GicState ext_gic;
+    SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
 };
 
 #define TYPE_EXYNOS4210_SOC "exynos4210"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
     uint32_t grp, bit, irq_id, n;
     Exynos4210Irq *is = &s->irqs;
     DeviceState *extgicdev = DEVICE(&s->ext_gic);
+    int splitcount = 0;
+    DeviceState *splitter;
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
             /* MCT_G1 is passed to External and GIC */
             irq_id = EXT_GIC_ID_MCT_G1;
         }
+
+        assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
+        splitter = DEVICE(&s->splitter[splitcount]);
+        qdev_prop_set_uint16(splitter, "num-lines", 2);
+        qdev_realize(splitter, NULL, &error_abort);
+        splitcount++;
+        s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
+        qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
         if (irq_id) {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                                             qdev_get_gpio_in(extgicdev,
-                                                              irq_id - 32));
+            qdev_connect_gpio_out(splitter, 1,
+                                  qdev_get_gpio_in(extgicdev, irq_id - 32));
         } else {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                    is->ext_combiner_irq[n]);
+            qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
         }
     }
     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
 
         if (irq_id) {
-            s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
-                                             qdev_get_gpio_in(extgicdev,
-                                                              irq_id - 32));
+            assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
+            splitter = DEVICE(&s->splitter[splitcount]);
+            qdev_prop_set_uint16(splitter, "num-lines", 2);
+            qdev_realize(splitter, NULL, &error_abort);
+            splitcount++;
+            s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
+            qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
+            qdev_connect_gpio_out(splitter, 1,
+                                  qdev_get_gpio_in(extgicdev, irq_id - 32));
         }
     }
+    /*
+     * We check this here to avoid a more obscure assert later when
+     * qdev_assert_realized_properly() checks that we realized every
+     * child object we initialized.
+     */
+    assert(splitcount == EXYNOS4210_NUM_SPLITTERS);
 }
 
 /*
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
         object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
     }
 
+    for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
+        g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
+        object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ);
+    }
+
     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
     object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
 }
-- 
2.25.1

In exynos4210_init_board_irqs(), the loop that handles IRQ lines that
are in a range that applies to the internal combiner only creates a
splitter for those interrupts which go to both the internal combiner
and to the external GIC, but it does nothing at all for the
interrupts which don't go to the external GIC, leaving the
irq_table[] array element empty for those.  (This will result in
those interrupts simply being lost, not in a QEMU crash.)

I don't have a reliable datasheet for this SoC, but since we do wire
up one interrupt line in this category (the HDMI I2C device on
interrupt 16,1), this seems like it must be a bug in the existing
QEMU code.  Fill in the irq_table[] entries where we're not splitting
the IRQ to both the internal combiner and the external GIC with the
IRQ line of the internal combiner.  (That is, these IRQ lines go to
just one device, not multiple.)

This bug didn't have any visible guest effects because the only
implemented device that was affected was the HDMI I2C controller,
and we never connect any I2C devices to that bus.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-14-peter.maydell@linaro.org
---
 hw/arm/exynos4210.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
             qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
             qdev_connect_gpio_out(splitter, 1,
                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
+        } else {
+            s->irq_table[n] = is->int_combiner_irq[n];
         }
     }
     /*
-- 
2.25.1

Currently for the interrupts MCT_G0 and MCT_G1 which are
the only ones in the input range of the external combiner
and which are also wired to the external GIC, we connect
them only to the internal combiner and the external GIC.
This seems likely to be a bug, as all other interrupts
which are in the input range of both combiners are
connected to both combiners. (The fact that the code in
exynos4210_combiner_get_gpioin() is also trying to wire
up these inputs on both combiners also suggests this.)

Wire these interrupts up to both combiners, like the rest.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-15-peter.maydell@linaro.org
---
 hw/arm/exynos4210.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
 
         assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
         splitter = DEVICE(&s->splitter[splitcount]);
-        qdev_prop_set_uint16(splitter, "num-lines", 2);
+        qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2);
         qdev_realize(splitter, NULL, &error_abort);
         splitcount++;
         s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
         qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
+        qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
         if (irq_id) {
-            qdev_connect_gpio_out(splitter, 1,
+            qdev_connect_gpio_out(splitter, 2,
                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
-        } else {
-            qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
         }
     }
     for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
-- 
2.25.1

The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0
and EXT_GIC_ID_MCT_G1 multiple times. This means that we will
connect multiple IRQs up to the same external GIC input, which
is not permitted. We do the same thing in the code in
exynos4210_init_board_irqs() because the conditionals selecting
an irq_id in the first loop match multiple interrupt IDs.

Overall we do this for interrupt IDs
(1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0
and
(1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1

These correspond to the cases for the multi-core timer that we are
wiring up to multiple inputs on the combiner in
exynos4210_combiner_get_gpioin().  That code already deals with all
these interrupt IDs being the same input source, so we don't need to
connect the external GIC interrupt for any of them except the first
(1, 4) and (1, 5). Remove the array entries and conditionals which
were incorrectly causing us to wire up extra lines.

This bug didn't cause any visible effects, because we only connect
up a device to the "primary" ID values (1, 4) and (1, 5), so the
extra lines would never be set to a level.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-16-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  2 +-
 hw/arm/exynos4210.c         | 12 +++++-------
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
  * one for every non-zero entry in combiner_grp_to_gic_id[].
  * We'll assert in exynos4210_init_board_irqs() if this is wrong.
  */
-#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
 
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
     /* int combiner group 34 */
     { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
     /* int combiner group 35 */
-    { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    { 0, 0, 0, EXT_GIC_ID_MCT_L1 },
     /* int combiner group 36 */
     { EXT_GIC_ID_MIXER },
     /* int combiner group 37 */
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
     /* groups 38-50 */
     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
     /* int combiner group 51 */
-    { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    { EXT_GIC_ID_MCT_L0 },
     /* group 52 */
     { },
     /* int combiner group 53 */
-    { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
+    { EXT_GIC_ID_WDT },
     /* groups 54-63 */
     { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
 };
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
+        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) {
             /* MCT_G0 is passed to External GIC */
             irq_id = EXT_GIC_ID_MCT_G0;
         }
-        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
-                n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
+        if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) {
             /* MCT_G1 is passed to External and GIC */
             irq_id = EXT_GIC_ID_MCT_G1;
         }
-- 
2.25.1

At this point, the function exynos4210_init_board_irqs() splits input
IRQ lines to connect them to the input combiner, output combiner and
external GIC.  The function exynos4210_combiner_get_gpioin() splits
some of the combiner input lines further to connect them to multiple
different inputs on the combiner.

Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a
configurable number of outputs, we can do all this in one place, by
making exynos4210_init_board_irqs() add extra outputs to the splitter
device when it must be connected to more than one input on each
combiner.

We do this with a new data structure, the combinermap, which is an
array each of whose elements is a list of the interrupt IDs on the
combiner which must be tied together.  As we loop through each
interrupt ID, if we find that it is the first one in one of these
lists, we configure the splitter device with eonugh extra outputs and
wire them up to the other interrupt IDs in the list.

Conveniently, for all the cases where this is necessary, the
lowest-numbered interrupt ID in each group is in the range of the
external combiner, so we only need to code for this in the first of
the two loops in exynos4210_init_board_irqs().

The old code in exynos4210_combiner_get_gpioin() which is being
deleted here had several problems which don't exist in the new code
in its handling of the multi-core timer interrupts:
 (1) the case labels specified bits 4 ... 8, but bit '8' doesn't
     exist; these should have been 4 ... 7
 (2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]
     multiple times as the input of several different splitters,
     which isn't allowed
 (3) in an apparent cut-and-paste error, the cases for all the
     multi-core timer inputs used "bit + 4" even though the
     bit range for the case was (intended to be) 4 ... 7, which
     meant it was looking at non-existent bits 8 ... 11.
None of these exist in the new code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-17-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |   6 +-
 hw/arm/exynos4210.c         | 178 +++++++++++++++++++++++-------------
 2 files changed, 119 insertions(+), 65 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 
 /*
  * We need one splitter for every external combiner input, plus
- * one for every non-zero entry in combiner_grp_to_gic_id[].
+ * one for every non-zero entry in combiner_grp_to_gic_id[],
+ * minus one for every external combiner ID in second or later
+ * places in a combinermap[] line.
  * We'll assert in exynos4210_init_board_irqs() if this is wrong.
  */
-#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
 
 typedef struct Exynos4210Irq {
     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
 #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
     ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
 
+/*
+ * Some interrupt lines go to multiple combiner inputs.
+ * This data structure defines those: each array element is
+ * a list of combiner inputs which are connected together;
+ * the one with the smallest interrupt ID value must be first.
+ * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being
+ * wired to anything so we can use 0 as a terminator.
+ */
+#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B)
+#define IRQNONE 0
+
+#define COMBINERMAP_SIZE 16
+
+static const int combinermap[COMBINERMAP_SIZE][6] = {
+    /* MDNIE_LCD1 */
+    { IRQNO(0, 4), IRQNO(1, 0), IRQNONE },
+    { IRQNO(0, 5), IRQNO(1, 1), IRQNONE },
+    { IRQNO(0, 6), IRQNO(1, 2), IRQNONE },
+    { IRQNO(0, 7), IRQNO(1, 3), IRQNONE },
+    /* TMU */
+    { IRQNO(2, 4), IRQNO(3, 4), IRQNONE },
+    { IRQNO(2, 5), IRQNO(3, 5), IRQNONE },
+    { IRQNO(2, 6), IRQNO(3, 6), IRQNONE },
+    { IRQNO(2, 7), IRQNO(3, 7), IRQNONE },
+    /* LCD1 */
+    { IRQNO(11, 4), IRQNO(12, 0), IRQNONE },
+    { IRQNO(11, 5), IRQNO(12, 1), IRQNONE },
+    { IRQNO(11, 6), IRQNO(12, 2), IRQNONE },
+    { IRQNO(11, 7), IRQNO(12, 3), IRQNONE },
+    /* Multi-core timer */
+    { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE },
+    { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE },
+    { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE },
+    { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE },
+};
+
+#undef IRQNO
+
+static const int *combinermap_entry(int irq)
+{
+    /*
+     * If the interrupt number passed in is the first entry in some
+     * line of the combinermap, return a pointer to that line;
+     * otherwise return NULL.
+     */
+    int i;
+    for (i = 0; i < COMBINERMAP_SIZE; i++) {
+        if (combinermap[i][0] == irq) {
+            return combinermap[i];
+        }
+    }
+    return NULL;
+}
+
+static int mapline_size(const int *mapline)
+{
+    /* Return number of entries in this mapline in total */
+    int i = 0;
+
+    if (!mapline) {
+        /* Not in the map? IRQ goes to exactly one combiner input */
+        return 1;
+    }
+    while (*mapline != IRQNONE) {
+        mapline++;
+        i++;
+    }
+    return i;
+}
+
 /*
  * Initialize board IRQs.
  * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
     DeviceState *extgicdev = DEVICE(&s->ext_gic);
     int splitcount = 0;
     DeviceState *splitter;
+    const int *mapline;
+    int numlines, splitin, in;
 
     for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
         irq_id = 0;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
             irq_id = EXT_GIC_ID_MCT_G1;
         }
 
+        if (s->irq_table[n]) {
+            /*
+             * This must be some non-first entry in a combinermap line,
+             * and we've already filled it in.
+             */
+            continue;
+        }
+        mapline = combinermap_entry(n);
+        /*
+         * We need to connect the IRQ to multiple inputs on both combiners
+         * and possibly also to the external GIC.
+         */
+        numlines = 2 * mapline_size(mapline);
+        if (irq_id) {
+            numlines++;
+        }
         assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
         splitter = DEVICE(&s->splitter[splitcount]);
-        qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2);
+        qdev_prop_set_uint16(splitter, "num-lines", numlines);
         qdev_realize(splitter, NULL, &error_abort);
         splitcount++;
-        s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
-        qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
-        qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
+
+        in = n;
+        splitin = 0;
+        for (;;) {
+            s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
+            qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]);
+            qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]);
+            splitin += 2;
+            if (!mapline) {
+                break;
+            }
+            mapline++;
+            in = *mapline;
+            if (in == IRQNONE) {
+                break;
+            }
+        }
         if (irq_id) {
-            qdev_connect_gpio_out(splitter, 2,
+            qdev_connect_gpio_out(splitter, splitin,
                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
         }
     }
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
         irq_id = combiner_grp_to_gic_id[grp -
                      EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
 
+        if (s->irq_table[n]) {
+            /*
+             * This must be some non-first entry in a combinermap line,
+             * and we've already filled it in.
+             */
+            continue;
+        }
+
         if (irq_id) {
             assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
             splitter = DEVICE(&s->splitter[splitcount]);
@@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
                                            DeviceState *dev, int ext)
 {
     int n;
-    int bit;
     int max;
     qemu_irq *irq;
 
@@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
         EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
     irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
 
-    /*
-     * Some IRQs of Int/External Combiner are going to two Combiners groups,
-     * so let split them.
-     */
     for (n = 0; n < max; n++) {
-
-        bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
-
-        switch (n) {
-        /* MDNIE_LCD1 INTG1 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
-            continue;
-
-        /* TMU INTG3 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
-            continue;
-
-        /* LCD1 INTG12 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG12 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
-               irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                       irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG35 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG51 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-
-        /* Multi-Core Timer INTG53 */
-        case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
-             EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
-            irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
-                    irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
-            continue;
-        }
-
         irq[n] = qdev_get_gpio_in(dev, n);
     }
 }
-- 
2.25.1

Switch the creation of the combiner devices to the new-style
"embedded in state struct" approach, so we can easily refer
to the object elsewhere during realize.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-18-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h           |  3 ++
 include/hw/intc/exynos4210_combiner.h | 57 +++++++++++++++++++++++++++
 hw/arm/exynos4210.c                   | 20 +++++-----
 hw/intc/exynos4210_combiner.c         | 31 +--------------
 4 files changed, 72 insertions(+), 39 deletions(-)
 create mode 100644 include/hw/intc/exynos4210_combiner.h

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/intc/exynos4210_gic.h"
+#include "hw/intc/exynos4210_combiner.h"
 #include "hw/core/split-irq.h"
 #include "target/arm/cpu-qom.h"
 #include "qom/object.h"
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
     A9MPPrivState a9mpcore;
     Exynos4210GicState ext_gic;
+    Exynos4210CombinerState int_combiner;
+    Exynos4210CombinerState ext_combiner;
     SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
 };
 
diff --git a/include/hw/intc/exynos4210_combiner.h b/include/hw/intc/exynos4210_combiner.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/intc/exynos4210_combiner.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * Samsung exynos4210 Interrupt Combiner
+ *
+ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
+ * All rights reserved.
+ *
+ * Evgeny Voevodin <e.voevodin@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_INTC_EXYNOS4210_COMBINER
+#define HW_INTC_EXYNOS4210_COMBINER
+
+#include "hw/sysbus.h"
+
+/*
+ * State for each output signal of internal combiner
+ */
+typedef struct CombinerGroupState {
+    uint8_t src_mask;            /* 1 - source enabled, 0 - disabled */
+    uint8_t src_pending;        /* Pending source interrupts before masking */
+} CombinerGroupState;
+
+#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
+
+/* Number of groups and total number of interrupts for the internal combiner */
+#define IIC_NGRP 64
+#define IIC_NIRQ (IIC_NGRP * 8)
+#define IIC_REGSET_SIZE 0x41
+
+struct Exynos4210CombinerState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+
+    struct CombinerGroupState group[IIC_NGRP];
+    uint32_t reg_set[IIC_REGSET_SIZE];
+    uint32_t icipsr[2];
+    uint32_t external;          /* 1 means that this combiner is external */
+
+    qemu_irq output_irq[IIC_NGRP];
+};
+
+#endif
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     }
 
     /* Internal Interrupt Combiner */
-    dev = qdev_new("exynos4210.combiner");
-    busdev = SYS_BUS_DEVICE(dev);
-    sysbus_realize_and_unref(busdev, &error_fatal);
+    busdev = SYS_BUS_DEVICE(&s->int_combiner);
+    sysbus_realize(busdev, &error_fatal);
     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
         sysbus_connect_irq(busdev, n,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
     }
-    exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
+    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 
     /* External Interrupt Combiner */
-    dev = qdev_new("exynos4210.combiner");
-    qdev_prop_set_uint32(dev, "external", 1);
-    busdev = SYS_BUS_DEVICE(dev);
-    sysbus_realize_and_unref(busdev, &error_fatal);
+    qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1);
+    busdev = SYS_BUS_DEVICE(&s->ext_combiner);
+    sysbus_realize(busdev, &error_fatal);
     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
     }
-    exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
+    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 
     /* Initialize board IRQs. */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
 
     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
     object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
+    object_initialize_child(obj, "int-combiner", &s->int_combiner,
+                            TYPE_EXYNOS4210_COMBINER);
+    object_initialize_child(obj, "ext-combiner", &s->ext_combiner,
+                            TYPE_EXYNOS4210_COMBINER);
 }
 
 static void exynos4210_class_init(ObjectClass *klass, void *data)
diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/exynos4210_combiner.c
+++ b/hw/intc/exynos4210_combiner.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "migration/vmstate.h"
 #include "qemu/module.h"
-
+#include "hw/intc/exynos4210_combiner.h"
 #include "hw/arm/exynos4210.h"
 #include "hw/hw.h"
 #include "hw/irq.h"
@@ -XXX,XX +XXX,XX @@
 #define DPRINTF(fmt, ...) do {} while (0)
 #endif
 
-#define    IIC_NGRP        64            /* Internal Interrupt Combiner
-                                            Groups number */
-#define    IIC_NIRQ        (IIC_NGRP * 8)/* Internal Interrupt Combiner
-                                            Interrupts number */
 #define IIC_REGION_SIZE    0x108         /* Size of memory mapped region */
-#define IIC_REGSET_SIZE    0x41
-
-/*
- * State for each output signal of internal combiner
- */
-typedef struct CombinerGroupState {
-    uint8_t src_mask;            /* 1 - source enabled, 0 - disabled */
-    uint8_t src_pending;        /* Pending source interrupts before masking */
-} CombinerGroupState;
-
-#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
-
-struct Exynos4210CombinerState {
-    SysBusDevice parent_obj;
-
-    MemoryRegion iomem;
-
-    struct CombinerGroupState group[IIC_NGRP];
-    uint32_t reg_set[IIC_REGSET_SIZE];
-    uint32_t icipsr[2];
-    uint32_t external;          /* 1 means that this combiner is external */
-
-    qemu_irq output_irq[IIC_NGRP];
-};
 
 static const VMStateDescription vmstate_exynos4210_combiner_group_state = {
     .name = "exynos4210.combiner.groupstate",
-- 
2.25.1

The only time we use the int_combiner_irq[] and ext_combiner_irq[]
arrays in the Exynos4210Irq struct is during realize of the SoC -- we
initialize them with the input IRQs of the combiner devices, and then
connect those to outputs of other devices in
exynos4210_init_board_irqs().  Now that the combiner objects are
easily accessible as s->int_combiner and s->ext_combiner we can make
the connections directly from one device to the other without going
via these arrays.

Since these are the only two remaining elements of Exynos4210Irq,
we can remove that struct entirely.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-19-peter.maydell@linaro.org
---
 include/hw/arm/exynos4210.h |  6 ------
 hw/arm/exynos4210.c         | 34 ++++++++--------------------------
 2 files changed, 8 insertions(+), 32 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@
  */
 #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
 
-typedef struct Exynos4210Irq {
-    qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
-    qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
-} Exynos4210Irq;
-
 struct Exynos4210State {
     /*< private >*/
     SysBusDevice parent_obj;
     /*< public >*/
     ARMCPU *cpu[EXYNOS4210_NCPUS];
-    Exynos4210Irq irqs;
     qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
 
     MemoryRegion chipid_mem;
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline)
 static void exynos4210_init_board_irqs(Exynos4210State *s)
 {
     uint32_t grp, bit, irq_id, n;
-    Exynos4210Irq *is = &s->irqs;
     DeviceState *extgicdev = DEVICE(&s->ext_gic);
+    DeviceState *intcdev = DEVICE(&s->int_combiner);
+    DeviceState *extcdev = DEVICE(&s->ext_combiner);
     int splitcount = 0;
     DeviceState *splitter;
     const int *mapline;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
         splitin = 0;
         for (;;) {
             s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
-            qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]);
-            qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]);
+            qdev_connect_gpio_out(splitter, splitin,
+                                  qdev_get_gpio_in(intcdev, in));
+            qdev_connect_gpio_out(splitter, splitin + 1,
+                                  qdev_get_gpio_in(extcdev, in));
             splitin += 2;
             if (!mapline) {
                 break;
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
             qdev_realize(splitter, NULL, &error_abort);
             splitcount++;
             s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
-            qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
+            qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n));
             qdev_connect_gpio_out(splitter, 1,
                                   qdev_get_gpio_in(extgicdev, irq_id - 32));
         } else {
-            s->irq_table[n] = is->int_combiner_irq[n];
+            s->irq_table[n] = qdev_get_gpio_in(intcdev, n);
         }
     }
     /*
@@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
     return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
 }
 
-/*
- * Get Combiner input GPIO into irqs structure
- */
-static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
-                                           DeviceState *dev, int ext)
-{
-    int n;
-    int max;
-    qemu_irq *irq;
-
-    max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
-        EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
-    irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
-
-    for (n = 0; n < max; n++) {
-        irq[n] = qdev_get_gpio_in(dev, n);
-    }
-}
-
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
         sysbus_connect_irq(busdev, n,
                            qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
     }
-    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
 
     /* External Interrupt Combiner */
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
     for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
         sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
     }
-    exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1);
     sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
 
     /* Initialize board IRQs. */
-- 
2.25.1

From: Zongyuan Li <zongyuan.li@smartx.com>

Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/realview.c | 33 ++++++++++++++++++++++++---------
 1 file changed, 24 insertions(+), 9 deletions(-)

diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
+#include "hw/core/split-irq.h"
 #include "hw/net/lan9118.h"
 #include "hw/net/smc91c111.h"
 #include "hw/pci/pci.h"
+#include "hw/qdev-core.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "hw/boards.h"
@@ -XXX,XX +XXX,XX @@ static const int realview_board_id[] = {
     0x76d
 };
 
+static void split_irq_from_named(DeviceState *src, const char* outname,
+                                 qemu_irq out1, qemu_irq out2) {
+    DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
+
+    qdev_prop_set_uint32(splitter, "num-lines", 2);
+
+    qdev_realize_and_unref(splitter, NULL, &error_fatal);
+
+    qdev_connect_gpio_out(splitter, 0, out1);
+    qdev_connect_gpio_out(splitter, 1, out2);
+    qdev_connect_gpio_out_named(src, outname, 0,
+                                qdev_get_gpio_in(splitter, 0));
+}
+
 static void realview_init(MachineState *machine,
                           enum realview_board_type board_type)
 {
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
     DeviceState *dev, *sysctl, *gpio2, *pl041;
     SysBusDevice *busdev;
     qemu_irq pic[64];
-    qemu_irq mmc_irq[2];
     PCIBus *pci_bus = NULL;
     NICInfo *nd;
     DriveInfo *dinfo;
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
      * and the PL061 has them the other way about. Also the card
      * detect line is inverted.
      */
-    mmc_irq[0] = qemu_irq_split(
-        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
-        qdev_get_gpio_in(gpio2, 1));
-    mmc_irq[1] = qemu_irq_split(
-        qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
-        qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
-    qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]);
-    qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]);
+    split_irq_from_named(dev, "card-read-only",
+                   qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
+                   qdev_get_gpio_in(gpio2, 1));
+
+    split_irq_from_named(dev, "card-inserted",
+                   qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
+                   qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
+
     dinfo = drive_get(IF_SD, 0, 0);
     if (dinfo) {
         DeviceState *card;
-- 
2.25.1

From: Zongyuan Li <zongyuan.li@smartx.com>

Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/stellaris.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
+#include "hw/core/split-irq.h"
 #include "hw/sysbus.h"
 #include "hw/sd/sd.h"
 #include "hw/ssi/ssi.h"
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
             DeviceState *ssddev;
             DriveInfo *dinfo;
             DeviceState *carddev;
+            DeviceState *gpio_d_splitter;
             BlockBackend *blk;
 
             /*
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
                                    &error_fatal);
 
             ssddev = ssi_create_peripheral(bus, "ssd0323");
-            gpio_out[GPIO_D][0] = qemu_irq_split(
-                    qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
+
+            gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
+            qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
+            qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
+            qdev_connect_gpio_out(
+                    gpio_d_splitter, 0,
+                    qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0));
+            qdev_connect_gpio_out(
+                    gpio_d_splitter, 1,
                     qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
+            gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0);
+
             gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
 
             /* Make sure the select pin is high.  */
-- 
2.25.1

From: Zongyuan Li <zongyuan.li@smartx.com>

Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/irq.h |  5 -----
 hw/core/irq.c    | 15 ---------------
 2 files changed, 20 deletions(-)

diff --git a/include/hw/irq.h b/include/hw/irq.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq);
 /* Returns a new IRQ with opposite polarity.  */
 qemu_irq qemu_irq_invert(qemu_irq irq);
 
-/* Returns a new IRQ which feeds into both the passed IRQs.
- * It's probably better to use the TYPE_SPLIT_IRQ device instead.
- */
-qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
-
 /* For internal use in qtest.  Similar to qemu_irq_split, but operating
    on an existing vector of qemu_irq.  */
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
diff --git a/hw/core/irq.c b/hw/core/irq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_invert(qemu_irq irq)
     return qemu_allocate_irq(qemu_notirq, irq, 0);
 }
 
-static void qemu_splitirq(void *opaque, int line, int level)
-{
-    struct IRQState **irq = opaque;
-    irq[0]->handler(irq[0]->opaque, irq[0]->n, level);
-    irq[1]->handler(irq[1]->opaque, irq[1]->n, level);
-}
-
-qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
-{
-    qemu_irq *s = g_new0(qemu_irq, 2);
-    s[0] = irq1;
-    s[1] = irq2;
-    return qemu_allocate_irq(qemu_splitirq, s, 0);
-}
-
 void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
 {
     int i;
-- 
2.25.1

From: Hao Wu <wuhaotsh@google.com>

Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
the PWRON STRAP fields in their corresponding module for NPCM7XX.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20220411165842.3912945-2-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/npcm7xx_gcr.h
+++ b/include/hw/misc/npcm7xx_gcr.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/memory.h"
 #include "hw/sysbus.h"
 
+/*
+ * NPCM7XX PWRON STRAP bit fields
+ * 12: SPI0 powered by VSBV3 at 1.8V
+ * 11: System flash attached to BMC
+ * 10: BSP alternative pins.
+ * 9:8: Flash UART command route enabled.
+ * 7: Security enabled.
+ * 6: HI-Z state control.
+ * 5: ECC disabled.
+ * 4: Reserved
+ * 3: JTAG2 enabled.
+ * 2:0: CPU and DRAM clock frequency.
+ */
+#define NPCM7XX_PWRON_STRAP_SPI0F18                 BIT(12)
+#define NPCM7XX_PWRON_STRAP_SFAB                    BIT(11)
+#define NPCM7XX_PWRON_STRAP_BSPA                    BIT(10)
+#define NPCM7XX_PWRON_STRAP_FUP(x)                  ((x) << 8)
+#define     FUP_NORM_UART2      3
+#define     FUP_PROG_UART3      2
+#define     FUP_PROG_UART2      1
+#define     FUP_NORM_UART3      0
+#define NPCM7XX_PWRON_STRAP_SECEN                   BIT(7)
+#define NPCM7XX_PWRON_STRAP_HIZ                     BIT(6)
+#define NPCM7XX_PWRON_STRAP_ECC                     BIT(5)
+#define NPCM7XX_PWRON_STRAP_RESERVE1                BIT(4)
+#define NPCM7XX_PWRON_STRAP_J2EN                    BIT(3)
+#define NPCM7XX_PWRON_STRAP_CKFRQ(x)                (x)
+#define     CKFRQ_SKIPINIT      0x000
+#define     CKFRQ_DEFAULT       0x111
+
 /*
  * Number of registers in our device state structure. Don't change this without
  * incrementing the version_id in the vmstate.
-- 
2.25.1

From: Hao Wu <wuhaotsh@google.com>

This patch uses the defined fields to describe PWRON STRAPs for
better readability.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20220411165842.3912945-3-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/npcm7xx_boards.c | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "sysemu/block-backend.h"
 
-#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
-#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
-#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff
-#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff
-#define MORI_BMC_POWER_ON_STRAPS 0x00001fff
+#define NPCM7XX_POWER_ON_STRAPS_DEFAULT (           \
+        NPCM7XX_PWRON_STRAP_SPI0F18 |               \
+        NPCM7XX_PWRON_STRAP_SFAB |                  \
+        NPCM7XX_PWRON_STRAP_BSPA |                  \
+        NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) |   \
+        NPCM7XX_PWRON_STRAP_SECEN |                 \
+        NPCM7XX_PWRON_STRAP_HIZ |                   \
+        NPCM7XX_PWRON_STRAP_ECC |                   \
+        NPCM7XX_PWRON_STRAP_RESERVE1 |              \
+        NPCM7XX_PWRON_STRAP_J2EN |                  \
+        NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT))
+
+#define NPCM750_EVB_POWER_ON_STRAPS ( \
+        NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN)
+#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
+#define QUANTA_GBS_POWER_ON_STRAPS ( \
+        NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
+#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
+#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
 
 static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
 
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2.25.1