Patchew URL: https://patchew.org/QEMU/20190904193059.26202-1-richard.henderson@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190904193059.26202-1-richard.henderson@linaro.org
Type: series
Subject: [Qemu-devel] [PATCH v4 00/69] target/arm: Convert aa32 base isa to decodetree
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
f240e8f target/arm: Inline gen_bx_im into callers
10d4d3d target/arm: Clean up disas_thumb_insn
e36cea5 target/arm: Convert T16, long branches
1061d1b target/arm: Convert T16, Unconditional branch
7c2aede target/arm: Convert T16, load (literal)
fd73031 target/arm: Convert T16, shift immediate
ac59480 target/arm: Convert T16, Miscellaneous 16-bit instructions
d0ec6df target/arm: Convert T16, Conditional branches, Supervisor call
5c1ac2f target/arm: Convert T16, push and pop
bdac1b8 target/arm: Split gen_nop_hint
0b3fed7 target/arm: Convert T16, nop hints
5021591 target/arm: Convert T16, Reverse bytes
3ec6264 target/arm: Convert T16, Change processor state
8bfb8e3 target/arm: Convert T16, extract
75466c7 target/arm: Convert T16 adjust sp (immediate)
9ab6de5 target/arm: Convert T16 add, compare, move (two high registers)
f004a7c target/arm: Convert T16 branch and exchange
cc1634d target/arm: Convert T16 one low register and immediate
d92915a target/arm: Convert T16 add/sub (3 low, 2 low and imm)
1acf8f6 target/arm: Convert T16 load/store multiple
af56e9a target/arm: Convert T16 add pc/sp (immediate)
c0275cf target/arm: Convert T16 load/store (immediate offset)
bfba5bf target/arm: Convert T16 load/store (register offset)
2f6c9ca target/arm: Convert T16 data-processing (two low regs)
994e0b4 target/arm: Add skeleton for T16 decodetree
25c88a8 target/arm: Simplify disas_arm_insn
446ed56 target/arm: Simplify disas_thumb2_insn
ee41906 target/arm: Convert TT
eb5f39d target/arm: Convert SG
39e761d target/arm: Convert Table Branch
86eec33 target/arm: Convert Unallocated memory hint
d17b1df target/arm: Convert PLI, PLD, PLDW
cdab118 target/arm: Convert SETEND
b374ec7 target/arm: Convert CPS (privileged)
fcf2c5a target/arm: Convert Clear-Exclusive, Barriers
6084bd7 target/arm: Convert RFE and SRS
d3a1d7b target/arm: Convert SVC
967a9fd target/arm: Convert B, BL, BLX (immediate)
e2925d5 target/arm: Diagnose base == pc for LDM/STM
80fca3c target/arm: Diagnose too few registers in list for LDM/STM
b585071 target/arm: Diagnose writeback register in list for LDM for v7
0d41010 target/arm: Convert LDM, STM
0318d42 target/arm: Convert MOVW, MOVT
f911da0 target/arm: Convert Signed multiply, signed and unsigned divide
dc67f09 target/arm: Convert packing, unpacking, saturation, and reversal
76b3d60 target/arm: Convert Parallel addition and subtraction
90d3a3b target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF
5dbd48c target/arm: Diagnose UNPREDICTABLE ldrex/strex cases
3007337 target/arm: Convert Synchronization primitives
e27fda5 target/arm: Convert load/store (register, immediate, literal)
7f75e0f target/arm: Convert T32 ADDW/SUBW
3da4ded target/arm: Convert the rest of A32 Miscelaneous instructions
fd3df88 target/arm: Convert ERET
2116b98 target/arm: Convert CLZ
43f780c target/arm: Convert BX, BXJ, BLX (register)
e46bd40 target/arm: Convert Cyclic Redundancy Check
9824eaa target/arm: Convert MRS/MSR (banked, register)
7c864c7 target/arm: Convert MSR (immediate) and hints
f9b0422 target/arm: Simplify op_smlawx for SMLAW*
60dff02 target/arm: Simplify op_smlaxxx for SMLAL*
7de1dd4 target/arm: Convert Halfword multiply and multiply accumulate
620dfcd target/arm: Convert Saturating addition and subtraction
d795a84 target/arm: Simplify UMAAL
6d5e8d6 target/arm: Convert multiply and multiply accumulate
ed27304 target/arm: Convert Data Processing (immediate)
6b7986e target/arm: Convert Data Processing (reg-shifted-reg)
08c75f2 target/arm: Convert Data Processing (register)
92b92a6 target/arm: Add stubs for aa32 decodetree
010e06b target/arm: Use store_reg_from_load in thumb2 code
=== OUTPUT BEGIN ===
1/69 Checking commit 010e06b2e758 (target/arm: Use store_reg_from_load in thumb2 code)
2/69 Checking commit 92b92a62ad69 (target/arm: Add stubs for aa32 decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 154 lines checked
Patch 2/69 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/69 Checking commit 08c75f210ec5 (target/arm: Convert Data Processing (register))
4/69 Checking commit 6b7986e01dc9 (target/arm: Convert Data Processing (reg-shifted-reg))
5/69 Checking commit ed273043b335 (target/arm: Convert Data Processing (immediate))
6/69 Checking commit 6d5e8d6635d9 (target/arm: Convert multiply and multiply accumulate)
7/69 Checking commit d795a84e97c8 (target/arm: Simplify UMAAL)
8/69 Checking commit 620dfcda6680 (target/arm: Convert Saturating addition and subtraction)
9/69 Checking commit 7de1dd41c41e (target/arm: Convert Halfword multiply and multiply accumulate)
10/69 Checking commit 60dff02fa9ed (target/arm: Simplify op_smlaxxx for SMLAL*)
11/69 Checking commit f9b04228f14c (target/arm: Simplify op_smlawx for SMLAW*)
12/69 Checking commit 7c864c754920 (target/arm: Convert MSR (immediate) and hints)
13/69 Checking commit 9824eaac1c17 (target/arm: Convert MRS/MSR (banked, register))
14/69 Checking commit e46bd404e5f9 (target/arm: Convert Cyclic Redundancy Check)
15/69 Checking commit 43f780c34d6f (target/arm: Convert BX, BXJ, BLX (register))
16/69 Checking commit 2116b988bc12 (target/arm: Convert CLZ)
17/69 Checking commit fd3df8890864 (target/arm: Convert ERET)
18/69 Checking commit 3da4dedcbb2d (target/arm: Convert the rest of A32 Miscelaneous instructions)
19/69 Checking commit 7f75e0f6d791 (target/arm: Convert T32 ADDW/SUBW)
20/69 Checking commit e27fda585f07 (target/arm: Convert load/store (register, immediate, literal))
21/69 Checking commit 30073379c3c1 (target/arm: Convert Synchronization primitives)
22/69 Checking commit 5dbd48cd4f8c (target/arm: Diagnose UNPREDICTABLE ldrex/strex cases)
23/69 Checking commit 90d3a3b738a0 (target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF)
24/69 Checking commit 76b3d6038d80 (target/arm: Convert Parallel addition and subtraction)
25/69 Checking commit dc67f09ea978 (target/arm: Convert packing, unpacking, saturation, and reversal)
ERROR: trailing statements should be on next line
#785: FILE: target/arm/translate.c:11522:
+ case 1: gen_rev16(tmp, tmp); break;
ERROR: trailing statements should be on next line
#786: FILE: target/arm/translate.c:11523:
+ case 3: gen_revsh(tmp, tmp); break;
total: 2 errors, 0 warnings, 747 lines checked
Patch 25/69 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
26/69 Checking commit f911da0740cf (target/arm: Convert Signed multiply, signed and unsigned divide)
27/69 Checking commit 0318d4286b49 (target/arm: Convert MOVW, MOVT)
28/69 Checking commit 0d41010f7949 (target/arm: Convert LDM, STM)
29/69 Checking commit b5850718adc9 (target/arm: Diagnose writeback register in list for LDM for v7)
30/69 Checking commit 80fca3c503b3 (target/arm: Diagnose too few registers in list for LDM/STM)
31/69 Checking commit e2925d5dce6b (target/arm: Diagnose base == pc for LDM/STM)
32/69 Checking commit 967a9fdae3ba (target/arm: Convert B, BL, BLX (immediate))
33/69 Checking commit d3a1d7b01496 (target/arm: Convert SVC)
34/69 Checking commit 6084bd7f8c96 (target/arm: Convert RFE and SRS)
WARNING: Block comments use a leading /* on a separate line
#64: FILE: target/arm/translate.c:10103:
+ /* DA */ -4, /* IA */ 0, /* DB */ -8, /* IB */ 4
WARNING: Block comments use a leading /* on a separate line
#67: FILE: target/arm/translate.c:10106:
+ /* DA */ -8, /* IA */ 4, /* DB */ -4, /* IB */ 0
total: 0 errors, 2 warnings, 202 lines checked
Patch 34/69 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
35/69 Checking commit fcf2c5ac71c2 (target/arm: Convert Clear-Exclusive, Barriers)
36/69 Checking commit b374ec7008f5 (target/arm: Convert CPS (privileged))
37/69 Checking commit cdab1187dab9 (target/arm: Convert SETEND)
38/69 Checking commit d17b1dfbae34 (target/arm: Convert PLI, PLD, PLDW)
39/69 Checking commit 86eec3335c43 (target/arm: Convert Unallocated memory hint)
40/69 Checking commit 39e761ddb924 (target/arm: Convert Table Branch)
41/69 Checking commit eb5f39d5e4ba (target/arm: Convert SG)
42/69 Checking commit ee419060fd23 (target/arm: Convert TT)
43/69 Checking commit 446ed56b59e0 (target/arm: Simplify disas_thumb2_insn)
44/69 Checking commit 25c88a885268 (target/arm: Simplify disas_arm_insn)
45/69 Checking commit 994e0b46cb4b (target/arm: Add skeleton for T16 decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#35:
new file mode 100644
total: 0 errors, 1 warnings, 56 lines checked
Patch 45/69 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
46/69 Checking commit 2f6c9ca3cd0b (target/arm: Convert T16 data-processing (two low regs))
47/69 Checking commit bfba5bf520fa (target/arm: Convert T16 load/store (register offset))
48/69 Checking commit c0275cfb2490 (target/arm: Convert T16 load/store (immediate offset))
49/69 Checking commit af56e9a31ade (target/arm: Convert T16 add pc/sp (immediate))
50/69 Checking commit 1acf8f6a401f (target/arm: Convert T16 load/store multiple)
51/69 Checking commit d92915a5080d (target/arm: Convert T16 add/sub (3 low, 2 low and imm))
52/69 Checking commit cc1634df1fa7 (target/arm: Convert T16 one low register and immediate)
53/69 Checking commit f004a7ce03e9 (target/arm: Convert T16 branch and exchange)
54/69 Checking commit 9ab6de5cc9fe (target/arm: Convert T16 add, compare, move (two high registers))
55/69 Checking commit 75466c74c63b (target/arm: Convert T16 adjust sp (immediate))
56/69 Checking commit 8bfb8e3d1859 (target/arm: Convert T16, extract)
57/69 Checking commit 3ec6264bee2e (target/arm: Convert T16, Change processor state)
58/69 Checking commit 5021591b3dac (target/arm: Convert T16, Reverse bytes)
59/69 Checking commit 0b3fed7d9540 (target/arm: Convert T16, nop hints)
60/69 Checking commit bdac1b8c584b (target/arm: Split gen_nop_hint)
61/69 Checking commit 5c1ac2f5c6b9 (target/arm: Convert T16, push and pop)
62/69 Checking commit d0ec6df88c06 (target/arm: Convert T16, Conditional branches, Supervisor call)
63/69 Checking commit ac594802b762 (target/arm: Convert T16, Miscellaneous 16-bit instructions)
64/69 Checking commit fd73031d10d7 (target/arm: Convert T16, shift immediate)
65/69 Checking commit 7c2aede1dd5f (target/arm: Convert T16, load (literal))
66/69 Checking commit 1061d1b051a9 (target/arm: Convert T16, Unconditional branch)
67/69 Checking commit e36cea5616a4 (target/arm: Convert T16, long branches)
68/69 Checking commit 10d4d3d1b070 (target/arm: Clean up disas_thumb_insn)
69/69 Checking commit f240e8f55d8b (target/arm: Inline gen_bx_im into callers)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190904193059.26202-1-richard.henderson@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com