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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FjDIKcJDagE4KvmbL7+MpEBImmBNGJkd778M5x6AXXs=; b=UGBjdgwLFxZQx/7pCfVP8X7GevREYhNUXRnu5/WhhS3Dsv/v5o4cV4hg2C57d8LLK9 WemmVHXsSrwYfz6RZq7JkIWRNh3EoG3qdTis/hP4Euey8urPGn/7fbFaVddiXPvnPg6y qbavQnIApVlH1A50cgjvtr+dylOE/8x5OT75eidBdTUvDZWws17i1u1+pGhTYL37dA5A tHIMgUkSojAZiWhT0nxdlCTksQfTRzyjmgNl0vOzHvxaMnCuFz1KpctmTxqc3vRloKhD KCYQYEvtIoLk8YxGujIxkmEKE7zjDmhUZUhZ7FeEIlbAMBC9mQuPUxbOiiz2cPzfoo/M qweQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FjDIKcJDagE4KvmbL7+MpEBImmBNGJkd778M5x6AXXs=; b=pxMbrcJN2upH5yxOwWgpu2/488/YlWN6zHCYBmSmzC0JNORPVGvkMSUkkhkX2JDEXt hD3PJ1f0e/yj21iWCcMClthcPoZxBV7gDJWlCmAQdierIZjijyyMgYqo/F3vaCxdJbCA sCFhkaS6M6yP6mMN6HrIvNq827kx4Dr+YT9WaP74ugW4Gl5jnBEN0EzZ3dpIlTXUL2R2 LRNyQhM2856wewnUCCM6quJ8CbFW9ovixFas4N42GU473Kj61FMMoNlNPBNc5+GtTkZo V85aSepT353oqMe1muFp/xtfYZJaRYiMv3qK+PWRE0RLzizunBb6kOEXrfvanydCqF9U z1Fg== X-Gm-Message-State: APjAAAVqJXci8ShJyo5LHpapqC7SX6F8dxQsduTtvvEIp/6yeCsPaDnp SQfuZ5fbFBUEdUtd9BEvMyyxRSU17OQ= X-Google-Smtp-Source: APXvYqyqccW8btYoqgllDrn7+3LpHRtsWtTHd29gzh21bx4YRhFMAHF8CdWmrrRj4yUbeAu9ZjCCoA== X-Received: by 2002:aa7:9508:: with SMTP id b8mr31570203pfp.36.1567625462903; Wed, 04 Sep 2019 12:31:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:51 -0700 Message-Id: <20190904193059.26202-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v4 01/69] target/arm: Use store_reg_from_load in thumb2 code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This function already includes the test for an interworking write to PC from a load. Change the T32 LDM implementation to match the A32 LDM implementation. For LDM, the reordering of the tests does not change valid behaviour because the only case that differs is has rn =3D=3D 15, which is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b0d32ff8c9..a39f792463 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9742,13 +9742,11 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) /* Load. */ tmp =3D tcg_temp_new_i32(); gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i =3D=3D 15) { - gen_bx_excret(s, tmp); - } else if (i =3D=3D rn) { + if (i =3D=3D rn) { loaded_var =3D tmp; loaded_base =3D 1; } else { - store_reg(s, i, tmp); + store_reg_from_load(s, i, tmp); } } else { /* Store. */ @@ -10889,11 +10887,7 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_i32(addr); goto illegal_op; } - if (rs =3D=3D 15) { - gen_bx_excret(s, tmp); - } else { - store_reg(s, rs, tmp); - } + store_reg_from_load(s, rs, tmp); } else { /* Store. */ tmp =3D load_reg(s, rs); --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567625666; cv=none; d=zoho.com; s=zohoarc; b=VMtJ11woBxLT6RC/BdcoOHqEM/zfJFso1hg8fnQZ6kMlVsfHbKlV5RmOtITZ0OzLdhhC64TcSfeZDduYldqoKSuU8axfanhUIMeHXZvIBtP3roneJd9XX0TMbtYd7QFsQ14S7fHnavEMR3a2BiQpe5WIbtx2aNmLyW7+gKVcFro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567625666; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=NBzAHUlZzheDevf0bsXniXn3jInVmGNWWYOMzwYImOs=; b=RSqofx17JG5GyK+60HzrJurd7Jzc8n1Ene/xt+3S37gwk1MzpF2me28WU8CNBQN0XNCgH3/luywpPJILyYolKqhFnTzgP6emhkcvYuEXemMTWVYvJekwIcKC8O+iWUyg9UD49zpOiJXtBukV9uy4Lgo0ke5AISomUkD9cyLl2ec= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156762566669971.17865861658436; Wed, 4 Sep 2019 12:34:26 -0700 (PDT) Received: from localhost ([::1]:37552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b2t-0006sv-0H for importer@patchew.org; Wed, 04 Sep 2019 15:34:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39694) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5azj-000443-OW for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5azh-000233-LJ for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:07 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:34493) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5azh-000223-DT for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:05 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d3so14306plr.1 for ; Wed, 04 Sep 2019 12:31:05 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NBzAHUlZzheDevf0bsXniXn3jInVmGNWWYOMzwYImOs=; b=PKPWhUOfdKlfW1ND0j1hjvfaxn6oOmd+JQ5mkfiVBiWjXduZm8Yr8dNyFV3yPVjHYf A0FWvxcjlh+k3CzZdoFJDqeaCW2RD6xyTFzsimxjmx2ekolc5yxgC3BNu9ZXny+ZmyaF 4Sbx8AySsfE0aS+oxsWivlEOSLB4UFiWdkbP1gHYc4iZeRTSVNx76vmEfMzk6zEcFJCJ dOLal0p6Ic/udlEq+Oz/Qz101gDe6EUqhrMIqGVYkDwv4xA7C7VY6LNqUhS5zNFTb+1P gwUcJo2vZROoJ1BVteOzzGQoo7rVRPUMUAQQs2RfxfnFFCf/7xydmCJ7laCz6qPtw+GZ y7Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NBzAHUlZzheDevf0bsXniXn3jInVmGNWWYOMzwYImOs=; b=nGtjEoi7Ccj9i22RRpPvmyIN6tSMrJONkceKAWvWho/UThmhZ+BgYVU44AS7eYdZs5 GcnCwu84B83OMjCP3ZoE7o4tujOXpvC6xAO8TMuF7CXCbKOqk31ZpdLIjNzM7C7sL2YP Tg1g+8lzpEBX+SSVr/i0XvPSx+Cw1c+GU0OtPsk3ouxVcPQxEMBdHlNOySCpsk+YRjSY rnqOBOl3T5mydjUBkKDshXopdC8KT0IF27V0Fug29Fk12WdVa3jANB2QwLnpSM4lCb4S avR3W6EML2reibyL7FBd4fp6CnmmTDMMH2LAubdArycBGJKgSiNhEh/9jI/DHijFsaEe 6vSw== X-Gm-Message-State: APjAAAW5ab1hqhjDFZVKHESoEamYq1EogKpiHOyZc7m66MNgBCDNNglV vbU9rJdBjL9MSG6s8jcHEas3LfiuE2w= X-Google-Smtp-Source: APXvYqzf5ldTE8qdH0mj91+uE/ADmds+KnFBOKtWCEOecIE3rXLmCzXQgYDEXFhJyWsdTT3weo7L7Q== X-Received: by 2002:a17:902:850a:: with SMTP id bj10mr2755063plb.254.1567625463978; Wed, 04 Sep 2019 12:31:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:52 -0700 Message-Id: <20190904193059.26202-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62f Subject: [Qemu-devel] [PATCH v4 02/69] target/arm: Add stubs for aa32 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Add the infrastructure that will become the new decoder. No instructions adjusted so far. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 31 ++++++++++++++++++++++++++++++- target/arm/Makefile.objs | 18 ++++++++++++++++++ target/arm/a32-uncond.decode | 23 +++++++++++++++++++++++ target/arm/a32.decode | 23 +++++++++++++++++++++++ target/arm/t32.decode | 20 ++++++++++++++++++++ 5 files changed, 114 insertions(+), 1 deletion(-) create mode 100644 target/arm/a32-uncond.decode create mode 100644 target/arm/a32.decode create mode 100644 target/arm/t32.decode diff --git a/target/arm/translate.c b/target/arm/translate.c index a39f792463..07674d223c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7683,6 +7683,18 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } =20 +/* + * Include the generated decoders. + */ + +#include "decode-a32.inc.c" +#include "decode-a32-uncond.inc.c" +#include "decode-t32.inc.c" + +/* + * Legacy decoder. + */ + static void disas_arm_insn(DisasContext *s, unsigned int insn) { unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; @@ -7701,7 +7713,8 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) return; } cond =3D insn >> 28; - if (cond =3D=3D 0xf){ + + if (cond =3D=3D 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we * choose to UNDEF. In ARMv5 and above the space is used * for miscellaneous unconditional instructions. @@ -7709,6 +7722,11 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) ARCH(5); =20 /* Unconditional instructions. */ + if (disas_a32_uncond(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if (((insn >> 25) & 7) =3D=3D 1) { /* NEON Data processing. */ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -7923,6 +7941,12 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) next instruction */ arm_skip_unless(s, cond); } + + if (disas_a32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if ((insn & 0x0f900000) =3D=3D 0x03000000) { if ((insn & (1 << 21)) =3D=3D 0) { ARCH(6T2); @@ -9414,6 +9438,11 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) ARCH(6T2); } =20 + if (disas_t32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + rn =3D (insn >> 16) & 0xf; rs =3D (insn >> 12) & 0xf; rd =3D (insn >> 8) & 0xf; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 5cafc1eb6c..7806b4dac0 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/a= rm/vfp-uncond.decode $(D $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ "GEN", $(TARGET_DIR)$@) =20 +target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.deco= de $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c +target/arm/translate.o: target/arm/decode-a32.inc.c +target/arm/translate.o: target/arm/decode-a32-uncond.inc.c +target/arm/translate.o: target/arm/decode-t32.inc.c =20 obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode new file mode 100644 index 0000000000..8dee26d3b6 --- /dev/null +++ b/target/arm/a32-uncond.decode @@ -0,0 +1,23 @@ +# A32 unconditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All insns that have 0xf in insn[31:28] are decoded here. +# All of those that have a COND field in insn[31:28] are in a32.decode +# diff --git a/target/arm/a32.decode b/target/arm/a32.decode new file mode 100644 index 0000000000..a3e6e8c1c2 --- /dev/null +++ b/target/arm/a32.decode @@ -0,0 +1,23 @@ +# A32 conditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All of the insn that have a COND field in insn[31:28] are here. +# All insns that have 0xf in insn[31:28] are in a32-uncond.decode. +# diff --git a/target/arm/t32.decode b/target/arm/t32.decode new file mode 100644 index 0000000000..ac01fb6958 --- /dev/null +++ b/target/arm/t32.decode @@ -0,0 +1,20 @@ +# Thumb2 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567625702; cv=none; d=zoho.com; s=zohoarc; b=UtKtZX4TRhSdMWpYGMMys9ncRkvVvBjK87w8kivJGksxhP7U96OywDr7KhgyO6ERfhqw6iEgCOZ3HhBLaCaCSOOjO04ABvkTQQCe5rLrBpHWEFieWUIf1riO/nYaMiQinwdZ0gq1EAHOYxQL+p8aXvDHaR4tAh3rTbyhWlwsIBw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567625702; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=IYs4/Iy+m5flK8PpSYLGsEq72fMMXSyXbIuQC71eMFA=; b=V7Gw8cgUSYN5AVcG/hNsZlcyYqMwCBf/LhhBs+htTBNMfBdAC2JhsCCcxQme37ZTfaNfO18x8HOiqrxyKaCmoraS7wvglYJ0TDv9wUJ7yUY/dp3scqlEY6AP176+Or0TAi08dXTm6pTFAVYdwilqZt479Gbpwz5mcYebP4tNSTk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567625702908306.79239157754785; Wed, 4 Sep 2019 12:35:02 -0700 (PDT) Received: from localhost ([::1]:37556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b3T-0007RI-6u for importer@patchew.org; Wed, 04 Sep 2019 15:34:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39725) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5azl-00046P-Ba for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5azi-00024E-RI for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:09 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:34212) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5azi-00023S-J6 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:06 -0400 Received: by mail-pl1-x642.google.com with SMTP id d3so14348plr.1 for ; Wed, 04 Sep 2019 12:31:06 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IYs4/Iy+m5flK8PpSYLGsEq72fMMXSyXbIuQC71eMFA=; b=MJZSDnSedVUF2Yw92eKjiS4lKQA5XXk082YzKImw2SNCvz4p671CLn97jlE/qlr+e4 rGVCrv6BFvWnDgPzCqclIF0JFlWttY78kjNwFzyJEsCKfhKH6WnRgLuvi3oC4JH1YO4C oA4u8DR75EYb9CSQsFjr/7wuYhZrje0PIakDcHsW9NMr5HSPXzALnxtmgEm2CvxHQuvy DGY8Z5iDeJq13MHDEW5D4ALyxQkjPSK7lzb8xqAfyzw31+HYXTMkmSnAJrSgaQBHFIJy 39kl4OSfy/xEJSsa86LTMd7/PU0mkAnpHsIxyYS5TzW0yRcUbtXwhmFjZGV+KuF0ajKO 4gzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IYs4/Iy+m5flK8PpSYLGsEq72fMMXSyXbIuQC71eMFA=; b=sXp7433VyevP8XL67yY+z6KSxnMb4abkR0SA8IN2n4PQcSYtKU+3Fx+hSYEPhxAqVP JQxKcFZmBKDY5le9YynW31s9CV606CIc2Os6BDvLYMV4Vp0Xeg/rpAaNoxEJes8lay6l 3zJocWE8Dz82qL4Ht2DpitLGTmta6HQ5ftXZwyfDOH71eyoqKKTe5Vzy2j/FdQ5GZBpk /rPLndiWtgnFhX/gG81jAmSXp7G4WdpaGrWPFt8L6wliln9f9hT4wUHedDU7sSYvk/Kf uP3jbyfp8d3PPoXYIf1xM6xV/vbPn7JZFXxUn+e/T+sRtT9d4niAu0tAZ6wsoOSxJast bg7A== X-Gm-Message-State: APjAAAWlR3hTL9UIyvbaG1qZrdMxlbWKUaLx1mDlSdoKGKbKW4KfXmA4 kS0M530DMlK7U+SdNS961k5Lpou8xAM= X-Google-Smtp-Source: APXvYqyFJuNH3F28p/59DadhAuGVhEBGFvbuP4uJaSwsN/KblQuUbPTZzHI4886EW34px1VQzABGIw== X-Received: by 2002:a17:902:7d98:: with SMTP id a24mr23920531plm.271.1567625465201; Wed, 04 Sep 2019 12:31:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:53 -0700 Message-Id: <20190904193059.26202-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v4 03/69] target/arm: Convert Data Processing (register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for user/hyp check. --- target/arm/translate.c | 236 ++++++++++++++++++++++++++++++++++------- target/arm/a32.decode | 28 +++++ target/arm/t32.decode | 43 ++++++++ 3 files changed, 271 insertions(+), 36 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 07674d223c..cb97f5b22d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7691,6 +7691,204 @@ static void arm_skip_unless(DisasContext *s, uint32= _t cond) #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" =20 +/* Helpers to swap operands for reverse-subtract. */ +static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_sub_i32(dst, b, a); +} + +static void gen_rsb_CC(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_CC(dst, b, a); +} + +static void gen_rsc(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_carry(dest, b, a); +} + +static void gen_rsc_CC(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sbc_CC(dest, b, a); +} + +/* + * Helpers for the data processing routines. + * + * After the computation store the results back. + * This may be suppressed altogether (STREG_NONE), require a runtime + * check against the stack limits (STREG_SP_CHECK), or generate an + * exception return. Oh, or store into a register. + * + * Always return true, indicating success for a trans_* function. + */ +typedef enum { + STREG_NONE, + STREG_NORMAL, + STREG_SP_CHECK, + STREG_EXC_RET, +} StoreRegKind; + +static bool store_reg_kind(DisasContext *s, int rd, + TCGv_i32 val, StoreRegKind kind) +{ + switch (kind) { + case STREG_NONE: + tcg_temp_free_i32(val); + return true; + case STREG_NORMAL: + /* See ALUWritePC: Interworking only from a32 mode. */ + if (s->thumb) { + store_reg(s, rd, val); + } else { + store_reg_bx(s, rd, val); + } + return true; + case STREG_SP_CHECK: + store_sp_checked(s, val); + return true; + case STREG_EXC_RET: + gen_exception_return(s, val); + return true; + } + g_assert_not_reached(); +} + +/* + * Data Processing (register) + * + * Operate, with set flags, one register source, + * one immediate shifted register source, and a destination. + */ +static bool op_s_rrr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp2 =3D load_reg(s, a->rm); + gen_arm_shift_im(tmp2, a->shty, a->shim, logic_cc); + tmp1 =3D load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp; + + tmp =3D load_reg(s, a->rm); + gen_arm_shift_im(tmp, a->shty, a->shim, logic_cc); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return store_reg_kind(s, a->rd, tmp, kind); +} + +#define DO_ANY3(NAME, OP, L, K) \ + static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ + { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } + +#define DO_ANY2(NAME, OP, L, K) \ + static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ + { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } + +#define DO_CMP2(NAME, OP, L) \ + static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ + { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } + +DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) +DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) +DO_ANY3(ORR, tcg_gen_or_i32, a->s, STREG_NORMAL) +DO_ANY3(BIC, tcg_gen_andc_i32, a->s, STREG_NORMAL) + +DO_ANY3(RSB, a->s ? gen_rsb_CC : gen_rsb, false, STREG_NORMAL) +DO_ANY3(ADC, a->s ? gen_adc_CC : gen_add_carry, false, STREG_NORMAL) +DO_ANY3(SBC, a->s ? gen_sbc_CC : gen_sub_carry, false, STREG_NORMAL) +DO_ANY3(RSC, a->s ? gen_rsc_CC : gen_rsc, false, STREG_NORMAL) + +DO_CMP2(TST, tcg_gen_and_i32, true) +DO_CMP2(TEQ, tcg_gen_xor_i32, true) +DO_CMP2(CMN, gen_add_CC, false) +DO_CMP2(CMP, gen_sub_CC, false) + +DO_ANY3(ADD, a->s ? gen_add_CC : tcg_gen_add_i32, false, + a->rd =3D=3D 13 && a->rn =3D=3D 13 ? STREG_SP_CHECK : STREG_NORMAL) + +/* + * Note for the computation of StoreRegKind we return out of the + * middle of the functions that are expanded by DO_ANY3, and that + * we modify a->s via that parameter before it is used by OP. + */ +DO_ANY3(SUB, a->s ? gen_sub_CC : tcg_gen_sub_i32, false, + ({ + StoreRegKind ret =3D STREG_NORMAL; + if (a->rd =3D=3D 15 && a->s) { + /* + * See ALUExceptionReturn: + * In User mode, UNPREDICTABLE; we choose UNDEF. + * In Hyp mode, UNDEFINED. + */ + if (IS_USER(s) || s->current_el =3D=3D 2) { + unallocated_encoding(s); + return true; + } + /* There is no writeback of nzcv to PSTATE. */ + a->s =3D 0; + ret =3D STREG_EXC_RET; + } else if (a->rd =3D=3D 13 && a->rn =3D=3D 13) { + ret =3D STREG_SP_CHECK; + } + ret; + })) + +DO_ANY2(MOV, tcg_gen_mov_i32, a->s, + ({ + StoreRegKind ret =3D STREG_NORMAL; + if (a->rd =3D=3D 15 && a->s) { + /* + * See ALUExceptionReturn: + * In User mode, UNPREDICTABLE; we choose UNDEF. + * In Hyp mode, UNDEFINED. + */ + if (IS_USER(s) || s->current_el =3D=3D 2) { + unallocated_encoding(s); + return true; + } + /* There is no writeback of nzcv to PSTATE. */ + a->s =3D 0; + ret =3D STREG_EXC_RET; + } else if (a->rd =3D=3D 13) { + ret =3D STREG_SP_CHECK; + } + ret; + })) + +DO_ANY2(MVN, tcg_gen_not_i32, a->s, STREG_NORMAL) + +/* + * ORN is only available with T32, so there is no register-shifted-register + * form of the insn. Using the DO_ANY3 macro would create an unused funct= ion. + */ +static bool trans_ORN_rrri(DisasContext *s, arg_s_rrr_shi *a) +{ + return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); +} + +#undef DO_ANY3 +#undef DO_ANY2 +#undef DO_CMP2 + /* * Legacy decoder. */ @@ -9305,13 +9503,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uin= t32_t pc, uint32_t insn) return true; } =20 -/* Return true if this is a Thumb-2 logical op. */ -static int -thumb2_logic_op(int op) -{ - return (op < 8); -} - /* Generate code for a Thumb-2 data processing operation. If CONDS is non= zero then set condition code flags based on the result of the operation. If SHIFTER_OUT is nonzero then set the carry flag for logical operations @@ -9399,8 +9590,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32= _t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int shiftop; - int conds; int logic_cc; =20 /* @@ -9830,33 +10019,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) store_reg(s, rd, tmp); } else { /* Data processing register constant shift. */ - if (rn =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rn); - } - tmp2 =3D load_reg(s, rm); - - shiftop =3D (insn >> 4) & 3; - shift =3D ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - conds =3D (insn & (1 << 20)) !=3D 0; - logic_cc =3D (conds && thumb2_logic_op(op)); - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - if (rd =3D=3D 13 && - ((op =3D=3D 2 && rn =3D=3D 15) || - (op =3D=3D 8 && rn =3D=3D 13) || - (op =3D=3D 13 && rn =3D=3D 13))) { - /* MOV SP, ... or ADD SP, SP, ... or SUB SP, SP, ... */ - store_sp_checked(s, tmp); - } else if (rd !=3D 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 13: /* Misc data processing. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index a3e6e8c1c2..b23e83f17c 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -21,3 +21,31 @@ # All of the insn that have a COND field in insn[31:28] are here. # All insns that have 0xf in insn[31:28] are in a32-uncond.decode. # + +&s_rrr_shi s rd rn rm shim shty + +# Data-processing (register) + +@s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi +@s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi rn=3D0 +@S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \ + &s_rrr_shi s=3D1 rd=3D0 + +AND_rrri .... 000 0000 . .... .... ..... .. 0 .... @s_rrr_shi +EOR_rrri .... 000 0001 . .... .... ..... .. 0 .... @s_rrr_shi +SUB_rrri .... 000 0010 . .... .... ..... .. 0 .... @s_rrr_shi +RSB_rrri .... 000 0011 . .... .... ..... .. 0 .... @s_rrr_shi +ADD_rrri .... 000 0100 . .... .... ..... .. 0 .... @s_rrr_shi +ADC_rrri .... 000 0101 . .... .... ..... .. 0 .... @s_rrr_shi +SBC_rrri .... 000 0110 . .... .... ..... .. 0 .... @s_rrr_shi +RSC_rrri .... 000 0111 . .... .... ..... .. 0 .... @s_rrr_shi +TST_xrri .... 000 1000 1 .... 0000 ..... .. 0 .... @S_xrr_shi +TEQ_xrri .... 000 1001 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMP_xrri .... 000 1010 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMN_xrri .... 000 1011 1 .... 0000 ..... .. 0 .... @S_xrr_shi +ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi +MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi +BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi +MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ac01fb6958..7068596b99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -18,3 +18,46 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty + +# Data-processing (register) + +%imm5_12_6 12:3 6:2 + +@s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=3D%imm5_12_6 +@s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=3D%imm5_12_6 rn=3D0 +@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ + &s_rrr_shi shim=3D%imm5_12_6 s=3D1 rd=3D0 + +{ + TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi + AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi +} +BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi +{ + MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi + ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi + ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi + EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi +} +# PKHBT, PKHTB at opc1 =3D 0110 +{ + CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi + ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi +} +ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi +SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi +{ + CMP_xrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi + SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi +} +RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Jry4oWswzAPXeBy/WDcBrZ1+10Lxn1DFEJfUkAP4P00=; b=kaRIVmJQlGcC7fofMY4bXSi62XONCG/gw7TdtihxGNdETO6Bjn4Nssr6TLKDNsgVKV lGI7WBfmr1wPN6sJtIQJPg/jHOnWIFcBFnnjvOym5WaElNZGkNAYhnrvXL7otqIkrO6a r9m5QjEFhfjplM6qbIfRE3ZmYtYuzEMJdv53AYQtwah5ocGJiUsY81Jbvn33bj00INZI L50ZFJ4DJdH9xnOZ9heoFojJssIHIbrKeze3thvFUGvfh8/Ws21YQY2tRXot/kloiy8s iQ9Hs6e0bZmifJTfXG4zOMcJc5POW5QTBFpe/KxZEtYVkwshCzuicO4XTomz46i8rX9p 5JOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jry4oWswzAPXeBy/WDcBrZ1+10Lxn1DFEJfUkAP4P00=; b=o5eAr+eYlJ8qTGk9QwxRDA1wW5x+u0KlSJSv4qfOln2foZIv+kj8w0uiNv6gX1ynxU sGJj8ejoWKh5tbDeilBP7vGPakzocurY6LCodDQEYYVWuY4DSSHiYA5ksTiT5rktMEqs d9Wd/0zcqHGRMUwTH3zfpQwc8hQuaQpaTB1mXHpyNDC+u/fgK0tC1YyI9sF0rl+rGTMR 5KiNsvvXqlRbl+T/5MvaDMZXD5mK0KEiThO2NUyX6DJJNeIshac407cGQ9gWskxGAVOD inT8p8Icnk0/DR4rPU9YF03eEASlrcZWHrNwdAUzK/DPOnjBQGisowjGqlnuNKQRYf1G 4oGg== X-Gm-Message-State: APjAAAVKRe1uRiZFwKYCCNvjLUv52DaF6M4gh6aGE0fZxGikndWR+hfB D2WRoqIwGLStYckpqPrzJuPt8U+iLXE= X-Google-Smtp-Source: APXvYqwvttWCHoclzCV4SG2gipL6osx0TGua8brelxF3p+ExBlmunu77mcMwqS1KT4cx9B5JnqDQtA== X-Received: by 2002:a63:9e54:: with SMTP id r20mr37646975pgo.64.1567625466391; Wed, 04 Sep 2019 12:31:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:54 -0700 Message-Id: <20190904193059.26202-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 04/69] target/arm: Convert Data Processing (reg-shifted-reg) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 74 ++++++++++++++++++++++++++++++------------ target/arm/a32.decode | 27 +++++++++++++++ target/arm/t32.decode | 6 ++++ 3 files changed, 87 insertions(+), 20 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index cb97f5b22d..ff78b1bb74 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7795,17 +7795,66 @@ static bool op_s_rxr_shi(DisasContext *s, arg_s_rrr= _shi *a, return store_reg_kind(s, a->rd, tmp, kind); } =20 +/* + * Data-processing (register-shifted register) + * + * Operate, with set flags, one register source, + * one register shifted register source, and a destination. + */ +static bool op_s_rrr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 =3D load_reg(s, a->rs); + tmp2 =3D load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + tmp1 =3D load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 =3D load_reg(s, a->rs); + tmp2 =3D load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + + gen(tmp2, tmp2); + if (logic_cc) { + gen_logic_CC(tmp2); + } + return store_reg_kind(s, a->rd, tmp2, kind); +} + #define DO_ANY3(NAME, OP, L, K) \ static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ - { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } \ + static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ + { StoreRegKind k =3D (K); return op_s_rrr_shr(s, a, OP, L, k); } =20 #define DO_ANY2(NAME, OP, L, K) \ static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ - { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } \ + static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ + { StoreRegKind k =3D (K); return op_s_rxr_shr(s, a, OP, L, k); } =20 #define DO_CMP2(NAME, OP, L) \ static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ - { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } + { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ + static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ + { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } =20 DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) @@ -9590,7 +9639,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32= _t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int logic_cc; =20 /* * ARMv6-M supports a limited subset of Thumb2 instructions. @@ -10028,22 +10076,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) if (op < 4 && (insn & 0xf000) !=3D 0xf000) goto illegal_op; switch (op) { - case 0: /* Register controlled shift. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if ((insn & 0x70) !=3D 0) - goto illegal_op; - /* - * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx: - * - MOV, MOVS (register-shifted register), flagsetting - */ - op =3D (insn >> 21) & 3; - logic_cc =3D (insn & (1 << 20)) !=3D 0; - gen_arm_shift_reg(tmp, op, tmp2, logic_cc); - if (logic_cc) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; + case 0: /* Register controlled shift, in decodetree */ + goto illegal_op; case 1: /* Sign/zero extend. */ op =3D (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index b23e83f17c..8e0fb06d05 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -23,6 +23,7 @@ # =20 &s_rrr_shi s rd rn rm shim shty +&s_rrr_shr s rn rd rm rs shty =20 # Data-processing (register) =20 @@ -49,3 +50,29 @@ ORR_rrri .... 000 1100 . .... .... ..... .. 0 ..= .. @s_rrr_shi MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi + +# Data-processing (register-shifted register) + +@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr +@s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rn=3D0 +@S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rd=3D0 s=3D1 + +AND_rrrr .... 000 0000 . .... .... .... 0 .. 1 .... @s_rrr_shr +EOR_rrrr .... 000 0001 . .... .... .... 0 .. 1 .... @s_rrr_shr +SUB_rrrr .... 000 0010 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSB_rrrr .... 000 0011 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADD_rrrr .... 000 0100 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADC_rrrr .... 000 0101 . .... .... .... 0 .. 1 .... @s_rrr_shr +SBC_rrrr .... 000 0110 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSC_rrrr .... 000 0111 . .... .... .... 0 .. 1 .... @s_rrr_shr +TST_xrrr .... 000 1000 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +TEQ_xrrr .... 000 1001 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMP_xrrr .... 000 1010 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMN_xrrr .... 000 1011 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr +MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr +BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr +MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7068596b99..f0a73fa003 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -20,6 +20,7 @@ # =20 &s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty =20 # Data-processing (register) =20 @@ -61,3 +62,8 @@ SBC_rrri 1110101 1011 . .... 0 ... .... .... ....= @s_rrr_shi SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi } RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi + +# Data-processing (register-shifted register) + +MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ + &s_rrr_shr rn=3D0 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P5lvwtIACyV9ZUvbqn+xMJvNmsrDasaQ1Nh981WiZ3I=; b=jqk1yOxXu8nqgdIANgGh2oQA/T01kxFmI7pGTEwqEghq67eVHauoOHO72qm6snBso7 61Hqbnj6n2lwdZhLBmYKYI01z3EYe72V4Qqjg/yl5sQI5KcH3HA+jroPLZx48bIDIVst 0fLPXD+AnCfzYuaM/mlKLrFKJ2oGRSJWNINtrFh4R9RH6aYrJmEjuLqA1jIc2LT/2K3a VcgceRq7HNnNV2J0DAVpzjbZlFltke6PcA2mRrDWBe5V3i4T50H6QxdbeEdRbJy0RmiE y0ly3MWCTk8/J4Sl8lZrhiTwPtJ4cmuwqtK6KuPc5O4FyV7DILbOGfLDBDvgZfIaAFAF Jj3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P5lvwtIACyV9ZUvbqn+xMJvNmsrDasaQ1Nh981WiZ3I=; b=nO43YcFI4EAzelCk0/0vfXZwvZFTM0N/oq49iX+tPsmTTbFuYG1Nz0odaVcJYW8T2u vryujkjDQWBnv3+Y0DPZhHbzqMcXPSIVJ9/bIwAd9qd3v9iwkX3cFeqnuMYqnoxP92LU V2u/6fOw0hjQFcDqKKQSkTzXnXFSRPVT/I6Jgu7l2ewKBV+rqpeszsrdoHJYuCOAwa0r VSaJet36vYgT0K/N3I8mwSVb1lSUf+4MJreWA7idSKVAi97FEuYA0RFSatC6yvHBbydo ifHp+2bfbC2a3ICvxRaP3BDkOve8tNHqq88mr++xmOlc05d1HfFEpThRx6LxKD2f2gQj 0ldQ== X-Gm-Message-State: APjAAAVhRL1cxRNmBRCJ43t/tsvG2QnziZK/tdLONIVGh24v57TV0kQO yGqitEoWRd2ubtB7ushgd3Ytm5oi02U= X-Google-Smtp-Source: APXvYqzuxL1hITiitqLD7O8Tne79jy7GZmaIKEQIhocka/u7+wnqkhcPx195IbtNSaGLP5JonwrSrQ== X-Received: by 2002:a17:902:ff09:: with SMTP id f9mr414988plj.55.1567625467681; Wed, 04 Sep 2019 12:31:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:55 -0700 Message-Id: <20190904193059.26202-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v4 05/69] target/arm: Convert Data Processing (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 449 +++++++++++------------------------------ target/arm/a32.decode | 29 +++ target/arm/t32.decode | 42 ++++ 3 files changed, 186 insertions(+), 334 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ff78b1bb74..1222946ba4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -439,12 +439,6 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_temp_free_i32(t1); } =20 -/* Set CF to the top bit of var. */ -static void gen_set_CF_bit31(TCGv_i32 var) -{ - tcg_gen_shri_i32(cpu_CF, var, 31); -} - /* Set N and Z flags from var. */ static inline void gen_logic_CC(TCGv_i32 var) { @@ -857,25 +851,6 @@ void arm_gen_test_cc(int cc, TCGLabel *label) arm_free_cc(&cmp); } =20 -static const uint8_t table_logic_cc[16] =3D { - 1, /* and */ - 1, /* xor */ - 0, /* sub */ - 0, /* rsb */ - 0, /* add */ - 0, /* adc */ - 0, /* sbc */ - 0, /* rsc */ - 1, /* andl */ - 1, /* xorl */ - 0, /* cmp */ - 0, /* cmn */ - 1, /* orr */ - 1, /* mov */ - 1, /* bic */ - 1, /* mvn */ -}; - static inline void gen_set_condexec(DisasContext *s) { if (s->condexec_mask) { @@ -7683,6 +7658,48 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) arm_gen_test_cc(cond ^ 1, s->condlabel); } =20 + +/* + * Constant expanders for the decoders. + */ + +static int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +/* Return only the rotation part of T32ExpandImm. */ +static int t32_expandimm_rot(DisasContext *s, int x) +{ + return x & 0xc00 ? extract32(x, 7, 5) : 0; +} + +/* Return the unrotated immediate from T32ExpandImm. */ +static int t32_expandimm_imm(DisasContext *s, int x) +{ + int imm =3D extract32(x, 0, 8); + + switch (extract32(x, 8, 4)) { + case 0: /* XY */ + /* Nothing to do. */ + break; + case 1: /* 00XY00XY */ + imm *=3D 0x00010001; + break; + case 2: /* XY00XY00 */ + imm *=3D 0x01000100; + break; + case 3: /* XYXYXYXY */ + imm *=3D 0x01010101; + break; + default: + /* Rotated constant. */ + imm |=3D 0x80; + break; + } + return imm; +} + /* * Include the generated decoders. */ @@ -7838,23 +7855,82 @@ static bool op_s_rxr_shr(DisasContext *s, arg_s_rrr= _shr *a, return store_reg_kind(s, a->rd, tmp2, kind); } =20 +/* + * Data-processing (immediate) + * + * Operate, with set flags, one register source, + * one rotated immediate, and a destination. + * + * Note that logic_cc && a->rot setting CF based on the msb of the + * immediate is the reason why we must pass in the unrotated form + * of the immediate. + */ +static bool op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp1, tmp2; + uint32_t imm; + + imm =3D ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp2 =3D tcg_const_i32(imm); + tmp1 =3D load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return store_reg_kind(s, a->rd, tmp1, kind); +} + +static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc, StoreRegKind kind) +{ + TCGv_i32 tmp; + uint32_t imm; + + imm =3D ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp =3D tcg_const_i32(imm); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return store_reg_kind(s, a->rd, tmp, kind); +} + #define DO_ANY3(NAME, OP, L, K) \ static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ { StoreRegKind k =3D (K); return op_s_rrr_shi(s, a, OP, L, k); } \ static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ - { StoreRegKind k =3D (K); return op_s_rrr_shr(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rrr_shr(s, a, OP, L, k); } \ + static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \ + { StoreRegKind k =3D (K); return op_s_rri_rot(s, a, OP, L, k); } =20 #define DO_ANY2(NAME, OP, L, K) \ static bool trans_##NAME##_rxri(DisasContext *s, arg_s_rrr_shi *a) \ { StoreRegKind k =3D (K); return op_s_rxr_shi(s, a, OP, L, k); } \ static bool trans_##NAME##_rxrr(DisasContext *s, arg_s_rrr_shr *a) \ - { StoreRegKind k =3D (K); return op_s_rxr_shr(s, a, OP, L, k); } + { StoreRegKind k =3D (K); return op_s_rxr_shr(s, a, OP, L, k); } \ + static bool trans_##NAME##_rxi(DisasContext *s, arg_s_rri_rot *a) \ + { StoreRegKind k =3D (K); return op_s_rxi_rot(s, a, OP, L, k); } =20 #define DO_CMP2(NAME, OP, L) \ static bool trans_##NAME##_xrri(DisasContext *s, arg_s_rrr_shi *a) \ { return op_s_rrr_shi(s, a, OP, L, STREG_NONE); } \ static bool trans_##NAME##_xrrr(DisasContext *s, arg_s_rrr_shr *a) \ - { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } + { return op_s_rrr_shr(s, a, OP, L, STREG_NONE); } \ + static bool trans_##NAME##_xri(DisasContext *s, arg_s_rri_rot *a) \ + { return op_s_rri_rot(s, a, OP, L, STREG_NONE); } =20 DO_ANY3(AND, tcg_gen_and_i32, a->s, STREG_NORMAL) DO_ANY3(EOR, tcg_gen_xor_i32, a->s, STREG_NORMAL) @@ -7934,6 +8010,11 @@ static bool trans_ORN_rrri(DisasContext *s, arg_s_rr= r_shi *a) return op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); } =20 +static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) +{ + return op_s_rri_rot(s, a, tcg_gen_orc_i32, a->s, STREG_NORMAL); +} + #undef DO_ANY3 #undef DO_ANY2 #undef DO_CMP2 @@ -8471,182 +8552,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) } else if (((insn & 0x0e000000) =3D=3D 0 && (insn & 0x00000090) !=3D 0x90) || ((insn & 0x0e000000) =3D=3D (1 << 25))) { - int set_cc, logic_cc, shiftop; - - op1 =3D (insn >> 21) & 0xf; - set_cc =3D (insn >> 20) & 1; - logic_cc =3D table_logic_cc[op1] & set_cc; - - /* data processing instruction */ - if (insn & (1 << 25)) { - /* immediate operand */ - val =3D insn & 0xff; - shift =3D ((insn >> 8) & 0xf) * 2; - val =3D ror32(val, shift); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - if (logic_cc && shift) { - gen_set_CF_bit31(tmp2); - } - } else { - /* register */ - rm =3D (insn) & 0xf; - tmp2 =3D load_reg(s, rm); - shiftop =3D (insn >> 5) & 3; - if (!(insn & (1 << 4))) { - shift =3D (insn >> 7) & 0x1f; - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - } else { - rs =3D (insn >> 8) & 0xf; - tmp =3D load_reg(s, rs); - gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc); - } - } - if (op1 !=3D 0x0f && op1 !=3D 0x0d) { - rn =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rn); - } else { - tmp =3D NULL; - } - rd =3D (insn >> 12) & 0xf; - switch(op1) { - case 0x00: - tcg_gen_and_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x01: - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x02: - if (set_cc && rd =3D=3D 15) { - /* SUBS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_sub_CC(tmp, tmp, tmp2); - gen_exception_return(s, tmp); - } else { - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } else { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - } - break; - case 0x03: - if (set_cc) { - gen_sub_CC(tmp, tmp2, tmp); - } else { - tcg_gen_sub_i32(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x04: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x05: - if (set_cc) { - gen_adc_CC(tmp, tmp, tmp2); - } else { - gen_add_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x06: - if (set_cc) { - gen_sbc_CC(tmp, tmp, tmp2); - } else { - gen_sub_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x07: - if (set_cc) { - gen_sbc_CC(tmp, tmp2, tmp); - } else { - gen_sub_carry(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x08: - if (set_cc) { - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x09: - if (set_cc) { - tcg_gen_xor_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x0a: - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0b: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0c: - tcg_gen_or_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x0d: - if (logic_cc && rd =3D=3D 15) { - /* MOVS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_exception_return(s, tmp2); - } else { - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - } - break; - case 0x0e: - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - default: - case 0x0f: - tcg_gen_not_i32(tmp2, tmp2); - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - break; - } - if (op1 !=3D 0x0f && op1 !=3D 0x0d) { - tcg_temp_free_i32(tmp2); - } + /* Data-processing (reg, reg-shift-reg, imm). */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { /* other instructions */ op1 =3D (insn >> 24) & 0xf; @@ -9552,82 +9460,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uin= t32_t pc, uint32_t insn) return true; } =20 -/* Generate code for a Thumb-2 data processing operation. If CONDS is non= zero - then set condition code flags based on the result of the operation. - If SHIFTER_OUT is nonzero then set the carry flag for logical operations - to the high bit of T1. - Returns zero if the opcode is valid. */ - -static int -gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_ou= t, - TCGv_i32 t0, TCGv_i32 t1) -{ - int logic_cc; - - logic_cc =3D 0; - switch (op) { - case 0: /* and */ - tcg_gen_and_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 1: /* bic */ - tcg_gen_andc_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 2: /* orr */ - tcg_gen_or_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 3: /* orn */ - tcg_gen_orc_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 4: /* eor */ - tcg_gen_xor_i32(t0, t0, t1); - logic_cc =3D conds; - break; - case 8: /* add */ - if (conds) - gen_add_CC(t0, t0, t1); - else - tcg_gen_add_i32(t0, t0, t1); - break; - case 10: /* adc */ - if (conds) - gen_adc_CC(t0, t0, t1); - else - gen_adc(t0, t1); - break; - case 11: /* sbc */ - if (conds) { - gen_sbc_CC(t0, t0, t1); - } else { - gen_sub_carry(t0, t0, t1); - } - break; - case 13: /* sub */ - if (conds) - gen_sub_CC(t0, t0, t1); - else - tcg_gen_sub_i32(t0, t0, t1); - break; - case 14: /* rsb */ - if (conds) - gen_sub_CC(t0, t1, t0); - else - tcg_gen_sub_i32(t0, t1, t0); - break; - default: /* 5, 6, 7, 9, 12, 15. */ - return 1; - } - if (logic_cc) { - gen_logic_CC(t0); - if (shifter_out) - gen_set_CF_bit31(t1); - } - return 0; -} - /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { @@ -10909,60 +10741,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } } } else { - /* - * 0b1111_0x0x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate) - */ - int shifter_out =3D 0; - /* modified 12-bit immediate. */ - shift =3D ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >= > 12); - imm =3D (insn & 0xff); - switch (shift) { - case 0: /* XY */ - /* Nothing to do. */ - break; - case 1: /* 00XY00XY */ - imm |=3D imm << 16; - break; - case 2: /* XY00XY00 */ - imm |=3D imm << 16; - imm <<=3D 8; - break; - case 3: /* XYXYXYXY */ - imm |=3D imm << 16; - imm |=3D imm << 8; - break; - default: /* Rotated constant. */ - shift =3D (shift << 1) | (imm >> 7); - imm |=3D 0x80; - imm =3D imm << (32 - shift); - shifter_out =3D 1; - break; - } - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, imm); - rn =3D (insn >> 16) & 0xf; - if (rn =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rn); - } - op =3D (insn >> 21) & 0xf; - if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) !=3D 0, - shifter_out, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - rd =3D (insn >> 8) & 0xf; - if (rd =3D=3D 13 && rn =3D=3D 13 - && (op =3D=3D 8 || op =3D=3D 13)) { - /* ADD(S) SP, SP, imm or SUB(S) SP, SP, imm */ - store_sp_checked(s, tmp); - } else if (rd !=3D 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* Data-processing (modified immediate) */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 8e0fb06d05..286adcbf89 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -24,6 +24,7 @@ =20 &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty +&s_rri_rot s rn rd imm rot =20 # Data-processing (register) =20 @@ -76,3 +77,31 @@ ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .= ... @s_rrr_shr MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr + +# Data-processing (immediate) + +%a32extrot 8:4 !function=3Dtimes_2 + +@s_rri_rot ---- ... .... s:1 rn:4 rd:4 .... imm:8 \ + &s_rri_rot rot=3D%a32extrot +@s_rxi_rot ---- ... .... s:1 .... rd:4 .... imm:8 \ + &s_rri_rot rot=3D%a32extrot rn=3D0 +@S_xri_rot ---- ... .... . rn:4 .... .... imm:8 \ + &s_rri_rot rot=3D%a32extrot rd=3D0 s=3D1 + +AND_rri .... 001 0000 . .... .... ............ @s_rri_rot +EOR_rri .... 001 0001 . .... .... ............ @s_rri_rot +SUB_rri .... 001 0010 . .... .... ............ @s_rri_rot +RSB_rri .... 001 0011 . .... .... ............ @s_rri_rot +ADD_rri .... 001 0100 . .... .... ............ @s_rri_rot +ADC_rri .... 001 0101 . .... .... ............ @s_rri_rot +SBC_rri .... 001 0110 . .... .... ............ @s_rri_rot +RSC_rri .... 001 0111 . .... .... ............ @s_rri_rot +TST_xri .... 001 1000 1 .... 0000 ............ @S_xri_rot +TEQ_xri .... 001 1001 1 .... 0000 ............ @S_xri_rot +CMP_xri .... 001 1010 1 .... 0000 ............ @S_xri_rot +CMN_xri .... 001 1011 1 .... 0000 ............ @S_xri_rot +ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot +MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot +BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot +MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f0a73fa003..50cbe48cc8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -21,6 +21,7 @@ =20 &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot =20 # Data-processing (register) =20 @@ -67,3 +68,44 @@ RSB_rrri 1110101 1110 . .... 0 ... .... .... ...= . @s_rrr_shi =20 MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ &s_rrr_shr rn=3D0 + +# Data-processing (immediate) + +%t32extrot 26:1 12:3 0:8 !function=3Dt32_expandimm_rot +%t32extimm 26:1 12:3 0:8 !function=3Dt32_expandimm_imm + +@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=3D%t32extimm rot=3D%t32extrot +@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \ + &s_rri_rot imm=3D%t32extimm rot=3D%t32extrot rn=3D0 +@S_xri_rot ....... .... . rn:4 . ... .... ........ \ + &s_rri_rot imm=3D%t32extimm rot=3D%t32extrot s=3D1 rd=3D0 + +{ + TST_xri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot + AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot +} +BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot +{ + MOV_rxi 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot + ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot +} +{ + MVN_rxi 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot + ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot +} +{ + TEQ_xri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot + EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot +} +{ + CMN_xri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot + ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot +} +ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot +SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot +{ + CMP_xri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot + SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot +} +RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6btmBHWXRhaUGCf9AVKicEVV4kOt3nzzH+qx83dQ5AQ=; b=VtOPnJBSJajCEbK5RBhfRdqrKa8/5Y7p+PXRFMzyANdKd02+RDKChvmtaPB47EQRGA Ygm3Tz+trmE8jENaIm4RKobiMRO/1amNyAdavxevZJdYetfo+YEF6fF5TnKSLM7pw0af 1IerxfOj3g7j5CYXQv/okYJUEsgsh9JxNXq/81PfSjU6DmE4ThYwruF4p3F3eQ74d0up sKuFL9IZBPpe8IlyNA2LqiTehmLkHvzYGkk0OmCrWamWkfLkRXLobkbtcrMgYSSE9unp ebYNXXE+q7pENQvQ3/18dhi1b9FMIY3DCSKeVew7kS+CR1OssXJ0Fsf84lwiSOWxFQvg RBIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6btmBHWXRhaUGCf9AVKicEVV4kOt3nzzH+qx83dQ5AQ=; b=c36CMux0aiLR0s7P1os55hcmr+nLnMEeovhogbyCPh/bHjhX1HCgwAKafMP306wFX2 T+TUnfaREfVWEuJXN40GCBLQR2OIammNg0CZ/jE+misQd2GNteyW95FErR6pC++CfFQT 4B9JwITSMlz6v3OFwjR144nAKzyankVhvxIVjid31okN4s8/vbg1+2NvhCN2MMj1YeTV eXJjScjxsJQLi3xzvxZIwToMYdOPFSpGgMqMgr5Faf5gEqzAHc+pyGdh2QUMkiNHD3o/ qFdhlMwvnSderYL823XI/9+qEYesJswz3ciiDQSIdeDkvw6DfMAyGE/ARqhQOLyKBDZb 5lpg== X-Gm-Message-State: APjAAAW7u2bZKG4OAvzAcmSqH8fCR8aYnbOrqmBWd+izZCyLJk4iKHSY esh3Z/J1qEdG08CnKgkt55jv96jhUrI= X-Google-Smtp-Source: APXvYqwlMeF13eQ2VF29I4hSjZvuNVeS+6o8H8jWF25YoC9toq/5U0XD6Tv93xKoPC/cVqIB9zhJZg== X-Received: by 2002:a17:90a:234d:: with SMTP id f71mr6598365pje.125.1567625468647; Wed, 04 Sep 2019 12:31:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:56 -0700 Message-Id: <20190904193059.26202-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH v4 06/69] target/arm: Convert multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 248 +++++++++++++++++++++++------------------ target/arm/a32.decode | 17 +++ target/arm/t32.decode | 19 ++++ 3 files changed, 177 insertions(+), 107 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1222946ba4..9bcf1e0964 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8019,6 +8019,125 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rr= i_rot *a) #undef DO_ANY2 #undef DO_CMP2 =20 +/* + * Multiply and multiply accumulate + */ + +static bool op_mla(DisasContext *s, arg_s_rrrr *a, bool add) +{ + TCGv_i32 t1, t2; + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + if (add) { + t2 =3D load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + if (a->s) { + gen_logic_CC(t1); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_MUL(DisasContext *s, arg_MUL *a) +{ + return op_mla(s, a, false); +} + +static bool trans_MLA(DisasContext *s, arg_MLA *a) +{ + return op_mla(s, a, true); +} + +static bool trans_MLS(DisasContext *s, arg_MLS *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6T2) { + return false; + } + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + t2 =3D load_reg(s, a->ra); + tcg_gen_sub_i32(t1, t2, t1); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_mlal(DisasContext *s, arg_s_rrrr *a, bool uns, bool add) +{ + TCGv_i32 t0, t1, t2, t3; + + t0 =3D load_reg(s, a->rm); + t1 =3D load_reg(s, a->rn); + if (uns) { + tcg_gen_mulu2_i32(t0, t1, t0, t1); + } else { + tcg_gen_muls2_i32(t0, t1, t0, t1); + } + if (add) { + t2 =3D load_reg(s, a->ra); + t3 =3D load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + if (a->s) { + gen_logicq_cc(t0, t1); + } + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_UMULL(DisasContext *s, arg_UMULL *a) +{ + return op_mlal(s, a, true, false); +} + +static bool trans_SMULL(DisasContext *s, arg_SMULL *a) +{ + return op_mlal(s, a, false, false); +} + +static bool trans_UMLAL(DisasContext *s, arg_UMLAL *a) +{ + return op_mlal(s, a, true, true); +} + +static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) +{ + return op_mlal(s, a, false, true); +} + +static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 =3D load_reg(s, a->rm); + t1 =3D load_reg(s, a->rn); + t64 =3D gen_mulu_i64_i32(t0, t1); + gen_addq_lo(s, t64, a->ra); + gen_addq_lo(s, t64, a->rd); + gen_storeq_reg(s, a->ra, a->rd, t64); + tcg_temp_free_i64(t64); + return true; +} + /* * Legacy decoder. */ @@ -8565,71 +8684,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) sh =3D (insn >> 5) & 3; if (sh =3D=3D 0) { if (op1 =3D=3D 0x0) { - rd =3D (insn >> 16) & 0xf; - rn =3D (insn >> 12) & 0xf; - rs =3D (insn >> 8) & 0xf; - rm =3D (insn) & 0xf; - op1 =3D (insn >> 20) & 0xf; - switch (op1) { - case 0: case 1: case 2: case 3: case 6: - /* 32 bit mul */ - tmp =3D load_reg(s, rs); - tmp2 =3D load_reg(s, rm); - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 22)) { - /* Subtract (mls) */ - ARCH(6T2); - tmp2 =3D load_reg(s, rn); - tcg_gen_sub_i32(tmp, tmp2, tmp); - tcg_temp_free_i32(tmp2); - } else if (insn & (1 << 21)) { - /* Add */ - tmp2 =3D load_reg(s, rn); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; - case 4: - /* 64 bit mul double accumulate (UMAAL) */ - ARCH(6); - tmp =3D load_reg(s, rs); - tmp2 =3D load_reg(s, rm); - tmp64 =3D gen_mulu_i64_i32(tmp, tmp2); - gen_addq_lo(s, tmp64, rn); - gen_addq_lo(s, tmp64, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - break; - case 8: case 9: case 10: case 11: - case 12: case 13: case 14: case 15: - /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */ - tmp =3D load_reg(s, rs); - tmp2 =3D load_reg(s, rm); - if (insn & (1 << 22)) { - tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2); - } else { - tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2); - } - if (insn & (1 << 21)) { /* mult accumulate */ - TCGv_i32 al =3D load_reg(s, rn); - TCGv_i32 ah =3D load_reg(s, rd); - tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah); - tcg_temp_free_i32(al); - tcg_temp_free_i32(ah); - } - if (insn & (1 << 20)) { - gen_logicq_cc(tmp, tmp2); - } - store_reg(s, rn, tmp); - store_reg(s, rd, tmp2); - break; - default: - goto illegal_op; - } + /* Multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops= . */ + goto illegal_op; } else { rn =3D (insn >> 16) & 0xf; rd =3D (insn >> 12) & 0xf; @@ -10075,7 +10132,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ + case 0: /* 32 x 32 -> 32, in decodetree */ + goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; case 1: /* 16 x 16 -> 32 */ @@ -10092,18 +10150,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tmp =3D load_reg(s, rn); tmp2 =3D load_reg(s, rm); switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) { - tmp2 =3D load_reg(s, rs); - if (op) - tcg_gen_sub_i32(tmp, tmp2, tmp); - else - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 1: /* 16 x 16 -> 32 */ gen_mulxy(tmp, tmp2, op & 2, op & 1); tcg_temp_free_i32(tmp2); @@ -10233,36 +10279,24 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) gen_storeq_reg(s, rs, rd, tmp64); tcg_temp_free_i64(tmp64); } else { - if (op & 0x20) { - /* Unsigned 64-bit multiply */ - tmp64 =3D gen_mulu_i64_i32(tmp, tmp2); - } else { - if (op & 8) { - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - } else { - /* Signed 64-bit multiply */ - tmp64 =3D gen_muls_i64_i32(tmp, tmp2); - } + if ((op & 0x20) || !(op & 8)) { + /* Signed/unsigned 64-bit multiply, in decodetree */ + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + goto illegal_op; } - if (op & 4) { - /* umaal */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i64(tmp64); - goto illegal_op; - } - gen_addq_lo(s, tmp64, rs); - gen_addq_lo(s, tmp64, rd); - } else if (op & 0x40) { + /* smlalxy */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + goto illegal_op; + } + gen_mulxy(tmp, tmp2, op & 2, op & 1); + tcg_temp_free_i32(tmp2); + tmp64 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(tmp64, tmp); + tcg_temp_free_i32(tmp); + if (op & 0x40) { /* 64-bit accumulate. */ gen_addq(s, tmp64, rs, rd); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 286adcbf89..87bbb2eec2 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -25,6 +25,8 @@ &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot +&s_rrrr s rd rn rm ra +&rrrr rd rn rm ra =20 # Data-processing (register) =20 @@ -105,3 +107,18 @@ ORR_rri .... 001 1100 . .... .... ...........= . @s_rri_rot MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot + +# Multiply and multiply accumulate + +@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr +@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra= =3D0 +@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr + +MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn +MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn +UMAAL .... 0000 010 0 .... .... .... 1001 .... @rdamn +MLS .... 0000 011 0 .... .... .... 1001 .... @rdamn +UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn +UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn +SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn +SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 50cbe48cc8..40cc69aee3 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -22,6 +22,8 @@ &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra +&rrrr !extern rd rn rm ra =20 # Data-processing (register) =20 @@ -109,3 +111,20 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... .....= ... @s_rri_rot SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot + +# Multiply and multiply accumulate + +@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 +@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra= =3D0 s=3D0 +@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr + +{ + MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm + MLA 1111 1011 0000 .... .... .... 0000 .... @s0_rnadm +} +MLS 1111 1011 0000 .... .... .... 0001 .... @rnadm +SMULL 1111 1011 1000 .... .... .... 0000 .... @s0_rnadm +UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm +SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm +UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm +UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mUfMuu94nY9iTVUmT2HpXRX8/pvEI2tD109hkQpzr/w=; b=eTUNQP7nuw/1zXzNDy5hZ1YIGSvXVg8rujyUAG00PzwjJ3vzlL7jDdJeI9pE4q8dbh wCNZOn50+lnBnX1aXdMHrXtVdoIvy3v8rOoJMcLiOBBQoYT3WU+o3uwmMiw5h/NVi4/b IPtTBerwL7MkgFVN+BXAfrgO1Jmz8M8R04s9DcJOyhG8ReWUxe2pJu0nDa87qMlwHm5n weIQ9aat7rahADviAxFqNP9GC7LQ/7Fp7tCdbF7E/jQjvwkMyxUVp62VdQivWetcc3zq KCGMz6pYXRlJOtiFh9LxatENMrljJVVu03FfFAbR8uDP37+fzTlJeooBq1UwEtcjWvLB 318A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mUfMuu94nY9iTVUmT2HpXRX8/pvEI2tD109hkQpzr/w=; b=a58ElbmzxoEtb9O84NiRtz86fpcVKym9kotkCORgz4ZylfPPI78nDByHLDCHj0liaV dOQwiCuAny0MyMcZZQ+ILoJe5ZP8u2wQqJ7JIdr0p6B1anCjcJkx/FnV8ft+mLoOmBEs x1PJcPf4HEkuG0/P4yTP7W9P9U4hma16xisKvT3Wyux6pq1mbZSuZcU7zccQcM6NhUpl /vTbRP9zqmK1Q+LX4RrSzi9JiuPuQeYSqdnHHCWwzhVyDYDz66pEmqq/j69z1mtLZ6cp nmpnIyxtIOwVD21XqfsUkg9Yp8GzWbnyn7AMnSw7o+WXncJyUm63TGkOpRetkEbq4auf J1RQ== X-Gm-Message-State: APjAAAVYHRi64Txrs3fcPnHhr/RviW5ez1ttKsQJe4mCQTyaS2cs5FlT Mtjm1k4U7/EnrT0rPaf4kGxGJHwwq0o= X-Google-Smtp-Source: APXvYqySPakiBWbCu98zVf96FdYT6ybGHkVYoAjArSLBAeZk+1xF+mN/Z72wXUk4SxwtN7Uh3XIXEA== X-Received: by 2002:a17:90a:db0e:: with SMTP id g14mr4882317pjv.54.1567625469925; Wed, 04 Sep 2019 12:31:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:57 -0700 Message-Id: <20190904193059.26202-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v4 07/69] target/arm: Simplify UMAAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_mulu2_i32 and tcg_gen_add2_i32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 34 ++++++++++++---------------------- 1 file changed, 12 insertions(+), 22 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9bcf1e0964..8d70f15a4f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7346,21 +7346,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow= , int rhigh, TCGv_i64 val) store_reg(s, rhigh, tmp); } =20 -/* load a 32-bit value from a register and perform a 64-bit accumulate. */ -static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) -{ - TCGv_i64 tmp; - TCGv_i32 tmp2; - - /* Load value and extend to 64 bits. */ - tmp =3D tcg_temp_new_i64(); - tmp2 =3D load_reg(s, rlow); - tcg_gen_extu_i32_i64(tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_gen_add_i64(val, val, tmp); - tcg_temp_free_i64(tmp); -} - /* load and add a 64-bit value from a register pair. */ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) { @@ -8119,8 +8104,7 @@ static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) =20 static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, t2, zero; =20 if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8130,11 +8114,17 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL = *a) =20 t0 =3D load_reg(s, a->rm); t1 =3D load_reg(s, a->rn); - t64 =3D gen_mulu_i64_i32(t0, t1); - gen_addq_lo(s, t64, a->ra); - gen_addq_lo(s, t64, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_gen_mulu2_i32(t0, t1, t0, t1); + zero =3D tcg_const_i32(0); + t2 =3D load_reg(s, a->ra); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + t2 =3D load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(zero); + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); return true; } =20 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567626224; cv=none; d=zoho.com; s=zohoarc; b=Pzr89sglS8LHhYJqzlIDXqW0jtK7E796Ktm9LFrfzks3rLaq5zPDMlPSNWZbbanJ4SeYTKD64agiT0PY/ISRtr0D/EkyD5FHr0GVsWB/OYmE/x0j1xN2DiZejIPgDABZ6sSdaJ/1Os9W0HRq0yA1F2eCiclLxVapLnRBnvAUVEw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567626224; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=qTBjneugtZF+JoWXJ5FX48BYqpDgfu4BcdXmC9Vl7mc=; b=cqONabkjV4YMDb5YaglkFnYGPZonlxR8o9q83TaGTHl/DlT90JwrqJXkbq1RGH1VequcaL7T4342/IJZsZOXBpxU7SsDxeC45/PZVzs28ZYFWWscgJbmuZsKRqfh8cG5gTNe9L9mrxmrCeNOKWdJ+47M2se7OEnAgYfBdJoPCjo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567626224666637.7151048584444; Wed, 4 Sep 2019 12:43:44 -0700 (PDT) Received: from localhost ([::1]:37730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bBv-0007qx-23 for importer@patchew.org; Wed, 04 Sep 2019 15:43:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39845) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5azr-0004Ed-DL for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5azp-0002Aq-Bx for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:15 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:40180) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5azp-00029s-1q for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:13 -0400 Received: by mail-pf1-x430.google.com with SMTP id x127so1219634pfb.7 for ; Wed, 04 Sep 2019 12:31:12 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qTBjneugtZF+JoWXJ5FX48BYqpDgfu4BcdXmC9Vl7mc=; b=DThbwQFoX4lrYPGrFakxxGuxvnL9WS4y8KglsDchw1r2YrIJLI5zFITZGthASxkvKV 94ZwvDXjVXNLUeJoD0XXl70UilJ3M3LGBZN1FQAG7C4IbGwBmAXvsu+WjGSJvZTTM2HU HSJkt66aMtBxiAhCjy+XU9ZTO+ZGnJnxvhRF/KzHc+RiZdwreIq7l1VdvxDsCqQYkESW Iw8R0/pGnq/LySiMttD9wpipucZkVpM3QxaVDaX/Siq6IsLHxTs1q9msTIcpkh+Y8ly3 CfxZIz2pf7S/fIK16tY2YkMSqB/4wByf3C8017xXW+RYqZKCSt1kqenZLcId2r0rZkLu aTVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qTBjneugtZF+JoWXJ5FX48BYqpDgfu4BcdXmC9Vl7mc=; b=Pjagj5p2n+cnJhvnDyHGYx9eyh6JRHrw2zfmTPFD6XyYawVTJN2Ut2Zw4y2n5PWDXB 6zf7sJvTm+IVmPhpJSwOSxMifttqW1biGWA4eActmk8ogGZJRRwW9umq2CcmxLhxACZP yPV4B4BXA183bZK8mE/JXxud7nYIKsD02PMIAQSsmDYNaYV9Q60ORkOd5C0YH+JWGtJ/ jDTbgXbxKoPfJwQn+6O4iXtyGjCaoZUogdVV5vxOfo10+CXHcIMsUK7+ZUeGT5ioz/nm 2MhcMUSNlexESRvBLuC5teQSmb+SmhmpUxLCh9gyBeHRrzMrvWqsVNKi6xEMPJfurVcH SEFQ== X-Gm-Message-State: APjAAAUzdHr7hDJYN8PdUu2DDZh2flIIZNxSrAAY3okWd+Ipu8CY11wU HE4CyPz92zx42OBbXwNnC4BcVkPdKg0= X-Google-Smtp-Source: APXvYqx2oNVa2Ek+gdx0Ko+C4ZqqVYmkBtmIuwWV6W9A22cHRMzKFgR3+56cfbwHaR7KVqL2Jm4rmw== X-Received: by 2002:a17:90a:7783:: with SMTP id v3mr6417490pjk.109.1567625470998; Wed, 04 Sep 2019 12:31:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:29:58 -0700 Message-Id: <20190904193059.26202-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH v4 08/69] target/arm: Convert Saturating addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 75 +++++++++++++++++++++++++++--------------- target/arm/a32.decode | 10 ++++++ target/arm/t32.decode | 9 +++++ 3 files changed, 67 insertions(+), 27 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 8d70f15a4f..ddb2c764a1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8128,6 +8128,48 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *= a) return true; } =20 +/* + * Saturating addition and subtraction + */ + +static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 =3D load_reg(s, a->rm); + t1 =3D load_reg(s, a->rn); + if (doub) { + gen_helper_add_saturate(t1, cpu_env, t1, t1); + } + if (add) { + gen_helper_add_saturate(t0, cpu_env, t0, t1); + } else { + gen_helper_sub_saturate(t0, cpu_env, t0, t1); + } + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_QADDSUB(NAME, ADD, DOUB) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_qaddsub(s, a, ADD, DOUB); \ +} + +DO_QADDSUB(QADD, true, false) +DO_QADDSUB(QSUB, false, false) +DO_QADDSUB(QDADD, true, true) +DO_QADDSUB(QDSUB, false, true) + +#undef DO_QADDSUB + /* * Legacy decoder. */ @@ -8537,21 +8579,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) store_reg(s, rd, tmp); break; } - case 0x5: /* saturating add/subtract */ - ARCH(5TE); - rd =3D (insn >> 12) & 0xf; - rn =3D (insn >> 16) & 0xf; - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rn); - if (op1 & 2) - gen_helper_add_saturate(tmp2, cpu_env, tmp2, tmp2); - if (op1 & 1) - gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 0x5: + /* Saturating addition and subtraction. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x6: /* ERET */ if (op1 !=3D 3) { goto illegal_op; @@ -10024,18 +10055,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) op =3D ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { /* Saturating add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if (op & 1) - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp); - if (op & 2) - gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { switch (op) { case 0x0a: /* rbit */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 87bbb2eec2..7791be5590 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -27,6 +27,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr rd rn rm =20 # Data-processing (register) =20 @@ -122,3 +123,12 @@ UMULL .... 0000 100 . .... .... .... 1001 .= ... @s_rdamn UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn + +# Saturating addition and subtraction + +@rndm ---- .... .... rn:4 rd:4 .... .... rm:4 &rrr + +QADD .... 0001 0000 .... .... 0000 0101 .... @rndm +QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm +QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm +QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 40cc69aee3..7c6226e0af 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr !extern rd rn rm =20 # Data-processing (register) =20 @@ -117,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ......= .. @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra= =3D0 s=3D0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr =20 { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -128,3 +130,10 @@ UMULL 1111 1011 1010 .... .... .... 0000 ..= .. @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm + +# Data-processing (two source registers) + +QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm +QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm +QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm +QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567625928; cv=none; d=zoho.com; s=zohoarc; b=c5JEuMx1jsXvGPJBGnkD+E1eQk9Ev2wmcyTRCoYcQpI0pomN4cazeI/DjR6EzQn90TPK7MsIyLQKSHsntQ7xwV8YBTYHnd94IwjXn/NJs9vx1C2AfsGqKwvLm1bkZuJagqc7dIrQRVlEweA6B5ntZS75hT9/LwLCCDNsDrs1XmY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567625928; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=iwMY4Va0yfoxKscjE8xig8J8a9Pr7U82PT5LI3ovLKI=; b=nYAd9/tFLq5XWGizfTNJzZa3j7Oml/HeokTp9n5B4a9jmeqiKoBcOmWsSedF7yEw9UPTKpSnhxVcwIFLVuzqWNNBZ5qOttYHl0ylkuIloasvfdTCKS01fdXiIqNjz0P4i/fGs01PxJkMtsARCZkh67m/6s2jO9s9JOC4iZkxtfc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567625928666938.2564321849059; Wed, 4 Sep 2019 12:38:48 -0700 (PDT) Received: from localhost ([::1]:37632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b78-000393-NJ for importer@patchew.org; Wed, 04 Sep 2019 15:38:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39916) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5azt-0004Ho-SO for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5azq-0002Bv-92 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:17 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:42985) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5azp-0002Af-SD for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:14 -0400 Received: by mail-pl1-x644.google.com with SMTP id y1so10010965plp.9 for ; Wed, 04 Sep 2019 12:31:13 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v4 09/69] target/arm: Convert Halfword multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 218 +++++++++++++++++++++++------------------ target/arm/a32.decode | 20 ++++ target/arm/t32.decode | 29 ++++++ 3 files changed, 170 insertions(+), 97 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ddb2c764a1..5306e93470 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8170,6 +8170,117 @@ DO_QADDSUB(QDSUB, false, true) =20 #undef DO_QADDSUB =20 +/* + * Halfword multiply and multiply accumulate + */ + +static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, + int add_long, bool nt, bool mt) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + gen_mulxy(t0, t1, nt, mt); + tcg_temp_free_i32(t1); + + switch (add_long) { + case 0: + store_reg(s, a->rd, t0); + break; + case 1: + t1 =3D load_reg(s, a->ra); + gen_helper_add_setq(t0, cpu_env, t0, t1); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + break; + case 2: + t64 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(t64, t0); + tcg_temp_free_i32(t0); + gen_addq(s, t64, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, t64); + tcg_temp_free_i64(t64); + break; + default: + g_assert_not_reached(); + } + return true; +} + +#define DO_SMLAX(NAME, add, nt, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlaxxx(s, a, add, nt, mt); \ +} + +DO_SMLAX(SMULBB, 0, 0, 0) +DO_SMLAX(SMULBT, 0, 0, 1) +DO_SMLAX(SMULTB, 0, 1, 0) +DO_SMLAX(SMULTT, 0, 1, 1) + +DO_SMLAX(SMLABB, 1, 0, 0) +DO_SMLAX(SMLABT, 1, 0, 1) +DO_SMLAX(SMLATB, 1, 1, 0) +DO_SMLAX(SMLATT, 1, 1, 1) + +DO_SMLAX(SMLALBB, 2, 0, 0) +DO_SMLAX(SMLALBT, 2, 0, 1) +DO_SMLAX(SMLALTB, 2, 1, 0) +DO_SMLAX(SMLALTT, 2, 1, 1) + +#undef DO_SMLAX + +static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) +{ + TCGv_i32 t0, t1; + TCGv_i64 t64; + + if (!ENABLE_ARCH_5TE) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + if (mt) { + tcg_gen_sari_i32(t1, t1, 16); + } else { + gen_sxth(t1); + } + t64 =3D gen_muls_i64_i32(t0, t1); + tcg_gen_shri_i64(t64, t64, 16); + t1 =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(t1, t64); + tcg_temp_free_i64(t64); + if (add) { + t0 =3D load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t0); + tcg_temp_free_i32(t0); + } + store_reg(s, a->rd, t1); + return true; +} + +#define DO_SMLAWX(NAME, add, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlawx(s, a, add, mt); \ +} + +DO_SMLAWX(SMULWB, 0, 0) +DO_SMLAWX(SMULWT, 0, 1) +DO_SMLAWX(SMLAWB, 1, 0) +DO_SMLAWX(SMLAWT, 1, 1) + +#undef DO_SMLAWX + /* * Legacy decoder. */ @@ -8636,56 +8747,13 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) } break; } - case 0x8: /* signed multiply */ + case 0x8: case 0xa: case 0xc: case 0xe: - ARCH(5TE); - rs =3D (insn >> 8) & 0xf; - rn =3D (insn >> 12) & 0xf; - rd =3D (insn >> 16) & 0xf; - if (op1 =3D=3D 1) { - /* (32 * 16) >> 16 */ - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - if (sh & 4) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 =3D gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if ((sh & 2) =3D=3D 0) { - tmp2 =3D load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } else { - /* 16 * 16 */ - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - gen_mulxy(tmp, tmp2, sh & 2, sh & 4); - tcg_temp_free_i32(tmp2); - if (op1 =3D=3D 2) { - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rn, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - if (op1 =3D=3D 0) { - tmp2 =3D load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } - } - break; + /* Halfword multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; default: goto illegal_op; } @@ -10143,13 +10211,14 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32, in decodetree */ + case 0: /* 32 x 32 -> 32 */ + case 1: /* 16 x 16 -> 32 */ + case 3: /* 32 * 16 -> 32msb */ + /* in decodetree */ goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; - case 1: /* 16 x 16 -> 32 */ case 2: /* Dual multiply add. */ - case 3: /* 32 * 16 -> 32msb */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { @@ -10161,15 +10230,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tmp =3D load_reg(s, rn); tmp2 =3D load_reg(s, rm); switch ((insn >> 20) & 7) { - case 1: /* 16 x 16 -> 32 */ - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) { - tmp2 =3D load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ if (op) @@ -10193,23 +10253,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tcg_temp_free_i32(tmp2); } break; - case 3: /* 32 * 16 -> 32msb */ - if (op) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 =3D gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if (rs !=3D 15) - { - tmp2 =3D load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); if (rs !=3D 15) { @@ -10290,29 +10333,10 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) gen_storeq_reg(s, rs, rd, tmp64); tcg_temp_free_i64(tmp64); } else { - if ((op & 0x20) || !(op & 8)) { - /* Signed/unsigned 64-bit multiply, in decodetree */ - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); + /* Signed/unsigned 64-bit multiply, in decodetree */ tcg_temp_free_i32(tmp2); - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); tcg_temp_free_i32(tmp); - if (op & 0x40) { - /* 64-bit accumulate. */ - gen_addq(s, tmp64, rs, rd); - } - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); + goto illegal_op; } break; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 7791be5590..19d12e726b 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -114,6 +114,7 @@ MVN_rxi .... 001 1111 . 0000 .... ............= @s_rxi_rot @s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr @s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra= =3D0 @rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr +@rd0mn ---- .... ... . rd:4 .... rm:4 .... rn:4 &rrrr ra=3D0 =20 MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn @@ -132,3 +133,22 @@ QADD .... 0001 0000 .... .... 0000 0101 ..= .. @rndm QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm + +# Halfword multiply and multiply accumulate + +SMLABB .... 0001 0000 .... .... .... 1000 .... @rdamn +SMLABT .... 0001 0000 .... .... .... 1100 .... @rdamn +SMLATB .... 0001 0000 .... .... .... 1010 .... @rdamn +SMLATT .... 0001 0000 .... .... .... 1110 .... @rdamn +SMLAWB .... 0001 0010 .... .... .... 1000 .... @rdamn +SMULWB .... 0001 0010 .... 0000 .... 1010 .... @rd0mn +SMLAWT .... 0001 0010 .... .... .... 1100 .... @rdamn +SMULWT .... 0001 0010 .... 0000 .... 1110 .... @rd0mn +SMLALBB .... 0001 0100 .... .... .... 1000 .... @rdamn +SMLALBT .... 0001 0100 .... .... .... 1100 .... @rdamn +SMLALTB .... 0001 0100 .... .... .... 1010 .... @rdamn +SMLALTT .... 0001 0100 .... .... .... 1110 .... @rdamn +SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn +SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn +SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn +SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7c6226e0af..122a0537ed 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -118,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ......= .. @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra= =3D0 s=3D0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=3D0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr =20 { @@ -130,6 +131,34 @@ UMULL 1111 1011 1010 .... .... .... 0000 ..= .. @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm +{ + SMULWB 1111 1011 0011 .... 1111 .... 0000 .... @rn0dm + SMLAWB 1111 1011 0011 .... .... .... 0000 .... @rnadm +} +{ + SMULWT 1111 1011 0011 .... 1111 .... 0001 .... @rn0dm + SMLAWT 1111 1011 0011 .... .... .... 0001 .... @rnadm +} +{ + SMULBB 1111 1011 0001 .... 1111 .... 0000 .... @rn0dm + SMLABB 1111 1011 0001 .... .... .... 0000 .... @rnadm +} +{ + SMULBT 1111 1011 0001 .... 1111 .... 0001 .... @rn0dm + SMLABT 1111 1011 0001 .... .... .... 0001 .... @rnadm +} +{ + SMULTB 1111 1011 0001 .... 1111 .... 0010 .... @rn0dm + SMLATB 1111 1011 0001 .... .... .... 0010 .... @rnadm +} +{ + SMULTT 1111 1011 0001 .... 1111 .... 0011 .... @rn0dm + SMLATT 1111 1011 0001 .... .... .... 0011 .... @rnadm +} +SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm +SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm +SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm +SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm =20 # Data-processing (two source registers) =20 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=l0Gtdyo5nMKKRI4uQ/+uyb9G9cj8p6HrKAyS4O+r2fs=; b=tlkXgdWIQHefx+VpksUhUtq3Z52JJCeLbdGikVTjX5c61VCUvgzBJG01Dg8rDhMBXi dIAKwe8xmTGmmoXp3Z+wSs5zQMr+jTcVzIxZVoJDWbk+Y/bcZkNPCoSuXdZuLpIhpoMG 77QfhTcWKchL2GzhPnVj8q7CyZ18Waks9aJm5wX5/WO72+FtXZfmvZGnP9R7XLT9A959 CB4F66lNs1q+vR9IysQ2qluoTNzh7Qe14Sp2xrrXiULHgY9ZY+IlZB2EHa6by/UeUJve ApvKwWPCDzIFII9FZrYWk5wGIv6Ppcay2hItvsUKbu55Y1MF5ilUV5SHjlAr7nkSXWAq 4wPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=l0Gtdyo5nMKKRI4uQ/+uyb9G9cj8p6HrKAyS4O+r2fs=; b=Ib1cReoN1OZf5MlwLV7b8NFtcze6gF7spQD2vdoI4A7gBro0p0j8Ooa/WrJqzzpukj 1qE0nKVYBkABMHgQNmYv2ZxrtnFTRa2/UrORRJG8gH7JcbEHP/F8OEKJtVjyRSoo2D0R 2LKg2cjOUQtOo11Zt13Z+U0R6V/fOAhykUF3ha6e2q/DXlV+hW1JLNLKsrHzAbnJwCc6 D7XbvgGsMo3hz2DzeQ0bcvAip905hwztMLPAllw6/ejXBUOjtkyF4hBUefgu7kXE+rwX QA8fZDpb1WQAvWGN4riUuqAena/x84PsZP+h4iHoU9cmZhPfeMrAYD7FLhRTI8EpY65f yddQ== X-Gm-Message-State: APjAAAUx9XNvNU7HnElp0n9XmeraEDUth6ocuixOZbRv4y8BReMlcAua zIbXGvPosuVi9EpACsNUADvIiCtGnDo= X-Google-Smtp-Source: APXvYqxyP0Trnwe+z9o/h9RBWTB1KnuiaZyQkws/igSTHRoHy3G+8g9HD0VYY7I07SnKMQbKwz304Q== X-Received: by 2002:a17:902:4581:: with SMTP id n1mr43263035pld.310.1567625473716; Wed, 04 Sep 2019 12:31:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:00 -0700 Message-Id: <20190904193059.26202-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v4 10/69] target/arm: Simplify op_smlaxxx for SMLAL* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Since all of the inputs and outputs are i32, dispense with the intermediate promotion to i64 and use tcg_gen_add2_i32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5306e93470..37aa873e25 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8177,8 +8177,7 @@ DO_QADDSUB(QDSUB, false, true) static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, int add_long, bool nt, bool mt) { - TCGv_i32 t0, t1; - TCGv_i64 t64; + TCGv_i32 t0, t1, tl, th; =20 if (s->thumb ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) @@ -8202,12 +8201,14 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, store_reg(s, a->rd, t0); break; case 2: - t64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(t64, t0); + tl =3D load_reg(s, a->ra); + th =3D load_reg(s, a->rd); + t1 =3D tcg_const_i32(0); + tcg_gen_add2_i32(tl, th, tl, th, t0, t1); tcg_temp_free_i32(t0); - gen_addq(s, t64, a->ra, a->rd); - gen_storeq_reg(s, a->ra, a->rd, t64); - tcg_temp_free_i64(t64); + tcg_temp_free_i32(t1); + store_reg(s, a->ra, tl); + store_reg(s, a->rd, th); break; default: g_assert_not_reached(); --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567626292; cv=none; d=zoho.com; s=zohoarc; b=AOdqzxbkUdzjJoLp1hKG/fBtmJKI0hoGWvZaF25Z1kCqZ47cBHnmZiwyF2yoqGtTxgMK1V9T1XrnhLBh7Q9XRyQ5LERibkazG/gYycMx1ASEAQvVjPZA4y5Lpq8A8IGktwGoBjdXPIMpQm8lHqSEbwpUqIS2jI0L6n3QDddmjWQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567626292; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=d8Wdw3hGEJ+w80H7Z6N3YxcS5gbQ3Bt1g5kmZafUCnU=; b=nEMIjXD4xS/5YxHEDVAQABKAnSbTs4KYIw2l8GeQ1zAbE1K1HDisnMY2DNcjy0WmKtahcQwxt4lPoSfCkJoj7l33r1qfIVuDtRfGrlD+atBGcoI9NMXgVywp9aSxMlcxeLLe1x6QKL3W+1WXH4z31k/3a+/p3CS291O2mnniAMk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567626292518767.2144636453263; Wed, 4 Sep 2019 12:44:52 -0700 (PDT) Received: from localhost ([::1]:37740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bD0-0000pX-VI for importer@patchew.org; Wed, 04 Sep 2019 15:44:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39926) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5azt-0004I1-Tv for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5azs-0002Dg-EF for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:17 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:34997) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5azs-0002D8-5C for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:16 -0400 Received: by mail-pl1-x643.google.com with SMTP id gn20so10396plb.2 for ; Wed, 04 Sep 2019 12:31:16 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=d8Wdw3hGEJ+w80H7Z6N3YxcS5gbQ3Bt1g5kmZafUCnU=; b=XqaFgemVzu4+yDiome30Gqndsi6Hd7TEIU+HmdXOt9oYd10J3YEtc3gPX/3qKvBS2m JryOVOrvFEv3gpcv+I3QiMD2gh6pBPnS/Y6GaKxqEa5Mkp8MkNggOF6nh24wk5XCo+1m gCFelZkqGfT4V52m5Ud9+NX7QCu9jLFxe/StTcBVYvRldGVELXFvEIYj8CDV6wHg/oBa LCmaJ7wL8sqOqjLA+5stnPxlJn6t/aK+GsVL6tgStRuf9JpiodOaOVRCnktA6xEI/yju t8Pg5sqc3xyn6D8FBiKoZfK5c2HX5N6qaEoRaYMgsLu3cXDUtJEC5zXxJSeQYP10pRof uQBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=d8Wdw3hGEJ+w80H7Z6N3YxcS5gbQ3Bt1g5kmZafUCnU=; b=Yj/XpbSTO0Jo4e1icUJmcLDlmHtZMhef/MRhITZxtcesPqDdFTXl1uQeN4tNoec9pC kR7rEkHryI6cHPFji5J+7XI6LZldbPZDJ0LlLYTauT67M4Nc4IeMX16peb+JF/JDDXxz eWPJ3meyiQ6zl4UyxROqw/ftzdOk6aTgbyvet0ZdOyjBce77hSfmFON7H1JGKAjJifsc BoHABvMUqL88C+hxZgLF5y1XKqzeWQ/LMAnfBFvhQ/L8j81D0OMfOL3C6nz38qbuaGnW yOsNH5szb0ROmZ8CVkFZjVMH7AllYBb4gXuONqMPkVOmoaO4ijHh2p+b4nIrHhHO83ql wuSQ== X-Gm-Message-State: APjAAAXCOKjXKypA7YV5gxW+lpRhKuAlDCGRV+c3mDBy3Zuvv56x1ON7 x6JzNaM4h+ZegXevqZ7hRdwe2rhckkI= X-Google-Smtp-Source: APXvYqzpIhulbr6Ms4FPfL8FL04IHY0jVKTL5JN+6CehQ1BAR6SzSLFf14GVTfVoE2DZ06GwZgDLnw== X-Received: by 2002:a17:902:36a:: with SMTP id 97mr4443725pld.75.1567625474851; Wed, 04 Sep 2019 12:31:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:01 -0700 Message-Id: <20190904193059.26202-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 11/69] target/arm: Simplify op_smlawx for SMLAW* X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" By shifting the 16-bit input left by 16, we can align the desired portion of the 48-bit product and use tcg_gen_muls2_i32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 37aa873e25..71cc96b70e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8242,7 +8242,6 @@ DO_SMLAX(SMLALTT, 2, 1, 1) static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) { TCGv_i32 t0, t1; - TCGv_i64 t64; =20 if (!ENABLE_ARCH_5TE) { return false; @@ -8250,16 +8249,17 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a,= bool add, bool mt) =20 t0 =3D load_reg(s, a->rn); t1 =3D load_reg(s, a->rm); + /* + * Since the nominal result is product<47:16>, shift the 16-bit + * input up by 16 bits, so that the result is at product<63:32>. + */ if (mt) { - tcg_gen_sari_i32(t1, t1, 16); + tcg_gen_andi_i32(t1, t1, 0xffff0000); } else { - gen_sxth(t1); + tcg_gen_shli_i32(t1, t1, 16); } - t64 =3D gen_muls_i64_i32(t0, t1); - tcg_gen_shri_i64(t64, t64, 16); - t1 =3D tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(t1, t64); - tcg_temp_free_i64(t64); + tcg_gen_muls2_i32(t0, t1, t0, t1); + tcg_temp_free_i32(t0); if (add) { t0 =3D load_reg(s, a->ra); gen_helper_add_setq(t1, cpu_env, t1, t0); --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567626482; cv=none; d=zoho.com; s=zohoarc; b=erv6mmoRUwB9BHVXB8ZzwD41b56u6K25lcvfnHolSPQ/N87LhGWnkqRbd1RZcy9yc1CE2HMDFVTRMoMpAwgszYDA5A3SmeY4OEiQTON8UaW5COSiqbKgLUeaJk4qoA2EXsNhxji1V0W7s+XkVTjeXA0BYcv8gv5vodDQ3/4Ik0M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567626482; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=qIboakrWv9IiGA+mdMxhBvLjlTlOJK5d1FVqxlQZi7U=; b=PgUx/EH1zPsyR2W4Zs2VwxL2Yn+3riuJKqEUNNIXX1J+FDcxj/9zMhKwZw9/y4znwcAccY7lnFto6wysdJWffA9xquw5SlAejviY2gm560NdvxEhnopWwCh0Oetqvc4qRLDgSDBYO18JqcHaSHnD5baU+L9vjsuAIQoz/SOGA2Y= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567626482796526.6738729991881; Wed, 4 Sep 2019 12:48:02 -0700 (PDT) Received: from localhost ([::1]:37798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bG5-0004Uu-0r for importer@patchew.org; Wed, 04 Sep 2019 15:48:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39959) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5azv-0004KC-Eh for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5azt-0002Ek-JI for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:19 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:42985) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5azt-0002E1-Ab for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:17 -0400 Received: by mail-pl1-x643.google.com with SMTP id y1so10011102plp.9 for ; Wed, 04 Sep 2019 12:31:17 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qIboakrWv9IiGA+mdMxhBvLjlTlOJK5d1FVqxlQZi7U=; b=tHoGUVceZAs8Vh4SMtRsAay5YBKllYR3EERReCZ7oqZws/QiS1wYSKRM01SXA5Fz/n nDYYu9GVabSJr0K/i667V2zI2nkC+Yd6c7DlxkNjOK9GYBZtvSCpBHNkTIYtA0D4kCgp +ScJJ6BeKxvmnukc0AKJCa9lw8P9ArRPH88riZPYm/pJLFZXIis3TeWztY3LhYa0VzXr KNgNINPkEXloRwEgUw5oUXCHyi+8GMSQhCaPmaZQh/PxqLJm3BzbTXkVxsZHPwX6oOGd 7iwYhlttSJVKEevJEvOsD/SaPje29+1mq2zsGzi8nEvhmdo3ttGhUmrN1J5QrGUbH8WB iWeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qIboakrWv9IiGA+mdMxhBvLjlTlOJK5d1FVqxlQZi7U=; b=eRM0zmQ0RVCLT1rsasTurd8p3Q5JAOYby4h089fprA2bIxQwQRFwb4WWvYMOBsVai/ BuNukEx+e9HuUrMDd8lfBhNjpm873A9On3hsd+lO989PRNXa8fKbGvjxAMG+f5MZ4SRx Q0Q/hudrMC9ku0mAEpF0sZevUFg4kF7wnImGyNUyEl2C5koEVhnAn2beGPVKZZg6q4Lt 6a3hw1JnhWErvmoiyHAlHY2nk/uheqvQJcXX+mKhHanwUK5kzzA0wrDDkS3WsFpngXt2 XRD0vsvQso12gZxwSlqoMOxCn4hnSI3k/vikzGxMwQhgTpynr6s9gI95z19NbZwDa3nQ 2ldQ== X-Gm-Message-State: APjAAAXCjedoeEsmkGO5K+xrR5HUyXf7t1xrSabY6BOeTaDbYe34Yh5s 3Vulz42xQPklRkjetBo+ivfT/xtxBjM= X-Google-Smtp-Source: APXvYqxVxFJ3OAcZkRJ7W6DFwVq5/eT8jAW04Ar/u9B0VJ/hQQkKJx22+TyHvb15UobKAQyY1Nj+Xw== X-Received: by 2002:a17:902:6842:: with SMTP id f2mr43499203pln.39.1567625476030; Wed, 04 Sep 2019 12:31:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:02 -0700 Message-Id: <20190904193059.26202-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 12/69] target/arm: Convert MSR (immediate) and hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 60 +++++++++++++++++++++++++++++------------- target/arm/a32.decode | 25 ++++++++++++++++++ target/arm/t32.decode | 17 ++++++++++++ 3 files changed, 84 insertions(+), 18 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 71cc96b70e..58bfbb8ed9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8282,6 +8282,44 @@ DO_SMLAWX(SMLAWT, 1, 1) =20 #undef DO_SMLAWX =20 +/* + * MSR (immediate) and hints + */ + +static bool trans_YIELD(DisasContext *s, arg_YIELD *a) +{ + gen_nop_hint(s, 1); + return true; +} + +static bool trans_WFE(DisasContext *s, arg_WFE *a) +{ + gen_nop_hint(s, 2); + return true; +} + +static bool trans_WFI(DisasContext *s, arg_WFI *a) +{ + gen_nop_hint(s, 3); + return true; +} + +static bool trans_NOP(DisasContext *s, arg_NOP *a) +{ + return true; +} + +static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) +{ + uint32_t val =3D ror32(a->imm, a->rot * 2); + uint32_t mask =3D msr_mask(s, a->mask, a->r); + + if (gen_set_psr_im(s, mask, a->r, val)) { + unallocated_encoding(s); + } + return true; +} + /* * Legacy decoder. */ @@ -8555,21 +8593,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } store_reg(s, rd, tmp); } else { - if (((insn >> 12) & 0xf) !=3D 0xf) - goto illegal_op; - if (((insn >> 16) & 0xf) =3D=3D 0) { - gen_nop_hint(s, insn & 0xff); - } else { - /* CPSR =3D immediate */ - val =3D insn & 0xff; - shift =3D ((insn >> 8) & 0xf) * 2; - val =3D ror32(val, shift); - i =3D ((insn & (1 << 22)) !=3D 0); - if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i), - i, val)) { - goto illegal_op; - } - } + /* MSR (immediate) and hints */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); } } else if ((insn & 0x0f900000) =3D=3D 0x01000000 && (insn & 0x00000090) !=3D 0x00000090) { @@ -10522,9 +10548,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; break; case 2: /* cps, nop-hint. */ - if (((insn >> 8) & 7) =3D=3D 0) { - gen_nop_hint(s, insn & 0xff); - } + /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ if (IS_USER(s)) break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 19d12e726b..3d5c5408f9 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -22,6 +22,7 @@ # All insns that have 0xf in insn[31:28] are in a32-uncond.decode. # =20 +&empty &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot @@ -152,3 +153,27 @@ SMULBB .... 0001 0110 .... 0000 .... 1000 ..= .. @rd0mn SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn + +# MSR (immediate) and hints + +&msr_i r mask rot imm +@msr_i ---- .... .... mask:4 .... rot:4 imm:8 &msr_i + +{ + { + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + # The canonical nop ends in 00000000, but the whole of the + # rest of the space executes as nop if otherwise unsupported. + NOP ---- 0011 0010 0000 1111 ---- ---- ---- + } + # Note mask =3D 0 is covered by NOP + MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=3D0 +} +MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=3D1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 122a0537ed..ccb7cdd4ef 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # =20 +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -166,3 +167,19 @@ QADD 1111 1010 1000 .... 1111 .... 1000 ..= .. @rndm QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm + +# Branches and miscellaneous control + +{ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- +} --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567626244; cv=none; d=zoho.com; s=zohoarc; b=annuW6HLD4SvSPzSdA83BhsiCZxTe8C2jt6o4UKULaFhYIYDgc8tZcNYh3Fyf8orLdp52b+Xk0VQBDhf0F0HRkxhqrYRgcN2DYDl9Q55AaYWyGOfzl1o+SzvG2KRqn9JRY7mGe0QoDdeULeq4NT+Ct9PovX8WtZt7ifvWryjh9E= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m4MAJXgoOrMBvW2yiXtAmVUpQTazbzn/T7aZQnWvwi0=; b=eIPILYG8yjvEJv8JQUxy5uo0zPkPhAqyeATFr5S5HCoNLWrGabXRpyhz6fHUYsZfOh /U5cnMnFUcDUT0BWe9qOO9kvo6D/LR/KYWHmgliL25xoK5CxVkaWZXXeJ5baaTjECM06 lwgkO+dXUQKX6dfUZS3yJBf74nuaCeLgGNRlJMt9SMUf60WWaO6pSxtIr8nN7Ynfvk/4 Nb+eQu5n0MvUuZ9LKgHj3CdnCjSLv4kIAw4NBc4hAgQmys/F7LlBHqERm1bO50TSk7CG XiufRqX3PBJFtKgXGzJrz7BD0Aujn7Nidy+fijEEkaZrZDM5B7TOg+2aVr5XlHod5ZES K3rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m4MAJXgoOrMBvW2yiXtAmVUpQTazbzn/T7aZQnWvwi0=; b=PX4yF8HjoaKriyClnURbT+qGMJ7ExWS1thqhyMyLEubAN+SrT7UZHpwn8VfTDSEcFb GeMurW/lLp929zzIb7iPhRWAkKyh0KkLEEHvmK2sfb+QHufpK3jcwFKoEkM2QNazNkiT brEZxUnzedadbJyw7knUNyKrrt7IIZe8qNlRdusVbBikAicMWHlcXTMgHVIB/rvrsa2x nD6fqJgQnrFzzkQUpI10CWfjCX72cGubJ6mZASVfemYZ5LGsGYmE7N+sR7ick0qmYG1g OOrxhye/Blb/lXfiA3PfmQtP58foTCLEH4HWLg09gq0FmuvRR3+YzJEJhAixuT8j6pNJ 5ExQ== X-Gm-Message-State: APjAAAWHe1Vq/5WXfiDYTClb+uP3LK6GR1P8SCF3gfJytg3Lm+RnDbB0 RukbMUxXT/WT/DIqwYz2hwbtD2tVMLM= X-Google-Smtp-Source: APXvYqwY0hV7cT1SCsZvaiCbIL1mD12RgT1WE8Ynn2+lUjbHfmifERONiAczKXH7KyEV3PdCfPxytQ== X-Received: by 2002:a17:902:a415:: with SMTP id p21mr18461988plq.319.1567625477232; Wed, 04 Sep 2019 12:31:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:03 -0700 Message-Id: <20190904193059.26202-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 13/69] target/arm: Convert MRS/MSR (banked, register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 226 ++++++++++++++++++----------------------- target/arm/a32.decode | 14 +++ target/arm/t32.decode | 40 ++++++-- 3 files changed, 142 insertions(+), 138 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 58bfbb8ed9..02dd4a2ab8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8320,6 +8320,93 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_i= mm *a) return true; } =20 +/* + * Miscellaneous instructions + */ + +static bool trans_MRS_bank(DisasContext *s, arg_MRS_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_mrs_banked(s, a->r, a->sysm, a->rd); + return true; +} + +static bool trans_MSR_bank(DisasContext *s, arg_MSR_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_msr_banked(s, a->r, a->sysm, a->rn); + return true; +} + +static bool trans_MRS_reg(DisasContext *s, arg_MRS_reg *a) +{ + TCGv_i32 tmp; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (a->r) { + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + tmp =3D load_cpu_field(spsr); + } else { + tmp =3D tcg_temp_new_i32(); + gen_helper_cpsr_read(tmp, cpu_env); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_reg(DisasContext *s, arg_MSR_reg *a) +{ + TCGv_i32 tmp; + uint32_t mask =3D msr_mask(s, a->mask, a->r); + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp =3D load_reg(s, a->rn); + if (gen_set_psr(s, mask, a->r, tmp)) { + unallocated_encoding(s); + } + return true; +} + +static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) +{ + TCGv_i32 tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp =3D tcg_const_i32(a->sysm); + gen_helper_v7m_mrs(tmp, cpu_env, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) +{ + TCGv_i32 addr, reg; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + addr =3D tcg_const_i32((a->mask << 10) | a->sysm); + reg =3D load_reg(s, a->rn); + gen_helper_v7m_msr(cpu_env, addr, reg); + tcg_temp_free_i32(addr); + tcg_temp_free_i32(reg); + gen_lookup_tb(s); + return true; +} + /* * Legacy decoder. */ @@ -8604,46 +8691,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) sh =3D (insn >> 4) & 0xf; rm =3D insn & 0xf; switch (sh) { - case 0x0: /* MSR, MRS */ - if (insn & (1 << 9)) { - /* MSR (banked) and MRS (banked) */ - int sysm =3D extract32(insn, 16, 4) | - (extract32(insn, 8, 1) << 4); - int r =3D extract32(insn, 22, 1); - - if (op1 & 1) { - /* MSR (banked) */ - gen_msr_banked(s, r, sysm, rm); - } else { - /* MRS (banked) */ - int rd =3D extract32(insn, 12, 4); - - gen_mrs_banked(s, r, sysm, rd); - } - break; - } - - /* MSR, MRS (for PSRs) */ - if (op1 & 1) { - /* PSR =3D reg */ - tmp =3D load_reg(s, rm); - i =3D ((op1 & 2) !=3D 0); - if (gen_set_psr(s, msr_mask(s, (insn >> 16) & 0xf, i), i, = tmp)) - goto illegal_op; - } else { - /* reg =3D PSR */ - rd =3D (insn >> 12) & 0xf; - if (op1 & 2) { - if (IS_USER(s)) - goto illegal_op; - tmp =3D load_cpu_field(spsr); - } else { - tmp =3D tcg_temp_new_i32(); - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - } - break; + case 0x0: + /* MSR/MRS (banked/register) */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); case 0x1: if (op1 =3D=3D 1) { /* branch/exchange thumb (bx). */ @@ -10513,40 +10564,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } else { op =3D (insn >> 20) & 7; switch (op) { - case 0: /* msr cpsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp =3D load_reg(s, rn); - /* the constant is the mask and SYSm fields */ - addr =3D tcg_const_i32(insn & 0xfff); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - break; - } - /* fall through */ - case 1: /* msr spsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - - if (extract32(insn, 5, 1)) { - /* MSR (banked) */ - int sysm =3D extract32(insn, 8, 4) | - (extract32(insn, 4, 1) << 4); - int r =3D op & 1; - - gen_msr_banked(s, r, sysm, rm); - break; - } - - /* MSR (for PSRs) */ - tmp =3D load_reg(s, rn); - if (gen_set_psr(s, - msr_mask(s, (insn >> 8) & 0xf, op =3D=3D 1), - op =3D=3D 1, tmp)) - goto illegal_op; - break; + case 0: /* msr cpsr, in decodetree */ + case 1: /* msr spsr, in decodetree */ + goto illegal_op; case 2: /* cps, nop-hint. */ /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ @@ -10638,61 +10658,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } gen_exception_return(s, tmp); break; - case 6: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm =3D extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 0, sysm, rd); - break; - } - - if (extract32(insn, 16, 4) !=3D 0xf) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_M) && - extract32(insn, 0, 8) !=3D 0) { - goto illegal_op; - } - - /* mrs cpsr */ - tmp =3D tcg_temp_new_i32(); - if (arm_dc_feature(s, ARM_FEATURE_M)) { - addr =3D tcg_const_i32(insn & 0xff); - gen_helper_v7m_mrs(tmp, cpu_env, addr); - tcg_temp_free_i32(addr); - } else { - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - break; - case 7: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm =3D extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 1, sysm, rd); - break; - } - - /* mrs spsr. */ - /* Not accessible in user mode. */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)= ) { - goto illegal_op; - } - - if (extract32(insn, 16, 4) !=3D 0xf || - extract32(insn, 0, 8) !=3D 0) { - goto illegal_op; - } - - tmp =3D load_cpu_field(spsr); - store_reg(s, rd, tmp); - break; + case 6: /* MRS, in decodetree */ + case 7: /* MSR, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 3d5c5408f9..6ee12c1140 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,10 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&msr_reg rn r mask +&mrs_reg rd r +&msr_bank rn r sysm +&mrs_bank rd r sysm =20 # Data-processing (register) =20 @@ -177,3 +181,13 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 ..= .. @rd0mn MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=3D0 } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=3D1 + +# Miscellaneous instructions + +%sysm 8:1 16:4 + +MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm +MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm + +MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg +MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ccb7cdd4ef..98b682e7ec 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,10 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&msr_reg !extern rn r mask +&mrs_reg !extern rd r +&msr_bank !extern rn r sysm +&mrs_bank !extern rd r sysm =20 # Data-processing (register) =20 @@ -170,16 +174,34 @@ QDSUB 1111 1010 1000 .... 1111 .... 1011 .= ... @rndm =20 # Branches and miscellaneous control =20 +%msr_sysm 4:1 8:4 +%mrs_sysm 4:1 16:4 + { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + &mrs_bank sysm=3D%mrs_sysm + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + &msr_bank sysm=3D%msr_sysm + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } } --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 14/69] target/arm: Convert Cyclic Redundancy Check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 +++++++++++++++++++---------------------- target/arm/a32.decode | 9 +++ target/arm/t32.decode | 7 +++ 3 files changed, 72 insertions(+), 65 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 02dd4a2ab8..9d3f31f569 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8320,6 +8320,57 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_i= mm *a) return true; } =20 +/* + * Cyclic Redundancy Check + */ + +static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, MemOp sz) +{ + TCGv_i32 t1, t2, t3; + + if (!dc_isar_feature(aa32_crc32, s)) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + switch (sz) { + case MO_8: + gen_uxtb(t2); + break; + case MO_16: + gen_uxth(t2); + break; + case MO_32: + break; + default: + g_assert_not_reached(); + } + t3 =3D tcg_const_i32(1 << sz); + if (c) { + gen_helper_crc32c(t1, t1, t2, t3); + } else { + gen_helper_crc32(t1, t1, t2, t3); + } + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + store_reg(s, a->rd, t1); + return true; +} + +#define DO_CRC32(NAME, c, sz) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ + { return op_crc32(s, a, c, sz); } + +DO_CRC32(CRC32B, false, MO_8) +DO_CRC32(CRC32H, false, MO_16) +DO_CRC32(CRC32W, false, MO_32) +DO_CRC32(CRC32CB, true, MO_8) +DO_CRC32(CRC32CH, true, MO_16) +DO_CRC32(CRC32CW, true, MO_32) + +#undef DO_CRC32 + /* * Miscellaneous instructions */ @@ -8735,39 +8786,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) gen_bx(s, tmp); break; case 0x4: - { - /* crc32/crc32c */ - uint32_t c =3D extract32(insn, 8, 4); - - /* Check this CPU supports ARMv8 CRC instructions. - * op1 =3D=3D 3 is UNPREDICTABLE but handle as UNDEFINED. - * Bits 8, 10 and 11 should be zero. - */ - if (!dc_isar_feature(aa32_crc32, s) || op1 =3D=3D 0x3 || (c & = 0xd) !=3D 0) { - goto illegal_op; - } - - rn =3D extract32(insn, 16, 4); - rd =3D extract32(insn, 12, 4); - - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if (op1 =3D=3D 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (op1 =3D=3D 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 =3D tcg_const_i32(1 << op1); - if (c & 0x2) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - store_reg(s, rd, tmp); - break; - } + /* crc32 */ + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; case 0x5: /* Saturating addition and subtraction. */ /* All done in decodetree. Reach here for illegal ops. */ @@ -10216,16 +10237,13 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) goto illegal_op; } break; - case 0x20: /* crc32/crc32c */ + case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: case 0x28: case 0x29: case 0x2a: - if (!dc_isar_feature(aa32_crc32, s)) { - goto illegal_op; - } - break; + goto illegal_op; default: goto illegal_op; } @@ -10254,33 +10272,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 0x18: /* clz */ tcg_gen_clzi_i32(tmp, tmp, 32); break; - case 0x20: - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - { - /* crc32/crc32c */ - uint32_t sz =3D op & 0x3; - uint32_t c =3D op & 0x8; - - tmp2 =3D load_reg(s, rm); - if (sz =3D=3D 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (sz =3D=3D 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 =3D tcg_const_i32(1 << sz); - if (c) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - break; - } default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6ee12c1140..a8ef435b15 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -182,6 +182,15 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 ..= .. @rd0mn } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=3D1 =20 +# Cyclic Redundancy Check + +CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm +CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm +CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm +CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm +CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm +CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm + # Miscellaneous instructions =20 %sysm 8:1 16:4 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 98b682e7ec..261db100ff 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -172,6 +172,13 @@ QSUB 1111 1010 1000 .... 1111 .... 1010 ..= .. @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm =20 +CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm +CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm +CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm +CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm +CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm +CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm + # Branches and miscellaneous control =20 %msr_sysm 4:1 8:4 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DQ2Al2ZzVVcL195LoX3T2MlUUfcTCEsrN0xAjDQ6QOs=; b=rzQPC7qk+vBNALaK/ET6NoVKklI8sPNx+uJAEcv7SPlZJBWxxNa80iuJ3v9do3CZU+ WY9JXwlvhKpatCZAbWsz0DBvgYj3f068/Jaf3tG73cZg7kXad0JY7XfGd0MdxkLn/DlW tLh2g+TO8XeiEZm3czeWtqS/fX4dZH+nUS2eRRHdDtsoEj9GMhJhcchJt7Y0Ys4Tfv2t woQEg3bOwsbmfxC4EMRHDE/o4DBuwM2YD1vietsH3DjQvOYAye9SMzDOQ9LJhcroOMK+ iPAlqvp1X9kydUJHU6XuuPTA7lYZUou46u+eMpC98rm34dXShCNegGUEutcmWcaeIgYG o4rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DQ2Al2ZzVVcL195LoX3T2MlUUfcTCEsrN0xAjDQ6QOs=; b=J4i+J30AReL2i+eLbOYBY8+6w0gqcDBu2khddQ7SzXjQQ3WO6zI/jTEdwC5JrXGfWK vMLTe+dP8QiqwwUzsZzT6FnR/1GahPWxMxeNJpPTi619wMLGnsQII4FUw6nJ7OiZqya1 CA2mjKtXUC29DllmpKeKUtxx9q6un/OEBfVruM+uJni/6EpI0FSOnv97iIGHNL+XHAsn +8Jb/vNI4dsI4WfMe2pr9NbtvH1frs3r3d+8Qh5q7uB6PY+kQwegTpJVlNsAiOPuiedo YqWUU7kIKd4RISQ7H1c4W2MPuDGQ4IZrfFhSm320c9w23NhniiW7AEXnj2kGt0bQUrFo fMLg== X-Gm-Message-State: APjAAAUo8RZoV3kFkHhSxAK4IV7y3Il7tDE7qaQ0LTxp5sJC6TDNkA8r oGoyRWtorfX4SqXc+fnR9N0iaWK8NgQ= X-Google-Smtp-Source: APXvYqyutN8Hjxb0ZFGZOyMJXuImeGg1Qma/KR6IOj+GsWmg0S30sBKRf3qZ9PadAHXNLmaAgTpI6g== X-Received: by 2002:a63:5f09:: with SMTP id t9mr36814107pgb.351.1567625479605; Wed, 04 Sep 2019 12:31:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:05 -0700 Message-Id: <20190904193059.26202-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::530 Subject: [Qemu-devel] [PATCH v4 15/69] target/arm: Convert BX, BXJ, BLX (register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 78 ++++++++++++++++++++---------------------- target/arm/a32.decode | 7 ++++ target/arm/t32.decode | 2 ++ 3 files changed, 47 insertions(+), 40 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9d3f31f569..386a460bf5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8458,6 +8458,38 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v= 7m *a) return true; } =20 +static bool trans_BX(DisasContext *s, arg_BX *a) +{ + if (!ENABLE_ARCH_4T) { + return false; + } + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BXJ(DisasContext *s, arg_BXJ *a) +{ + if (!ENABLE_ARCH_5J || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + /* Trivial implementation equivalent to bx. */ + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp =3D load_reg(s, a->rm); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_bx(s, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8747,12 +8779,7 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) /* All done in decodetree. Illegal ops already signalled. */ g_assert_not_reached(); case 0x1: - if (op1 =3D=3D 1) { - /* branch/exchange thumb (bx). */ - ARCH(4T); - tmp =3D load_reg(s, rm); - gen_bx(s, tmp); - } else if (op1 =3D=3D 3) { + if (op1 =3D=3D 3) { /* clz */ ARCH(5); rd =3D (insn >> 12) & 0xf; @@ -8763,30 +8790,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) goto illegal_op; } break; - case 0x2: - if (op1 =3D=3D 1) { - ARCH(5J); /* bxj */ - /* Trivial implementation equivalent to bx. */ - tmp =3D load_reg(s, rm); - gen_bx(s, tmp); - } else { - goto illegal_op; - } - break; - case 0x3: - if (op1 !=3D 1) - goto illegal_op; - - ARCH(5); - /* branch link/exchange thumb (blx) */ - tmp =3D load_reg(s, rm); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - case 0x4: - /* crc32 */ + case 0x2: /* bxj */ + case 0x3: /* blx */ + case 0x4: /* crc32 */ /* All done in decodetree. Illegal ops reach here. */ goto illegal_op; case 0x5: @@ -10620,16 +10626,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) goto illegal_op; } break; - case 4: /* bxj */ - /* Trivial implementation equivalent to bx. - * This instruction doesn't exist at all for M-pro= file. - */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - tmp =3D load_reg(s, rn); - gen_bx(s, tmp); - break; + case 4: /* bxj, in decodetree */ + goto illegal_op; case 5: /* Exception return. */ if (IS_USER(s)) { goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index a8ef435b15..6cb9c16e2f 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,7 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&r rm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -195,8 +196,14 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 ..= .. @rndm =20 %sysm 8:1 16:4 =20 +@rm ---- .... .... .... .... .... .... rm:4 &r + MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm =20 MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg + +BX .... 0001 0010 1111 1111 1111 0001 .... @rm +BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm +BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 261db100ff..337706ebbe 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -211,4 +212,5 @@ CRC32CW 1111 1010 1101 .... 1111 .... 1010 ...= . @rndm MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r } --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567626691; cv=none; d=zoho.com; s=zohoarc; b=U3jnS7+tARmnsUBi9Sg2gb3aB2Z/GKlhD8kWNsnm+pFgDqeoIf7rBjaCpeuJCfvhvmLjM2lq2uUfB/DVrzvwQPphH4KblBOzOUS2Fq33/oYB6t1exGZNdmqsWMRcHtfVOZwCRgIYhUOwNFNpS8V2YBRZnX6vO/BLWiV4oIqmQkU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567626691; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=gVoXo3oBV5rjG7odbH2AUIPExjRoZyxfBk+LHOtrM+4=; b=JKFxQE4HONIAcOMtBksUjkuVMlGltVnCcqXvDi5gdrhy8dPP2tfOJT7lR5+KDPc2wL9k7ORg0EjJAG4OHCVurGE4/jTG4+WQ6drKIg9XNl6uVdtMUpVg9buaIuDR/qVmHR6fzM5iUnnGW0PNSNyY7wVMXqTJC7mzsDYqRhBBkoM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567626691623916.6091285999784; Wed, 4 Sep 2019 12:51:31 -0700 (PDT) Received: from localhost ([::1]:37872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bJS-00080Z-6r for importer@patchew.org; Wed, 04 Sep 2019 15:51:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40082) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b00-0004Qt-8B for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5azy-0002JG-Dn for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:23 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:41025) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5azy-0002Ic-6l for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:22 -0400 Received: by mail-pg1-x543.google.com with SMTP id x15so11778859pgg.8 for ; Wed, 04 Sep 2019 12:31:22 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gVoXo3oBV5rjG7odbH2AUIPExjRoZyxfBk+LHOtrM+4=; b=Vwo8qtj1VcyQsHwTJghLoAhJf6TUVmZs/MhHhGWfHYzpl/doUFuVSYsdDJxJmWcZtr uWppIDVTcI7WJHzhDfQ2CBMlOeh8DLVE6EDuVyXeUZko+BSwrFTaGulLxDi/Ds4jBIsB Rh0ExsQA9f3hurtn9fbCnwa5g32SBtXBuYVyIlS6iZTuYNvGN6+0MbMeQ+4mgQXUz8H2 u45LA45eom3+qWEbJTR2K9IFIJcfeI/IkYiiKJx2PkO0btuXZmXq+mazOVrdOKTQJntw yu5lBduQu4jAFxiLM1JUjwFy1p0yj910I/dqFrA/VEQD3HfFW3AvyhCP2Xj2aJAyxBPX x0pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gVoXo3oBV5rjG7odbH2AUIPExjRoZyxfBk+LHOtrM+4=; b=d5WNfKzdtz44TPPrcP+gdRKHuM5tbv2q7lQqrXhIFCCJLSgwUnvX9bFTxErecWK7gV XyG9LE9j1tcrDL3utVV7//qNzNS/z58pJUrsp9hQMPn7H/9EwCe/Oq02MLj7jWyh+pKK 2/FdgxEmwJtP7yB76QiGJOqXca8rd8uHyrqw18MXLEHUWMtON3uQfAyzmX2qysPy0c+X NO0e98u9p6RZxO9SXMtI1Wc/t5jojTSMbqnpBqeMAnqzjf/funnlPjekjQ3EXXlVQhiV p7vSYA78BtSdxT03VGIoWHjmhNMjkDgLGtXQT73Ww9vjBG9QzHtxp/ISCr3xqgyalSFh kQIA== X-Gm-Message-State: APjAAAVVk1UV+bl/6wVT2W2d1eAlsr+QFOzs+3nI38qn+e+oeCVt5+Ve d8Ghxt1cSNlTZjOCVWjP5fOGvYCGTek= X-Google-Smtp-Source: APXvYqxj1YhkJf33DIwAKnvy4IeFuJoWp1ENl0ujLNZUiENItPy+bXH6R4y8s8VweF9vE7THWwIe8g== X-Received: by 2002:aa7:98d2:: with SMTP id e18mr10640019pfm.188.1567625480867; Wed, 04 Sep 2019 12:31:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:06 -0700 Message-Id: <20190904193059.26202-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 16/69] target/arm: Convert CLZ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour. This matches the undocumented choice made by the legacy decoder. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 31 +++++++++++++++---------------- target/arm/a32.decode | 4 ++++ target/arm/t32.decode | 5 +++++ 3 files changed, 24 insertions(+), 16 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 386a460bf5..7de6949db3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8490,6 +8490,19 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *= a) return true; } =20 +static bool trans_CLZ(DisasContext *s, arg_CLZ *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp =3D load_reg(s, a->rm); + tcg_gen_clzi_i32(tmp, tmp, 32); + store_reg(s, a->rd, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8778,18 +8791,7 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) /* MSR/MRS (banked/register) */ /* All done in decodetree. Illegal ops already signalled. */ g_assert_not_reached(); - case 0x1: - if (op1 =3D=3D 3) { - /* clz */ - ARCH(5); - rd =3D (insn >> 12) & 0xf; - tmp =3D load_reg(s, rm); - tcg_gen_clzi_i32(tmp, tmp, 32); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + case 0x1: /* bx, clz */ case 0x2: /* bxj */ case 0x3: /* blx */ case 0x4: /* crc32 */ @@ -10236,13 +10238,13 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) case 0x08: /* rev */ case 0x09: /* rev16 */ case 0x0b: /* revsh */ - case 0x18: /* clz */ break; case 0x10: /* sel */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { goto illegal_op; } break; + case 0x18: /* clz, in decodetree */ case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: @@ -10275,9 +10277,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) tcg_temp_free_i32(tmp3); tcg_temp_free_i32(tmp2); break; - case 0x18: /* clz */ - tcg_gen_clzi_i32(tmp, tmp, 32); - break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 6cb9c16e2f..182f2b6725 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,7 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&rr rd rm &r rm &msr_reg rn r mask &mrs_reg rd r @@ -197,6 +198,7 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 ...= . @rndm %sysm 8:1 16:4 =20 @rm ---- .... .... .... .... .... .... rm:4 &r +@rdm ---- .... .... .... rd:4 .... .... rm:4 &rr =20 MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm @@ -207,3 +209,5 @@ MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 00= 00 rn:4 &msr_reg BX .... 0001 0010 1111 1111 1111 0001 .... @rm BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm + +CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 337706ebbe..67724efe4b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&rr !extern rd rm &r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r @@ -126,6 +127,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ......= .. @s_rri_rot @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr @rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=3D0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr +@rdm .... .... .... .... .... rd:4 .... rm:4 &rr =20 { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -180,6 +182,9 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 ...= . @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm =20 +# Note rn !=3D rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. +CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm + # Branches and miscellaneous control =20 %msr_sysm 4:1 8:4 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567626221; cv=none; d=zoho.com; s=zohoarc; b=mlProEvN5wS9iiCeJS2yNnXn+7UxMLvHQYrXoIR18zUKhJy9IxCw/JNuNCpd2UjiywYPlhC/gG9PbTqdZvx8kxl/WVjocVzXfvatDJ6LBkjOqN9BfxvKO4XBjL84CfJU8y34yf/kcCra4o15+Y+YmXnlibQc95xY1Tjj1F4Vxnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Br2b0vbKeN/2j/h9uyRFZAyuwQitptP6m+++156fwxo=; b=dFs7DNhzB5u2A91Ak+rjbPDGaGeks5wjKoIQ1+RLRSx/0nxs2YzaGimIR3Usv+tVBs mZvcoZkf8P2pIUSZy/EE8ymjymAhrLf/xdJwlVy8/uLR66mIS3Z3JVLBJ6OlPrKTT70n X6KVWYY8HN7LYYvjMWp6lejaEV4dO5G92Je/vPaaWhE8EN/Il8Gh9ZFmpek0gCXQ7gMp 3uJoWzfv7m4dmg8/eGMYMwgLJmfLBKoGDKDdkWqVx5zTwDXjBJksJcdBT4fZ1rpOGb8p i6pm+M4dqNV1DnTDn04dk4GCSQGeW4Tmn1nICDVAUzew1eUFd/FofRGLLCj6Davx4tQs DMKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Br2b0vbKeN/2j/h9uyRFZAyuwQitptP6m+++156fwxo=; b=LeHyM1CU0s6YegEeG6r+t6yOIeShXP4bZssK1eTrD1jwl3eHw+zsP1G4cHfqJc2WR+ mM6jSRpxa2FZbLkyOIaIB5a2GhBh/jKT/T1h/Nwq7W72Xj+ZZWTvuoBvS6NbhrTx4AkM cTpa8V8nhhQNK8VHqharfyxaJE5BHv8+HxGKzDeZX7M4IKqgbo2JOiSNgjZltkiUFnUf fro6AbcJItdNCXbo+Cibhjaiy5/cs2ViDWy7o0jIg6Ir2MTR5Lf47d3Ur3OMOrTAVxiO /ufVIpjhIJLh8oAYorcwmcMjXv44pzvBBo9CHyt8DG6qRE5jWvc+Sjrv6JZEMF+1r8LN MNKA== X-Gm-Message-State: APjAAAXQhRBwoHgaGbbMoivqqLw+IQJs+huqlZH/e9KcnphTFoTMJS3C sasqOF43L0olGZrVG10CntzhJNYCwhY= X-Google-Smtp-Source: APXvYqwcBq1qJu3RFxmxwyJUlCRJOOMJjSC1qFt1CPRfgy4GV5BEAQxxm1NTnTqQGG0ocwqlWyrBAw== X-Received: by 2002:a62:55c1:: with SMTP id j184mr28269987pfb.104.1567625481933; Wed, 04 Sep 2019 12:31:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:07 -0700 Message-Id: <20190904193059.26202-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 17/69] target/arm: Convert ERET X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Pass the T5 encoding of SUBS PC, LR, #IMM through the normal SUBS path to make it clear exactly what's happening -- we hit ALUExceptionReturn along that path. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for IS_USER check. --- target/arm/translate.c | 62 ++++++++++++++++-------------------------- target/arm/a32.decode | 2 ++ target/arm/t32.decode | 8 ++++++ 3 files changed, 33 insertions(+), 39 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7de6949db3..9589e9bbb9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8503,6 +8503,27 @@ static bool trans_CLZ(DisasContext *s, arg_CLZ *a) return true; } =20 +static bool trans_ERET(DisasContext *s, arg_ERET *a) +{ + TCGv_i32 tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + if (s->current_el =3D=3D 2) { + /* ERET from Hyp uses ELR_Hyp, not LR */ + tmp =3D load_cpu_field(elr_el[2]); + } else { + tmp =3D load_reg(s, 14); + } + gen_exception_return(s, tmp); + return true; +} + /* * Legacy decoder. */ @@ -8797,29 +8818,10 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) case 0x4: /* crc32 */ /* All done in decodetree. Illegal ops reach here. */ goto illegal_op; - case 0x5: - /* Saturating addition and subtraction. */ + case 0x5: /* Saturating addition and subtraction. */ + case 0x6: /* ERET */ /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; - case 0x6: /* ERET */ - if (op1 !=3D 3) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { - goto illegal_op; - } - if ((insn & 0x000fff0f) !=3D 0x0000000e) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - - if (s->current_el =3D=3D 2) { - tmp =3D load_cpu_field(elr_el[2]); - } else { - tmp =3D load_reg(s, 14); - } - gen_exception_return(s, tmp); - break; case 7: { int imm16 =3D extract32(insn, 0, 4) | (extract32(insn, 8, 12) = << 4); @@ -10628,24 +10630,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 4: /* bxj, in decodetree */ goto illegal_op; case 5: /* Exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - if (rn !=3D 14 || rd !=3D 15) { - goto illegal_op; - } - if (s->current_el =3D=3D 2) { - /* ERET from Hyp uses ELR_Hyp, not LR */ - if (insn & 0xff) { - goto illegal_op; - } - tmp =3D load_cpu_field(elr_el[2]); - } else { - tmp =3D load_reg(s, rn); - tcg_gen_subi_i32(tmp, tmp, insn & 0xff); - } - gen_exception_return(s, tmp); - break; case 6: /* MRS, in decodetree */ case 7: /* MSR, in decodetree */ goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 182f2b6725..52a66dd1d5 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -211,3 +211,5 @@ BXJ .... 0001 0010 1111 1111 1111 0010 ...= . @rm BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm =20 CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm + +ERET ---- 0001 0110 0000 0000 0000 0110 1110 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 67724efe4b..6236d28b99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -218,4 +218,12 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as = for + # every other encoding of SUBS. With v7VE, IMM=3D0 is redefined as ER= ET. + # The distinction between the two only matters for Hyp mode. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + &s_rri_rot rot=3D0 s=3D1 rd=3D15 rn=3D14 + } } --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567626887; cv=none; d=zoho.com; s=zohoarc; b=BonR8MRCAQS8nwKf1e39XaqWyIyFVCyyex7lULnyvjd5mLsIGIlDvjmHqK63rPVLrd9CHuONr5MqRsnfgrqJT0VnwtpTkUEyruvNP1p+8seqddEluIl1o53KOgsQVfACzpwShO1k6y/b6qpJ5YJXxtxBxpuRBeSbIIczgHyVQ+8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567626887; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=kFutySvY3dUNUb39wtRAtuDmuWFVewtZdUowhmVNFME=; b=nPy1ZCAOKmPW96M2j3930do+92Hvn75+Q4M3B2nxZUqoSUxQDCOmX5no2WjWn7//wyz2BwewZieOqZZP8a/D3ina0atVedYP+784K0B8q0HqzQR9+icv152krBa0OiebY5AGZCQH8Mmkl68mkqKAmREPtxvPandWDEHJPKnBwro= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567626887102602.0574471068289; Wed, 4 Sep 2019 12:54:47 -0700 (PDT) Received: from localhost ([::1]:37940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bMb-0003bx-9g for importer@patchew.org; Wed, 04 Sep 2019 15:54:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40149) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b03-0004V3-3D for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b01-0002Lo-6V for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:26 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:42778) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b00-0002Kz-To for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:25 -0400 Received: by mail-pg1-x541.google.com with SMTP id p3so11766631pgb.9 for ; Wed, 04 Sep 2019 12:31:24 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kFutySvY3dUNUb39wtRAtuDmuWFVewtZdUowhmVNFME=; b=h0I4AGChQmOFpnuu3N8eLh1aCtt0OYY01ThVKLyDf1codyYb9MBPqYJkTFsIaL7DSe wx6bw3zaPkpyi6cVULO4livkYrv2suKfyZP2Ztg3OrEa0wc/NXfUVhvG01QikwRXSy5X SBg95LZmRxqhUYXdEfqFNoU/36Ra2NMIiKyOErO0cMfZ5y6MuT7m3JYBm15vlZdYKs48 jWY+UNuGofxNcRlr7gXzOH1H2BqnkzEq7C0mKfaWaQP097FO1FZ1ucq78uPaiME6642r x/K8QKi1X//1Hh8x19V/jwezVeDXJilutJROgfTjBSme8RpTrPMTojssPIczPBDEZ2Q2 dFTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kFutySvY3dUNUb39wtRAtuDmuWFVewtZdUowhmVNFME=; b=NqmvDpWT/pbPLaQ9V/d/+l4058cCobA6uIWaSHVKPC1yULk8VMp1IV2VcEXqQ4iGOL ZJFdXP6tQ11eLV2WmUXs1wKLfyacB5G3McakgKjZDs3Fs/3e4Ey/bEgfpk+RfxFAqUJF auNB9SAMJWL4NPxlFPGIohnFzMuPWcu4+uro6sqnm/gNyMULl4ro2bsVBbcREQSu4ALa bRVJAlaADJGlkQTyV/IPY1RY5/ZcG9xa+QsimebTiWetsVNvhuc0A00fYA3iJi/MY6u3 A21upbNluuxf2K+6gLH0jjcZ/3dPloZ2kzSCuqOGnlInWvehIwQD7uHh+EajrmHiHzJP mh1Q== X-Gm-Message-State: APjAAAWUL2U1KBeBo7BlhpUnoCRUpA/rIqEVmui293q6zpu2LIrbCnpS jhIOBuc3v8XhoUIHTOPa9g0dvj+V04I= X-Google-Smtp-Source: APXvYqwOojm5WqWPK5A7zcamAMoGbVrBkkKS425pPqEFCpIVgst3RfzqjnxM91SFBim6Xm3B5yWf+w== X-Received: by 2002:a65:4507:: with SMTP id n7mr24803865pgq.86.1567625483476; Wed, 04 Sep 2019 12:31:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:08 -0700 Message-Id: <20190904193059.26202-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v4 18/69] target/arm: Convert the rest of A32 Miscelaneous instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Call unallocated_encoding for IS_USER. --- target/arm/translate.c | 127 +++++++++++++++-------------------------- target/arm/a32.decode | 8 +++ target/arm/t32.decode | 5 ++ 3 files changed, 58 insertions(+), 82 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9589e9bbb9..750331071b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8524,6 +8524,47 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) return true; } =20 +static bool trans_HLT(DisasContext *s, arg_HLT *a) +{ + gen_hlt(s, a->imm); + return true; +} + +static bool trans_BKPT(DisasContext *s, arg_BKPT *a) +{ + if (!ENABLE_ARCH_5) { + return false; + } + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + return true; +} + +static bool trans_HVC(DisasContext *s, arg_HVC *a) +{ + if (!ENABLE_ARCH_7 || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + } else { + gen_hvc(s, a->imm); + } + return true; +} + +static bool trans_SMC(DisasContext *s, arg_SMC *a) +{ + if (!ENABLE_ARCH_6K || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + } else { + gen_smc(s); + } + return true; +} + /* * Legacy decoder. */ @@ -8804,68 +8845,8 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } else if ((insn & 0x0f900000) =3D=3D 0x01000000 && (insn & 0x00000090) !=3D 0x00000090) { /* miscellaneous instructions */ - op1 =3D (insn >> 21) & 3; - sh =3D (insn >> 4) & 0xf; - rm =3D insn & 0xf; - switch (sh) { - case 0x0: - /* MSR/MRS (banked/register) */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - case 0x1: /* bx, clz */ - case 0x2: /* bxj */ - case 0x3: /* blx */ - case 0x4: /* crc32 */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - case 0x5: /* Saturating addition and subtraction. */ - case 0x6: /* ERET */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 7: - { - int imm16 =3D extract32(insn, 0, 4) | (extract32(insn, 8, 12) = << 4); - switch (op1) { - case 0: - /* HLT */ - gen_hlt(s, imm16); - break; - case 1: - /* bkpt */ - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false)); - break; - case 2: - /* Hypervisor call (v7) */ - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - break; - case 3: - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - break; - default: - g_assert_not_reached(); - } - break; - } - case 0x8: - case 0xa: - case 0xc: - case 0xe: - /* Halfword multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - default: - goto illegal_op; - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if (((insn & 0x0e000000) =3D=3D 0 && (insn & 0x00000090) !=3D 0x90) || ((insn & 0x0e000000) =3D=3D (1 << 25))) { @@ -10539,26 +10520,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) goto illegal_op; =20 if (insn & (1 << 26)) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (!(insn & (1 << 20))) { - /* Hypervisor call (v7) */ - int imm16 =3D extract32(insn, 16, 4) << 12 - | extract32(insn, 0, 12); - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - } else { - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - } + /* hvc, smc, in decodetree */ + goto illegal_op; } else { op =3D (insn >> 20) & 7; switch (op) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 52a66dd1d5..c7f156be6d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -31,6 +31,7 @@ &rrr rd rn rm &rr rd rm &r rm +&i imm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -196,9 +197,11 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 ..= .. @rndm # Miscellaneous instructions =20 %sysm 8:1 16:4 +%imm16_8_0 8:12 0:4 =20 @rm ---- .... .... .... .... .... .... rm:4 &r @rdm ---- .... .... .... rd:4 .... .... rm:4 &rr +@i16 ---- .... .... .... .... .... .... .... &i imm=3D%im= m16_8_0 =20 MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %s= ysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %s= ysm @@ -213,3 +216,8 @@ BLX_r .... 0001 0010 1111 1111 1111 0011 ...= . @rm CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm =20 ERET ---- 0001 0110 0000 0000 0000 0110 1110 + +HLT .... 0001 0000 .... .... .... 0111 .... @i16 +BKPT .... 0001 0010 .... .... .... 0111 .... @i16 +HVC .... 0001 0100 .... .... .... 0111 .... @i16 +SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 6236d28b99..5116c6165a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -28,6 +28,7 @@ &rrr !extern rd rn rm &rr !extern rd rm &r !extern rm +&i !extern imm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -189,6 +190,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm =20 %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 +%imm16_16_0 16:4 0:12 =20 { { @@ -226,4 +228,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=3D0 s=3D1 rd=3D15 rn=3D14 } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ + &i imm=3D%imm16_16_0 } --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VBWptZwV41wrybglM+V4M0H5NWdfiBjh3fvGH/I8Il8=; b=lCJWSj6FvV6YXOL/SGlJ2Z+qLbaColkyYDbblmOn7Fb/57++oNnVzepyyFsNqSxdSf oMA5o4sY+VEyAR+sSxVIL2aXv2Bjma6i4nYuNxpUv+OsGDHBqEbALnEXsJ8N72QhxrE9 jSYlDxmiy/puELGP98tNqGQ3/nPvRkW0sBktEtc+/Vf026xAa2Uaz7PJ/MGF+iHdg93C 9IAxrdgtjV43/o7A/3S9M5kkHNGgj9g4oxdis0v5gEqkIL/puURJIikRXqV3YCvLo/AK pnP6SqpC2p22ztLjR+sjxxt5GPLw3KBVnEdOeu9ulPxStKq/eMlK8qt9o1kc8leHznRW C2+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VBWptZwV41wrybglM+V4M0H5NWdfiBjh3fvGH/I8Il8=; b=WYr70ecBRXOCu87QGcAA0l/ihppGfcylA6Aa2zhSKhkhT7i8MUIU9rHZlaLEhYSzFC fxEh+ci4Fkp9ORE8sz/ZX2eZG8eNXnlekNuk9uwdUMK86vA1ssj3WUSDfEwD7DX1ObYm Qh022flXeA0S/9yUVoMGwkBNfKQsjyjTutTGoqJKU/IjDukOKfDI97r9MJdjau5c8KmV FZbx0KRBf5UxL93S5cAZiBJfTIEhrPOrKz/3hi45yjmq9wkqPZaxDiPNm1Nq24fsSwNK 02Sc/tn9EBU2emy9yQvHvCWEs/aiXeZUcCD/sSynw3FCWIO7gcaAGgMDeeTM9U7jibmE qCgw== X-Gm-Message-State: APjAAAWIa/0NipcDpy8B0Rfom5fKlo0xHU3dq1yvLcE1ehbOWEvktfRQ UERA6fbB/zhrIlTvF4kC3nK2WbhGUfo= X-Google-Smtp-Source: APXvYqyttA+PAxzJyj67o13yz4DnKwhCU8O/yz5f99KDwMBEJwrqj8e8XHbVlZ1NS0t8O+jiSHho5Q== X-Received: by 2002:a63:d04e:: with SMTP id s14mr34727644pgi.189.1567625484790; Wed, 04 Sep 2019 12:31:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:09 -0700 Message-Id: <20190904193059.26202-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 19/69] target/arm: Convert T32 ADDW/SUBW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 24 +++++++++++++----------- target/arm/a32.decode | 1 + target/arm/t32.decode | 19 +++++++++++++++++++ 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 750331071b..7d12be4025 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7648,6 +7648,11 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) * Constant expanders for the decoders. */ =20 +static int negate(DisasContext *s, int x) +{ + return -x; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -8004,6 +8009,12 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri= _rot *a) #undef DO_ANY2 #undef DO_CMP2 =20 +static bool trans_ADR(DisasContext *s, arg_ri *a) +{ + store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm)); + return true; +} + /* * Multiply and multiply accumulate */ @@ -10724,17 +10735,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } store_reg(s, rd, tmp); } else { - /* Add/sub 12-bit immediate. */ - if (insn & (1 << 23)) { - imm =3D -imm; - } - tmp =3D add_reg_for_lit(s, rn, imm); - if (rn =3D=3D 13 && rd =3D=3D 13) { - /* ADD SP, SP, imm or SUB SP, SP, imm */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } + /* Add/sub 12-bit immediate, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c7f156be6d..aac991664d 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -30,6 +30,7 @@ &rrrr rd rn rm ra &rrr rd rn rm &rr rd rm +&ri rd imm &r rm &i imm &msr_reg rn r mask diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 5116c6165a..be4e5f087c 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -27,6 +27,7 @@ &rrrr !extern rd rn rm ra &rrr !extern rd rn rm &rr !extern rd rm +&ri !extern rd imm &r !extern rm &i !extern imm &msr_reg !extern rn r mask @@ -121,6 +122,24 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... .....= ... @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot =20 +# Data processing (plain binary immediate) + +%imm12_26_12_0 26:1 12:3 0:8 +%neg12_26_12_0 26:1 12:3 0:8 !function=3Dnegate +@s0_rri_12 .... ... .... . rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=3D%imm12_26_12_0 rot=3D0 s=3D0 + +{ + ADR 1111 0.1 0000 0 1111 0 ... rd:4 ........ \ + &ri imm=3D%imm12_26_12_0 + ADD_rri 1111 0.1 0000 0 .... 0 ... .... ........ @s0_rri_12 +} +{ + ADR 1111 0.1 0101 0 1111 0 ... rd:4 ........ \ + &ri imm=3D%neg12_26_12_0 + SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 +} + # Multiply and multiply accumulate =20 @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=a8H4t27w6832KquvYvlu5uopeAI47LGitZ7EzlLFkOY=; b=NfgKSfr30UVlZsAsO7kQDHIybDb1eLk3tQD4LH3hVMSIExUj2PLVVooVOb439LbI23 z9z2WRzW1awPFnkPC+hbRnHV+x8pgTT/ZSxlfj1Ju3MNBxoESMRFSf3FM0bXaELGxita /vHscm3GIauX00la+urW3iNFWlUP2l9zeMKB2HRgavPAVjJrhhgJWsFBDoD+hsGlUppY PI/q9oiD7qbqz0UvPBAxQ3VP2rul7Z1FkHGIMByUs/q3sZt9C1erTsAsFTDWezNx76G0 /IrazxRH0l2CjsjgVEn2SXxbfvPy2PPDBS/CYsGaV8HyLoCk2RwDqxZIoU/gUC0zbh01 C/+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=a8H4t27w6832KquvYvlu5uopeAI47LGitZ7EzlLFkOY=; b=EF0H1CGxb0lGPdyPKLz2if2GGYeAObtdqhgdwZWFOjtFTpuW/43qSD1H6pvJCaag72 X62PYwrncxsZfOYvwNaVFh/F2BOplrb83+M6gnYIrnb6uSLZtc2JL8yVJQYVkoCzsDbm 7mEpbwJsXxIEdUcrxOxopyf7AaTEVXp3OxsPjpuUOf/JYUkKNwWkG0DOPx+1Xw2C2Xwk n0hjfjg25iS51DuL8s3OaBjBnaazuoBxFNlGXCS6krk1NqHIj3zzHZ2HQEiGNhIW7ZXa Os2UNfDI2+n95ehDwMwFUmD6bUibYZYfvt9nzdRqftukUNCGay16Qj/oa9yxM+wNL+Am 3yJg== X-Gm-Message-State: APjAAAWLGcmSEQxA+RrbGzcpHGcQVCQYfGxyEq0hYWJAfOOZdovq2OjL uiz388GrxqG0tlN4gG27xh+xhvjpPdU= X-Google-Smtp-Source: APXvYqypjhhoC4cSeN2SpoNvsh+1vsCJlB9NNMe9naO5cDwIBKowdI+MQc18WHKRmwBaPzdyVuDO7g== X-Received: by 2002:a63:b346:: with SMTP id x6mr36947032pgt.218.1567625486149; Wed, 04 Sep 2019 12:31:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:10 -0700 Message-Id: <20190904193059.26202-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v4 20/69] target/arm: Convert load/store (register, immediate, literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for RT odd --- target/arm/translate.c | 805 ++++++++++++++++++----------------------- target/arm/a32.decode | 120 ++++++ target/arm/t32.decode | 141 ++++++++ 3 files changed, 623 insertions(+), 443 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7d12be4025..d383a16f4b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1265,62 +1265,6 @@ static inline void gen_hlt(DisasContext *s, int imm) unallocated_encoding(s); } =20 -static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, - TCGv_i32 var) -{ - int val, rm, shift, shiftop; - TCGv_i32 offset; - - if (!(insn & (1 << 25))) { - /* immediate */ - val =3D insn & 0xfff; - if (!(insn & (1 << 23))) - val =3D -val; - if (val !=3D 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* shift/register */ - rm =3D (insn) & 0xf; - shift =3D (insn >> 7) & 0x1f; - shiftop =3D (insn >> 5) & 3; - offset =3D load_reg(s, rm); - gen_arm_shift_im(offset, shiftop, shift, 0); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - -static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, - int extra, TCGv_i32 var) -{ - int val, rm; - TCGv_i32 offset; - - if (insn & (1 << 22)) { - /* immediate */ - val =3D (insn & 0xf) | ((insn >> 4) & 0xf0); - if (!(insn & (1 << 23))) - val =3D -val; - val +=3D extra; - if (val !=3D 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* register */ - if (extra) - tcg_gen_addi_i32(var, var, extra); - rm =3D (insn) & 0xf; - offset =3D load_reg(s, rm); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - static TCGv_ptr get_fpstatus_ptr(int neon) { TCGv_ptr statusptr =3D tcg_temp_new_ptr(); @@ -7658,6 +7602,11 @@ static int times_2(DisasContext *s, int x) return x * 2; } =20 +static int times_4(DisasContext *s, int x) +{ + return x * 4; +} + /* Return only the rotation part of T32ExpandImm. */ static int t32_expandimm_rot(DisasContext *s, int x) { @@ -8576,6 +8525,353 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } =20 +/* + * Load/store register index + */ + +static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) +{ + ISSInfo ret; + + /* ISS not valid if writeback */ + if (p && !w) { + ret =3D rd; + } else { + ret =3D ISSInvalid; + } + return ret; +} + +static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a) +{ + TCGv_i32 addr =3D load_reg(s, a->rn); + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + if (a->p) { + TCGv_i32 ofs =3D load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } + return addr; +} + +static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + TCGv_i32 ofs =3D load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, + MemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr =3D op_addr_rr_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_rr_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, + MemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr =3D op_addr_rr_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, 0); + return true; +} + +static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + addr =3D op_addr_rr_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt + 1, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_rr_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + addr =3D op_addr_rr_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D load_reg(s, a->rt + 1); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, -4); + return true; +} + +/* + * Load/store immediate index + */ + +static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a) +{ + int ofs =3D a->imm; + + if (!a->u) { + ofs =3D -ofs; + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + /* + * Stackcheck. Here we know 'addr' is the current SP; + * U is set if we're moving SP up, else down. It is + * UNKNOWN whether the limit check triggers when SP starts + * below the limit and ends up above it; we chose to do so. + */ + if (!a->u) { + TCGv_i32 newsp =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(newsp, cpu_R[13], ofs); + gen_helper_v8m_stackcheck(cpu_env, newsp); + tcg_temp_free_i32(newsp); + } else { + gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]); + } + } + + return add_reg_for_lit(s, a->rn, a->p ? ofs : 0); +} + +static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + if (a->u) { + address_offset +=3D a->imm; + } else { + address_offset -=3D a->imm; + } + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, + MemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_ri_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, + MemOp mop, int mem_idx) +{ + ISSInfo issinfo =3D make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, 0); + return true; +} + +static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, rt2, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_LDRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_ldrd_ri(s, a, a->rt + 1); +} + +static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b =3D { + .u =3D a->u, .w =3D a->w, .p =3D a->p, + .rn =3D a->rn, .rt =3D a->rt, .imm =3D a->imm + }; + return op_ldrd_ri(s, &b, a->rt2); +} + +static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx =3D get_mem_index(s); + TCGv_i32 addr, tmp; + + addr =3D op_addr_ri_pre(s, a); + + tmp =3D load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp =3D load_reg(s, rt2); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_strd_ri(s, a, a->rt + 1); +} + +static bool trans_STRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b =3D { + .u =3D a->u, .w =3D a->w, .p =3D a->p, + .rn =3D a->rn, .rt =3D a->rt, .imm =3D a->imm + }; + return op_strd_ri(s, &b, a->rt2); +} + +#define DO_LDST(NAME, WHICH, MEMOP) \ +static bool trans_##NAME##_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} \ +static bool trans_##NAME##_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} + +DO_LDST(LDR, load, MO_UL) +DO_LDST(LDRB, load, MO_UB) +DO_LDST(LDRH, load, MO_UW) +DO_LDST(LDRSB, load, MO_SB) +DO_LDST(LDRSH, load, MO_SW) + +DO_LDST(STR, store, MO_UL) +DO_LDST(STRB, store, MO_UB) +DO_LDST(STRH, store, MO_UW) + +#undef DO_LDST + /* * Legacy decoder. */ @@ -9033,100 +9329,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) } } } else { - int address_offset; - bool load =3D insn & (1 << 20); - bool wbit =3D insn & (1 << 21); - bool pbit =3D insn & (1 << 24); - bool doubleword =3D false; - ISSInfo issinfo; - - /* Misc load/store */ - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - - /* ISS not valid if writeback */ - issinfo =3D (pbit & !wbit) ? rd : ISSInvalid; - - if (!load && (sh & 2)) { - /* doubleword */ - ARCH(5TE); - if (rd & 1) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - load =3D (sh & 1) =3D=3D 0; - doubleword =3D true; - } - - addr =3D load_reg(s, rn); - if (pbit) { - gen_add_datah_offset(s, insn, 0, addr); - } - address_offset =3D 0; - - if (doubleword) { - if (!load) { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D load_reg(s, rd + 1); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } else { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - rd++; - } - address_offset =3D -4; - } else if (load) { - /* load */ - tmp =3D tcg_temp_new_i32(); - switch (sh) { - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - case 2: - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - default: - case 3: - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - } - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issi= nfo); - tcg_temp_free_i32(tmp); - } - /* Perform base writeback before the loaded value to - ensure correct behavior with overlapping index register= s. - ldrd with base writeback is undefined if the - destination and index registers overlap. */ - if (!pbit) { - gen_add_datah_offset(s, insn, address_offset, addr); - store_reg(s, rn, addr); - } else if (wbit) { - if (address_offset) - tcg_gen_addi_i32(addr, addr, address_offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (load) { - /* Complete the load. */ - store_reg(s, rd, tmp); - } + /* Extra load/store (register) instructions */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 0x4: @@ -9443,58 +9648,8 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) break; } do_ldst: - /* Check for undefined extension instructions - * per the ARM Bible IE: - * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx - */ - sh =3D (0xf << 20) | (0xf << 4); - if (op1 =3D=3D 0x7 && ((insn & sh) =3D=3D sh)) - { - goto illegal_op; - } - /* load/store byte/word */ - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - tmp2 =3D load_reg(s, rn); - if ((insn & 0x01200000) =3D=3D 0x00200000) { - /* ldrt/strt */ - i =3D get_a32_user_mem_index(s); - } else { - i =3D get_mem_index(s); - } - if (insn & (1 << 24)) - gen_add_data_offset(s, insn, tmp2); - if (insn & (1 << 20)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - if (insn & (1 << 22)) { - gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd); - } - } else { - /* store */ - tmp =3D load_reg(s, rd); - if (insn & (1 << 22)) { - gen_aa32_st8_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_st32_iss(s, tmp, tmp2, i, rd); - } - tcg_temp_free_i32(tmp); - } - if (!(insn & (1 << 24))) { - gen_add_data_offset(s, insn, tmp2); - store_reg(s, rn, tmp2); - } else if (insn & (1 << 21)) { - store_reg(s, rn, tmp2); - } else { - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) { - /* Complete the load. */ - store_reg_from_load(s, rd, tmp); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x08: case 0x09: { @@ -9795,75 +9950,8 @@ static void disas_thumb2_insn(DisasContext *s, uint3= 2_t insn) s->condexec_mask =3D 0; } } else if (insn & 0x01200000) { - /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (post-indexed) - * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (literal and immediate) - * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (pre-indexed) - */ - bool wback =3D extract32(insn, 21, 1); - - if (rn =3D=3D 15 && (insn & (1 << 21))) { - /* UNPREDICTABLE */ - goto illegal_op; - } - - addr =3D add_reg_for_lit(s, rn, 0); - offset =3D (insn & 0xff) * 4; - if ((insn & (1 << 23)) =3D=3D 0) { - offset =3D -offset; - } - - if (s->v8m_stackcheck && rn =3D=3D 13 && wback) { - /* - * Here 'addr' is the current SP; if offset is +ve we'= re - * moving SP up, else down. It is UNKNOWN whether the = limit - * check triggers when SP starts below the limit and e= nds - * up above it; check whichever of the current and fin= al - * SP is lower, so QEMU will trigger in that situation. - */ - if ((int32_t)offset < 0) { - TCGv_i32 newsp =3D tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, offset); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, offset); - offset =3D 0; - } - if (insn & (1 << 20)) { - /* ldrd */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rs, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* strd */ - tmp =3D load_reg(s, rs); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - if (wback) { - /* Base writeback. */ - tcg_gen_addi_i32(addr, addr, offset - 4); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* load/store dual, in decodetree */ + goto illegal_op; } else if ((insn & (1 << 23)) =3D=3D 0) { /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx * - load/store exclusive word @@ -10746,184 +10834,15 @@ static void disas_thumb2_insn(DisasContext *s, u= int32_t insn) } } break; - case 12: /* Load/store single data item. */ - { - int postinc =3D 0; - int writeback =3D 0; - int memidx; - ISSInfo issinfo; - + case 12: if ((insn & 0x01100000) =3D=3D 0x01000000) { if (disas_neon_ls_insn(s, insn)) { goto illegal_op; } break; } - op =3D ((insn >> 21) & 3) | ((insn >> 22) & 4); - if (rs =3D=3D 15) { - if (!(insn & (1 << 20))) { - goto illegal_op; - } - if (op !=3D 2) { - /* Byte or halfword load space with dest =3D=3D r15 : memo= ry hints. - * Catch them early so we don't emit pointless addressing = code. - * This space is a mix of: - * PLD/PLDW/PLI, which we implement as NOPs (note that u= nlike - * the ARM encodings, PLDW space doesn't UNDEF for non= -v7MP - * cores) - * unallocated hints, which must be treated as NOPs - * UNPREDICTABLE space, which we NOP or UNDEF depending on - * which is easiest for the decoding logic - * Some space which must UNDEF - */ - int op1 =3D (insn >> 23) & 3; - int op2 =3D (insn >> 6) & 0x3f; - if (op & 2) { - goto illegal_op; - } - if (rn =3D=3D 15) { - /* UNPREDICTABLE, unallocated hint or - * PLD/PLDW/PLI (literal) - */ - return; - } - if (op1 & 1) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - if ((op2 =3D=3D 0) || ((op2 & 0x3c) =3D=3D 0x30)) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - /* UNDEF space, or an UNPREDICTABLE */ - goto illegal_op; - } - } - memidx =3D get_mem_index(s); - imm =3D insn & 0xfff; - if (insn & (1 << 23)) { - /* PC relative or Positive offset. */ - addr =3D add_reg_for_lit(s, rn, imm); - } else if (rn =3D=3D 15) { - /* PC relative with negative offset. */ - addr =3D add_reg_for_lit(s, rn, -imm); - } else { - addr =3D load_reg(s, rn); - imm =3D insn & 0xff; - switch ((insn >> 8) & 0xf) { - case 0x0: /* Shifted Register. */ - shift =3D (insn >> 4) & 0xf; - if (shift > 3) { - tcg_temp_free_i32(addr); - goto illegal_op; - } - tmp =3D load_reg(s, rm); - tcg_gen_shli_i32(tmp, tmp, shift); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - break; - case 0xc: /* Negative offset. */ - tcg_gen_addi_i32(addr, addr, -imm); - break; - case 0xe: /* User privilege. */ - tcg_gen_addi_i32(addr, addr, imm); - memidx =3D get_a32_user_mem_index(s); - break; - case 0x9: /* Post-decrement. */ - imm =3D -imm; - /* Fall through. */ - case 0xb: /* Post-increment. */ - postinc =3D 1; - writeback =3D 1; - break; - case 0xd: /* Pre-decrement. */ - imm =3D -imm; - /* Fall through. */ - case 0xf: /* Pre-increment. */ - writeback =3D 1; - break; - default: - tcg_temp_free_i32(addr); - goto illegal_op; - } - } - - issinfo =3D writeback ? ISSInvalid : rs; - - if (s->v8m_stackcheck && rn =3D=3D 13 && writeback) { - /* - * Stackcheck. Here we know 'addr' is the current SP; - * if imm is +ve we're moving SP up, else down. It is - * UNKNOWN whether the limit check triggers when SP starts - * below the limit and ends up above it; we chose to do so. - */ - if ((int32_t)imm < 0) { - TCGv_i32 newsp =3D tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, imm); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (writeback && !postinc) { - tcg_gen_addi_i32(addr, addr, imm); - } - - if (insn & (1 << 20)) { - /* Load. */ - tmp =3D tcg_temp_new_i32(); - switch (op) { - case 0: - gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo); - break; - case 4: - gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo); - break; - case 5: - gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - store_reg_from_load(s, rs, tmp); - } else { - /* Store. */ - tmp =3D load_reg(s, rs); - switch (op) { - case 0: - gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - tcg_temp_free_i32(tmp); - } - if (postinc) - tcg_gen_addi_i32(addr, addr, imm); - if (writeback) { - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - } - break; + /* Load/store single data item, in decodetree */ + goto illegal_op; default: goto illegal_op; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index aac991664d..f7742deaee 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -37,6 +37,8 @@ &mrs_reg rd r &msr_bank rn r sysm &mrs_bank rd r sysm +&ldst_rr p w u rn rt rm shimm shtype +&ldst_ri p w u rn rt imm =20 # Data-processing (register) =20 @@ -222,3 +224,121 @@ HLT .... 0001 0000 .... .... .... 0111 .= ... @i16 BKPT .... 0001 0010 .... .... .... 0111 .... @i16 HVC .... 0001 0100 .... .... .... 0111 .... @i16 SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i + +# Load/Store Dual, Half, Signed Byte (register) + +@ldst_rr_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=3D1 shimm=3D0 shtype=3D0 +@ldst_rr_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=3D0 w=3D0 shimm=3D0 shtype=3D0 + +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_pw0 +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_p1w + +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_pw0 +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_p1w + +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_pw0 +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p1w + +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_pw0 +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p1w + +# Note the unpriv load/stores use the previously invalid P=3D0, W=3D1 enco= ding, +# and act as normal post-indexed (P=3D0, W=3D0). +@ldst_rr_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=3D0 w=3D0 shimm=3D0 shtype=3D0 + +STRHT_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRHT_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRSBT_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p0w1 +LDRSHT_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p0w1 + +# Load/Store word and unsigned byte (register) + +@ldst_rs_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=3D1 +@ldst_rs_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=3D0 w=3D0 + +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_pw0 +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p1w +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_pw0 +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p1w + +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p1w +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p1w + +@ldst_rs_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=3D0 w=3D0 + +STRT_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p0w1 +STRBT_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRT_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRBT_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p0w1 + +# Load/Store Dual, Half, Signed Byte (immediate) + +%imm8s_8_0 8:4 0:4 +@ldst_ri8_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=3D%imm8s_8_0 p=3D1 +@ldst_ri8_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=3D%imm8s_8_0 p=3D0 w=3D0 + +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_pw0 +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_p1w + +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_pw0 +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_p1w + +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_pw0 +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p1w + +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_pw0 +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p1w + +# Note the unpriv load/stores use the previously invalid P=3D0, W=3D1 enco= ding, +# and act as normal post-indexed (P=3D0, W=3D0). +@ldst_ri8_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=3D%imm8s_8_0 p=3D0 w=3D0 + +STRHT_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p0= w1 +LDRHT_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p0= w1 +LDRSBT_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p0= w1 +LDRSHT_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p0= w1 + +# Load/Store word and unsigned byte (immediate) + +@ldst_ri12_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 imm:12 &ldst_ri p= =3D1 +@ldst_ri12_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 imm:12 &ldst_ri p= =3D0 w=3D0 + +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p= 1w +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p= w0 +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= 1w +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= w0 + +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= 1w +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= w0 +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= 1w +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= w0 + +@ldst_ri12_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 imm:12 &ldst_ri p= =3D0 w=3D0 + +STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p= 0w1 +STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= 0w1 +LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= 0w1 +LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= 0w1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index be4e5f087c..a86597562b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -34,6 +34,8 @@ &mrs_reg !extern rd r &msr_bank !extern rn r sysm &mrs_bank !extern rd r sysm +&ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm =20 # Data-processing (register) =20 @@ -251,3 +253,142 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=3D%imm16_16_0 } + +# Load/store (register, immediate, literal) + +@ldst_rr .... .... .... rn:4 rt:4 ...... shimm:2 rm:4 \ + &ldst_rr p=3D1 w=3D0 u=3D1 shtype=3D0 +@ldst_ri_idx .... .... .... rn:4 rt:4 . p:1 u:1 . imm:8 \ + &ldst_ri w=3D1 +@ldst_ri_neg .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=3D1 w=3D0 u=3D0 +@ldst_ri_unp .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=3D1 w=3D0 u=3D1 +@ldst_ri_pos .... .... .... rn:4 rt:4 imm:12 \ + &ldst_ri p=3D1 w=3D0 u=3D1 +@ldst_ri_lit .... .... u:1 ... .... rt:4 imm:12 \ + &ldst_ri p=3D1 w=3D0 rn=3D15 + +STRB_rr 1111 1000 0000 .... .... 000000 .. .... @ldst_rr +STRB_ri 1111 1000 0000 .... .... 1..1 ........ @ldst_ri_idx +STRB_ri 1111 1000 0000 .... .... 1100 ........ @ldst_ri_neg +STRBT_ri 1111 1000 0000 .... .... 1110 ........ @ldst_ri_unp +STRB_ri 1111 1000 1000 .... .... ............ @ldst_ri_pos + +STRH_rr 1111 1000 0010 .... .... 000000 .. .... @ldst_rr +STRH_ri 1111 1000 0010 .... .... 1..1 ........ @ldst_ri_idx +STRH_ri 1111 1000 0010 .... .... 1100 ........ @ldst_ri_neg +STRHT_ri 1111 1000 0010 .... .... 1110 ........ @ldst_ri_unp +STRH_ri 1111 1000 1010 .... .... ............ @ldst_ri_pos + +STR_rr 1111 1000 0100 .... .... 000000 .. .... @ldst_rr +STR_ri 1111 1000 0100 .... .... 1..1 ........ @ldst_ri_idx +STR_ri 1111 1000 0100 .... .... 1100 ........ @ldst_ri_neg +STRT_ri 1111 1000 0100 .... .... 1110 ........ @ldst_ri_unp +STR_ri 1111 1000 1100 .... .... ............ @ldst_ri_pos + +# Note that Load, unsigned (literal) overlaps all other load encodings. +{ + { + NOP 1111 1000 -001 1111 1111 ------------ # PLD + LDRB_ri 1111 1000 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1001 ---- 1111 ------------ # PLD + LDRB_ri 1111 1000 1001 .... .... ............ @ldst_ri_pos + } + LDRB_ri 1111 1000 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0001 ---- 1111 1100 -------- # PLD + LDRB_ri 1111 1000 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRBT_ri 1111 1000 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0001 ---- 1111 000000 -- ---- # PLD + LDRB_rr 1111 1000 0001 .... .... 000000 .. .... @ldst_rr + } +} +{ + { + NOP 1111 1000 -011 1111 1111 ------------ # PLD + LDRH_ri 1111 1000 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1011 ---- 1111 ------------ # PLDW + LDRH_ri 1111 1000 1011 .... .... ............ @ldst_ri_pos + } + LDRH_ri 1111 1000 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0011 ---- 1111 1100 -------- # PLDW + LDRH_ri 1111 1000 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRHT_ri 1111 1000 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0011 ---- 1111 000000 -- ---- # PLDW + LDRH_rr 1111 1000 0011 .... .... 000000 .. .... @ldst_rr + } +} +{ + LDR_ri 1111 1000 .101 1111 .... ............ @ldst_ri_lit + LDR_ri 1111 1000 1101 .... .... ............ @ldst_ri_pos + LDR_ri 1111 1000 0101 .... .... 1..1 ........ @ldst_ri_idx + LDR_ri 1111 1000 0101 .... .... 1100 ........ @ldst_ri_neg + LDRT_ri 1111 1000 0101 .... .... 1110 ........ @ldst_ri_unp + LDR_rr 1111 1000 0101 .... .... 000000 .. .... @ldst_rr +} +# NOPs here are PLI. +{ + { + NOP 1111 1001 -001 1111 1111 ------------ + LDRSB_ri 1111 1001 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1001 ---- 1111 ------------ + LDRSB_ri 1111 1001 1001 .... .... ............ @ldst_ri_pos + } + LDRSB_ri 1111 1001 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0001 ---- 1111 1100 -------- + LDRSB_ri 1111 1001 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRSBT_ri 1111 1001 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0001 ---- 1111 000000 -- ---- + LDRSB_rr 1111 1001 0001 .... .... 000000 .. .... @ldst_rr + } +} +# NOPs here are unallocated memory hints, treated as NOP. +{ + { + NOP 1111 1001 -011 1111 1111 ------------ + LDRSH_ri 1111 1001 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1011 ---- 1111 ------------ + LDRSH_ri 1111 1001 1011 .... .... ............ @ldst_ri_pos + } + LDRSH_ri 1111 1001 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0011 ---- 1111 1100 -------- + LDRSH_ri 1111 1001 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRSHT_ri 1111 1001 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0011 ---- 1111 000000 -- ---- + LDRSH_rr 1111 1001 0011 .... .... 000000 .. .... @ldst_rr + } +} + +%imm8x4 0:8 !function=3Dtimes_4 +&ldst_ri2 p w u rn rt rt2 imm +@ldstd_ri8 .... .... u:1 ... rn:4 rt:4 rt2:4 ........ \ + &ldst_ri2 imm=3D%imm8x4 + +STRD_ri_t32 1110 1000 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D0 +LDRD_ri_t32 1110 1000 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D0 + +STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=3D= 0 p=3D1 +LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=3D= 0 p=3D1 + +STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 --=20 2.17.1 From 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 21/69] target/arm: Convert Synchronization primitives X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Fix arch test for {ld,st}rex[bh] Use unallocated_encoding for odd reg checks --- target/arm/translate.c | 576 +++++++++++++++++++++++------------------ target/arm/a32.decode | 48 ++++ target/arm/t32.decode | 46 ++++ 3 files changed, 412 insertions(+), 258 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d383a16f4b..ec80c9cbbc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8872,6 +8872,318 @@ DO_LDST(STRH, store, MO_UW) =20 #undef DO_LDST =20 +/* + * Synchronization primitives + */ + +static bool op_swp(DisasContext *s, arg_SWP *a, MemOp opc) +{ + TCGv_i32 addr, tmp; + TCGv taddr; + + opc |=3D s->be_data; + addr =3D load_reg(s, a->rn); + taddr =3D gen_aa32_addr(s, addr, opc); + tcg_temp_free_i32(addr); + + tmp =3D load_reg(s, a->rt2); + tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, get_mem_index(s), opc); + tcg_temp_free(taddr); + + store_reg(s, a->rt, tmp); + return true; +} + +static bool trans_SWP(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UL | MO_ALIGN); +} + +static bool trans_SWPB(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UB); +} + +/* + * Load/Store Exclusive and Load-Acquire/Store-Release + */ + +static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel) +{ + TCGv_i32 addr; + + if (rel) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + + addr =3D tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_store_exclusive(s, a->rd, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STREX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_strex(s, a, MO_32, false); +} + +static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 =3D a->rt + 1; + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXD_t32(DisasContext *s, arg_STREX *a) +{ + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXB(DisasContext *s, arg_STREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_8, false); +} + +static bool trans_STREXH(DisasContext *s, arg_STREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_16, false); +} + +static bool trans_STLEX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_32, true); +} + +static bool trans_STLEXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 =3D a->rt + 1; + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXD_t32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXB(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_8, true); +} + +static bool trans_STLEXH(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_16, true); +} + +static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr =3D load_reg(s, a->rn); + + tmp =3D load_reg(s, a->rt); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STL(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UL); +} + +static bool trans_STLB(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UB); +} + +static bool trans_STLH(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UW); +} + +static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq) +{ + TCGv_i32 addr; + + addr =3D tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_load_exclusive(s, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + + if (acq) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_LDREX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_ldrex(s, a, MO_32, false); +} + +static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 =3D a->rt + 1; + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXD_t32(DisasContext *s, arg_LDREX *a) +{ + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXB(DisasContext *s, arg_LDREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_8, false); +} + +static bool trans_LDREXH(DisasContext *s, arg_LDREX *a) +{ + if (s->thumb ? !ENABLE_ARCH_7 : !ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_16, false); +} + +static bool trans_LDAEX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_32, true); +} + +static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + if (a->rt & 1) { + unallocated_encoding(s); + return true; + } + a->rt2 =3D a->rt + 1; + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXD_t32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXB(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_8, true); +} + +static bool trans_LDAEXH(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_16, true); +} + +static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr =3D load_reg(s, a->rn); + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); + tcg_temp_free_i32(addr); + + store_reg(s, a->rt, tmp); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + return true; +} + +static bool trans_LDA(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UL); +} + +static bool trans_LDAB(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UB); +} + +static bool trans_LDAH(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UW); +} + /* * Legacy decoder. */ @@ -9167,172 +9479,8 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) case 0x0: case 0x1: /* multiplies, extra load/stores */ - sh =3D (insn >> 5) & 3; - if (sh =3D=3D 0) { - if (op1 =3D=3D 0x0) { - /* Multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops= . */ - goto illegal_op; - } else { - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - if (insn & (1 << 23)) { - /* load/store exclusive */ - bool is_ld =3D extract32(insn, 20, 1); - bool is_lasr =3D !extract32(insn, 8, 1); - int op2 =3D (insn >> 8) & 3; - op1 =3D (insn >> 21) & 0x3; - - switch (op2) { - case 0: /* lda/stl */ - if (op1 =3D=3D 1) { - goto illegal_op; - } - ARCH(8); - break; - case 1: /* reserved */ - goto illegal_op; - case 2: /* ldaex/stlex */ - ARCH(8); - break; - case 3: /* ldrex/strex */ - if (op1) { - ARCH(6K); - } else { - ARCH(6); - } - break; - } - - addr =3D tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - if (op2 =3D=3D 0) { - if (is_ld) { - tmp =3D tcg_temp_new_i32(); - switch (op1) { - case 0: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 2: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 3: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rd, tmp); - } else { - rm =3D insn & 0xf; - tmp =3D load_reg(s, rm); - switch (op1) { - case 0: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 2: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 3: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - switch (op1) { - case 0: /* ldrex */ - gen_load_exclusive(s, rd, 15, addr, 2); - break; - case 1: /* ldrexd */ - gen_load_exclusive(s, rd, rd + 1, addr, 3); - break; - case 2: /* ldrexb */ - gen_load_exclusive(s, rd, 15, addr, 0); - break; - case 3: /* ldrexh */ - gen_load_exclusive(s, rd, 15, addr, 1); - break; - default: - abort(); - } - } else { - rm =3D insn & 0xf; - switch (op1) { - case 0: /* strex */ - gen_store_exclusive(s, rd, rm, 15, addr, 2= ); - break; - case 1: /* strexd */ - gen_store_exclusive(s, rd, rm, rm + 1, add= r, 3); - break; - case 2: /* strexb */ - gen_store_exclusive(s, rd, rm, 15, addr, 0= ); - break; - case 3: /* strexh */ - gen_store_exclusive(s, rd, rm, 15, addr, 1= ); - break; - default: - abort(); - } - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - } else if ((insn & 0x00300f00) =3D=3D 0) { - /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx - * - SWP, SWPB - */ - - TCGv taddr; - MemOp opc =3D s->be_data; - - rm =3D (insn) & 0xf; - - if (insn & (1 << 22)) { - opc |=3D MO_UB; - } else { - opc |=3D MO_UL | MO_ALIGN; - } - - addr =3D load_reg(s, rn); - taddr =3D gen_aa32_addr(s, addr, opc); - tcg_temp_free_i32(addr); - - tmp =3D load_reg(s, rm); - tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, - get_mem_index(s), opc); - tcg_temp_free(taddr); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - } - } else { - /* Extra load/store (register) instructions */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; break; case 0x4: case 0x5: @@ -9987,15 +10135,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) } goto illegal_op; } - addr =3D tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); - if (insn & (1 << 20)) { - gen_load_exclusive(s, rs, 15, addr, 2); - } else { - gen_store_exclusive(s, rd, rs, 15, addr, 2); - } - tcg_temp_free_i32(addr); + /* Load/store exclusive, in decodetree */ + goto illegal_op; } else if ((insn & (7 << 5)) =3D=3D 0) { /* Table Branch. */ addr =3D load_reg(s, rn); @@ -10017,89 +10158,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tcg_gen_addi_i32(tmp, tmp, read_pc(s)); store_reg(s, 15, tmp); } else { - bool is_lasr =3D false; - bool is_ld =3D extract32(insn, 20, 1); - int op2 =3D (insn >> 6) & 0x3; - op =3D (insn >> 4) & 0x3; - switch (op2) { - case 0: - goto illegal_op; - case 1: - /* Load/store exclusive byte/halfword/doubleword */ - if (op =3D=3D 2) { - goto illegal_op; - } - ARCH(7); - break; - case 2: - /* Load-acquire/store-release */ - if (op =3D=3D 3) { - goto illegal_op; - } - /* Fall through */ - case 3: - /* Load-acquire/store-release exclusive */ - ARCH(8); - is_lasr =3D true; - break; - } - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - addr =3D tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - if (!(op2 & 1)) { - if (is_ld) { - tmp =3D tcg_temp_new_i32(); - switch (op) { - case 0: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(= s), - rs | ISSIsAcqRel); - break; - case 1: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index= (s), - rs | ISSIsAcqRel); - break; - case 2: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index= (s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rs, tmp); - } else { - tmp =3D load_reg(s, rs); - switch (op) { - case 0: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s= ), - rs | ISSIsAcqRel); - break; - case 1: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(= s), - rs | ISSIsAcqRel); - break; - case 2: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(= s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - gen_load_exclusive(s, rs, rd, addr, op); - } else { - gen_store_exclusive(s, rm, rs, rd, addr, op); - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } + /* Load/store exclusive, load-acq/store-rel, in decodetree= */ + goto illegal_op; } } else { /* Load/store multiple, RFE, SRS. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index f7742deaee..c76cbad569 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -39,6 +39,8 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&strex rn rd rt rt2 imm +&ldrex rn rt rt2 imm =20 # Data-processing (register) =20 @@ -342,3 +344,49 @@ STRT_ri .... 010. .0.0 .... .... ............= @ldst_ri12_p0w1 STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p= 0w1 LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p= 0w1 LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p= 0w1 + +# Synchronization primitives + +@swp ---- .... .... rn:4 rt:4 .... .... rt2:4 + +SWP .... 0001 0000 .... .... 0000 1001 .... @swp +SWPB .... 0001 0100 .... .... 0000 1001 .... @swp + +# Load/Store Exclusive and Load-Acquire/Store-Release +# +# Note rt2 for STREXD/LDREXD is set by the helper after checking rt is eve= n. + +@strex ---- .... .... rn:4 rd:4 .... .... rt:4 \ + &strex imm=3D0 rt2=3D15 +@ldrex ---- .... .... rn:4 rt:4 .... .... .... \ + &ldrex imm=3D0 rt2=3D15 +@stl ---- .... .... rn:4 .... .... .... rt:4 \ + &ldrex imm=3D0 rt2=3D15 + +STREX .... 0001 1000 .... .... 1111 1001 .... @strex +STREXD_a32 .... 0001 1010 .... .... 1111 1001 .... @strex +STREXB .... 0001 1100 .... .... 1111 1001 .... @strex +STREXH .... 0001 1110 .... .... 1111 1001 .... @strex + +STLEX .... 0001 1000 .... .... 1110 1001 .... @strex +STLEXD_a32 .... 0001 1010 .... .... 1110 1001 .... @strex +STLEXB .... 0001 1100 .... .... 1110 1001 .... @strex +STLEXH .... 0001 1110 .... .... 1110 1001 .... @strex + +STL .... 0001 1000 .... 1111 1100 1001 .... @stl +STLB .... 0001 1100 .... 1111 1100 1001 .... @stl +STLH .... 0001 1110 .... 1111 1100 1001 .... @stl + +LDREX .... 0001 1001 .... .... 1111 1001 1111 @ldrex +LDREXD_a32 .... 0001 1011 .... .... 1111 1001 1111 @ldrex +LDREXB .... 0001 1101 .... .... 1111 1001 1111 @ldrex +LDREXH .... 0001 1111 .... .... 1111 1001 1111 @ldrex + +LDAEX .... 0001 1001 .... .... 1110 1001 1111 @ldrex +LDAEXD_a32 .... 0001 1011 .... .... 1110 1001 1111 @ldrex +LDAEXB .... 0001 1101 .... .... 1110 1001 1111 @ldrex +LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex + +LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex +LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex +LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex diff --git a/target/arm/t32.decode b/target/arm/t32.decode index a86597562b..70cf8039d7 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -36,6 +36,8 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&strex !extern rn rd rt rt2 imm +&ldrex !extern rn rt rt2 imm =20 # Data-processing (register) =20 @@ -392,3 +394,47 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... .......= . @ldstd_ri8 w=3D0 p=3D1 =20 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 + +# Load/Store Exclusive and Load-Acquire/Store-Release + +@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ + &strex rt2=3D15 imm=3D%imm8x4 +@strex_0 .... .... .... rn:4 rt:4 .... .... rd:4 \ + &strex rt2=3D15 imm=3D0 +@strex_d .... .... .... rn:4 rt:4 rt2:4 .... rd:4 \ + &strex imm=3D0 + +@ldrex_i .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=3D15 imm=3D%imm8x4 +@ldrex_0 .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=3D15 imm=3D0 +@ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ + &ldrex imm=3D0 + +STREX 1110 1000 0100 .... .... .... .... .... @strex_i +STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 +STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 +STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d + +STLEX 1110 1000 1100 .... .... 1111 1110 .... @strex_0 +STLEXB 1110 1000 1100 .... .... 1111 1100 .... @strex_0 +STLEXH 1110 1000 1100 .... .... 1111 1101 .... @strex_0 +STLEXD_t32 1110 1000 1100 .... .... .... 1111 .... @strex_d + +STL 1110 1000 1100 .... .... 1111 1010 1111 @ldrex_0 +STLB 1110 1000 1100 .... .... 1111 1000 1111 @ldrex_0 +STLH 1110 1000 1100 .... .... 1111 1001 1111 @ldrex_0 + +LDREX 1110 1000 0101 .... .... 1111 .... .... @ldrex_i +LDREXB 1110 1000 1101 .... .... 1111 0100 1111 @ldrex_0 +LDREXH 1110 1000 1101 .... .... 1111 0101 1111 @ldrex_0 +LDREXD_t32 1110 1000 1101 .... .... .... 0111 1111 @ldrex_d + +LDAEX 1110 1000 1101 .... .... 1111 1110 1111 @ldrex_0 +LDAEXB 1110 1000 1101 .... .... 1111 1100 1111 @ldrex_0 +LDAEXH 1110 1000 1101 .... .... 1111 1101 1111 @ldrex_0 +LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d + +LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 +LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 +LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567626904; cv=none; d=zoho.com; s=zohoarc; b=LcoWFV7wr0KPsKZn+jFgwG5i2QS9B/izpTXf/sBEwDRhKpuaK9Khodqf95SrDKW1Zs6ICsZaKbhieHg/YKAVWc5/2wGCBS/nWo9CsSlX0kHQouqy8IvusqEUVxMvCk06j3skfeORGWiakIxH/BnzjvI5sVD+d+iaVburVqDcFeA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567626904; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=w4KLvtnzbGeNcUZz918DD9xSWUWeMSJ2fRY4zLuIN7M=; b=m0ZrSpuSBGQdrwSzyTPvjfo9cDXo5cpMb2VJJaJ+1yyT/IzbCxskf0AwEXpFiWW4DTP8F1PFzfXSlL30yoToISlnU8IuLKs4eznCT/VfakujaqFTR+j8RKHENRSamCR5y5WQoPXGAXaVZNemwWybJbx4xmILw///YcunEsqyHo8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567626904649538.7939603008452; Wed, 4 Sep 2019 12:55:04 -0700 (PDT) Received: from localhost ([::1]:37944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bMs-0003zi-Pi for importer@patchew.org; Wed, 04 Sep 2019 15:55:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40220) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b08-0004cd-Re for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b06-0002QL-O9 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:32 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:36832) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b06-0002Pp-EV for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:30 -0400 Received: by mail-pf1-x442.google.com with SMTP id y22so8276700pfr.3 for ; Wed, 04 Sep 2019 12:31:30 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 22/69] target/arm: Diagnose UNPREDICTABLE ldrex/strex cases X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 40 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ec80c9cbbc..9338873a4a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8912,6 +8912,18 @@ static bool op_strex(DisasContext *s, arg_STREX *a, = MemOp mop, bool rel) { TCGv_i32 addr; =20 + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rd =3D=3D 15 || a->rn =3D=3D 15 || a->rt =3D=3D 15 + || a->rd =3D=3D a->rn || a->rd =3D=3D a->rt + || (s->thumb && (a->rd =3D=3D 13 || a->rt =3D=3D 13)) + || (mop =3D=3D MO_64 + && (a->rt2 =3D=3D 15 + || a->rd =3D=3D a->rt2 || a->rt =3D=3D a->rt2 + || (s->thumb && a->rt2 =3D=3D 13)))) { + unallocated_encoding(s); + return true; + } + if (rel) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } @@ -8938,6 +8950,7 @@ static bool trans_STREXD_a32(DisasContext *s, arg_STR= EX *a) if (!ENABLE_ARCH_6K) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -8980,6 +8993,7 @@ static bool trans_STLEXD_a32(DisasContext *s, arg_STR= EX *a) if (!ENABLE_ARCH_8) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -9019,8 +9033,13 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemO= p mop) if (!ENABLE_ARCH_8) { return false; } - addr =3D load_reg(s, a->rn); + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rn =3D=3D 15 || a->rt =3D=3D 15) { + unallocated_encoding(s); + return true; + } =20 + addr =3D load_reg(s, a->rn); tmp =3D load_reg(s, a->rt); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); @@ -9050,6 +9069,16 @@ static bool op_ldrex(DisasContext *s, arg_LDREX *a, = MemOp mop, bool acq) { TCGv_i32 addr; =20 + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rn =3D=3D 15 || a->rt =3D=3D 15 + || (s->thumb && a->rt =3D=3D 13) + || (mop =3D=3D MO_64 + && (a->rt2 =3D=3D 15 || a->rt =3D=3D a->rt2 + || (s->thumb && a->rt2 =3D=3D 13)))) { + unallocated_encoding(s); + return true; + } + addr =3D tcg_temp_local_new_i32(); load_reg_var(s, addr, a->rn); tcg_gen_addi_i32(addr, addr, a->imm); @@ -9076,6 +9105,7 @@ static bool trans_LDREXD_a32(DisasContext *s, arg_LDR= EX *a) if (!ENABLE_ARCH_6K) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -9118,6 +9148,7 @@ static bool trans_LDAEXD_a32(DisasContext *s, arg_LDR= EX *a) if (!ENABLE_ARCH_8) { return false; } + /* We UNDEF for these UNPREDICTABLE cases. */ if (a->rt & 1) { unallocated_encoding(s); return true; @@ -9157,8 +9188,13 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemO= p mop) if (!ENABLE_ARCH_8) { return false; } - addr =3D load_reg(s, a->rn); + /* We UNDEF for these UNPREDICTABLE cases. */ + if (a->rn =3D=3D 15 || a->rt =3D=3D 15) { + unallocated_encoding(s); + return true; + } =20 + addr =3D load_reg(s, a->rn); tmp =3D tcg_temp_new_i32(); gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9EVYYItSGNQSywfg+zBeibu25FcUXVkBN++lQhzBXj0=; b=Li4LbwiE0oYalvKlZHVMqJt3VJRTDO73Rt92TjbJNJeZrdywh7g4ESP8C5wl+R4E/E 7LBKCKPkrq6iZtCVtkkuZ991TRbD/8LaWbegV/Qu+OXUkbjdWzw4JwFu3OpGxKPnvTy9 5Q/nJS1Ly721iJaIYawR5YTJ8OvKjmqHenatmWbjP9qVS+05NsNpClxAXbh7mrG8MZbD /qO6JPO0prxsCmRIrhhhVG97+OhVsZ5Z1QNr0Fe03wgfZDOej4H9vDIMQbEzGhSv1B/U 5Y4Owj1Y9W2dwKeWDhMiNcIAYxnDm9x5J0SMN0z6qsH2a+UyfIxuaGNzSa8wwsSaH5qs 4nbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9EVYYItSGNQSywfg+zBeibu25FcUXVkBN++lQhzBXj0=; b=PTfgTL64mBw5ObdJJ/XmvjSRgSedZHD3xWo/Fhnp/RMJIL31IZpWPzPqJ2PRJKf3su Ir5vhfPArfQQswEY9uSN/6K3E8h+huXl/EXkhPDk/CT0AE+KDad6BB31tF3Wcfw7yu5q 3cq7DqsX+GGvsgrQ1J9FIya8qQsoJcJ3MMb2FfRdpi0t4WOoGrk6fgq7eq7Sk6OC2cig s0CchZnkV6tIS5TkB5KnzRrhjQQDuyhUWmxgrt7uCEotYGyQ3m4VXUeNHXFdtPAxHSb+ 2Mg1qDWlKn/8muVq836SYJsBuHMKjaLoVoPlrLmgx9++slE8OGeYVrs8Uqc+rmXulktC uoQw== X-Gm-Message-State: APjAAAWtPSV1k7Vz7jT9ZfxIZ2iabRExERF+j8pzoEmLKp2FYZgbplcL DoRx53lVZoRVPqQI3/y8Z4yM5T1SUsc= X-Google-Smtp-Source: APXvYqyoPAOaEeL+f52zyOKNHtvJg9xWqCQ6mTJMdHUCuUlmKr9ywKqNh73JOM94AP23syj0Zwm4pQ== X-Received: by 2002:a63:3006:: with SMTP id w6mr36813812pgw.440.1567625490222; Wed, 04 Sep 2019 12:31:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:13 -0700 Message-Id: <20190904193059.26202-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 23/69] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In op_bfx, note that tcg_gen_{,s}extract_i32 already checks for width =3D=3D 32, so we don't need to special case that here. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding for out-of-range bitops. --- target/arm/translate.c | 201 +++++++++++++++++++++-------------------- target/arm/a32.decode | 20 ++++ target/arm/t32.decode | 19 ++++ 3 files changed, 144 insertions(+), 96 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9338873a4a..1c50ea232a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9220,6 +9220,104 @@ static bool trans_LDAH(DisasContext *s, arg_LDA *a) return op_lda(s, a, MO_UW); } =20 +/* + * Media instructions + */ + +static bool trans_USADA8(DisasContext *s, arg_USADA8 *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + gen_helper_usad8(t1, t1, t2); + tcg_temp_free_i32(t2); + if (a->ra !=3D 15) { + t2 =3D load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool op_bfx(DisasContext *s, arg_UBFX *a, bool u) +{ + TCGv_i32 tmp; + int width =3D a->widthm1 + 1; + int shift =3D a->lsb; + + if (!ENABLE_ARCH_6T2) { + return false; + } + if (shift + width > 32) { + /* UNPREDICTABLE; we choose to UNDEF */ + unallocated_encoding(s); + return true; + } + + tmp =3D load_reg(s, a->rn); + if (u) { + tcg_gen_extract_i32(tmp, tmp, shift, width); + } else { + tcg_gen_sextract_i32(tmp, tmp, shift, width); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SBFX(DisasContext *s, arg_SBFX *a) +{ + return op_bfx(s, a, false); +} + +static bool trans_UBFX(DisasContext *s, arg_UBFX *a) +{ + return op_bfx(s, a, true); +} + +static bool trans_BFCI(DisasContext *s, arg_BFCI *a) +{ + TCGv_i32 tmp; + int msb =3D a->msb, lsb =3D a->lsb; + int width; + + if (!ENABLE_ARCH_6T2) { + return false; + } + if (msb < lsb) { + /* UNPREDICTABLE; we choose to UNDEF */ + unallocated_encoding(s); + return true; + } + + width =3D msb + 1 - lsb; + if (a->rn =3D=3D 15) { + /* BFC */ + tmp =3D tcg_const_i32(0); + } else { + /* BFI */ + tmp =3D load_reg(s, a->rn); + } + if (width !=3D 32) { + TCGv_i32 tmp2 =3D load_reg(s, a->rd); + tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_UDF(DisasContext *s, arg_UDF *a) +{ + unallocated_encoding(s); + return true; +} + /* * Legacy decoder. */ @@ -9769,65 +9867,9 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) } break; case 3: - op1 =3D ((insn >> 17) & 0x38) | ((insn >> 5) & 7); - switch (op1) { - case 0: /* Unsigned sum of absolute differences. */ - ARCH(6); - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd !=3D 15) { - tmp2 =3D load_reg(s, rd); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - break; - case 0x20: case 0x24: case 0x28: case 0x2c: - /* Bitfield insert/clear. */ - ARCH(6T2); - shift =3D (insn >> 7) & 0x1f; - i =3D (insn >> 16) & 0x1f; - if (i < shift) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - i =3D i + 1 - shift; - if (rm =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rm); - } - if (i !=3D 32) { - tmp2 =3D load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, i); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - break; - case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */ - case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */ - ARCH(6T2); - tmp =3D load_reg(s, rm); - shift =3D (insn >> 7) & 0x1f; - i =3D ((insn >> 16) & 0x1f) + 1; - if (shift + i > 32) - goto illegal_op; - if (i < 32) { - if (op1 & 0x20) { - tcg_gen_extract_i32(tmp, tmp, shift, i); - } else { - tcg_gen_sextract_i32(tmp, tmp, shift, i); - } - } - store_reg(s, rd, tmp); - break; - default: - goto illegal_op; - } - break; + /* USAD, BFI, BFC, SBFX, UBFX */ + /* Done by decodetree */ + goto illegal_op; } break; } @@ -10466,10 +10508,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 0: /* 32 x 32 -> 32 */ case 1: /* 16 x 16 -> 32 */ case 3: /* 32 * 16 -> 32msb */ + case 7: /* Unsigned sum of absolute differences. */ /* in decodetree */ goto illegal_op; - case 7: /* Unsigned sum of absolute differences. */ - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ @@ -10534,15 +10575,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } tcg_temp_free_i32(tmp2); break; - case 7: /* Unsigned sum of absolute differences. */ - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) { - tmp2 =3D load_reg(s, rs); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; } store_reg(s, rd, tmp); break; @@ -10837,32 +10869,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) tmp =3D load_reg(s, rn); } switch (op) { - case 2: /* Signed bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_sextract_i32(tmp, tmp, shift, imm); - } - break; - case 6: /* Unsigned bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_extract_i32(tmp, tmp, shift, imm); - } - break; - case 3: /* Bitfield insert/clear. */ - if (imm < shift) - goto illegal_op; - imm =3D imm + 1 - shift; - if (imm !=3D 32) { - tmp2 =3D load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, imm= ); - tcg_temp_free_i32(tmp2); - } - break; + case 2: /* Signed bitfield extract, in decodetree */ + case 6: /* Unsigned bitfield extract, in decodetree */ + case 3: /* Bitfield insert/clear, in decodetree */ case 7: goto illegal_op; default: /* Saturate. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c76cbad569..285c08ca22 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -41,6 +41,8 @@ &ldst_ri p w u rn rt imm &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm +&bfx rd rn lsb widthm1 +&bfi rd rn lsb msb =20 # Data-processing (register) =20 @@ -390,3 +392,21 @@ LDAEXH .... 0001 1111 .... .... 1110 1001 11= 11 @ldrex LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex + +# Media instructions + +# usad8 is usada8 w/ ra=3D15 +USADA8 ---- 0111 1000 rd:4 ra:4 rm:4 0001 rn:4 + +# ubfx and sbfx +@bfx ---- .... ... widthm1:5 rd:4 lsb:5 ... rn:4 &bfx + +SBFX .... 0111 101 ..... .... ..... 101 .... @bfx +UBFX .... 0111 111 ..... .... ..... 101 .... @bfx + +# bfc is bfi w/ rn=3D15 +BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi + +# While we could get UDEF by not including this, add the pattern for +# documentation and to conflict with any other typos in this file. +UDF 1110 0111 1111 ---- ---- ---- 1111 ---- diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 70cf8039d7..682fc5c2c4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -38,6 +38,8 @@ &ldst_ri !extern p w u rn rt imm &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm +&bfx !extern rd rn lsb widthm1 +&bfi !extern rd rn lsb msb =20 # Data-processing (register) =20 @@ -144,6 +146,19 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... .....= ... @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } =20 +# Saturate, bitfield + +@bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ + &bfx lsb=3D%imm5_12_6 +@bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ + &bfi lsb=3D%imm5_12_6 + +SBFX 1111 0011 010 0 .... 0 ... .... ..0..... @bfx +UBFX 1111 0011 110 0 .... 0 ... .... ..0..... @bfx + +# bfc is bfi w/ rn=3D15 +BFCI 1111 0011 011 0 .... 0 ... .... ..0..... @bfi + # Multiply and multiply accumulate =20 @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=3D0 @@ -192,6 +207,9 @@ SMLALBT 1111 1011 1100 .... .... .... 1001 ...= . @rnadm SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm =20 +# usad8 is usada8 w/ ra=3D15 +USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm + # Data-processing (two source registers) =20 QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm @@ -254,6 +272,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ...= . @rdm SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=3D%imm16_16_0 + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- } =20 # Load/store (register, immediate, literal) --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 24/69] target/arm: Convert Parallel addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 229 ++++++++++++++++++++--------------------- target/arm/a32.decode | 44 ++++++++ target/arm/t32.decode | 44 ++++++++ 3 files changed, 200 insertions(+), 117 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1c50ea232a..181d3d77f0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -648,99 +648,6 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, int= shiftop, tcg_temp_free_i32(shift); } =20 -#define PAS_OP(pfx) \ - switch (op2) { \ - case 0: gen_pas_helper(glue(pfx,add16)); break; \ - case 1: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 2: gen_pas_helper(glue(pfx,subaddx)); break; \ - case 3: gen_pas_helper(glue(pfx,sub16)); break; \ - case 4: gen_pas_helper(glue(pfx,add8)); break; \ - case 7: gen_pas_helper(glue(pfx,sub8)); break; \ - } -static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32= b) -{ - TCGv_ptr tmp; - - switch (op1) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 1: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 5: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 2: - PAS_OP(q); - break; - case 3: - PAS_OP(sh); - break; - case 6: - PAS_OP(uq); - break; - case 7: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - -/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings= . */ -#define PAS_OP(pfx) \ - switch (op1) { \ - case 0: gen_pas_helper(glue(pfx,add8)); break; \ - case 1: gen_pas_helper(glue(pfx,add16)); break; \ - case 2: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 4: gen_pas_helper(glue(pfx,sub8)); break; \ - case 5: gen_pas_helper(glue(pfx,sub16)); break; \ - case 6: gen_pas_helper(glue(pfx,subaddx)); break; \ - } -static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_= i32 b) -{ - TCGv_ptr tmp; - - switch (op2) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 0: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 4: - tmp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 1: - PAS_OP(q); - break; - case 2: - PAS_OP(sh); - break; - case 5: - PAS_OP(uq); - break; - case 6: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - /* * Generate a conditional based on ARM condition code cc. * This is common between ARM and Aarch64 targets. @@ -9318,6 +9225,114 @@ static bool trans_UDF(DisasContext *s, arg_UDF *a) return true; } =20 +/* + * Parallel addition and subtraction + */ + +static bool op_par_addsub(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + + gen(t0, t0, t1); + + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +static bool op_par_addsub_ge(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, + TCGv_i32, TCGv_ptr)) +{ + TCGv_i32 t0, t1; + TCGv_ptr ge; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 =3D load_reg(s, a->rn); + t1 =3D load_reg(s, a->rm); + + ge =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE)); + gen(t0, t0, t1, ge); + + tcg_temp_free_ptr(ge); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_PAR_ADDSUB(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub(s, a, helper); \ +} + +#define DO_PAR_ADDSUB_GE(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub_ge(s, a, helper); \ +} + +DO_PAR_ADDSUB_GE(SADD16, gen_helper_sadd16) +DO_PAR_ADDSUB_GE(SASX, gen_helper_saddsubx) +DO_PAR_ADDSUB_GE(SSAX, gen_helper_ssubaddx) +DO_PAR_ADDSUB_GE(SSUB16, gen_helper_ssub16) +DO_PAR_ADDSUB_GE(SADD8, gen_helper_sadd8) +DO_PAR_ADDSUB_GE(SSUB8, gen_helper_ssub8) + +DO_PAR_ADDSUB_GE(UADD16, gen_helper_uadd16) +DO_PAR_ADDSUB_GE(UASX, gen_helper_uaddsubx) +DO_PAR_ADDSUB_GE(USAX, gen_helper_usubaddx) +DO_PAR_ADDSUB_GE(USUB16, gen_helper_usub16) +DO_PAR_ADDSUB_GE(UADD8, gen_helper_uadd8) +DO_PAR_ADDSUB_GE(USUB8, gen_helper_usub8) + +DO_PAR_ADDSUB(QADD16, gen_helper_qadd16) +DO_PAR_ADDSUB(QASX, gen_helper_qaddsubx) +DO_PAR_ADDSUB(QSAX, gen_helper_qsubaddx) +DO_PAR_ADDSUB(QSUB16, gen_helper_qsub16) +DO_PAR_ADDSUB(QADD8, gen_helper_qadd8) +DO_PAR_ADDSUB(QSUB8, gen_helper_qsub8) + +DO_PAR_ADDSUB(UQADD16, gen_helper_uqadd16) +DO_PAR_ADDSUB(UQASX, gen_helper_uqaddsubx) +DO_PAR_ADDSUB(UQSAX, gen_helper_uqsubaddx) +DO_PAR_ADDSUB(UQSUB16, gen_helper_uqsub16) +DO_PAR_ADDSUB(UQADD8, gen_helper_uqadd8) +DO_PAR_ADDSUB(UQSUB8, gen_helper_uqsub8) + +DO_PAR_ADDSUB(SHADD16, gen_helper_shadd16) +DO_PAR_ADDSUB(SHASX, gen_helper_shaddsubx) +DO_PAR_ADDSUB(SHSAX, gen_helper_shsubaddx) +DO_PAR_ADDSUB(SHSUB16, gen_helper_shsub16) +DO_PAR_ADDSUB(SHADD8, gen_helper_shadd8) +DO_PAR_ADDSUB(SHSUB8, gen_helper_shsub8) + +DO_PAR_ADDSUB(UHADD16, gen_helper_uhadd16) +DO_PAR_ADDSUB(UHASX, gen_helper_uhaddsubx) +DO_PAR_ADDSUB(UHSAX, gen_helper_uhsubaddx) +DO_PAR_ADDSUB(UHSUB16, gen_helper_uhsub16) +DO_PAR_ADDSUB(UHADD8, gen_helper_uhadd8) +DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) + +#undef DO_PAR_ADDSUB +#undef DO_PAR_ADDSUB_GE + /* * Legacy decoder. */ @@ -9630,16 +9645,8 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) rs =3D (insn >> 8) & 0xf; switch ((insn >> 23) & 3) { case 0: /* Parallel add/subtract. */ - op1 =3D (insn >> 20) & 7; - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - sh =3D (insn >> 5) & 7; - if ((op1 & 3) =3D=3D 0 || sh =3D=3D 5 || sh =3D=3D 6) - goto illegal_op; - gen_arm_parallel_addsub(op1, sh, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + /* Done by decodetree */ + goto illegal_op; case 1: if ((insn & 0x00700020) =3D=3D 0) { /* Halfword pack. */ @@ -10432,20 +10439,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } store_reg(s, rd, tmp); break; - case 2: /* SIMD add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - op =3D (insn >> 20) & 7; - shift =3D (insn >> 4) & 7; - if ((op & 3) =3D=3D 3 || (shift & 3) =3D=3D 3) - goto illegal_op; - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 2: /* SIMD add/subtract, in decodetree */ + goto illegal_op; case 3: /* Other data processing. */ op =3D ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 285c08ca22..4dfd8133f7 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -410,3 +410,47 @@ BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn= :4 &bfi # While we could get UDEF by not including this, add the pattern for # documentation and to conflict with any other typos in this file. UDF 1110 0111 1111 ---- ---- ---- 1111 ---- + +# Parallel addition and subtraction + +SADD16 .... 0110 0001 .... .... 1111 0001 .... @rndm +SASX .... 0110 0001 .... .... 1111 0011 .... @rndm +SSAX .... 0110 0001 .... .... 1111 0101 .... @rndm +SSUB16 .... 0110 0001 .... .... 1111 0111 .... @rndm +SADD8 .... 0110 0001 .... .... 1111 1001 .... @rndm +SSUB8 .... 0110 0001 .... .... 1111 1111 .... @rndm + +QADD16 .... 0110 0010 .... .... 1111 0001 .... @rndm +QASX .... 0110 0010 .... .... 1111 0011 .... @rndm +QSAX .... 0110 0010 .... .... 1111 0101 .... @rndm +QSUB16 .... 0110 0010 .... .... 1111 0111 .... @rndm +QADD8 .... 0110 0010 .... .... 1111 1001 .... @rndm +QSUB8 .... 0110 0010 .... .... 1111 1111 .... @rndm + +SHADD16 .... 0110 0011 .... .... 1111 0001 .... @rndm +SHASX .... 0110 0011 .... .... 1111 0011 .... @rndm +SHSAX .... 0110 0011 .... .... 1111 0101 .... @rndm +SHSUB16 .... 0110 0011 .... .... 1111 0111 .... @rndm +SHADD8 .... 0110 0011 .... .... 1111 1001 .... @rndm +SHSUB8 .... 0110 0011 .... .... 1111 1111 .... @rndm + +UADD16 .... 0110 0101 .... .... 1111 0001 .... @rndm +UASX .... 0110 0101 .... .... 1111 0011 .... @rndm +USAX .... 0110 0101 .... .... 1111 0101 .... @rndm +USUB16 .... 0110 0101 .... .... 1111 0111 .... @rndm +UADD8 .... 0110 0101 .... .... 1111 1001 .... @rndm +USUB8 .... 0110 0101 .... .... 1111 1111 .... @rndm + +UQADD16 .... 0110 0110 .... .... 1111 0001 .... @rndm +UQASX .... 0110 0110 .... .... 1111 0011 .... @rndm +UQSAX .... 0110 0110 .... .... 1111 0101 .... @rndm +UQSUB16 .... 0110 0110 .... .... 1111 0111 .... @rndm +UQADD8 .... 0110 0110 .... .... 1111 1001 .... @rndm +UQSUB8 .... 0110 0110 .... .... 1111 1111 .... @rndm + +UHADD16 .... 0110 0111 .... .... 1111 0001 .... @rndm +UHASX .... 0110 0111 .... .... 1111 0011 .... @rndm +UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm +UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm +UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm +UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 682fc5c2c4..c899c56766 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -457,3 +457,47 @@ LDAEXD_t32 1110 1000 1101 .... .... .... 1111 11= 11 @ldrex_d LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 + +# Parallel addition and subtraction + +SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm +QADD8 1111 1010 1000 .... 1111 .... 0001 .... @rndm +SHADD8 1111 1010 1000 .... 1111 .... 0010 .... @rndm +UADD8 1111 1010 1000 .... 1111 .... 0100 .... @rndm +UQADD8 1111 1010 1000 .... 1111 .... 0101 .... @rndm +UHADD8 1111 1010 1000 .... 1111 .... 0110 .... @rndm + +SADD16 1111 1010 1001 .... 1111 .... 0000 .... @rndm +QADD16 1111 1010 1001 .... 1111 .... 0001 .... @rndm +SHADD16 1111 1010 1001 .... 1111 .... 0010 .... @rndm +UADD16 1111 1010 1001 .... 1111 .... 0100 .... @rndm +UQADD16 1111 1010 1001 .... 1111 .... 0101 .... @rndm +UHADD16 1111 1010 1001 .... 1111 .... 0110 .... @rndm + +SASX 1111 1010 1010 .... 1111 .... 0000 .... @rndm +QASX 1111 1010 1010 .... 1111 .... 0001 .... @rndm +SHASX 1111 1010 1010 .... 1111 .... 0010 .... @rndm +UASX 1111 1010 1010 .... 1111 .... 0100 .... @rndm +UQASX 1111 1010 1010 .... 1111 .... 0101 .... @rndm +UHASX 1111 1010 1010 .... 1111 .... 0110 .... @rndm + +SSUB8 1111 1010 1100 .... 1111 .... 0000 .... @rndm +QSUB8 1111 1010 1100 .... 1111 .... 0001 .... @rndm +SHSUB8 1111 1010 1100 .... 1111 .... 0010 .... @rndm +USUB8 1111 1010 1100 .... 1111 .... 0100 .... @rndm +UQSUB8 1111 1010 1100 .... 1111 .... 0101 .... @rndm +UHSUB8 1111 1010 1100 .... 1111 .... 0110 .... @rndm + +SSUB16 1111 1010 1101 .... 1111 .... 0000 .... @rndm +QSUB16 1111 1010 1101 .... 1111 .... 0001 .... @rndm +SHSUB16 1111 1010 1101 .... 1111 .... 0010 .... @rndm +USUB16 1111 1010 1101 .... 1111 .... 0100 .... @rndm +UQSUB16 1111 1010 1101 .... 1111 .... 0101 .... @rndm +UHSUB16 1111 1010 1101 .... 1111 .... 0110 .... @rndm + +SSAX 1111 1010 1110 .... 1111 .... 0000 .... @rndm +QSAX 1111 1010 1110 .... 1111 .... 0001 .... @rndm +SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm +USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm +UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm +UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v4 25/69] target/arm: Convert packing, unpacking, saturation, and reversal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 541 ++++++++++++++++++----------------------- target/arm/a32.decode | 32 +++ target/arm/t32.decode | 37 ++- 3 files changed, 300 insertions(+), 310 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 181d3d77f0..a6de23c6d3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -355,7 +355,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) } =20 /* Byteswap each halfword. */ -static void gen_rev16(TCGv_i32 var) +static void gen_rev16(TCGv_i32 dest, TCGv_i32 var) { TCGv_i32 tmp =3D tcg_temp_new_i32(); TCGv_i32 mask =3D tcg_const_i32(0x00ff00ff); @@ -363,17 +363,17 @@ static void gen_rev16(TCGv_i32 var) tcg_gen_and_i32(tmp, tmp, mask); tcg_gen_and_i32(var, var, mask); tcg_gen_shli_i32(var, var, 8); - tcg_gen_or_i32(var, var, tmp); + tcg_gen_or_i32(dest, var, tmp); tcg_temp_free_i32(mask); tcg_temp_free_i32(tmp); } =20 /* Byteswap low halfword and sign extend. */ -static void gen_revsh(TCGv_i32 var) +static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) { tcg_gen_ext16u_i32(var, var); tcg_gen_bswap16_i32(var, var); - tcg_gen_ext16s_i32(var, var); + tcg_gen_ext16s_i32(dest, var); } =20 /* 32x32->64 multiply. Marks inputs as dead. */ @@ -426,7 +426,7 @@ static void gen_swap_half(TCGv_i32 var) t0 =3D (t0 + t1) ^ tmp; */ =20 -static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) +static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { TCGv_i32 tmp =3D tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, t0, t1); @@ -434,9 +434,8 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_gen_andi_i32(t0, t0, ~0x8000); tcg_gen_andi_i32(t1, t1, ~0x8000); tcg_gen_add_i32(t0, t0, t1); - tcg_gen_xor_i32(t0, t0, tmp); + tcg_gen_xor_i32(dest, t0, tmp); tcg_temp_free_i32(tmp); - tcg_temp_free_i32(t1); } =20 /* Set N and Z flags from var. */ @@ -6356,7 +6355,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } break; case NEON_2RM_VREV16: - gen_rev16(tmp); + gen_rev16(tmp, tmp); break; case NEON_2RM_VCLS: switch (size) { @@ -9333,13 +9332,225 @@ DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) #undef DO_PAR_ADDSUB #undef DO_PAR_ADDSUB_GE =20 +/* + * Packing, unpacking, saturation, and reversal + */ + +static bool trans_PKH(DisasContext *s, arg_PKH *a) +{ + TCGv_i32 tn, tm; + int shift =3D a->imm; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + tn =3D load_reg(s, a->rn); + tm =3D load_reg(s, a->rm); + if (a->tb) { + /* PKHTB */ + if (shift =3D=3D 0) { + shift =3D 31; + } + tcg_gen_sari_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tn, tm, 0, 16); + } else { + /* PKHBT */ + tcg_gen_shli_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tm, tn, 0, 16); + } + tcg_temp_free_i32(tm); + store_reg(s, a->rd, tn); + return true; +} + +static bool op_sat(DisasContext *s, arg_sat *a, + void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp, satimm; + int shift =3D a->imm; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp =3D load_reg(s, a->rn); + if (a->sh) { + tcg_gen_sari_i32(tmp, tmp, shift ? shift : 31); + } else { + tcg_gen_shli_i32(tmp, tmp, shift); + } + + satimm =3D tcg_const_i32(a->satimm); + gen(tmp, cpu_env, tmp, satimm); + tcg_temp_free_i32(satimm); + + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SSAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_ssat); +} + +static bool trans_USAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_usat); +} + +static bool trans_SSAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_ssat16); +} + +static bool trans_USAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_usat16); +} + +static bool op_xta(DisasContext *s, arg_rrr_rot *a, + void (*gen_extract)(TCGv_i32, TCGv_i32), + void (*gen_add)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp =3D load_reg(s, a->rm); + /* + * TODO: In many cases we could do a shift instead of a rotate. + * Combined with a simple extend, that becomes an extract. + */ + tcg_gen_rotri_i32(tmp, tmp, a->rot * 8); + gen_extract(tmp, tmp); + + if (a->rn !=3D 15) { + TCGv_i32 tmp2 =3D load_reg(s, a->rn); + gen_add(tmp, tmp, tmp2); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_sxtb16, gen_add16); +} + +static bool trans_UXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_uxtb16, gen_add16); +} + +static bool trans_SEL(DisasContext *s, arg_rrr *a) +{ + TCGv_i32 t1, t2, t3; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + t3 =3D tcg_temp_new_i32(); + tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE)); + gen_helper_sel_flags(t1, t3, t1, t2); + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_rr(DisasContext *s, arg_rr *a, + void (*gen)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + tmp =3D load_reg(s, a->rm); + gen(tmp, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_REV(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, tcg_gen_bswap32_i32); +} + +static bool trans_REV16(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_rev16); +} + +static bool trans_REVSH(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_revsh); +} + +static bool trans_RBIT(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6T2) { + return false; + } + return op_rr(s, a, gen_helper_rbit); +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; + unsigned int cond, val, op1, i, rm, rs, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 tmp3; @@ -9648,112 +9859,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) /* Done by decodetree */ goto illegal_op; case 1: - if ((insn & 0x00700020) =3D=3D 0) { - /* Halfword pack. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - shift =3D (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - /* pkhtb */ - if (shift =3D=3D 0) { - shift =3D 31; - } - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); - } else { - /* pkhbt */ - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00200020) =3D=3D 0x00200000) { - /* [us]sat */ - tmp =3D load_reg(s, rm); - shift =3D (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - if (shift =3D=3D 0) - shift =3D 31; - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - sh =3D (insn >> 16) & 0x1f; - tmp2 =3D tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00300fe0) =3D=3D 0x00200f20) { - /* [us]sat16 */ - tmp =3D load_reg(s, rm); - sh =3D (insn >> 16) & 0x1f; - tmp2 =3D tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00700fe0) =3D=3D 0x00000fa0) { - /* Select bytes. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - tmp3 =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState= , GE)); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x000003e0) =3D=3D 0x00000060) { - tmp =3D load_reg(s, rm); - shift =3D (insn >> 10) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op1 =3D (insn >> 20) & 7; - switch (op1) { - case 0: gen_sxtb16(tmp); break; - case 2: gen_sxtb(tmp); break; - case 3: gen_sxth(tmp); break; - case 4: gen_uxtb16(tmp); break; - case 6: gen_uxtb(tmp); break; - case 7: gen_uxth(tmp); break; - default: goto illegal_op; - } - if (rn !=3D 15) { - tmp2 =3D load_reg(s, rn); - if ((op1 & 3) =3D=3D 0) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - } else if ((insn & 0x003f0f60) =3D=3D 0x003f0f20) { - /* rev */ - tmp =3D load_reg(s, rm); - if (insn & (1 << 22)) { - if (insn & (1 << 7)) { - gen_revsh(tmp); - } else { - ARCH(6T2); - gen_helper_rbit(tmp, tmp); - } - } else { - if (insn & (1 << 7)) - gen_rev16(tmp); - else - tcg_gen_bswap32_i32(tmp, tmp); - } - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ + /* Done by decodetree */ + goto illegal_op; case 2: /* Multiplies (Type 3). */ switch ((insn >> 20) & 0x7) { case 5: @@ -10098,7 +10206,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, shift, offset; + uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10353,151 +10461,18 @@ static void disas_thumb2_insn(DisasContext *s, u= int32_t insn) } break; case 5: - - op =3D (insn >> 21) & 0xf; - if (op =3D=3D 6) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - /* Halfword pack. */ - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - shift =3D ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); - if (insn & (1 << 5)) { - /* pkhtb */ - if (shift =3D=3D 0) { - shift =3D 31; - } - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16); - } else { - /* pkhbt */ - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else { - /* Data processing register constant shift. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 13: /* Misc data processing. */ op =3D ((insn >> 22) & 6) | ((insn >> 7) & 1); if (op < 4 && (insn & 0xf000) !=3D 0xf000) goto illegal_op; switch (op) { case 0: /* Register controlled shift, in decodetree */ - goto illegal_op; - case 1: /* Sign/zero extend. */ - op =3D (insn >> 20) & 7; - switch (op) { - case 0: /* SXTAH, SXTH */ - case 1: /* UXTAH, UXTH */ - case 4: /* SXTAB, SXTB */ - case 5: /* UXTAB, UXTB */ - break; - case 2: /* SXTAB16, SXTB16 */ - case 3: /* UXTAB16, UXTB16 */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - default: - goto illegal_op; - } - if (rn !=3D 15) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - } - tmp =3D load_reg(s, rm); - shift =3D (insn >> 4) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op =3D (insn >> 20) & 7; - switch (op) { - case 0: gen_sxth(tmp); break; - case 1: gen_uxth(tmp); break; - case 2: gen_sxtb16(tmp); break; - case 3: gen_uxtb16(tmp); break; - case 4: gen_sxtb(tmp); break; - case 5: gen_uxtb(tmp); break; - default: - g_assert_not_reached(); - } - if (rn !=3D 15) { - tmp2 =3D load_reg(s, rn); - if ((op >> 1) =3D=3D 1) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - break; + case 1: /* Sign/zero extend, in decodetree */ case 2: /* SIMD add/subtract, in decodetree */ + case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 3: /* Other data processing. */ - op =3D ((insn >> 17) & 0x38) | ((insn >> 4) & 7); - if (op < 4) { - /* Saturating add/subtract. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - switch (op) { - case 0x0a: /* rbit */ - case 0x08: /* rev */ - case 0x09: /* rev16 */ - case 0x0b: /* revsh */ - break; - case 0x10: /* sel */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - case 0x18: /* clz, in decodetree */ - case 0x20: /* crc32/crc32c, in decodetree */ - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - goto illegal_op; - default: - goto illegal_op; - } - tmp =3D load_reg(s, rn); - switch (op) { - case 0x0a: /* rbit */ - gen_helper_rbit(tmp, tmp); - break; - case 0x08: /* rev */ - tcg_gen_bswap32_i32(tmp, tmp); - break; - case 0x09: /* rev16 */ - gen_rev16(tmp); - break; - case 0x0b: /* revsh */ - gen_revsh(tmp); - break; - case 0x10: /* sel */ - tmp2 =3D load_reg(s, rm); - tmp3 =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE= )); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - break; - default: - g_assert_not_reached(); - } - } - store_reg(s, rd, tmp); - break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ switch ((insn >> 20) & 7) { case 0: /* 32 x 32 -> 32 */ @@ -10851,60 +10826,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) * - Data-processing (plain binary immediate) */ if (insn & (1 << 24)) { - if (insn & (1 << 20)) - goto illegal_op; - /* Bitfield/Saturate. */ - op =3D (insn >> 21) & 7; - imm =3D insn & 0x1f; - shift =3D ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - if (rn =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp =3D load_reg(s, rn); - } - switch (op) { - case 2: /* Signed bitfield extract, in decodetree */ - case 6: /* Unsigned bitfield extract, in decodetree */ - case 3: /* Bitfield insert/clear, in decodetree */ - case 7: - goto illegal_op; - default: /* Saturate. */ - if (op & 1) { - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - tmp2 =3D tcg_const_i32(imm); - if (op & 4) { - /* Unsigned. */ - if ((op & 1) && shift =3D=3D 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_D= SP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - } - } else { - /* Signed. */ - if ((op & 1) && shift =3D=3D 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_D= SP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - } - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); + /* Bitfield/Saturate, in decodetree */ + goto illegal_op; } else { imm =3D ((insn & 0x04000000) >> 15) | ((insn & 0x7000) >> 4) | (insn & 0xff); @@ -11596,8 +11519,8 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) tmp =3D load_reg(s, rn); switch (op1) { case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp); break; - case 3: gen_revsh(tmp); break; + case 1: gen_rev16(tmp, tmp); break; + case 3: gen_revsh(tmp, tmp); break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4dfd8133f7..4990eb3839 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -28,6 +28,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr_rot rd rn rm rot &rrr rd rn rm &rr rd rm &ri rd imm @@ -43,6 +44,8 @@ &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 &bfi rd rn lsb msb +&sat rd rn satimm imm sh +&pkh rd rn rm imm tb =20 # Data-processing (register) =20 @@ -454,3 +457,32 @@ UHSAX .... 0110 0111 .... .... 1111 0101 ..= .. @rndm UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm + +# Packing, unpacking, saturation, and reversal + +PKH ---- 0110 1000 rn:4 rd:4 imm:5 tb:1 01 rm:4 &pkh + +@sat ---- .... ... satimm:5 rd:4 imm:5 sh:1 .. rn:4 &sat +@sat16 ---- .... .... satimm:4 rd:4 .... .... rn:4 \ + &sat imm=3D0 sh=3D0 + +SSAT .... 0110 101. .... .... .... ..01 .... @sat +USAT .... 0110 111. .... .... .... ..01 .... @sat + +SSAT16 .... 0110 1010 .... .... 1111 0011 .... @sat16 +USAT16 .... 0110 1110 .... .... 1111 0011 .... @sat16 + +@rrr_rot ---- .... .... rn:4 rd:4 rot:2 ...... rm:4 &rrr_rot + +SXTAB16 .... 0110 1000 .... .... ..00 0111 .... @rrr_rot +SXTAB .... 0110 1010 .... .... ..00 0111 .... @rrr_rot +SXTAH .... 0110 1011 .... .... ..00 0111 .... @rrr_rot +UXTAB16 .... 0110 1100 .... .... ..00 0111 .... @rrr_rot +UXTAB .... 0110 1110 .... .... ..00 0111 .... @rrr_rot +UXTAH .... 0110 1111 .... .... ..00 0111 .... @rrr_rot + +SEL .... 0110 1000 .... .... 1111 1011 .... @rndm +REV .... 0110 1011 1111 .... 1111 0011 .... @rdm +REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm +REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm +RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c899c56766..71f6d728f2 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -25,6 +25,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr_rot !extern rd rn rm rot &rrr !extern rd rn rm &rr !extern rd rm &ri !extern rd imm @@ -40,6 +41,8 @@ &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 &bfi !extern rd rn lsb msb +&sat !extern rd rn satimm imm sh +&pkh !extern rd rn rm imm tb =20 # Data-processing (register) =20 @@ -69,7 +72,8 @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... ....= @s_rrr_shi TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi } -# PKHBT, PKHTB at opc1 =3D 0110 +PKH 1110101 0110 0 rn:4 0 ... rd:4 .. tb:1 0 rm:4 \ + &pkh imm=3D%imm5_12_6 { CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi @@ -148,6 +152,20 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... .....= ... @s_rri_rot =20 # Saturate, bitfield =20 +@sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ + &sat imm=3D%imm5_12_6 +@sat16 .... .... .. . . rn:4 . ... rd:4 .. . satimm:5 \ + &sat sh=3D0 imm=3D0 + +{ + SSAT16 1111 0011 001 0 .... 0 000 .... 00 0 ..... @sat16 + SSAT 1111 0011 00. 0 .... 0 ... .... .. 0 ..... @sat +} +{ + USAT16 1111 0011 101 0 .... 0 000 .... 00 0 ..... @sat16 + USAT 1111 0011 10. 0 .... 0 ... .... .. 0 ..... @sat +} + @bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ &bfx lsb=3D%imm5_12_6 @bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ @@ -224,7 +242,13 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 ..= .. @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm =20 +SEL 1111 1010 1010 .... 1111 .... 1000 .... @rndm + # Note rn !=3D rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn. +REV 1111 1010 1001 ---- 1111 .... 1000 .... @rdm +REV16 1111 1010 1001 ---- 1111 .... 1001 .... @rdm +RBIT 1111 1010 1001 ---- 1111 .... 1010 .... @rdm +REVSH 1111 1010 1001 ---- 1111 .... 1011 .... @rdm CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm =20 # Branches and miscellaneous control @@ -501,3 +525,14 @@ SHSAX 1111 1010 1110 .... 1111 .... 0010 ..= .. @rndm USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm + +# Register extends + +@rrr_rot .... .... .... rn:4 .... rd:4 .. rot:2 rm:4 &rrr_rot + +SXTAH 1111 1010 0000 .... 1111 .... 10.. .... @rrr_rot +UXTAH 1111 1010 0001 .... 1111 .... 10.. .... @rrr_rot +SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot +UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot +SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot +UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH v4 26/69] target/arm: Convert Signed multiply, signed and unsigned divide X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 490 ++++++++++++++++++----------------------- target/arm/a32.decode | 22 ++ target/arm/t32.decode | 18 ++ 3 files changed, 258 insertions(+), 272 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a6de23c6d3..5b9b303467 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9544,18 +9544,228 @@ static bool trans_RBIT(DisasContext *s, arg_rr *a) return op_rr(s, a, gen_helper_rbit); } =20 +/* + * Signed multiply, signed and unsigned divide + */ + +static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + if (sub) { + /* This subtraction cannot overflow. */ + tcg_gen_sub_i32(t1, t1, t2); + } else { + /* + * This addition cannot overflow 32 bits; however it may + * overflow considered as a signed operation, in which case + * we must set the Q flag. + */ + gen_helper_add_setq(t1, cpu_env, t1, t2); + } + tcg_temp_free_i32(t2); + + if (a->ra !=3D 15) { + t2 =3D load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMLAD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, false); +} + +static bool trans_SMLADX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, false); +} + +static bool trans_SMLSD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, true); +} + +static bool trans_SMLSDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, true); +} + +static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + TCGv_i64 l1, l2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + l1 =3D tcg_temp_new_i64(); + l2 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(l1, t1); + tcg_gen_ext_i32_i64(l2, t2); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); + + if (sub) { + tcg_gen_sub_i64(l1, l1, l2); + } else { + tcg_gen_add_i64(l1, l1, l2); + } + tcg_temp_free_i64(l2); + + gen_addq(s, l1, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, l1); + tcg_temp_free_i64(l1); + return true; +} + +static bool trans_SMLALD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, false); +} + +static bool trans_SMLALDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, false); +} + +static bool trans_SMLSLD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, true); +} + +static bool trans_SMLSLDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, true); +} + +static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + tcg_gen_muls2_i32(t2, t1, t1, t2); + + if (a->ra !=3D 15) { + TCGv_i32 t3 =3D load_reg(s, a->ra); + if (sub) { + /* + * For SMMLS, we need a 64-bit subtract. Borrow caused by + * a non-zero multiplicand lowpart, and the correct result + * lowpart for rounding. + */ + TCGv_i32 zero =3D tcg_const_i32(0); + tcg_gen_sub2_i32(t2, t1, zero, t3, t2, t1); + tcg_temp_free_i32(zero); + } else { + tcg_gen_add_i32(t1, t1, t3); + } + tcg_temp_free_i32(t3); + } + if (round) { + /* + * Adding 0x80000000 to the 64-bit quantity means that we have + * carry in to the high word when the low word has the msb set. + */ + tcg_gen_shri_i32(t2, t2, 31); + tcg_gen_add_i32(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMMLA(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, false); +} + +static bool trans_SMMLAR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, false); +} + +static bool trans_SMMLS(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, true); +} + +static bool trans_SMMLSR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, true); +} + +static bool op_div(DisasContext *s, arg_rrr *a, bool u) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !dc_isar_feature(thumb_div, s) + : !dc_isar_feature(arm_div, s)) { + return false; + } + + t1 =3D load_reg(s, a->rn); + t2 =3D load_reg(s, a->rm); + if (u) { + gen_helper_udiv(t1, t1, t2); + } else { + gen_helper_sdiv(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, false); +} + +static bool trans_UDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, true); +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rm, rs, rn, rd; + unsigned int cond, val, op1, i, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; - TCGv_i64 tmp64; =20 /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -9838,157 +10048,10 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) switch(op1) { case 0x0: case 0x1: - /* multiplies, extra load/stores */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - break; case 0x4: case 0x5: - goto do_ldst; case 0x6: case 0x7: - if (insn & (1 << 4)) { - ARCH(6); - /* Armv6 Media instructions. */ - rm =3D insn & 0xf; - rn =3D (insn >> 16) & 0xf; - rd =3D (insn >> 12) & 0xf; - rs =3D (insn >> 8) & 0xf; - switch ((insn >> 23) & 3) { - case 0: /* Parallel add/subtract. */ - /* Done by decodetree */ - goto illegal_op; - case 1: - /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ - /* Done by decodetree */ - goto illegal_op; - case 2: /* Multiplies (Type 3). */ - switch ((insn >> 20) & 0x7) { - case 5: - if (((insn >> 6) ^ (insn >> 7)) & 1) { - /* op2 not 00x or 11x : UNDEF */ - goto illegal_op; - } - /* Signed multiply most significant [accumulate]. - (SMMUL, SMMLA, SMMLS) */ - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); - - if (rd !=3D 15) { - tmp3 =3D load_reg(s, rd); - if (insn & (1 << 6)) { - /* - * For SMMLS, we need a 64-bit subtract. - * Borrow caused by a non-zero multiplicand - * lowpart, and the correct result lowpart - * for rounding. - */ - TCGv_i32 zero =3D tcg_const_i32(0); - tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, - tmp2, tmp); - tcg_temp_free_i32(zero); - } else { - tcg_gen_add_i32(tmp, tmp, tmp3); - } - tcg_temp_free_i32(tmp3); - } - if (insn & (1 << 5)) { - /* - * Adding 0x80000000 to the 64-bit quantity - * means that we have carry in to the high - * word when the low word has the high bit set. - */ - tcg_gen_shri_i32(tmp2, tmp2, 31); - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - case 0: - case 4: - /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */ - if (insn & (1 << 7)) { - goto illegal_op; - } - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - if (insn & (1 << 5)) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* smlald, smlsld */ - TCGv_i64 tmp64_2; - - tmp64 =3D tcg_temp_new_i64(); - tmp64_2 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_gen_ext_i32_i64(tmp64_2, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 6)) { - tcg_gen_sub_i64(tmp64, tmp64, tmp64_2); - } else { - tcg_gen_add_i64(tmp64, tmp64, tmp64_2); - } - tcg_temp_free_i64(tmp64_2); - gen_addq(s, tmp64, rd, rn); - gen_storeq_reg(s, rd, rn, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* smuad, smusd, smlad, smlsd */ - if (insn & (1 << 6)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a - * signed operation, in which case we must= set - * the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp= 2); - } - tcg_temp_free_i32(tmp2); - if (rd !=3D 15) - { - tmp2 =3D load_reg(s, rd); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp= 2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - } - break; - case 1: - case 3: - /* SDIV, UDIV */ - if (!dc_isar_feature(arm_div, s)) { - goto illegal_op; - } - if (((insn >> 5) & 7) || (rd !=3D 15)) { - goto illegal_op; - } - tmp =3D load_reg(s, rm); - tmp2 =3D load_reg(s, rs); - if (insn & (1 << 21)) { - gen_helper_udiv(tmp, tmp, tmp2); - } else { - gen_helper_sdiv(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - default: - goto illegal_op; - } - break; - case 3: - /* USAD, BFI, BFC, SBFX, UBFX */ - /* Done by decodetree */ - goto illegal_op; - } - break; - } - do_ldst: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0x08: @@ -10210,9 +10273,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; - TCGv_i64 tmp64; int op; =20 /* @@ -10473,126 +10534,11 @@ static void disas_thumb2_insn(DisasContext *s, u= int32_t insn) case 2: /* SIMD add/subtract, in decodetree */ case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 4: case 5: /* 32-bit multiply. Sum of absolute differences. = */ - switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - case 1: /* 16 x 16 -> 32 */ - case 3: /* 32 * 16 -> 32msb */ - case 7: /* Unsigned sum of absolute differences. */ - /* in decodetree */ - goto illegal_op; - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - } - op =3D (insn >> 4) & 0xf; - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - switch ((insn >> 20) & 7) { - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - if (op) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a signed - * operation, in which case we must set the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - if (rs !=3D 15) - { - tmp2 =3D load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2); - if (rs !=3D 15) { - tmp3 =3D load_reg(s, rs); - if (insn & (1 << 20)) { - tcg_gen_add_i32(tmp, tmp, tmp3); - } else { - /* - * For SMMLS, we need a 64-bit subtract. - * Borrow caused by a non-zero multiplicand lowpar= t, - * and the correct result lowpart for rounding. - */ - TCGv_i32 zero =3D tcg_const_i32(0); - tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, tmp2, tmp); - tcg_temp_free_i32(zero); - } - tcg_temp_free_i32(tmp3); - } - if (insn & (1 << 4)) { - /* - * Adding 0x80000000 to the 64-bit quantity - * means that we have carry in to the high - * word when the low word has the high bit set. - */ - tcg_gen_shri_i32(tmp2, tmp2, 31); - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); - break; - case 6: case 7: /* 64-bit multiply, Divide. */ - op =3D ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); - tmp =3D load_reg(s, rn); - tmp2 =3D load_reg(s, rm); - if ((op & 0x50) =3D=3D 0x10) { - /* sdiv, udiv */ - if (!dc_isar_feature(thumb_div, s)) { - goto illegal_op; - } - if (op & 0x20) - gen_helper_udiv(tmp, tmp, tmp2); - else - gen_helper_sdiv(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((op & 0xe) =3D=3D 0xc) { - /* Dual multiply accumulate long. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - if (op & 1) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (op & 0x10) { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - /* BUGFIX */ - tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rs, rd); - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* Signed/unsigned 64-bit multiply, in decodetree */ - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - break; + case 4: case 5: + /* 32-bit multiply. Sum of absolute differences, in decodetre= e */ + goto illegal_op; + case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ + goto illegal_op; } break; case 6: case 7: case 14: case 15: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4990eb3839..d7a333b90b 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -486,3 +486,25 @@ REV .... 0110 1011 1111 .... 1111 0011 ..= .. @rdm REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm + +# Signed multiply, signed and unsigned divide + +@rdmn ---- .... .... rd:4 .... rm:4 .... rn:4 &rrr + +SMLAD .... 0111 0000 .... .... .... 0001 .... @rdamn +SMLADX .... 0111 0000 .... .... .... 0011 .... @rdamn +SMLSD .... 0111 0000 .... .... .... 0101 .... @rdamn +SMLSDX .... 0111 0000 .... .... .... 0111 .... @rdamn + +SDIV .... 0111 0001 .... 1111 .... 0001 .... @rdmn +UDIV .... 0111 0011 .... 1111 .... 0001 .... @rdmn + +SMLALD .... 0111 0100 .... .... .... 0001 .... @rdamn +SMLALDX .... 0111 0100 .... .... .... 0011 .... @rdamn +SMLSLD .... 0111 0100 .... .... .... 0101 .... @rdamn +SMLSLDX .... 0111 0100 .... .... .... 0111 .... @rdamn + +SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn +SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn +SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn +SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 71f6d728f2..677acb698d 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -228,6 +228,24 @@ SMLALTT 1111 1011 1100 .... .... .... 1011 ..= .. @rnadm # usad8 is usada8 w/ ra=3D15 USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm =20 +SMLAD 1111 1011 0010 .... .... .... 0000 .... @rnadm +SMLADX 1111 1011 0010 .... .... .... 0001 .... @rnadm +SMLSD 1111 1011 0100 .... .... .... 0000 .... @rnadm +SMLSDX 1111 1011 0100 .... .... .... 0001 .... @rnadm + +SMLALD 1111 1011 1100 .... .... .... 1100 .... @rnadm +SMLALDX 1111 1011 1100 .... .... .... 1101 .... @rnadm +SMLSLD 1111 1011 1101 .... .... .... 1100 .... @rnadm +SMLSLDX 1111 1011 1101 .... .... .... 1101 .... @rnadm + +SMMLA 1111 1011 0101 .... .... .... 0000 .... @rnadm +SMMLAR 1111 1011 0101 .... .... .... 0001 .... @rnadm +SMMLS 1111 1011 0110 .... .... .... 0000 .... @rnadm +SMMLSR 1111 1011 0110 .... .... .... 0001 .... @rnadm + +SDIV 1111 1011 1001 .... 1111 .... 1111 .... @rndm +UDIV 1111 1011 1011 .... 1111 .... 1111 .... @rndm + # Data-processing (two source registers) =20 QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 27/69] target/arm: Convert MOVW, MOVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 89 ++++++++++++++++-------------------------- target/arm/a32.decode | 6 +++ target/arm/t32.decode | 9 +++++ 3 files changed, 48 insertions(+), 56 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5b9b303467..b7d26f7cc8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7870,6 +7870,34 @@ static bool trans_ADR(DisasContext *s, arg_ri *a) return true; } =20 +static bool trans_MOVW(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp =3D tcg_const_i32(a->imm); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MOVT(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp =3D load_reg(s, a->rd); + tcg_gen_ext16u_i32(tmp, tmp); + tcg_gen_ori_i32(tmp, tmp, a->imm << 16); + store_reg(s, a->rd, tmp); + return true; +} + /* * Multiply and multiply accumulate */ @@ -9762,7 +9790,7 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn, rd; + unsigned int cond, val, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10011,26 +10039,8 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) /* fall back to legacy decoder */ =20 if ((insn & 0x0f900000) =3D=3D 0x03000000) { - if ((insn & (1 << 21)) =3D=3D 0) { - ARCH(6T2); - rd =3D (insn >> 12) & 0xf; - val =3D ((insn >> 4) & 0xf000) | (insn & 0xfff); - if ((insn & (1 << 22)) =3D=3D 0) { - /* MOVW */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, val); - } else { - /* MOVT */ - tmp =3D load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, val << 16); - } - store_reg(s, rd, tmp); - } else { - /* MSR (immediate) and hints */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if ((insn & 0x0f900000) =3D=3D 0x01000000 && (insn & 0x00000090) !=3D 0x00000090) { /* miscellaneous instructions */ @@ -10765,42 +10775,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) /* * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx * - Data-processing (modified immediate, plain binary immedi= ate) + * All in decodetree. */ - if (insn & (1 << 25)) { - /* - * 0b1111_0x1x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (plain binary immediate) - */ - if (insn & (1 << 24)) { - /* Bitfield/Saturate, in decodetree */ - goto illegal_op; - } else { - imm =3D ((insn & 0x04000000) >> 15) - | ((insn & 0x7000) >> 4) | (insn & 0xff); - if (insn & (1 << 22)) { - /* 16-bit immediate. */ - imm |=3D (insn >> 4) & 0xf000; - if (insn & (1 << 23)) { - /* movt */ - tmp =3D load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, imm << 16); - } else { - /* movw */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, imm); - } - store_reg(s, rd, tmp); - } else { - /* Add/sub 12-bit immediate, in decodetree */ - goto illegal_op; - } - } - } else { - /* Data-processing (modified immediate) */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + goto illegal_op; } break; case 12: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index d7a333b90b..341882e637 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -73,6 +73,12 @@ MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 ..= .. @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi =20 +%imm16 16:4 0:12 +@mov16 ---- .... .... .... rd:4 ............ &ri imm=3D%i= mm16 + +MOVW .... 0011 0000 .... .... ............ @mov16 +MOVT .... 0011 0100 .... .... ............ @mov16 + # Data-processing (register-shifted register) =20 @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 677acb698d..f315fde0f4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -150,6 +150,15 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... .....= ... @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } =20 +# Move Wide + +%imm16_26_16_12_0 16:4 26:1 12:3 0:8 +@mov16 .... .... .... .... .... rd:4 .... .... \ + &ri imm=3D%imm16_26_16_12_0 + +MOVW 1111 0.10 0100 .... 0 ... .... ........ @mov16 +MOVT 1111 0.10 1100 .... 0 ... .... ........ @mov16 + # Saturate, bitfield =20 @sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567627041; cv=none; d=zoho.com; s=zohoarc; b=R9uZAETWWGhnHnAouyOxbIpi1Jl+z/ukJk+DZjsKsjhw4VgxoZhhnRecUjxX2/J1LVh4i3Fh1wocNjmiqvYXXa1dcl3ACV9rzBgWyyLxfqOTaD6ObGrEO8Z62RE42y6tE98o0CUgSuPtalBszI0iAA82APVBlhDTBXnccPNS7iA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567627041; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=BBXbQPZIVt2C5TSZNQAU4v9y0CqssCskt3ZWxo2XK/s=; b=ALqxMJo954J91ag8evZDpRlSJEo2S5XcTB39g7aCahfDb+9k+bzQURKsYrcNWxy35S57qwZgJy2pTRfgee8hjSzmcaGlmKP1ffHyTBCqNcxb7z0gzPUUBK3kJzbojV8+hRJgg65i8f0SCnRBLWnuIRursJvvSdRudgUTmEmbLrA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567627041308321.3691200683055; Wed, 4 Sep 2019 12:57:21 -0700 (PDT) Received: from localhost ([::1]:38054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bOy-0007Ei-D5 for importer@patchew.org; Wed, 04 Sep 2019 15:57:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40448) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0K-0004tz-2v for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0F-0002Yj-Id for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:43 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:39241) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0F-0002Xs-7J for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:39 -0400 Received: by mail-pf1-x432.google.com with SMTP id s12so6915963pfe.6 for ; Wed, 04 Sep 2019 12:31:38 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BBXbQPZIVt2C5TSZNQAU4v9y0CqssCskt3ZWxo2XK/s=; b=LnxX8rTqpYomTYr8Kh2GsIdLly36XqMqA6cKO62A4a37ulZ4V0TYEz/hTWCteflc5S hCiSGw7biQWZGXujrQArKQjAmxDQr1Ff4GAu4MlSpGLAqmZ2bvpcZZEMjwGSFKqrdOlp k7mhb92xoDFkk5ywa16sLDbEAkghX3Y6ni1GiU34jXmLdl2AQwM1F60WHodXqjcHLGMk NBhac7KIQYejpSKfRl7U1pC56pE84iejJCoiXkTC8DqbItOBZDhwm1zipdLh4QYZuvKw P42bPDB533Nl1lkrUoiurRCQK7No85z1NWAr6ft3qx2WFLBeSPyqe4mvsGA8/Ky7vFeW nQ3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BBXbQPZIVt2C5TSZNQAU4v9y0CqssCskt3ZWxo2XK/s=; b=hRV04ry3BR1zvCe18AOd7ai8VNfH2BShNL3Ux0fjHT307kvSJ1tiPgQEEnem5fXWkO ctgRBGlgCqF1bkAggml7H59DkGzo9dtHyxzvhZ68AXsO2oCBydRoy+5eyzM/S9XTaLHL tbn/NZ12tHXgMr5c9d2OweyTHdfXW+xFDuWfMwL2JcJ4jPIy1S2bGmLkrtdH3O7edNI/ OAfNDBGd/NORBwXVvx/3xWaSmVo1S+n+7kqU0cQuooO005NpVFiQIel8oaN431MbUJDx YqqAgzCZWMhwpFi0yJ6IGLlySMIcYklWxiNY8NoFGv99GeN9VGOUWYV7WCBKD0TBgkC8 xWqA== X-Gm-Message-State: APjAAAVCbuq1PZhunwCpHmD/hm59EVSsor2J5xH0nA8xt3OXOFeFYfHi 6x9HEYesdcN/YJjfZlsuv18neJIvVcI= X-Google-Smtp-Source: APXvYqyzdMr7Y9jvuMc0SSMs6FFeO7T0WtFFgshZ6JbDVWDHRiPG1EoTl6xwc/bLzRMxZ+uajGUQgg== X-Received: by 2002:a63:f857:: with SMTP id v23mr36328845pgj.228.1567625497446; Wed, 04 Sep 2019 12:31:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:18 -0700 Message-Id: <20190904193059.26202-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PATCH v4 28/69] target/arm: Convert LDM, STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This includes a minor bug fix to LDM (user), which requires bit 21 to be 0, which means no writeback. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 428 ++++++++++++++++++++++------------------- target/arm/a32.decode | 6 + target/arm/t32.decode | 10 + 3 files changed, 246 insertions(+), 198 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b7d26f7cc8..1f3c7bbd54 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9784,6 +9784,232 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) return op_div(s, a, true); } =20 +/* + * Block data transfer + */ + +static TCGv_i32 op_addr_block_pre(DisasContext *s, arg_ldst_block *a, int = n) +{ + TCGv_i32 addr =3D load_reg(s, a->rn); + + if (a->b) { + if (a->i) { + /* pre increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n !=3D 1) { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + /* + * If the writeback is incrementing SP rather than + * decrementing it, and the initial SP is below the + * stack limit but the final written-back SP would + * be above, then then we must not perform any memory + * accesses, but it is IMPDEF whether we generate + * an exception. We choose to do so in this case. + * At this point 'addr' is the lowest address, so + * either the original SP (if incrementing) or our + * final SP (if decrementing), so that's what we check. + */ + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + return addr; +} + +static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, + TCGv_i32 addr, int n) +{ + if (a->w) { + /* write back */ + if (!a->b) { + if (a->i) { + /* post increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n !=3D 1) { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } +} + +static bool op_stm(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + bool user =3D a->u; + TCGv_i32 addr, tmp, tmp2; + + if (user) { + /* STM (user) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + unallocated_encoding(s); + return true; + } + } + + list =3D a->list; + n =3D ctpop16(list); + /* TODO: test invalid n =3D=3D 0 case */ + + addr =3D op_addr_block_pre(s, a, n); + mem_idx =3D get_mem_index(s); + + for (i =3D j =3D 0; i < 16; i++) { + if (!(list & (1 << i))) { + continue; + } + + if (user && i !=3D 15) { + tmp =3D tcg_temp_new_i32(); + tmp2 =3D tcg_const_i32(i); + gen_helper_get_user_reg(tmp, cpu_env, tmp2); + tcg_temp_free_i32(tmp2); + } else { + tmp =3D load_reg(s, i); + } + gen_aa32_st32(s, tmp, addr, mem_idx); + tcg_temp_free_i32(tmp); + + /* No need to add after the last transfer. */ + if (++j !=3D n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + return true; +} + +static bool trans_STM(DisasContext *s, arg_ldst_block *a) +{ + return op_stm(s, a); +} + +static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback register in register list is UNPREDICTABLE for T32. */ + if (a->w && (a->list & (1 << a->rn))) { + unallocated_encoding(s); + return true; + } + return op_stm(s, a); +} + +static bool do_ldm(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + bool loaded_base; + bool user =3D a->u; + bool exc_return =3D false; + TCGv_i32 addr, tmp, tmp2, loaded_var; + + if (user) { + /* LDM (user), LDM (exception return) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + unallocated_encoding(s); + return true; + } + if (extract32(a->list, 15, 1)) { + exc_return =3D true; + user =3D false; + } else { + /* LDM (user) does not allow writeback. */ + if (a->w) { + unallocated_encoding(s); + return true; + } + } + } + + list =3D a->list; + n =3D ctpop16(list); + /* TODO: test invalid n =3D=3D 0 case */ + + addr =3D op_addr_block_pre(s, a, n); + mem_idx =3D get_mem_index(s); + loaded_base =3D false; + loaded_var =3D NULL; + + for (i =3D j =3D 0; i < 16; i++) { + if (!(list & (1 << i))) { + continue; + } + + tmp =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, tmp, addr, mem_idx); + if (user) { + tmp2 =3D tcg_const_i32(i); + gen_helper_set_user_reg(cpu_env, tmp2, tmp); + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + } else if (i =3D=3D a->rn) { + loaded_var =3D tmp; + loaded_base =3D true; + } else if (i =3D=3D 15 && exc_return) { + store_pc_exc_ret(s, tmp); + } else { + store_reg_from_load(s, i, tmp); + } + + /* No need to add after the last transfer. */ + if (++j !=3D n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + + if (loaded_base) { + store_reg(s, a->rn, loaded_var); + } + + if (exc_return) { + /* Restore CPSR from SPSR. */ + tmp =3D load_cpu_field(spsr); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_cpsr_write_eret(cpu_env, tmp); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } + tcg_temp_free_i32(tmp); + /* Must exit loop to check un-masked IRQs */ + s->base.is_jmp =3D DISAS_EXIT; + } + return true; +} + +static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) +{ + return do_ldm(s, a); +} + +static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback register in register list is UNPREDICTABLE for T32. */ + if (a->w && (a->list & (1 << a->rn))) { + unallocated_encoding(s); + return true; + } + return do_ldm(s, a); +} + /* * Legacy decoder. */ @@ -10062,139 +10288,10 @@ static void disas_arm_insn(DisasContext *s, unsi= gned int insn) case 0x5: case 0x6: case 0x7: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0x08: case 0x09: - { - int j, n, loaded_base; - bool exc_return =3D false; - bool is_load =3D extract32(insn, 20, 1); - bool user =3D false; - TCGv_i32 loaded_var; - /* load/store multiple words */ - /* XXX: store correct base if write back */ - if (insn & (1 << 22)) { - /* LDM (user), LDM (exception return) and STM (user) */ - if (IS_USER(s)) - goto illegal_op; /* only usable in supervisor mode= */ - - if (is_load && extract32(insn, 15, 1)) { - exc_return =3D true; - } else { - user =3D true; - } - } - rn =3D (insn >> 16) & 0xf; - addr =3D load_reg(s, rn); - - /* compute total size */ - loaded_base =3D 0; - loaded_var =3D NULL; - n =3D 0; - for (i =3D 0; i < 16; i++) { - if (insn & (1 << i)) - n++; - } - /* XXX: test invalid n =3D=3D 0 case ? */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - tcg_gen_addi_i32(addr, addr, 4); - } else { - /* post increment */ - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } else { - /* post decrement */ - if (n !=3D 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); - } - } - j =3D 0; - for (i =3D 0; i < 16; i++) { - if (insn & (1 << i)) { - if (is_load) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (user) { - tmp2 =3D tcg_const_i32(i); - gen_helper_set_user_reg(cpu_env, tmp2, tmp= ); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - } else if (i =3D=3D rn) { - loaded_var =3D tmp; - loaded_base =3D 1; - } else if (i =3D=3D 15 && exc_return) { - store_pc_exc_ret(s, tmp); - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* store */ - if (i =3D=3D 15) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, read_pc(s)); - } else if (user) { - tmp =3D tcg_temp_new_i32(); - tmp2 =3D tcg_const_i32(i); - gen_helper_get_user_reg(tmp, cpu_env, tmp2= ); - tcg_temp_free_i32(tmp2); - } else { - tmp =3D load_reg(s, i); - } - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - j++; - /* no need to add after the last transfer */ - if (j !=3D n) - tcg_gen_addi_i32(addr, addr, 4); - } - } - if (insn & (1 << 21)) { - /* write back */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - } else { - /* post increment */ - tcg_gen_addi_i32(addr, addr, 4); - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - if (n !=3D 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4= )); - } else { - /* post decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (exc_return) { - /* Restore CPSR from SPSR. */ - tmp =3D load_cpu_field(spsr); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_cpsr_write_eret(cpu_env, tmp); - tcg_temp_free_i32(tmp); - /* Must exit loop to check un-masked IRQs */ - s->base.is_jmp =3D DISAS_EXIT; - } - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xa: case 0xb: { @@ -10461,73 +10558,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) insn & (1 << 21)); } } else { - int i, loaded_base =3D 0; - TCGv_i32 loaded_var; - bool wback =3D extract32(insn, 21, 1); - /* Load/store multiple. */ - addr =3D load_reg(s, rn); - offset =3D 0; - for (i =3D 0; i < 16; i++) { - if (insn & (1 << i)) - offset +=3D 4; - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck && rn =3D=3D 13 && wback) { - /* - * If the writeback is incrementing SP rather than - * decrementing it, and the initial SP is below the - * stack limit but the final written-back SP would - * be above, then then we must not perform any memory - * accesses, but it is IMPDEF whether we generate - * an exception. We choose to do so in this case. - * At this point 'addr' is the lowest address, so - * either the original SP (if incrementing) or our - * final SP (if decrementing), so that's what we check. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - loaded_var =3D NULL; - for (i =3D 0; i < 16; i++) { - if ((insn & (1 << i)) =3D=3D 0) - continue; - if (insn & (1 << 20)) { - /* Load. */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i =3D=3D rn) { - loaded_var =3D tmp; - loaded_base =3D 1; - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* Store. */ - tmp =3D load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (wback) { - /* Base register writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* Fault if writeback register is in register list. */ - if (insn & (1 << rn)) - goto illegal_op; - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* Load/store multiple, in decodetree */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 341882e637..1267a689e2 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -40,6 +40,7 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&ldst_block rn i b u w list &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 @@ -514,3 +515,8 @@ SMMLA .... 0111 0101 .... .... .... 0001 ...= . @rdamn SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn + +# Block data transfer + +STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block +LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f315fde0f4..f1e2b934f8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -37,6 +37,7 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 @@ -563,3 +564,12 @@ SXTAB16 1111 1010 0010 .... 1111 .... 10.. ..= .. @rrr_rot UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot + +# Load/store multiple + +@ldstm .... .... .. w:1 . rn:4 list:16 &ldst_block = u=3D0 + +STM_t32 1110 1000 10.0 .... ................ @ldstm i=3D1= b=3D0 +STM_t32 1110 1001 00.0 .... ................ @ldstm i=3D0= b=3D1 +LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 +LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aH/3YEr2M2jm0vMpMPf4pJC6xbTf5AjfAwZZFhTAH2w=; b=e63ejY72sEioWyaiQCpLM3xEYOOAhhtw0DG4+SExnKUVjm9aNEKrL5btXq6wusbXSr sS5pXwwUvKG7CnaJ+j0TkkVMql1OXsUFn++2Fgx4nkd7cUt8RBrtIxF/CDBLifWEqRFV pSbry/0Y6PduCsEzuD/nlGtmRJxDykFisKGaE+HfeP6Hdr8NYK+MTHqrLH97k+ogZ0c3 Wb3zHxSNq2Baw2Zsb4yCLJeNrDM39lTmIfFRSznj6BUEHFnoSkdquRZuyGLK5jUTCULq 0oF3x8N61lU51LFDOBPEfxXB9W8/nXPkcUDx0snA+SVjnENxfg8c+8lfh3rU8yySqv5b lY/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aH/3YEr2M2jm0vMpMPf4pJC6xbTf5AjfAwZZFhTAH2w=; b=KC+owVVlIqBjpFg5DO6fyUkYiNteLGA1asdnw28eUZDQDbTkux/NdImuGamZaIql2o PpJvUhpLCijW3xdVk0S+3pDION2PuQUopxUrTZ2Pbeeefr9NpVp6c8nDAV7bjRcElYac UcGJw1bKNQPYImeBjI2zO0CUMPICBkpEeQbCy/gdwEUJfXhKTyrwMziO3/dW6xZBtS3u CG0EuMC4omV39sqGWHMjl4zpnr2SS77QMDRJDKl3sbn7tZcCBhLelK7lHf+SOhOiYpfA ld5A4QbgsNechijDrADyoHY97mTDiJNqd2127xpe/fh9w1lxlYgEQq6rAImUYDfaDehF H6Qw== X-Gm-Message-State: APjAAAWpOYYIaSe3c221csoq/wrf2tGE/8DHO0Ki1+uL/U9vfxkD5yHf ZepeK1od/SL8PAOtklGzeSaO4UA5uEk= X-Google-Smtp-Source: APXvYqxC/slEzOdenOWMz6a9YBW/Vyod8EJuAFm2zCYnqfDpd3mnKa3FKIiALemXtvP80GC22cWNng== X-Received: by 2002:aa7:9117:: with SMTP id 23mr24816920pfh.94.1567625498662; Wed, 04 Sep 2019 12:31:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:19 -0700 Message-Id: <20190904193059.26202-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 29/69] target/arm: Diagnose writeback register in list for LDM for v7 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Prior to v7, for the A32 encoding, this operation wrote an UNKNOWN value back to the base register. Starting in v7 this is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1f3c7bbd54..b67e7389d3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9997,6 +9997,15 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *= a) =20 static bool trans_LDM_a32(DisasContext *s, arg_ldst_block *a) { + /* + * Writeback register in register list is UNPREDICTABLE + * for ArchVersion() >=3D 7. Prior to v7, A32 would write + * an UNKNOWN value to the base register. + */ + if (ENABLE_ARCH_7 && a->w && (a->list & (1 << a->rn))) { + unallocated_encoding(s); + return true; + } return do_ldm(s, a); } =20 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567627374; cv=none; d=zoho.com; s=zohoarc; b=Tc0ZpfRsgXDctRubImQfmzR2So26oK2XUAi32xuHZ6klffFIn57fdkWtC1mmecTJxdDbkpPk0rmHEM/dwKlycLAozWLz2oh2UM8FcMHnuT/7DAIolRYksiKRelvBQdiZgjrovhNtiQP3Wpm09rHc3FwdbbByzmQjpY9h4uluPOI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567627374; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=aOeT7JW4syMFoke9pOSfcUTMmUalFkDrt8zliWzFSBI=; b=EcAzEryWmYzD7BUXcJF63MmTE6P2mHEbM6OQqJoCoMM2t3Tinohhzb8YeZgA0hKlLFMxOj3RxA+RBmbslDjGifYiCiuumfOpTV0Dh1p/QtC1M2cBD7sWgZPnWiFz3Jow2OpNYrBGyvTP4XNckU+9hOFL8jzBKZxD3tDQtHwxXrE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567627374564474.3671182961624; Wed, 4 Sep 2019 13:02:54 -0700 (PDT) Received: from localhost ([::1]:38186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bUP-0003xh-LF for importer@patchew.org; Wed, 04 Sep 2019 16:02:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40453) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0K-0004u8-AC for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0H-0002aI-F2 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:44 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:37428) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0H-0002ZU-4K for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:41 -0400 Received: by mail-pf1-x443.google.com with SMTP id y9so13910790pfl.4 for ; Wed, 04 Sep 2019 12:31:40 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aOeT7JW4syMFoke9pOSfcUTMmUalFkDrt8zliWzFSBI=; b=PC6P+R2ZIPGunwlvD2YZXGgZJOQ06RN/RE+cazziFhPqltlTlTHhEBUn1au/EFJ66N rM3GuU10yZlTqBGrGqxvOnRrbAlPrJcg3WscIfqDvXTm5QNyroTBJ5J2P7UL6hSR12zY Ast5tqsMYeXVrXC727LXHyi58efXyYV86n9seuxEajOJXQ1i/eOruSIspq7fJUbr9dtK lyuRKeSOgIoRs62B+vaapzDgyId1v2kh/UX2LgubKTvudTyosqcqJpmF5r57PRN2HLqh 4+ScQuJ6KRksTDqOb/GeI88pizOyAA3AYWhB3MGmubZOIXB5BMKjATees9YbYKy1D3wq noTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aOeT7JW4syMFoke9pOSfcUTMmUalFkDrt8zliWzFSBI=; b=pNE6w6CowiE7q5imAFCsLywZtL2MZmnfXRr2x3l24udVtv2c3KdHov1r/hfyt0mEYr XCrzrhuCInqaxTfyXPL+COcpSt+7nEaVOdwamFBN9IHuF12vi+rW6mhJKsnLLyhPMtdZ 6bQpuHVUKbtDlm/MhvPQ8wDxM/fHTG2zwWdcnFmCUrw5eXWFwXFwTA/fycyIEDKfZBIK oFIi44Ti5Zs7+b4sPDLJcL3R3bFW1RljZeiA7kMPTlTAy2N4xyO0Y1JRabADqapPRBm/ Ph7ez31UDGqZp7phjuft6jiwf6Vk9zJU+GwoVdr9UJN7xieLGhaiT9gCpTMvZFi3O/qb csbw== X-Gm-Message-State: APjAAAWF5Um4Sdf/GvZPHiPCe/0uvoVRnZY8/Ia8KUc5QZz85VXVWrHk +qXjFl5D5DzBmZaB/cDpHnPKHkvBBkQ= X-Google-Smtp-Source: APXvYqxMls52XxXZlM05hnIB2WIpnp+BFSyg4bKNPOLazo/V9w00WzQ8G3tkYHRXL8OsBILTzXVwRw== X-Received: by 2002:a17:90a:fd8c:: with SMTP id cx12mr6705903pjb.95.1567625499743; Wed, 04 Sep 2019 12:31:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:20 -0700 Message-Id: <20190904193059.26202-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v4 30/69] target/arm: Diagnose too few registers in list for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This has been a TODO item for quite a while. The minimum bit count for A32 and T16 is 1, and for T32 is 2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b67e7389d3..b623dbcd48 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9846,7 +9846,7 @@ static void op_addr_block_post(DisasContext *s, arg_l= dst_block *a, } } =20 -static bool op_stm(DisasContext *s, arg_ldst_block *a) +static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool user =3D a->u; @@ -9863,7 +9863,10 @@ static bool op_stm(DisasContext *s, arg_ldst_block *= a) =20 list =3D a->list; n =3D ctpop16(list); - /* TODO: test invalid n =3D=3D 0 case */ + if (n < min_n) { + unallocated_encoding(s); + return true; + } =20 addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); @@ -9896,7 +9899,8 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a) =20 static bool trans_STM(DisasContext *s, arg_ldst_block *a) { - return op_stm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return op_stm(s, a, 1); } =20 static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a) @@ -9906,10 +9910,11 @@ static bool trans_STM_t32(DisasContext *s, arg_ldst= _block *a) unallocated_encoding(s); return true; } - return op_stm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return op_stm(s, a, 2); } =20 -static bool do_ldm(DisasContext *s, arg_ldst_block *a) +static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) { int i, j, n, list, mem_idx; bool loaded_base; @@ -9938,7 +9943,10 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *= a) =20 list =3D a->list; n =3D ctpop16(list); - /* TODO: test invalid n =3D=3D 0 case */ + if (n < min_n) { + unallocated_encoding(s); + return true; + } =20 addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); @@ -10006,7 +10014,8 @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst= _block *a) unallocated_encoding(s); return true; } - return do_ldm(s, a); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); } =20 static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a) @@ -10016,7 +10025,8 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst= _block *a) unallocated_encoding(s); return true; } - return do_ldm(s, a); + /* BitCount(list) < 2 is UNPREDICTABLE */ + return do_ldm(s, a, 2); } =20 /* --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567626858; cv=none; d=zoho.com; s=zohoarc; b=CIUxFKg22asAZR2AUSobxST9++wmdZO0k2ueBuMHeYAzrkpROnsaeIgPsEfIdftLsuL+wXSe1w8VQaVWEnA5dM47cJyTsdev7txMOMhTCafzX5YZcX6hGIsotieql6Dcv+WpA0kYAAG/pK2So2M424cA0aM+45MUudwpq1MUSEg= ARC-Message-Signature: i=1; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U7L/XkW0Sx1L9zkCTuOn1y4+61r+0iIpJsvReD5rmxY=; b=RbPthGKhSrOSS/iRPvl4YUByTNVFLfRkCYR0MMaJdkJP1MXbEvc9Eh8/eOAWr5UL2q 5dwl8TcXzfR8zbmekhwzfQGlI2dcHwjqkfxtxrLZZbjWxne3v5fSMsCKNtbaw1mknDO9 I5sjMs1PhysxDvBOWqbKfyqjhuWXF+oXB9gXK8vxwaDRfFyK7trqAldSkS1XR8+M8+rR A6ccsgl+RtlC1vL88j6i4d7cMfC09bowUN0RT6yZJK8zgCI7OISbdnvjTzl2gqfIIXnB Zw+EfhqjKRZxHGR3mf1KbE8vw1VUJ2MGxZIIbJNbwXI58Fx91kbReSAfDCk/9lbS7PN6 G2GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U7L/XkW0Sx1L9zkCTuOn1y4+61r+0iIpJsvReD5rmxY=; b=pBVrgAECmLI6EzzxhCxdzGrjF2hbiAR47E/tWV28/l02Ik0o+T3F9F9fMYVfmdYEZM n3TuT1Yvjz0mSPsXQpa1T+70LRSxd0cnU94UJg41M0cnSOovy9N0HHKw+3WdJ7ZdXVdX Ca5KOQ94sk0j/ZEiBuTSVSn38F/5cMx/rrzgrOvtTTsdGw2LADCYHFsm+aJ7cdK/Jllb 2ulzC7ggvFTT2VWJ5lrEArkRpS3AzHDjcRb9dJYhZFCQKX1llJ401IUjDWileN8YdHfx n0WbyDGb+BtnJO4X7+kdnQg0Mmk5QRPDN/i3/lIugOBabtoB/vft1Fs4CHHMvqbPrs2L h9GQ== X-Gm-Message-State: APjAAAWJ1oi7OGLO2HlR2PLsQretCuekKqp996nTRxOT9RIF9whkZ/sY 75vXcLUHSdqlqGR4RzHOj0powxjgSrU= X-Google-Smtp-Source: APXvYqxwtfbKSp8K0QvXtfQ+Jt1eP5HJ1f8k485c+oZo715zqU2ssjUNAHpB4WOu81zfyhg776Gf6w== X-Received: by 2002:a65:6557:: with SMTP id a23mr36592316pgw.439.1567625500863; Wed, 04 Sep 2019 12:31:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:21 -0700 Message-Id: <20190904193059.26202-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 31/69] target/arm: Diagnose base == pc for LDM/STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We have been using store_reg and not store_reg_for_load when writing back a loaded value into the base register. At first glance this is incorrect when base =3D=3D pc, however that case is UNPREDICTABLE. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b623dbcd48..d0fc916ff9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9863,7 +9863,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) =20 list =3D a->list; n =3D ctpop16(list); - if (n < min_n) { + if (n < min_n || a->rn =3D=3D 15) { unallocated_encoding(s); return true; } @@ -9943,7 +9943,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) =20 list =3D a->list; n =3D ctpop16(list); - if (n < min_n) { + if (n < min_n || a->rn =3D=3D 15) { unallocated_encoding(s); return true; } @@ -9983,6 +9983,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) op_addr_block_post(s, a, addr, n); =20 if (loaded_base) { + /* Note that we reject base =3D=3D pc above. */ store_reg(s, a->rn, loaded_var); } =20 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567627265; cv=none; d=zoho.com; s=zohoarc; b=FG1Le2+l+7nWKSsU52OQB4o7nWSfJ8+JGAlzDX86lCLQEeBggawyCBA3ctAuIKbe5oojGfmYXBxLHG8yNJ3iZ5sSmRHvwHwZsL60tM9qE4Wx8ORyczGK5w9gMJiTrTYM2RvtGD1iWsYjbIDYUHQMaydswy5mWoc0dOekba7Odyg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567627265; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ctDcPeje2HRWgMe1VT5hCwuGlGkqYpgPECSd4XI9r2U=; b=QmmdkGWdPzyETRM/a5J0iDZJQ9ehYuARL3O9XPKGhhzr9YiqJdygRDS1wAi6EjrEVO7xBOwwv+tnhv82VqOj4UsKZtSVwTMlu8djtl6AlS4GexaDCPcbCsDpCTPBfpT1Rn2SaEJ5WPJTwEeXgTFzRHiK5NrLECFEvDI7jBMJ7Jc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567627265558668.4282970272632; Wed, 4 Sep 2019 13:01:05 -0700 (PDT) Received: from localhost ([::1]:38112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bSi-0002VU-1X for importer@patchew.org; Wed, 04 Sep 2019 16:01:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40545) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0O-00050O-ON for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0K-0002dF-6K for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:48 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:42288) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0J-0002c1-OO for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:43 -0400 Received: by mail-pg1-x531.google.com with SMTP id p3so11767158pgb.9 for ; Wed, 04 Sep 2019 12:31:43 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ctDcPeje2HRWgMe1VT5hCwuGlGkqYpgPECSd4XI9r2U=; b=hAdwaEa5el4i2o3bqPrNHFBJyTwXkxQEO0dIXUA2klF0fGkyV4ChEQ7m0OwLffNmBc IDMlhu9qmJfKFTNU4VPNDRmKXzPkRYGuTtRV+utGtKhl4SmzoSWinhxstj9C7IOQ/l73 AJNNjDnVf3pkvQ69xueMAzV0VLeVtJSWi6IaLhJjbZ+hkdw16hc/OlOVn4MuQzyUbvBo 7Ha4x3IuXWJXz9+3DYdyaqTe7ql343O6j9IXGGSqOtxaEkRKSVP01sGqJ7Q3SxtEZ121 34bfHPpfXKIyGiFfABTpEpiMrvEHtVo34V4tpJH0qBbogQYYfdST41N0Pln3+g6khotM Oy/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ctDcPeje2HRWgMe1VT5hCwuGlGkqYpgPECSd4XI9r2U=; b=CiOc+19Zbb/csa0vsLe4t/XEm54KG9t7tAw4pINVIOY9RHvQJxtigzXt8hsRemnM7f 7UHOz19VMpbC+zZjKK6toCUplmAszudeGGO/RRwdWg1QrsknyNB9SLTPCQSiLmHM/T/4 oeVHmmRbze0v6oBGCKsvOsAYwvE+gDFEZmsDPV0/BXsOoFCcQfo6V6LR3CL6Gid+uC5a lN1H6/cPh+Ol/lALVTHJT3UqIwGXEtxiBuRBeCHQHc11uwTeAJxlVyim/skMzjr6Y3Pq 25euIFPz5gUlS/V7hatMn7GEQjZcR+IVTGVOj8xNXK+TtV/vBXzVPkGeKgoLN/9OOXgq yXjw== X-Gm-Message-State: APjAAAU/OFJl1L7SACyX8tzos7mbsNE3mXCi0Tw/Z37ygGRe9k7DfWs6 TesoQYB1h0ruBqorHbEQyMz7SddOQJ8= X-Google-Smtp-Source: APXvYqzV7gmRYYUaRUJywbYsDZCtxZGKJp9ZqBwNloI2tNnijXKNG5AkI8NJIwTVQjjROCyLjS21hg== X-Received: by 2002:a63:6f8f:: with SMTP id k137mr36322906pgc.90.1567625502117; Wed, 04 Sep 2019 12:31:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:22 -0700 Message-Id: <20190904193059.26202-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::531 Subject: [Qemu-devel] [PATCH v4 32/69] target/arm: Convert B, BL, BLX (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 133 +++++++++++++++-------------------- target/arm/a32-uncond.decode | 8 +++ target/arm/a32.decode | 8 +++ target/arm/t32.decode | 81 ++++++++++++--------- 4 files changed, 123 insertions(+), 107 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d0fc916ff9..72e4708e61 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7545,6 +7545,14 @@ static int t32_expandimm_imm(DisasContext *s, int x) return imm; } =20 +static int t32_branch24(DisasContext *s, int x) +{ + /* Convert J1:J2 at x[22:21] to I2:I1, which involves I=3DJ^~S. */ + x ^=3D !(x < 0) * (3 << 21); + /* Append the final zero. */ + return x << 1; +} + /* * Include the generated decoders. */ @@ -10030,13 +10038,56 @@ static bool trans_LDM_t32(DisasContext *s, arg_ld= st_block *a) return do_ldm(s, a, 2); } =20 +/* + * Branch, branch with link + */ + +static bool trans_B(DisasContext *s, arg_i *a) +{ + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a) +{ + /* This has cond from encoding, required to be outside IT block. */ + if (a->cond >=3D 0xe) { + return false; + } + if (s->condexec_mask) { + unallocated_encoding(s); + return true; + } + arm_skip_unless(s, a->cond); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_BL(DisasContext *s, arg_i *a) +{ + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + +static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) +{ + /* For A32, ARCH(5) is checked near the start of the uncond block. */ + if (s->thumb && (a->imm & 2)) { + return false; + } + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); + gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); + return true; +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn; + unsigned int cond, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10204,21 +10255,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } gen_rfe(s, tmp, tmp2); return; - } else if ((insn & 0x0e000000) =3D=3D 0x0a000000) { - /* branch link and change to thumb (blx ) */ - int32_t offset; - - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->base.pc_next); - store_reg(s, 14, tmp); - /* Sign-extend the 24-bit offset */ - offset =3D (((int32_t)insn) << 8) >> 8; - val =3D read_pc(s); - /* offset * 4 + bit24 * 2 + (thumb bit) */ - val +=3D (offset << 2) | ((insn >> 23) & 2) | 1; - /* protected by ARCH(5); above, near the start of uncond block= */ - gen_bx_im(s, val); - return; } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10310,23 +10346,10 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) case 0x7: case 0x08: case 0x09: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0xa: case 0xb: - { - int32_t offset; - - /* branch (and link) */ - if (insn & (1 << 24)) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->base.pc_next); - store_reg(s, 14, tmp); - } - offset =3D sextract32(insn << 2, 0, 26); - gen_jmp(s, read_pc(s) + offset); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xc: case 0xd: case 0xe: @@ -10693,32 +10716,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) if (insn & (1 << 15)) { /* Branches, misc control. */ if (insn & 0x5000) { - /* Unconditional branch. */ - /* signextend(hw1[10:0]) -> offset[:12]. */ - offset =3D ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff; - /* hw1[10:0] -> offset[11:1]. */ - offset |=3D (insn & 0x7ff) << 1; - /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22] - offset[24:22] already have the same value because of the - sign extension above. */ - offset ^=3D ((~insn) & (1 << 13)) << 10; - offset ^=3D ((~insn) & (1 << 11)) << 11; - - if (insn & (1 << 14)) { - /* Branch and link. */ - tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); - } - - offset +=3D read_pc(s); - if (insn & (1 << 12)) { - /* b/bl */ - gen_jmp(s, offset); - } else { - /* blx */ - offset &=3D ~(uint32_t)2; - /* thumb2 bx, no need to check */ - gen_bx_im(s, offset); - } + /* Unconditional branch, in decodetree */ + goto illegal_op; } else if (((insn >> 23) & 7) =3D=3D 7) { /* Misc control */ if (insn & (1 << 13)) @@ -10804,24 +10803,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } } } else { - /* Conditional branch. */ - op =3D (insn >> 22) & 0xf; - /* Generate a conditional jump to next instruction. */ - arm_skip_unless(s, op); - - /* offset[11:1] =3D insn[10:0] */ - offset =3D (insn & 0x7ff) << 1; - /* offset[17:12] =3D insn[21:16]. */ - offset |=3D (insn & 0x003f0000) >> 4; - /* offset[31:20] =3D insn[26]. */ - offset |=3D ((int32_t)((insn << 5) & 0x80000000)) >> 11; - /* offset[18] =3D insn[13]. */ - offset |=3D (insn & (1 << 13)) << 5; - /* offset[19] =3D insn[11]. */ - offset |=3D (insn & (1 << 11)) << 8; - - /* jump to the offset */ - gen_jmp(s, read_pc(s) + offset); + /* Conditional branch, in decodetree */ + goto illegal_op; } } else { /* diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 8dee26d3b6..573ac2cf8e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -21,3 +21,11 @@ # All insns that have 0xf in insn[31:28] are decoded here. # All of those that have a COND field in insn[31:28] are in a32.decode # + +&i !extern imm + +# Branch with Link and Exchange + +%imm24h 0:s24 24:1 !function=3Dtimes_2 + +BLX_i 1111 101 . ........................ &i imm=3D%im= m24h diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 1267a689e2..62c6f8562e 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -520,3 +520,11 @@ SMMLSR .... 0111 0101 .... .... .... 1111 ..= .. @rdamn =20 STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block + +# Branch, branch with link + +%imm26 0:s24 !function=3Dtimes_4 +@branch ---- .... ........................ &i imm=3D%im= m26 + +B .... 1010 ........................ @branch +BL .... 1011 ........................ @branch diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f1e2b934f8..ebc92f2c28 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -284,47 +284,55 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 %imm16_16_0 16:4 0:12 +%imm21 26:s1 11:1 13:1 16:6 0:11 !function=3Dtimes_2 +&ci cond imm =20 { + # Group insn[25:23] =3D 111, which is cond=3D111x for the branch below, + # or unconditional, which would be illegal for the branch. { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + # Hints + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- - } - # Note that the v7m insn overlaps both the normal and banked insn. - { - MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ &mrs_bank sysm=3D%mrs_sysm - MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg - MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 - } - { - MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ &msr_bank sysm=3D%msr_sysm - MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg - MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 - } - BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r - { - # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as = for - # every other encoding of SUBS. With v7VE, IMM=3D0 is redefined as ER= ET. - # The distinction between the two only matters for Hyp mode. - ERET 1111 0011 1101 1110 1000 1111 0000 0000 - SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works a= s for + # every other encoding of SUBS. With v7VE, IMM=3D0 is redefined as = ERET. + # The distinction between the two only matters for Hyp mode. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=3D0 s=3D1 rd=3D15 rn=3D14 - } - SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i - HVC 1111 0111 1110 .... 1000 .... .... .... \ + } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=3D%imm16_16_0 - UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + } + B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=3D%i= mm21 } =20 # Load/store (register, immediate, literal) @@ -573,3 +581,12 @@ STM_t32 1110 1000 10.0 .... ................ = @ldstm i=3D1 b=3D0 STM_t32 1110 1001 00.0 .... ................ @ldstm i=3D0= b=3D1 LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 + +# Branches + +%imm24 26:s1 13:1 11:1 16:10 0:11 !function=3Dt32_branch24 +@branch24 ................................ &i imm=3D%im= m24 + +B 1111 0. .......... 10.1 ............ @branch24 +BL 1111 0. .......... 11.1 ............ @branch24 +BLX_i 1111 0. .......... 11.0 ............ @branch24 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567627783; cv=none; d=zoho.com; s=zohoarc; b=WHHcKMm1MU9ereANuhdOAf70zdKu/rRDXuEL2y4kJopDCN37gVEkI3XpYDR6KviKCDbu83Cec66QWSFDUGD6P+xslf4Zyu0iB51yH7tgKU4EZ4TxE5sSQbna/GceC0AQ5OXaIqsIK4bPTlECAiB0cS1KBCq2YxMQwLDJTqv8+vA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567627783; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=jCLx5wbUWyoQFBTJtKxHJZzHzglyCub6PkVD7Xy998w=; b=aJhBt+8Hl4L0lzhSUqRMOBqPQpfRRsFYfC5bJ4DnUQONlZn8we3rTsHyBLXoxkyY2PetF4m96hM/rgDfv1anQ+5O9T+7OtLpqooZU5B12BP9mTqQRfBbRBjRgmX1yXwQmuCdqIxpU6xEiyKOh9fK6Xk/umBrfgOufVL6A+vUJSs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567627783901645.9121232515497; Wed, 4 Sep 2019 13:09:43 -0700 (PDT) Received: from localhost ([::1]:38454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bb0-0003Um-1J for importer@patchew.org; Wed, 04 Sep 2019 16:09:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40536) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0O-0004zw-H4 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0L-0002er-PE for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:48 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:47066) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0L-0002e3-EQ for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:45 -0400 Received: by mail-pg1-x534.google.com with SMTP id m3so11750369pgv.13 for ; Wed, 04 Sep 2019 12:31:45 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::534 Subject: [Qemu-devel] [PATCH v4 33/69] target/arm: Convert SVC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 19 +++++++++++++------ target/arm/a32.decode | 4 ++++ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 72e4708e61..208021181f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10081,6 +10081,18 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i= *a) return true; } =20 +/* + * Supervisor call + */ + +static bool trans_SVC(DisasContext *s, arg_SVC *a) +{ + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm =3D a->imm; + s->base.is_jmp =3D DISAS_SWI; + return true; +} + /* * Legacy decoder. */ @@ -10348,6 +10360,7 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) case 0x09: case 0xa: case 0xb: + case 0xf: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0xc: @@ -10363,12 +10376,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) goto illegal_op; } break; - case 0xf: - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm =3D extract32(insn, 0, 24); - s->base.is_jmp =3D DISAS_SWI; - break; default: illegal_op: unallocated_encoding(s); diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 62c6f8562e..0bd952c069 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -528,3 +528,7 @@ LDM_a32 ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:1= 6 &ldst_block =20 B .... 1010 ........................ @branch BL .... 1011 ........................ @branch + +# Supervisor call + +SVC ---- 1111 imm:24 &i --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567627078; cv=none; d=zoho.com; s=zohoarc; b=hT7KlogKE1b2gsSXj8IeFJyaeqCpFsznDsGnAbz1s3q2na7SIzt0TRxUkq3TQ4Lb0QV7RhwvntW81xWwtmRd6XmnOo/N9b1gm+fe6lMFsxg7XlqJ1Na+oq2FMIX56MZ4km4n304Y987y3qK/Z2LKL20DWbaMoAUtKq2nm0fPmUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567627078; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=YVJNMt9WNTMYk7iugljb14Z8xnu973MKG4jgT87zBAI=; b=anFbXUY1MpT/GhB0A+TUGs9vD2sRnZ3wsiPAk7Jl7Fac1kRL2tP2LBX0rV5h/KEeFpO4RPXC4GlT7YngtfnAldunREQgVDVgH66sTAeQzXvTkzXljcG7VssZzmNK1LT8WJDxdmghE0iqK5jM/65l0iwtvxbaZg/szbXAn3M6ADc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567627078144962.578041315744; Wed, 4 Sep 2019 12:57:58 -0700 (PDT) Received: from localhost ([::1]:38064 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bPg-0008Me-Hw for importer@patchew.org; Wed, 04 Sep 2019 15:57:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40593) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0R-00053p-3s for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0N-0002gN-Jc for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:50 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:34379) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0N-0002fT-24 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:47 -0400 Received: by mail-pf1-x444.google.com with SMTP id r12so1751556pfh.1 for ; Wed, 04 Sep 2019 12:31:46 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YVJNMt9WNTMYk7iugljb14Z8xnu973MKG4jgT87zBAI=; b=zE+5ggMyDItv5RLOwTGxaMpU5R9edQKlLUpI4TmDEP9t8/L/912WND2sA2e/a11WIX ax1xfsCxdV6GOf+MPTVwJBESzA6cYQkdvhXAvbqoZuJ3BrhMQ4vDcI5j7e8zL/Jkz1Uh KlIFvpdD4Ff/+iRItI9uiDDn4Kbup17ScSIYmk/BfdaoMgs4F2Yd42wjNzyqmZyQXum4 GCI1ojgN6An+lwh4Qga3BqWDn5m6Io5kXuQqY8VYcmI5E+elVcV7j6W0EYHPIyfObQK4 KzzvLAto1inJoJf4a4ZfA+C9WNCusXH5ckWYmK9BgRaoATqyX+B9L8Rh9VlK4w1Yh1S3 9THA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YVJNMt9WNTMYk7iugljb14Z8xnu973MKG4jgT87zBAI=; b=qzC9zvYXJ+wFrnK58fp1Mm4s5xZoaqvRULnu+XjvzllTeM+BNyAO7mHz+mLZSPU1po xKnPqU6yH72+hwx4916NNco4kR+TEyxAwQJKNa3hmvKmCM+3h5tc1hd7JJoKFnk5Yq/7 T7DhYC8l0e3wRxl2sZpJn5I1d07rf4TJvGRxa2hovRVHmSj2cshA8UH4JhcFE3GJyU3P TKELybkqZlRh7zVHxVbnIBx1ns3+aAuZqYdGepDfH4h3Ha4TwGYoQHXdw8kaw638tAja Sg2ljVUz6vlZmnPdWFEHbHTRtVTLzTw3ROS9i59vHmQs3cHH7Pgt35JqdXVWTPPav8Pu 43uQ== X-Gm-Message-State: APjAAAVqOIl3gNBfJ5OfG+K73RZ3ZTttTgctal05wInY1pV6k2l6rR2F uCj3cfBbffYPeYCZI0hcLoJk/UyDc3Y= X-Google-Smtp-Source: APXvYqyrKkGMPmbsHqV9gL5gV3h9idCGib7jQuAnRwO6Mi9+JTZl3rqnOAHxuSH9Xe+FQIetHLSkBA== X-Received: by 2002:aa7:8556:: with SMTP id y22mr21006149pfn.252.1567625505594; Wed, 04 Sep 2019 12:31:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:24 -0700 Message-Id: <20190904193059.26202-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 34/69] target/arm: Convert RFE and SRS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Fix SRS decode; reject RFE and SRS for m-profile. v4: Fix checkpatch failure in trans_RFE. --- target/arm/translate.c | 144 +++++++++++++---------------------- target/arm/a32-uncond.decode | 8 ++ target/arm/t32.decode | 12 +++ 3 files changed, 75 insertions(+), 89 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 208021181f..ca4873e514 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10093,16 +10093,65 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) return true; } =20 +/* + * Unconditional system instructions + */ + +static bool trans_RFE(DisasContext *s, arg_RFE *a) +{ + static const int8_t pre_offset[4] =3D { + /* DA */ -4, /* IA */ 0, /* DB */ -8, /* IB */ 4 + }; + static const int8_t post_offset[4] =3D { + /* DA */ -8, /* IA */ 4, /* DB */ -4, /* IB */ 0 + }; + TCGv_i32 addr, t1, t2; + + if (!ENABLE_ARCH_6 || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + unallocated_encoding(s); + return true; + } + + addr =3D load_reg(s, a->rn); + tcg_gen_addi_i32(addr, addr, pre_offset[a->pu]); + + /* Load PC into tmp and CPSR into tmp2. */ + t1 =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, t1, addr, get_mem_index(s)); + tcg_gen_addi_i32(addr, addr, 4); + t2 =3D tcg_temp_new_i32(); + gen_aa32_ld32u(s, t2, addr, get_mem_index(s)); + + if (a->w) { + /* Base writeback. */ + tcg_gen_addi_i32(addr, addr, post_offset[a->pu]); + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + gen_rfe(s, t1, t2); + return true; +} + +static bool trans_SRS(DisasContext *s, arg_SRS *a) +{ + if (!ENABLE_ARCH_6 || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_srs(s, a->mode, a->pu, a->w); + return true; +} + /* * Legacy decoder. */ =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1, i, rn; - TCGv_i32 tmp; - TCGv_i32 tmp2; - TCGv_i32 addr; + unsigned int cond, op1; =20 /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10221,52 +10270,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) default: goto illegal_op; } - } else if ((insn & 0x0e5fffe0) =3D=3D 0x084d0500) { - /* srs */ - ARCH(6); - gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21)); - return; - } else if ((insn & 0x0e50ffe0) =3D=3D 0x08100a00) { - /* rfe */ - int32_t offset; - if (IS_USER(s)) - goto illegal_op; - ARCH(6); - rn =3D (insn >> 16) & 0xf; - addr =3D load_reg(s, rn); - i =3D (insn >> 23) & 3; - switch (i) { - case 0: offset =3D -4; break; /* DA */ - case 1: offset =3D 0; break; /* IA */ - case 2: offset =3D -8; break; /* DB */ - case 3: offset =3D 4; break; /* IB */ - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - /* Load PC into tmp and CPSR into tmp2. */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - switch (i) { - case 0: offset =3D -8; break; - case 1: offset =3D 4; break; - case 2: offset =3D -4; break; - case 3: offset =3D 0; break; - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - return; } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10429,7 +10432,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; - TCGv_i32 tmp2; TCGv_i32 addr; int op; =20 @@ -10573,44 +10575,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) goto illegal_op; } } else { - /* Load/store multiple, RFE, SRS. */ - if (((insn >> 23) & 1) =3D=3D ((insn >> 24) & 1)) { - /* RFE, SRS: not available in user mode or on M profile */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (insn & (1 << 20)) { - /* rfe */ - addr =3D load_reg(s, rn); - if ((insn & (1 << 24)) =3D=3D 0) - tcg_gen_addi_i32(addr, addr, -8); - /* Load PC into tmp and CPSR into tmp2. */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, 4); - } else { - tcg_gen_addi_i32(addr, addr, -4); - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - } else { - /* srs */ - gen_srs(s, (insn & 0x1f), (insn & (1 << 24)) ? 1 : 2, - insn & (1 << 21)); - } - } else { - /* Load/store multiple, in decodetree */ - goto illegal_op; - } + /* Load/store multiple, RFE, SRS, in decodetree */ + goto illegal_op; } break; case 5: diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 573ac2cf8e..64548a93e2 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -29,3 +29,11 @@ %imm24h 0:s24 24:1 !function=3Dtimes_2 =20 BLX_i 1111 101 . ........................ &i imm=3D%im= m24h + +# System Instructions + +&rfe rn w pu +&srs mode w pu + +RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe +SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ebc92f2c28..c8a8aeceee 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -582,6 +582,18 @@ STM_t32 1110 1001 00.0 .... ................ = @ldstm i=3D0 b=3D1 LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 =20 +&rfe !extern rn w pu +@rfe .... .... .. w:1 . rn:4 ................ &rfe + +RFE 1110 1000 00.1 .... 1100000000000000 @rfe pu=3D2 +RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=3D1 + +&srs !extern mode w pu +@srs .... .... .. w:1 . .... ........... mode:5 &srs + +SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=3D2 +SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=3D1 + # Branches =20 %imm24 26:s1 13:1 11:1 16:10 0:11 !function=3Dt32_branch24 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M4Erk2+6lG2j0nHNnlb8vKxLu6BsAo4xgf3Pb8Z6zRA=; b=GYNMcUZRLtjVXYbKNahv9TJRKOxR3l6UVXD+vWWBYBrbpZTY4Zdy2dgZN7/nsi9J8S DCQDc62T14yl0ZPdz9kNZVSnmd8BMgDsAvgR7x+aL6pjmTCT7O1aSuzUsBApn12F4Qgb H0AYl7Wy9Ptn9iCmWP18l4oY5sJYbXgnvOiJaRyN8vGdmYx7LtIsm4oT1BMEfhdNo3yV E3vj/eWlHhGodESkiPfVDio1qQRF9pmLjIxeb/fSnqJFl3/ud5Ffrd0MdEUCwTn1LAr2 Vnzbzy26CqNtyfBJOw553cdOylsm6YgDGmq3jEYWn38jD/moYsx43vfc6YVCYV7DlZ+M U82A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M4Erk2+6lG2j0nHNnlb8vKxLu6BsAo4xgf3Pb8Z6zRA=; b=G7aL7nD5kdx7Mq/PcAj12chGYiH4jr4CvEOK/yhzenrqcmfT9Usrb1tqeeAMjoe+CN /kwFBAq/5mkN6Y3VDhvP0CjJM0hFgNiyCO9An0hcZBz/DJfcm7lYvmj7FL50BwwoMYaW ofyINAX+bbmOYSt5Geg4ot8BOpCUK8eij+gtNGmUw4HOoEvsGXqWaX0YmAON0RlEhsdD J182pRc2CxpqROx+oiwYPE/ed3TyQwERXNR1X0SqmbGpdGHnbmcE3nlXlOo1UH9EXgsp DDbE6scbaUIP21FlheZJ0LovmW6CcsaxNcj6PKTBrTXQeo39puBUviddMi0bD5+DVDin J/rQ== X-Gm-Message-State: APjAAAUeU6/62R5t+CMYXM6ibZpSgpkp0+MdNB21S3vDpazC3o5mYZP7 hZD2NznHoEwwOGve9E2BRpsTu+kSmqQ= X-Google-Smtp-Source: APXvYqw9kCH1+3cRIGWDunQC6vPbFxLf5Fprgh2OwIBTUgCwV283GFZrZofO8TAtpFlOZJHmhlyxRQ== X-Received: by 2002:aa7:998f:: with SMTP id k15mr34497360pfh.203.1567625506689; Wed, 04 Sep 2019 12:31:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:25 -0700 Message-Id: <20190904193059.26202-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42e Subject: [Qemu-devel] [PATCH v4 35/69] target/arm: Convert Clear-Exclusive, Barriers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- v3: Check m-profile for all; fix missing isa check for ISB; fix thumb isa check for CLREX and DSB. --- target/arm/translate.c | 127 ++++++++++++++++------------------- target/arm/a32-uncond.decode | 10 +++ target/arm/t32.decode | 10 +++ 3 files changed, 78 insertions(+), 69 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ca4873e514..364b51c2a6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10145,6 +10145,63 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } =20 +/* + * Clear-Exclusive, Barriers + */ + +static bool trans_CLREX(DisasContext *s, arg_CLREX *a) +{ + if (s->thumb + ? !ENABLE_ARCH_7 && !arm_dc_feature(s, ARM_FEATURE_M) + : !ENABLE_ARCH_6K) { + return false; + } + gen_clrex(s); + return true; +} + +static bool trans_DSB(DisasContext *s, arg_DSB *a) +{ + if (!ENABLE_ARCH_7 && !arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + return true; +} + +static bool trans_DMB(DisasContext *s, arg_DMB *a) +{ + return trans_DSB(s, NULL); +} + +static bool trans_ISB(DisasContext *s, arg_ISB *a) +{ + if (!ENABLE_ARCH_7 && !arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + /* + * We need to break the TB after this insn to execute + * self-modifying code correctly and also to take + * any pending interrupts immediately. + */ + gen_goto_tb(s, 0, s->base.pc_next); + return true; +} + +static bool trans_SB(DisasContext *s, arg_SB *a) +{ + if (!dc_isar_feature(aa32_sb, s)) { + return false; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->base.pc_next); + return true; +} + /* * Legacy decoder. */ @@ -10238,38 +10295,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) s->base.is_jmp =3D DISAS_UPDATE; } return; - } else if ((insn & 0x0fffff00) =3D=3D 0x057ff000) { - switch ((insn >> 4) & 0xf) { - case 1: /* clrex */ - ARCH(6K); - gen_clrex(s); - return; - case 4: /* dsb */ - case 5: /* dmb */ - ARCH(7); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - return; - case 6: /* isb */ - /* We need to break the TB after this insn to execute - * self-modifying code correctly and also to take - * any pending interrupts immediately. - */ - gen_goto_tb(s, 0, s->base.pc_next); - return; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); - return; - default: - goto illegal_op; - } } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10730,43 +10755,7 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) gen_set_psr_im(s, offset, 0, imm); } break; - case 3: /* Special control operations. */ - if (!arm_dc_feature(s, ARM_FEATURE_V7) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - op =3D (insn >> 4) & 0xf; - switch (op) { - case 2: /* clrex */ - gen_clrex(s); - break; - case 4: /* dsb */ - case 5: /* dmb */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - break; - case 6: /* isb */ - /* We need to break the TB after this insn - * to execute self-modifying code correctly - * and also to take any pending interrupts - * immediately. - */ - gen_goto_tb(s, 0, s->base.pc_next); - break; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, = s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); - break; - default: - goto illegal_op; - } - break; + case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; case 5: /* Exception return. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 64548a93e2..c7e9df8030 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -22,6 +22,7 @@ # All of those that have a COND field in insn[31:28] are in a32.decode # =20 +&empty !extern &i !extern imm =20 # Branch with Link and Exchange @@ -37,3 +38,12 @@ BLX_i 1111 101 . ........................ = &i imm=3D%imm24h =20 RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs + +# Clear-Exclusive, Barriers + +# QEMU does not require the option field for the barriers. +CLREX 1111 0101 0111 1111 1111 0000 0001 1111 +DSB 1111 0101 0111 1111 1111 0000 0100 ---- +DMB 1111 0101 0111 1111 1111 0000 0101 ---- +ISB 1111 0101 0111 1111 1111 0000 0110 ---- +SB 1111 0101 0111 1111 1111 0000 0111 0000 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c8a8aeceee..63bca82575 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -305,6 +305,16 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm # of the space is "reserved hint, behaves as nop". NOP 1111 0011 1010 1111 1000 0000 ---- ---- } + + # Miscellaneous control + { + CLREX 1111 0011 1011 1111 1000 1111 0010 1111 + DSB 1111 0011 1011 1111 1000 1111 0100 ---- + DMB 1111 0011 1011 1111 1000 1111 0101 ---- + ISB 1111 0011 1011 1111 1000 1111 0110 ---- + SB 1111 0011 1011 1111 1000 1111 0111 0000 + } + # Note that the v7m insn overlaps both the normal and banked insn. { MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567627594; cv=none; d=zoho.com; s=zohoarc; b=eZbIXjFQbFR0AI7PHkJoxP6aosa0De9les9Ehc7sAbcB4xaMX7Dz+ReUVgGuBz5gKr4HvwZJ5ZM5aXy0AxcVSrntG+m6pcWan0sZ4yLJQ2LOx8I9QwiedP7XroY1uczeqh37XNah4Y+Ujd6MumFJ7qlyUqUsVQea2fOx0WbOZMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567627594; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=mFp920jQZpixU7k16+FPmF8mjjZjYKv6xPjZ8lwU3rc=; b=PoT0TvcRVZocO3YgpRyrPYy0w/Y/viAl13zQu0xB9HTgzVuEDObGRGY2yQOCAZdlWIIO1R23A+MZ87jAa30xaw4m5c07ssz58KABrD6XxqqwRtQ9HrJ/zYV4GwULFBtd8uA/7YvNU6x+wy4bmT1jamnH7PbqHr2CAEsBxHUqhVk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567627594918239.3256532577724; Wed, 4 Sep 2019 13:06:34 -0700 (PDT) Received: from localhost ([::1]:38366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bY0-0008LS-Um for importer@patchew.org; Wed, 04 Sep 2019 16:06:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40658) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0T-00057A-Em for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0P-0002is-S4 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:53 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:33368) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0P-0002ht-Fi for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:49 -0400 Received: by mail-pf1-x444.google.com with SMTP id q10so8854499pfl.0 for ; Wed, 04 Sep 2019 12:31:49 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 36/69] target/arm: Convert CPS (privileged) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Reject for m-profile; add TODO for unpredictable arguments. Sort the T32 decode adjacent to the hint space. --- target/arm/translate.c | 91 ++++++++++++++++-------------------- target/arm/a32-uncond.decode | 3 ++ target/arm/t32.decode | 5 ++ 3 files changed, 48 insertions(+), 51 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 364b51c2a6..664ea281f8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10145,6 +10145,44 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } =20 +static bool trans_CPS(DisasContext *s, arg_CPS *a) +{ + uint32_t mask, val; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + /* TODO: There are quite a lot of UNPREDICTABLE argument combinations.= */ + + mask =3D val =3D 0; + if (a->imod & 2) { + if (a->A) { + mask |=3D CPSR_A; + } + if (a->I) { + mask |=3D CPSR_I; + } + if (a->F) { + mask |=3D CPSR_F; + } + if (a->imod & 1) { + val |=3D mask; + } + } + if (a->M) { + mask |=3D CPSR_M; + val |=3D a->mode; + } + if (mask) { + gen_set_psr_im(s, mask, 0, val); + } + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10321,31 +10359,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) ARCH(5TE); } else if ((insn & 0x0f000010) =3D=3D 0x0e000010) { /* Additional coprocessor register transfer. */ - } else if ((insn & 0x0ff10020) =3D=3D 0x01000000) { - uint32_t mask; - uint32_t val; - /* cps (privileged) */ - if (IS_USER(s)) - return; - mask =3D val =3D 0; - if (insn & (1 << 19)) { - if (insn & (1 << 8)) - mask |=3D CPSR_A; - if (insn & (1 << 7)) - mask |=3D CPSR_I; - if (insn & (1 << 6)) - mask |=3D CPSR_F; - if (insn & (1 << 18)) - val |=3D mask; - } - if (insn & (1 << 17)) { - mask |=3D CPSR_M; - val |=3D (insn & 0x1f); - } - if (mask) { - gen_set_psr_im(s, mask, 0, val); - } - return; } goto illegal_op; } @@ -10454,7 +10467,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 addr; @@ -10730,31 +10742,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) case 0: /* msr cpsr, in decodetree */ case 1: /* msr spsr, in decodetree */ goto illegal_op; - case 2: /* cps, nop-hint. */ - /* nop hints in decodetree */ - /* Implemented as NOP in user mode. */ - if (IS_USER(s)) - break; - offset =3D 0; - imm =3D 0; - if (insn & (1 << 10)) { - if (insn & (1 << 7)) - offset |=3D CPSR_A; - if (insn & (1 << 6)) - offset |=3D CPSR_I; - if (insn & (1 << 5)) - offset |=3D CPSR_F; - if (insn & (1 << 9)) - imm =3D CPSR_A | CPSR_I | CPSR_F; - } - if (insn & (1 << 8)) { - offset |=3D 0x1f; - imm |=3D (insn & 0x1f); - } - if (offset) { - gen_set_psr_im(s, offset, 0, imm); - } - break; + case 2: /* cps, nop-hint, in decodetree */ + goto illegal_op; case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ goto illegal_op; diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index c7e9df8030..de611e8aff 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -35,9 +35,12 @@ BLX_i 1111 101 . ........................ = &i imm=3D%imm24h =20 &rfe rn w pu &srs mode w pu +&cps mode imod M A I F =20 RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs +CPS 1111 0001 0000 imod:2 M:1 0 0000 000 A:1 I:1 F:1 0 mode:5= \ + &cps =20 # Clear-Exclusive, Barriers =20 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 63bca82575..11a9a2ef58 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -44,6 +44,7 @@ &bfi !extern rd rn lsb msb &sat !extern rd rn satimm imm sh &pkh !extern rd rn rm imm tb +&cps !extern mode imod M A I F =20 # Data-processing (register) =20 @@ -306,6 +307,10 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm NOP 1111 0011 1010 1111 1000 0000 ---- ---- } =20 + # If imod =3D=3D '00' && M =3D=3D '0' then SEE "Hint instructions", ab= ove. + CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \ + &cps + # Miscellaneous control { CLREX 1111 0011 1011 1111 1000 1111 0010 1111 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 37/69] target/arm: Convert SETEND X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 22 +++++++++++++--------- target/arm/a32-uncond.decode | 4 ++++ 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 664ea281f8..a599da96e1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10240,6 +10240,18 @@ static bool trans_SB(DisasContext *s, arg_SB *a) return true; } =20 +static bool trans_SETEND(DisasContext *s, arg_SETEND *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + if (a->E !=3D (s->be_data =3D=3D MO_BE)) { + gen_helper_setend(cpu_env); + s->base.is_jmp =3D DISAS_UPDATE; + } + return true; +} + /* * Legacy decoder. */ @@ -10325,15 +10337,7 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) return; /* v7MP: Unallocated memory hint: must NOP */ } =20 - if ((insn & 0x0ffffdff) =3D=3D 0x01010000) { - ARCH(6); - /* setend */ - if (((insn >> 9) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp =3D DISAS_UPDATE; - } - return; - } else if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { + if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ if (extract32(s->c15_cpar, 1, 1)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index de611e8aff..32253b4f9a 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -24,6 +24,7 @@ =20 &empty !extern &i !extern imm +&setend E =20 # Branch with Link and Exchange =20 @@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ---- DMB 1111 0101 0111 1111 1111 0000 0101 ---- ISB 1111 0101 0111 1111 1111 0000 0110 ---- SB 1111 0101 0111 1111 1111 0000 0111 0000 + +# Set Endianness +SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 38/69] target/arm: Convert PLI, PLD, PLDW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 37 +++++++++++++++++++----------------- target/arm/a32-uncond.decode | 10 ++++++++++ 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a599da96e1..3f02532d12 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10252,6 +10252,26 @@ static bool trans_SETEND(DisasContext *s, arg_SETE= ND *a) return true; } =20 +/* + * Preload instructions + * All are nops, contingent on the appropriate arch level. + */ + +static bool trans_PLD(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_5TE; +} + +static bool trans_PLDW(DisasContext *s, arg_PLD *a) +{ + return arm_dc_feature(s, ARM_FEATURE_V7MP); +} + +static bool trans_PLI(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_7; +} + /* * Legacy decoder. */ @@ -10312,23 +10332,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } return; } - if (((insn & 0x0f30f000) =3D=3D 0x0510f000) || - ((insn & 0x0f30f010) =3D=3D 0x0710f000)) { - if ((insn & (1 << 22)) =3D=3D 0) { - /* PLDW; v7MP */ - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - } - /* Otherwise PLD; v5TE+ */ - ARCH(5TE); - return; - } - if (((insn & 0x0f70f000) =3D=3D 0x0450f000) || - ((insn & 0x0f70f010) =3D=3D 0x0650f000)) { - ARCH(7); - return; /* PLI; V7 */ - } if (((insn & 0x0f700000) =3D=3D 0x04100000) || ((insn & 0x0f700010) =3D=3D 0x06100000)) { if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 32253b4f9a..ddc5edfa5e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -54,3 +54,13 @@ SB 1111 0101 0111 1111 1111 0000 0111 0000 =20 # Set Endianness SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend + +# Preload instructions + +PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5= te +PLDW 1111 0101 -001 ---- 1111 ---- ---- ---- # (imm, lit) 7= mp +PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 + +PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5= te +PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7= mp +PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v4 39/69] target/arm: Convert Unallocated memory hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 -------- target/arm/a32-uncond.decode | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3f02532d12..7023ee78f1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10332,14 +10332,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } return; } - if (((insn & 0x0f700000) =3D=3D 0x04100000) || - ((insn & 0x0f700010) =3D=3D 0x06100000)) { - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - return; /* v7MP: Unallocated memory hint: must NOP */ - } - if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index ddc5edfa5e..60ccfc598d 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -64,3 +64,11 @@ PLI 1111 0100 -101 ---- 1111 ---- ---- ----= # (imm, lit) 7 PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5= te PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7= mp PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 + +# Unallocated memory hints +# +# Since these are v7MP nops, and PLDW is v7MP and implemented as nop, +# (ab)use the PLDW helper. + +PLDW 1111 0100 -001 ---- ---- ---- ---- ---- +PLDW 1111 0110 -001 ---- ---- ---- ---0 ---- --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567627920; cv=none; d=zoho.com; s=zohoarc; b=B61p6HlAwkgZUW0ggKbxg3+qSzP1qnSo7um/IXo1/HWXQ3ClLQ8obRr7XYYgx8493cce9WFZJXkBkJSDfgVYfKWdpr7OWAqiwIOWsvwk2J+wNhUzuJtfjWX6OC/EWwAxHc2lDXsclnehleOiEkXX3FO+AIIHd2Fv84zN45Jnvgc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567627920; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=fNVbTJv60xmJj9T6kktIzTW/0WXFeS41CSEU1hxli/Q=; b=R/+OqKMyGM5ntYzHZ8EzsMoN/ZRnX3nOgD4e44tTiPqLW0qPsb2K/h0qWgPCXj/RTrHaOMAtQB2zUrn8mRMVePW47tXbUV96uTeyjNKOQTKCYRYldy8GOZWJVckBvS+mRmjo14TYgQiohHiUrVeapJ0l4Drlig7BdEykxWHWRm4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15676279208091020.4751617307379; Wed, 4 Sep 2019 13:12:00 -0700 (PDT) Received: from localhost ([::1]:38500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bdH-00067A-D1 for importer@patchew.org; Wed, 04 Sep 2019 16:11:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40804) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0X-0005Cz-ID for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0U-0002nz-FD for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:57 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:36488) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0U-0002mt-5c for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:54 -0400 Received: by mail-pf1-x42e.google.com with SMTP id y22so8278107pfr.3 for ; Wed, 04 Sep 2019 12:31:53 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fNVbTJv60xmJj9T6kktIzTW/0WXFeS41CSEU1hxli/Q=; b=R0l99mDmG8Bhz7FJaVV83gZVzSWNzXbKZ2JcXFi35aYnjpBekNK8r+sH1vHvnXzdHv zEt4oIRXbQMNWQwaCIS2Uyn+hvvIdRHtznBz7S12BcdyqwqK00jFm1HpWYoXwsFSE9Q3 JYN9DM3JxD3xLfp1tel9AmIPN05x+fzrWblj7afz6aqPGuy1+tlRgL5jcKm17iurJyOZ +9MZ0RAdXl4r+1Qx+6J6nPPiHQEzYt3EC+BDPUFRNs15p1Gt0u6Z4O+vdRWSDvvccCI4 j/cocG/75N/5SbuX4QVT5it9/jlUNul8B3xJKMugOgs8eCAQFLTushhSvOoj08iVAWgx ioPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fNVbTJv60xmJj9T6kktIzTW/0WXFeS41CSEU1hxli/Q=; b=jy9W55+zZNvd+HFSvlBdxDBDuu9z3fIBPorthj+CQeeRxKk0hBPBa2d5mq9w6NTR44 B5zLvokY2WSiYblZCJp2k4bpomKayhcMfZ/SylswNgWlYQpjtlg7/2auIeJMe+bseIhz eEpFc4brr6+B/ejJtdyG8DReMUoUoW5WnpEy0Jd/Fqsf8/MxitqrSmqRqBaQON55sW4k rlwDxBeJ5RLB8qjqmo5WPZW6PyoqxwRSf1I+SOmJpHuc0auUhxgUSA43/Wrba77MkPCI fDwTT3hXDpI4qqcbhfTxelh7wg6WBTJs5h55g20DOH63sfBE6PFAXmOcaEZENztF72PN OhGg== X-Gm-Message-State: APjAAAW6NO+Sc8uWzYI9Y8NIbgCypaiVqLKS2l6EFoVXRtUWpIwiS/0A Rau4C4S4c1KSkSyL0bfWp3IVpOwnZS4= X-Google-Smtp-Source: APXvYqydGdInQz3GcqSi3R7G42d78YIYmjPmpSqdirJ4E4LYpfu4oW9s3WTciwQJgzmp5NaL1YcK3A== X-Received: by 2002:a17:90a:cf0b:: with SMTP id h11mr6642189pju.95.1567625512623; Wed, 04 Sep 2019 12:31:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:30 -0700 Message-Id: <20190904193059.26202-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42e Subject: [Qemu-devel] [PATCH v4 40/69] target/arm: Convert Table Branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 57 +++++++++++++++++++++++++----------------- target/arm/t32.decode | 8 +++++- 2 files changed, 41 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7023ee78f1..96149eabf4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10081,6 +10081,37 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i= *a) return true; } =20 +static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) +{ + TCGv_i32 addr, tmp; + + tmp =3D load_reg(s, a->rm); + if (half) { + tcg_gen_add_i32(tmp, tmp, tmp); + } + addr =3D load_reg(s, a->rn); + tcg_gen_add_i32(addr, addr, tmp); + + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + half ? MO_UW | s->be_data : MO_UB); + tcg_temp_free_i32(addr); + + tcg_gen_add_i32(tmp, tmp, tmp); + tcg_gen_addi_i32(tmp, tmp, read_pc(s)); + store_reg(s, 15, tmp); + return true; +} + +static bool trans_TBB(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, false); +} + +static bool trans_TBH(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, true); +} + /* * Supervisor call */ @@ -10466,9 +10497,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, rs; - TCGv_i32 tmp; - TCGv_i32 addr; + uint32_t rd, rn, rs; int op; =20 /* @@ -10514,7 +10543,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) rn =3D (insn >> 16) & 0xf; rs =3D (insn >> 12) & 0xf; rd =3D (insn >> 8) & 0xf; - rm =3D insn & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ @@ -10587,25 +10615,8 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) /* Load/store exclusive, in decodetree */ goto illegal_op; } else if ((insn & (7 << 5)) =3D=3D 0) { - /* Table Branch. */ - addr =3D load_reg(s, rn); - tmp =3D load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - if (insn & (1 << 4)) { - /* tbh */ - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - } else { /* tbb */ - tcg_temp_free_i32(tmp); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - } - tcg_temp_free_i32(addr); - tcg_gen_shli_i32(tmp, tmp, 1); - tcg_gen_addi_i32(tmp, tmp, read_pc(s)); - store_reg(s, 15, tmp); + /* Table Branch, in decodetree */ + goto illegal_op; } else { /* Load/store exclusive, load-acq/store-rel, in decodetree= */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 11a9a2ef58..d05673ff3e 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -489,7 +489,7 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........= @ldstd_ri8 w=3D0 p=3D1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 =20 -# Load/Store Exclusive and Load-Acquire/Store-Release +# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch =20 @strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ &strex rt2=3D15 imm=3D%imm8x4 @@ -533,6 +533,12 @@ LDA 1110 1000 1101 .... .... 1111 1010 11= 11 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 =20 +&tbranch rn rm +@tbranch .... .... .... rn:4 .... .... .... rm:4 &tbranch + +TBB 1110 1000 1101 .... 1111 0000 0000 .... @tbranch +TBH 1110 1000 1101 .... 1111 0000 0001 .... @tbranch + # Parallel addition and subtraction =20 SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567628286; cv=none; d=zoho.com; s=zohoarc; b=YQF1kumm+RBmfZv2hWPivfpI23oX9MnmFvSnCNNpi14s1hwLGFrWGc4S3lpHMVPAEw4WpD79ycOBNqjLd2z1xPDXqiE4c1H5JP43kd+NMsUk7BiPTL7m9HknBYF0bvRE2wW1sjEtG1NpbtX9wjbSNw1gmF9S2Akxf4oehEIXdEc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567628286; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=bRqYq2TLJ+WIjlJfH/2hIAtxOVh3ChiZfI3nAvVSmQE=; b=TuTJAHJEphVHffVemb138GuTA94tOBeWhhWypCIsUd+DK9ZTSVXtv051Ztj2CoZyDDSK7xn+zfwpFNYcj9BG2lCN2FuUXAd3zUKG9ApZHgbwWHVfBeIuERJoMo7UgHuf/wR7fCy//CN5ijhO05Hzf6P/PsV0aVEthpoS/+ndlx0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567628286303915.1722051674658; Wed, 4 Sep 2019 13:18:06 -0700 (PDT) Received: from localhost ([::1]:38586 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bjA-0002zz-Js for importer@patchew.org; Wed, 04 Sep 2019 16:18:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40820) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0Y-0005De-38 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0V-0002p0-Fu for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:57 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:36838) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0V-0002oD-6x for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:55 -0400 Received: by mail-pf1-x444.google.com with SMTP id y22so8278172pfr.3 for ; Wed, 04 Sep 2019 12:31:55 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bRqYq2TLJ+WIjlJfH/2hIAtxOVh3ChiZfI3nAvVSmQE=; b=iRb1/wXKxZU+WH6cNoOPPE5ajNFKlx1uJ2+hVuPfjqFHjBEk0jz1T+w9rM4cyydPB5 EgEVrmaGhx078DRYd78x9KDvO53i2785IeiT4DzWbP6t8gekmX2VPMGOY2/uK54d+WDg J7fUy/pmqBIlYfcuY3MH1HMHKSXYM9T1oHezV8zmvNZ/DCbBf+2DVe7zUYrjjlaNQuHG aooOtLGhp+zPkr4f3LsQVjKO2BOZlZ5K93OWB/seJNuKHBai4eZMTMZjRNIIwpegdwDI U/hNvDa+VSo1a2OtZIebBWTAfjZp9sq18l1iXQe03OFMyyjBqIpJFnYDVdPp8yO3nAcX jEKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bRqYq2TLJ+WIjlJfH/2hIAtxOVh3ChiZfI3nAvVSmQE=; b=IXKT9TsvWbrE3SNIXrEJY3HBFTv++5aTblOhm+2tHAj9UwVg8P8YC1qA0r9jj8xFr2 VzWJa4piM5FKRmDQ1QVTHa1cutjjb5XQcwFSgyBnkRf0LCZA9QoxO77snm5Uxmc7cLio /a2KbLW9j62US67avM+PmNkog2AwJyivQtM5cWjhbFvj82oHdUH8l6CI2Zvylq1eeDbi 8C8WAZ7La3vHGbK00lA4/SAGhZaHTF+OD6AzzxZ9nlyQ9h6Y+VoRbbAbOVL6qSY/MtMq 4PouwrPfipxiguBpPJpptXt/nTF0+9FPsf6wCIW63awhRw8ALjEN68gEsq0gtBFWORgb JUVQ== X-Gm-Message-State: APjAAAXPdW7NSCjwIwlAWMmwUe6vf74u5VwkPgVpNhxGd/Fc5+jVFfE5 D18opc3P76V86ZQ8Hd4TCB+Gw8RH/ng= X-Google-Smtp-Source: APXvYqwdwCm/L5Pm9JDrtMYyHek472nzxNwi3rii63fpU0BfyfXqrf2U+9S773i2khK72IyEBc06jw== X-Received: by 2002:a63:1b66:: with SMTP id b38mr36618239pgm.54.1567625513742; Wed, 04 Sep 2019 12:31:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:31 -0700 Message-Id: <20190904193059.26202-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 41/69] target/arm: Convert SG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++++++++++++++++++++++++------------------ target/arm/t32.decode | 5 ++++- 2 files changed, 33 insertions(+), 23 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 96149eabf4..af7eddca48 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8467,6 +8467,34 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } =20 +static bool trans_SG(DisasContext *s, arg_SG *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + /* + * SG (v8M only) + * The bulk of the behaviour for this instruction is implemented + * in v7m_handle_execute_nsc(), which deals with the insn when + * it is executed by a CPU in non-secure state from memory + * which is Secure & NonSecure-Callable. + * Here we only need to handle the remaining cases: + * * in NS memory (including the "security extension not + * implemented" case) : NOP + * * in S memory but CPU already secure (clear IT bits) + * We know that the attribute for the memory this insn is + * in must match the current CPU state, because otherwise + * get_phys_addr_pmsav8 would have generated an exception. + */ + if (s->v8m_secure) { + /* Like the IT insn, we don't need to generate any code */ + s->condexec_cond =3D 0; + s->condexec_mask =3D 0; + } + return true; +} + /* * Load/store register index */ @@ -10553,28 +10581,7 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) * - load/store doubleword, load/store exclusive, ldacq/strel, * table branch, TT. */ - if (insn =3D=3D 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M)= && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1001_0111_1111_1110_1001_0111_111 - * - SG (v8M only) - * The bulk of the behaviour for this instruction is imple= mented - * in v7m_handle_execute_nsc(), which deals with the insn = when - * it is executed by a CPU in non-secure state from memory - * which is Secure & NonSecure-Callable. - * Here we only need to handle the remaining cases: - * * in NS memory (including the "security extension not - * implemented" case) : NOP - * * in S memory but CPU already secure (clear IT bits) - * We know that the attribute for the memory this insn is - * in must match the current CPU state, because otherwise - * get_phys_addr_pmsav8 would have generated an exception. - */ - if (s->v8m_secure) { - /* Like the IT insn, we don't need to generate any cod= e */ - s->condexec_cond =3D 0; - s->condexec_mask =3D 0; - } - } else if (insn & 0x01200000) { + if (insn & 0x01200000) { /* load/store dual, in decodetree */ goto illegal_op; } else if ((insn & (1 << 23)) =3D=3D 0) { diff --git a/target/arm/t32.decode b/target/arm/t32.decode index d05673ff3e..c956ddb254 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -487,7 +487,10 @@ STRD_ri_t32 1110 1001 .100 .... .... .... .......= . @ldstd_ri8 w=3D0 p=3D1 LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=3D= 0 p=3D1 =20 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 -LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +{ + SG 1110 1001 0111 1111 1110 1001 01111111 + LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=3D= 1 p=3D1 +} =20 # Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch =20 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1o+uWqBuu4o1NL9VW7TCfscdl6K+gK/4Ohpfut2UuGg=; b=fNdd8DiuTLcYPMGPz+kZGEZm4gOdHJ/qr/K3hJmq8zB+3wPlF8ErMIikd1RNliqWM/ 6IzjIlqCFvu2Y+zQkQdAjABeSb79T47F206LwD7yO9s6qn5mYuzUMjJ2PpxGjfuyQN/L mXgDlbbRg4PUSL5DNfnSSHK7PMVvkQjPwe3q5vZALDJKkmwlCzs61njv5oZQAwkL7jU0 LIYdvIBNRXjOeb6Wn1lcn9yc2cqY5EPAYTHtvG79V2IXksLR5nBUFdY86lpBlQem6JZ7 cEOOeEvItIPqJ3UB2EsOttSCI32ObEDyqU0U4kwzd7S2Y8F+0nxaMRL5+h9/7cnPW/vk aS6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1o+uWqBuu4o1NL9VW7TCfscdl6K+gK/4Ohpfut2UuGg=; b=JRdtDLG5/wUipQjJL0u+VO+phpbiW75sAGo2P4i53nyBn56hHBlwMsJlMDoAnhO5pB ZSKwsJGpItcCgxz4L3WaCJTbbTTYdvzBgYy+gBqCkTJ41MQwJmPpjIu+BBL3EUnaI/TU f0Lr1jVt3zoosXATUYthqPLmgD4dQwr4/T7vNoXFdLqHh5bxyWkt4suDhFserIJ00L8A 4aQEDy3gS45kaOE3A/Y29qUu4I1CLLd9GewtywWMCW2x3gAJGYcudz35gnlZagJ99N5l KjUKsDm+O1YtBMmKGAKSBCNWIzGLt+9OEwbDA9AmDoBkXwvd4vPBFDfyihJ1ySOs3vt1 2wMg== X-Gm-Message-State: APjAAAWNoNYuz0rLPj+xjNeTKHlaxQegZYuQ6EcYjlbcOMedBFUYWH38 izAisoCYgCn8yWv3Jt731YMURQYbjug= X-Google-Smtp-Source: APXvYqzkR1nB+o0n7VkzJ53grmloFg4oT7AdQWlmAoo3XojS37DC2XiOiPSyicwBzLCZlvd58cdL3g== X-Received: by 2002:a63:9e54:: with SMTP id r20mr37649749pgo.64.1567625514948; Wed, 04 Sep 2019 12:31:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:32 -0700 Message-Id: <20190904193059.26202-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v4 42/69] target/arm: Convert TT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Use unallocated_encoding. --- target/arm/translate.c | 90 ++++++++++++++---------------------------- target/arm/t32.decode | 5 ++- 2 files changed, 34 insertions(+), 61 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index af7eddca48..46c27ea6a8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8495,6 +8495,33 @@ static bool trans_SG(DisasContext *s, arg_SG *a) return true; } =20 +static bool trans_TT(DisasContext *s, arg_TT *a) +{ + TCGv_i32 addr, tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + if (a->rd =3D=3D 13 || a->rd =3D=3D 15 || a->rn =3D=3D 15) { + /* We UNDEF for these UNPREDICTABLE cases */ + unallocated_encoding(s); + return true; + } + if (a->A && !s->v8m_secure) { + /* This case is UNDEFINED. */ + unallocated_encoding(s); + return true; + } + + addr =3D load_reg(s, a->rn); + tmp =3D tcg_const_i32((a->A << 1) | a->T); + gen_helper_v7m_tt(tmp, cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + store_reg(s, a->rd, tmp); + return true; +} + /* * Load/store register index */ @@ -10525,7 +10552,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rs; + uint32_t rn; int op; =20 /* @@ -10569,70 +10596,13 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) /* fall back to legacy decoder */ =20 rn =3D (insn >> 16) & 0xf; - rs =3D (insn >> 12) & 0xf; - rd =3D (insn >> 8) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); case 4: - if (insn & (1 << 22)) { - /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store doubleword, load/store exclusive, ldacq/strel, - * table branch, TT. - */ - if (insn & 0x01200000) { - /* load/store dual, in decodetree */ - goto illegal_op; - } else if ((insn & (1 << 23)) =3D=3D 0) { - /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store exclusive word - * - TT (v8M only) - */ - if (rs =3D=3D 15) { - if (!(insn & (1 << 20)) && - arm_dc_feature(s, ARM_FEATURE_M) && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1000_0100_xxxx_1111_xxxx_xxxx_xxxx - * - TT (v8M only) - */ - bool alt =3D insn & (1 << 7); - TCGv_i32 addr, op, ttresp; - - if ((insn & 0x3f) || rd =3D=3D 13 || rd =3D=3D 15 = || rn =3D=3D 15) { - /* we UNDEF for these UNPREDICTABLE cases */ - goto illegal_op; - } - - if (alt && !s->v8m_secure) { - goto illegal_op; - } - - addr =3D load_reg(s, rn); - op =3D tcg_const_i32(extract32(insn, 6, 2)); - ttresp =3D tcg_temp_new_i32(); - gen_helper_v7m_tt(ttresp, cpu_env, addr, op); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(op); - store_reg(s, rd, ttresp); - break; - } - goto illegal_op; - } - /* Load/store exclusive, in decodetree */ - goto illegal_op; - } else if ((insn & (7 << 5)) =3D=3D 0) { - /* Table Branch, in decodetree */ - goto illegal_op; - } else { - /* Load/store exclusive, load-acq/store-rel, in decodetree= */ - goto illegal_op; - } - } else { - /* Load/store multiple, RFE, SRS, in decodetree */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 5: /* All in decodetree */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c956ddb254..c63082fc9c 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -508,7 +508,10 @@ STRD_ri_t32 1110 1001 .110 .... .... .... .......= . @ldstd_ri8 w=3D1 p=3D1 @ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ &ldrex imm=3D0 =20 -STREX 1110 1000 0100 .... .... .... .... .... @strex_i +{ + TT 1110 1000 0100 rn:4 1111 rd:4 A:1 T:1 000000 + STREX 1110 1000 0100 .... .... .... .... .... @strex_i +} STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567628694; cv=none; d=zoho.com; s=zohoarc; b=QFBbm1Fhz6RS94EZlWMoPSEKsZd21K/D1tqF7EQMR/KW/sgAQ2Jmc33OdVGGiQ+IgMo82yNUbSEED/t3JDM8qu0sniNg00/Hee3Bsl3n3Gmp5nCGAF7xTcnxQ4EnUJA4LnScLME/fmXHSu64O95ktFIR2DQZJdFYy3JakN4cvt4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567628694; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=3YTIbEYYLxo/KQorAmZTbgiM25Lefa2PHYOLeWCcYi0=; b=XTdzbHGAnxU4nYRv0JH6SHyBOhmMPOhBlsDHDma0+YFyE64RpLJU/2QjkJSp43Bu73vslVlFqygmgssZNLrZujHy99o2jF0kOt6aog8h/x9XPfYlTA5xIu3g10C8jxnfrH5wgNgPnoBqujzjV7CJrMUSZhWzzYCjRCvaIbSCZfA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156762869399458.98879710967287; Wed, 4 Sep 2019 13:24:53 -0700 (PDT) Received: from localhost ([::1]:38720 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bpk-000263-Ti for importer@patchew.org; Wed, 04 Sep 2019 16:24:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40877) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0Z-0005GD-Rn for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0X-0002rv-WE for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:59 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:42782) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0X-0002qm-L6 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:57 -0400 Received: by mail-pg1-x542.google.com with SMTP id p3so11767558pgb.9 for ; Wed, 04 Sep 2019 12:31:57 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3YTIbEYYLxo/KQorAmZTbgiM25Lefa2PHYOLeWCcYi0=; b=sWmnukhBDGqqcv9TjfJdZ4SDcjn9MSCaKDM1tJlw3hc3tFSxec9rouYA6YODRBk0o7 n94gEhbxKULseowqcYiiBCewkSsYUt8yq+el1xfOtPtk12nql1NRSzE7ZknirJ2Xcbd5 ANt7aIWg/D1iLHRXqxnubmvKCKvXIHfTHrO4SgDq5tioVMz1lHYX7VZNzXRoxSmEZMQX jWSaxVv7e6fGN5ciAUK3BkJsRoz+mTHBpcesf1guc1o/EAkSKx2PWE3Ec9K87205CoUS LSLZMszDz8c1KSyKVlXoWjVSgrHfFA6yUZg8ZUO1na9EJTx1ae9wTM/rvhmx4WyYe7xU DZJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3YTIbEYYLxo/KQorAmZTbgiM25Lefa2PHYOLeWCcYi0=; b=TdJmOILL9+7AjrPvSnocMTxYAiZMYKrr3erJzrJaytKX6Gz8DQUGTRxPPrTT3LLMq1 RpZDQcx7ohQBlRIy9mNss07suGQB9BZXW0yCfD5E9kmvxbYn+DdDcGZnnjdj085Bpuop aBUUbVC5IDflvjdQWL99m5earcPxJVO3ZaXli/n5t2DXyiM22c1AyulRAURDFEFaBZqR t+kyhbJ5Qx6knzl0mOtvq9GZfcPOtI+Z3Mu1Xg+n1DXUlPUDa4pCc+erdQJIxcL+JJEv jPDr94x33bLKAg0OcfYwglO1k5kp0mOiF0yaOuLmaBQZ6nwPhQBgkyDlG/Jc/Qz12XSj NGxg== X-Gm-Message-State: APjAAAWz5mwICENaTe+oJmlV7kqu7wcZ7JrxD/X1mkJy+NCB1Ibdl9KH 21CvVGjqvgX03WDEGq2z5c+dd/cfEAo= X-Google-Smtp-Source: APXvYqxeXi/ceqN0XHAoOunUdbpcpnq/5W8WjrkMgDm0AyORoB8C0RwshAs0bQ5OPQVwMv92XfPiGA== X-Received: by 2002:a63:f048:: with SMTP id s8mr35777496pgj.26.1567625516138; Wed, 04 Sep 2019 12:31:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:33 -0700 Message-Id: <20190904193059.26202-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v4 43/69] target/arm: Simplify disas_thumb2_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 79 ++---------------------------------------- 1 file changed, 3 insertions(+), 76 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 46c27ea6a8..f68e09ff1f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10552,9 +10552,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, ui= nt32_t pc, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rn; - int op; - /* * ARMv6-M supports a limited subset of Thumb2 instructions. * Other Thumb1 architectures allow only 32-bit @@ -10595,34 +10592,10 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) } /* fall back to legacy decoder */ =20 - rn =3D (insn >> 16) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); - case 4: - /* All in decodetree */ - goto illegal_op; - case 5: - /* All in decodetree */ - goto illegal_op; - case 13: /* Misc data processing. */ - op =3D ((insn >> 22) & 6) | ((insn >> 7) & 1); - if (op < 4 && (insn & 0xf000) !=3D 0xf000) - goto illegal_op; - switch (op) { - case 0: /* Register controlled shift, in decodetree */ - case 1: /* Sign/zero extend, in decodetree */ - case 2: /* SIMD add/subtract, in decodetree */ - case 3: /* Other data processing, in decodetree */ - goto illegal_op; - case 4: case 5: - /* 32-bit multiply. Sum of absolute differences, in decodetre= e */ - goto illegal_op; - case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ - goto illegal_op; - } - break; case 6: case 7: case 14: case 15: /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { @@ -10651,6 +10624,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) } =20 if (arm_dc_feature(s, ARM_FEATURE_VFP)) { + uint32_t rn =3D (insn >> 16) & 0xf; TCGv_i32 fptr =3D load_reg(s, rn); =20 if (extract32(insn, 20, 1)) { @@ -10709,50 +10683,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) } } break; - case 8: case 9: case 10: case 11: - if (insn & (1 << 15)) { - /* Branches, misc control. */ - if (insn & 0x5000) { - /* Unconditional branch, in decodetree */ - goto illegal_op; - } else if (((insn >> 23) & 7) =3D=3D 7) { - /* Misc control */ - if (insn & (1 << 13)) - goto illegal_op; - - if (insn & (1 << 26)) { - /* hvc, smc, in decodetree */ - goto illegal_op; - } else { - op =3D (insn >> 20) & 7; - switch (op) { - case 0: /* msr cpsr, in decodetree */ - case 1: /* msr spsr, in decodetree */ - goto illegal_op; - case 2: /* cps, nop-hint, in decodetree */ - goto illegal_op; - case 3: /* Special control operations, in decodetree */ - case 4: /* bxj, in decodetree */ - goto illegal_op; - case 5: /* Exception return. */ - case 6: /* MRS, in decodetree */ - case 7: /* MSR, in decodetree */ - goto illegal_op; - } - } - } else { - /* Conditional branch, in decodetree */ - goto illegal_op; - } - } else { - /* - * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate, plain binary immedi= ate) - * All in decodetree. - */ - goto illegal_op; - } - break; case 12: if ((insn & 0x01100000) =3D=3D 0x01000000) { if (disas_neon_ls_insn(s, insn)) { @@ -10760,14 +10690,11 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) } break; } - /* Load/store single data item, in decodetree */ goto illegal_op; default: - goto illegal_op; + illegal_op: + unallocated_encoding(s); } - return; -illegal_op: - unallocated_encoding(s); } =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567628980; cv=none; d=zoho.com; s=zohoarc; b=JmQFrClQmN/G7ty7GK3cs/OsKgUxyIXNmYpSNAZ31M8jZV4u5MtwGa/LYDYmiHDUGbi+sc/HTWH2NjhQkP5iHUui2C+7dFx/rS0oQYA2BtzoTrMP7FKxHrnnZuGZ4PRxjM/61lyqo7IBxdYboiYZ2owSwlvjZDsZ+/XbDAh0y1E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567628980; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=VzsNEJ79vBBXHa6di56eotbjbD089opoeS7FPmrAgFs=; b=Ks14B57gEuaDKvT93r19X+SoK3ZxEtFSpVoaf0+UUP2M85cjkBEe+3MYWY3QSJLBU3qQw+AB0HJArKmj7MqXOquBDhsLeZ0WIwSZ8XwlxZcsvpT8jbL2HvN1QVtc7XuYeiO0WX5e3wNduW3AHSSCnNUMqd+De2+OEXhRW9mqtXc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567628980416338.1261338489078; Wed, 4 Sep 2019 13:29:40 -0700 (PDT) Received: from localhost ([::1]:38794 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5buM-0006Tj-JE for importer@patchew.org; Wed, 04 Sep 2019 16:29:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40893) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0a-0005Hf-RU for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0Y-0002sx-Ti for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:00 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:34379) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0Y-0002s8-M7 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:58 -0400 Received: by mail-pf1-x441.google.com with SMTP id r12so1752236pfh.1 for ; Wed, 04 Sep 2019 12:31:58 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VzsNEJ79vBBXHa6di56eotbjbD089opoeS7FPmrAgFs=; b=hYOf+kyOC9AZ+E0vgO5tCaEmGZjWMRbuJk28WTnMTHv6EuLVa+7DBJc/eksBzZo3ei dfExrjpYNfdJRIuoi+MKnL2DXyOsStqRfz3w1yWlS2W+I/4h2uAtEtzo3RP3zhjJrGH9 tjaLNGjFGa8dBAVjJA7RWZZ6zNVMn3r80s/0kk//6JQMKkD4MVpYese8MTXahI9d9Osj pmXmn+dWSymsAAgUGwNvqFVZtnGGkwwD6/XATdAsSCKijQZHauCbH8kS18D67WEyUqP2 oH/NYHq1etyDOUttNqtOHaYJwQJbclcgrT+0dyhkXQoWHzyO2E0fyIX+ot7TW7vSgCA+ 5A5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VzsNEJ79vBBXHa6di56eotbjbD089opoeS7FPmrAgFs=; b=dJRrZAbBICfdO38G17a7kXcBrlGS1hvIIr+au48Tq8TSObIvz1ZnV3OwNoXx1gwhP8 tUgBy9UZt6T56JlhvnXPpEKpogXqSStEEuccTlN7KmOzXReuKcuYWx9sVjW91aA8HB3c XPiHIy8LHkxPJzd//BP9l4gGPQE5O9cFp/Vur7G7Gnmt/7yWbGuwtWaZhJtEtzv4Oy6e LLqOGkt5rGaq9pqTF/pyM1DiXA5bXBAzGfDsoR0dEc+b10jVSajkBu9SFcsBfISYyagx XzJrdTAtEGR0Y6oZAnBOk2Gpce/u5anFdYXpsj2cJxWG4LuLmkUgXYZxkjsZnP4RwC6z plTw== X-Gm-Message-State: APjAAAWhXWYv256b6oByvtzjFPiV+b/V/JzmCEbStnpGkopPjQWMXibt XWSMIcfo4YvbhngV7QyvNhaQYFepn20= X-Google-Smtp-Source: APXvYqwpLVEfboqWbPqy3LvUl85SokwSibRFFd0zDN7B5Pk9L9tO6wYVBj0DmSJvMlHr83Gr1Jqk4w== X-Received: by 2002:a63:755e:: with SMTP id f30mr36601200pgn.246.1567625517269; Wed, 04 Sep 2019 12:31:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:34 -0700 Message-Id: <20190904193059.26202-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v4 44/69] target/arm: Simplify disas_arm_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 69 ++++++++++-------------------------------- 1 file changed, 16 insertions(+), 53 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f68e09ff1f..7f2a46100e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10364,7 +10364,7 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) =20 static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1; + unsigned int cond =3D insn >> 28; =20 /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10374,7 +10374,6 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) default_exception_el(s)); return; } - cond =3D insn >> 28; =20 if (cond =3D=3D 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we @@ -10439,11 +10438,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) goto illegal_op; } return; - } else if ((insn & 0x0fe00000) =3D=3D 0x0c400000) { - /* Coprocessor double register transfer. */ - ARCH(5TE); - } else if ((insn & 0x0f000010) =3D=3D 0x0e000010) { - /* Additional coprocessor register transfer. */ } goto illegal_op; } @@ -10458,55 +10452,24 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) } /* fall back to legacy decoder */ =20 - if ((insn & 0x0f900000) =3D=3D 0x03000000) { - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if ((insn & 0x0f900000) =3D=3D 0x01000000 - && (insn & 0x00000090) !=3D 0x00000090) { - /* miscellaneous instructions */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if (((insn & 0x0e000000) =3D=3D 0 && - (insn & 0x00000090) !=3D 0x90) || - ((insn & 0x0e000000) =3D=3D (1 << 25))) { - /* Data-processing (reg, reg-shift-reg, imm). */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - /* other instructions */ - op1 =3D (insn >> 24) & 0xf; - switch(op1) { - case 0x0: - case 0x1: - case 0x4: - case 0x5: - case 0x6: - case 0x7: - case 0x08: - case 0x09: - case 0xa: - case 0xb: - case 0xf: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 0xc: - case 0xd: - case 0xe: - if (((insn >> 8) & 0xe) =3D=3D 10) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - } else if (disas_coproc_insn(s, insn)) { - /* Coprocessor. */ + switch ((insn >> 24) & 0xf) { + case 0xc: + case 0xd: + case 0xe: + if (((insn >> 8) & 0xe) =3D=3D 10) { + /* VFP. */ + if (disas_vfp_insn(s, insn)) { goto illegal_op; } - break; - default: - illegal_op: - unallocated_encoding(s); - break; + } else if (disas_coproc_insn(s, insn)) { + /* Coprocessor. */ + goto illegal_op; } + break; + default: + illegal_op: + unallocated_encoding(s); + break; } } =20 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567628148; cv=none; d=zoho.com; s=zohoarc; b=kis+/G1Z86sKDT/NNnl+JSJSo6fSqLMZ+gA07nfnv+VUK5RkAihVxco2AHQOartUHSzLn+san+oGQrWlo++ZK+jmQnsV6Emrcaf4pXHN+z9ZEXY/5Irskzl/7GUfdd5YtzYbVu8W86XaJkJxCenLvLAKsfG5d0PwwXXuDXnhP9s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567628148; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=0Xeagu+uHVK2sO684+uTrIYgzxrvd15EJGaykrkk5Oc=; b=b8htKRlXP20hFRo0sZy4Q4F1fkytkayoEgww1Bcs9F8D/OluooNH0T+PDAXbKh7LCGlvtaOIKc5elLTsfC96CkZjP4MYYYuBlakeVQZ/Dgzsnt4rhvzuZg2Lqk96Tbe4sa/D26UI9l7Rhd3VR60YYOW/ZXoB+EtxEUvglgp0fQA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567628148293362.40578989140124; Wed, 4 Sep 2019 13:15:48 -0700 (PDT) Received: from localhost ([::1]:38564 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bgw-0001GV-6I for importer@patchew.org; Wed, 04 Sep 2019 16:15:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40944) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0d-0005KB-T9 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0a-0002uO-7V for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:03 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:46569) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0Z-0002tR-OR for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:31:59 -0400 Received: by mail-pf1-x429.google.com with SMTP id q5so6053948pfg.13 for ; Wed, 04 Sep 2019 12:31:59 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.31.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:31:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Xeagu+uHVK2sO684+uTrIYgzxrvd15EJGaykrkk5Oc=; b=BS78uIzA2V0Ik7j6VEbA7aI72ZgTwaaKBBGMTUeQviINV0kX4qtTKqHJt8e6tArPUo UyD4fJg9iQ+tUEFxjwxQERsd8G6YShBq0RWaLha6aQ2QKLZdxMljZOQCEWQ6vgI+jRmY p1GiTpIFObExKRSUhk1Pmv9jTdMF509w23YrQw3kcNo2+igLvm7Oo93bmvtYdQ4d1oVT xdWbXzvHK7CEbvWhJDf42eONr4Km+2g3Z4wceZGLkCFcltzmD2Sh6Y+UzL2QLT9vrv2K pCNu0JLYsqUObqszMpMJQV8qo8f5McC3eyIl236Ac0HWVsrQpzeoE7C19bwBHsMvy7UO qZkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Xeagu+uHVK2sO684+uTrIYgzxrvd15EJGaykrkk5Oc=; b=Lc63ie8RAOvSvHAUEuq9Grk/BmtJuMFSV3wf3g6lEJBIG0l54P+h34vOZWss4h+ncv yJAOYJxgRRG/LeUCUf40Xga1/Xo0zvcFqRhUSj1/19GSxChYfLklIKE9K1Dh9lMMZMUp 4aRP+WDYPqJkmtGoICUAIG1wVCI1y0ZtY5ElgKBwaVOsSZcnyQtZAw66zdi/A+t+4jcG jfKMR7KzrgXFdWOV90F9tQdVT81p/XHxdTOWKmT9xwojmWCuGiQHStJ4H1p5uhDBB9Sl rV4O5zbsJqtyEKpwoNutnFyih4jqzN3lXib6Qs2nIE+XTCfzOYh9X4sZnbZOOt1nXGr1 4EeA== X-Gm-Message-State: APjAAAVGbdhGv/qtze+xkM54TqBUG8WOMso/kDdUCY5Ha29s+WkpNP17 A3TBjI3QjgKlSonbBGdfMfD02YaBvV8= X-Google-Smtp-Source: APXvYqzob+jJfdQl1gBys4C3M1sna8ZtCZiwS++2m1pXsRkFUHpG1KsicGGEOSpVFW/kbKH9ii81VQ== X-Received: by 2002:a63:fc52:: with SMTP id r18mr36581969pgk.378.1567625518491; Wed, 04 Sep 2019 12:31:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:35 -0700 Message-Id: <20190904193059.26202-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PATCH v4 45/69] target/arm: Add skeleton for T16 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/translate.c | 6 ++++++ target/arm/Makefile.objs | 6 ++++++ target/arm/t16.decode | 20 ++++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 target/arm/t16.decode diff --git a/target/arm/translate.c b/target/arm/translate.c index 7f2a46100e..7e530f1fdc 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7560,6 +7560,7 @@ static int t32_branch24(DisasContext *s, int x) #include "decode-a32.inc.c" #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" +#include "decode-t16.inc.c" =20 /* Helpers to swap operands for reverse-subtract. */ static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) @@ -10669,6 +10670,11 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) TCGv_i32 tmp2; TCGv_i32 addr; =20 + if (disas_t16(s, insn)) { + return; + } + /* fall back to legacy decoder */ + switch (insn >> 12) { case 0: case 1: =20 diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 7806b4dac0..cf26c16f5f 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -43,12 +43,18 @@ target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32= .decode $(DECODETREE) $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ "GEN", $(TARGET_DIR)$@) =20 +target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETRE= E) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c target/arm/translate.o: target/arm/decode-a32.inc.c target/arm/translate.o: target/arm/decode-a32-uncond.inc.c target/arm/translate.o: target/arm/decode-t32.inc.c +target/arm/translate.o: target/arm/decode-t16.inc.c =20 obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o diff --git a/target/arm/t16.decode b/target/arm/t16.decode new file mode 100644 index 0000000000..e954f61fe4 --- /dev/null +++ b/target/arm/t16.decode @@ -0,0 +1,20 @@ +# Thumb1 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567627824; cv=none; d=zoho.com; s=zohoarc; b=FLL4dUAlDRbn+USZSRqJ/rB1l+7Uz0GE4CQO0yp9WhWBqmvMsiE8ACe8pTithUUgmdyoKNZToqG4YZGtWWNKHxyT6oxMi5OO61104unzSic0I89zMHayBP0IksPUlpD4kYXsfaFje5pB9FTMMey0+YiE70SQOwC0geqDJFzHKkE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567627824; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=egisVGOg4CJ3QPg/JSR7AUyfTVGzQfFPHW96Z7DyXjs=; b=FQlRS3xt+L25pkxC0r08aoRHo9FvjjTF7ZHCGT/ZzUSmrTk1xGfshOSvMzTgtekepKfvw8hGV2neRbniakawrI7quAH85+s4Kw+guLvI2HIAn+UBsbTdzykuVParQRlsmJP2BqHzEgPeoPgCSQWIhS3c09kCj31Swp83d9TZ2Z0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567627824295987.3710995114293; Wed, 4 Sep 2019 13:10:24 -0700 (PDT) Received: from localhost ([::1]:38478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bbi-0004aK-E3 for importer@patchew.org; Wed, 04 Sep 2019 16:10:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40946) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0d-0005KD-TG for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0b-0002vd-Cb for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:03 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:35276) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0a-0002uc-WA for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:01 -0400 Received: by mail-pg1-x544.google.com with SMTP id n4so11796708pgv.2 for ; Wed, 04 Sep 2019 12:32:00 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH v4 46/69] target/arm: Convert T16 data-processing (two low regs) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 152 ++--------------------------------------- target/arm/t16.decode | 36 ++++++++++ 2 files changed, 43 insertions(+), 145 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7e530f1fdc..b77922f808 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -445,13 +445,6 @@ static inline void gen_logic_CC(TCGv_i32 var) tcg_gen_mov_i32(cpu_ZF, var); } =20 -/* T0 +=3D T1 + CF. */ -static void gen_adc(TCGv_i32 t0, TCGv_i32 t1) -{ - tcg_gen_add_i32(t0, t0, t1); - tcg_gen_add_i32(t0, t0, cpu_CF); -} - /* dest =3D T0 + T1 + CF. */ static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { @@ -7553,6 +7546,11 @@ static int t32_branch24(DisasContext *s, int x) return x << 1; } =20 +static int t16_setflags(DisasContext *s) +{ + return s->condexec_mask =3D=3D 0; +} + /* * Include the generated decoders. */ @@ -10861,145 +10859,9 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) =20 /* * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers) + * - Data-processing (two low registers), in decodetree */ - rd =3D insn & 7; - rm =3D (insn >> 3) & 7; - op =3D (insn >> 6) & 0xf; - if (op =3D=3D 2 || op =3D=3D 3 || op =3D=3D 4 || op =3D=3D 7) { - /* the shift/rotate ops want the operands backwards */ - val =3D rm; - rm =3D rd; - rd =3D val; - val =3D 1; - } else { - val =3D 0; - } - - if (op =3D=3D 9) { /* neg */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else if (op !=3D 0xf) { /* mvn doesn't read its first operand */ - tmp =3D load_reg(s, rd); - } else { - tmp =3D NULL; - } - - tmp2 =3D load_reg(s, rm); - switch (op) { - case 0x0: /* and */ - tcg_gen_and_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x1: /* eor */ - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x2: /* lsl */ - if (s->condexec_mask) { - gen_shl(tmp2, tmp2, tmp); - } else { - gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x3: /* lsr */ - if (s->condexec_mask) { - gen_shr(tmp2, tmp2, tmp); - } else { - gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x4: /* asr */ - if (s->condexec_mask) { - gen_sar(tmp2, tmp2, tmp); - } else { - gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x5: /* adc */ - if (s->condexec_mask) { - gen_adc(tmp, tmp2); - } else { - gen_adc_CC(tmp, tmp, tmp2); - } - break; - case 0x6: /* sbc */ - if (s->condexec_mask) { - gen_sub_carry(tmp, tmp, tmp2); - } else { - gen_sbc_CC(tmp, tmp, tmp2); - } - break; - case 0x7: /* ror */ - if (s->condexec_mask) { - tcg_gen_andi_i32(tmp, tmp, 0x1f); - tcg_gen_rotr_i32(tmp2, tmp2, tmp); - } else { - gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x8: /* tst */ - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - rd =3D 16; - break; - case 0x9: /* neg */ - if (s->condexec_mask) - tcg_gen_neg_i32(tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - break; - case 0xa: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - rd =3D 16; - break; - case 0xb: /* cmn */ - gen_add_CC(tmp, tmp, tmp2); - rd =3D 16; - break; - case 0xc: /* orr */ - tcg_gen_or_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xd: /* mul */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xe: /* bic */ - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xf: /* mvn */ - tcg_gen_not_i32(tmp2, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp2); - val =3D 1; - rm =3D rd; - break; - } - if (rd !=3D 16) { - if (val) { - store_reg(s, rm, tmp2); - if (op !=3D 0xf) - tcg_temp_free_i32(tmp); - } else { - store_reg(s, rd, tmp); - tcg_temp_free_i32(tmp2); - } - } else { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - } - break; + goto illegal_op; =20 case 5: /* load/store register offset. */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index e954f61fe4..44e7250c55 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -18,3 +18,39 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra + +# Set S if the instruction is outside of an IT block. +%s !function=3Dt16_setflags + +# Data-processing (two low registers) + +%reg_0 0:3 + +@lll_noshr ...... .... rm:3 rd:3 \ + &s_rrr_shi %s rn=3D%reg_0 shim=3D0 shty=3D0 +@xll_noshr ...... .... rm:3 rn:3 \ + &s_rrr_shi s=3D1 rd=3D0 shim=3D0 shty=3D0 +@lxl_shr ...... .... rs:3 rd:3 \ + &s_rrr_shr %s rm=3D%reg_0 rn=3D0 + +AND_rrri 010000 0000 ... ... @lll_noshr +EOR_rrri 010000 0001 ... ... @lll_noshr +MOV_rxrr 010000 0010 ... ... @lxl_shr shty=3D0 # LSL +MOV_rxrr 010000 0011 ... ... @lxl_shr shty=3D1 # LSR +MOV_rxrr 010000 0100 ... ... @lxl_shr shty=3D2 # ASR +ADC_rrri 010000 0101 ... ... @lll_noshr +SBC_rrri 010000 0110 ... ... @lll_noshr +MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3D3 # ROR +TST_xrri 010000 1000 ... ... @xll_noshr +RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=3D0 rot= =3D0 +CMP_xrri 010000 1010 ... ... @xll_noshr +CMN_xrri 010000 1011 ... ... @xll_noshr +ORR_rrri 010000 1100 ... ... @lll_noshr +MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=3D%reg_0 ra= =3D0 +BIC_rrri 010000 1110 ... ... @lll_noshr +MVN_rxri 010000 1111 ... ... @lll_noshr --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v4 47/69] target/arm: Convert T16 load/store (register offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++---------------------------------------- target/arm/t16.decode | 15 +++++++++++++ 2 files changed, 17 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b77922f808..789abe9b87 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10864,55 +10864,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; =20 case 5: - /* load/store register offset. */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - rm =3D (insn >> 6) & 7; - op =3D (insn >> 9) & 7; - addr =3D load_reg(s, rn); - tmp =3D load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - - if (op < 3) { /* store */ - tmp =3D load_reg(s, rd); - } else { - tmp =3D tcg_temp_new_i32(); - } - - switch (op) { - case 0: /* str */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 1: /* strh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 2: /* strb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16B= it); - break; - case 3: /* ldrsb */ - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 4: /* ldr */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - break; - case 5: /* ldrh */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - break; - case 6: /* ldrb */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - break; - case 7: /* ldrsh */ - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - break; - } - if (op >=3D 3) { /* load */ - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; + /* load/store register offset, in decodetree */ + goto illegal_op; =20 case 6: /* load/store word immediate offset */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 44e7250c55..83fe4363c7 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ldst_rr !extern p w u rn rt rm shimm shtype =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -54,3 +55,17 @@ ORR_rrri 010000 1100 ... ... @lll_nos= hr MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=3D%reg_0 ra= =3D0 BIC_rrri 010000 1110 ... ... @lll_noshr MVN_rxri 010000 1111 ... ... @lll_noshr + +# Load/store (register offset) + +@ldst_rr ....... rm:3 rn:3 rt:3 \ + &ldst_rr p=3D1 w=3D0 u=3D1 shimm=3D0 shtype=3D0 + +STR_rr 0101 000 ... ... ... @ldst_rr +STRH_rr 0101 001 ... ... ... @ldst_rr +STRB_rr 0101 010 ... ... ... @ldst_rr +LDRSB_rr 0101 011 ... ... ... @ldst_rr +LDR_rr 0101 100 ... ... ... @ldst_rr +LDRH_rr 0101 101 ... ... ... @ldst_rr +LDRB_rr 0101 110 ... ... ... @ldst_rr +LDRSH_rr 0101 111 ... ... ... @ldst_rr --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 48/69] target/arm: Convert T16 load/store (immediate offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 94 +++--------------------------------------- target/arm/t16.decode | 33 +++++++++++++++ 2 files changed, 38 insertions(+), 89 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 789abe9b87..4ae73d1c92 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10863,97 +10863,13 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) */ goto illegal_op; =20 - case 5: - /* load/store register offset, in decodetree */ + case 5: /* load/store register offset, in decodetree */ + case 6: /* load/store word immediate offset, in decodetree */ + case 7: /* load/store byte immediate offset, in decodetree */ + case 8: /* load/store halfword immediate offset, in decodetree */ + case 9: /* load/store from stack, in decodetree */ goto illegal_op; =20 - case 6: - /* load/store word immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 4) & 0x7c; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 7: - /* load/store byte immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 6) & 0x1f; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16B= it); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 8: - /* load/store halfword immediate offset */ - rd =3D insn & 7; - rn =3D (insn >> 3) & 7; - addr =3D load_reg(s, rn); - val =3D (insn >> 5) & 0x3e; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 9: - /* load/store from stack */ - rd =3D (insn >> 8) & 7; - addr =3D load_reg(s, 13); - val =3D (insn & 0xff) * 4; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs1= 6Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp =3D load_reg(s, rd); - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16= Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - case 10: /* * 0b1010_xxxx_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 83fe4363c7..1cf79789ac 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -69,3 +70,35 @@ LDR_rr 0101 100 ... ... ... @ldst_rr LDRH_rr 0101 101 ... ... ... @ldst_rr LDRB_rr 0101 110 ... ... ... @ldst_rr LDRSH_rr 0101 111 ... ... ... @ldst_rr + +# Load/store word/byte (immediate offset) + +%imm5_6x4 6:5 !function=3Dtimes_4 + +@ldst_ri_1 ..... imm:5 rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 +@ldst_ri_4 ..... ..... rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm5_6x4 + +STR_ri 01100 ..... ... ... @ldst_ri_4 +LDR_ri 01101 ..... ... ... @ldst_ri_4 +STRB_ri 01110 ..... ... ... @ldst_ri_1 +LDRB_ri 01111 ..... ... ... @ldst_ri_1 + +# Load/store halfword (immediate offset) + +%imm5_6x2 6:5 !function=3Dtimes_2 +@ldst_ri_2 ..... ..... rn:3 rt:3 \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm5_6x2 + +STRH_ri 10000 ..... ... ... @ldst_ri_2 +LDRH_ri 10001 ..... ... ... @ldst_ri_2 + +# Load/store (SP-relative) + +%imm8_0x4 0:8 !function=3Dtimes_4 +@ldst_spec_i ..... rt:3 ........ \ + &ldst_ri p=3D1 w=3D0 u=3D1 imm=3D%imm8_0x4 + +STR_ri 10010 ... ........ @ldst_spec_i rn=3D13 +LDR_ri 10011 ... ........ @ldst_spec_i rn=3D13 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PATCH v4 49/69] target/arm: Convert T16 add pc/sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +----------- target/arm/t16.decode | 7 +++++++ 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4ae73d1c92..d8a4c7bf99 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10868,19 +10868,9 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) case 7: /* load/store byte immediate offset, in decodetree */ case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ + case 10: /* add PC/SP (immediate), in decodetree */ goto illegal_op; =20 - case 10: - /* - * 0b1010_xxxx_xxxx_xxxx - * - Add PC/SP (immediate) - */ - rd =3D (insn >> 8) & 7; - val =3D (insn & 0xff) * 4; - tmp =3D add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val); - store_reg(s, rd, tmp); - break; - case 11: /* misc */ op =3D (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 1cf79789ac..71b3e8f02e 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm =20 @@ -102,3 +103,9 @@ LDRH_ri 10001 ..... ... ... @ldst_r= i_2 =20 STR_ri 10010 ... ........ @ldst_spec_i rn=3D13 LDR_ri 10011 ... ........ @ldst_spec_i rn=3D13 + +# Add PC/SP (immediate) + +ADR 10100 rd:3 ........ imm=3D%imm8_0x4 +ADD_rri 10101 rd:3 ........ \ + &s_rri_rot rn=3D13 s=3D0 rot=3D0 imm=3D%imm8_0x4 # SP --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567629746; cv=none; d=zoho.com; s=zohoarc; b=KHgF0qkLe6SSI4FCedAgpF0iyfrz6HDLwuGB+rAL3kwYa/NyxIlNlpka2wlNz1TDX8/fkLPEKNXgZvOIwLkj/lX6wdZgS141XER4i/ZSQPlr2BEEd4QznxtKqn/eJVrOn8Eof57uxicyBh5dahIAWPuv9CVw4DF3Rirdnd6beI0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567629746; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=w0yZvSWJxMpGMZQus1AoRlEpuCLgbCFvsCSBHnvLgJY=; b=d+WQmd/8Ss8+ZUxfz5uNbgljSDHjJGAnoZZIiZThXHLtNKmfqafuQRcKryPiq+D2nsnkF76NgZqdkdPMsQ5duPl/Ia8kTVzcFF6f1pEReiAW54lG2IWO3ukJTszcKFXfjZdz6W6ldZ4Bz1JBFPOyvJtimuSBFsgUYSZRoxDAXeA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 156762974630465.71496065856695; Wed, 4 Sep 2019 13:42:26 -0700 (PDT) Received: from localhost ([::1]:39256 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5c6i-00038U-Vr for importer@patchew.org; Wed, 04 Sep 2019 16:42:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41058) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0p-0005QE-8K for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0n-00034A-3p for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:15 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:37432) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0l-0002yr-21 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:11 -0400 Received: by mail-pf1-x444.google.com with SMTP id y9so13912269pfl.4 for ; Wed, 04 Sep 2019 12:32:05 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w0yZvSWJxMpGMZQus1AoRlEpuCLgbCFvsCSBHnvLgJY=; b=oAWMyx+OInAyeHVBRTYQ0211CU9f7YQQu7eHhi0OtBesm6zLBmEq4gf0IAnKFOltPU FKqnJxVRtrbo0daKSFCCZxQHxGDhHrvx0UwxrpjDBHWNdI50D9d4+Okda5HrDKAlRBAa XCNHiXgJS0RaUzzpBG6aMA4PvDSaUmgY61v0ysv2xMJAP443bsF8l6TmdKYeIGbiIVKh BJ487Djgb1nLzYlDBW/Y6mfmewyiEIlU5m7YHGwrB6yAcgOlTqLcVCx/AbOQj4k3kqs7 vP38dqCyHKO54mAMSc225E7JzZ5IGQlDoCVCYyvU+Svt4po73TMEDYbt0CFoJxXJR1c1 71Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w0yZvSWJxMpGMZQus1AoRlEpuCLgbCFvsCSBHnvLgJY=; b=LaUY3Z5uL8gq1a+J2B5o0EudKMjVZDoMGlZ0621aYz7pDnin2C0pyn4hwe1x/nNofZ 2jDy0mlI0+vRb1sckcR8ZVV9FswChvEB8Bqgc7LxneJHTJfTR6aWY7DrGBOietn+kBeX FHtMjDV343EerWYVa2qEi6YvJW2iCyZbKQBXxvBtibVX27t/giwVkpAKC3MTkzrM4EeQ lZfBMgMowWb94Uyp4UUWxqKSHSE66Gss4xCt71O1BkFtAtkhyg7FO9Ih5jHv5+NIglI1 p3jgAuJZ33PIikFhLQ+mI5pfBg0QQHn57KqmSdxRHTm6e9BFZnaXTkS8NH4b9OU8AdlP iz7Q== X-Gm-Message-State: APjAAAUbyBWHTgadpo8Asck02BLzw7xPh8/clGlrcwMe3RLYKwKUXJa9 XdMH92sFc2lqQp9LmRa01DSNEBpg1Yg= X-Google-Smtp-Source: APXvYqzDmzn2ArF2IUTIOfAmxP6op311GEPsnDAViWTSHhSS5FOzm+s1OKHauysgb9jGLdn0Ju6heQ== X-Received: by 2002:a63:b346:: with SMTP id x6mr36949199pgt.218.1567625524723; Wed, 04 Sep 2019 12:32:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:40 -0700 Message-Id: <20190904193059.26202-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 50/69] target/arm: Convert T16 load/store multiple X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 48 ++++++++---------------------------------- target/arm/t16.decode | 8 +++++++ 2 files changed, 17 insertions(+), 39 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d8a4c7bf99..f9d4b619fa 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10092,6 +10092,14 @@ static bool trans_LDM_t32(DisasContext *s, arg_lds= t_block *a) return do_ldm(s, a, 2); } =20 +static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback is conditional on the base register not being loaded. */ + a->w =3D !(a->list & (1 << a->rn)); + /* BitCount(list) < 1 is UNPREDICTABLE */ + return do_ldm(s, a, 1); +} + /* * Branch, branch with link */ @@ -10869,6 +10877,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 12: /* load/store multiple, in decodetree */ goto illegal_op; =20 case 11: @@ -11092,45 +11101,6 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) } break; =20 - case 12: - { - /* load/store multiple */ - TCGv_i32 loaded_var =3D NULL; - rn =3D (insn >> 8) & 0x7; - addr =3D load_reg(s, rn); - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* load */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i =3D=3D rn) { - loaded_var =3D tmp; - } else { - store_reg(s, i, tmp); - } - } else { - /* store */ - tmp =3D load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - if ((insn & (1 << rn)) =3D=3D 0) { - /* base reg not in list: base register writeback */ - store_reg(s, rn, addr); - } else { - /* base reg in list: if load, complete it now */ - if (insn & (1 << 11)) { - store_reg(s, rn, loaded_var); - } - tcg_temp_free_i32(addr); - } - break; - } case 13: /* conditional branch or swi */ cond =3D (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 71b3e8f02e..a7a437f930 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -26,6 +26,7 @@ &ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -109,3 +110,10 @@ LDR_ri 10011 ... ........ @ldst_= spec_i rn=3D13 ADR 10100 rd:3 ........ imm=3D%imm8_0x4 ADD_rri 10101 rd:3 ........ \ &s_rri_rot rn=3D13 s=3D0 rot=3D0 imm=3D%imm8_0x4 # SP + +# Load/store multiple + +@ldstm ..... rn:3 list:8 &ldst_block i=3D1 b=3D0 u= =3D0 w=3D1 + +STM 11000 ... ........ @ldstm +LDM_t16 11001 ... ........ @ldstm --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 51/69] target/arm: Convert T16 add/sub (3 low, 2 low and imm) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f9d4b619fa..45d617a2d3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10691,31 +10691,9 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) * 0b0001_1xxx_xxxx_xxxx * - Add, subtract (three low registers) * - Add, subtract (two low registers and immediate) + * In decodetree. */ - rn =3D (insn >> 3) & 7; - tmp =3D load_reg(s, rn); - if (insn & (1 << 10)) { - /* immediate */ - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, (insn >> 6) & 7); - } else { - /* reg */ - rm =3D (insn >> 6) & 7; - tmp2 =3D load_reg(s, rm); - } - if (insn & (1 << 9)) { - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - } else { - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); + goto illegal_op; } else { /* shift immediate */ rm =3D (insn >> 3) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index a7a437f930..2b5f368d31 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -117,3 +117,19 @@ ADD_rri 10101 rd:3 ........ \ =20 STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm + +# Add/subtract (three low registers) + +@addsub_3 ....... rm:3 rn:3 rd:3 \ + &s_rrr_shi %s shim=3D0 shty=3D0 + +ADD_rrri 0001100 ... ... ... @addsub_3 +SUB_rrri 0001101 ... ... ... @addsub_3 + +# Add/subtract (two low registers and immediate) + +@addsub_2i ....... imm:3 rn:3 rd:3 \ + &s_rri_rot %s rot=3D0 + +ADD_rri 0001 110 ... ... ... @addsub_2i +SUB_rri 0001 111 ... ... ... @addsub_2i --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GTpzfRqA1Z7CTTR4kjGQDvZeJQsqYpR7KKBaZOTKQX8=; b=xBr3jDB+VGXTWDyJtijhac1nLdzJw0dR9/idz0hu1xY62fYMdAqnpwxvJT5mP76+xC 5GtUs8+hfRtJ6q4YZxWFsSW1rbvBHLFvizZPdrRCAEDEUw/FbEylHgNZJEMURJ8SlnkQ 65HA6LJFKtgMlJpDPJORWkGXjrlIRYHgroIAHN7m65QvRD4Adzd27TD/kJ0rva2HN2/i fwosAVB8e9Ph9G0b1+ZTQDKg/MzXAc9HwVPIQLbxsSfqn5jkaY1lrsv26EF8P5n+Iefg facNsKao72OMYvDwYrtbAddx+bUzAiFv27Ds6xZD8w6UrwaerIhS7oKI5BxnrT+c2hAB YRNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GTpzfRqA1Z7CTTR4kjGQDvZeJQsqYpR7KKBaZOTKQX8=; b=HIUOHPlkBPDHEh7Q2XZ1KiD50gszZvKknIAcpqCn69L5Nvu+/L4bodjjBux5Go5Rzn kGA7vaFYAQUi8JoLbEKDJ2Cqk3EW08Lk3wK7czQ5C8Th0FSZ5PqZSlC+O0CgYk+3FMtj 78siSLBCxmHGpZCJGMs70BR3As9FdJohOgK4I0wJ7zxpQv5iMHvLGH3+SBoIFT+/BUgX XILoXBImeU016gzA7qVzVZxHvuP9UHPwSIFx4ECXttrE2xf1bXPV+7qQMTkFC3Gzzba6 rF3AejtE00JlDMZzNup+/Y5W+ImpgpNr6Y4Rp3jiuAGp3jAWvS6P5uqPCClAYzBgEoiN RXsg== X-Gm-Message-State: APjAAAVQwzhCOI14BJRrDuu3g27M1fHkdKmj+mqEMcFyLZQNjJ+PtghB 6EvEoEaYhm2ksJo8jd/7mAloZsKT7cg= X-Google-Smtp-Source: APXvYqwDF0NMnvJblyDch+LRhDkCAcR5UPs4+J+1sM4hdDW+mCB45EGKca0+qraeOWvnZFAs4+I0eA== X-Received: by 2002:a63:5c1a:: with SMTP id q26mr19300441pgb.19.1567625527220; Wed, 04 Sep 2019 12:32:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:42 -0700 Message-Id: <20190904193059.26202-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 52/69] target/arm: Convert T16 one low register and immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 44 ++---------------------------------------- target/arm/t16.decode | 11 +++++++++++ 2 files changed, 13 insertions(+), 42 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 45d617a2d3..405176527c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10705,48 +10705,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) store_reg(s, rd, tmp); } break; - case 2: case 3: - /* - * 0b001x_xxxx_xxxx_xxxx - * - Add, subtract, compare, move (one low register and immediate) - */ - op =3D (insn >> 11) & 3; - rd =3D (insn >> 8) & 0x7; - if (op =3D=3D 0) { /* mov */ - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, insn & 0xff); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } else { - tmp =3D load_reg(s, rd); - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, insn & 0xff); - switch (op) { - case 1: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - break; - case 2: /* add */ - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - case 3: /* sub */ - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - } - } - break; + case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ + goto illegal_op; case 4: if (insn & (1 << 11)) { rd =3D (insn >> 8) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 2b5f368d31..0654275e68 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -133,3 +133,14 @@ SUB_rrri 0001101 ... ... ... @addsu= b_3 =20 ADD_rri 0001 110 ... ... ... @addsub_2i SUB_rri 0001 111 ... ... ... @addsub_2i + +# Add, subtract, compare, move (one low register and immediate) + +%reg_8 8:3 +@arith_1i ..... rd:3 imm:8 \ + &s_rri_rot rot=3D0 rn=3D%reg_8 + +MOV_rxi 00100 ... ........ @arith_1i %s +CMP_xri 00101 ... ........ @arith_1i s=3D1 +ADD_rri 00110 ... ........ @arith_1i %s +SUB_rri 00111 ... ........ @arith_1i %s --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH v4 53/69] target/arm: Convert T16 branch and exchange X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 70 +++++++++++++++++------------------------- target/arm/t16.decode | 10 ++++++ 2 files changed, 39 insertions(+), 41 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 405176527c..e6ef935247 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8364,7 +8364,7 @@ static bool trans_BX(DisasContext *s, arg_BX *a) if (!ENABLE_ARCH_4T) { return false; } - gen_bx(s, load_reg(s, a->rm)); + gen_bx_excret(s, load_reg(s, a->rm)); return true; } =20 @@ -8391,6 +8391,32 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *= a) return true; } =20 +/* + * BXNS/BLXNS: only exist for v8M with the security extensions, + * and always UNDEF if NonSecure. We don't implement these in + * the user-only mode either (in theory you can use them from + * Secure User mode but they are too tied in to system emulation). + */ +static bool trans_BXNS(DisasContext *s, arg_BXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + unallocated_encoding(s); + } else { + gen_bxns(s, a->rm); + } + return true; +} + +static bool trans_BLXNS(DisasContext *s, arg_BLXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + unallocated_encoding(s); + } else { + gen_blxns(s, a->rm); + } + return true; +} + static bool trans_CLZ(DisasContext *s, arg_CLZ *a) { TCGv_i32 tmp; @@ -10756,49 +10782,11 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) } break; case 3: - { /* 0b0100_0111_xxxx_xxxx * - branch [and link] exchange thumb register + * In decodetree */ - bool link =3D insn & (1 << 7); - - if (insn & 3) { - goto undef; - } - if (link) { - ARCH(5); - } - if ((insn & 4)) { - /* BXNS/BLXNS: only exists for v8M with the - * security extensions, and always UNDEF if NonSecure. - * We don't implement these in the user-only mode - * either (in theory you can use them from Secure User - * mode but they are too tied in to system emulation.) - */ - if (!s->v8m_secure || IS_USER_ONLY) { - goto undef; - } - if (link) { - gen_blxns(s, rm); - } else { - gen_bxns(s, rm); - } - break; - } - /* BLX/BX */ - tmp =3D load_reg(s, rm); - if (link) { - val =3D (uint32_t)s->base.pc_next | 1; - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* Only BX works as exception-return, not BLX */ - gen_bx_excret(s, tmp); - } - break; - } + goto illegal_op; } break; } diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 0654275e68..edddbfb9b8 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ri !extern rd imm +&r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list @@ -144,3 +145,12 @@ MOV_rxi 00100 ... ........ @arith= _1i %s CMP_xri 00101 ... ........ @arith_1i s=3D1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s + +# Branch and exchange + +@branchr .... .... . rm:4 ... &r + +BX 0100 0111 0 .... 000 @branchr +BLX_r 0100 0111 1 .... 000 @branchr +BXNS 0100 0111 0 .... 100 @branchr +BLXNS 0100 0111 1 .... 100 @branchr --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 54/69] target/arm: Convert T16 add, compare, move (two high registers) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 49 ++---------------------------------------- target/arm/t16.decode | 10 +++++++++ 2 files changed, 12 insertions(+), 47 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e6ef935247..73c8863134 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10745,55 +10745,10 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) store_reg(s, rd, tmp); break; } - if (insn & (1 << 10)) { - /* 0b0100_01xx_xxxx_xxxx - * - data processing extended, branch and exchange - */ - rd =3D (insn & 7) | ((insn >> 4) & 8); - rm =3D (insn >> 3) & 0xf; - op =3D (insn >> 8) & 3; - switch (op) { - case 0: /* add */ - tmp =3D load_reg(s, rd); - tmp2 =3D load_reg(s, rm); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd =3D=3D 13) { - /* ADD SP, SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 1: /* cmp */ - tmp =3D load_reg(s, rd); - tmp2 =3D load_reg(s, rm); - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - break; - case 2: /* mov/cpy */ - tmp =3D load_reg(s, rm); - if (rd =3D=3D 13) { - /* MOV SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 3: - /* 0b0100_0111_xxxx_xxxx - * - branch [and link] exchange thumb register - * In decodetree - */ - goto illegal_op; - } - break; - } =20 /* - * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers), in decodetree + * - Data-processing (two low registers), in decodetree + * - data processing extended, branch and exchange, in decodetree */ goto illegal_op; =20 diff --git a/target/arm/t16.decode b/target/arm/t16.decode index edddbfb9b8..5a570484e3 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -146,6 +146,16 @@ CMP_xri 00101 ... ........ @arith= _1i s=3D1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s =20 +# Add, compare, move (two high registers) + +%reg_0_7 7:1 0:3 +@addsub_2h .... .... . rm:4 ... \ + &s_rrr_shi rd=3D%reg_0_7 rn=3D%reg_0_7 shim=3D0 shty=3D0 + +ADD_rrri 0100 0100 . .... ... @addsub_2h s=3D0 +CMP_xrri 0100 0101 . .... ... @addsub_2h s=3D1 +MOV_rxri 0100 0110 . .... ... @addsub_2h s=3D0 + # Branch and exchange =20 @branchr .... .... . rm:4 ... &r --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v4 55/69] target/arm: Convert T16 adjust sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 ++------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 73c8863134..8399a2c1f6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10765,19 +10765,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) /* misc */ op =3D (insn >> 8) & 0xf; switch (op) { - case 0: - /* - * 0b1011_0000_xxxx_xxxx - * - ADD (SP plus immediate) - * - SUB (SP minus immediate) - */ - tmp =3D load_reg(s, 13); - val =3D (insn & 0x7f) * 4; - if (insn & (1 << 7)) - val =3D -(int32_t)val; - tcg_gen_addi_i32(tmp, tmp, val); - store_sp_checked(s, tmp); - break; + case 0: /* add/sub (sp, immediate), in decodetree */ + goto illegal_op; =20 case 2: /* sign/zero extend. */ ARCH(6); diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 5a570484e3..b425b86795 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -156,6 +156,15 @@ ADD_rrri 0100 0100 . .... ... @addsu= b_2h s=3D0 CMP_xrri 0100 0101 . .... ... @addsub_2h s=3D1 MOV_rxri 0100 0110 . .... ... @addsub_2h s=3D0 =20 +# Adjust SP (immediate) + +%imm7_0x4 0:7 !function=3Dtimes_4 +@addsub_sp_i .... .... . ....... \ + &s_rri_rot s=3D0 rd=3D13 rn=3D13 rot=3D0 imm=3D%imm7_0x4 + +ADD_rri 1011 0000 0 ....... @addsub_sp_i +SUB_rri 1011 0000 1 ....... @addsub_sp_i + # Branch and exchange =20 @branchr .... .... . rm:4 ... &r --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567628278; cv=none; d=zoho.com; s=zohoarc; b=TGYk/CZ+uNg81EkbiKGzeDINbfklQDHzIpDdxyZUzghiylDqN9vcY8g2k09D7jwzkwMMKW/r/YNvfpaN1R53H6JqHT0mWdRzIrVTwOU6rUCyGOHZrisQE7u1PF9dBGyUHXury8COPANiK9fZYhCSolilgYSTDqN+A1UhCtQFxwU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567628278; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=hhcY0Qa7fXCZ0Y1BiAhkkX6indoh0p/z8TLYSSed1LE=; b=U9Z1u0dzuvFCzbYFArupSXv1vGMQLjKGxhWxPm4RIAcX/JJopsUzF3r4cIjRtLO7BlXB+xc9AAUV5pP6Y10Pz6uMfd+tZSW+/xGLZUlIIwQAdkFo6wBjUTPcSBPuvrsOIAbSfRbu9BoN5bKvi38fbuo9IWtwM0h/emwuI2Khhfo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567628278377261.0241452012061; Wed, 4 Sep 2019 13:17:58 -0700 (PDT) Received: from localhost ([::1]:38578 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5biv-0002d9-2n for importer@patchew.org; Wed, 04 Sep 2019 16:17:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41171) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0t-0005Uz-HH for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0r-00038q-Gk for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:19 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:36058) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0r-00033y-2a for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:17 -0400 Received: by mail-pg1-x541.google.com with SMTP id l21so11787468pgm.3 for ; Wed, 04 Sep 2019 12:32:13 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v4 56/69] target/arm: Convert T16, extract X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 14 +------------- target/arm/t16.decode | 10 ++++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 8399a2c1f6..09c05de320 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10766,21 +10766,9 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) op =3D (insn >> 8) & 0xf; switch (op) { case 0: /* add/sub (sp, immediate), in decodetree */ + case 2: /* sign/zero extend, in decodetree */ goto illegal_op; =20 - case 2: /* sign/zero extend. */ - ARCH(6); - rd =3D insn & 7; - rm =3D (insn >> 3) & 7; - tmp =3D load_reg(s, rm); - switch ((insn >> 6) & 3) { - case 0: gen_sxth(tmp); break; - case 1: gen_sxtb(tmp); break; - case 2: gen_uxth(tmp); break; - case 3: gen_uxtb(tmp); break; - } - store_reg(s, rd, tmp); - break; case 4: case 5: case 0xc: case 0xd: /* * 0b1011_x10x_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b425b86795..b5b5086e8a 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&rrr_rot !extern rd rn rm rot &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branc= hr BLX_r 0100 0111 1 .... 000 @branchr BXNS 0100 0111 0 .... 100 @branchr BLXNS 0100 0111 1 .... 100 @branchr + +# Extend + +@extend .... .... .. rm:3 rd:3 &rrr_rot rn=3D15 rot=3D0 + +SXTAH 1011 0010 00 ... ... @extend +SXTAB 1011 0010 01 ... ... @extend +UXTAH 1011 0010 10 ... ... @extend +UXTAB 1011 0010 11 ... ... @extend --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567628581; cv=none; d=zoho.com; s=zohoarc; b=TatVNX8O1L9S92rFjXepe+uTsVc5gtPCvzVgQqxyntIh1UmBO64eeRyBwYy9ZQiKCsBYNzrvYTKqn22VuIH74bJoHVltm3IEXUNRsRpOCBJCk8rbP8pIVMvDnpJhVYrN7O/rNZ75MPHdPfwNkvWh5F7rBcrpLvGhHSjVUy2m59M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567628581; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=fMRa2kGO1W6JycMdagL8+nOz15aN9a5pAkRiDJ3RJXk=; b=E/eM1LTlBgH6wB8IL8hb0ymAG9OcmEk/ishkQDVOkr09npn5vslVpHYQMoHhekSEYehpHOhB8LSQ2LnYe+gOYz85wHjNMCeb71l5BMJgAMApYeob2QWUVyq+HwUT2yRLv9/Y0I/HjtRv2PFLi7VvbRs76HdbJTs6z2xwXZpzMoQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567628581297739.5395357516749; Wed, 4 Sep 2019 13:23:01 -0700 (PDT) Received: from localhost ([::1]:38680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bnr-0008Iv-ND for importer@patchew.org; Wed, 04 Sep 2019 16:22:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41281) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0w-0005XQ-5C for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0s-00039o-4V for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:22 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:38492) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0r-00035G-MG for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:17 -0400 Received: by mail-pg1-x541.google.com with SMTP id d10so7223689pgo.5 for ; Wed, 04 Sep 2019 12:32:14 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fMRa2kGO1W6JycMdagL8+nOz15aN9a5pAkRiDJ3RJXk=; b=t9LNCLqqeK9QG+WOaFCZF8UD/ZNxAlbiKE59zZVqeg29cGvwLhpNXZ9Mk2/VZaDhIL Yk4rKljlbV+t7T/mB04uEEBWJPUjYPyUYiZTJfaFDTpFZdIpNDZQeuuRA6kRb/SNCb0C ast6nklDU97wbUjwBw6OY/gxbN1geFzoYvIX5ijd18aYNlM6NeSBJ+PNxKPR5ucTsmnh VujDO4DhgUB/VuuHNb8C4QLHI+3tuzyFOR61UqJKTxBxsEtjN/4CjJODcdC5H6s+r7MN Br5hQJA9OxydauMkXJ+5pkk3Gd4ilpWk37mnMAt7fdW8yaOeP1qqPXSBh5iF+4CDYcnL 2pUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fMRa2kGO1W6JycMdagL8+nOz15aN9a5pAkRiDJ3RJXk=; b=RXbJAUnjGlvrzk/d6wmDl98HxgLF5vj07NBYkdBKz69MIMwFtpZGWg6Yog3ftLPgJD lZzyPorR2n0ek/6TIPG3NrjMKAlfnoEaVIYNHlu06OO2NXx9SENkRKlgk8n8wwzQ+R8W 3CNeprxS++h2uY5O0a/VePLn+8jNe5eZnslw3/vG/t3De9aGcb0l+TgvsalrSjGGTyQN QK/WIh5AL6zAYplYieqTmSsqv2B0TgxGYtlRfm6kk/z7tATlXxcLQz6DzXiSI6we/NpO UoJuyMsQUWzRMlUv9iCoHUncqCAVrmrQRzWGOC66jugZayc1N4h00sFyI2PwvzAEvKiy e4+A== X-Gm-Message-State: APjAAAW9567M18ieJvp2U0AIa9PVFaa8xnPP87s1ixay2KCHAZwRCm9A NJ8MCiOYzX++wo7K+agkG7d7fGg0434= X-Google-Smtp-Source: APXvYqyD1mqj7A/UT4YyQN+pinDnU3X/x7LgvR+J9dc01QHRx2AzmcZHQdfxGmoxIUXvTPMCwL1ydA== X-Received: by 2002:a65:6557:: with SMTP id a23mr36594161pgw.439.1567625533378; Wed, 04 Sep 2019 12:32:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:47 -0700 Message-Id: <20190904193059.26202-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v4 57/69] target/arm: Convert T16, Change processor state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a check for ARMv6 in trans_CPS. We had this correct in the T16 path, but had previously forgotten the check on the A32 and T32 paths. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Fix cps architecture checks. Rename s/v6m/v7m/g --- target/arm/translate.c | 84 +++++++++++++++++++----------------------- target/arm/t16.decode | 12 ++++++ 2 files changed, 50 insertions(+), 46 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 09c05de320..ce394ddb00 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7496,6 +7496,11 @@ static int negate(DisasContext *s, int x) return -x; } =20 +static int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -10268,7 +10273,7 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) { uint32_t mask, val; =20 - if (arm_dc_feature(s, ARM_FEATURE_M)) { + if (!ENABLE_ARCH_6 || arm_dc_feature(s, ARM_FEATURE_M)) { return false; } if (IS_USER(s)) { @@ -10302,6 +10307,36 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) return true; } =20 +static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a) +{ + TCGv_i32 tmp, addr; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + + tmp =3D tcg_const_i32(a->im); + /* FAULTMASK */ + if (a->F) { + addr =3D tcg_const_i32(19); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + /* PRIMASK */ + if (a->I) { + addr =3D tcg_const_i32(16); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10908,51 +10943,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) break; } =20 - case 6: - switch ((insn >> 5) & 7) { - case 2: - /* setend */ - ARCH(6); - if (((insn >> 3) & 1) !=3D !!(s->be_data =3D=3D MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp =3D DISAS_UPDATE; - } - break; - case 3: - /* cps */ - ARCH(6); - if (IS_USER(s)) { - break; - } - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp =3D tcg_const_i32((insn & (1 << 4)) !=3D 0); - /* FAULTMASK */ - if (insn & 1) { - addr =3D tcg_const_i32(19); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - /* PRIMASK */ - if (insn & 2) { - addr =3D tcg_const_i32(16); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - } else { - if (insn & (1 << 4)) { - shift =3D CPSR_A | CPSR_I | CPSR_F; - } else { - shift =3D 0; - } - gen_set_psr_im(s, ((insn & 7) << 6), 0, shift); - } - break; - default: - goto undef; - } - break; + case 6: /* setend, cps; in decodetree */ + goto illegal_op; =20 default: goto undef; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index b5b5086e8a..032902a1f4 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -29,6 +29,8 @@ &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list +&setend !extern E +&cps !extern mode imod M A I F =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -183,3 +185,13 @@ SXTAH 1011 0010 00 ... ... @extend SXTAB 1011 0010 01 ... ... @extend UXTAH 1011 0010 10 ... ... @extend UXTAB 1011 0010 11 ... ... @extend + +# Change processor state + +%imod 4:1 !function=3Dplus_2 + +SETEND 1011 0110 010 1 E:1 000 &setend +{ + CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=3D0 M=3D0 %imod + CPS_v7m 1011 0110 011 im:1 00 I:1 F:1 +} --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PATCH v4 58/69] target/arm: Convert T16, Reverse bytes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 +++--------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 12 insertions(+), 15 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ce394ddb00..b70491d39e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10730,7 +10730,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rn, rd, shift, cond; + uint32_t val, op, rm, rd, shift, cond; int32_t offset; int i; TCGv_i32 tmp; @@ -10927,20 +10927,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) break; } =20 - /* Otherwise this is rev */ - ARCH(6); - rn =3D (insn >> 3) & 0x7; - rd =3D insn & 0x7; - tmp =3D load_reg(s, rn); - switch (op1) { - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp, tmp); break; - case 3: gen_revsh(tmp, tmp); break; - default: - g_assert_not_reached(); - } - store_reg(s, rd, tmp); - break; + /* Otherwise this is rev, in decodetree */ + goto illegal_op; } =20 case 6: /* setend, cps; in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 032902a1f4..19a442b894 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrr_rot !extern rd rn rm rot +&rr !extern rd rm &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -195,3 +196,11 @@ SETEND 1011 0110 010 1 E:1 000 &setend CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=3D0 M=3D0 %imod CPS_v7m 1011 0110 011 im:1 00 I:1 F:1 } + +# Reverse bytes + +@rdm .... .... .. rm:3 rd:3 &rr + +REV 1011 1010 00 ... ... @rdm +REV16 1011 1010 01 ... ... @rdm +REVSH 1011 1010 11 ... ... @rdm --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH v4 59/69] target/arm: Convert T16, nop hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate.c | 3 +-- target/arm/t16.decode | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b70491d39e..69092c12c3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10891,8 +10891,7 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) =20 case 15: /* IT, nop-hint. */ if ((insn & 0xf) =3D=3D 0) { - gen_nop_hint(s, (insn >> 4) & 0xf); - break; + goto illegal_op; /* nop hint, in decodetree */ } /* * IT (If-Then) diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 19a442b894..5829b9a58c 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # =20 +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -204,3 +205,19 @@ SETEND 1011 0110 010 1 E:1 000 &setend REV 1011 1010 00 ... ... @rdm REV16 1011 1010 01 ... ... @rdm REVSH 1011 1010 11 ... ... @rdm + +# Hints + +{ + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 + + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 +} --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567628535; cv=none; d=zoho.com; s=zohoarc; b=JRujlNjh8Q75hATYqhS41sqmgNdYbtq+PazKG46eJq9VrQ8Q4prNQM4RrCKNFcoiQZGEVJy88y4pTqN1RCIicU52KCtp3LkHnfmxDBpOMNWn1WQ1MAGP7M2FupBCT5Ki9IPm83hn+09xaA365DBTkTM97mmy0vW925TSpTw8ahM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567628535; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=QO3IBs61SUEB1dyssLo6yzRJXGICvl8lJuuHe5SABa4=; b=WKu8x66GyEeODQNE4oi9lCiecFFImixWJbdy14AqU0quWKFAIwoVF3vr+4snFgd3G4L+SpUhY7yMmImovA5EGFYWEauQWuO3peResbbgkD5Sa4x5khkFlF3rWL05nsWAG2aHxJy+q9IgBeIKD//LzJ1zbSc4wwyqUYawb/Tcr0c= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567628535384583.3632706557103; Wed, 4 Sep 2019 13:22:15 -0700 (PDT) Received: from localhost ([::1]:38672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bn7-0007Kr-US for importer@patchew.org; Wed, 04 Sep 2019 16:22:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41299) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0x-0005Ys-5p for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0t-0003B8-15 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:22 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:39060) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0s-00039G-GB for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:18 -0400 Received: by mail-pl1-x641.google.com with SMTP id bd8so3713619plb.6 for ; Wed, 04 Sep 2019 12:32:18 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QO3IBs61SUEB1dyssLo6yzRJXGICvl8lJuuHe5SABa4=; b=nKLxRsbD9qVwU7AV2bUR2h5Flog47pBDBLggJR/s4mautgkbdP7gh3jngNlkJDF4I0 gK3CB9GvbaAvnfHoujqVwMEEU63KNcI50Ty9Q+Dwy4ismaU9WbL4erabtcjtzjbrHRLW TLBVQvPuYH/oDnAsOoa8ARU8jBak+bSmQbJiPbLx70mw8QN0qBJUwYQ1MVvHxUESGhrR 0FzL6WYcBAnq6d73Ypc+kkkYV5ASNqPg4JyuEcS7V+QJ3ePgTlNjVzd45QskXg80uq2x m1q8kQ45CYcOxmNhoRqsX/xyTOYLhqVhu9e1C5vbyUOLlM/YDQW4WHEAdRm3Opd3/k1Q sl6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QO3IBs61SUEB1dyssLo6yzRJXGICvl8lJuuHe5SABa4=; b=Q5JKsnQAUIF3xjsuSJZERf38u2GpvfszVne+raByBuHQKlZHE0l667+CPrq3g8pLHE 72VT/D0IE8aqDcP4DuKIPqNyZwOVvlUaUKbbe79EueD2SlN6Xcv1pF1A3vu10/PDaSqV 3lKb/of5WlualTIVRFInprV/DjS4mDsjyWbQ/U5K8gpJZPQ3PPla9UpD9mnHOQ6YFiB0 76woEypkZRn4RQbIXaxOLHQckSllrd9+7DApdU0soiFgU9Zo3zRmMv6ECpmjJtU2iIPu exvSjf4OnGuV48PHjwwH+VouoO9/4QYAtFcHlRyfNRmSN1M9KYIuM+bhZAPIOZkqL3cg uC6w== X-Gm-Message-State: APjAAAU9+VITpgR6lYK4LUqwM7gTq6BQ3KTDXgYz1BXNroxvTlIlz2QF p0b5j1m8+Map2vw/q0RP/X7Ms/kd2is= X-Google-Smtp-Source: APXvYqyh+UJy/tO+k6FJ1Kn/ThVhBjk35MFpIp/M4lwmBno2tRRuPBvFXZakRY4mXlcdQaM+bEmwmA== X-Received: by 2002:a17:902:848c:: with SMTP id c12mr42247324plo.47.1567625537068; Wed, 04 Sep 2019 12:32:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:50 -0700 Message-Id: <20190904193059.26202-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v4 60/69] target/arm: Split gen_nop_hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that all callers pass a constant value, split the switch statement into the individual trans_* functions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 67 +++++++++++++++--------------------------- 1 file changed, 24 insertions(+), 43 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 69092c12c3..d076c962ea 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3061,46 +3061,6 @@ static void gen_exception_return(DisasContext *s, TC= Gv_i32 pc) gen_rfe(s, pc, load_cpu_field(spsr)); } =20 -/* - * For WFI we will halt the vCPU until an IRQ. For WFE and YIELD we - * only call the helper when running single threaded TCG code to ensure - * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we - * just skip this instruction. Currently the SEV/SEVL instructions - * which are *one* of many ways to wake the CPU from WFE are not - * implemented so we can't sleep like WFI does. - */ -static void gen_nop_hint(DisasContext *s, int val) -{ - switch (val) { - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - case 1: /* yield */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp =3D DISAS_YIELD; - } - break; - case 3: /* wfi */ - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp =3D DISAS_WFI; - break; - case 2: /* wfe */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_set_pc_im(s, s->base.pc_next); - s->base.is_jmp =3D DISAS_WFE; - } - break; - case 4: /* sev */ - case 5: /* sevl */ - /* TODO: Implement SEV, SEVL and WFE. May help SMP performance. = */ - default: /* nop */ - break; - } -} - #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 =20 static inline void gen_neon_add(int size, TCGv_i32 t0, TCGv_i32 t1) @@ -8194,19 +8154,40 @@ DO_SMLAWX(SMLAWT, 1, 1) =20 static bool trans_YIELD(DisasContext *s, arg_YIELD *a) { - gen_nop_hint(s, 1); + /* + * When running single-threaded TCG code, use the helper to ensure that + * the next round-robin scheduled vCPU gets a crack. When running in + * MTTCG we don't generate jumps to the helper as it won't affect the + * scheduling of other vCPUs. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp =3D DISAS_YIELD; + } return true; } =20 static bool trans_WFE(DisasContext *s, arg_WFE *a) { - gen_nop_hint(s, 2); + /* + * When running single-threaded TCG code, use the helper to ensure that + * the next round-robin scheduled vCPU gets a crack. In MTTCG mode we + * just skip this instruction. Currently the SEV/SEVL instructions, + * which are *one* of many ways to wake the CPU from WFE, are not + * implemented so we can't sleep like WFI does. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp =3D DISAS_WFE; + } return true; } =20 static bool trans_WFI(DisasContext *s, arg_WFI *a) { - gen_nop_hint(s, 3); + /* For WFI, halt the vCPU until an IRQ. */ + gen_set_pc_im(s, s->base.pc_next); + s->base.is_jmp =3D DISAS_WFI; return true; } =20 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567629169; cv=none; d=zoho.com; s=zohoarc; b=k9ONmSagueAW8kt0a+GGbHnjbr1DXBZM5t2W0RDzkP9p7yFCtHiGCmZzHXhkTsd9ziu3nnx6LVLRztd54DNhrsI6JA1+s2yDvPKE6Jcub4Kj8VsZyH7vGIBK89pVTeL3DmDVdMQkd7vI2Uugy3ylq+ro+nXCEy5ZdzDqq0qIMNE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567629169; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=dXwskgwxwGoHO9g80cjucHpMD4vJQ5Oi2of0il2UAv8=; b=J27IQLiS1SGo0WpE1ZOzkHJgMwyBXa0F0Aw5Po4kA+Sl0x5lRvND4yAt6KA3BDt6i8rJtHQ6OG0oWZbOJGJTYDxG9a36CxPB78BASqYnvBv3iqVNyOgBJ+7zNJor/riVGxpvRC4FcCdvuua9AnAISUbY+gfRdnNe2EPi7C3FdbA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567629168977161.10599404027028; Wed, 4 Sep 2019 13:32:48 -0700 (PDT) Received: from localhost ([::1]:38948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bxP-0000I2-0y for importer@patchew.org; Wed, 04 Sep 2019 16:32:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41350) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0z-0005Zf-1R for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0u-0003Cx-ED for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:24 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:34491) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0u-0003BL-0r for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:20 -0400 Received: by mail-pl1-x629.google.com with SMTP id d3so16962plr.1 for ; Wed, 04 Sep 2019 12:32:19 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dXwskgwxwGoHO9g80cjucHpMD4vJQ5Oi2of0il2UAv8=; b=awDsgTvBw3Jo2mOzDrNg6vw8t7K3zMt9+omHocXqlpvz1LDWzx+/hivJY7mraY0F+3 aaTLno6CnSb8ZDrzozteHVYDdjmEF3mngBoSEnD5Y6sfZui3o57ptfByylfTNd6SNr18 6MiExsuyY35uOc303YDN+Ck5x0h/ZheJhSNoyLBgL1gTyGQMY4/jIy7RqGPcDn0Szwrd 6cMKS/w3Mi4iKwfkWOobSbus1RfTHKNIpqq/CXk55A9HGVbyy4S6bwliF1I5MTEl8Sdp oVV5ZGpbcymkXgMueLXMMznFDZWBU42n5W9R/ScgM1FnBHbn88Mm+clIKwl2c/XeI4Rg fvfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dXwskgwxwGoHO9g80cjucHpMD4vJQ5Oi2of0il2UAv8=; b=BbQQbHKalcr8ERZHErdIJyvvSWEPx7cQ8gtOZ9OuobPQHcflMR1TEp6JD+WQYyJ9ax dRLTqzmxJGGUedxTwZRLxpWgVW+6pGrPDP47Dg5cY3ESo9/QttA4Ni48ZBUIoLqVD+kO fVMMMGFcj59TprYjkyzPGNN4FcsM38D3vlJgzte+kGFNwAoaEYrz0J7Ut1C/+elluvvf OhTtrZAe1xppdYiJg7CmVfNH/l9qSZ0VdbT1ZoOtqGBfUBlbrXaj+8f0yyNLG3r2jB7Y bBwJN1BxmZh9ar00LnNKW6H3Tyh9pWTsYcYEU6K5Bdnhkr1we27L+P6XJVjJJ/mkRoP8 VFtQ== X-Gm-Message-State: APjAAAWL/E5pxJ/jST8OOdkK1/ahcMXHKzpBq1Xm31zmG+XQwr2wel5k ru7qRi8Ua8tYSiK1G7frOnYphLNWEMg= X-Google-Smtp-Source: APXvYqwqJqRIXhoj1WZFQVgzVBLoVbWqC4QjvnEo9Zeq0y4WMdXqdY9fvTj0tCq/NTvuNBbdnN2PJg== X-Received: by 2002:a17:902:5e1:: with SMTP id f88mr13079569plf.1.1567625538333; Wed, 04 Sep 2019 12:32:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:51 -0700 Message-Id: <20190904193059.26202-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::629 Subject: [Qemu-devel] [PATCH v4 61/69] target/arm: Convert T16, push and pop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 83 ++++++------------------------------------ target/arm/t16.decode | 10 +++++ 2 files changed, 22 insertions(+), 71 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d076c962ea..ed52018c17 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7516,6 +7516,16 @@ static int t16_setflags(DisasContext *s) return s->condexec_mask =3D=3D 0; } =20 +static int t16_push_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (14 - 8); +} + +static int t16_pop_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (15 - 8); +} + /* * Include the generated decoders. */ @@ -10713,7 +10723,6 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) { uint32_t val, op, rm, rd, shift, cond; int32_t offset; - int i; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10786,76 +10795,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; =20 case 4: case 5: case 0xc: case 0xd: - /* - * 0b1011_x10x_xxxx_xxxx - * - push/pop - */ - addr =3D load_reg(s, 13); - if (insn & (1 << 8)) - offset =3D 4; - else - offset =3D 0; - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) - offset +=3D 4; - } - if ((insn & (1 << 11)) =3D=3D 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck) { - /* - * Here 'addr' is the lower of "old SP" and "new SP"; - * if this is a pop that starts below the limit and ends - * above it, it is UNKNOWN whether the limit check trigger= s; - * we choose to trigger. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - for (i =3D 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* pop */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, i, tmp); - } else { - /* push */ - tmp =3D load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address. */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - tmp =3D NULL; - if (insn & (1 << 8)) { - if (insn & (1 << 11)) { - /* pop pc */ - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - /* don't set the pc until the rest of the instruction - has completed */ - } else { - /* push lr */ - tmp =3D load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if ((insn & (1 << 11)) =3D=3D 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* write back the new stack pointer */ - store_reg(s, 13, addr); - /* set the new PC value */ - if ((insn & 0x0900) =3D=3D 0x0900) { - store_reg_from_load(s, 15, tmp); - } - break; + /* push/pop, in decodetree */ + goto illegal_op; =20 case 1: case 3: case 9: case 11: /* czb */ rm =3D insn & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 5829b9a58c..55fadce223 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -221,3 +221,13 @@ REVSH 1011 1010 11 ... ... @rdm # rest of the space is a reserved hint, behaves as nop. NOP 1011 1111 ---- 0000 } + +# Push and Pop + +%push_list 0:9 !function=3Dt16_push_list +%pop_list 0:9 !function=3Dt16_pop_list + +STM 1011 010 ......... \ + &ldst_block i=3D0 b=3D1 u=3D0 w=3D1 rn=3D13 list=3D%push_l= ist +LDM_t16 1011 110 ......... \ + &ldst_block i=3D1 b=3D0 u=3D0 w=3D1 rn=3D13 list=3D%pop_li= st --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567629354; cv=none; d=zoho.com; s=zohoarc; b=kL9PEZQXhxwLW2aaw9TMIxX6Q6w9gLacV6n75GR8T9iY1UAswE+89OH4pzYdIn18KX48pSJKvX5G/cg87BFydulrRbWzr/wBkmLKJXCcTsZ5IrbsYK9NzLbVTPG3gF7wjl/GJhfl3HlRRmysbKuniGCJBehKm3Dpqy2GTBNXoMg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567629354; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=852c/awIgTh3C7GCCijbpsvu4SQYTMvdpB+Gb73lAXI=; b=nTgPcYQFZR5AYr3bMHeGRZ37wKBdInAhTuu5v3+RHsFegF58RLjqaYRgsPO0japf/4WfPwFzT5KDUEiUhCl1/y7MNjKnpB7WeWbChy6SivltOo76DwgvEOQ7J9qRfPks/1hPo2JM4Jft807FEszchMIc/TGnnTPe5mJQEOzySJ8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567629354799528.0065523676942; Wed, 4 Sep 2019 13:35:54 -0700 (PDT) Received: from localhost ([::1]:39032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5c0P-0003tS-FE for importer@patchew.org; Wed, 04 Sep 2019 16:35:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41351) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b0z-0005Zh-0F for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b0v-0003Dv-GN for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:24 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:38494) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b0u-0003Co-V2 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:21 -0400 Received: by mail-pg1-x543.google.com with SMTP id d10so7223853pgo.5 for ; Wed, 04 Sep 2019 12:32:20 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 62/69] target/arm: Convert T16, Conditional branches, Supervisor call X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 +++----------------------- target/arm/t16.decode | 12 ++++++++++++ 2 files changed, 15 insertions(+), 23 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ed52018c17..a4844992d5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10721,7 +10721,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift, cond; + uint32_t val, op, rm, rd, shift; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10860,28 +10860,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) } break; =20 - case 13: - /* conditional branch or swi */ - cond =3D (insn >> 8) & 0xf; - if (cond =3D=3D 0xe) - goto undef; - - if (cond =3D=3D 0xf) { - /* swi */ - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm =3D extract32(insn, 0, 8); - s->base.is_jmp =3D DISAS_SWI; - break; - } - /* generate a conditional jump to next instruction */ - arm_skip_unless(s, cond); - - /* jump to the offset */ - val =3D read_pc(s); - offset =3D ((int32_t)insn << 24) >> 24; - val +=3D offset << 1; - gen_jmp(s, val); - break; + case 13: /* conditional branch or swi, in decodetree */ + goto illegal_op; =20 case 14: if (insn & (1 << 11)) { diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 55fadce223..cbc64f4e48 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -28,11 +28,13 @@ &rr !extern rd rm &ri !extern rd imm &r !extern rm +&i !extern imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list &setend !extern E &cps !extern mode imod M A I F +&ci !extern cond imm =20 # Set S if the instruction is outside of an IT block. %s !function=3Dt16_setflags @@ -231,3 +233,13 @@ STM 1011 010 ......... \ &ldst_block i=3D0 b=3D1 u=3D0 w=3D1 rn=3D13 list=3D%push_l= ist LDM_t16 1011 110 ......... \ &ldst_block i=3D1 b=3D0 u=3D0 w=3D1 rn=3D13 list=3D%pop_li= st + +# Conditional branches, Supervisor call + +%imm8_0x2 0:s8 !function=3Dtimes_2 + +{ + UDF 1101 1110 ---- ---- + SVC 1101 1111 imm:8 &i + B_cond_thumb 1101 cond:4 ........ &ci imm=3D%imm8_0x2 +} --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::536 Subject: [Qemu-devel] [PATCH v4 63/69] target/arm: Convert T16, Miscellaneous 16-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Split firstcond & mask within trans_IT. --- target/arm/translate.c | 111 +++++++++++++---------------------------- target/arm/t16.decode | 29 +++++++---- 2 files changed, 54 insertions(+), 86 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a4844992d5..48ed6f6b5d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10196,6 +10196,18 @@ static bool trans_TBH(DisasContext *s, arg_tbranch= *a) return op_tbranch(s, a, true); } =20 +static bool trans_CBZ(DisasContext *s, arg_CBZ *a) +{ + TCGv_i32 tmp =3D load_reg(s, a->rn); + + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, + tmp, 0, s->condlabel); + tcg_temp_free_i32(tmp); + gen_jmp(s, read_pc(s) + a->imm); + return true; +} + /* * Supervisor call */ @@ -10417,6 +10429,27 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) return ENABLE_ARCH_7; } =20 +/* + * If-then + */ + +static bool trans_IT(DisasContext *s, arg_IT *a) +{ + int cond_mask =3D a->cond_mask; + + /* + * No actual code generated for this insn, just setup state. + * + * Combinations of firstcond and mask which set up an 0b1111 + * condition are UNPREDICTABLE; we take the CONSTRAINED + * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, + * i.e. both meaning "execute always". + */ + s->condexec_cond =3D (cond_mask >> 4) & 0xe; + s->condexec_mask =3D cond_mask & 0x1f; + return true; +} + /* * Legacy decoder. */ @@ -10783,83 +10816,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ - goto illegal_op; - - case 11: - /* misc */ - op =3D (insn >> 8) & 0xf; - switch (op) { - case 0: /* add/sub (sp, immediate), in decodetree */ - case 2: /* sign/zero extend, in decodetree */ - goto illegal_op; - - case 4: case 5: case 0xc: case 0xd: - /* push/pop, in decodetree */ - goto illegal_op; - - case 1: case 3: case 9: case 11: /* czb */ - rm =3D insn & 7; - tmp =3D load_reg(s, rm); - arm_gen_condlabel(s); - if (insn & (1 << 11)) - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); - else - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); - tcg_temp_free_i32(tmp); - offset =3D ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; - gen_jmp(s, read_pc(s) + offset); - break; - - case 15: /* IT, nop-hint. */ - if ((insn & 0xf) =3D=3D 0) { - goto illegal_op; /* nop hint, in decodetree */ - } - /* - * IT (If-Then) - * - * Combinations of firstcond and mask which set up an 0b1111 - * condition are UNPREDICTABLE; we take the CONSTRAINED - * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, - * i.e. both meaning "execute always". - */ - s->condexec_cond =3D (insn >> 4) & 0xe; - s->condexec_mask =3D insn & 0x1f; - /* No actual code generated for this insn, just setup state. = */ - break; - - case 0xe: /* bkpt */ - { - int imm8 =3D extract32(insn, 0, 8); - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); - break; - } - - case 0xa: /* rev, and hlt */ - { - int op1 =3D extract32(insn, 6, 2); - - if (op1 =3D=3D 2) { - /* HLT */ - int imm6 =3D extract32(insn, 0, 6); - - gen_hlt(s, imm6); - break; - } - - /* Otherwise this is rev, in decodetree */ - goto illegal_op; - } - - case 6: /* setend, cps; in decodetree */ - goto illegal_op; - - default: - goto undef; - } - break; - case 13: /* conditional branch or swi, in decodetree */ goto illegal_op; =20 @@ -10915,7 +10873,6 @@ static void disas_thumb_insn(DisasContext *s, uint3= 2_t insn) } return; illegal_op: -undef: unallocated_encoding(s); } =20 diff --git a/target/arm/t16.decode b/target/arm/t16.decode index cbc64f4e48..f128110dee 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -211,19 +211,30 @@ REVSH 1011 1010 11 ... ... @rdm # Hints =20 { - YIELD 1011 1111 0001 0000 - WFE 1011 1111 0010 0000 - WFI 1011 1111 0011 0000 + { + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1011 1111 0100 0000 - # SEVL 1011 1111 0101 0000 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 =20 - # The canonical nop has the second nibble as 0000, but the whole of the - # rest of the space is a reserved hint, behaves as nop. - NOP 1011 1111 ---- 0000 + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 + } + IT 1011 1111 cond_mask:8 } =20 +# Miscellaneous 16-bit instructions + +%imm6_9_3 9:1 3:5 !function=3Dtimes_2 + +HLT 1011 1010 10 imm:6 &i +BKPT 1011 1110 imm:8 &i +CBZ 1011 nz:1 0.1 ..... rn:3 imm=3D%imm6_9_3 + # Push and Pop =20 %push_list 0:9 !function=3Dt16_push_list --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 64/69] target/arm: Convert T16, shift immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 8 ++++++++ 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 48ed6f6b5d..d409afd55f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10754,7 +10754,7 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift; + uint32_t val, rd; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10766,29 +10766,7 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) /* fall back to legacy decoder */ =20 switch (insn >> 12) { - case 0: case 1: - - rd =3D insn & 7; - op =3D (insn >> 11) & 3; - if (op =3D=3D 3) { - /* - * 0b0001_1xxx_xxxx_xxxx - * - Add, subtract (three low registers) - * - Add, subtract (two low registers and immediate) - * In decodetree. - */ - goto illegal_op; - } else { - /* shift immediate */ - rm =3D (insn >> 3) & 7; - shift =3D (insn >> 6) & 0x1f; - tmp =3D load_reg(s, rm); - gen_arm_shift_im(tmp, op, shift, s->condexec_mask =3D=3D 0); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } - break; + case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree = */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ goto illegal_op; case 4: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index f128110dee..79a1d66d6c 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm =20 +# Shift (immediate) + +@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=3D%reg_0 + +MOV_rxri 000 00 ..... ... ... @shift_i shty=3D0 # LSL +MOV_rxri 000 01 ..... ... ... @shift_i shty=3D1 # LSR +MOV_rxri 000 10 ..... ... ... @shift_i shty=3D2 # ASR + # Add/subtract (three low registers) =20 @addsub_3 ....... rm:3 rn:3 rd:3 \ --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VYZV/zdp2JerFG4ZPo6G3uzAjb1Br+I2f89wbKWVC8A=; b=V/9uNM7qgsoR3NIi+cKH/0++FBpIoU7LmUYFtCBnsCivHLFAoFyZvz8Xi9t13wXIOo zk5QT+QED/Gi12rPWf8pk1t+RDrb4Z5jdKeTDrbCxjKHAB5APwkudCtjk/7mbsbL+9TS hovgJo/08r60d46E2eQA53GE9ILADG1Ua8GlfkSbPlIxfj94g1olSsXbejOJKcCoGm50 nOydBviW8XZCkhZnQUIIQ8cBHP8fyOQhe79qGfj/8KNek5mZqJTFezL7A6Othtp7Ci/2 QeJEe2WV383jfgWUQQKvCaKvxqHxmGimlLfM3g2FmLrkyOdH/YUT+m77bwufpDuotqBu 8pYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VYZV/zdp2JerFG4ZPo6G3uzAjb1Br+I2f89wbKWVC8A=; b=W1srCzv3J0LlDMUdS3IAkGBO4eTEh+7d7a7DbiOz839zzpaG7P069EVCzZW5fhuqDO yKODmSN0Wv8ED/dXIDQvlRDjflopP0T4lfB30zLwv23+5Iva1smd/GN5+idCny9X4xEA TW8prSx21MZ/ziKamI/ySH/WvNjw8lORp+TlLEYlqq7jpvx6Sls9OHpq3xcsahwhwiw7 pwJvNy1UOqmUzNR00cWZG22L9KI9yzgHmx6zrJfP1/OMB49Fm51cTuDurKhhGwcxTYWw BSSIAb3TPRLoKcLeZ66nykk1ebWSkk5/BWTHeRqveyY1WF9sTO6+PTm2CeVEYowVXuuI JwFw== X-Gm-Message-State: APjAAAVt8DwoPYe1HIC7CoDGud7Rz6NgdH+obb00VzqrTKJcE1Ovbj2E WoS7GieC1lA8jra4fR97bGl0l0vIoCg= X-Google-Smtp-Source: APXvYqySDzkV5npXSlDRhOHpZ05cCNarJctNDMRf4t/NRtUTQAbT5HSqFfm1xpBSR7RpPKKAd0VIOw== X-Received: by 2002:a62:e802:: with SMTP id c2mr12575057pfi.212.1567625543381; Wed, 04 Sep 2019 12:32:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:55 -0700 Message-Id: <20190904193059.26202-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v4 65/69] target/arm: Convert T16, load (literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 42 ++---------------------------------------- target/arm/t16.decode | 4 ++++ 2 files changed, 6 insertions(+), 40 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index d409afd55f..4f4c77fc89 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -982,14 +982,6 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, = TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_ld##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo); \ } =20 #define DO_GEN_ST(SUFF, OPC) \ @@ -997,14 +989,6 @@ static inline void gen_aa32_st##SUFF(DisasContext *s, = TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_st##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \ } =20 static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) @@ -1053,9 +1037,7 @@ static inline void gen_aa32_st64(DisasContext *s, TCG= v_i64 val, gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data); } =20 -DO_GEN_LD(8s, MO_SB) DO_GEN_LD(8u, MO_UB) -DO_GEN_LD(16s, MO_SW) DO_GEN_LD(16u, MO_UW) DO_GEN_LD(32u, MO_UL) DO_GEN_ST(8, MO_UB) @@ -10754,11 +10736,10 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, rd; + uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 addr; =20 if (disas_t16(s, insn)) { return; @@ -10768,26 +10749,7 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) switch (insn >> 12) { case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree = */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - goto illegal_op; - case 4: - if (insn & (1 << 11)) { - rd =3D (insn >> 8) & 7; - /* load pc-relative. Bit 1 of PC is ignored. */ - addr =3D add_reg_for_lit(s, 15, (insn & 0xff) * 4); - tmp =3D tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), - rd | ISSIs16Bit); - tcg_temp_free_i32(addr); - store_reg(s, rd, tmp); - break; - } - - /* - * - Data-processing (two low registers), in decodetree - * - data processing extended, branch and exchange, in decodetree - */ - goto illegal_op; - + case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree= */ case 5: /* load/store register offset, in decodetree */ case 6: /* load/store word immediate offset, in decodetree */ case 7: /* load/store byte immediate offset, in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 79a1d66d6c..0b4da411e0 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -113,6 +113,10 @@ LDRH_ri 10001 ..... ... ... @ldst_= ri_2 STR_ri 10010 ... ........ @ldst_spec_i rn=3D13 LDR_ri 10011 ... ........ @ldst_spec_i rn=3D13 =20 +# Load (PC-relative) + +LDR_ri 01001 ... ........ @ldst_spec_i rn=3D15 + # Add PC/SP (immediate) =20 ADR 10100 rd:3 ........ imm=3D%imm8_0x4 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567629497; cv=none; d=zoho.com; s=zohoarc; b=DcKjm03TE/TeOcCu703paWAFzpL1j+BPhscS6EH+UvVLFY7NcVb1psXvGrZNbYECq3fGZUvDk84tsGGcRihJRmiBC6O5p/OlOTO4X92QESoB+lfaf5GEG1xEHPCbEMd1CzbA/Hekj5WMlwzvjqQkc43dzYCFswSuxJEm+OwSnhw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567629497; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=ubjb98obYB0wcr0PkhZrvGjTKBKP700KuYx4LrhjRCk=; b=mYCfuw02C+2FZdvZwSl1e7cFRGHc7rVIgixSolIRS8F07ue2Loi8b41m/fPEjm9F1zPZYqripEUG7IAm0keEyZkM/c1316XlMLLyCDiUl67Ze3JmhOYuSt3kSvZZR48aahtLmKMqN4JlSY3ZvdCOV83KaOdzJ+TJCXUCp862x5g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567629497222785.6702346912439; Wed, 4 Sep 2019 13:38:17 -0700 (PDT) Received: from localhost ([::1]:39084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5c2f-00079m-Aa for importer@patchew.org; Wed, 04 Sep 2019 16:38:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41501) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b15-0005dr-Bp for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b13-0003N7-BP for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:30 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:44811) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b11-0003J3-9w for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:29 -0400 Received: by mail-pf1-x435.google.com with SMTP id q21so8881001pfn.11 for ; Wed, 04 Sep 2019 12:32:26 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ubjb98obYB0wcr0PkhZrvGjTKBKP700KuYx4LrhjRCk=; b=fnGC5dr5sDsjett47yIJEN9Of0JrUcyoeppmr5Qh4LB6cNBWhsckqvU5cTE8lpAHEx r8Ih/AEiuDrykNM3qjQWxFWR+jjJaLlsjxe9mg1TpwaVsT+RnZl9huleOuQSAG835P79 d/C2lrMy6NecLtog9sLd5wE6f7q4Gn2O/7ukzRdFtk7Fv54Pts+pFWsnar2VZ0ESCn1Y hei9Pgi0PcyBK4QHejEVrCVuOs+5re1vjz8E42CHCLQRvE7jXnBOvgH1sISdNxGI6hyw TcS9ct4nuGS6ZuqPUww/QbokyjRXMtnjhQ7/Z1CxLsP5FXm73LahSLKzsgvasxXST37I U79g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ubjb98obYB0wcr0PkhZrvGjTKBKP700KuYx4LrhjRCk=; b=dqXP83yZQKTgevfEVDVVHHCUElCN+ZpJ11Y8EyOlWsL6+xQe1CDrcQGsQ11sGe2RYI VGA8VPtSJBLI6JvrH5TVdLAFe914m1oOKxvaiu0xnAgsBIh378snfv+v7uecTr/qqNhA Fum5j2aS/MYEuQZxA2KGvNzzVAmB669pbCKtRXmIkJ0qZamZqdHuCu4kAcozsetIkWF2 hreKiaINWdLE9R72Ri0l+Bx5KnIMHa5JnuzocdjdqddJoy6vMl4PRpRfSYP6d0O5m+Cj /M4weMCraVyeCerSHmae9uz6ZpwoGE83Olyhgc3qIGL3n0RU89vJjR5nDWe6U08ytJCI lABg== X-Gm-Message-State: APjAAAUepV2WpSrHkJLKF24Ysdex7ZBg+d5jtTe+hTFteq+g/ykGW0RW qXVRaDwW3mDBzcBbTEcUOGCmN7MJ2Zo= X-Google-Smtp-Source: APXvYqzUkpyiUrSHb6gzJRa9DtGOUg+tXICQVH0ofPcFhNpasc+qZOnqsyYZkf3F2t5yIjU3dZ6YVQ== X-Received: by 2002:a63:6f8f:: with SMTP id k137mr36325209pgc.90.1567625544802; Wed, 04 Sep 2019 12:32:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:56 -0700 Message-Id: <20190904193059.26202-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::435 Subject: [Qemu-devel] [PATCH v4 66/69] target/arm: Convert T16, Unconditional branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 ++------- target/arm/t16.decode | 6 ++++++ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4f4c77fc89..3238ccbf1e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10736,7 +10736,6 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10780,12 +10779,8 @@ static void disas_thumb_insn(DisasContext *s, uint= 32_t insn) gen_bx(s, tmp); break; } - /* unconditional branch */ - val =3D read_pc(s); - offset =3D ((int32_t)insn << 21) >> 21; - val +=3D offset << 1; - gen_jmp(s, val); - break; + /* unconditional branch, in decodetree */ + goto illegal_op; =20 case 15: /* thumb_insn_is_16bit() ensures we can't get here for diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 0b4da411e0..a4c89dba61 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -266,3 +266,9 @@ LDM_t16 1011 110 ......... \ SVC 1101 1111 imm:8 &i B_cond_thumb 1101 cond:4 ........ &ci imm=3D%imm8_0x2 } + +# Unconditional Branch + +%imm11_0x2 0:s11 !function=3Dtimes_2 + +B 11100 ........... &i imm=3D%imm11_0x2 --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567629106; cv=none; d=zoho.com; s=zohoarc; b=eUebRfHerhXVpEkRZXxQYnHoIG87YpyCidBfGNWXmsS1Zy0f7+sjrI0wmixo9BDMiw3YBiXOUY85/IJKom3VXvcHZsj+d7AyHmW/TLFDovpZ9KRo2gVVYb+dZP/+DOXTKqkD6Jl44PUqFg8WnCLT7ivpCzQfYVgEO1on7k9FmjE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567629106; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=HzFCgBINrkpo6Knja84cWCi2ubxaaPHPuYIHOK9s5JA=; b=SVWFrnD13gmq9/T66JbL51nkqB8wdHqk2P69jbRidRhvdnXBEQt6PGJq9L7VWpQxJ5zIqBbT/LxaX3MsV2V2ySdeDg7hgVpjwZoAWK1S8CMu7sR92VWk2fwU8g4z35NmYpkSKEsu+oKXEYubaI90N+iSSrv/h6STQ56OQ1tVZm0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15676291069665.167113109242905; Wed, 4 Sep 2019 13:31:46 -0700 (PDT) Received: from localhost ([::1]:38936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bwO-0008No-Pe for importer@patchew.org; Wed, 04 Sep 2019 16:31:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41525) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b17-0005eK-7T for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b14-0003OB-Fq for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:33 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:41331) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b11-0003Jo-A9 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:29 -0400 Received: by mail-pf1-x42d.google.com with SMTP id b13so7279017pfo.8 for ; Wed, 04 Sep 2019 12:32:27 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HzFCgBINrkpo6Knja84cWCi2ubxaaPHPuYIHOK9s5JA=; b=hUyxOfkyN8Z62KoAleLdJhBgHVDl4tlq7e0FQnUh83gjLqB0DXtswvQliWDEXlb+b/ 6tYgCmMquW0xHO4S1/TK7OXi0/vf2uEZY6WGM5It6sBad2uQm2m7YF5mwFOFp9Vw4ta0 mHue6gVV2k4I37B8w4SHawvZ27fednISIO43vOoKfJ7kEBIM8xfO8iy/0e88pbu3W+yC CCxrK8XH4+IMDkWYGX1Q+l1JG7T0nuA3cJP63Mkzro4XMeyUkYQKYq/eJmnVsLHd6lvc vXyiXSGyurO3+jWuT4Xxogjc9QDf9f4DLNWlebiE78/o/sxjgwZieroOFhiadxH31gzB E3Bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HzFCgBINrkpo6Knja84cWCi2ubxaaPHPuYIHOK9s5JA=; b=Lew/XT4bBY6Lca3GoKq98junB08+7ctFaNqHv1us9rKrihOPcdRolkhYKXjIU3RLnB wnG47iA9VCHycOqnvd/iFNlQktQSV4v6nOQG8MFadmo8KiZKivT2tZcLrRG4loBJ0tYv 2YtZJlfoF+ByE0Ux0wd/g/Rki4iLY4wFAtDI3zu6UxbFMkoe9VBQwMByeRYvVRDFhmWY xzhKP2RA1frKdOToAHqAhUVOSVpWBMhrLEq3NwniUh8tjHtVlzT7W2JmiBoszSpTOQfN McdKKbfwQ+Btp/DcPtI2Ez4LGhgR8TqJ/ZIvrkVA+yPQi50rhJ2nRlCJIJHRcsUF+Ypw Ld/w== X-Gm-Message-State: APjAAAWXUeFPA69w/thT4h7fG1jX7q3eOD5HzVhnMSCetC9+dDf4AvED 56f26smDWq3ggjbRpayvKh/8f7t8PvI= X-Google-Smtp-Source: APXvYqwzkChEJsuBeNVZXdBbk+R8/f1VRqzqqd2ey1e2iQX3J8sh34wrxor4+Z4CM41fUIk9IsrCfg== X-Received: by 2002:a62:d143:: with SMTP id t3mr44324988pfl.213.1567625545880; Wed, 04 Sep 2019 12:32:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:57 -0700 Message-Id: <20190904193059.26202-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42d Subject: [Qemu-devel] [PATCH v4 67/69] target/arm: Convert T16, long branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 85 ++++++++++++++++++------------------------ target/arm/t16.decode | 7 ++++ 2 files changed, 43 insertions(+), 49 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3238ccbf1e..a99a5c2eef 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10147,6 +10147,40 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i= *a) return true; } =20 +static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a) +{ + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_movi_i32(cpu_R[14], read_pc(s) + (a->imm << 12)); + return true; +} + +static bool trans_BL_suffix(DisasContext *s, arg_BL_suffix *a) +{ + TCGv_i32 tmp =3D tcg_temp_new_i32(); + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_bx(s, tmp); + return true; +} + +static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a) +{ + TCGv_i32 tmp; + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + if (!ENABLE_ARCH_5) { + return false; + } + tmp =3D tcg_temp_new_i32(); + tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1); + tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); + tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1); + gen_bx(s, tmp); + return true; +} + static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) { TCGv_i32 addr, tmp; @@ -10736,10 +10770,6 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - int32_t offset; - TCGv_i32 tmp; - TCGv_i32 tmp2; - if (disas_t16(s, insn)) { return; } @@ -10758,53 +10788,10 @@ static void disas_thumb_insn(DisasContext *s, uin= t32_t insn) case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ case 13: /* conditional branch or swi, in decodetree */ - goto illegal_op; - case 14: - if (insn & (1 << 11)) { - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX: - * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF) - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - ARCH(5); - offset =3D ((insn & 0x7ff) << 1); - tmp =3D load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); - - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - } - /* unconditional branch, in decodetree */ - goto illegal_op; - case 15: - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX. - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - - if (insn & (1 << 11)) { - /* 0b1111_1xxx_xxxx_xxxx : BL suffix */ - offset =3D ((insn & 0x7ff) << 1) | 1; - tmp =3D load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - - tmp2 =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->base.pc_next | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */ - uint32_t uoffset =3D ((int32_t)insn << 21) >> 9; - - tcg_gen_movi_i32(cpu_R[14], read_pc(s) + uoffset); - } - break; + /* branches, in decodetree */ + goto illegal_op; } return; illegal_op: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index a4c89dba61..43b9a267a1 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -272,3 +272,10 @@ LDM_t16 1011 110 ......... \ %imm11_0x2 0:s11 !function=3Dtimes_2 =20 B 11100 ........... &i imm=3D%imm11_0x2 + +# thumb_insn_is_16bit() ensures we won't be decoding these as +# T16 instructions for a Thumb2 CPU, so these patterns must be +# a Thumb1 split BL/BLX. +BLX_suffix 11101 imm:11 &i +BL_BLX_prefix 11110 imm:s11 &i +BL_suffix 11111 imm:11 &i --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 68/69] target/arm: Clean up disas_thumb_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that everything is converted, remove the rest of the legacy decode. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 27 ++------------------------- 1 file changed, 2 insertions(+), 25 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index a99a5c2eef..2412dde631 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10770,32 +10770,9 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) =20 static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - if (disas_t16(s, insn)) { - return; + if (!disas_t16(s, insn)) { + unallocated_encoding(s); } - /* fall back to legacy decoder */ - - switch (insn >> 12) { - case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree = */ - case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree= */ - case 5: /* load/store register offset, in decodetree */ - case 6: /* load/store word immediate offset, in decodetree */ - case 7: /* load/store byte immediate offset, in decodetree */ - case 8: /* load/store halfword immediate offset, in decodetree */ - case 9: /* load/store from stack, in decodetree */ - case 10: /* add PC/SP (immediate), in decodetree */ - case 11: /* misc, in decodetree */ - case 12: /* load/store multiple, in decodetree */ - case 13: /* conditional branch or swi, in decodetree */ - case 14: - case 15: - /* branches, in decodetree */ - goto illegal_op; - } - return; -illegal_op: - unallocated_encoding(s); } =20 static bool insn_crosses_page(CPUARMState *env, DisasContext *s) --=20 2.17.1 From nobody Sun May 5 04:10:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1567629083; cv=none; d=zoho.com; s=zohoarc; b=IZYHLJBlIYAWgGceUjqrgCXSh5JRrnOrYeDtcA1GGfdcHhHARV7VJiVD3iauQ2OVpw6cR56Pr9qwtADjBjtwOYtkB+0BaFa7GrSGHUhWxFrmxgoqRe2b2niL0aJdWndHqkvNRUstnOCUZpqc1PjcLnTtj/fIiBbV7xyOlNeVIfg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567629083; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=/PXkXzASKMcUQDbV6Hl9B5xocqfOCXTaxlqtgyWXLXY=; b=MKu31566N8cYulw+8ULVhuG161OudtDnvsp5Yqh0/8z97xGhNyEPgrL836kMq5w/qrRhex5zlCWUB1vmglo00scL+8U8/jQfK/ClQ3PxotjVmgX+TLwas1xTQGtAGWIQW+Wx4GfGUdJdR7GYh3tIlh+wE1q33CNzU7j66Q/wy64= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1567629083505521.6926258062737; Wed, 4 Sep 2019 13:31:23 -0700 (PDT) Received: from localhost ([::1]:38806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5bvw-0007hh-Dy for importer@patchew.org; Wed, 04 Sep 2019 16:31:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41556) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5b18-0005hD-Dp for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5b17-0003Rx-5y for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:34 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:43518) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i5b15-0003Mj-9d for qemu-devel@nongnu.org; Wed, 04 Sep 2019 15:32:33 -0400 Received: by mail-pg1-x543.google.com with SMTP id u72so7590058pgb.10 for ; Wed, 04 Sep 2019 12:32:29 -0700 (PDT) Received: from localhost.localdomain (97-113-7-119.tukw.qwest.net. [97.113.7.119]) by smtp.gmail.com with ESMTPSA id f6sm18999174pga.50.2019.09.04.12.32.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 12:32:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/PXkXzASKMcUQDbV6Hl9B5xocqfOCXTaxlqtgyWXLXY=; b=oABczCk+r1Ph0Tq2jPBo4ES/BfjeCyUc6xL4ploAXIPJzq/gYgpcgxyWnDR0wfZE3f rsVTU3KR+3UO9RS/YgdhiYCHZhs9EVm8Hg4cuGSgTd4da+HOwTrvsl8JeXkUrHk1RruX pJ2cakqWG4tSenbqapliTXOMKW1ZZgmGcBax4TfTppRZVfj9o2XSfetNh0Jb8m+itPVd TRJwvNONdH3NwCZdHyrsb0qRIjQumfxlRgOxEEkflKdL1nq/1owXSVtBbPVPtxcrsJ5f RJGfAgGhuHmsWIPNML5xTpV2CBiQjU5Juqvn066SjDs18JTatE2je8EkbRfW8BPI6J2v 74AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/PXkXzASKMcUQDbV6Hl9B5xocqfOCXTaxlqtgyWXLXY=; b=FQ8a0mP5aXvXe33l3RWLUAeRlOIuUBs5EszddrvVQVzoXfKBwfGGmR0SGACrHHOH6D WhNgBmZCxpfZ1vwu464ax1fZGVVLIHFQ82h11UszobRqk39iLwF7qpZYYitIVOjEDJ7b tovY0FCoXSrTUejWYc66I4g/clKUiw7k29rbquXs1PDvynN9YTjddQ8lJfNbdmjb/vbe SxLjT5QRqUqUkr/DguI2ms91MfPriPDCiFv1WR5e8CezSFrNB5WvaERX1UKkk43MCLVp uhxw0lOigrio/gQQCs/omnsgefnzM/UYdWUDmzpVAUb9WNIXHq0QHdkOwq2tXfklGAPh n5Rg== X-Gm-Message-State: APjAAAWUFsMhz9DMXvrhcPYf+PjXKSXWZHph3Fq5f1F8tuYF5Vgqolt3 vQF9Ax8ohoDePHDworomMocEcw8m2H0= X-Google-Smtp-Source: APXvYqxD3a1G2MCmL8jFGOeZT09xJ3q4yvUpX6mX1baMUoOE5EwoofX4ykXyID8mriOwyVH230y0DA== X-Received: by 2002:aa7:8556:: with SMTP id y22mr21009221pfn.252.1567625548160; Wed, 04 Sep 2019 12:32:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 12:30:59 -0700 Message-Id: <20190904193059.26202-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904193059.26202-1-richard.henderson@linaro.org> References: <20190904193059.26202-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v4 69/69] target/arm: Inline gen_bx_im into callers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There are only two remaining uses of gen_bx_im. In each case, we know the destination mode -- not changing in the case of gen_jmp or changing in the case of trans_BLX_i. Use this to simplify the surrounding code. For trans_BLX_i, use gen_jmp for the actual branch. For gen_jmp, use gen_set_pc_im to set up the single-step. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 +++++++------------------- 1 file changed, 7 insertions(+), 19 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 2412dde631..34bb280e3d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -765,21 +765,6 @@ static inline void gen_set_pc_im(DisasContext *s, targ= et_ulong val) tcg_gen_movi_i32(cpu_R[15], val); } =20 -/* Set PC and Thumb state from an immediate address. */ -static inline void gen_bx_im(DisasContext *s, uint32_t addr) -{ - TCGv_i32 tmp; - - s->base.is_jmp =3D DISAS_JUMP; - if (s->thumb !=3D (addr & 1)) { - tmp =3D tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, addr & 1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb)); - tcg_temp_free_i32(tmp); - } - tcg_gen_movi_i32(cpu_R[15], addr & ~1); -} - /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { @@ -2725,9 +2710,8 @@ static inline void gen_jmp (DisasContext *s, uint32_t= dest) { if (unlikely(is_singlestepping(s))) { /* An indirect jump so that we still trigger the debug exception. = */ - if (s->thumb) - dest |=3D 1; - gen_bx_im(s, dest); + gen_set_pc_im(s, dest); + s->base.is_jmp =3D DISAS_JUMP; } else { gen_goto_tb(s, 0, dest); } @@ -10138,12 +10122,16 @@ static bool trans_BL(DisasContext *s, arg_i *a) =20 static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) { + TCGv_i32 tmp; + /* For A32, ARCH(5) is checked near the start of the uncond block. */ if (s->thumb && (a->imm & 2)) { return false; } tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | s->thumb); - gen_bx_im(s, (read_pc(s) & ~3) + a->imm + !s->thumb); + tmp =3D tcg_const_i32(!s->thumb); + store_cpu_field(tmp, thumb); + gen_jmp(s, (read_pc(s) & ~3) + a->imm); return true; } =20 --=20 2.17.1