[Qemu-devel] [PULL v2 00/47] target-arm queue
[PULL v2 00/57] target-arm queue
1
v2: dropped USHL/SSHL patch
1
Squashed in a trivial fix for 32-bit hosts:
2
2
3
The following changes since commit 785a602eae7ad97076b9794ebaba072ad4a9f74f:
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
9
- acc = int128_add(acc, 1 << 7); \
10
+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
4
14
5
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190613-pull-request' into staging (2019-06-13 13:25:25 +0100)
15
-- PMM
16
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
18
19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
6
20
7
are available in the Git repository at:
21
are available in the Git repository at:
8
22
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190613-1
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
10
24
11
for you to fetch changes up to 18cf951af9a27ae573a6fa17f9d0c103f7b7679b:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
12
26
13
target/arm: Fix short-vector increment behaviour (2019-06-13 15:14:06 +0100)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
14
28
15
----------------------------------------------------------------
29
----------------------------------------------------------------
16
target-arm queue:
30
target-arm queue:
17
* convert aarch32 VFP decoder to decodetree
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
18
(includes tightening up decode in a few places)
32
* docs: Document which architecture extensions we emulate
19
* fix minor bugs in VFP short-vector handling
33
* Fix bugs in M-profile FPCXT_NS accesses
20
* hw/core/bus.c: Only the main system bus can have no parent
34
* First slice of MVE patches
21
* smmuv3: Fix decoding of ID register range
35
* Implement MTE3
22
* Implement NSACR gating of floating point
36
* docs/system: arm: Add nRF boards description
23
* Use tcg_gen_gvec_bitsel
24
37
25
----------------------------------------------------------------
38
----------------------------------------------------------------
26
Peter Maydell (44):
39
Alexandre Iooss (1):
27
target/arm: Implement NSACR gating of floating point
40
docs/system: arm: Add nRF boards description
28
hw/arm/smmuv3: Fix decoding of ID register range
29
hw/core/bus.c: Only the main system bus can have no parent
30
target/arm: Add stubs for AArch32 VFP decodetree
31
target/arm: Factor out VFP access checking code
32
target/arm: Fix Cortex-R5F MVFR values
33
target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max
34
target/arm: Convert the VSEL instructions to decodetree
35
target/arm: Convert VMINNM, VMAXNM to decodetree
36
target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree
37
target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree
38
target/arm: Move the VFP trans_* functions to translate-vfp.inc.c
39
target/arm: Add helpers for VFP register loads and stores
40
target/arm: Convert "double-precision" register moves to decodetree
41
target/arm: Convert "single-precision" register moves to decodetree
42
target/arm: Convert VFP two-register transfer insns to decodetree
43
target/arm: Convert VFP VLDR and VSTR to decodetree
44
target/arm: Convert the VFP load/store multiple insns to decodetree
45
target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d
46
target/arm: Convert VFP VMLA to decodetree
47
target/arm: Convert VFP VMLS to decodetree
48
target/arm: Convert VFP VNMLS to decodetree
49
target/arm: Convert VFP VNMLA to decodetree
50
target/arm: Convert VMUL to decodetree
51
target/arm: Convert VNMUL to decodetree
52
target/arm: Convert VADD to decodetree
53
target/arm: Convert VSUB to decodetree
54
target/arm: Convert VDIV to decodetree
55
target/arm: Convert VFP fused multiply-add insns to decodetree
56
target/arm: Convert VMOV (imm) to decodetree
57
target/arm: Convert VABS to decodetree
58
target/arm: Convert VNEG to decodetree
59
target/arm: Convert VSQRT to decodetree
60
target/arm: Convert VMOV (register) to decodetree
61
target/arm: Convert VFP comparison insns to decodetree
62
target/arm: Convert the VCVT-from-f16 insns to decodetree
63
target/arm: Convert the VCVT-to-f16 insns to decodetree
64
target/arm: Convert VFP round insns to decodetree
65
target/arm: Convert double-single precision conversion insns to decodetree
66
target/arm: Convert integer-to-float insns to decodetree
67
target/arm: Convert VJCVT to decodetree
68
target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree
69
target/arm: Convert float-to-integer VCVT insns to decodetree
70
target/arm: Fix short-vector increment behaviour
71
41
72
Richard Henderson (3):
42
Peter Collingbourne (1):
73
target/arm: Use tcg_gen_gvec_bitsel
43
target/arm: Implement MTE3
74
target/arm: Fix output of PAuth Auth
75
decodetree: Fix comparison of Field
76
44
77
target/arm/Makefile.objs | 13 +
45
Peter Maydell (55):
78
tests/tcg/aarch64/Makefile.target | 2 +-
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
79
target/arm/cpu.h | 11 +
47
hw/acpi: Provide function acpi_ghes_present()
80
target/arm/translate-a64.h | 2 +
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
81
target/arm/translate.h | 3 -
49
docs/system/arm: Document which architecture extensions we emulate
82
hw/arm/smmuv3.c | 2 +-
50
target/arm/translate-vfp.c: Whitespace fixes
83
hw/core/bus.c | 21 +-
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
84
target/arm/cpu.c | 6 +
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
85
target/arm/helper.c | 75 +-
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
86
target/arm/pauth_helper.c | 4 +-
54
target/arm: Factor FP context update code out into helper function
87
target/arm/translate-a64.c | 15 +-
55
target/arm: Split vfp_access_check() into A and M versions
88
target/arm/translate-vfp.inc.c | 2672 +++++++++++++++++++++++++++++++++++++
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
89
target/arm/translate.c | 1581 +---------------------
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
90
tests/tcg/aarch64/pauth-2.c | 61 +
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
91
scripts/decodetree.py | 2 +-
59
target/arm: Implement MVE VCLZ
92
target/arm/vfp-uncond.decode | 63 +
60
target/arm: Implement MVE VCLS
93
target/arm/vfp.decode | 242 ++++
61
target/arm: Implement MVE VREV16, VREV32, VREV64
94
17 files changed, 3203 insertions(+), 1572 deletions(-)
62
target/arm: Implement MVE VMVN (register)
95
create mode 100644 target/arm/translate-vfp.inc.c
63
target/arm: Implement MVE VABS
96
create mode 100644 tests/tcg/aarch64/pauth-2.c
64
target/arm: Implement MVE VNEG
97
create mode 100644 target/arm/vfp-uncond.decode
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
98
create mode 100644 target/arm/vfp.decode
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
99
101
102
docs/system/arm/emulation.rst | 103 ++++
103
docs/system/arm/nrf.rst | 51 ++
104
docs/system/target-arm.rst | 7 +
105
include/hw/acpi/ghes.h | 9 +
106
include/tcg/tcg-op.h | 8 +
107
include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
109
target/arm/helper.h | 2 +
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
135
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.