On May 8, 2019 2:32 AM, "Richard Henderson" <richard.henderson@linaro.org>
wrote:
>
> This macro is now always empty, so remove it. This leaves the
> entire contents of CPUArchState under the control of the guest
> architecture.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/exec/cpu-defs.h | 2 --
> target/alpha/cpu.h | 3 ---
> target/arm/cpu.h | 4 +---
> target/cris/cpu.h | 2 --
> target/hppa/cpu.h | 3 ---
> target/i386/cpu.h | 4 +---
> target/lm32/cpu.h | 2 --
> target/m68k/cpu.h | 2 --
> target/microblaze/cpu.h | 2 --
> target/mips/cpu.h | 2 --
> target/moxie/cpu.h | 3 ---
> target/nios2/cpu.h | 2 --
> target/openrisc/cpu.h | 2 --
> target/ppc/cpu.h | 2 --
> target/riscv/cpu.h | 4 ----
> target/s390x/cpu.h | 2 --
> target/sh4/cpu.h | 2 --
> target/sparc/cpu.h | 2 --
> target/tilegx/cpu.h | 2 --
> target/tricore/cpu.h | 2 --
> target/unicore32/cpu.h | 2 --
> target/xtensa/cpu.h | 2 --
> 22 files changed, 2 insertions(+), 51 deletions(-)
>
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index 4cde7d611c..1f75a97701 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -233,8 +233,6 @@ typedef struct CPUTLB { } CPUTLB;
>
> #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
>
> -#define CPU_COMMON /* Nothing */
> -
> /*
> * This structure must be placed in ArchCPU immedately
> * before CPUArchState, as a field named "neg".
> diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
> index f4bb67c101..5bd90b7ce5 100644
> --- a/target/alpha/cpu.h
> +++ b/target/alpha/cpu.h
> @@ -246,9 +246,6 @@ struct CPUAlphaState {
> /* This alarm doesn't exist in real hardware; we wish it did. */
> uint64_t alarm_expire;
>
> - /* Those resources are used only in QEMU core */
> - CPU_COMMON
> -
> int error_code;
>
> uint32_t features;
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 909cb4604d..135a16a351 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -643,9 +643,7 @@ typedef struct CPUARMState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> - /* Fields after CPU_COMMON are preserved across CPU reset. */
> + /* Fields after this point are preserved across CPU reset. */
>
> /* Internal CPU feature flags. */
> uint64_t features;
> diff --git a/target/cris/cpu.h b/target/cris/cpu.h
> index eeab483dba..6dc4502e9a 100644
> --- a/target/cris/cpu.h
> +++ b/target/cris/cpu.h
> @@ -163,8 +163,6 @@ typedef struct CPUCRISState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Members from load_info on are preserved across resets. */
> void *load_info;
> } CPUCRISState;
> diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
> index 0661ff60c1..3ed2ac3c25 100644
> --- a/target/hppa/cpu.h
> +++ b/target/hppa/cpu.h
> @@ -197,9 +197,6 @@ struct CPUHPPAState {
> target_ureg cr_back[2]; /* back of cr17/cr18 */
> target_ureg shadow[7]; /* shadow registers */
>
> - /* Those resources are used only in QEMU core */
> - CPU_COMMON
> -
> /* ??? The number of entries isn't specified by the architecture. */
> /* ??? Implement a unified itlb/dtlb for the moment. */
> /* ??? We should use a more intelligent data structure. */
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 43bb6ab841..8069e5b19d 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1288,9 +1288,7 @@ typedef struct CPUX86State {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> - /* Fields after CPU_COMMON are preserved across CPU reset. */
> + /* Fields after this point are preserved across CPU reset. */
>
> /* processor features (e.g. for CPUID insn) */
> /* Minimum level/xlevel/xlevel2, based on CPU model + features */
> diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
> index 0ec898eb1d..563600a30a 100644
> --- a/target/lm32/cpu.h
> +++ b/target/lm32/cpu.h
> @@ -159,8 +159,6 @@ struct CPULM32State {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> uint32_t eba; /* exception base address */
> uint32_t deba; /* debug exception base address */
> diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
> index 096d1eb588..4e27ff677f 100644
> --- a/target/m68k/cpu.h
> +++ b/target/m68k/cpu.h
> @@ -143,8 +143,6 @@ typedef struct CPUM68KState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> uint32_t features;
> } CPUM68KState;
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 732653caed..6a470a2492 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -266,8 +266,6 @@ struct CPUMBState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* These fields are preserved on reset. */
>
> struct {
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 2d9c5f26eb..b9e58ed883 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1021,8 +1021,6 @@ struct CPUMIPSState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> CPUMIPSMVPContext *mvp;
> #if !defined(CONFIG_USER_ONLY)
> diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
> index f5ee8a02f4..a62cca1817 100644
> --- a/target/moxie/cpu.h
> +++ b/target/moxie/cpu.h
> @@ -45,9 +45,6 @@ typedef struct CPUMoxieState {
>
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
> -
> - CPU_COMMON
> -
> } CPUMoxieState;
>
> #include "qom/cpu.h"
> diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
> index cd06a2ef41..75ea964632 100644
> --- a/target/nios2/cpu.h
> +++ b/target/nios2/cpu.h
> @@ -166,8 +166,6 @@ struct CPUNios2State {
>
> uint32_t irq_pending;
> #endif
> -
> - CPU_COMMON
> };
>
> /**
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index e1acd48652..e3ffa618c9 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -286,8 +286,6 @@ typedef struct CPUOpenRISCState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> uint32_t cpucfgr; /* CPU configure register */
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index bb57496212..bbc8eb0cfc 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -999,8 +999,6 @@ struct CPUPPCState {
> /* when a memory exception occurs, the access type is stored here */
> int access_type;
>
> - CPU_COMMON
> -
> /* MMU context - only relevant for full system emulation */
> #if !defined(CONFIG_USER_ONLY)
> #if defined(TARGET_PPC64)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 30a01e8386..7086b336c6 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -169,10 +169,6 @@ struct CPURISCVState {
>
> float_status fp_status;
>
> - /* QEMU */
> - CPU_COMMON
> -
> - /* Fields from here on are preserved across CPU reset. */
Why is this comment line deleted in this patch? If you want to delete this
line, you should do it in a separate patch, with a separate explanation, as
the comment has nothing to do with CPU_COMMON.
Thanks,
Aleksandar
> QEMUTimer *timer; /* Internal timer */
> };
>
> diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
> index ebcf7863e4..17d54f9587 100644
> --- a/target/s390x/cpu.h
> +++ b/target/s390x/cpu.h
> @@ -114,8 +114,6 @@ struct CPUS390XState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> #if !defined(CONFIG_USER_ONLY)
> uint32_t core_id; /* PoP "CPU address", same as cpu_index */
> uint64_t cpuid;
> diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
> index 944854dbe0..974d46aae1 100644
> --- a/target/sh4/cpu.h
> +++ b/target/sh4/cpu.h
> @@ -179,8 +179,6 @@ typedef struct CPUSH4State {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved over CPU reset. */
> int id; /* CPU model */
>
> diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
> index ae9ac07a9d..69e2199569 100644
> --- a/target/sparc/cpu.h
> +++ b/target/sparc/cpu.h
> @@ -446,8 +446,6 @@ struct CPUSPARCState {
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
>
> - CPU_COMMON
> -
> /* Fields from here on are preserved across CPU reset. */
> target_ulong version;
> uint32_t nwindows;
> diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
> index deb3e836ea..c2acb43c2b 100644
> --- a/target/tilegx/cpu.h
> +++ b/target/tilegx/cpu.h
> @@ -93,8 +93,6 @@ typedef struct CPUTLGState {
>
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
> -
> - CPU_COMMON
> } CPUTLGState;
>
> #include "qom/cpu.h"
> diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
> index 43ef29b6bd..9fe501f98f 100644
> --- a/target/tricore/cpu.h
> +++ b/target/tricore/cpu.h
> @@ -184,8 +184,6 @@ struct CPUTriCoreState {
> int error_code;
> uint32_t hflags; /* CPU State */
>
> - CPU_COMMON
> -
> /* Internal CPU feature flags. */
> uint64_t features;
>
> diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
> index 140c590ec1..1ae0d78f4f 100644
> --- a/target/unicore32/cpu.h
> +++ b/target/unicore32/cpu.h
> @@ -55,8 +55,6 @@ typedef struct CPUUniCore32State {
> float_status fp_status;
> } ucf64;
>
> - CPU_COMMON
> -
> /* Internal CPU feature flags. */
> uint32_t features;
>
> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
> index 1bbb839bed..4e289dfa6e 100644
> --- a/target/xtensa/cpu.h
> +++ b/target/xtensa/cpu.h
> @@ -511,8 +511,6 @@ typedef struct CPUXtensaState {
>
> /* Watchpoints for DBREAK registers */
> struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
> -
> - CPU_COMMON
> } CPUXtensaState;
>
> /**
> --
> 2.17.1
>
>