[Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments

Richard Henderson posted 8 patches 5 years, 1 month ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20190401031155.21293-1-richard.henderson@linaro.org
Maintainers: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Palmer Dabbelt <palmer@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>
target/riscv/cpu.c                      |  16 +-
target/riscv/insn_trans/trans_rvc.inc.c | 347 ------------------------
target/riscv/insn_trans/trans_rvi.inc.c |  20 +-
target/riscv/translate.c                |  40 ++-
target/riscv/Makefile.objs              |  15 +-
target/riscv/insn16-32.decode           |  28 ++
target/riscv/insn16-64.decode           |  30 ++
target/riscv/insn16.decode              | 154 ++++++-----
target/riscv/insn32.decode              |  10 +-
9 files changed, 205 insertions(+), 455 deletions(-)
delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
create mode 100644 target/riscv/insn16-32.decode
create mode 100644 target/riscv/insn16-64.decode
[Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments
Posted by Richard Henderson 5 years, 1 month ago
There's new support in decodetree for pattern groups.
I believe that patch 5, or something close to it, was
posted as an RFC as part of the original pattern group
patch set, but this cleans that up further.


r~


Richard Henderson (8):
  target/riscv: Name the argument sets for all of insn32 formats
  target/riscv: Use --static-decode for decodetree
  target/riscv: Merge argument sets for insn32 and insn16
  target/riscv: Merge argument decode for RVC shifti
  target/riscv: Use pattern groups in insn16.decode
  target/riscv: Split RVC32 and RVC64 insns into separate files
  target/riscv: Split gen_arith_imm into functional and temp
  target/riscv: Remove spaces from register names

 target/riscv/cpu.c                      |  16 +-
 target/riscv/insn_trans/trans_rvc.inc.c | 347 ------------------------
 target/riscv/insn_trans/trans_rvi.inc.c |  20 +-
 target/riscv/translate.c                |  40 ++-
 target/riscv/Makefile.objs              |  15 +-
 target/riscv/insn16-32.decode           |  28 ++
 target/riscv/insn16-64.decode           |  30 ++
 target/riscv/insn16.decode              | 154 ++++++-----
 target/riscv/insn32.decode              |  10 +-
 9 files changed, 205 insertions(+), 455 deletions(-)
 delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
 create mode 100644 target/riscv/insn16-32.decode
 create mode 100644 target/riscv/insn16-64.decode

-- 
2.17.1


Re: [Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments
Posted by Palmer Dabbelt 5 years ago
On Sun, 31 Mar 2019 20:11:47 PDT (-0700), richard.henderson@linaro.org wrote:
> There's new support in decodetree for pattern groups.
> I believe that patch 5, or something close to it, was
> posted as an RFC as part of the original pattern group
> patch set, but this cleans that up further.
>
>
> r~
>
>
> Richard Henderson (8):
>   target/riscv: Name the argument sets for all of insn32 formats
>   target/riscv: Use --static-decode for decodetree
>   target/riscv: Merge argument sets for insn32 and insn16
>   target/riscv: Merge argument decode for RVC shifti
>   target/riscv: Use pattern groups in insn16.decode
>   target/riscv: Split RVC32 and RVC64 insns into separate files
>   target/riscv: Split gen_arith_imm into functional and temp
>   target/riscv: Remove spaces from register names
>
>  target/riscv/cpu.c                      |  16 +-
>  target/riscv/insn_trans/trans_rvc.inc.c | 347 ------------------------
>  target/riscv/insn_trans/trans_rvi.inc.c |  20 +-
>  target/riscv/translate.c                |  40 ++-
>  target/riscv/Makefile.objs              |  15 +-
>  target/riscv/insn16-32.decode           |  28 ++
>  target/riscv/insn16-64.decode           |  30 ++
>  target/riscv/insn16.decode              | 154 ++++++-----
>  target/riscv/insn32.decode              |  10 +-
>  9 files changed, 205 insertions(+), 455 deletions(-)
>  delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
>  create mode 100644 target/riscv/insn16-32.decode
>  create mode 100644 target/riscv/insn16-64.decode

Thanks!  I'm happy taking this as it stands, since all those decode issues I
pointed out aren't regressions in this patch set.  Let me know if you want to
fix those or if you want me to -- as you can probably tell my email queue is a
bit long... :)

I've dropped this on my integration branch, but I probably won't submit a pull
for a week or so.

Re: [Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments
Posted by Richard Henderson 5 years ago
On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
> 
> Thanks!  I'm happy taking this as it stands, since all those decode issues I
> pointed out aren't regressions in this patch set.  Let me know if you want to
> fix those or if you want me to -- as you can probably tell my email queue is a
> bit long... :)

I'm happy to fix those, if you'll point me at your branch.


r~

Re: [Qemu-devel] [PATCH for-4.1 0/8] target/riscv: decodetree improvments
Posted by Palmer Dabbelt 5 years ago
On Thu, 25 Apr 2019 09:23:56 PDT (-0700), richard.henderson@linaro.org wrote:
> On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
>>
>> Thanks!  I'm happy taking this as it stands, since all those decode issues I
>> pointed out aren't regressions in this patch set.  Let me know if you want to
>> fix those or if you want me to -- as you can probably tell my email queue is a
>> bit long... :)
>
> I'm happy to fix those, if you'll point me at your branch.

github.com/palmer-dabbelt/riscv-qemu, for-master branch.  I haven't sent the PR
because I haven't banged on the branch yet, but I don't anticipate any major
problems.