From nobody Fri May 17 01:43:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554088465753208.24270660484842; Sun, 31 Mar 2019 20:14:25 -0700 (PDT) Received: from localhost ([127.0.0.1]:33543 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnOw-0007uh-OB for importer@patchew.org; Sun, 31 Mar 2019 23:14:22 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38929) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnMx-0006l2-DQ for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hAnMv-0002q4-H2 for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:19 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:32770) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hAnMr-0002o2-Pe for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:15 -0400 Received: by mail-pl1-x643.google.com with SMTP id t16so1860735plo.0 for ; Sun, 31 Mar 2019 20:12:12 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id c1sm11843954pfd.114.2019.03.31.20.12.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 31 Mar 2019 20:12:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ldf8BOBEYaEPwE6SNRadbgy/cKtsZyA6qEQMWTLJRXo=; b=C42HRDUuoHU68BYcw1+t98DCrTpIIf4ZfPz80bb6hCWnjllckksce+rNvKiEYBZN5m 2O453wURXsQMh6z+ryrHVf/aatu6AWBcX3elTM+zolosMkqZVEapg4+76iJILiN6/vrI Z92foNiPo0YfvhoFnNZiqfG6wMXWFTlQiJZfGz18bjxPOev5Pgo/GZR98IKnjpQRkaGI SQat+TJGecKfXhgdHm51NPkpfiYK9K79PDhZpngu7bRdun5WsusYUyY9O7qe9wm9NzTQ BOgll4d8iEoag1GNlCDIik+KKLJ5xw5JSA6KGwM+Zcy+OET9mszf9u20ZI0IULBWEgTd qXNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ldf8BOBEYaEPwE6SNRadbgy/cKtsZyA6qEQMWTLJRXo=; b=PPLM/5N6pQNo+1z+NltFAs7cCvnptP6ECURs3MHmNemZQwj3lejj70ttd9jjQ9Y6M0 ymWEjOMA5+qxcS0KjT9yuXsIRs1R+M7iqJ2Trjl65TTyxvHQcYK8c2iVCjzTPgf94wjf kaNPDP7Dq21VdQequk/vdVh3+8r1d3p6VtMJvC+v4688KLDR1v/DsW73ER9INU9nt0rG 3gTrCy4dySIjbDbCpgeVDXk1ul1JxcIgTrKgpGYZfV5lttQjSUJdMvJx+PNG+wKENQvg RjJxqtPgRCEwvvG6qlzlQ/nk0JFpEpbQICEFLr9jBvQDg999Wv1wkTkrohWldQhVEUIu 85dw== X-Gm-Message-State: APjAAAUeSboduBSIJK58gsMm8mAASP5goqyy6l7ABhyeztTng8qWkKaf BjX5uv57w0Lh6zjIzt6lnjRmzt7nNZZfJw== X-Google-Smtp-Source: APXvYqytktj8BJrz61ioYBIKw8vv+dLRwGyqH7rphG09oGXZp8iMc4wHhXiKd1rVWLmj69tunIlYIw== X-Received: by 2002:a17:902:b948:: with SMTP id h8mr32760111pls.39.1554088331042; Sun, 31 Mar 2019 20:12:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 10:11:48 +0700 Message-Id: <20190401031155.21293-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190401031155.21293-1-richard.henderson@linaro.org> References: <20190401031155.21293-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, palmer@sifive.com, Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/insn32.decode | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6f3ab7aa52..77f794ed70 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -34,9 +34,13 @@ %imm_u 12:s20 !function=3Dex_shift_12 =20 # Argument sets: +&empty &b imm rs2 rs1 &i imm rs1 rd +&j imm rd &r rd rs1 rs2 +&s imm rs1 rs2 +&u imm rd &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd =20 @@ -44,9 +48,9 @@ @r ....... ..... ..... ... ..... ....... &r %rs2 %r= s1 %rd @i ............ ..... ... ..... ....... &i imm=3D%imm_i = %rs1 %rd @b ....... ..... ..... ... ..... ....... &b imm=3D%imm_b %rs2= %rs1 -@s ....... ..... ..... ... ..... ....... imm=3D%imm_s %rs2= %rs1 -@u .................... ..... ....... imm=3D%imm_u = %rd -@j .................... ..... ....... imm=3D%imm_j = %rd +@s ....... ..... ..... ... ..... ....... &s imm=3D%imm_s %rs2= %rs1 +@u .................... ..... ....... &u imm=3D%imm_u = %rd +@j .................... ..... ....... &j imm=3D%imm_j = %rd =20 @sh ...... ...... ..... ... ..... ....... &shift shamt=3D%sh10 = %rs1 %rd @csr ............ ..... ... ..... ....... %csr %r= s1 %rd --=20 2.17.1 From nobody Fri May 17 01:43:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554088675953467.25009470130306; Sun, 31 Mar 2019 20:17:55 -0700 (PDT) Received: from localhost ([127.0.0.1]:34357 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnS7-0002VC-Hq for importer@patchew.org; Sun, 31 Mar 2019 23:17:39 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38976) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnN0-0006nk-Cf for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hAnMz-0002rO-EB for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:22 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46562) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hAnMx-0002p7-Jl for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:21 -0400 Received: by mail-pg1-x541.google.com with SMTP id q1so3971949pgv.13 for ; Sun, 31 Mar 2019 20:12:15 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id c1sm11843954pfd.114.2019.03.31.20.12.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 31 Mar 2019 20:12:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dpFu0UtJn3h4iEnuE21ntkTj1sL+0aSszxtNnRJ8slY=; b=cuvFpT6dCZz+T+10qlpByshL2+NDRl94HsNxeEyC20fAX1tH5dXkxflFqc0waLOfNa JCgKXbvPc1BZzJQufk13MwVRwsOkbWUo/+ShzyVRA8NR3GG1Uc5tZqKQ2EH4US63QR+2 ZqqFwu+DLNpQI2qYUm3Jkw2SJGO4VYn8Bo7HjimL+96MU3FOtP8d9CXTtnIyEnoQfvej 3/IePFcUbfLImhDldIhPHBZu3Boqku2SQmglLyY/LUCpizZSIWV7zghrZFhFHHehQy3Q 1o2gCKh5/xnsPFk1v5rJnj3yb63ok+XHzaqsGkN54Z0aEFCLKITytK8OT86up4x1H8vc vsQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dpFu0UtJn3h4iEnuE21ntkTj1sL+0aSszxtNnRJ8slY=; b=Tp0l2IyAYCDNPGmANrvrovAuhnSwKpcYSXXgHHjspka7LP449M4RyqcjYk37rBdq8Y 8gzA2mJQTAC/xpf5Qq8zSrEr6RRJpQcGsSwH5rGrzdEtEXLUAR95Qusa2mLA8F0F6q1K Pj+4YzYEIu+L2jZLECM51+7yeiXjHUSGHeQ00YF7tanUvJKPKdkixkS76UeI7YuhQX6f I9ZW/0nPGxjAtkFVVyp4Qy9C4XpccyqliuogPKeWY/m9oqrfUs9ZCp2LOhjUnTWUgMO9 F5unrQsxHXVEnJUvIpxm0puyzkqsE9+0jOGOnzxdhGwqqck54H9DXFIkNMqW/tX7r0XM utWw== X-Gm-Message-State: APjAAAWhL3sh/zX66LKkBeAL/x+EjbgiB9yqS6/vjp7IL1Pp46T96IFv AEOutklmprODyCEqQY3nhxKIOqg0Ffnl0Q== X-Google-Smtp-Source: APXvYqzD8BbRLotGQp7cDFgS0PD/h6ZMEzhdLgbjgpvgiD13ssBwPt71ngvQhZBdjRA1RfqlIsU63w== X-Received: by 2002:a62:b612:: with SMTP id j18mr89117pff.124.1554088334102; Sun, 31 Mar 2019 20:12:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 10:11:49 +0700 Message-Id: <20190401031155.21293-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190401031155.21293-1-richard.henderson@linaro.org> References: <20190401031155.21293-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, palmer@sifive.com, Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The generated functions are only used within translate.c and do not need to be global, or declared. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/translate.c | 2 -- target/riscv/Makefile.objs | 8 ++++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index dd763647ea..7ebd590486 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -538,7 +538,6 @@ static int ex_rvc_register(int reg) return 8 + reg; } =20 -bool decode_insn32(DisasContext *ctx, uint32_t insn); /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" =20 @@ -667,7 +666,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_privileged.inc.c" =20 -bool decode_insn16(DisasContext *ctx, uint16_t insn); /* auto-generated decoder*/ #include "decode_insn16.inc.c" #include "insn_trans/trans_rvc.inc.c" diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index 9c6c109327..c7a1b063ed 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -7,14 +7,14 @@ decode32-$(TARGET_RISCV64) +=3D $(SRC_PATH)/target/riscv/= insn32-64.decode =20 target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn32 $(decode32-y), \ - "GEN", $(TARGET_DIR)$@) + $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \ + $(decode32-y), "GEN", $(TARGET_DIR)$@) =20 target/riscv/decode_insn16.inc.c: \ $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE) $(call quiet-command, \ - $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn16 --insnwidth 16 $<,= \ - "GEN", $(TARGET_DIR)$@) + $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \ + --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@) =20 target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ target/riscv/decode_insn16.inc.c --=20 2.17.1 From nobody Fri May 17 01:43:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554088521878891.2877487927376; Sun, 31 Mar 2019 20:15:21 -0700 (PDT) Received: from localhost ([127.0.0.1]:33760 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnPp-00006F-N9 for importer@patchew.org; Sun, 31 Mar 2019 23:15:17 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39015) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnN1-0006pK-Sh for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hAnMz-0002rw-Qf for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:23 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:33773) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hAnMz-0002qG-G6 for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:21 -0400 Received: by mail-pf1-x42a.google.com with SMTP id i19so3807576pfd.0 for ; Sun, 31 Mar 2019 20:12:18 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id c1sm11843954pfd.114.2019.03.31.20.12.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 31 Mar 2019 20:12:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zL5P23Mn+NYHoXMQvj57/wL84uuiMV0hE9AjurSDVNU=; b=UZyntfjpMp3bBrbNj/ZfwlBLSTTSEJ5ouOPpkQBLusRi8/uZkK/cy8XBRGAFsdZOmt IjdQiMytqnFwvVMBqFwVJR6PHWaLTQWu2hXsSIgHvmBcQ4neMvoZzfaeaBh308gxxv1i k1+m0Xgczxzm/gWVbpWwqvhoLoU6Di+ZMDxxIdaYaNCE/JiXYRuCr5YV0lQR/3dRd+ca IHuXJQnHIgMIp2K37koZykgPO0qr7Ura3CEYfXwnLTgXgplv6CfnN+F4sLK3zTFDhePF bSi/taD6djQPXsKmlU4FF+yDfLUsbfsKP7FW5RTbPRIo+bF5Bqm1BoQJWaZjuyzvttDX lZdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zL5P23Mn+NYHoXMQvj57/wL84uuiMV0hE9AjurSDVNU=; b=NJA6srJa69NwcD6UQZOWx/OGq2alIOLfa2TTaX06XpKI+OSAC++IizVvwdaIxCWyCX JSlI2eLwG4Eyn1GpoPZh5Aw+bqbQNjPzJw8JQlA3ZHbBjNnyV2eq4eTFvYo0AF0t8g44 XaA28tTQx1zmhPUFFFrtDgtUdTHC9uuo2sz6mZhBA9PgQFQhIM7mod7WP6Rt+BXOlTIj egPKpPHlbtvP1e19dxWHDgFkUV4GJl8C03KxT7rB8Ssnk8a/klCzHOzFoXUC3CZFavvj p8y0Fueiw1uS9od91nk/JnQuHEBj8+CPBC8QLS4lrO4zopmWMd0fJenhAkUX2PzhFS9t ygHg== X-Gm-Message-State: APjAAAUSS0IToUvXPNCeta9W3wX1GTwkTrotKhvJlkdKBB1jXaZAPePc 95OO475WY7Mj51JHx5+T8pjc87IEJpRTbg== X-Google-Smtp-Source: APXvYqyG/lNaIFtUAmvMxk8Rozhdb6eME6l/8Yb/MUcaJEqpydtKN3WXRSlMFxsgQ1D5Fm3eGf9Tyw== X-Received: by 2002:a65:6283:: with SMTP id f3mr59630486pgv.108.1554088336901; Sun, 31 Mar 2019 20:12:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 10:11:50 +0700 Message-Id: <20190401031155.21293-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190401031155.21293-1-richard.henderson@linaro.org> References: <20190401031155.21293-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, palmer@sifive.com, Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In some cases this allows us to directly use the insn32 translator function. In some cases we still need a shim. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvc.inc.c | 144 ++---------------------- target/riscv/translate.c | 13 ++- target/riscv/insn16.decode | 82 ++++++++------ 3 files changed, 69 insertions(+), 170 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index ebcd977b2f..dfb46a2348 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -28,18 +28,6 @@ static bool trans_c_addi4spn(DisasContext *ctx, arg_c_ad= di4spn *a) return trans_addi(ctx, &arg); } =20 -static bool trans_c_fld(DisasContext *ctx, arg_c_fld *a) -{ - arg_fld arg =3D { .rd =3D a->rd, .rs1 =3D a->rs1, .imm =3D a->uimm }; - return trans_fld(ctx, &arg); -} - -static bool trans_c_lw(DisasContext *ctx, arg_c_lw *a) -{ - arg_lw arg =3D { .rd =3D a->rd, .rs1 =3D a->rs1, .imm =3D a->uimm }; - return trans_lw(ctx, &arg); -} - static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) { #ifdef TARGET_RISCV32 @@ -47,31 +35,17 @@ static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw= _ld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - arg_c_lw tmp; - decode_insn16_extract_cl_w(&tmp, ctx->opcode); - arg_flw arg =3D { .rd =3D tmp.rd, .rs1 =3D tmp.rs1, .imm =3D tmp.uimm = }; + arg_i arg; + decode_insn16_extract_cl_w(&arg, ctx->opcode); return trans_flw(ctx, &arg); #else /* C.LD ( RV64C/RV128C-only ) */ - arg_c_fld tmp; - decode_insn16_extract_cl_d(&tmp, ctx->opcode); - arg_ld arg =3D { .rd =3D tmp.rd, .rs1 =3D tmp.rs1, .imm =3D tmp.uimm }; + arg_i arg; + decode_insn16_extract_cl_d(&arg, ctx->opcode); return trans_ld(ctx, &arg); #endif } =20 -static bool trans_c_fsd(DisasContext *ctx, arg_c_fsd *a) -{ - arg_fsd arg =3D { .rs1 =3D a->rs1, .rs2 =3D a->rs2, .imm =3D a->uimm }; - return trans_fsd(ctx, &arg); -} - -static bool trans_c_sw(DisasContext *ctx, arg_c_sw *a) -{ - arg_sw arg =3D { .rs1 =3D a->rs1, .rs2 =3D a->rs2, .imm =3D a->uimm }; - return trans_sw(ctx, &arg); -} - static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) { #ifdef TARGET_RISCV32 @@ -79,34 +53,22 @@ static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw= _sd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - arg_c_sw tmp; - decode_insn16_extract_cs_w(&tmp, ctx->opcode); - arg_fsw arg =3D { .rs1 =3D tmp.rs1, .rs2 =3D tmp.rs2, .imm =3D tmp.uim= m }; + arg_s arg; + decode_insn16_extract_cs_w(&arg, ctx->opcode); return trans_fsw(ctx, &arg); #else /* C.SD ( RV64C/RV128C-only ) */ - arg_c_fsd tmp; - decode_insn16_extract_cs_d(&tmp, ctx->opcode); - arg_sd arg =3D { .rs1 =3D tmp.rs1, .rs2 =3D tmp.rs2, .imm =3D tmp.uimm= }; + arg_s arg; + decode_insn16_extract_cs_d(&arg, ctx->opcode); return trans_sd(ctx, &arg); #endif } =20 -static bool trans_c_addi(DisasContext *ctx, arg_c_addi *a) -{ - if (a->imm =3D=3D 0) { - /* Hint: insn is valid but does not affect state */ - return true; - } - arg_addi arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .imm =3D a->imm }; - return trans_addi(ctx, &arg); -} - static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a) { #ifdef TARGET_RISCV32 /* C.JAL */ - arg_c_j tmp; + arg_j tmp; decode_insn16_extract_cj(&tmp, ctx->opcode); arg_jal arg =3D { .rd =3D 1, .imm =3D tmp.imm }; return trans_jal(ctx, &arg); @@ -117,16 +79,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_= jal_addiw *a) #endif } =20 -static bool trans_c_li(DisasContext *ctx, arg_c_li *a) -{ - if (a->rd =3D=3D 0) { - /* Hint: insn is valid but does not affect state */ - return true; - } - arg_addi arg =3D { .rd =3D a->rd, .rs1 =3D 0, .imm =3D a->imm }; - return trans_addi(ctx, &arg); -} - static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a) { if (a->rd =3D=3D 2) { @@ -177,41 +129,10 @@ static bool trans_c_srai(DisasContext *ctx, arg_c_sra= i *a) return trans_srai(ctx, &arg); } =20 -static bool trans_c_andi(DisasContext *ctx, arg_c_andi *a) -{ - arg_andi arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .imm =3D a->imm }; - return trans_andi(ctx, &arg); -} - -static bool trans_c_sub(DisasContext *ctx, arg_c_sub *a) -{ - arg_sub arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_sub(ctx, &arg); -} - -static bool trans_c_xor(DisasContext *ctx, arg_c_xor *a) -{ - arg_xor arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_xor(ctx, &arg); -} - -static bool trans_c_or(DisasContext *ctx, arg_c_or *a) -{ - arg_or arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_or(ctx, &arg); -} - -static bool trans_c_and(DisasContext *ctx, arg_c_and *a) -{ - arg_and arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_and(ctx, &arg); -} - static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) { #ifdef TARGET_RISCV64 - arg_subw arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_subw(ctx, &arg); + return trans_subw(ctx, a); #else return false; #endif @@ -220,31 +141,12 @@ static bool trans_c_subw(DisasContext *ctx, arg_c_sub= w *a) static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a) { #ifdef TARGET_RISCV64 - arg_addw arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->rs2 }; - return trans_addw(ctx, &arg); + return trans_addw(ctx, a); #else return false; #endif } =20 -static bool trans_c_j(DisasContext *ctx, arg_c_j *a) -{ - arg_jal arg =3D { .rd =3D 0, .imm =3D a->imm }; - return trans_jal(ctx, &arg); -} - -static bool trans_c_beqz(DisasContext *ctx, arg_c_beqz *a) -{ - arg_beq arg =3D { .rs1 =3D a->rs1, .rs2 =3D 0, .imm =3D a->imm }; - return trans_beq(ctx, &arg); -} - -static bool trans_c_bnez(DisasContext *ctx, arg_c_bnez *a) -{ - arg_bne arg =3D { .rs1 =3D a->rs1, .rs2 =3D 0, .imm =3D a->imm }; - return trans_bne(ctx, &arg); -} - static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a) { int shamt =3D a->shamt; @@ -261,18 +163,6 @@ static bool trans_c_slli(DisasContext *ctx, arg_c_slli= *a) return trans_slli(ctx, &arg); } =20 -static bool trans_c_fldsp(DisasContext *ctx, arg_c_fldsp *a) -{ - arg_fld arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm }; - return trans_fld(ctx, &arg); -} - -static bool trans_c_lwsp(DisasContext *ctx, arg_c_lwsp *a) -{ - arg_lw arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm }; - return trans_lw(ctx, &arg); -} - static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) { #ifdef TARGET_RISCV32 @@ -321,18 +211,6 @@ static bool trans_c_ebreak_jalr_add(DisasContext *ctx,= arg_c_ebreak_jalr_add *a) return false; } =20 -static bool trans_c_fsdsp(DisasContext *ctx, arg_c_fsdsp *a) -{ - arg_fsd arg =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm }; - return trans_fsd(ctx, &arg); -} - -static bool trans_c_swsp(DisasContext *ctx, arg_c_swsp *a) -{ - arg_sw arg =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm }; - return trans_sw(ctx, &arg); -} - static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) { #ifdef TARGET_RISCV32 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7ebd590486..9e016d8e50 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -666,8 +666,19 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, #include "insn_trans/trans_rvd.inc.c" #include "insn_trans/trans_privileged.inc.c" =20 -/* auto-generated decoder*/ +/* + * Auto-generated decoder. + * Note that the 16-bit decoder reuses some of the trans_* functions + * initially declared by the 32-bit decoder, which results in duplicate + * declaration warnings. Suppress them. + */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wredundant-decls" + #include "decode_insn16.inc.c" + +#pragma GCC diagnostic pop + #include "insn_trans/trans_rvc.inc.c" =20 static void decode_opc(DisasContext *ctx) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 17cc52cf2a..d0cc778bc9 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -40,17 +40,24 @@ %imm_lui 12:s1 2:5 !function=3Dex_shift_12 =20 =20 +# Argument sets imported from insn32.decode: +&empty !extern +&r rd rs1 rs2 !extern +&i imm rs1 rd !extern +&s imm rs1 rs2 !extern +&j imm rd !extern +&b imm rs2 rs1 !extern +&u imm rd !extern +&shift shamt rs1 rd !extern =20 # Argument sets: &cl rs1 rd &cl_dw uimm rs1 rd -&ci imm rd &ciw nzuimm rd &cs rs1 rs2 &cs_dw uimm rs1 rs2 &cb imm rs1 &cr rd rs2 -&cj imm &c_shift shamt rd =20 &c_ld uimm rd @@ -61,23 +68,24 @@ &cfswsp_sdsp uimm_fswsp uimm_sdsp rs2 =20 # Formats 16: -@cr .... ..... ..... .. &cr rs2=3D%rs2_5 %rd -@ci ... . ..... ..... .. &ci imm=3D%imm_ci %rd +@cr .... ..... ..... .. &r rs2=3D%rs2_5 rs1=3D%rd = %rd +@ci ... . ..... ..... .. &i imm=3D%imm_ci rs1=3D%rd = %rd @ciw ... ........ ... .. &ciw nzuimm=3D%nzuimm_ciw rd= =3D%rs2_3 -@cl_d ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 -@cl_w ... ... ... .. ... .. &cl_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 +@cl_d ... ... ... .. ... .. &i imm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 +@cl_w ... ... ... .. ... .. &i imm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 @cl ... ... ... .. ... .. &cl rs1=3D%rs1_3 rd= =3D%rs2_3 @cs ... ... ... .. ... .. &cs rs1=3D%rs1_3 rs= 2=3D%rs2_3 -@cs_2 ... ... ... .. ... .. &cr rd=3D%rs1_3 rs= 2=3D%rs2_3 -@cs_d ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_d rs1=3D%rs1_3 = rs2=3D%rs2_3 -@cs_w ... ... ... .. ... .. &cs_dw uimm=3D%uimm_cl_w rs1=3D%rs1_3 = rs2=3D%rs2_3 -@cb ... ... ... .. ... .. &cb imm=3D%imm_cb rs1=3D%rs1_3 -@cj ... ........... .. &cj imm=3D%imm_cj +@cs_2 ... ... ... .. ... .. &r rs2=3D%rs2_3 rs1=3D%rs1_3 = rd=3D%rs1_3 +@cs_d ... ... ... .. ... .. &s imm=3D%uimm_cl_d rs1=3D%rs1_3 = rs2=3D%rs2_3 +@cs_w ... ... ... .. ... .. &s imm=3D%uimm_cl_w rs1=3D%rs1_3 = rs2=3D%rs2_3 +@cj ... ........... .. &j imm=3D%imm_cj +@cb_z ... ... ... .. ... .. &b imm=3D%imm_cb rs1=3D%rs1_3 = rs2=3D0 =20 -@c_ld ... . ..... ..... .. &c_ld uimm=3D%uimm_6bit_ld %rd -@c_lw ... . ..... ..... .. &c_ld uimm=3D%uimm_6bit_lw %rd -@c_sd ... . ..... ..... .. &c_sd uimm=3D%uimm_6bit_sd rs2=3D%rs= 2_5 -@c_sw ... . ..... ..... .. &c_sd uimm=3D%uimm_6bit_sw rs2=3D%rs= 2_5 +@c_ldsp ... . ..... ..... .. &i imm=3D%uimm_6bit_ld rs1=3D2 %rd +@c_lwsp ... . ..... ..... .. &i imm=3D%uimm_6bit_lw rs1=3D2 %rd +@c_sdsp ... . ..... ..... .. &s imm=3D%uimm_6bit_sd rs1=3D2 rs2= =3D%rs2_5 +@c_swsp ... . ..... ..... .. &s imm=3D%uimm_6bit_sw rs1=3D2 rs2= =3D%rs2_5 +@c_li ... . ..... ..... .. &i imm=3D%imm_ci rs1=3D0 %rd =20 @c_addi16sp_lui ... . ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16s= p %rd @c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=3D%uimm_6bit= _lw \ @@ -85,45 +93,47 @@ @c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=3D%uimm_6bit= _sw \ uimm_sdsp=3D%uimm_6bit_sd rs2=3D%rs2_5 =20 -@c_shift ... . .. ... ..... .. &c_shift rd=3D%rs1_3 shamt=3D%nzuimm= _6bit -@c_shift2 ... . .. ... ..... .. &c_shift rd=3D%rd shamt=3D%nzuimm= _6bit +@c_shift ... . .. ... ..... .. \ + &shift rd=3D%rs1_3 rs1=3D%rs1_3 shamt=3D%nzuimm_6bit +@c_shift2 ... . .. ... ..... .. \ + &shift rd=3D%rd rs1=3D%rd shamt=3D%nzuimm_6bit =20 -@c_andi ... . .. ... ..... .. &ci imm=3D%imm_ci rd=3D%rs1_3 +@c_andi ... . .. ... ..... .. &i imm=3D%imm_ci rs1=3D%rs1_3 rd=3D%= rs1_3 =20 # *** RV64C Standard Extension (Quadrant 0) *** c_addi4spn 000 ........ ... 00 @ciw -c_fld 001 ... ... .. ... 00 @cl_d -c_lw 010 ... ... .. ... 00 @cl_w +fld 001 ... ... .. ... 00 @cl_d +lw 010 ... ... .. ... 00 @cl_w c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm man= ually -c_fsd 101 ... ... .. ... 00 @cs_d -c_sw 110 ... ... .. ... 00 @cs_w +fsd 101 ... ... .. ... 00 @cs_d +sw 110 ... ... .. ... 00 @cs_w c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm man= ually =20 # *** RV64C Standard Extension (Quadrant 1) *** -c_addi 000 . ..... ..... 01 @ci +addi 000 . ..... ..... 01 @ci c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm ma= nually -c_li 010 . ..... ..... 01 @ci +addi 010 . ..... ..... 01 @c_li c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with= C.LUI c_srli 100 . 00 ... ..... 01 @c_shift c_srai 100 . 01 ... ..... 01 @c_shift -c_andi 100 . 10 ... ..... 01 @c_andi -c_sub 100 0 11 ... 00 ... 01 @cs_2 -c_xor 100 0 11 ... 01 ... 01 @cs_2 -c_or 100 0 11 ... 10 ... 01 @cs_2 -c_and 100 0 11 ... 11 ... 01 @cs_2 +andi 100 . 10 ... ..... 01 @c_andi +sub 100 0 11 ... 00 ... 01 @cs_2 +xor 100 0 11 ... 01 ... 01 @cs_2 +or 100 0 11 ... 10 ... 01 @cs_2 +and 100 0 11 ... 11 ... 01 @cs_2 c_subw 100 1 11 ... 00 ... 01 @cs_2 c_addw 100 1 11 ... 01 ... 01 @cs_2 -c_j 101 ........... 01 @cj -c_beqz 110 ... ... ..... 01 @cb -c_bnez 111 ... ... ..... 01 @cb +jal 101 ........... 01 @cj rd=3D0 # C.J +beq 110 ... ... ..... 01 @cb_z +bne 111 ... ... ..... 01 @cb_z =20 # *** RV64C Standard Extension (Quadrant 2) *** c_slli 000 . ..... ..... 10 @c_shift2 -c_fldsp 001 . ..... ..... 10 @c_ld -c_lwsp 010 . ..... ..... 10 @c_lw +fld 001 . ..... ..... 10 @c_ldsp +lw 010 . ..... ..... 10 @c_lwsp c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWS= P:RV32 c_jr_mv 100 0 ..... ..... 10 @cr c_ebreak_jalr_add 100 1 ..... ..... 10 @cr -c_fsdsp 101 ...... ..... 10 @c_sd -c_swsp 110 . ..... ..... 10 @c_sw +fsd 101 ...... ..... 10 @c_sdsp +sw 110 . ..... ..... 10 @c_swsp c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWS= P:RV32 --=20 2.17.1 From nobody Fri May 17 01:43:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 155408866954227.68682271877242; Sun, 31 Mar 2019 20:17:49 -0700 (PDT) Received: from localhost ([127.0.0.1]:34392 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnSD-0002bh-AV for importer@patchew.org; Sun, 31 Mar 2019 23:17:45 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38997) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnN1-0006oN-2T for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hAnMz-0002rp-QI for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:23 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:33487) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hAnMz-0002qw-FL for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:21 -0400 Received: by mail-pg1-x544.google.com with SMTP id b12so4005876pgk.0 for ; Sun, 31 Mar 2019 20:12:20 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id c1sm11843954pfd.114.2019.03.31.20.12.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 31 Mar 2019 20:12:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JUQH54WlqWGm8qyK2Q0VFVzTkdAZArTzYx2vwJJCIVI=; b=GD0V5uMURb1QM+rZt7wGIQ5Met93OWvQpXKF0JN9RT/Y/FDsmy6j4ZF9YkmR2At3Z9 g5ExvDJcQSzya65ef+53d1P+TQKS611GqCOiGOBVxe6D0hN7NIl63IGsbv97V8yz5xQp nJOhbXBZradEvA41045luL20QmPiejGtbu9p3bXVJWjC1ohyUnC7gR97OHH3CVLPZE4n yfTW/1WV71rprSsELS3BKgHKApID/3xrXVff1PBD0VZ3xFg/XNW5ExzFZEYqUsL/S1zX ptS2G4sqYdVSdnM+wv1nyu5kfoN14IpuyfxnnAPvdzyrTm01pO59thqTqi6/oJC5E7/M miGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JUQH54WlqWGm8qyK2Q0VFVzTkdAZArTzYx2vwJJCIVI=; b=okqGe7fk7QEHkHbsR27tF/1Hco6fjYhvZKjdDtIoZ055/beRVzg9BeLPwss4X2rOhT 9NPE+sgxLIKgftBVQu2yC4ttrlcJaow+zqXTx5aP6F5N+1f80XgDoJJ3RGrsfZnHX98X RLAhX+mxIncnZdudIJdzxhpJcTPJqa20jllweNDyeKgjX3l+MyebQYi+XMLuhH6OXlB0 LCgn1zno4tTej4B6k0zfQnnyLLo60/CanGdSN8VxvMcStQfNH8lYe8rjdZtfu7db+R1M 0GQPMmFNJzsC60WP1nxHo3VIuvnH1SjkOyx+q8/zjicX4V26iVezR0yAPb02ES89lXvz ouoA== X-Gm-Message-State: APjAAAU7pZwMVIRqmtMRQ1qvvFnU42uzot/isSP1c6HUR9+d47822DkO FYywZmFxjQ4JK/hUlDxL2Ykm9nLW433Hsg== X-Google-Smtp-Source: APXvYqzTdRFtojuCNnW0xKO8vqyCJzYlwSorBVwiCOXuftNt4+vRJznWLwcfd1+uv72nUQCt8npZag== X-Received: by 2002:a63:d5f:: with SMTP id 31mr12260960pgn.208.1554088339769; Sun, 31 Mar 2019 20:12:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 10:11:51 +0700 Message-Id: <20190401031155.21293-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190401031155.21293-1-richard.henderson@linaro.org> References: <20190401031155.21293-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, palmer@sifive.com, Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Special handling for IMM=3D=3D0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvc.inc.c | 47 ------------------------- target/riscv/translate.c | 6 ++++ target/riscv/insn16.decode | 12 +++---- 3 files changed, 12 insertions(+), 53 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index dfb46a2348..691b1e2725 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -97,37 +97,6 @@ static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_= c_addi16sp_lui *a) return false; } =20 -static bool trans_c_srli(DisasContext *ctx, arg_c_srli *a) -{ - int shamt =3D a->shamt; - if (shamt =3D=3D 0) { - /* For RV128 a shamt of 0 means a shift by 64 */ - shamt =3D 64; - } - /* Ensure, that shamt[5] is zero for RV32 */ - if (shamt >=3D TARGET_LONG_BITS) { - return false; - } - - arg_srli arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .shamt =3D a->shamt = }; - return trans_srli(ctx, &arg); -} - -static bool trans_c_srai(DisasContext *ctx, arg_c_srai *a) -{ - int shamt =3D a->shamt; - if (shamt =3D=3D 0) { - /* For RV128 a shamt of 0 means a shift by 64 */ - shamt =3D 64; - } - /* Ensure, that shamt[5] is zero for RV32 */ - if (shamt >=3D TARGET_LONG_BITS) { - return false; - } - - arg_srai arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .shamt =3D a->shamt = }; - return trans_srai(ctx, &arg); -} =20 static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) { @@ -147,22 +116,6 @@ static bool trans_c_addw(DisasContext *ctx, arg_c_addw= *a) #endif } =20 -static bool trans_c_slli(DisasContext *ctx, arg_c_slli *a) -{ - int shamt =3D a->shamt; - if (shamt =3D=3D 0) { - /* For RV128 a shamt of 0 means a shift by 64 */ - shamt =3D 64; - } - /* Ensure, that shamt[5] is zero for RV32 */ - if (shamt >=3D TARGET_LONG_BITS) { - return false; - } - - arg_slli arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .shamt =3D a->shamt = }; - return trans_slli(ctx, &arg); -} - static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) { #ifdef TARGET_RISCV32 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9e016d8e50..a1cd29f80f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -538,6 +538,12 @@ static int ex_rvc_register(int reg) return 8 + reg; } =20 +static int ex_rvc_shifti(int imm) +{ + /* For RV128 a shamt of 0 means a shift by 64. */ + return imm ? imm : 64; +} + /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" =20 diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index d0cc778bc9..add9cf3923 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -30,7 +30,7 @@ %imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=3Dex_shift_1 %imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=3Dex_shift_1 =20 -%nzuimm_6bit 12:1 2:5 +%shimm_6bit 12:1 2:5 !function=3Dex_rvc_shifti %uimm_6bit_ld 2:3 12:1 5:2 !function=3Dex_shift_3 %uimm_6bit_lw 2:2 12:1 4:3 !function=3Dex_shift_2 %uimm_6bit_sd 7:3 10:3 !function=3Dex_shift_3 @@ -94,9 +94,9 @@ uimm_sdsp=3D%uimm_6bit_sd rs2=3D%rs2_5 =20 @c_shift ... . .. ... ..... .. \ - &shift rd=3D%rs1_3 rs1=3D%rs1_3 shamt=3D%nzuimm_6bit + &shift rd=3D%rs1_3 rs1=3D%rs1_3 shamt=3D%shimm_6bit @c_shift2 ... . .. ... ..... .. \ - &shift rd=3D%rd rs1=3D%rd shamt=3D%nzuimm_6bit + &shift rd=3D%rd rs1=3D%rd shamt=3D%shimm_6bit =20 @c_andi ... . .. ... ..... .. &i imm=3D%imm_ci rs1=3D%rs1_3 rd=3D%= rs1_3 =20 @@ -114,8 +114,8 @@ addi 000 . ..... ..... 01 @ci c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm ma= nually addi 010 . ..... ..... 01 @c_li c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with= C.LUI -c_srli 100 . 00 ... ..... 01 @c_shift -c_srai 100 . 01 ... ..... 01 @c_shift +srli 100 . 00 ... ..... 01 @c_shift +srai 100 . 01 ... ..... 01 @c_shift andi 100 . 10 ... ..... 01 @c_andi sub 100 0 11 ... 00 ... 01 @cs_2 xor 100 0 11 ... 01 ... 01 @cs_2 @@ -128,7 +128,7 @@ beq 110 ... ... ..... 01 @cb_z bne 111 ... ... ..... 01 @cb_z =20 # *** RV64C Standard Extension (Quadrant 2) *** -c_slli 000 . ..... ..... 10 @c_shift2 +slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp lw 010 . ..... ..... 10 @c_lwsp c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWS= P:RV32 --=20 2.17.1 From nobody Fri May 17 01:43:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554088480859220.44266012896196; Sun, 31 Mar 2019 20:14:40 -0700 (PDT) Received: from localhost ([127.0.0.1]:33592 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnP9-00083G-NZ for importer@patchew.org; Sun, 31 Mar 2019 23:14:35 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39051) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnN3-0006rI-Ow for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hAnN2-0002tM-7k for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:25 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:37305) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hAnN1-0002t2-Ux for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:24 -0400 Received: by mail-pg1-x544.google.com with SMTP id q206so3992883pgq.4 for ; Sun, 31 Mar 2019 20:12:23 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id c1sm11843954pfd.114.2019.03.31.20.12.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 31 Mar 2019 20:12:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zVkrbUuoiJ5PF3J+0B4MA51B6b0CZ7ZDOOl2e2CcX9k=; b=EOzREzVpmWT1ChQv4qBhettpX7mpR19ncOTqVc1UDhHYOcdAZP1Sxr0hkGDJOO+pIR skiAOBShJ1CUAsDxL0HWPXArY9kC3NRpOJDG/d0zpxEwIJ89/2SR3ZhMRMqGW7RD4mbU 0FIJPWcsnapGVsH+cvlF4qScw1ONgrDdvOVCG1v2H58ULubNAw4ZyekXU+Gcca9Vk8Wm kyHP0h0eGCgGY+KDj2a7x64cT+lFIDzKZeoW6dVi5ACyJVsD5NKwJqdoBxQ3njqO+XLL Qk1bAtJUa8LPU9+ZMidaufCXHW0ms1lv+x06U6capxR4wiM8++ECCzOqCsQKT2CflgrN XATg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zVkrbUuoiJ5PF3J+0B4MA51B6b0CZ7ZDOOl2e2CcX9k=; b=Rvvunf1FJU03Nq+c+hnKY83v5PHZHF/MmBemrRoHXBl5s48Q7p5dSup+KW9Ds8XTj/ gTNG0kEtYqmJKzZaPMu2CGn9EB4047Aoa7aSz/H4CQJTnHryRryuf9DaCKcp3ieOebBp iXNix3AmYVyY9oN1jINlD3qBlIaX5yC1ho7AHqNEckH3Av8kqCNkXQoQGlqC2Rdf5EQs 2xFNCLtAMqzCcp74SJqSb0p2TKR6BPo2QJTDewKZQHFVIhC/7yHpFgYHS5qMlAyeqR6R nTZ832lXVNP0fA/Osu6C9cFBmHQUiXD82I3y5aDCHNC0bDDYCuPRYYCMQvX7O0ked+q7 B18w== X-Gm-Message-State: APjAAAUTS+MY0wBJXCUIWLdX1SEhyk1yLKzP+5cf4LneidM839dtrZ0Z ZHQxz53PAqGeiR9SC4kVi5AyLtmlHcDbvg== X-Google-Smtp-Source: APXvYqyzhRH1XqCEtig9HPfxq+2X/Cc+ucNc3KpsB2yWvjl/yZmadZbCZCWhTFaquJ1p1JGNiYO2ww== X-Received: by 2002:a63:4144:: with SMTP id o65mr58722809pga.241.1554088342732; Sun, 31 Mar 2019 20:12:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 10:11:52 +0700 Message-Id: <20190401031155.21293-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190401031155.21293-1-richard.henderson@linaro.org> References: <20190401031155.21293-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH for-4.1 5/8] target/riscv: Use pattern groups in insn16.decode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, palmer@sifive.com, Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvc.inc.c | 63 ------------------------- target/riscv/insn_trans/trans_rvi.inc.c | 6 +++ target/riscv/insn16.decode | 29 +++++++++--- 3 files changed, 29 insertions(+), 69 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c index 691b1e2725..43bff97f66 100644 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ b/target/riscv/insn_trans/trans_rvc.inc.c @@ -18,16 +18,6 @@ * this program. If not, see . */ =20 -static bool trans_c_addi4spn(DisasContext *ctx, arg_c_addi4spn *a) -{ - if (a->nzuimm =3D=3D 0) { - /* Reserved in ISA */ - return false; - } - arg_addi arg =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->nzuimm }; - return trans_addi(ctx, &arg); -} - static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) { #ifdef TARGET_RISCV32 @@ -79,25 +69,6 @@ static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_j= al_addiw *a) #endif } =20 -static bool trans_c_addi16sp_lui(DisasContext *ctx, arg_c_addi16sp_lui *a) -{ - if (a->rd =3D=3D 2) { - /* C.ADDI16SP */ - arg_addi arg =3D { .rd =3D 2, .rs1 =3D 2, .imm =3D a->imm_addi16sp= }; - return trans_addi(ctx, &arg); - } else if (a->imm_lui !=3D 0) { - /* C.LUI */ - if (a->rd =3D=3D 0) { - /* Hint: insn is valid but does not affect state */ - return true; - } - arg_lui arg =3D { .rd =3D a->rd, .imm =3D a->imm_lui }; - return trans_lui(ctx, &arg); - } - return false; -} - - static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) { #ifdef TARGET_RISCV64 @@ -130,40 +101,6 @@ static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_= c_flwsp_ldsp *a) return false; } =20 -static bool trans_c_jr_mv(DisasContext *ctx, arg_c_jr_mv *a) -{ - if (a->rd !=3D 0 && a->rs2 =3D=3D 0) { - /* C.JR */ - arg_jalr arg =3D { .rd =3D 0, .rs1 =3D a->rd, .imm =3D 0 }; - return trans_jalr(ctx, &arg); - } else if (a->rd !=3D 0 && a->rs2 !=3D 0) { - /* C.MV */ - arg_add arg =3D { .rd =3D a->rd, .rs1 =3D 0, .rs2 =3D a->rs2 }; - return trans_add(ctx, &arg); - } - return false; -} - -static bool trans_c_ebreak_jalr_add(DisasContext *ctx, arg_c_ebreak_jalr_a= dd *a) -{ - if (a->rd =3D=3D 0 && a->rs2 =3D=3D 0) { - /* C.EBREAK */ - arg_ebreak arg =3D { }; - return trans_ebreak(ctx, &arg); - } else if (a->rd !=3D 0) { - if (a->rs2 =3D=3D 0) { - /* C.JALR */ - arg_jalr arg =3D { .rd =3D 1, .rs1 =3D a->rd, .imm =3D 0 }; - return trans_jalr(ctx, &arg); - } else { - /* C.ADD */ - arg_add arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .rs2 =3D a->r= s2 }; - return trans_add(ctx, &arg); - } - } - return false; -} - static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) { #ifdef TARGET_RISCV32 diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index d420a4d8b2..caf91f9a05 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -18,6 +18,12 @@ * this program. If not, see . */ =20 +static bool trans_illegal(DisasContext *ctx, arg_empty *a) +{ + gen_exception_illegal(ctx); + return true; +} + static bool trans_lui(DisasContext *ctx, arg_lui *a) { if (a->rd !=3D 0) { diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index add9cf3923..3c79edf1c9 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -70,7 +70,6 @@ # Formats 16: @cr .... ..... ..... .. &r rs2=3D%rs2_5 rs1=3D%rd = %rd @ci ... . ..... ..... .. &i imm=3D%imm_ci rs1=3D%rd = %rd -@ciw ... ........ ... .. &ciw nzuimm=3D%nzuimm_ciw rd= =3D%rs2_3 @cl_d ... ... ... .. ... .. &i imm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 @cl_w ... ... ... .. ... .. &i imm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 @cl ... ... ... .. ... .. &cl rs1=3D%rs1_3 rd= =3D%rs2_3 @@ -86,8 +85,12 @@ @c_sdsp ... . ..... ..... .. &s imm=3D%uimm_6bit_sd rs1=3D2 rs2= =3D%rs2_5 @c_swsp ... . ..... ..... .. &s imm=3D%uimm_6bit_sw rs1=3D2 rs2= =3D%rs2_5 @c_li ... . ..... ..... .. &i imm=3D%imm_ci rs1=3D0 %rd +@c_lui ... . ..... ..... .. &u imm=3D%imm_lui %rd +@c_jalr ... . ..... ..... .. &i imm=3D0 rs1=3D%rd +@c_mv ... . ..... ..... .. &i imm=3D0 rs1=3D%rs2_5 %rd =20 -@c_addi16sp_lui ... . ..... ..... .. &caddi16sp_lui %imm_lui %imm_addi16s= p %rd +@c_addi4spn ... . ..... ..... .. &i imm=3D%nzuimm_ciw rs1=3D2 rd=3D%r= s2_3 +@c_addi16sp ... . ..... ..... .. &i imm=3D%imm_addi16sp rs1=3D2 rd=3D2 @c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=3D%uimm_6bit= _lw \ uimm_ldsp=3D%uimm_6bit_ld %rd @c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=3D%uimm_6bit= _sw \ @@ -101,7 +104,11 @@ @c_andi ... . .. ... ..... .. &i imm=3D%imm_ci rs1=3D%rs1_3 rd=3D%= rs1_3 =20 # *** RV64C Standard Extension (Quadrant 0) *** -c_addi4spn 000 ........ ... 00 @ciw +{ + # Opcode of all zeros is illegal; rd !=3D 0, nzuimm =3D=3D 0 is reserved. + illegal 000 000 000 00 --- 00 + addi 000 ... ... .. ... 00 @c_addi4spn +} fld 001 ... ... .. ... 00 @cl_d lw 010 ... ... .. ... 00 @cl_w c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm man= ually @@ -113,7 +120,10 @@ c_fsw_sd 111 --- ... -- ... 00 @cs #Note:= Must parse uimm manually addi 000 . ..... ..... 01 @ci c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm ma= nually addi 010 . ..... ..... 01 @c_li -c_addi16sp_lui 011 . ..... ..... 01 @c_addi16sp_lui # shares opc with= C.LUI +{ + addi 011 . 00010 ..... 01 @c_addi16sp + lui 011 . ..... ..... 01 @c_lui +} srli 100 . 00 ... ..... 01 @c_shift srai 100 . 01 ... ..... 01 @c_shift andi 100 . 10 ... ..... 01 @c_andi @@ -132,8 +142,15 @@ slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp lw 010 . ..... ..... 10 @c_lwsp c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWS= P:RV32 -c_jr_mv 100 0 ..... ..... 10 @cr -c_ebreak_jalr_add 100 1 ..... ..... 10 @cr +{ + jalr 100 0 ..... 00000 10 @c_jalr rd=3D0 # C.JR + addi 100 0 ..... ..... 10 @c_mv +} +{ + ebreak 100 1 00000 00000 10 + jalr 100 1 ..... 00000 10 @c_jalr rd=3D1 # C.JALR + add 100 1 ..... ..... 10 @cr +} fsd 101 ...... ..... 10 @c_sdsp sw 110 . ..... ..... 10 @c_swsp c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWS= P:RV32 --=20 2.17.1 From nobody Fri May 17 01:43:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554088823321186.8367831511731; Sun, 31 Mar 2019 20:20:23 -0700 (PDT) Received: from localhost ([127.0.0.1]:35028 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnUi-00048n-Aj for importer@patchew.org; Sun, 31 Mar 2019 23:20:20 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39077) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnN6-0006up-W9 for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hAnN5-0002w6-4c for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:28 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:43247) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hAnN4-0002vq-Ro for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:27 -0400 Received: by mail-pg1-x541.google.com with SMTP id z9so3980072pgu.10 for ; Sun, 31 Mar 2019 20:12:26 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id c1sm11843954pfd.114.2019.03.31.20.12.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 31 Mar 2019 20:12:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+OJQdORZDRU7WkHu31V9fVmgGTMo6A9pTcblDt0OwEI=; b=EH3P00eXI0W7wPZoRmVt5k0DVZ8ylR1HAg/8xzIjxZlj17RXQ3HVFdl/rWg8j4noc9 MnoEpEuLHZhrZ6qQEkxVsuRqIJSnXMtMVNU5IoGwlcC5i7C/aMpmlkZM85jaOtbOuK2Y AnPMEHYPSa7o0rgVV/j+sxhu6Z6Zs1nfw+ztOttlBDb+dLdDlDpd6bFtjFiohzx84doZ UCTGamFYvcVQe5vvV9EcBMcq+6GXjmbZdmXJB6QcFgcAckCRY0TNmu9nG123HZRAz6md +YshGqvRhpi2IKqkFjw/UyNCxMLlteWlXdikAOlA0uJa+hLSB4qyCsCBdTXD6V/bbKLw OzeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+OJQdORZDRU7WkHu31V9fVmgGTMo6A9pTcblDt0OwEI=; b=syZacwfN6ClpbX/mq/21UREMjtTsp0CGb5AYkayvkpD2wEvpdRb3MYJqASn8bC/BF+ +pLSj+K8xCck7MDJLgNa6tUEcXHUi12uwaR8wnzgUYxCMhSR1BpXB+ZRKLTmY23AMxfS nBnChNqh5ZftCJ6umUy+vIMXLeRFzYeZ60ddnMDGdqyKK0wmY0qLJ9jrHdjv1xqjOFSb zpb9FudIvcpMg2xOO1YiyoX965bhRRiCk/Oow/aM5fIIaesZbm+PQo10mlLvMAc0EkYT Rz1Mx1/IdzGSx8mp4VkLz4hHQwkxxdQx7H32wW1iBQTGjBI5iThAqAV2mM+QUYUrZWgx s2uA== X-Gm-Message-State: APjAAAUXf3T80pMscIXtzVQW3CqtJh6w28tMKUiOrFgtQsjmqqsbGtdC zGufy1u211lLiTkhpnMlBlzoVwiYEp9RLQ== X-Google-Smtp-Source: APXvYqyjkiPPxbFMPLDYEoBL3QGnC8hV+w6bxbmCkpTbE0gBlVPZosNYOzNSmScsVz9FP5Tz0NkzBw== X-Received: by 2002:a63:b305:: with SMTP id i5mr12663409pgf.274.1554088345512; Sun, 31 Mar 2019 20:12:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 10:11:53 +0700 Message-Id: <20190401031155.21293-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190401031155.21293-1-richard.henderson@linaro.org> References: <20190401031155.21293-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, palmer@sifive.com, Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvc.inc.c | 115 ------------------------ target/riscv/translate.c | 2 - target/riscv/Makefile.objs | 9 +- target/riscv/insn16-32.decode | 28 ++++++ target/riscv/insn16-64.decode | 30 +++++++ target/riscv/insn16.decode | 35 +------- 6 files changed, 67 insertions(+), 152 deletions(-) delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c create mode 100644 target/riscv/insn16-32.decode create mode 100644 target/riscv/insn16-64.decode diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_tr= ans/trans_rvc.inc.c deleted file mode 100644 index 43bff97f66..0000000000 --- a/target/riscv/insn_trans/trans_rvc.inc.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * RISC-V translation routines for the RVC Compressed Instruction Set. - * - * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu - * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de - * Bastian Koppelmann, kbastian@mail.uni-paderborn.de - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ - -static bool trans_c_flw_ld(DisasContext *ctx, arg_c_flw_ld *a) -{ -#ifdef TARGET_RISCV32 - /* C.FLW ( RV32FC-only ) */ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - arg_i arg; - decode_insn16_extract_cl_w(&arg, ctx->opcode); - return trans_flw(ctx, &arg); -#else - /* C.LD ( RV64C/RV128C-only ) */ - arg_i arg; - decode_insn16_extract_cl_d(&arg, ctx->opcode); - return trans_ld(ctx, &arg); -#endif -} - -static bool trans_c_fsw_sd(DisasContext *ctx, arg_c_fsw_sd *a) -{ -#ifdef TARGET_RISCV32 - /* C.FSW ( RV32FC-only ) */ - REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); - - arg_s arg; - decode_insn16_extract_cs_w(&arg, ctx->opcode); - return trans_fsw(ctx, &arg); -#else - /* C.SD ( RV64C/RV128C-only ) */ - arg_s arg; - decode_insn16_extract_cs_d(&arg, ctx->opcode); - return trans_sd(ctx, &arg); -#endif -} - -static bool trans_c_jal_addiw(DisasContext *ctx, arg_c_jal_addiw *a) -{ -#ifdef TARGET_RISCV32 - /* C.JAL */ - arg_j tmp; - decode_insn16_extract_cj(&tmp, ctx->opcode); - arg_jal arg =3D { .rd =3D 1, .imm =3D tmp.imm }; - return trans_jal(ctx, &arg); -#else - /* C.ADDIW */ - arg_addiw arg =3D { .rd =3D a->rd, .rs1 =3D a->rd, .imm =3D a->imm }; - return trans_addiw(ctx, &arg); -#endif -} - -static bool trans_c_subw(DisasContext *ctx, arg_c_subw *a) -{ -#ifdef TARGET_RISCV64 - return trans_subw(ctx, a); -#else - return false; -#endif -} - -static bool trans_c_addw(DisasContext *ctx, arg_c_addw *a) -{ -#ifdef TARGET_RISCV64 - return trans_addw(ctx, a); -#else - return false; -#endif -} - -static bool trans_c_flwsp_ldsp(DisasContext *ctx, arg_c_flwsp_ldsp *a) -{ -#ifdef TARGET_RISCV32 - /* C.FLWSP */ - arg_flw arg_flw =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm_flws= p }; - return trans_flw(ctx, &arg_flw); -#else - /* C.LDSP */ - arg_ld arg_ld =3D { .rd =3D a->rd, .rs1 =3D 2, .imm =3D a->uimm_ldsp }; - return trans_ld(ctx, &arg_ld); -#endif - return false; -} - -static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a) -{ -#ifdef TARGET_RISCV32 - /* C.FSWSP */ - arg_fsw a_fsw =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm_fsws= p }; - return trans_fsw(ctx, &a_fsw); -#else - /* C.SDSP */ - arg_sd a_sd =3D { .rs1 =3D 2, .rs2 =3D a->rs2, .imm =3D a->uimm_sdsp }; - return trans_sd(ctx, &a_sd); -#endif -} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a1cd29f80f..50d8f58e4b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -685,8 +685,6 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, =20 #pragma GCC diagnostic pop =20 -#include "insn_trans/trans_rvc.inc.c" - static void decode_opc(DisasContext *ctx) { /* check for compressed insn */ diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index c7a1b063ed..b1c79bc1d1 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -5,16 +5,19 @@ DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py decode32-y =3D $(SRC_PATH)/target/riscv/insn32.decode decode32-$(TARGET_RISCV64) +=3D $(SRC_PATH)/target/riscv/insn32-64.decode =20 +decode16-y =3D $(SRC_PATH)/target/riscv/insn16.decode +decode16-$(TARGET_RISCV32) +=3D $(SRC_PATH)/target/riscv/insn16-32.decode +decode16-$(TARGET_RISCV64) +=3D $(SRC_PATH)/target/riscv/insn16-64.decode + target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \ $(decode32-y), "GEN", $(TARGET_DIR)$@) =20 -target/riscv/decode_insn16.inc.c: \ - $(SRC_PATH)/target/riscv/insn16.decode $(DECODETREE) +target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \ - --insnwidth 16 $<, "GEN", $(TARGET_DIR)$@) + --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@) =20 target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ target/riscv/decode_insn16.inc.c diff --git a/target/riscv/insn16-32.decode b/target/riscv/insn16-32.decode new file mode 100644 index 0000000000..0819b17028 --- /dev/null +++ b/target/riscv/insn16-32.decode @@ -0,0 +1,28 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along = with +# this program. If not, see . + +# *** RV32C Standard Extension (Quadrant 0) *** +flw 011 ... ... .. ... 00 @cl_w +fsw 111 ... ... .. ... 00 @cs_w + +# *** RV32C Standard Extension (Quadrant 1) *** +jal 001 ........... 01 @cj rd=3D1 # C.JAL + +# *** RV32C Standard Extension (Quadrant 2) *** +flw 011 . ..... ..... 10 @c_lwsp +fsw 111 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn16-64.decode b/target/riscv/insn16-64.decode new file mode 100644 index 0000000000..055859d29f --- /dev/null +++ b/target/riscv/insn16-64.decode @@ -0,0 +1,30 @@ +# +# RISC-V translation routines for the RVXI Base Integer Instruction Set. +# +# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de +# Bastian Koppelmann, kbastian@mail.uni-paderborn.de +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2 or later, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License along = with +# this program. If not, see . + +# *** RV64C Standard Extension (Quadrant 0) *** +ld 011 ... ... .. ... 00 @cl_d +sd 111 ... ... .. ... 00 @cs_d + +# *** RV64C Standard Extension (Quadrant 1) *** +addiw 001 . ..... ..... 01 @ci +subw 100 1 11 ... 00 ... 01 @cs_2 +addw 100 1 11 ... 01 ... 01 @cs_2 + +# *** RV64C Standard Extension (Quadrant 2) *** +ld 011 . ..... ..... 10 @c_ldsp +sd 111 . ..... ..... 10 @c_sdsp diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 3c79edf1c9..433c0e8c68 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -50,30 +50,12 @@ &u imm rd !extern &shift shamt rs1 rd !extern =20 -# Argument sets: -&cl rs1 rd -&cl_dw uimm rs1 rd -&ciw nzuimm rd -&cs rs1 rs2 -&cs_dw uimm rs1 rs2 -&cb imm rs1 -&cr rd rs2 -&c_shift shamt rd - -&c_ld uimm rd -&c_sd uimm rs2 - -&caddi16sp_lui imm_lui imm_addi16sp rd -&cflwsp_ldsp uimm_flwsp uimm_ldsp rd -&cfswsp_sdsp uimm_fswsp uimm_sdsp rs2 =20 # Formats 16: @cr .... ..... ..... .. &r rs2=3D%rs2_5 rs1=3D%rd = %rd @ci ... . ..... ..... .. &i imm=3D%imm_ci rs1=3D%rd = %rd @cl_d ... ... ... .. ... .. &i imm=3D%uimm_cl_d rs1=3D%rs1_3 = rd=3D%rs2_3 @cl_w ... ... ... .. ... .. &i imm=3D%uimm_cl_w rs1=3D%rs1_3 = rd=3D%rs2_3 -@cl ... ... ... .. ... .. &cl rs1=3D%rs1_3 rd= =3D%rs2_3 -@cs ... ... ... .. ... .. &cs rs1=3D%rs1_3 rs= 2=3D%rs2_3 @cs_2 ... ... ... .. ... .. &r rs2=3D%rs2_3 rs1=3D%rs1_3 = rd=3D%rs1_3 @cs_d ... ... ... .. ... .. &s imm=3D%uimm_cl_d rs1=3D%rs1_3 = rs2=3D%rs2_3 @cs_w ... ... ... .. ... .. &s imm=3D%uimm_cl_w rs1=3D%rs1_3 = rs2=3D%rs2_3 @@ -91,10 +73,6 @@ =20 @c_addi4spn ... . ..... ..... .. &i imm=3D%nzuimm_ciw rs1=3D2 rd=3D%r= s2_3 @c_addi16sp ... . ..... ..... .. &i imm=3D%imm_addi16sp rs1=3D2 rd=3D2 -@c_flwsp_ldsp ... . ..... ..... .. &cflwsp_ldsp uimm_flwsp=3D%uimm_6bit= _lw \ - uimm_ldsp=3D%uimm_6bit_ld %rd -@c_fswsp_sdsp ... . ..... ..... .. &cfswsp_sdsp uimm_fswsp=3D%uimm_6bit= _sw \ - uimm_sdsp=3D%uimm_6bit_sd rs2=3D%rs2_5 =20 @c_shift ... . .. ... ..... .. \ &shift rd=3D%rs1_3 rs1=3D%rs1_3 shamt=3D%shimm_6bit @@ -103,7 +81,7 @@ =20 @c_andi ... . .. ... ..... .. &i imm=3D%imm_ci rs1=3D%rs1_3 rd=3D%= rs1_3 =20 -# *** RV64C Standard Extension (Quadrant 0) *** +# *** RV32/64C Standard Extension (Quadrant 0) *** { # Opcode of all zeros is illegal; rd !=3D 0, nzuimm =3D=3D 0 is reserved. illegal 000 000 000 00 --- 00 @@ -111,14 +89,11 @@ } fld 001 ... ... .. ... 00 @cl_d lw 010 ... ... .. ... 00 @cl_w -c_flw_ld 011 --- ... -- ... 00 @cl #Note: Must parse uimm man= ually fsd 101 ... ... .. ... 00 @cs_d sw 110 ... ... .. ... 00 @cs_w -c_fsw_sd 111 --- ... -- ... 00 @cs #Note: Must parse uimm man= ually =20 -# *** RV64C Standard Extension (Quadrant 1) *** +# *** RV32/64C Standard Extension (Quadrant 1) *** addi 000 . ..... ..... 01 @ci -c_jal_addiw 001 . ..... ..... 01 @ci #Note: parse rd and/or imm ma= nually addi 010 . ..... ..... 01 @c_li { addi 011 . 00010 ..... 01 @c_addi16sp @@ -131,17 +106,14 @@ sub 100 0 11 ... 00 ... 01 @cs_2 xor 100 0 11 ... 01 ... 01 @cs_2 or 100 0 11 ... 10 ... 01 @cs_2 and 100 0 11 ... 11 ... 01 @cs_2 -c_subw 100 1 11 ... 00 ... 01 @cs_2 -c_addw 100 1 11 ... 01 ... 01 @cs_2 jal 101 ........... 01 @cj rd=3D0 # C.J beq 110 ... ... ..... 01 @cb_z bne 111 ... ... ..... 01 @cb_z =20 -# *** RV64C Standard Extension (Quadrant 2) *** +# *** RV32/64C Standard Extension (Quadrant 2) *** slli 000 . ..... ..... 10 @c_shift2 fld 001 . ..... ..... 10 @c_ldsp lw 010 . ..... ..... 10 @c_lwsp -c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp #C.LDSP:RV64;C.FLWS= P:RV32 { jalr 100 0 ..... 00000 10 @c_jalr rd=3D0 # C.JR addi 100 0 ..... ..... 10 @c_mv @@ -153,4 +125,3 @@ c_flwsp_ldsp 011 . ..... ..... 10 @c_flwsp_ldsp = #C.LDSP:RV64;C.FLWSP:RV32 } fsd 101 ...... ..... 10 @c_sdsp sw 110 . ..... ..... 10 @c_swsp -c_fswsp_sdsp 111 . ..... ..... 10 @c_fswsp_sdsp #C.SDSP:RV64;C.FSWS= P:RV32 --=20 2.17.1 From nobody Fri May 17 01:43:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1554088677317359.7358870610202; Sun, 31 Mar 2019 20:17:57 -0700 (PDT) Received: from localhost ([127.0.0.1]:34427 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnSN-0002gp-2v for importer@patchew.org; Sun, 31 Mar 2019 23:17:55 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnN8-0006wq-SQ for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hAnN7-0002wz-SG for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:30 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:43057) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hAnN7-0002wm-Ld for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:29 -0400 Received: by mail-pf1-x444.google.com with SMTP id c8so3788025pfd.10 for ; Sun, 31 Mar 2019 20:12:29 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id c1sm11843954pfd.114.2019.03.31.20.12.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 31 Mar 2019 20:12:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bnXtqozOkG0z0qCnfkwAnWD2s6dn2+EP98mQY8o0DN4=; b=IwTmtmSFyyyZOKW4PIIAABH7C7rV3H25nVU+95yPtMMnf2GV081bdsmG8E8Yag9pl2 tOO4GUnhCIzoM6M5Pflg5NFKcxyUcFex+JAqR7V7KpcwN3tiuSIkKagq3vmENnuo9VUz 6a7unnmxOLkGIlJvTvU7rC6zWvlnue/68F3Yt3bwUOClIGr2BsCGP63/7UE0qdAcTkRb OkyTQW1EseXuic01AELwwJ6V0vV0U9ave0q6vUYybHfc7xZSWsIFU43Aizt60A4Gapnl G5nxWEcbxl6sUC91PL9pwKr+rcih0qMP/QhDZ7cdg98SZmQ+ukOrbmneSlkQfOkorjOC P+Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bnXtqozOkG0z0qCnfkwAnWD2s6dn2+EP98mQY8o0DN4=; b=snkBRuQw26ewi4K5wy5Ze+G5LP0zSdJO2LpPG0MsGDSpxUlbTZkS8T1lyf+tvA4KFI H0S0jliBGKyuPp29yunBrHnImsBPL5/XftlyHWXWiK9D1hzNppC4duAuf30qdsQqadUY eeLXEqcFY3ReuyDn9srsLwn7r72uCV+Kx2zIgmtB32WTO2VpX3dhikD2jzXbYA1yM2KF vTYJFQDqNxWCE1Aygz11zAsbV0mSXoIrgvtOKS/PJYEaqu5xSS6mBJdxhnyvCywXm2vV moDVBXr+1GxaKNiFAzqE+uekF0KcwZBzq7AH4px0yUGnbyD1+XbmqqCq8g1bd/YxRDkU nhJQ== X-Gm-Message-State: APjAAAW5BFAk0i6N7raPee26aoC/WAdqBYvl1A99pc/Z++0Qw7mOEKAp PSGX1Gb9AGE9Sa6OSLFdBSxagy3BrH/HKw== X-Google-Smtp-Source: APXvYqxp4uHaZfVU9mNSR9lCIqFQCvItkOxdYZYgLxuCS3KDEaMjQNm+4gmXWwm8AA7WiGHqokzHAQ== X-Received: by 2002:a62:e112:: with SMTP id q18mr9520300pfh.116.1554088348367; Sun, 31 Mar 2019 20:12:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 10:11:54 +0700 Message-Id: <20190401031155.21293-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190401031155.21293-1-richard.henderson@linaro.org> References: <20190401031155.21293-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH for-4.1 7/8] target/riscv: Split gen_arith_imm into functional and temp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, palmer@sifive.com, Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The tcg_gen_fooi_tl functions have some immediate constant folding built in, which match up with some of the riscv asm builtin macros, like mv and not. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt --- target/riscv/insn_trans/trans_rvi.inc.c | 14 +++++++------- target/riscv/translate.c | 19 +++++++++++++++++-- 2 files changed, 24 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index caf91f9a05..620df5f323 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -223,7 +223,7 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a) =20 static bool trans_addi(DisasContext *ctx, arg_addi *a) { - return gen_arith_imm(ctx, a, &tcg_gen_add_tl); + return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl); } =20 static void gen_slt(TCGv ret, TCGv s1, TCGv s2) @@ -239,25 +239,25 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2) =20 static bool trans_slti(DisasContext *ctx, arg_slti *a) { - return gen_arith_imm(ctx, a, &gen_slt); + return gen_arith_imm_tl(ctx, a, &gen_slt); } =20 static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) { - return gen_arith_imm(ctx, a, &gen_sltu); + return gen_arith_imm_tl(ctx, a, &gen_sltu); } =20 static bool trans_xori(DisasContext *ctx, arg_xori *a) { - return gen_arith_imm(ctx, a, &tcg_gen_xor_tl); + return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl); } static bool trans_ori(DisasContext *ctx, arg_ori *a) { - return gen_arith_imm(ctx, a, &tcg_gen_or_tl); + return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl); } static bool trans_andi(DisasContext *ctx, arg_andi *a) { - return gen_arith_imm(ctx, a, &tcg_gen_and_tl); + return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl); } static bool trans_slli(DisasContext *ctx, arg_slli *a) { @@ -364,7 +364,7 @@ static bool trans_and(DisasContext *ctx, arg_and *a) #ifdef TARGET_RISCV64 static bool trans_addiw(DisasContext *ctx, arg_addiw *a) { - return gen_arith_imm(ctx, a, &gen_addw); + return gen_arith_imm_tl(ctx, a, &gen_addw); } =20 static bool trans_slliw(DisasContext *ctx, arg_slliw *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 50d8f58e4b..fb66e886bf 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -547,8 +547,23 @@ static int ex_rvc_shifti(int imm) /* Include the auto-generated decoder for 32 bit insn */ #include "decode_insn32.inc.c" =20 -static bool gen_arith_imm(DisasContext *ctx, arg_i *a, - void(*func)(TCGv, TCGv, TCGv)) +static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, + void (*func)(TCGv, TCGv, target_long)) +{ + TCGv source1; + source1 =3D tcg_temp_new(); + + gen_get_gpr(source1, a->rs1); + + (*func)(source1, source1, a->imm); + + gen_set_gpr(a->rd, source1); + tcg_temp_free(source1); + return true; +} + +static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, + void (*func)(TCGv, TCGv, TCGv)) { TCGv source1, source2; source1 =3D tcg_temp_new(); --=20 2.17.1 From nobody Fri May 17 01:43:48 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15540888687731020.7764736932672; Sun, 31 Mar 2019 20:21:08 -0700 (PDT) Received: from localhost ([127.0.0.1]:35249 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnVO-0004ph-JR for importer@patchew.org; Sun, 31 Mar 2019 23:21:02 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39127) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hAnNC-00070r-I5 for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hAnNB-0002xu-F4 for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:34 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:35447) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hAnNB-0002xh-81 for qemu-devel@nongnu.org; Sun, 31 Mar 2019 23:12:33 -0400 Received: by mail-pf1-x42a.google.com with SMTP id t21so3808726pfe.2 for ; Sun, 31 Mar 2019 20:12:33 -0700 (PDT) Received: from cloudburst.imgcgcw.net ([147.50.13.10]) by smtp.gmail.com with ESMTPSA id c1sm11843954pfd.114.2019.03.31.20.12.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 31 Mar 2019 20:12:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=FhiOeyfHkHtfNyh860mOu1MjVRG+GSdZNydGKNnZxaM=; b=u2ddnX2Jbcuy0y20WdQPkIYQhxH8vNAsfGSQChoFrIigA5Z2tihdJK9K8A6WyqScfY D3G25HzJxNY49I+wldtkXoha1lHYSOovrNcN81Hq3aZn+IfATHSyxT0WXqHI6YEFDIb1 CU/SwQwtDHtkwLGDyk2kcP2xU2vpuCpCWlW4UdV+KTI0ND30AJZHkBzwZtZSznLBCJY7 TgerYK22w0Lhl+2R0TwfiU79hxqQMgFpChMb6ah0QF+Ned5CG3yT7/2l3+dIdIw8jT6g nF85gVYal1bzN5vRaGMyG+lu62rhLL+Q1Qc7W5w7fzY0Qh/uiSJ7nJBpiIfQPj05GaZu 5iMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FhiOeyfHkHtfNyh860mOu1MjVRG+GSdZNydGKNnZxaM=; b=m8TbVGT+0HFVWMoyrg2xlRD+zmOrB9JhxGyr0L1OaoUQ6iulaqWW+9pNs34HXKVXoR BkRYoWPjRaXXuQYq9eiBzTi5aN0fbN++RqGFxBLSQRbwc0ehFmw5UjDTIPxSIQLtvmVz MeaPGZjrTZPf7wT6OgyHhOKYYcTjUwrp8ItzFOoZMRm9emXSEC+Z4TyPydVluIBHdcgk aQF2WxmZn5yRDZpF5xzj9kbrZX85PVecomL4vW/muf+BonZrD8/X/y1rm+whohyaZLdg sDGIDcvRYyW5rE+CnPUBl/VwjSX7lmJEkkIVn0n952lxQIS7CuEE8mKToCx9Av67Ybp/ xGWg== X-Gm-Message-State: APjAAAVFZ6xsNaOM8+yKTuihzjiGJop41qnuOTkWc7NBO37d5Yi+1qqq 46Lq4EzX8fjpqOrdNchbHo3btXMuoPZwhg== X-Google-Smtp-Source: APXvYqy/ET0VQKtjZjwftb2RI0SmTVMuTu1rKFB2dUFEExvHlKmCTYZALYdxyBqRQLEfWwF/Jx3Tlw== X-Received: by 2002:a62:bd09:: with SMTP id a9mr59551934pff.61.1554088352023; Sun, 31 Mar 2019 20:12:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 1 Apr 2019 10:11:55 +0700 Message-Id: <20190401031155.21293-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190401031155.21293-1-richard.henderson@linaro.org> References: <20190401031155.21293-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PATCH for-4.1 8/8] target/riscv: Remove spaces from register names X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kbastian@mail.uni-paderborn.de, palmer@sifive.com, Alistair.Francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" These extra spaces make the "-d op" dump look weird. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d61bce6d55..624528efb5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -29,17 +29,17 @@ static const char riscv_exts[26] =3D "IEMAFDQCLBJTPVNSUHKORWXYZG"; =20 const char * const riscv_int_regnames[] =3D { - "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ", - "s0 ", "s1 ", "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", - "a6 ", "a7 ", "s2 ", "s3 ", "s4 ", "s5 ", "s6 ", "s7 ", - "s8 ", "s9 ", "s10 ", "s11 ", "t3 ", "t4 ", "t5 ", "t6 " + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", + "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", + "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" }; =20 const char * const riscv_fpr_regnames[] =3D { - "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ", "ft7 ", - "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ", "fa5 ", - "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ", "fs7 ", - "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10", "ft11" + "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", + "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", + "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", + "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" }; =20 const char * const riscv_excp_names[] =3D { --=20 2.17.1