hw/riscv/sifive_prci.c | 51 ++++++++++++++++++++++++++++------ include/hw/riscv/sifive_prci.h | 32 +++++++++++++++++++++ 2 files changed, 75 insertions(+), 8 deletions(-)
From: Nathaniel Graff <nathaniel.graff@sifive.com>
Writes to the SiFive PRCI registers are preserved while leaving the
ready bits set for the HFX/HFR oscillators and the lock bit set for the
PLL.
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
hw/riscv/sifive_prci.c | 51 ++++++++++++++++++++++++++++------
include/hw/riscv/sifive_prci.h | 32 +++++++++++++++++++++
2 files changed, 75 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
index 0910ea32c1a5..1435423a23e4 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_prci.c
@@ -23,15 +23,19 @@
#include "target/riscv/cpu.h"
#include "hw/riscv/sifive_prci.h"
-/* currently implements enough to mock freedom-e-sdk BSP clock programming */
-
static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
{
- if (addr == 0 /* PRCI_HFROSCCFG */) {
- return 1 << 31; /* ROSC_RDY */
- }
- if (addr == 8 /* PRCI_PLLCFG */) {
- return 1 << 31; /* PLL_LOCK */
+ SiFivePRCIState *s = opaque;
+ switch(addr)
+ {
+ case SIFIVE_PRCI_HFROSCCFG:
+ return s->hfrosccfg;
+ case SIFIVE_PRCI_HFXOSCCFG:
+ return s->hfxosccfg;
+ case SIFIVE_PRCI_PLLCFG:
+ return s->pllcfg;
+ case SIFIVE_PRCI_PLLOUTDIV:
+ return s->plloutdiv;
}
hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);
return 0;
@@ -40,7 +44,31 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
static void sifive_prci_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
- /* discard writes */
+ SiFivePRCIState *s = opaque;
+ switch(addr)
+ {
+ case SIFIVE_PRCI_HFROSCCFG:
+ s->hfrosccfg = (uint32_t) val64;
+ /* OSC stays ready */
+ s->hfrosccfg |= SIFIVE_PRCI_HFROSCCFG_RDY;
+ break;
+ case SIFIVE_PRCI_HFXOSCCFG:
+ s->hfxosccfg = (uint32_t) val64;
+ /* OSC stays ready */
+ s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY;
+ break;
+ case SIFIVE_PRCI_PLLCFG:
+ s->pllcfg = (uint32_t) val64;
+ /* PLL stays locked */
+ s->pllcfg |= SIFIVE_PRCI_PLLCFG_LOCK;
+ break;
+ case SIFIVE_PRCI_PLLOUTDIV:
+ s->plloutdiv = (uint32_t) val64;
+ break;
+ default:
+ hw_error("%s: bad write: addr=0x%x v=0x%x\n",
+ __func__, (int)addr, (int)val64);
+ }
}
static const MemoryRegionOps sifive_prci_ops = {
@@ -60,6 +88,13 @@ static void sifive_prci_init(Object *obj)
memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s,
TYPE_SIFIVE_PRCI, 0x8000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+ s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
+ s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN);
+ s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS |
+ SIFIVE_PRCI_PLLCFG_LOCK);
+ s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1;
+
}
static const TypeInfo sifive_prci_info = {
diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h
index b6f4c486cc1e..bd51c4af3c1c 100644
--- a/include/hw/riscv/sifive_prci.h
+++ b/include/hw/riscv/sifive_prci.h
@@ -19,6 +19,34 @@
#ifndef HW_SIFIVE_PRCI_H
#define HW_SIFIVE_PRCI_H
+enum {
+ SIFIVE_PRCI_HFROSCCFG = 0x0,
+ SIFIVE_PRCI_HFXOSCCFG = 0x4,
+ SIFIVE_PRCI_PLLCFG = 0x8,
+ SIFIVE_PRCI_PLLOUTDIV = 0xC
+};
+
+enum {
+ SIFIVE_PRCI_HFROSCCFG_RDY = (1 << 31),
+ SIFIVE_PRCI_HFROSCCFG_EN = (1 << 30)
+};
+
+enum {
+ SIFIVE_PRCI_HFXOSCCFG_RDY = (1 << 31),
+ SIFIVE_PRCI_HFXOSCCFG_EN = (1 << 30)
+};
+
+enum {
+ SIFIVE_PRCI_PLLCFG_PLLSEL = (1 << 16),
+ SIFIVE_PRCI_PLLCFG_REFSEL = (1 << 17),
+ SIFIVE_PRCI_PLLCFG_BYPASS = (1 << 18),
+ SIFIVE_PRCI_PLLCFG_LOCK = (1 << 31)
+};
+
+enum {
+ SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
+};
+
#define TYPE_SIFIVE_PRCI "riscv.sifive.prci"
#define SIFIVE_PRCI(obj) \
@@ -30,6 +58,10 @@ typedef struct SiFivePRCIState {
/*< public >*/
MemoryRegion mmio;
+ uint32_t hfrosccfg;
+ uint32_t hfxosccfg;
+ uint32_t pllcfg;
+ uint32_t plloutdiv;
} SiFivePRCIState;
DeviceState *sifive_prci_create(hwaddr addr);
--
2.19.2
Patchew URL: https://patchew.org/QEMU/20190322002749.26561-1-palmer@sifive.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190322002749.26561-1-palmer@sifive.com
Subject: [Qemu-devel] [PATCH] sifive_prci: Read and write PRCI registers
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20190322002749.26561-1-palmer@sifive.com -> patchew/20190322002749.26561-1-palmer@sifive.com
Switched to a new branch 'test'
ba8be4dcb6 sifive_prci: Read and write PRCI registers
=== OUTPUT BEGIN ===
ERROR: that open brace { should be on the previous line
#35: FILE: hw/riscv/sifive_prci.c:29:
+ switch(addr)
+ {
ERROR: space required before the open parenthesis '('
#35: FILE: hw/riscv/sifive_prci.c:29:
+ switch(addr)
ERROR: that open brace { should be on the previous line
#54: FILE: hw/riscv/sifive_prci.c:48:
+ switch(addr)
+ {
ERROR: space required before the open parenthesis '('
#54: FILE: hw/riscv/sifive_prci.c:48:
+ switch(addr)
ERROR: trailing whitespace
#72: FILE: hw/riscv/sifive_prci.c:66:
+ s->plloutdiv = (uint32_t) val64; $
total: 5 errors, 0 warnings, 115 lines checked
Commit ba8be4dcb6c4 (sifive_prci: Read and write PRCI registers) has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20190322002749.26561-1-palmer@sifive.com/testing.checkpatch/?type=message.
---
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