From nobody Tue May 21 04:57:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (209.51.188.17 [209.51.188.17]) by mx.zohomail.com with SMTPS id 1553214618800978.6035190717889; Thu, 21 Mar 2019 17:30:18 -0700 (PDT) Received: from localhost ([127.0.0.1]:48617 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h784Y-0004Jd-4N for importer@patchew.org; Thu, 21 Mar 2019 20:30:10 -0400 Received: from eggs.gnu.org ([209.51.188.92]:41905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1h782X-0002zS-RY for qemu-devel@nongnu.org; Thu, 21 Mar 2019 20:28:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1h782W-0001a0-NJ for qemu-devel@nongnu.org; Thu, 21 Mar 2019 20:28:05 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:40413) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1h782W-0001YT-61 for qemu-devel@nongnu.org; Thu, 21 Mar 2019 20:28:04 -0400 Received: by mail-pg1-x543.google.com with SMTP id u9so208167pgo.7 for ; Thu, 21 Mar 2019 17:28:04 -0700 (PDT) Received: from localhost (2001-b011-7001-1ed7-23f1-a55b-5e6a-d75e.dynamic-ip6.hinet.net. [2001:b011:7001:1ed7:23f1:a55b:5e6a:d75e]) by smtp.gmail.com with ESMTPSA id p3sm9377942pfp.136.2019.03.21.17.28.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Mar 2019 17:28:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:mime-version:content-transfer-encoding:cc :from:to; bh=P0PmWB4MEKCw4NufvvW/W6VRhua7JfOUfUf8LMy67Nw=; b=RCTCIjMVKFXzVXxYtYpXDxycK0yT878i8qFxOqJ7K9rpmxJRPVPHOk9WGvSvzjkHOw EEUdtFmrYy0TKyvXY1SEZ1yc6UYiPhXcXn1nV65lLfWGpF2zZH1XAradu7AjgMgghd0B 4J7oVCXTOQ37t9ytcLvfC6XvhaVENd1U1XHU+fgIY+TGKxBmXHY0Gw0EypMP9xGquCCv nJUJpmdBIRsk74YXa1jtAD1KUjKb/Kdeqyykb1ThmVic8l9zhptr/ros3jygHnb6dcrl ykBJEBVeuhSg5umpvo34UQWOEN2I2Z8Bc16BllGVGBPza1KnM40r+Esg97YtO2489DiQ 8rdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:mime-version :content-transfer-encoding:cc:from:to; bh=P0PmWB4MEKCw4NufvvW/W6VRhua7JfOUfUf8LMy67Nw=; b=LWuVNr8xrAuROW4W+1pFtHFW/0tP5bXwYJVCFR7KHF9mQQE28NLT8OjwmYc8vF7Oiv SKurtKHIZDOXtuTBF+2H5iUPM3CbtP8YpNePx+NqJy6nEJGMngftT26MG5ShSrs7YCes 0gqi8vWzTMkSCSFmbjkV3Lkvawi2PJLGeYa8D4Yvj4novhgUtOJ3RgM9FXiE2JOrYH4q NQ/lVVyla1oPrpfnUogbkCeTPW1B08X6/XyLziqCcrtKTSglFMxkHKwJsBV9uXQk2UEK UnzV5M1sd7/7KS/wWzJHTQ5O1lJDJU/1CxCP1LtPLqpuGMuyJyDU87JoKkAXY0hbSG1f Rckg== X-Gm-Message-State: APjAAAUbhOwCOYXzFtB7S+aBtbqRsulTOVNsM9xhyuF/PHr4tpdehFNi lqPA09o3LqmtNXfwrgMJg6VcYbwCktY38HW4 X-Google-Smtp-Source: APXvYqxXSVY+r0ZviyvrqKYKwLd4FsEo9W0wW7yURBvoel2f45H0nuK/dqZzpHAICFofnSbgu2Ju6w== X-Received: by 2002:a63:ff0c:: with SMTP id k12mr6031929pgi.358.1553214482844; Thu, 21 Mar 2019 17:28:02 -0700 (PDT) Date: Thu, 21 Mar 2019 17:27:49 -0700 Message-Id: <20190322002749.26561-1-palmer@sifive.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Palmer Dabbelt To: qemu-riscv@nongnu.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH] sifive_prci: Read and write PRCI registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nathaniel Graff , Palmer Dabbelt , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Nathaniel Graff Writes to the SiFive PRCI registers are preserved while leaving the ready bits set for the HFX/HFR oscillators and the lock bit set for the PLL. Signed-off-by: Nathaniel Graff Reviewed-by: Michael Clark Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_prci.c | 51 ++++++++++++++++++++++++++++------ include/hw/riscv/sifive_prci.h | 32 +++++++++++++++++++++ 2 files changed, 75 insertions(+), 8 deletions(-) diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c index 0910ea32c1a5..1435423a23e4 100644 --- a/hw/riscv/sifive_prci.c +++ b/hw/riscv/sifive_prci.c @@ -23,15 +23,19 @@ #include "target/riscv/cpu.h" #include "hw/riscv/sifive_prci.h" =20 -/* currently implements enough to mock freedom-e-sdk BSP clock programming= */ - static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int s= ize) { - if (addr =3D=3D 0 /* PRCI_HFROSCCFG */) { - return 1 << 31; /* ROSC_RDY */ - } - if (addr =3D=3D 8 /* PRCI_PLLCFG */) { - return 1 << 31; /* PLL_LOCK */ + SiFivePRCIState *s =3D opaque; + switch(addr) + { + case SIFIVE_PRCI_HFROSCCFG: + return s->hfrosccfg; + case SIFIVE_PRCI_HFXOSCCFG: + return s->hfxosccfg; + case SIFIVE_PRCI_PLLCFG: + return s->pllcfg; + case SIFIVE_PRCI_PLLOUTDIV: + return s->plloutdiv; } hw_error("%s: read: addr=3D0x%x\n", __func__, (int)addr); return 0; @@ -40,7 +44,31 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr ad= dr, unsigned int size) static void sifive_prci_write(void *opaque, hwaddr addr, uint64_t val64, unsigned int size) { - /* discard writes */ + SiFivePRCIState *s =3D opaque; + switch(addr) + { + case SIFIVE_PRCI_HFROSCCFG: + s->hfrosccfg =3D (uint32_t) val64; + /* OSC stays ready */ + s->hfrosccfg |=3D SIFIVE_PRCI_HFROSCCFG_RDY; + break; + case SIFIVE_PRCI_HFXOSCCFG: + s->hfxosccfg =3D (uint32_t) val64; + /* OSC stays ready */ + s->hfxosccfg |=3D SIFIVE_PRCI_HFXOSCCFG_RDY; + break; + case SIFIVE_PRCI_PLLCFG: + s->pllcfg =3D (uint32_t) val64; + /* PLL stays locked */ + s->pllcfg |=3D SIFIVE_PRCI_PLLCFG_LOCK; + break; + case SIFIVE_PRCI_PLLOUTDIV: + s->plloutdiv =3D (uint32_t) val64;=20 + break; + default: + hw_error("%s: bad write: addr=3D0x%x v=3D0x%x\n", + __func__, (int)addr, (int)val64); + } } =20 static const MemoryRegionOps sifive_prci_ops =3D { @@ -60,6 +88,13 @@ static void sifive_prci_init(Object *obj) memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, TYPE_SIFIVE_PRCI, 0x8000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + s->hfrosccfg =3D (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN= ); + s->hfxosccfg =3D (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN= ); + s->pllcfg =3D (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS | + SIFIVE_PRCI_PLLCFG_LOCK); + s->plloutdiv =3D SIFIVE_PRCI_PLLOUTDIV_DIV1; + } =20 static const TypeInfo sifive_prci_info =3D { diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h index b6f4c486cc1e..bd51c4af3c1c 100644 --- a/include/hw/riscv/sifive_prci.h +++ b/include/hw/riscv/sifive_prci.h @@ -19,6 +19,34 @@ #ifndef HW_SIFIVE_PRCI_H #define HW_SIFIVE_PRCI_H =20 +enum { + SIFIVE_PRCI_HFROSCCFG =3D 0x0, + SIFIVE_PRCI_HFXOSCCFG =3D 0x4, + SIFIVE_PRCI_PLLCFG =3D 0x8, + SIFIVE_PRCI_PLLOUTDIV =3D 0xC +}; + +enum { + SIFIVE_PRCI_HFROSCCFG_RDY =3D (1 << 31), + SIFIVE_PRCI_HFROSCCFG_EN =3D (1 << 30) +}; + +enum { + SIFIVE_PRCI_HFXOSCCFG_RDY =3D (1 << 31), + SIFIVE_PRCI_HFXOSCCFG_EN =3D (1 << 30) +}; + +enum { + SIFIVE_PRCI_PLLCFG_PLLSEL =3D (1 << 16), + SIFIVE_PRCI_PLLCFG_REFSEL =3D (1 << 17), + SIFIVE_PRCI_PLLCFG_BYPASS =3D (1 << 18), + SIFIVE_PRCI_PLLCFG_LOCK =3D (1 << 31) +}; + +enum { + SIFIVE_PRCI_PLLOUTDIV_DIV1 =3D (1 << 8) +}; + #define TYPE_SIFIVE_PRCI "riscv.sifive.prci" =20 #define SIFIVE_PRCI(obj) \ @@ -30,6 +58,10 @@ typedef struct SiFivePRCIState { =20 /*< public >*/ MemoryRegion mmio; + uint32_t hfrosccfg; + uint32_t hfxosccfg; + uint32_t pllcfg; + uint32_t plloutdiv; } SiFivePRCIState; =20 DeviceState *sifive_prci_create(hwaddr addr); --=20 2.19.2