[Qemu-devel] [PULL 0/5] target-arm queue
[PULL v2 00/57] target-arm queue
1
A last arm pullreq before rc0. This is mostly bug fixes,
1
Squashed in a trivial fix for 32-bit hosts:
2
though you could call adding the missing local timer
3
support to bcm2836_control a new feature I suppose --
4
in any case it's a small and localised change.
5
2
6
thanks
3
--- a/target/arm/mve_helper.c
4
+++ b/target/arm/mve_helper.c
5
@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
6
acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
7
m[H##ESIZE(e)])); \
8
} \
9
- acc = int128_add(acc, 1 << 7); \
10
+ acc = int128_add(acc, int128_make64(1 << 7)); \
11
} \
12
} \
13
mve_advance_vpt(env); \
14
7
-- PMM
15
-- PMM
8
16
9
The following changes since commit 7074ab12c81a1b2b1e0e1c40983f56b2c5ccc494:
17
The following changes since commit 53f306f316549d20c76886903181413d20842423:
10
18
11
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-pull-request' into staging (2019-03-14 16:19:37 +0000)
19
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
12
20
13
are available in the Git repository at:
21
are available in the Git repository at:
14
22
15
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190315
23
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
16
24
17
for you to fetch changes up to 5de56742a3c91de3d646326bec43a989bba83ca4:
25
for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
18
26
19
target/arm: Check access permission to ADDVL/ADDPL/RDVL (2019-03-15 11:12:29 +0000)
27
docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
20
28
21
----------------------------------------------------------------
29
----------------------------------------------------------------
22
target-arm queue:
30
target-arm queue:
23
* Add missing SVE-enabled check to ADDVL/ADDPL/RDVL
31
* Don't require 'virt' board to be compiled in for ACPI GHES code
24
* virt-acpi-build: use PCIE_MMCFG_BUS to retrieve end_bus_number
32
* docs: Document which architecture extensions we emulate
25
* virt-acpi-build: Fix SMMUv3 GSIV values
33
* Fix bugs in M-profile FPCXT_NS accesses
26
* Allow EL0 to write to arch timer registers, not just read them
34
* First slice of MVE patches
27
* bcm2836_control: Implement local timer
35
* Implement MTE3
36
* docs/system: arm: Add nRF boards description
28
37
29
----------------------------------------------------------------
38
----------------------------------------------------------------
30
Amir Charif (1):
39
Alexandre Iooss (1):
31
target/arm: Check access permission to ADDVL/ADDPL/RDVL
40
docs/system: arm: Add nRF boards description
32
41
33
Dongjiu Geng (1):
42
Peter Collingbourne (1):
34
target/arm: change arch timer registers access permission
43
target/arm: Implement MTE3
35
44
36
Eric Auger (1):
45
Peter Maydell (55):
37
hw/arm/virt-acpi-build: Fix SMMUv3 GSIV values
46
hw/acpi: Provide stub version of acpi_ghes_record_errors()
47
hw/acpi: Provide function acpi_ghes_present()
48
target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
49
docs/system/arm: Document which architecture extensions we emulate
50
target/arm/translate-vfp.c: Whitespace fixes
51
target/arm: Handle FPU being disabled in FPCXT_NS accesses
52
target/arm: Don't NOCP fault for FPCXT_NS accesses
53
target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
54
target/arm: Factor FP context update code out into helper function
55
target/arm: Split vfp_access_check() into A and M versions
56
target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
57
target/arm: Implement MVE VLDR/VSTR (non-widening forms)
58
target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
59
target/arm: Implement MVE VCLZ
60
target/arm: Implement MVE VCLS
61
target/arm: Implement MVE VREV16, VREV32, VREV64
62
target/arm: Implement MVE VMVN (register)
63
target/arm: Implement MVE VABS
64
target/arm: Implement MVE VNEG
65
tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
66
target/arm: Implement MVE VDUP
67
target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
68
target/arm: Implement MVE VADD, VSUB, VMUL
69
target/arm: Implement MVE VMULH
70
target/arm: Implement MVE VRMULH
71
target/arm: Implement MVE VMAX, VMIN
72
target/arm: Implement MVE VABD
73
target/arm: Implement MVE VHADD, VHSUB
74
target/arm: Implement MVE VMULL
75
target/arm: Implement MVE VMLALDAV
76
target/arm: Implement MVE VMLSLDAV
77
target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
78
target/arm: Implement MVE VADD (scalar)
79
target/arm: Implement MVE VSUB, VMUL (scalar)
80
target/arm: Implement MVE VHADD, VHSUB (scalar)
81
target/arm: Implement MVE VBRSR
82
target/arm: Implement MVE VPST
83
target/arm: Implement MVE VQADD and VQSUB
84
target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
85
target/arm: Implement MVE VQDMULL scalar
86
target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
87
target/arm: Implement MVE VQADD, VQSUB (vector)
88
target/arm: Implement MVE VQSHL (vector)
89
target/arm: Implement MVE VQRSHL
90
target/arm: Implement MVE VSHL insn
91
target/arm: Implement MVE VRSHL
92
target/arm: Implement MVE VQDMLADH and VQRDMLADH
93
target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
94
target/arm: Implement MVE VQDMULL (vector)
95
target/arm: Implement MVE VRHADD
96
target/arm: Implement MVE VADC, VSBC
97
target/arm: Implement MVE VCADD
98
target/arm: Implement MVE VHCADD
99
target/arm: Implement MVE VADDV
100
target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
38
101
39
Wei Yang (1):
102
docs/system/arm/emulation.rst | 103 ++++
40
hw/arm/virt-acpi-build: use PCIE_MMCFG_BUS to retrieve end_bus_number
103
docs/system/arm/nrf.rst | 51 ++
104
docs/system/target-arm.rst | 7 +
105
include/hw/acpi/ghes.h | 9 +
106
include/tcg/tcg-op.h | 8 +
107
include/tcg/tcg.h | 1 -
108
target/arm/helper-mve.h | 357 +++++++++++++
109
target/arm/helper.h | 2 +
110
target/arm/internals.h | 11 +
111
target/arm/translate-a32.h | 3 +
112
target/arm/translate.h | 10 +
113
target/arm/m-nocp.decode | 24 +
114
target/arm/mve.decode | 240 +++++++++
115
target/arm/vfp.decode | 14 -
116
hw/acpi/ghes-stub.c | 22 +
117
hw/acpi/ghes.c | 17 +
118
target/arm/cpu64.c | 2 +-
119
target/arm/kvm64.c | 6 +-
120
target/arm/mte_helper.c | 82 +--
121
target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
122
target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
123
target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
124
target/arm/translate-vfp.c | 741 +++++++-------------------
125
tcg/tcg-op-gvec.c | 20 +-
126
MAINTAINERS | 1 +
127
hw/acpi/meson.build | 6 +-
128
target/arm/meson.build | 1 +
129
27 files changed, 3578 insertions(+), 629 deletions(-)
130
create mode 100644 docs/system/arm/emulation.rst
131
create mode 100644 docs/system/arm/nrf.rst
132
create mode 100644 target/arm/helper-mve.h
133
create mode 100644 hw/acpi/ghes-stub.c
134
create mode 100644 target/arm/mve_helper.c
41
135
42
Zoltán Baldaszti (1):
43
hw/intc/bcm2836_control: Implement local timer
44
45
include/hw/intc/bcm2836_control.h | 9 ++++
46
hw/arm/virt-acpi-build.c | 6 +--
47
hw/intc/bcm2836_control.c | 101 +++++++++++++++++++++++++++++++++++++-
48
target/arm/helper.c | 30 +++++------
49
target/arm/translate-sve.c | 22 ++++++---
50
5 files changed, 140 insertions(+), 28 deletions(-)
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/5] hw/intc/bcm2836_control: Implement local timer
Deleted patch
1
From: Zoltán Baldaszti <bztemail@gmail.com>
2
1
3
The BCM2836 control logic module includes a simple
4
"local timer" which is a programmable down-counter that
5
can generates an interrupt. Implement this functionality.
6
7
Signed-off-by: Zoltán Baldaszti <bztemail@gmail.com>
8
[PMM: wrote commit message; wrapped long line; tweaked
9
some comments to match the final version of the code]
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
include/hw/intc/bcm2836_control.h | 9 +++
14
hw/intc/bcm2836_control.c | 101 +++++++++++++++++++++++++++++-
15
2 files changed, 108 insertions(+), 2 deletions(-)
16
17
diff --git a/include/hw/intc/bcm2836_control.h b/include/hw/intc/bcm2836_control.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/intc/bcm2836_control.h
20
+++ b/include/hw/intc/bcm2836_control.h
21
@@ -XXX,XX +XXX,XX @@
22
* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
23
* Written by Andrew Baumann
24
*
25
+ * ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti
26
+ * Added basic IRQ_TIMER interrupt support
27
+ *
28
* This code is licensed under the GNU GPLv2 and later.
29
*/
30
31
@@ -XXX,XX +XXX,XX @@
32
#define BCM2836_CONTROL_H
33
34
#include "hw/sysbus.h"
35
+#include "qemu/timer.h"
36
37
/* 4 mailboxes per core, for 16 total */
38
#define BCM2836_NCORES 4
39
@@ -XXX,XX +XXX,XX @@ typedef struct BCM2836ControlState {
40
bool gpu_irq, gpu_fiq;
41
uint8_t timerirqs[BCM2836_NCORES];
42
43
+ /* local timer */
44
+ QEMUTimer timer;
45
+ uint32_t local_timer_control;
46
+ uint8_t route_localtimer;
47
+
48
/* interrupt source registers, post-routing (also input-derived; visible) */
49
uint32_t irqsrc[BCM2836_NCORES];
50
uint32_t fiqsrc[BCM2836_NCORES];
51
diff --git a/hw/intc/bcm2836_control.c b/hw/intc/bcm2836_control.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/intc/bcm2836_control.c
54
+++ b/hw/intc/bcm2836_control.c
55
@@ -XXX,XX +XXX,XX @@
56
* This code is licensed under the GNU GPLv2 and later.
57
*
58
* At present, only implements interrupt routing, and mailboxes (i.e.,
59
- * not local timer, PMU interrupt, or AXI counters).
60
+ * not PMU interrupt, or AXI counters).
61
+ *
62
+ * ARM Local Timer IRQ Copyright (c) 2019. Zoltán Baldaszti
63
*
64
* Ref:
65
* https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2836/QA7_rev3.4.pdf
66
@@ -XXX,XX +XXX,XX @@
67
#include "qemu/log.h"
68
69
#define REG_GPU_ROUTE 0x0c
70
+#define REG_LOCALTIMERROUTING 0x24
71
+#define REG_LOCALTIMERCONTROL 0x34
72
+#define REG_LOCALTIMERACK 0x38
73
#define REG_TIMERCONTROL 0x40
74
#define REG_MBOXCONTROL 0x50
75
#define REG_IRQSRC 0x60
76
@@ -XXX,XX +XXX,XX @@
77
#define IRQ_TIMER 11
78
#define IRQ_MAX IRQ_TIMER
79
80
+#define LOCALTIMER_FREQ 38400000
81
+#define LOCALTIMER_INTFLAG (1 << 31)
82
+#define LOCALTIMER_RELOAD (1 << 30)
83
+#define LOCALTIMER_INTENABLE (1 << 29)
84
+#define LOCALTIMER_ENABLE (1 << 28)
85
+#define LOCALTIMER_VALUE(x) ((x) & 0xfffffff)
86
+
87
static void deliver_local(BCM2836ControlState *s, uint8_t core, uint8_t irq,
88
uint32_t controlreg, uint8_t controlidx)
89
{
90
@@ -XXX,XX +XXX,XX @@ static void bcm2836_control_update(BCM2836ControlState *s)
91
s->fiqsrc[s->route_gpu_fiq] |= (uint32_t)1 << IRQ_GPU;
92
}
93
94
+ /*
95
+ * handle the control module 'local timer' interrupt for one of the
96
+ * cores' IRQ/FIQ; this is distinct from the per-CPU timer
97
+ * interrupts handled below.
98
+ */
99
+ if ((s->local_timer_control & LOCALTIMER_INTENABLE) &&
100
+ (s->local_timer_control & LOCALTIMER_INTFLAG)) {
101
+ if (s->route_localtimer & 4) {
102
+ s->fiqsrc[(s->route_localtimer & 3)] |= (uint32_t)1 << IRQ_TIMER;
103
+ } else {
104
+ s->irqsrc[(s->route_localtimer & 3)] |= (uint32_t)1 << IRQ_TIMER;
105
+ }
106
+ }
107
+
108
for (i = 0; i < BCM2836_NCORES; i++) {
109
/* handle local timer interrupts for this core */
110
if (s->timerirqs[i]) {
111
@@ -XXX,XX +XXX,XX @@ static void bcm2836_control_set_gpu_fiq(void *opaque, int irq, int level)
112
bcm2836_control_update(s);
113
}
114
115
+static void bcm2836_control_local_timer_set_next(void *opaque)
116
+{
117
+ BCM2836ControlState *s = opaque;
118
+ uint64_t next_event;
119
+
120
+ assert(LOCALTIMER_VALUE(s->local_timer_control) > 0);
121
+
122
+ next_event = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
123
+ muldiv64(LOCALTIMER_VALUE(s->local_timer_control),
124
+ NANOSECONDS_PER_SECOND, LOCALTIMER_FREQ);
125
+ timer_mod(&s->timer, next_event);
126
+}
127
+
128
+static void bcm2836_control_local_timer_tick(void *opaque)
129
+{
130
+ BCM2836ControlState *s = opaque;
131
+
132
+ bcm2836_control_local_timer_set_next(s);
133
+
134
+ s->local_timer_control |= LOCALTIMER_INTFLAG;
135
+ bcm2836_control_update(s);
136
+}
137
+
138
+static void bcm2836_control_local_timer_control(void *opaque, uint32_t val)
139
+{
140
+ BCM2836ControlState *s = opaque;
141
+
142
+ s->local_timer_control = val;
143
+ if (val & LOCALTIMER_ENABLE) {
144
+ bcm2836_control_local_timer_set_next(s);
145
+ } else {
146
+ timer_del(&s->timer);
147
+ }
148
+}
149
+
150
+static void bcm2836_control_local_timer_ack(void *opaque, uint32_t val)
151
+{
152
+ BCM2836ControlState *s = opaque;
153
+
154
+ if (val & LOCALTIMER_INTFLAG) {
155
+ s->local_timer_control &= ~LOCALTIMER_INTFLAG;
156
+ }
157
+ if ((val & LOCALTIMER_RELOAD) &&
158
+ (s->local_timer_control & LOCALTIMER_ENABLE)) {
159
+ bcm2836_control_local_timer_set_next(s);
160
+ }
161
+}
162
+
163
static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size)
164
{
165
BCM2836ControlState *s = opaque;
166
@@ -XXX,XX +XXX,XX @@ static uint64_t bcm2836_control_read(void *opaque, hwaddr offset, unsigned size)
167
assert(s->route_gpu_fiq < BCM2836_NCORES
168
&& s->route_gpu_irq < BCM2836_NCORES);
169
return ((uint32_t)s->route_gpu_fiq << 2) | s->route_gpu_irq;
170
+ } else if (offset == REG_LOCALTIMERROUTING) {
171
+ return s->route_localtimer;
172
+ } else if (offset == REG_LOCALTIMERCONTROL) {
173
+ return s->local_timer_control;
174
+ } else if (offset == REG_LOCALTIMERACK) {
175
+ return 0;
176
} else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
177
return s->timercontrol[(offset - REG_TIMERCONTROL) >> 2];
178
} else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
179
@@ -XXX,XX +XXX,XX @@ static void bcm2836_control_write(void *opaque, hwaddr offset,
180
if (offset == REG_GPU_ROUTE) {
181
s->route_gpu_irq = val & 0x3;
182
s->route_gpu_fiq = (val >> 2) & 0x3;
183
+ } else if (offset == REG_LOCALTIMERROUTING) {
184
+ s->route_localtimer = val & 7;
185
+ } else if (offset == REG_LOCALTIMERCONTROL) {
186
+ bcm2836_control_local_timer_control(s, val);
187
+ } else if (offset == REG_LOCALTIMERACK) {
188
+ bcm2836_control_local_timer_ack(s, val);
189
} else if (offset >= REG_TIMERCONTROL && offset < REG_MBOXCONTROL) {
190
s->timercontrol[(offset - REG_TIMERCONTROL) >> 2] = val & 0xff;
191
} else if (offset >= REG_MBOXCONTROL && offset < REG_IRQSRC) {
192
@@ -XXX,XX +XXX,XX @@ static void bcm2836_control_reset(DeviceState *d)
193
194
s->route_gpu_irq = s->route_gpu_fiq = 0;
195
196
+ timer_del(&s->timer);
197
+ s->route_localtimer = 0;
198
+ s->local_timer_control = 0;
199
+
200
for (i = 0; i < BCM2836_NCORES; i++) {
201
s->timercontrol[i] = 0;
202
s->mailboxcontrol[i] = 0;
203
@@ -XXX,XX +XXX,XX @@ static void bcm2836_control_init(Object *obj)
204
/* outputs to CPU cores */
205
qdev_init_gpio_out_named(dev, s->irq, "irq", BCM2836_NCORES);
206
qdev_init_gpio_out_named(dev, s->fiq, "fiq", BCM2836_NCORES);
207
+
208
+ /* create a qemu virtual timer */
209
+ timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL,
210
+ bcm2836_control_local_timer_tick, s);
211
}
212
213
static const VMStateDescription vmstate_bcm2836_control = {
214
.name = TYPE_BCM2836_CONTROL,
215
- .version_id = 1,
216
+ .version_id = 2,
217
.minimum_version_id = 1,
218
.fields = (VMStateField[]) {
219
VMSTATE_UINT32_ARRAY(mailboxes, BCM2836ControlState,
220
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_bcm2836_control = {
221
VMSTATE_UINT32_ARRAY(timercontrol, BCM2836ControlState, BCM2836_NCORES),
222
VMSTATE_UINT32_ARRAY(mailboxcontrol, BCM2836ControlState,
223
BCM2836_NCORES),
224
+ VMSTATE_TIMER_V(timer, BCM2836ControlState, 2),
225
+ VMSTATE_UINT32_V(local_timer_control, BCM2836ControlState, 2),
226
+ VMSTATE_UINT8_V(route_localtimer, BCM2836ControlState, 2),
227
VMSTATE_END_OF_LIST()
228
}
229
};
230
--
231
2.20.1
232
233
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/5] hw/arm/virt-acpi-build: Fix SMMUv3 GSIV values
Deleted patch
1
From: Eric Auger <eric.auger@redhat.com>
2
1
3
The GSIV numbers of the SPI based interrupts is not correct as
4
ARM_SPI_BASE was not added to the irqmap[VIRT_SMMU] value. So
5
this may collide with VIRTIO_MMIO irq window.
6
7
Signed-off-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20190312091031.5185-1-eric.auger@redhat.com
9
Reviewed-by: Shannon Zhao <shannon.zhaosl@gmail.com>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/virt-acpi-build.c | 2 +-
13
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/virt-acpi-build.c
18
+++ b/hw/arm/virt-acpi-build.c
19
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
20
its->identifiers[0] = 0; /* MADT translation_id */
21
22
if (vms->iommu == VIRT_IOMMU_SMMUV3) {
23
- int irq = vms->irqmap[VIRT_SMMU];
24
+ int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
25
26
/* SMMUv3 node */
27
smmu_offset = iort_node_offset + node_size;
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/5] target/arm: change arch timer registers access permission
Deleted patch
1
From: Dongjiu Geng <gengdongjiu@huawei.com>
2
1
3
Some generic arch timer registers are Config-RW in the EL0,
4
which means the EL0 exception level can have write permission
5
if it is appropriately configured.
6
7
When VM access registers, QEMU firstly checks whether they have RW
8
permission, then check whether it is appropriately configured.
9
If they are defined to read only in EL0, even though they have been
10
appropriately configured, they still do not have write permission.
11
So need to add the write permission according to ARMV8 spec when
12
define it.
13
14
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
15
Message-id: 1552395177-12608-1-git-send-email-gengdongjiu@huawei.com
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
target/arm/helper.c | 30 +++++++++++++++---------------
21
1 file changed, 15 insertions(+), 15 deletions(-)
22
23
diff --git a/target/arm/helper.c b/target/arm/helper.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/helper.c
26
+++ b/target/arm/helper.c
27
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
28
/* per-timer control */
29
{ .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
30
.secure = ARM_CP_SECSTATE_NS,
31
- .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
32
+ .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
33
.accessfn = gt_ptimer_access,
34
.fieldoffset = offsetoflow32(CPUARMState,
35
cp15.c14_timer[GTIMER_PHYS].ctl),
36
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
37
{ .name = "CNTP_CTL_S",
38
.cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
39
.secure = ARM_CP_SECSTATE_S,
40
- .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
41
+ .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
42
.accessfn = gt_ptimer_access,
43
.fieldoffset = offsetoflow32(CPUARMState,
44
cp15.c14_timer[GTIMER_SEC].ctl),
45
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
46
},
47
{ .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
48
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
49
- .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
50
+ .type = ARM_CP_IO, .access = PL0_RW,
51
.accessfn = gt_ptimer_access,
52
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
53
.resetvalue = 0,
54
.writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
55
},
56
{ .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
57
- .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
58
+ .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL0_RW,
59
.accessfn = gt_vtimer_access,
60
.fieldoffset = offsetoflow32(CPUARMState,
61
cp15.c14_timer[GTIMER_VIRT].ctl),
62
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
63
},
64
{ .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
65
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
66
- .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
67
+ .type = ARM_CP_IO, .access = PL0_RW,
68
.accessfn = gt_vtimer_access,
69
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
70
.resetvalue = 0,
71
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
72
/* TimerValue views: a 32 bit downcounting view of the underlying state */
73
{ .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
74
.secure = ARM_CP_SECSTATE_NS,
75
- .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
76
+ .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
77
.accessfn = gt_ptimer_access,
78
.readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
79
},
80
{ .name = "CNTP_TVAL_S",
81
.cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
82
.secure = ARM_CP_SECSTATE_S,
83
- .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
84
+ .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
85
.accessfn = gt_ptimer_access,
86
.readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
87
},
88
{ .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
89
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
90
- .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
91
+ .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
92
.accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
93
.readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
94
},
95
{ .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
96
- .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
97
+ .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
98
.accessfn = gt_vtimer_access,
99
.readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
100
},
101
{ .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
102
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
103
- .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
104
+ .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL0_RW,
105
.accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
106
.readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
107
},
108
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
109
/* Comparison value, indicating when the timer goes off */
110
{ .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
111
.secure = ARM_CP_SECSTATE_NS,
112
- .access = PL1_RW | PL0_R,
113
+ .access = PL0_RW,
114
.type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
115
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
116
.accessfn = gt_ptimer_access,
117
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
118
},
119
{ .name = "CNTP_CVAL_S", .cp = 15, .crm = 14, .opc1 = 2,
120
.secure = ARM_CP_SECSTATE_S,
121
- .access = PL1_RW | PL0_R,
122
+ .access = PL0_RW,
123
.type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
124
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
125
.accessfn = gt_ptimer_access,
126
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
127
},
128
{ .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
129
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
130
- .access = PL1_RW | PL0_R,
131
+ .access = PL0_RW,
132
.type = ARM_CP_IO,
133
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
134
.resetvalue = 0, .accessfn = gt_ptimer_access,
135
.writefn = gt_phys_cval_write, .raw_writefn = raw_write,
136
},
137
{ .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
138
- .access = PL1_RW | PL0_R,
139
+ .access = PL0_RW,
140
.type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
141
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
142
.accessfn = gt_vtimer_access,
143
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
144
},
145
{ .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
146
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
147
- .access = PL1_RW | PL0_R,
148
+ .access = PL0_RW,
149
.type = ARM_CP_IO,
150
.fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
151
.resetvalue = 0, .accessfn = gt_vtimer_access,
152
--
153
2.20.1
154
155
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/5] hw/arm/virt-acpi-build: use PCIE_MMCFG_BUS to retrieve end_bus_number
Deleted patch
1
From: Wei Yang <richardw.yang@linux.intel.com>
2
1
3
This is more proper to use PCIE_MMCFG_BUS to retrieve end_bus_number.
4
5
Signed-off-by: Wei Yang <richardw.yang@linux.intel.com>
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
8
Message-id: 20190312074953.16671-1-richardw.yang@linux.intel.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
hw/arm/virt-acpi-build.c | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/virt-acpi-build.c
17
+++ b/hw/arm/virt-acpi-build.c
18
@@ -XXX,XX +XXX,XX @@ build_mcfg(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
19
/* Only a single allocation so no need to play with segments */
20
mcfg->allocation[0].pci_segment = cpu_to_le16(0);
21
mcfg->allocation[0].start_bus_number = 0;
22
- mcfg->allocation[0].end_bus_number = (memmap[ecam_id].size
23
- / PCIE_MMCFG_SIZE_MIN) - 1;
24
+ mcfg->allocation[0].end_bus_number =
25
+ PCIE_MMCFG_BUS(memmap[ecam_id].size - 1);
26
27
build_header(linker, table_data, (void *)(table_data->data + mcfg_start),
28
"MCFG", table_data->len - mcfg_start, 1, NULL, NULL);
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 5/5] target/arm: Check access permission to ADDVL/ADDPL/RDVL
Deleted patch
1
From: Amir Charif <amir.charif@cea.fr>
2
1
3
These instructions do not trap when SVE is disabled in EL0,
4
causing them to be executed with wrong size information.
5
6
Signed-off-by: Amir Charif <amir.charif@cea.fr>
7
Message-id: 1552579248-31025-1-git-send-email-amir.charif@cea.fr
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
[PMM: added 'target/arm' prefix to subject]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/translate-sve.c | 22 ++++++++++++++--------
14
1 file changed, 14 insertions(+), 8 deletions(-)
15
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-sve.c
19
+++ b/target/arm/translate-sve.c
20
@@ -XXX,XX +XXX,XX @@ static bool trans_INDEX_rr(DisasContext *s, arg_INDEX_rr *a)
21
22
static bool trans_ADDVL(DisasContext *s, arg_ADDVL *a)
23
{
24
- TCGv_i64 rd = cpu_reg_sp(s, a->rd);
25
- TCGv_i64 rn = cpu_reg_sp(s, a->rn);
26
- tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s));
27
+ if (sve_access_check(s)) {
28
+ TCGv_i64 rd = cpu_reg_sp(s, a->rd);
29
+ TCGv_i64 rn = cpu_reg_sp(s, a->rn);
30
+ tcg_gen_addi_i64(rd, rn, a->imm * vec_full_reg_size(s));
31
+ }
32
return true;
33
}
34
35
static bool trans_ADDPL(DisasContext *s, arg_ADDPL *a)
36
{
37
- TCGv_i64 rd = cpu_reg_sp(s, a->rd);
38
- TCGv_i64 rn = cpu_reg_sp(s, a->rn);
39
- tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s));
40
+ if (sve_access_check(s)) {
41
+ TCGv_i64 rd = cpu_reg_sp(s, a->rd);
42
+ TCGv_i64 rn = cpu_reg_sp(s, a->rn);
43
+ tcg_gen_addi_i64(rd, rn, a->imm * pred_full_reg_size(s));
44
+ }
45
return true;
46
}
47
48
static bool trans_RDVL(DisasContext *s, arg_RDVL *a)
49
{
50
- TCGv_i64 reg = cpu_reg(s, a->rd);
51
- tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s));
52
+ if (sve_access_check(s)) {
53
+ TCGv_i64 reg = cpu_reg(s, a->rd);
54
+ tcg_gen_movi_i64(reg, a->imm * vec_full_reg_size(s));
55
+ }
56
return true;
57
}
58
59
--
60
2.20.1
61
62
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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