Most of this is the Neon decodetree patches, followed by Edgar's versal cleanups.

thanks

-- PMM

The following changes since commit 2ef486e76d64436be90f7359a3071fb2a56ce835:

Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into staging (2020-05-03 14:12:56 +0100)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200504

for you to fetch changes up to 9aefc6cf9b73f66062d2f914a0136756e7a28211:

target/arm: Move gen_ function typedefs to translate.h (2020-05-04 12:59:26 +0100)

* Start of conversion of Neon insns to decodetree

* versal board: support SD and RTC

* Implement ARMv8.2-TTS2UXN

* Make VQDMULL undefined when U=1

* Some minor code cleanups

Edgar E. Iglesias (11):

hw/arm: versal: Remove inclusion of arm_gicv3_common.h

hw/arm: versal: Move misplaced comment

hw/arm: versal-virt: Fix typo xlnx-ve -> xlnx-versal

hw/arm: versal: Embed the UARTs into the SoC type

hw/arm: versal: Embed the GEMs into the SoC type

hw/arm: versal: Embed the ADMAs into the SoC type

hw/arm: versal: Embed the APUs into the SoC type

hw/arm: versal: Add support for SD

hw/arm: versal: Add support for the RTC

hw/arm: versal-virt: Add support for SD

hw/arm: versal-virt: Add support for the RTC

Fredrik Strupe (1):

target/arm: Make VQDMULL undefined when U=1

Peter Maydell (25):

target/arm: Don't use a TLB for ARMMMUIdx_Stage2

target/arm: Use enum constant in get_phys_addr_lpae() call

target/arm: Add new 's1_is_el0' argument to get_phys_addr_lpae()

target/arm: Implement ARMv8.2-TTS2UXN

target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0

target/arm/translate-vfp.inc.c: Remove duplicate simd_r32 check

target/arm: Don't allow Thumb Neon insns without FEATURE_NEON

target/arm: Add stubs for AArch32 Neon decodetree

target/arm: Convert VCMLA (vector) to decodetree

target/arm: Convert VCADD (vector) to decodetree

target/arm: Convert V[US]DOT (vector) to decodetree

target/arm: Convert VFM[AS]L (vector) to decodetree

target/arm: Convert VCMLA (scalar) to decodetree

target/arm: Convert V[US]DOT (scalar) to decodetree

target/arm: Convert VFM[AS]L (scalar) to decodetree

target/arm: Convert Neon load/store multiple structures to decodetree

target/arm: Convert Neon 'load single structure to all lanes' to decodetree

target/arm: Convert Neon 'load/store single structure' to decodetree

target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree

target/arm: Convert Neon 3-reg-same logic ops to decodetree

target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree

target/arm: Convert Neon 3-reg-same comparisons to decodetree

target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree

target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree

target/arm: Move gen_ function typedefs to translate.h

We define ARMMMUIdx_Stage2 as being an MMU index which uses a QEMU

TLB. However we never actually use the TLB -- all stage 2 lookups

are done by direct calls to get_phys_addr_lpae() followed by a

physical address load via address_space_ld*().

Remove Stage2 from the list of ARM MMU indexes which correspond to

real core MMU indexes, and instead put it in the set of "NOTLB" ARM

MMU indexes.

This allows us to drop NB_MMU_MODES to 11. It also means we can

safely add support for the ARMv8.3-TTS2UXN extension, which adds

permission bits to the stage 2 descriptors which define execute

permission separatel for EL0 and EL1; supporting that while keeping

Stage2 in a QEMU TLB would require us to use separate TLBs for

"Stage2 for an EL0 access" and "Stage2 for an EL1 access", which is a

lot of extra complication given we aren't even using the QEMU TLB.

In the process of updating the comment on our MMU index use,

fix a couple of other minor errors:

* NS EL2 EL2&0 was missing from the list in the comment

* some text hadn't been updated from when we bumped NB_MMU_MODES

above 8

target/arm/cpu-param.h | 2 +-

target/arm/cpu.h | 21 +++++---

target/arm/helper.c | 112 ++++-------------------------------------

3 files changed, 27 insertions(+), 108 deletions(-)

diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu-param.h

+++ b/target/arm/cpu-param.h

@@ -XXX,XX +XXX,XX @@

# define TARGET_PAGE_BITS_MIN 10

#endif

-#define NB_MMU_MODES 12

+#define NB_MMU_MODES 11

#endif

@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);

* handling via the TLB. The only way to do a stage 1 translation without

* the immediate stage 2 translation is via the ATS or AT system insns,

* which can be slow-pathed and always do a page table walk.

+ * The only use of stage 2 translations is either as part of an s1+2

+ * lookup or when loading the descriptors during a stage 1 page table walk,

+ * and in both those cases we don't use the TLB.

* 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"

* translation regimes, because they map reasonably well to each other

* and they can't both be active at the same time.

@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);

* NS EL1 EL1&0 stage 1+2 (aka NS PL1)

* NS EL1 EL1&0 stage 1+2 +PAN

* NS EL0 EL2&0

+ * NS EL2 EL2&0

* NS EL2 EL2&0 +PAN

* NS EL2 (aka NS PL2)

* S EL0 EL1&0 (aka S PL0)

* S EL1 EL1&0 (not used if EL3 is 32 bit)

* S EL1 EL1&0 +PAN

* S EL3 (aka S PL1)

- * NS EL1&0 stage 2

- * for a total of 12 different mmu_idx.

+ * for a total of 11 different mmu_idx.

* R profile CPUs have an MPU, but can use the same set of MMU indexes

* as A profile. They only need to distinguish NS EL0 and NS EL1 (and

@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);

* are not quite the same -- different CPU types (most notably M profile

* vs A/R profile) would like to use MMU indexes with different semantics,

* but since we don't ever need to use all of those in a single CPU we

- * can avoid setting NB_MMU_MODES to more than 8. The lower bits of

+ * can avoid having to set NB_MMU_MODES to "total number of A profile MMU

+ * modes + total number of M profile MMU modes". The lower bits of

* ARMMMUIdx are the core TLB mmu index, and the higher bits are always

* the same for any particular CPU.

* Variables of type ARMMUIdx are always full values, and the core

@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {

ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,

ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A,

- ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A,

-

/*

* These are not allocated TLBs and are used only for AT system

* instructions or for the first stage of an S12 page table walk.

@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {

ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,

ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,

ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,

+ /*

+ * Not allocated a TLB: used only for second stage of an S12 page

+ * table walk, or for descriptor loads during first stage of an S1

+ * page table walk. Note that if we ever want to have a TLB for this

+ * then various TLB flush insns which currently are no-ops or flush

+ * only stage 1 MMU indexes will need to change to flush stage 2.

+ */

+ ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB,

/*

* M-profile.

@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {

TO_CORE_BIT(SE10_1),

TO_CORE_BIT(SE10_1_PAN),

TO_CORE_BIT(SE3),

- TO_CORE_BIT(Stage2),

TO_CORE_BIT(MUser),

TO_CORE_BIT(MPriv),

@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,

tlb_flush_by_mmuidx(cs,

ARMMMUIdxBit_E10_1 |

ARMMMUIdxBit_E10_1_PAN |

- ARMMMUIdxBit_E10_0 |

- ARMMMUIdxBit_Stage2);

+ ARMMMUIdxBit_E10_0);

static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,

@@ -XXX,XX +XXX,XX @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,

tlb_flush_by_mmuidx_all_cpus_synced(cs,

ARMMMUIdxBit_E10_1 |

ARMMMUIdxBit_E10_1_PAN |

- ARMMMUIdxBit_E10_0 |

- ARMMMUIdxBit_Stage2);

+ ARMMMUIdxBit_E10_0);

}

-static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,

- uint64_t value)

-{

- /* Invalidate by IPA. This has to invalidate any structures that

- * contain only stage 2 translation information, but does not need

- * to apply to structures that contain combined stage 1 and stage 2

- * translation information.

- * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.

- */

- CPUState *cs = env_cpu(env);

- uint64_t pageaddr;

-

- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {

- return;

- }

-

- pageaddr = sextract64(value << 12, 0, 40);

-

- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);

-}

-

-static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,

- uint64_t value)

-{

- CPUState *cs = env_cpu(env);

- uint64_t pageaddr;

-

- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {

- return;

- }

-

- pageaddr = sextract64(value << 12, 0, 40);

-

- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,

- ARMMMUIdxBit_Stage2);

-}

static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,

uint64_t value)

@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,

tlb_flush_by_mmuidx(cs,

ARMMMUIdxBit_E10_1 |

ARMMMUIdxBit_E10_1_PAN |

- ARMMMUIdxBit_E10_0 |

- ARMMMUIdxBit_Stage2);

+ ARMMMUIdxBit_E10_0);

raw_write(env, ri, value);

}

}

@@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env)

return ARMMMUIdxBit_SE10_1 |

ARMMMUIdxBit_SE10_1_PAN |

ARMMMUIdxBit_SE10_0;

- } else if (arm_feature(env, ARM_FEATURE_EL2)) {

- return ARMMMUIdxBit_E10_1 |

- ARMMMUIdxBit_E10_1_PAN |

- ARMMMUIdxBit_E10_0 |

- ARMMMUIdxBit_Stage2;

} else {

return ARMMMUIdxBit_E10_1 |

ARMMMUIdxBit_E10_1_PAN |

@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,

ARMMMUIdxBit_SE3);

}

-static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,

- uint64_t value)

-{

- /* Invalidate by IPA. This has to invalidate any structures that

- * contain only stage 2 translation information, but does not need

- * to apply to structures that contain combined stage 1 and stage 2

- * translation information.

- * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.

- */

- ARMCPU *cpu = env_archcpu(env);

- CPUState *cs = CPU(cpu);

- uint64_t pageaddr;

-

- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {

- return;

- }

-

- pageaddr = sextract64(value << 12, 0, 48);

-

- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_Stage2);

-}

-

-static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,

- uint64_t value)

-{

- CPUState *cs = env_cpu(env);

- uint64_t pageaddr;

-

- if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {

- return;

- }

-

- pageaddr = sextract64(value << 12, 0, 48);

-

- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,

- ARMMMUIdxBit_Stage2);

-}

-

static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,

bool isread)

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {

.writefn = tlbi_aa64_vae1_write },

{ .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,

- .access = PL2_W, .type = ARM_CP_NO_RAW,

- .writefn = tlbi_aa64_ipas2e1is_write },

+ .access = PL2_W, .type = ARM_CP_NOP },

{ .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,

- .access = PL2_W, .type = ARM_CP_NO_RAW,

- .writefn = tlbi_aa64_ipas2e1is_write },

+ .access = PL2_W, .type = ARM_CP_NOP },

{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,

.access = PL2_W, .type = ARM_CP_NO_RAW,

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {

.writefn = tlbi_aa64_alle1is_write },

{ .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,

- .access = PL2_W, .type = ARM_CP_NO_RAW,

- .writefn = tlbi_aa64_ipas2e1_write },

+ .access = PL2_W, .type = ARM_CP_NOP },

{ .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,

- .access = PL2_W, .type = ARM_CP_NO_RAW,

- .writefn = tlbi_aa64_ipas2e1_write },

+ .access = PL2_W, .type = ARM_CP_NOP },

{ .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,

.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,

.access = PL2_W, .type = ARM_CP_NO_RAW,

@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {

.writefn = tlbimva_hyp_is_write },

{ .name = "TLBIIPAS2",

.cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,

- .type = ARM_CP_NO_RAW, .access = PL2_W,

- .writefn = tlbiipas2_write },

+ .type = ARM_CP_NOP, .access = PL2_W },

{ .name = "TLBIIPAS2IS",

.cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,

- .type = ARM_CP_NO_RAW, .access = PL2_W,

- .writefn = tlbiipas2_is_write },

+ .type = ARM_CP_NOP, .access = PL2_W },

{ .name = "TLBIIPAS2L",

.cp = 15, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,

- .type = ARM_CP_NO_RAW, .access = PL2_W,

- .writefn = tlbiipas2_write },

+ .type = ARM_CP_NOP, .access = PL2_W },

{ .name = "TLBIIPAS2LIS",

.cp = 15, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,

- .type = ARM_CP_NO_RAW, .access = PL2_W,

- .writefn = tlbiipas2_is_write },

+ .type = ARM_CP_NOP, .access = PL2_W },

/* 32 bit cache operations */

{ .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,

.type = ARM_CP_NOP, .access = PL1_W, .accessfn = aa64_cacheop_pou_access },

The ARMv8.2-TTS2UXN feature extends the XN field in stage 2

translation table descriptors from just bit [54] to bits [54:53],

allowing stage 2 to control execution permissions separately for EL0

and EL1. Implement the new semantics of the XN field and enable

the feature for our 'max' CPU.

Message-id: 20200330210400.11724-5-peter.maydell@linaro.org

target/arm/cpu.h | 15 +++++++++++++++

target/arm/cpu.c | 1 +

target/arm/cpu64.c | 2 ++

target/arm/helper.c | 37 +++++++++++++++++++++++++++++++------

4 files changed, 49 insertions(+), 6 deletions(-)

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)

return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;

+static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)

+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;

@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)

t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */

t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */

t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */

+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */

cpu->isar.id_mmfr4 = t;

}

#endif

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);

t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */

t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */

+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */

cpu->isar.id_aa64mmfr1 = t;

t = cpu->isar.id_aa64mmfr2;

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */

u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */

u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */

+ u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */

cpu->isar.id_mmfr4 = u;

u = cpu->isar.id_aa64dfr0;

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)

*

* @env: CPUARMState

* @s2ap: The 2-bit stage2 access permissions (S2AP)

- * @xn: XN (execute-never) bit

+ * @xn: XN (execute-never) bits

+ * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0

*/

-static int get_S2prot(CPUARMState *env, int s2ap, int xn)

+static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)

{

int prot = 0;

@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn)

if (s2ap & 2) {

prot |= PAGE_WRITE;

- if (!xn) {

- if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {

+

+ if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {

+ switch (xn) {

+ case 0:

prot |= PAGE_EXEC;

+ break;

+ case 1:

+ if (s1_is_el0) {

+ prot |= PAGE_EXEC;

+ }

+ break;

+ case 2:

+ break;

+ case 3:

+ if (!s1_is_el0) {

+ prot |= PAGE_EXEC;

+ }

+ break;

+ default:

+ g_assert_not_reached();

+ }

+ } else {

+ if (!extract32(xn, 1, 1)) {

+ if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {

+ prot |= PAGE_EXEC;

+ }

}

return prot;

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

ap = extract32(attrs, 4, 2);

- xn = extract32(attrs, 12, 1);

if (mmu_idx == ARMMMUIdx_Stage2) {

ns = true;

- *prot = get_S2prot(env, ap, xn);

+ xn = extract32(attrs, 11, 2);

+ *prot = get_S2prot(env, ap, xn, s1_is_el0);

} else {

ns = extract32(attrs, 3, 1);

+ xn = extract32(attrs, 12, 1);

pxn = extract32(attrs, 11, 1);

*prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);

In aarch64_max_initfn() we update both 32-bit and 64-bit ID

registers. The intended pattern is that for 64-bit ID registers we

use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID

registers use FIELD_DP32 and the uint32_t 'u' register. For

ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of

this 64-bit ID register would end up always zero. Luckily at the

moment that's what they should be anyway, so this bug has no visible

effects.

Use the right-sized variable.

Fixes: 3bec78447a958d481991

target/arm/cpu64.c | 6 +++---

1 file changed, 3 insertions(+), 3 deletions(-)

u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */

cpu->isar.id_mmfr4 = u;

- u = cpu->isar.id_aa64dfr0;

- u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */

- cpu->isar.id_aa64dfr0 = u;

+ t = cpu->isar.id_aa64dfr0;

+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */

+ cpu->isar.id_aa64dfr0 = t;

u = cpu->isar.id_dfr0;

u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.

Represent it in QEMU's ARMCPU struct with a uint64_t, not a

uint32_t.

This fixes an error when compiling with -Werror=conversion

because we were manipulating the register value using a

local uint64_t variable:

target/arm/cpu64.c: In function ‘aarch64_max_initfn’:

target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]

628 | cpu->midr = t;

| ^

and future-proofs us against a possible future architecture

change using some of the top 32 bits.

Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Message-id: 20200428172634.29707-1-f4bug@amsat.org

target/arm/cpu.h | 2 +-

target/arm/cpu.c | 2 +-

2 files changed, 2 insertions(+), 2 deletions(-)

@@ -XXX,XX +XXX,XX @@ struct ARMCPU {

uint64_t id_aa64dfr0;

uint64_t id_aa64dfr1;

} isar;

- uint32_t midr;

+ uint64_t midr;

uint32_t revidr;

uint32_t reset_fpsid;

uint32_t ctr;

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {

static Property arm_cpu_properties[] = {

DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),

DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),

- DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),

+ DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),

DEFINE_PROP_UINT64("mp-affinity", ARMCPU,

mp_affinity, ARM64_AFFINITY_INVALID),

DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),