1 | Arm stuff, mostly patches from RTH. | 1 | Hi; here's the latest round of arm patches. I have included also |
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2 | my patchset for the RTC devices to avoid keeping time_t and | ||
3 | time_t diffs in 32-bit variables. | ||
2 | 4 | ||
3 | thanks | 5 | thanks |
4 | -- PMM | 6 | -- PMM |
5 | 7 | ||
6 | The following changes since commit 01a9a51ffaf4699827ea6425cb2b834a356e159d: | 8 | The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c: |
7 | 9 | ||
8 | Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190205-pull-request' into staging (2019-02-05 14:01:29 +0000) | 10 | Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400) |
9 | 11 | ||
10 | are available in the Git repository at: | 12 | are available in the Git repository at: |
11 | 13 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190205 | 14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831 |
13 | 15 | ||
14 | for you to fetch changes up to a15945d98d3a3390c3da344d1b47218e91e49d8b: | 16 | for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb: |
15 | 17 | ||
16 | target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI (2019-02-05 16:52:42 +0000) | 18 | hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100) |
17 | 19 | ||
18 | ---------------------------------------------------------------- | 20 | ---------------------------------------------------------------- |
19 | target-arm queue: | 21 | target-arm queue: |
20 | * Implement Armv8.5-BTI extension for system emulation mode | 22 | * Some of the preliminary patches for Cortex-A710 support |
21 | * Implement the PR_PAC_RESET_KEYS prctl() for linux-user mode's Armv8.3-PAuth support | 23 | * i.MX7 and i.MX6UL refactoring |
22 | * Support TBI (top-byte-ignore) properly for linux-user mode | 24 | * Implement SRC device for i.MX7 |
23 | * gdbstub: allow killing QEMU via vKill command | 25 | * Catch illegal-exception-return from EL3 with bad NSE/NS |
24 | * hw/arm/boot: Support DTB autoload for firmware-only boots | 26 | * Use 64-bit offsets for holding time_t differences in RTC devices |
25 | * target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI | 27 | * Model correct number of MPU regions for an505, an521, an524 boards |
26 | 28 | ||
27 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
28 | Max Filippov (1): | 30 | Alex Bennée (1): |
29 | gdbstub: allow killing QEMU via vKill command | 31 | target/arm: properly document FEAT_CRC32 |
30 | 32 | ||
31 | Peter Maydell (7): | 33 | Jean-Christophe Dubois (6): |
32 | target/arm: Compute TB_FLAGS for TBI for user-only | 34 | Remove i.MX7 IOMUX GPR device from i.MX6UL |
33 | hw/arm/boot: Fix block comment style in arm_load_kernel() | 35 | Refactor i.MX6UL processor code |
34 | hw/arm/boot: Factor out "direct kernel boot" code into its own function | 36 | Add i.MX6UL missing devices. |
35 | hw/arm/boot: Factor out "set up firmware boot" code | 37 | Refactor i.MX7 processor code |
36 | hw/arm/boot: Clarify why arm_setup_firmware_boot() doesn't set env->boot_info | 38 | Add i.MX7 missing TZ devices and memory regions |
37 | hw/arm/boot: Support DTB autoload for firmware-only boots | 39 | Add i.MX7 SRC device implementation |
38 | target/arm: Make FPSCR/FPCR trapped-exception bits RAZ/WI | ||
39 | 40 | ||
40 | Richard Henderson (14): | 41 | Peter Maydell (8): |
41 | target/arm: Introduce isar_feature_aa64_bti | 42 | target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS |
42 | target/arm: Add PSTATE.BTYPE | 43 | hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm() |
43 | target/arm: Add BT and BTYPE to tb->flags | 44 | hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec |
44 | exec: Add target-specific tlb bits to MemTxAttrs | 45 | hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference |
45 | target/arm: Cache the GP bit for a page in MemTxAttrs | 46 | rtc: Use time_t for passing and returning time offsets |
46 | target/arm: Default handling of BTYPE during translation | 47 | target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init |
47 | target/arm: Reset btype for direct branches | 48 | hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties |
48 | target/arm: Set btype for indirect branches | 49 | hw/arm: Set number of MPU regions correctly for an505, an521, an524 |
49 | target/arm: Enable BTI for -cpu max | ||
50 | linux-user: Implement PR_PAC_RESET_KEYS | ||
51 | tests/tcg/aarch64: Add pauth smoke test | ||
52 | target/arm: Add TBFLAG_A64_TBID, split out gen_top_byte_ignore | ||
53 | target/arm: Clean TBI for data operations in the translator | ||
54 | target/arm: Enable TBI for user-only | ||
55 | 50 | ||
56 | tests/tcg/aarch64/Makefile.target | 6 +- | 51 | Richard Henderson (9): |
57 | include/exec/memattrs.h | 10 + | 52 | target/arm: Reduce dcz_blocksize to uint8_t |
58 | linux-user/aarch64/target_syscall.h | 7 + | 53 | target/arm: Allow cpu to configure GM blocksize |
59 | target/arm/cpu.h | 27 +- | 54 | target/arm: Support more GM blocksizes |
60 | target/arm/internals.h | 27 +- | 55 | target/arm: When tag memory is not present, set MTE=1 |
61 | target/arm/translate.h | 12 +- | 56 | target/arm: Introduce make_ccsidr64 |
62 | gdbstub.c | 4 + | 57 | target/arm: Apply access checks to neoverse-n1 special registers |
63 | hw/arm/boot.c | 166 +++++++------ | 58 | target/arm: Apply access checks to neoverse-v1 special registers |
64 | linux-user/syscall.c | 36 +++ | 59 | target/arm: Suppress FEAT_TRBE (Trace Buffer Extension) |
65 | target/arm/cpu.c | 6 + | 60 | target/arm: Implement FEAT_HPDS2 as a no-op |
66 | target/arm/cpu64.c | 4 + | ||
67 | target/arm/helper.c | 80 +++--- | ||
68 | target/arm/translate-a64.c | 476 +++++++++++++++++++++++++----------- | ||
69 | tests/tcg/aarch64/pauth-1.c | 23 ++ | ||
70 | 14 files changed, 623 insertions(+), 261 deletions(-) | ||
71 | create mode 100644 tests/tcg/aarch64/pauth-1.c | ||
72 | 61 | ||
62 | docs/system/arm/emulation.rst | 2 + | ||
63 | include/hw/arm/armsse.h | 5 + | ||
64 | include/hw/arm/armv7m.h | 8 + | ||
65 | include/hw/arm/fsl-imx6ul.h | 158 ++++++++++++++++--- | ||
66 | include/hw/arm/fsl-imx7.h | 338 ++++++++++++++++++++++++++++++----------- | ||
67 | include/hw/misc/imx7_src.h | 66 ++++++++ | ||
68 | include/hw/rtc/aspeed_rtc.h | 2 +- | ||
69 | include/sysemu/rtc.h | 4 +- | ||
70 | target/arm/cpregs.h | 2 + | ||
71 | target/arm/cpu.h | 5 +- | ||
72 | target/arm/internals.h | 6 - | ||
73 | target/arm/tcg/translate.h | 2 + | ||
74 | hw/arm/armsse.c | 16 ++ | ||
75 | hw/arm/armv7m.c | 21 +++ | ||
76 | hw/arm/fsl-imx6ul.c | 174 +++++++++++++-------- | ||
77 | hw/arm/fsl-imx7.c | 201 +++++++++++++++++++----- | ||
78 | hw/arm/mps2-tz.c | 29 ++++ | ||
79 | hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++ | ||
80 | hw/rtc/aspeed_rtc.c | 5 +- | ||
81 | hw/rtc/m48t59.c | 2 +- | ||
82 | hw/rtc/twl92230.c | 4 +- | ||
83 | softmmu/rtc.c | 4 +- | ||
84 | target/arm/cpu.c | 207 ++++++++++++++----------- | ||
85 | target/arm/helper.c | 15 +- | ||
86 | target/arm/tcg/cpu32.c | 2 +- | ||
87 | target/arm/tcg/cpu64.c | 102 +++++++++---- | ||
88 | target/arm/tcg/helper-a64.c | 9 ++ | ||
89 | target/arm/tcg/mte_helper.c | 90 ++++++++--- | ||
90 | target/arm/tcg/translate-a64.c | 5 +- | ||
91 | hw/misc/meson.build | 1 + | ||
92 | hw/misc/trace-events | 4 + | ||
93 | 31 files changed, 1393 insertions(+), 372 deletions(-) | ||
94 | create mode 100644 include/hw/misc/imx7_src.h | ||
95 | create mode 100644 hw/misc/imx7_src.c | ||
96 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
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2 | |||
3 | This value is only 4 bits wide. | ||
2 | 4 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20190128223118.5255-4-richard.henderson@linaro.org | 7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Message-id: 20230811214031.171020-2-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 10 | --- |
8 | target/arm/cpu.h | 2 ++ | 11 | target/arm/cpu.h | 3 ++- |
9 | target/arm/translate.h | 4 ++++ | 12 | 1 file changed, 2 insertions(+), 1 deletion(-) |
10 | target/arm/helper.c | 22 +++++++++++++++------- | ||
11 | target/arm/translate-a64.c | 2 ++ | ||
12 | 4 files changed, 23 insertions(+), 7 deletions(-) | ||
13 | 13 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 16 | --- a/target/arm/cpu.h |
17 | +++ b/target/arm/cpu.h | 17 | +++ b/target/arm/cpu.h |
18 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, TBII, 0, 2) | 18 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
19 | FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) | 19 | bool prop_lpa2; |
20 | FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) | 20 | |
21 | FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) | 21 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ |
22 | +FIELD(TBFLAG_A64, BT, 9, 1) | 22 | - uint32_t dcz_blocksize; |
23 | +FIELD(TBFLAG_A64, BTYPE, 10, 2) | 23 | + uint8_t dcz_blocksize; |
24 | |||
25 | static inline bool bswap_code(bool sctlr_b) | ||
26 | { | ||
27 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/translate.h | ||
30 | +++ b/target/arm/translate.h | ||
31 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | ||
32 | bool ss_same_el; | ||
33 | /* True if v8.3-PAuth is active. */ | ||
34 | bool pauth_active; | ||
35 | + /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ | ||
36 | + bool bt; | ||
37 | + /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ | ||
38 | + uint8_t btype; | ||
39 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ | ||
40 | int c15_cpar; | ||
41 | /* TCG op of the current insn_start. */ | ||
42 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/helper.c | ||
45 | +++ b/target/arm/helper.c | ||
46 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
47 | |||
48 | if (is_a64(env)) { | ||
49 | ARMCPU *cpu = arm_env_get_cpu(env); | ||
50 | + uint64_t sctlr; | ||
51 | |||
52 | *pc = env->pc; | ||
53 | flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); | ||
54 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
55 | flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); | ||
56 | } | ||
57 | |||
58 | + if (current_el == 0) { | ||
59 | + /* FIXME: ARMv8.1-VHE S2 translation regime. */ | ||
60 | + sctlr = env->cp15.sctlr_el[1]; | ||
61 | + } else { | ||
62 | + sctlr = env->cp15.sctlr_el[current_el]; | ||
63 | + } | ||
64 | if (cpu_isar_feature(aa64_pauth, cpu)) { | ||
65 | /* | ||
66 | * In order to save space in flags, we record only whether | ||
67 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
68 | * a nop, or "active" when some action must be performed. | ||
69 | * The decision of which action to take is left to a helper. | ||
70 | */ | ||
71 | - uint64_t sctlr; | ||
72 | - if (current_el == 0) { | ||
73 | - /* FIXME: ARMv8.1-VHE S2 translation regime. */ | ||
74 | - sctlr = env->cp15.sctlr_el[1]; | ||
75 | - } else { | ||
76 | - sctlr = env->cp15.sctlr_el[current_el]; | ||
77 | - } | ||
78 | if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { | ||
79 | flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); | ||
80 | } | ||
81 | } | ||
82 | + | 24 | + |
83 | + if (cpu_isar_feature(aa64_bti, cpu)) { | 25 | uint64_t rvbar_prop; /* Property/input signals. */ |
84 | + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ | 26 | |
85 | + if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { | 27 | /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ |
86 | + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); | ||
87 | + } | ||
88 | + flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); | ||
89 | + } | ||
90 | } else { | ||
91 | *pc = env->regs[15]; | ||
92 | flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); | ||
93 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | --- a/target/arm/translate-a64.c | ||
96 | +++ b/target/arm/translate-a64.c | ||
97 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | ||
98 | dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL); | ||
99 | dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16; | ||
100 | dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); | ||
101 | + dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); | ||
102 | + dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); | ||
103 | dc->vec_len = 0; | ||
104 | dc->vec_stride = 0; | ||
105 | dc->cp_regs = arm_cpu->cp_regs; | ||
106 | -- | 28 | -- |
107 | 2.20.1 | 29 | 2.34.1 |
108 | 30 | ||
109 | 31 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Split out gen_top_byte_ignore in preparation of handling these | 3 | Previously we hard-coded the blocksize with GMID_EL1_BS. |
4 | data accesses; the new tbflags field is not yet honored. | 4 | But the value we choose for -cpu max does not match the |
5 | value that cortex-a710 uses. | ||
6 | |||
7 | Mirror the way we handle dcz_blocksize. | ||
5 | 8 | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20190204132126.3255-2-richard.henderson@linaro.org | 11 | Message-id: 20230811214031.171020-3-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | target/arm/cpu.h | 1 + | 14 | target/arm/cpu.h | 2 ++ |
12 | target/arm/translate.h | 3 +- | 15 | target/arm/internals.h | 6 ----- |
13 | target/arm/helper.c | 1 + | 16 | target/arm/tcg/translate.h | 2 ++ |
14 | target/arm/translate-a64.c | 72 +++++++++++++++++++------------------- | 17 | target/arm/helper.c | 11 +++++--- |
15 | 4 files changed, 40 insertions(+), 37 deletions(-) | 18 | target/arm/tcg/cpu64.c | 1 + |
19 | target/arm/tcg/mte_helper.c | 46 ++++++++++++++++++++++------------ | ||
20 | target/arm/tcg/translate-a64.c | 5 ++-- | ||
21 | 7 files changed, 45 insertions(+), 28 deletions(-) | ||
16 | 22 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 23 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h |
18 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 25 | --- a/target/arm/cpu.h |
20 | +++ b/target/arm/cpu.h | 26 | +++ b/target/arm/cpu.h |
21 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) | 27 | @@ -XXX,XX +XXX,XX @@ struct ArchCPU { |
22 | FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) | 28 | |
23 | FIELD(TBFLAG_A64, BT, 9, 1) | 29 | /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ |
24 | FIELD(TBFLAG_A64, BTYPE, 10, 2) | 30 | uint8_t dcz_blocksize; |
25 | +FIELD(TBFLAG_A64, TBID, 12, 2) | 31 | + /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ |
26 | 32 | + uint8_t gm_blocksize; | |
27 | static inline bool bswap_code(bool sctlr_b) | 33 | |
28 | { | 34 | uint64_t rvbar_prop; /* Property/input signals. */ |
29 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 35 | |
30 | index XXXXXXX..XXXXXXX 100644 | 36 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
31 | --- a/target/arm/translate.h | 37 | index XXXXXXX..XXXXXXX 100644 |
32 | +++ b/target/arm/translate.h | 38 | --- a/target/arm/internals.h |
39 | +++ b/target/arm/internals.h | ||
40 | @@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs); | ||
41 | |||
42 | #endif /* !CONFIG_USER_ONLY */ | ||
43 | |||
44 | -/* | ||
45 | - * The log2 of the words in the tag block, for GMID_EL1.BS. | ||
46 | - * The is the maximum, 256 bytes, which manipulates 64-bits of tags. | ||
47 | - */ | ||
48 | -#define GMID_EL1_BS 6 | ||
49 | - | ||
50 | /* | ||
51 | * SVE predicates are 1/8 the size of SVE vectors, and cannot use | ||
52 | * the same simd_desc() encoding due to restrictions on size. | ||
53 | diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/target/arm/tcg/translate.h | ||
56 | +++ b/target/arm/tcg/translate.h | ||
33 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 57 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { |
34 | int user; | 58 | int8_t btype; |
35 | #endif | 59 | /* A copy of cpu->dcz_blocksize. */ |
36 | ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ | 60 | uint8_t dcz_blocksize; |
37 | - uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */ | 61 | + /* A copy of cpu->gm_blocksize. */ |
38 | + uint8_t tbii; /* TBI1|TBI0 for insns */ | 62 | + uint8_t gm_blocksize; |
39 | + uint8_t tbid; /* TBI1|TBI0 for data */ | 63 | /* True if this page is guarded. */ |
40 | bool ns; /* Use non-secure CPREG bank on access */ | 64 | bool guarded_page; |
41 | int fp_excp_el; /* FP exception EL or 0 if enabled */ | 65 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ |
42 | int sve_excp_el; /* SVE exception EL or 0 if enabled */ | ||
43 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 66 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
44 | index XXXXXXX..XXXXXXX 100644 | 67 | index XXXXXXX..XXXXXXX 100644 |
45 | --- a/target/arm/helper.c | 68 | --- a/target/arm/helper.c |
46 | +++ b/target/arm/helper.c | 69 | +++ b/target/arm/helper.c |
47 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | 70 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = { |
48 | } | 71 | .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, |
49 | 72 | .access = PL1_RW, .accessfn = access_mte, | |
50 | flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); | 73 | .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, |
51 | + flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); | 74 | - { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, |
52 | } | 75 | - .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, |
76 | - .access = PL1_R, .accessfn = access_aa64_tid5, | ||
77 | - .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, | ||
78 | { .name = "TCO", .state = ARM_CP_STATE_AA64, | ||
79 | .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, | ||
80 | .type = ARM_CP_NO_RAW, | ||
81 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
82 | * then define only a RAZ/WI version of PSTATE.TCO. | ||
83 | */ | ||
84 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
85 | + ARMCPRegInfo gmid_reginfo = { | ||
86 | + .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, | ||
87 | + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, | ||
88 | + .access = PL1_R, .accessfn = access_aa64_tid5, | ||
89 | + .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, | ||
90 | + }; | ||
91 | + define_one_arm_cp_reg(cpu, &gmid_reginfo); | ||
92 | define_arm_cp_regs(cpu, mte_reginfo); | ||
93 | define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); | ||
94 | } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { | ||
95 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
96 | index XXXXXXX..XXXXXXX 100644 | ||
97 | --- a/target/arm/tcg/cpu64.c | ||
98 | +++ b/target/arm/tcg/cpu64.c | ||
99 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
100 | cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ | ||
101 | cpu->dcz_blocksize = 7; /* 512 bytes */ | ||
53 | #endif | 102 | #endif |
54 | 103 | + cpu->gm_blocksize = 6; /* 256 bytes */ | |
55 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 104 | |
56 | index XXXXXXX..XXXXXXX 100644 | 105 | cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); |
57 | --- a/target/arm/translate-a64.c | 106 | cpu->sme_vq.supported = SVE_VQ_POW2_MAP; |
58 | +++ b/target/arm/translate-a64.c | 107 | diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c |
59 | @@ -XXX,XX +XXX,XX @@ void gen_a64_set_pc_im(uint64_t val) | 108 | index XXXXXXX..XXXXXXX 100644 |
60 | tcg_gen_movi_i64(cpu_pc, val); | 109 | --- a/target/arm/tcg/mte_helper.c |
110 | +++ b/target/arm/tcg/mte_helper.c | ||
111 | @@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) | ||
112 | } | ||
61 | } | 113 | } |
62 | 114 | ||
63 | -/* Load the PC from a generic TCG variable. | 115 | -#define LDGM_STGM_SIZE (4 << GMID_EL1_BS) |
64 | +/* | 116 | - |
65 | + * Handle Top Byte Ignore (TBI) bits. | 117 | uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) |
66 | * | ||
67 | - * If address tagging is enabled via the TCR TBI bits, then loading | ||
68 | - * an address into the PC will clear out any tag in it: | ||
69 | + * If address tagging is enabled via the TCR TBI bits: | ||
70 | * + for EL2 and EL3 there is only one TBI bit, and if it is set | ||
71 | * then the address is zero-extended, clearing bits [63:56] | ||
72 | * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0 | ||
73 | @@ -XXX,XX +XXX,XX @@ void gen_a64_set_pc_im(uint64_t val) | ||
74 | * If the appropriate TBI bit is set for the address then | ||
75 | * the address is sign-extended from bit 55 into bits [63:56] | ||
76 | * | ||
77 | - * We can avoid doing this for relative-branches, because the | ||
78 | - * PC + offset can never overflow into the tag bits (assuming | ||
79 | - * that virtual addresses are less than 56 bits wide, as they | ||
80 | - * are currently), but we must handle it for branch-to-register. | ||
81 | + * Here We have concatenated TBI{1,0} into tbi. | ||
82 | */ | ||
83 | -static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) | ||
84 | +static void gen_top_byte_ignore(DisasContext *s, TCGv_i64 dst, | ||
85 | + TCGv_i64 src, int tbi) | ||
86 | { | 118 | { |
87 | - /* Note that TBII is TBI1:TBI0. */ | 119 | int mmu_idx = cpu_mmu_index(env, false); |
88 | - int tbi = s->tbii; | 120 | uintptr_t ra = GETPC(); |
89 | - | 121 | + int gm_bs = env_archcpu(env)->gm_blocksize; |
90 | - if (s->current_el <= 1) { | 122 | + int gm_bs_bytes = 4 << gm_bs; |
91 | - if (tbi != 0) { | 123 | void *tag_mem; |
92 | - /* Sign-extend from bit 55. */ | 124 | |
93 | - tcg_gen_sextract_i64(cpu_pc, src, 0, 56); | 125 | - ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); |
94 | - | 126 | + ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); |
95 | - if (tbi != 3) { | 127 | |
96 | - TCGv_i64 tcg_zero = tcg_const_i64(0); | 128 | /* Trap if accessing an invalid page. */ |
97 | - | 129 | tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, |
98 | - /* | 130 | - LDGM_STGM_SIZE, MMU_DATA_LOAD, |
99 | - * The two TBI bits differ. | 131 | - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); |
100 | - * If tbi0, then !tbi1: only use the extension if positive. | 132 | + gm_bs_bytes, MMU_DATA_LOAD, |
101 | - * if !tbi0, then tbi1: only use the extension if negative. | 133 | + gm_bs_bytes / (2 * TAG_GRANULE), ra); |
102 | - */ | 134 | |
103 | - tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT, | 135 | /* The tag is squashed to zero if the page does not support tags. */ |
104 | - cpu_pc, cpu_pc, tcg_zero, cpu_pc, src); | 136 | if (!tag_mem) { |
105 | - tcg_temp_free_i64(tcg_zero); | 137 | return 0; |
106 | - } | 138 | } |
107 | - return; | 139 | |
108 | - } | 140 | - QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); |
109 | + if (tbi == 0) { | 141 | /* |
110 | + /* Load unmodified address */ | 142 | - * We are loading 64-bits worth of tags. The ordering of elements |
111 | + tcg_gen_mov_i64(dst, src); | 143 | - * within the word corresponds to a 64-bit little-endian operation. |
112 | + } else if (s->current_el >= 2) { | 144 | + * The ordering of elements within the word corresponds to |
113 | + /* FIXME: ARMv8.1-VHE S2 translation regime. */ | 145 | + * a little-endian operation. |
114 | + /* Force tag byte to all zero */ | 146 | */ |
115 | + tcg_gen_extract_i64(dst, src, 0, 56); | 147 | - return ldq_le_p(tag_mem); |
148 | + switch (gm_bs) { | ||
149 | + case 6: | ||
150 | + /* 256 bytes -> 16 tags -> 64 result bits */ | ||
151 | + return ldq_le_p(tag_mem); | ||
152 | + default: | ||
153 | + /* cpu configured with unsupported gm blocksize. */ | ||
154 | + g_assert_not_reached(); | ||
155 | + } | ||
156 | } | ||
157 | |||
158 | void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
159 | { | ||
160 | int mmu_idx = cpu_mmu_index(env, false); | ||
161 | uintptr_t ra = GETPC(); | ||
162 | + int gm_bs = env_archcpu(env)->gm_blocksize; | ||
163 | + int gm_bs_bytes = 4 << gm_bs; | ||
164 | void *tag_mem; | ||
165 | |||
166 | - ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); | ||
167 | + ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | ||
168 | |||
169 | /* Trap if accessing an invalid page. */ | ||
170 | tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, | ||
171 | - LDGM_STGM_SIZE, MMU_DATA_LOAD, | ||
172 | - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); | ||
173 | + gm_bs_bytes, MMU_DATA_LOAD, | ||
174 | + gm_bs_bytes / (2 * TAG_GRANULE), ra); | ||
175 | |||
176 | /* | ||
177 | * Tag store only happens if the page support tags, | ||
178 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
179 | return; | ||
180 | } | ||
181 | |||
182 | - QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); | ||
183 | /* | ||
184 | - * We are storing 64-bits worth of tags. The ordering of elements | ||
185 | - * within the word corresponds to a 64-bit little-endian operation. | ||
186 | + * The ordering of elements within the word corresponds to | ||
187 | + * a little-endian operation. | ||
188 | */ | ||
189 | - stq_le_p(tag_mem, val); | ||
190 | + switch (gm_bs) { | ||
191 | + case 6: | ||
192 | + stq_le_p(tag_mem, val); | ||
193 | + break; | ||
194 | + default: | ||
195 | + /* cpu configured with unsupported gm blocksize. */ | ||
196 | + g_assert_not_reached(); | ||
197 | + } | ||
198 | } | ||
199 | |||
200 | void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
201 | diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c | ||
202 | index XXXXXXX..XXXXXXX 100644 | ||
203 | --- a/target/arm/tcg/translate-a64.c | ||
204 | +++ b/target/arm/tcg/translate-a64.c | ||
205 | @@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a) | ||
206 | gen_helper_stgm(cpu_env, addr, tcg_rt); | ||
116 | } else { | 207 | } else { |
117 | - if (tbi != 0) { | 208 | MMUAccessType acc = MMU_DATA_STORE; |
118 | - /* Force tag byte to all zero */ | 209 | - int size = 4 << GMID_EL1_BS; |
119 | - tcg_gen_extract_i64(cpu_pc, src, 0, 56); | 210 | + int size = 4 << s->gm_blocksize; |
120 | - return; | 211 | |
121 | + /* Sign-extend from bit 55. */ | 212 | clean_addr = clean_data_tbi(s, addr); |
122 | + tcg_gen_sextract_i64(dst, src, 0, 56); | 213 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); |
123 | + | 214 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a) |
124 | + if (tbi != 3) { | 215 | gen_helper_ldgm(tcg_rt, cpu_env, addr); |
125 | + TCGv_i64 tcg_zero = tcg_const_i64(0); | 216 | } else { |
126 | + | 217 | MMUAccessType acc = MMU_DATA_LOAD; |
127 | + /* | 218 | - int size = 4 << GMID_EL1_BS; |
128 | + * The two TBI bits differ. | 219 | + int size = 4 << s->gm_blocksize; |
129 | + * If tbi0, then !tbi1: only use the extension if positive. | 220 | |
130 | + * if !tbi0, then tbi1: only use the extension if negative. | 221 | clean_addr = clean_data_tbi(s, addr); |
131 | + */ | 222 | tcg_gen_andi_i64(clean_addr, clean_addr, -size); |
132 | + tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT, | ||
133 | + dst, dst, tcg_zero, dst, src); | ||
134 | + tcg_temp_free_i64(tcg_zero); | ||
135 | } | ||
136 | } | ||
137 | +} | ||
138 | |||
139 | - /* Load unmodified address */ | ||
140 | - tcg_gen_mov_i64(cpu_pc, src); | ||
141 | +static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) | ||
142 | +{ | ||
143 | + /* | ||
144 | + * If address tagging is enabled for instructions via the TCR TBI bits, | ||
145 | + * then loading an address into the PC will clear out any tag. | ||
146 | + */ | ||
147 | + gen_top_byte_ignore(s, cpu_pc, src, s->tbii); | ||
148 | } | ||
149 | |||
150 | typedef struct DisasCompare64 { | ||
151 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | 223 | @@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, |
152 | core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX); | 224 | dc->cp_regs = arm_cpu->cp_regs; |
153 | dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx); | 225 | dc->features = env->features; |
154 | dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII); | 226 | dc->dcz_blocksize = arm_cpu->dcz_blocksize; |
155 | + dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID); | 227 | + dc->gm_blocksize = arm_cpu->gm_blocksize; |
156 | dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx); | 228 | |
157 | #if !defined(CONFIG_USER_ONLY) | 229 | #ifdef CONFIG_USER_ONLY |
158 | dc->user = (dc->current_el == 0); | 230 | /* In sve_probe_page, we assume TBI is enabled. */ |
159 | -- | 231 | -- |
160 | 2.20.1 | 232 | 2.34.1 |
161 | |||
162 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Support all of the easy GM block sizes. | ||
4 | Use direct memory operations, since the pointers are aligned. | ||
5 | |||
6 | While BS=2 (16 bytes, 1 tag) is a legal setting, that requires | ||
7 | an atomic store of one nibble. This is not difficult, but there | ||
8 | is also no point in supporting it until required. | ||
9 | |||
10 | Note that cortex-a710 sets GM blocksize to match its cacheline | ||
11 | size of 64 bytes. I expect many implementations will also | ||
12 | match the cacheline, which makes 16 bytes very unlikely. | ||
13 | |||
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 16 | Message-id: 20230811214031.171020-4-richard.henderson@linaro.org |
5 | Message-id: 20190128223118.5255-9-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 18 | --- |
8 | target/arm/translate-a64.c | 37 ++++++++++++++++++++++++++++++++++++- | 19 | target/arm/cpu.c | 18 +++++++++--- |
9 | 1 file changed, 36 insertions(+), 1 deletion(-) | 20 | target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------ |
21 | 2 files changed, 62 insertions(+), 12 deletions(-) | ||
10 | 22 | ||
11 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 23 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
12 | index XXXXXXX..XXXXXXX 100644 | 24 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/translate-a64.c | 25 | --- a/target/arm/cpu.c |
14 | +++ b/target/arm/translate-a64.c | 26 | +++ b/target/arm/cpu.c |
15 | @@ -XXX,XX +XXX,XX @@ static void reset_btype(DisasContext *s) | 27 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
28 | ID_PFR1, VIRTUALIZATION, 0); | ||
16 | } | 29 | } |
30 | |||
31 | + if (cpu_isar_feature(aa64_mte, cpu)) { | ||
32 | + /* | ||
33 | + * The architectural range of GM blocksize is 2-6, however qemu | ||
34 | + * doesn't support blocksize of 2 (see HELPER(ldgm)). | ||
35 | + */ | ||
36 | + if (tcg_enabled()) { | ||
37 | + assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6); | ||
38 | + } | ||
39 | + | ||
40 | #ifndef CONFIG_USER_ONLY | ||
41 | - if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) { | ||
42 | /* | ||
43 | * Disable the MTE feature bits if we do not have tag-memory | ||
44 | * provided by the machine. | ||
45 | */ | ||
46 | - cpu->isar.id_aa64pfr1 = | ||
47 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
48 | - } | ||
49 | + if (cpu->tag_memory == NULL) { | ||
50 | + cpu->isar.id_aa64pfr1 = | ||
51 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | ||
52 | + } | ||
53 | #endif | ||
54 | + } | ||
55 | |||
56 | if (tcg_enabled()) { | ||
57 | /* | ||
58 | diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/tcg/mte_helper.c | ||
61 | +++ b/target/arm/tcg/mte_helper.c | ||
62 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) | ||
63 | int gm_bs = env_archcpu(env)->gm_blocksize; | ||
64 | int gm_bs_bytes = 4 << gm_bs; | ||
65 | void *tag_mem; | ||
66 | + uint64_t ret; | ||
67 | + int shift; | ||
68 | |||
69 | ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); | ||
70 | |||
71 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) | ||
72 | |||
73 | /* | ||
74 | * The ordering of elements within the word corresponds to | ||
75 | - * a little-endian operation. | ||
76 | + * a little-endian operation. Computation of shift comes from | ||
77 | + * | ||
78 | + * index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE> | ||
79 | + * data<index*4+3:index*4> = tag | ||
80 | + * | ||
81 | + * Because of the alignment of ptr above, BS=6 has shift=0. | ||
82 | + * All memory operations are aligned. Defer support for BS=2, | ||
83 | + * requiring insertion or extraction of a nibble, until we | ||
84 | + * support a cpu that requires it. | ||
85 | */ | ||
86 | switch (gm_bs) { | ||
87 | + case 3: | ||
88 | + /* 32 bytes -> 2 tags -> 8 result bits */ | ||
89 | + ret = *(uint8_t *)tag_mem; | ||
90 | + break; | ||
91 | + case 4: | ||
92 | + /* 64 bytes -> 4 tags -> 16 result bits */ | ||
93 | + ret = cpu_to_le16(*(uint16_t *)tag_mem); | ||
94 | + break; | ||
95 | + case 5: | ||
96 | + /* 128 bytes -> 8 tags -> 32 result bits */ | ||
97 | + ret = cpu_to_le32(*(uint32_t *)tag_mem); | ||
98 | + break; | ||
99 | case 6: | ||
100 | /* 256 bytes -> 16 tags -> 64 result bits */ | ||
101 | - return ldq_le_p(tag_mem); | ||
102 | + return cpu_to_le64(*(uint64_t *)tag_mem); | ||
103 | default: | ||
104 | - /* cpu configured with unsupported gm blocksize. */ | ||
105 | + /* | ||
106 | + * CPU configured with unsupported/invalid gm blocksize. | ||
107 | + * This is detected early in arm_cpu_realizefn. | ||
108 | + */ | ||
109 | g_assert_not_reached(); | ||
110 | } | ||
111 | + shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; | ||
112 | + return ret << shift; | ||
17 | } | 113 | } |
18 | 114 | ||
19 | +static void set_btype(DisasContext *s, int val) | 115 | void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) |
20 | +{ | 116 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) |
21 | + TCGv_i32 tcg_val; | 117 | int gm_bs = env_archcpu(env)->gm_blocksize; |
22 | + | 118 | int gm_bs_bytes = 4 << gm_bs; |
23 | + /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ | 119 | void *tag_mem; |
24 | + tcg_debug_assert(val >= 1 && val <= 3); | 120 | + int shift; |
25 | + | 121 | |
26 | + tcg_val = tcg_const_i32(val); | 122 | ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); |
27 | + tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); | 123 | |
28 | + tcg_temp_free_i32(tcg_val); | 124 | @@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) |
29 | + s->btype = -1; | ||
30 | +} | ||
31 | + | ||
32 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | ||
33 | fprintf_function cpu_fprintf, int flags) | ||
34 | { | ||
35 | @@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn) | ||
36 | static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
37 | { | ||
38 | unsigned int opc, op2, op3, rn, op4; | ||
39 | + unsigned btype_mod = 2; /* 0: BR, 1: BLR, 2: other */ | ||
40 | TCGv_i64 dst; | ||
41 | TCGv_i64 modifier; | ||
42 | |||
43 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
44 | case 0: /* BR */ | ||
45 | case 1: /* BLR */ | ||
46 | case 2: /* RET */ | ||
47 | + btype_mod = opc; | ||
48 | switch (op3) { | ||
49 | case 0: | ||
50 | /* BR, BLR, RET */ | ||
51 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
52 | default: | ||
53 | goto do_unallocated; | ||
54 | } | ||
55 | - | ||
56 | gen_a64_set_pc(s, dst); | ||
57 | /* BLR also needs to load return address */ | ||
58 | if (opc == 1) { | ||
59 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
60 | if ((op3 & ~1) != 2) { | ||
61 | goto do_unallocated; | ||
62 | } | ||
63 | + btype_mod = opc & 1; | ||
64 | if (s->pauth_active) { | ||
65 | dst = new_tmp_a64(s); | ||
66 | modifier = cpu_reg_sp(s, op4); | ||
67 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) | ||
68 | return; | 125 | return; |
69 | } | 126 | } |
70 | 127 | ||
71 | + switch (btype_mod) { | 128 | - /* |
72 | + case 0: /* BR */ | 129 | - * The ordering of elements within the word corresponds to |
73 | + if (dc_isar_feature(aa64_bti, s)) { | 130 | - * a little-endian operation. |
74 | + /* BR to {x16,x17} or !guard -> 1, else 3. */ | 131 | - */ |
75 | + set_btype(s, rn == 16 || rn == 17 || !s->guarded_page ? 1 : 3); | 132 | + /* See LDGM for comments on BS and on shift. */ |
76 | + } | 133 | + shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; |
134 | + val >>= shift; | ||
135 | switch (gm_bs) { | ||
136 | + case 3: | ||
137 | + /* 32 bytes -> 2 tags -> 8 result bits */ | ||
138 | + *(uint8_t *)tag_mem = val; | ||
77 | + break; | 139 | + break; |
78 | + | 140 | + case 4: |
79 | + case 1: /* BLR */ | 141 | + /* 64 bytes -> 4 tags -> 16 result bits */ |
80 | + if (dc_isar_feature(aa64_bti, s)) { | 142 | + *(uint16_t *)tag_mem = cpu_to_le16(val); |
81 | + /* BLR sets BTYPE to 2, regardless of source guarded page. */ | ||
82 | + set_btype(s, 2); | ||
83 | + } | ||
84 | + break; | 143 | + break; |
85 | + | 144 | + case 5: |
86 | + default: /* RET or none of the above. */ | 145 | + /* 128 bytes -> 8 tags -> 32 result bits */ |
87 | + /* BTYPE will be set to 0 by normal end-of-insn processing. */ | 146 | + *(uint32_t *)tag_mem = cpu_to_le32(val); |
88 | + break; | 147 | + break; |
89 | + } | 148 | case 6: |
90 | + | 149 | - stq_le_p(tag_mem, val); |
91 | s->base.is_jmp = DISAS_JUMP; | 150 | + /* 256 bytes -> 16 tags -> 64 result bits */ |
92 | } | 151 | + *(uint64_t *)tag_mem = cpu_to_le64(val); |
93 | 152 | break; | |
153 | default: | ||
154 | /* cpu configured with unsupported gm blocksize. */ | ||
94 | -- | 155 | -- |
95 | 2.20.1 | 156 | 2.34.1 |
96 | |||
97 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | When the cpu support MTE, but the system does not, reduce cpu | ||
4 | support to user instructions at EL0 instead of completely | ||
5 | disabling MTE. If we encounter a cpu implementation which does | ||
6 | something else, we can revisit this setting. | ||
7 | |||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Message-id: 20230811214031.171020-5-richard.henderson@linaro.org |
5 | Message-id: 20190201195404.30486-2-richard.henderson@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 12 | --- |
8 | linux-user/aarch64/target_syscall.h | 7 ++++++ | 13 | target/arm/cpu.c | 7 ++++--- |
9 | linux-user/syscall.c | 36 +++++++++++++++++++++++++++++ | 14 | 1 file changed, 4 insertions(+), 3 deletions(-) |
10 | 2 files changed, 43 insertions(+) | ||
11 | 15 | ||
12 | diff --git a/linux-user/aarch64/target_syscall.h b/linux-user/aarch64/target_syscall.h | 16 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
13 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/linux-user/aarch64/target_syscall.h | 18 | --- a/target/arm/cpu.c |
15 | +++ b/linux-user/aarch64/target_syscall.h | 19 | +++ b/target/arm/cpu.c |
16 | @@ -XXX,XX +XXX,XX @@ struct target_pt_regs { | 20 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
17 | #define TARGET_PR_SVE_SET_VL 50 | 21 | |
18 | #define TARGET_PR_SVE_GET_VL 51 | 22 | #ifndef CONFIG_USER_ONLY |
19 | 23 | /* | |
20 | +#define TARGET_PR_PAC_RESET_KEYS 54 | 24 | - * Disable the MTE feature bits if we do not have tag-memory |
21 | +# define TARGET_PR_PAC_APIAKEY (1 << 0) | 25 | - * provided by the machine. |
22 | +# define TARGET_PR_PAC_APIBKEY (1 << 1) | 26 | + * If we do not have tag-memory provided by the machine, |
23 | +# define TARGET_PR_PAC_APDAKEY (1 << 2) | 27 | + * reduce MTE support to instructions enabled at EL0. |
24 | +# define TARGET_PR_PAC_APDBKEY (1 << 3) | 28 | + * This matches Cortex-A710 BROADCASTMTE input being LOW. |
25 | +# define TARGET_PR_PAC_APGAKEY (1 << 4) | 29 | */ |
26 | + | 30 | if (cpu->tag_memory == NULL) { |
27 | void arm_init_pauth_key(ARMPACKey *key); | 31 | cpu->isar.id_aa64pfr1 = |
28 | 32 | - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); | |
29 | #endif /* AARCH64_TARGET_SYSCALL_H */ | 33 | + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1); |
30 | diff --git a/linux-user/syscall.c b/linux-user/syscall.c | 34 | } |
31 | index XXXXXXX..XXXXXXX 100644 | 35 | #endif |
32 | --- a/linux-user/syscall.c | 36 | } |
33 | +++ b/linux-user/syscall.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, | ||
35 | } | ||
36 | } | ||
37 | return ret; | ||
38 | + case TARGET_PR_PAC_RESET_KEYS: | ||
39 | + { | ||
40 | + CPUARMState *env = cpu_env; | ||
41 | + ARMCPU *cpu = arm_env_get_cpu(env); | ||
42 | + | ||
43 | + if (arg3 || arg4 || arg5) { | ||
44 | + return -TARGET_EINVAL; | ||
45 | + } | ||
46 | + if (cpu_isar_feature(aa64_pauth, cpu)) { | ||
47 | + int all = (TARGET_PR_PAC_APIAKEY | TARGET_PR_PAC_APIBKEY | | ||
48 | + TARGET_PR_PAC_APDAKEY | TARGET_PR_PAC_APDBKEY | | ||
49 | + TARGET_PR_PAC_APGAKEY); | ||
50 | + if (arg2 == 0) { | ||
51 | + arg2 = all; | ||
52 | + } else if (arg2 & ~all) { | ||
53 | + return -TARGET_EINVAL; | ||
54 | + } | ||
55 | + if (arg2 & TARGET_PR_PAC_APIAKEY) { | ||
56 | + arm_init_pauth_key(&env->apia_key); | ||
57 | + } | ||
58 | + if (arg2 & TARGET_PR_PAC_APIBKEY) { | ||
59 | + arm_init_pauth_key(&env->apib_key); | ||
60 | + } | ||
61 | + if (arg2 & TARGET_PR_PAC_APDAKEY) { | ||
62 | + arm_init_pauth_key(&env->apda_key); | ||
63 | + } | ||
64 | + if (arg2 & TARGET_PR_PAC_APDBKEY) { | ||
65 | + arm_init_pauth_key(&env->apdb_key); | ||
66 | + } | ||
67 | + if (arg2 & TARGET_PR_PAC_APGAKEY) { | ||
68 | + arm_init_pauth_key(&env->apga_key); | ||
69 | + } | ||
70 | + return 0; | ||
71 | + } | ||
72 | + } | ||
73 | + return -TARGET_EINVAL; | ||
74 | #endif /* AARCH64 */ | ||
75 | case PR_GET_SECCOMP: | ||
76 | case PR_SET_SECCOMP: | ||
77 | -- | 37 | -- |
78 | 2.20.1 | 38 | 2.34.1 |
79 | |||
80 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Also create field definitions for id_aa64pfr1 from ARMv8.5. | 3 | Do not hard-code the constants for Neoverse V1. |
4 | 4 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Message-id: 20230811214031.171020-6-richard.henderson@linaro.org |
7 | Message-id: 20190128223118.5255-2-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 9 | --- |
10 | target/arm/cpu.h | 10 ++++++++++ | 10 | target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++-------------- |
11 | 1 file changed, 10 insertions(+) | 11 | 1 file changed, 32 insertions(+), 16 deletions(-) |
12 | 12 | ||
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 13 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/cpu.h | 15 | --- a/target/arm/tcg/cpu64.c |
16 | +++ b/target/arm/cpu.h | 16 | +++ b/target/arm/tcg/cpu64.c |
17 | @@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, GIC, 24, 4) | 17 | @@ -XXX,XX +XXX,XX @@ |
18 | FIELD(ID_AA64PFR0, RAS, 28, 4) | 18 | #include "qemu/module.h" |
19 | FIELD(ID_AA64PFR0, SVE, 32, 4) | 19 | #include "qapi/visitor.h" |
20 | 20 | #include "hw/qdev-properties.h" | |
21 | +FIELD(ID_AA64PFR1, BT, 0, 4) | 21 | +#include "qemu/units.h" |
22 | +FIELD(ID_AA64PFR1, SBSS, 4, 4) | 22 | #include "internals.h" |
23 | +FIELD(ID_AA64PFR1, MTE, 8, 4) | 23 | #include "cpregs.h" |
24 | +FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) | 24 | |
25 | +static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize, | ||
26 | + unsigned cachesize) | ||
27 | +{ | ||
28 | + unsigned lg_linesize = ctz32(linesize); | ||
29 | + unsigned sets; | ||
25 | + | 30 | + |
26 | FIELD(ID_AA64MMFR0, PARANGE, 0, 4) | 31 | + /* |
27 | FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) | 32 | + * The 64-bit CCSIDR_EL1 format is: |
28 | FIELD(ID_AA64MMFR0, BIGEND, 8, 4) | 33 | + * [55:32] number of sets - 1 |
29 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_lor(const ARMISARegisters *id) | 34 | + * [23:3] associativity - 1 |
30 | return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0; | 35 | + * [2:0] log2(linesize) - 4 |
31 | } | 36 | + * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc |
32 | 37 | + */ | |
33 | +static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) | 38 | + assert(assoc != 0); |
34 | +{ | 39 | + assert(is_power_of_2(linesize)); |
35 | + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; | 40 | + assert(lg_linesize >= 4 && lg_linesize <= 7 + 4); |
41 | + | ||
42 | + /* sets * associativity * linesize == cachesize. */ | ||
43 | + sets = cachesize / (assoc * linesize); | ||
44 | + assert(cachesize % (assoc * linesize) == 0); | ||
45 | + | ||
46 | + return ((uint64_t)(sets - 1) << 32) | ||
47 | + | ((assoc - 1) << 3) | ||
48 | + | (lg_linesize - 4); | ||
36 | +} | 49 | +} |
37 | + | 50 | + |
38 | /* | 51 | static void aarch64_a35_initfn(Object *obj) |
39 | * Forward to the above feature tests given an ARMCPU pointer. | 52 | { |
40 | */ | 53 | ARMCPU *cpu = ARM_CPU(obj); |
54 | @@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj) | ||
55 | * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, | ||
56 | * but also says it implements CCIDX, which means they should be | ||
57 | * 64-bit format. So we here use values which are based on the textual | ||
58 | - * information in chapter 2 of the TRM (and on the fact that | ||
59 | - * sets * associativity * linesize == cachesize). | ||
60 | - * | ||
61 | - * The 64-bit CCSIDR_EL1 format is: | ||
62 | - * [55:32] number of sets - 1 | ||
63 | - * [23:3] associativity - 1 | ||
64 | - * [2:0] log2(linesize) - 4 | ||
65 | - * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc | ||
66 | - * | ||
67 | - * L1: 4-way set associative 64-byte line size, total size 64K, | ||
68 | - * so sets is 256. | ||
69 | + * information in chapter 2 of the TRM: | ||
70 | * | ||
71 | + * L1: 4-way set associative 64-byte line size, total size 64K. | ||
72 | * L2: 8-way set associative, 64 byte line size, either 512K or 1MB. | ||
73 | - * We pick 1MB, so this has 2048 sets. | ||
74 | - * | ||
75 | * L3: No L3 (this matches the CLIDR_EL1 value). | ||
76 | */ | ||
77 | - cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */ | ||
78 | - cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */ | ||
79 | - cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */ | ||
80 | + cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ | ||
81 | + cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ | ||
82 | + cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */ | ||
83 | |||
84 | /* From 3.2.115 SCTLR_EL3 */ | ||
85 | cpu->reset_sctlr = 0x30c50838; | ||
41 | -- | 86 | -- |
42 | 2.20.1 | 87 | 2.34.1 |
43 | |||
44 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Caching the bit means that we will not have to re-walk the | 3 | Access to many of the special registers is enabled or disabled |
4 | page tables to look up the bit during translation. | 4 | by ACTLR_EL[23], which we implement as constant 0, which means |
5 | that all writes outside EL3 should trap. | ||
5 | 6 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20190128223118.5255-6-richard.henderson@linaro.org | 9 | Message-id: 20230811214031.171020-7-richard.henderson@linaro.org |
9 | [PMM: no need to OR in guarded bit status] | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | target/arm/helper.c | 6 ++++++ | 12 | target/arm/cpregs.h | 2 ++ |
13 | 1 file changed, 6 insertions(+) | 13 | target/arm/helper.c | 4 ++-- |
14 | target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++--------- | ||
15 | 3 files changed, 41 insertions(+), 11 deletions(-) | ||
14 | 16 | ||
17 | diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/cpregs.h | ||
20 | +++ b/target/arm/cpregs.h | ||
21 | @@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } | ||
22 | void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); | ||
23 | #endif | ||
24 | |||
25 | +CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool); | ||
26 | + | ||
27 | #endif /* TARGET_ARM_CPREGS_H */ | ||
15 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 28 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/helper.c | 30 | --- a/target/arm/helper.c |
18 | +++ b/target/arm/helper.c | 31 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | 32 | @@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, |
20 | bool ttbr1_valid; | 33 | } |
21 | uint64_t descaddrmask; | 34 | |
22 | bool aarch64 = arm_el_is_aa64(env, el); | 35 | /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ |
23 | + bool guarded = false; | 36 | -static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, |
24 | 37 | - bool isread) | |
25 | /* TODO: | 38 | +CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri, |
26 | * This code does not handle the different format TCR for VTCR_EL2. | 39 | + bool isread) |
27 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | 40 | { |
28 | } | 41 | if (arm_current_el(env) == 1) { |
29 | /* Merge in attributes from table descriptors */ | 42 | uint64_t trap = isread ? HCR_TRVM : HCR_TVM; |
30 | attrs |= nstable << 3; /* NS */ | 43 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
31 | + guarded = extract64(descriptor, 50, 1); /* GP */ | 44 | index XXXXXXX..XXXXXXX 100644 |
32 | if (param.hpd) { | 45 | --- a/target/arm/tcg/cpu64.c |
33 | /* HPD disables all the table attributes except NSTable. */ | 46 | +++ b/target/arm/tcg/cpu64.c |
34 | break; | 47 | @@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj) |
35 | @@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, | 48 | /* TODO: Add A64FX specific HPC extension registers */ |
36 | */ | 49 | } |
37 | txattrs->secure = false; | 50 | |
38 | } | 51 | +static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r, |
39 | + /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */ | 52 | + bool read) |
40 | + if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { | 53 | +{ |
41 | + txattrs->target_tlb_bit0 = true; | 54 | + if (!read) { |
55 | + int el = arm_current_el(env); | ||
56 | + | ||
57 | + /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */ | ||
58 | + if (el < 2 && arm_is_el2_enabled(env)) { | ||
59 | + return CP_ACCESS_TRAP_EL2; | ||
60 | + } | ||
61 | + /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */ | ||
62 | + if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) { | ||
63 | + return CP_ACCESS_TRAP_EL3; | ||
64 | + } | ||
42 | + } | 65 | + } |
43 | 66 | + return CP_ACCESS_OK; | |
44 | if (cacheattrs != NULL) { | 67 | +} |
45 | if (mmu_idx == ARMMMUIdx_S2NS) { | 68 | + |
69 | static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
70 | { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64, | ||
71 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0, | ||
72 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
73 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
74 | + /* Traps and enables are the same as for TCR_EL1. */ | ||
75 | + .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, }, | ||
76 | { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64, | ||
77 | .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0, | ||
78 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
79 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
80 | .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
81 | { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
82 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0, | ||
83 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
84 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
85 | + .accessfn = access_actlr_w }, | ||
86 | { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64, | ||
87 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1, | ||
88 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
89 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
90 | + .accessfn = access_actlr_w }, | ||
91 | { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64, | ||
92 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2, | ||
93 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
94 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
95 | + .accessfn = access_actlr_w }, | ||
96 | /* | ||
97 | * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU | ||
98 | * (and in particular its system registers). | ||
99 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
100 | .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 }, | ||
101 | { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
102 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4, | ||
103 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 }, | ||
104 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010, | ||
105 | + .accessfn = access_actlr_w }, | ||
106 | { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64, | ||
107 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1, | ||
108 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
109 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = { | ||
110 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
111 | { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64, | ||
112 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, | ||
113 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
114 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
115 | + .accessfn = access_actlr_w }, | ||
116 | { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64, | ||
117 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2, | ||
118 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
119 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
120 | + .accessfn = access_actlr_w }, | ||
121 | { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64, | ||
122 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1, | ||
123 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
124 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
125 | + .accessfn = access_actlr_w }, | ||
126 | { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64, | ||
127 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, | ||
128 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
129 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, | ||
130 | + .accessfn = access_actlr_w }, | ||
131 | }; | ||
132 | |||
133 | static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) | ||
46 | -- | 134 | -- |
47 | 2.20.1 | 135 | 2.34.1 |
48 | |||
49 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This is all of the non-exception cases of DISAS_NORETURN. | 3 | There is only one additional EL1 register modeled, which |
4 | also needs to use access_actlr_w. | ||
4 | 5 | ||
5 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20190128223118.5255-8-richard.henderson@linaro.org | 8 | Message-id: 20230811214031.171020-8-richard.henderson@linaro.org |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/translate-a64.c | 6 ++++++ | 11 | target/arm/tcg/cpu64.c | 3 ++- |
11 | 1 file changed, 6 insertions(+) | 12 | 1 file changed, 2 insertions(+), 1 deletion(-) |
12 | 13 | ||
13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 14 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate-a64.c | 16 | --- a/target/arm/tcg/cpu64.c |
16 | +++ b/target/arm/translate-a64.c | 17 | +++ b/target/arm/tcg/cpu64.c |
17 | @@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) | 18 | @@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) |
18 | } | 19 | static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { |
19 | 20 | { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, | |
20 | /* B Branch / BL Branch with link */ | 21 | .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, |
21 | + reset_btype(s); | 22 | - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
22 | gen_goto_tb(s, 0, addr); | 23 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, |
23 | } | 24 | + .accessfn = access_actlr_w }, |
24 | 25 | { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, | |
25 | @@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) | 26 | .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, |
26 | tcg_cmp = read_cpu_reg(s, rt, sf); | 27 | .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
27 | label_match = gen_new_label(); | ||
28 | |||
29 | + reset_btype(s); | ||
30 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | ||
31 | tcg_cmp, 0, label_match); | ||
32 | |||
33 | @@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) | ||
34 | tcg_cmp = tcg_temp_new_i64(); | ||
35 | tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); | ||
36 | label_match = gen_new_label(); | ||
37 | + | ||
38 | + reset_btype(s); | ||
39 | tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, | ||
40 | tcg_cmp, 0, label_match); | ||
41 | tcg_temp_free_i64(tcg_cmp); | ||
42 | @@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) | ||
43 | addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; | ||
44 | cond = extract32(insn, 0, 4); | ||
45 | |||
46 | + reset_btype(s); | ||
47 | if (cond < 0x0e) { | ||
48 | /* genuinely conditional branches */ | ||
49 | TCGLabel *label_match = gen_new_label(); | ||
50 | @@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn, | ||
51 | * a self-modified code correctly and also to take | ||
52 | * any pending interrupts immediately. | ||
53 | */ | ||
54 | + reset_btype(s); | ||
55 | gen_goto_tb(s, 0, s->pc); | ||
56 | return; | ||
57 | default: | ||
58 | -- | 28 | -- |
59 | 2.20.1 | 29 | 2.34.1 |
60 | |||
61 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This has been enabled in the linux kernel since v3.11 | 3 | Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing |
4 | (commit d50240a5f6cea, 2013-09-03, | 4 | external to the cpu, which is out of scope for QEMU. |
5 | "arm64: mm: permit use of tagged pointers at EL0"). | ||
6 | 5 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Message-id: 20230811214031.171020-10-richard.henderson@linaro.org |
9 | Message-id: 20190204132126.3255-5-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 10 | --- |
12 | target/arm/cpu.c | 6 ++++++ | 11 | target/arm/cpu.c | 3 +++ |
13 | 1 file changed, 6 insertions(+) | 12 | 1 file changed, 3 insertions(+) |
14 | 13 | ||
15 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 14 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.c | 16 | --- a/target/arm/cpu.c |
18 | +++ b/target/arm/cpu.c | 17 | +++ b/target/arm/cpu.c |
19 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | 18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) |
20 | env->vfp.zcr_el[1] = cpu->sve_max_vq - 1; | 19 | /* FEAT_SPE (Statistical Profiling Extension) */ |
21 | env->vfp.zcr_el[2] = env->vfp.zcr_el[1]; | 20 | cpu->isar.id_aa64dfr0 = |
22 | env->vfp.zcr_el[3] = env->vfp.zcr_el[1]; | 21 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); |
23 | + /* | 22 | + /* FEAT_TRBE (Trace Buffer Extension) */ |
24 | + * Enable TBI0 and TBI1. While the real kernel only enables TBI0, | 23 | + cpu->isar.id_aa64dfr0 = |
25 | + * turning on both here will produce smaller code and otherwise | 24 | + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0); |
26 | + * make no difference to the user-level emulation. | 25 | /* FEAT_TRF (Self-hosted Trace Extension) */ |
27 | + */ | 26 | cpu->isar.id_aa64dfr0 = |
28 | + env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); | 27 | FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); |
29 | #else | ||
30 | /* Reset into the highest available EL */ | ||
31 | if (arm_feature(env, ARM_FEATURE_EL3)) { | ||
32 | -- | 28 | -- |
33 | 2.20.1 | 29 | 2.34.1 |
34 | |||
35 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | These bits can be used to cache target-specific data in cputlb | 3 | This feature allows the operating system to set TCR_ELx.HWU* |
4 | read from the page tables. | 4 | to allow the implementation to use the PBHA bits from the |
5 | block and page descriptors for for IMPLEMENTATION DEFINED | ||
6 | purposes. Since QEMU has no need to use these bits, we may | ||
7 | simply ignore them. | ||
5 | 8 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Message-id: 20190128223118.5255-5-richard.henderson@linaro.org | 11 | Message-id: 20230811214031.171020-11-richard.henderson@linaro.org |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 13 | --- |
11 | include/exec/memattrs.h | 10 ++++++++++ | 14 | docs/system/arm/emulation.rst | 1 + |
12 | 1 file changed, 10 insertions(+) | 15 | target/arm/tcg/cpu32.c | 2 +- |
16 | target/arm/tcg/cpu64.c | 2 +- | ||
17 | 3 files changed, 3 insertions(+), 2 deletions(-) | ||
13 | 18 | ||
14 | diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h | 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/exec/memattrs.h | 21 | --- a/docs/system/arm/emulation.rst |
17 | +++ b/include/exec/memattrs.h | 22 | +++ b/docs/system/arm/emulation.rst |
18 | @@ -XXX,XX +XXX,XX @@ typedef struct MemTxAttrs { | 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
19 | unsigned int user:1; | 24 | - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) |
20 | /* Requester ID (for MSI for example) */ | 25 | - FEAT_HCX (Support for the HCRX_EL2 register) |
21 | unsigned int requester_id:16; | 26 | - FEAT_HPDS (Hierarchical permission disables) |
22 | + /* | 27 | +- FEAT_HPDS2 (Translation table page-based hardware attributes) |
23 | + * The following are target-specific page-table bits. These are not | 28 | - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) |
24 | + * related to actual memory transactions at all. However, this structure | 29 | - FEAT_IDST (ID space trap handling) |
25 | + * is part of the tlb_fill interface, cached in the cputlb structure, | 30 | - FEAT_IESB (Implicit error synchronization event) |
26 | + * and has unused bits. These fields will be read by target-specific | 31 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c |
27 | + * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. | 32 | index XXXXXXX..XXXXXXX 100644 |
28 | + */ | 33 | --- a/target/arm/tcg/cpu32.c |
29 | + unsigned int target_tlb_bit0 : 1; | 34 | +++ b/target/arm/tcg/cpu32.c |
30 | + unsigned int target_tlb_bit1 : 1; | 35 | @@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu) |
31 | + unsigned int target_tlb_bit2 : 1; | 36 | cpu->isar.id_mmfr3 = t; |
32 | } MemTxAttrs; | 37 | |
33 | 38 | t = cpu->isar.id_mmfr4; | |
34 | /* Bus masters which don't specify any attributes will get this, | 39 | - t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ |
40 | + t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */ | ||
41 | t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ | ||
42 | t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ | ||
43 | t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ | ||
44 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/tcg/cpu64.c | ||
47 | +++ b/target/arm/tcg/cpu64.c | ||
48 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
49 | t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ | ||
50 | t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ | ||
51 | t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ | ||
52 | - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ | ||
53 | + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */ | ||
54 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ | ||
55 | t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */ | ||
56 | t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ | ||
35 | -- | 57 | -- |
36 | 2.20.1 | 58 | 2.34.1 |
37 | |||
38 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 3 | This is a mandatory feature for Armv8.1 architectures but we don't |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | state the feature clearly in our emulation list. Also include |
5 | Message-id: 20190128223118.5255-11-richard.henderson@linaro.org | 5 | FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping. |
6 | |||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
8 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
9 | Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org | ||
10 | Cc: qemu-stable@nongnu.org | ||
11 | Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org> | ||
12 | [PMM: pluralize 'instructions' in docs] | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 14 | --- |
8 | target/arm/cpu64.c | 4 ++++ | 15 | docs/system/arm/emulation.rst | 1 + |
9 | 1 file changed, 4 insertions(+) | 16 | target/arm/tcg/cpu64.c | 2 +- |
17 | 2 files changed, 2 insertions(+), 1 deletion(-) | ||
10 | 18 | ||
11 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 19 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
12 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/cpu64.c | 21 | --- a/docs/system/arm/emulation.rst |
14 | +++ b/target/arm/cpu64.c | 22 | +++ b/docs/system/arm/emulation.rst |
15 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | 23 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
16 | t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); | 24 | - FEAT_BBM at level 2 (Translation table break-before-make levels) |
17 | cpu->isar.id_aa64pfr0 = t; | 25 | - FEAT_BF16 (AArch64 BFloat16 instructions) |
18 | 26 | - FEAT_BTI (Branch Target Identification) | |
19 | + t = cpu->isar.id_aa64pfr1; | 27 | +- FEAT_CRC32 (CRC32 instructions) |
20 | + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); | 28 | - FEAT_CSV2 (Cache speculation variant 2) |
21 | + cpu->isar.id_aa64pfr1 = t; | 29 | - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) |
22 | + | 30 | - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) |
23 | t = cpu->isar.id_aa64mmfr1; | 31 | diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c |
24 | t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ | 32 | index XXXXXXX..XXXXXXX 100644 |
25 | t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); | 33 | --- a/target/arm/tcg/cpu64.c |
34 | +++ b/target/arm/tcg/cpu64.c | ||
35 | @@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj) | ||
36 | t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ | ||
37 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ | ||
38 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ | ||
39 | - t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); | ||
40 | + t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */ | ||
41 | t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ | ||
42 | t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ | ||
43 | t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ | ||
26 | -- | 44 | -- |
27 | 2.20.1 | 45 | 2.34.1 |
28 | 46 | ||
29 | 47 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
1 | 2 | ||
3 | i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device. | ||
4 | In particular, register 22 is not present on i.MX6UL and this is actualy | ||
5 | The only register that is really emulated in the i.MX7 IOMUX GPR device. | ||
6 | |||
7 | Note: The i.MX6UL code is actually also implementing the IOMUX GPR device | ||
8 | as an unimplemented device at the same bus adress and the 2 instantiations | ||
9 | were actualy colliding. So we go back to the unimplemented device for now. | ||
10 | |||
11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
12 | Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | include/hw/arm/fsl-imx6ul.h | 2 -- | ||
17 | hw/arm/fsl-imx6ul.c | 11 ----------- | ||
18 | 2 files changed, 13 deletions(-) | ||
19 | |||
20 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/include/hw/arm/fsl-imx6ul.h | ||
23 | +++ b/include/hw/arm/fsl-imx6ul.h | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #include "hw/misc/imx6ul_ccm.h" | ||
26 | #include "hw/misc/imx6_src.h" | ||
27 | #include "hw/misc/imx7_snvs.h" | ||
28 | -#include "hw/misc/imx7_gpr.h" | ||
29 | #include "hw/intc/imx_gpcv2.h" | ||
30 | #include "hw/watchdog/wdt_imx2.h" | ||
31 | #include "hw/gpio/imx_gpio.h" | ||
32 | @@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState { | ||
33 | IMX6SRCState src; | ||
34 | IMX7SNVSState snvs; | ||
35 | IMXGPCv2State gpcv2; | ||
36 | - IMX7GPRState gpr; | ||
37 | IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS]; | ||
38 | IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS]; | ||
39 | IMXSerialState uart[FSL_IMX6UL_NUM_UARTS]; | ||
40 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/hw/arm/fsl-imx6ul.c | ||
43 | +++ b/hw/arm/fsl-imx6ul.c | ||
44 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
45 | */ | ||
46 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
47 | |||
48 | - /* | ||
49 | - * GPR | ||
50 | - */ | ||
51 | - object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); | ||
52 | - | ||
53 | /* | ||
54 | * GPIOs 1 to 5 | ||
55 | */ | ||
56 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
57 | FSL_IMX6UL_WDOGn_IRQ[i])); | ||
58 | } | ||
59 | |||
60 | - /* | ||
61 | - * GPR | ||
62 | - */ | ||
63 | - sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); | ||
64 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR); | ||
65 | - | ||
66 | /* | ||
67 | * SDMA | ||
68 | */ | ||
69 | -- | ||
70 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
1 | 2 | ||
3 | * Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file. | ||
4 | * Use those newly defined named constants whenever possible. | ||
5 | * Standardize the way we init a familly of unimplemented devices | ||
6 | - SAI | ||
7 | - PWM | ||
8 | - CAN | ||
9 | * Add/rework few comments | ||
10 | |||
11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
12 | Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net | ||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++----- | ||
17 | hw/arm/fsl-imx6ul.c | 147 ++++++++++++++++++++++----------- | ||
18 | 2 files changed, 232 insertions(+), 71 deletions(-) | ||
19 | |||
20 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/include/hw/arm/fsl-imx6ul.h | ||
23 | +++ b/include/hw/arm/fsl-imx6ul.h | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #include "exec/memory.h" | ||
26 | #include "cpu.h" | ||
27 | #include "qom/object.h" | ||
28 | +#include "qemu/units.h" | ||
29 | |||
30 | #define TYPE_FSL_IMX6UL "fsl-imx6ul" | ||
31 | OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL) | ||
32 | @@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration { | ||
33 | FSL_IMX6UL_NUM_ADCS = 2, | ||
34 | FSL_IMX6UL_NUM_USB_PHYS = 2, | ||
35 | FSL_IMX6UL_NUM_USBS = 2, | ||
36 | + FSL_IMX6UL_NUM_SAIS = 3, | ||
37 | + FSL_IMX6UL_NUM_CANS = 2, | ||
38 | + FSL_IMX6UL_NUM_PWMS = 4, | ||
39 | }; | ||
40 | |||
41 | struct FslIMX6ULState { | ||
42 | @@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState { | ||
43 | |||
44 | enum FslIMX6ULMemoryMap { | ||
45 | FSL_IMX6UL_MMDC_ADDR = 0x80000000, | ||
46 | - FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, | ||
47 | + FSL_IMX6UL_MMDC_SIZE = (2 * GiB), | ||
48 | |||
49 | FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000, | ||
50 | - FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, | ||
51 | - FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, | ||
52 | - FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, | ||
53 | - FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, | ||
54 | + FSL_IMX6UL_QSPI1_MEM_SIZE = (256 * MiB), | ||
55 | |||
56 | - /* AIPS-2 */ | ||
57 | + FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000, | ||
58 | + FSL_IMX6UL_EIM_ALIAS_SIZE = (128 * MiB), | ||
59 | + | ||
60 | + FSL_IMX6UL_EIM_CS_ADDR = 0x50000000, | ||
61 | + FSL_IMX6UL_EIM_CS_SIZE = (128 * MiB), | ||
62 | + | ||
63 | + FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000, | ||
64 | + FSL_IMX6UL_AES_ENCRYPT_SIZE = (1 * MiB), | ||
65 | + | ||
66 | + FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000, | ||
67 | + FSL_IMX6UL_QSPI1_RX_SIZE = (32 * MiB), | ||
68 | + | ||
69 | + /* AIPS-2 Begin */ | ||
70 | FSL_IMX6UL_UART6_ADDR = 0x021FC000, | ||
71 | + | ||
72 | FSL_IMX6UL_I2C4_ADDR = 0x021F8000, | ||
73 | + | ||
74 | FSL_IMX6UL_UART5_ADDR = 0x021F4000, | ||
75 | FSL_IMX6UL_UART4_ADDR = 0x021F0000, | ||
76 | FSL_IMX6UL_UART3_ADDR = 0x021EC000, | ||
77 | FSL_IMX6UL_UART2_ADDR = 0x021E8000, | ||
78 | + | ||
79 | FSL_IMX6UL_WDOG3_ADDR = 0x021E4000, | ||
80 | + | ||
81 | FSL_IMX6UL_QSPI_ADDR = 0x021E0000, | ||
82 | + FSL_IMX6UL_QSPI_SIZE = 0x500, | ||
83 | + | ||
84 | FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000, | ||
85 | + FSL_IMX6UL_SYS_CNT_CTRL_SIZE = (16 * KiB), | ||
86 | + | ||
87 | FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000, | ||
88 | + FSL_IMX6UL_SYS_CNT_CMP_SIZE = (16 * KiB), | ||
89 | + | ||
90 | FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000, | ||
91 | + FSL_IMX6UL_SYS_CNT_RD_SIZE = (16 * KiB), | ||
92 | + | ||
93 | FSL_IMX6UL_TZASC_ADDR = 0x021D0000, | ||
94 | + FSL_IMX6UL_TZASC_SIZE = (16 * KiB), | ||
95 | + | ||
96 | FSL_IMX6UL_PXP_ADDR = 0x021CC000, | ||
97 | + FSL_IMX6UL_PXP_SIZE = (16 * KiB), | ||
98 | + | ||
99 | FSL_IMX6UL_LCDIF_ADDR = 0x021C8000, | ||
100 | + FSL_IMX6UL_LCDIF_SIZE = 0x100, | ||
101 | + | ||
102 | FSL_IMX6UL_CSI_ADDR = 0x021C4000, | ||
103 | + FSL_IMX6UL_CSI_SIZE = 0x100, | ||
104 | + | ||
105 | FSL_IMX6UL_CSU_ADDR = 0x021C0000, | ||
106 | + FSL_IMX6UL_CSU_SIZE = (16 * KiB), | ||
107 | + | ||
108 | FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000, | ||
109 | + FSL_IMX6UL_OCOTP_CTRL_SIZE = (4 * KiB), | ||
110 | + | ||
111 | FSL_IMX6UL_EIM_ADDR = 0x021B8000, | ||
112 | + FSL_IMX6UL_EIM_SIZE = 0x100, | ||
113 | + | ||
114 | FSL_IMX6UL_SIM2_ADDR = 0x021B4000, | ||
115 | + | ||
116 | FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000, | ||
117 | + FSL_IMX6UL_MMDC_CFG_SIZE = (4 * KiB), | ||
118 | + | ||
119 | FSL_IMX6UL_ROMCP_ADDR = 0x021AC000, | ||
120 | + FSL_IMX6UL_ROMCP_SIZE = 0x300, | ||
121 | + | ||
122 | FSL_IMX6UL_I2C3_ADDR = 0x021A8000, | ||
123 | FSL_IMX6UL_I2C2_ADDR = 0x021A4000, | ||
124 | FSL_IMX6UL_I2C1_ADDR = 0x021A0000, | ||
125 | + | ||
126 | FSL_IMX6UL_ADC2_ADDR = 0x0219C000, | ||
127 | FSL_IMX6UL_ADC1_ADDR = 0x02198000, | ||
128 | + FSL_IMX6UL_ADCn_SIZE = 0x100, | ||
129 | + | ||
130 | FSL_IMX6UL_USDHC2_ADDR = 0x02194000, | ||
131 | FSL_IMX6UL_USDHC1_ADDR = 0x02190000, | ||
132 | - FSL_IMX6UL_SIM1_ADDR = 0x0218C000, | ||
133 | - FSL_IMX6UL_ENET1_ADDR = 0x02188000, | ||
134 | - FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, | ||
135 | - FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000, | ||
136 | - FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000, | ||
137 | - FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000, | ||
138 | - FSL_IMX6UL_CAAM_ADDR = 0x02140000, | ||
139 | - FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000, | ||
140 | |||
141 | - /* AIPS-1 */ | ||
142 | + FSL_IMX6UL_SIM1_ADDR = 0x0218C000, | ||
143 | + FSL_IMX6UL_SIMn_SIZE = (16 * KiB), | ||
144 | + | ||
145 | + FSL_IMX6UL_ENET1_ADDR = 0x02188000, | ||
146 | + | ||
147 | + FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, | ||
148 | + FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000, | ||
149 | + FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200, | ||
150 | + | ||
151 | + FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000, | ||
152 | + FSL_IMX6UL_USBO2_PL301_SIZE = (16 * KiB), | ||
153 | + | ||
154 | + FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000, | ||
155 | + FSL_IMX6UL_AIPS2_CFG_SIZE = 0x100, | ||
156 | + | ||
157 | + FSL_IMX6UL_CAAM_ADDR = 0x02140000, | ||
158 | + FSL_IMX6UL_CAAM_SIZE = (16 * KiB), | ||
159 | + | ||
160 | + FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000, | ||
161 | + FSL_IMX6UL_A7MPCORE_DAP_SIZE = (4 * KiB), | ||
162 | + /* AIPS-2 End */ | ||
163 | + | ||
164 | + /* AIPS-1 Begin */ | ||
165 | FSL_IMX6UL_PWM8_ADDR = 0x020FC000, | ||
166 | FSL_IMX6UL_PWM7_ADDR = 0x020F8000, | ||
167 | FSL_IMX6UL_PWM6_ADDR = 0x020F4000, | ||
168 | FSL_IMX6UL_PWM5_ADDR = 0x020F0000, | ||
169 | + | ||
170 | FSL_IMX6UL_SDMA_ADDR = 0x020EC000, | ||
171 | + FSL_IMX6UL_SDMA_SIZE = 0x300, | ||
172 | + | ||
173 | FSL_IMX6UL_GPT2_ADDR = 0x020E8000, | ||
174 | + | ||
175 | FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000, | ||
176 | + FSL_IMX6UL_IOMUXC_GPR_SIZE = 0x40, | ||
177 | + | ||
178 | FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000, | ||
179 | + FSL_IMX6UL_IOMUXC_SIZE = 0x700, | ||
180 | + | ||
181 | FSL_IMX6UL_GPC_ADDR = 0x020DC000, | ||
182 | + | ||
183 | FSL_IMX6UL_SRC_ADDR = 0x020D8000, | ||
184 | + | ||
185 | FSL_IMX6UL_EPIT2_ADDR = 0x020D4000, | ||
186 | FSL_IMX6UL_EPIT1_ADDR = 0x020D0000, | ||
187 | + | ||
188 | FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000, | ||
189 | + | ||
190 | FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000, | ||
191 | - FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024), | ||
192 | FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000, | ||
193 | - FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024), | ||
194 | + | ||
195 | FSL_IMX6UL_ANALOG_ADDR = 0x020C8000, | ||
196 | + FSL_IMX6UL_ANALOG_SIZE = 0x300, | ||
197 | + | ||
198 | FSL_IMX6UL_CCM_ADDR = 0x020C4000, | ||
199 | + | ||
200 | FSL_IMX6UL_WDOG2_ADDR = 0x020C0000, | ||
201 | FSL_IMX6UL_WDOG1_ADDR = 0x020BC000, | ||
202 | + | ||
203 | FSL_IMX6UL_KPP_ADDR = 0x020B8000, | ||
204 | + FSL_IMX6UL_KPP_SIZE = 0x10, | ||
205 | + | ||
206 | FSL_IMX6UL_ENET2_ADDR = 0x020B4000, | ||
207 | + | ||
208 | FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000, | ||
209 | + FSL_IMX6UL_SNVS_LP_SIZE = (16 * KiB), | ||
210 | + | ||
211 | FSL_IMX6UL_GPIO5_ADDR = 0x020AC000, | ||
212 | FSL_IMX6UL_GPIO4_ADDR = 0x020A8000, | ||
213 | FSL_IMX6UL_GPIO3_ADDR = 0x020A4000, | ||
214 | FSL_IMX6UL_GPIO2_ADDR = 0x020A0000, | ||
215 | FSL_IMX6UL_GPIO1_ADDR = 0x0209C000, | ||
216 | + | ||
217 | FSL_IMX6UL_GPT1_ADDR = 0x02098000, | ||
218 | + | ||
219 | FSL_IMX6UL_CAN2_ADDR = 0x02094000, | ||
220 | FSL_IMX6UL_CAN1_ADDR = 0x02090000, | ||
221 | + FSL_IMX6UL_CANn_SIZE = (4 * KiB), | ||
222 | + | ||
223 | FSL_IMX6UL_PWM4_ADDR = 0x0208C000, | ||
224 | FSL_IMX6UL_PWM3_ADDR = 0x02088000, | ||
225 | FSL_IMX6UL_PWM2_ADDR = 0x02084000, | ||
226 | FSL_IMX6UL_PWM1_ADDR = 0x02080000, | ||
227 | + FSL_IMX6UL_PWMn_SIZE = 0x20, | ||
228 | + | ||
229 | FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000, | ||
230 | + FSL_IMX6UL_AIPS1_CFG_SIZE = (16 * KiB), | ||
231 | + | ||
232 | FSL_IMX6UL_BEE_ADDR = 0x02044000, | ||
233 | + FSL_IMX6UL_BEE_SIZE = (16 * KiB), | ||
234 | + | ||
235 | FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000, | ||
236 | + FSL_IMX6UL_TOUCH_CTRL_SIZE = 0x100, | ||
237 | + | ||
238 | FSL_IMX6UL_SPBA_ADDR = 0x0203C000, | ||
239 | + FSL_IMX6UL_SPBA_SIZE = 0x100, | ||
240 | + | ||
241 | FSL_IMX6UL_ASRC_ADDR = 0x02034000, | ||
242 | + FSL_IMX6UL_ASRC_SIZE = 0x100, | ||
243 | + | ||
244 | FSL_IMX6UL_SAI3_ADDR = 0x02030000, | ||
245 | FSL_IMX6UL_SAI2_ADDR = 0x0202C000, | ||
246 | FSL_IMX6UL_SAI1_ADDR = 0x02028000, | ||
247 | + FSL_IMX6UL_SAIn_SIZE = 0x200, | ||
248 | + | ||
249 | FSL_IMX6UL_UART8_ADDR = 0x02024000, | ||
250 | FSL_IMX6UL_UART1_ADDR = 0x02020000, | ||
251 | FSL_IMX6UL_UART7_ADDR = 0x02018000, | ||
252 | + | ||
253 | FSL_IMX6UL_ECSPI4_ADDR = 0x02014000, | ||
254 | FSL_IMX6UL_ECSPI3_ADDR = 0x02010000, | ||
255 | FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000, | ||
256 | FSL_IMX6UL_ECSPI1_ADDR = 0x02008000, | ||
257 | + | ||
258 | FSL_IMX6UL_SPDIF_ADDR = 0x02004000, | ||
259 | + FSL_IMX6UL_SPDIF_SIZE = 0x100, | ||
260 | + /* AIPS-1 End */ | ||
261 | + | ||
262 | + FSL_IMX6UL_BCH_ADDR = 0x01808000, | ||
263 | + FSL_IMX6UL_BCH_SIZE = 0x200, | ||
264 | + | ||
265 | + FSL_IMX6UL_GPMI_ADDR = 0x01806000, | ||
266 | + FSL_IMX6UL_GPMI_SIZE = 0x200, | ||
267 | |||
268 | FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000, | ||
269 | - FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024), | ||
270 | + FSL_IMX6UL_APBH_DMA_SIZE = (4 * KiB), | ||
271 | |||
272 | FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000, | ||
273 | |||
274 | FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000, | ||
275 | - FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000, | ||
276 | + FSL_IMX6UL_OCRAM_ALIAS_SIZE = (384 * KiB), | ||
277 | + | ||
278 | FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000, | ||
279 | - FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000, | ||
280 | + FSL_IMX6UL_OCRAM_MEM_SIZE = (128 * KiB), | ||
281 | + | ||
282 | FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000, | ||
283 | - FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000, | ||
284 | + FSL_IMX6UL_CAAM_MEM_SIZE = (32 * KiB), | ||
285 | + | ||
286 | FSL_IMX6UL_ROM_ADDR = 0x00000000, | ||
287 | - FSL_IMX6UL_ROM_SIZE = 0x00018000, | ||
288 | + FSL_IMX6UL_ROM_SIZE = (96 * KiB), | ||
289 | }; | ||
290 | |||
291 | enum FslIMX6ULIRQs { | ||
292 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c | ||
293 | index XXXXXXX..XXXXXXX 100644 | ||
294 | --- a/hw/arm/fsl-imx6ul.c | ||
295 | +++ b/hw/arm/fsl-imx6ul.c | ||
296 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
297 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
298 | |||
299 | /* | ||
300 | - * GPIOs 1 to 5 | ||
301 | + * GPIOs | ||
302 | */ | ||
303 | for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { | ||
304 | snprintf(name, NAME_SIZE, "gpio%d", i); | ||
305 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
306 | } | ||
307 | |||
308 | /* | ||
309 | - * GPT 1, 2 | ||
310 | + * GPTs | ||
311 | */ | ||
312 | for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { | ||
313 | snprintf(name, NAME_SIZE, "gpt%d", i); | ||
314 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
315 | } | ||
316 | |||
317 | /* | ||
318 | - * EPIT 1, 2 | ||
319 | + * EPITs | ||
320 | */ | ||
321 | for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { | ||
322 | snprintf(name, NAME_SIZE, "epit%d", i + 1); | ||
323 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
324 | } | ||
325 | |||
326 | /* | ||
327 | - * eCSPI | ||
328 | + * eCSPIs | ||
329 | */ | ||
330 | for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { | ||
331 | snprintf(name, NAME_SIZE, "spi%d", i + 1); | ||
332 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
333 | } | ||
334 | |||
335 | /* | ||
336 | - * I2C | ||
337 | + * I2Cs | ||
338 | */ | ||
339 | for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { | ||
340 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); | ||
341 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
342 | } | ||
343 | |||
344 | /* | ||
345 | - * UART | ||
346 | + * UARTs | ||
347 | */ | ||
348 | for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { | ||
349 | snprintf(name, NAME_SIZE, "uart%d", i); | ||
350 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
351 | } | ||
352 | |||
353 | /* | ||
354 | - * Ethernet | ||
355 | + * Ethernets | ||
356 | */ | ||
357 | for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) { | ||
358 | snprintf(name, NAME_SIZE, "eth%d", i); | ||
359 | object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET); | ||
360 | } | ||
361 | |||
362 | - /* USB */ | ||
363 | + /* | ||
364 | + * USB PHYs | ||
365 | + */ | ||
366 | for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { | ||
367 | snprintf(name, NAME_SIZE, "usbphy%d", i); | ||
368 | object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY); | ||
369 | } | ||
370 | + | ||
371 | + /* | ||
372 | + * USBs | ||
373 | + */ | ||
374 | for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { | ||
375 | snprintf(name, NAME_SIZE, "usb%d", i); | ||
376 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); | ||
377 | } | ||
378 | |||
379 | /* | ||
380 | - * SDHCI | ||
381 | + * SDHCIs | ||
382 | */ | ||
383 | for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | ||
384 | snprintf(name, NAME_SIZE, "usdhc%d", i); | ||
385 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj) | ||
386 | } | ||
387 | |||
388 | /* | ||
389 | - * Watchdog | ||
390 | + * Watchdogs | ||
391 | */ | ||
392 | for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { | ||
393 | snprintf(name, NAME_SIZE, "wdt%d", i); | ||
394 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
395 | * A7MPCORE DAP | ||
396 | */ | ||
397 | create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, | ||
398 | - 0x100000); | ||
399 | + FSL_IMX6UL_A7MPCORE_DAP_SIZE); | ||
400 | |||
401 | /* | ||
402 | - * GPT 1, 2 | ||
403 | + * GPTs | ||
404 | */ | ||
405 | for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) { | ||
406 | static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = { | ||
407 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
408 | } | ||
409 | |||
410 | /* | ||
411 | - * EPIT 1, 2 | ||
412 | + * EPITs | ||
413 | */ | ||
414 | for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) { | ||
415 | static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = { | ||
416 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
417 | } | ||
418 | |||
419 | /* | ||
420 | - * GPIO | ||
421 | + * GPIOs | ||
422 | */ | ||
423 | for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) { | ||
424 | static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = { | ||
425 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
426 | } | ||
427 | |||
428 | /* | ||
429 | - * IOMUXC and IOMUXC_GPR | ||
430 | + * IOMUXC | ||
431 | */ | ||
432 | - for (i = 0; i < 1; i++) { | ||
433 | - static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = { | ||
434 | - FSL_IMX6UL_IOMUXC_ADDR, | ||
435 | - FSL_IMX6UL_IOMUXC_GPR_ADDR, | ||
436 | - }; | ||
437 | - | ||
438 | - snprintf(name, NAME_SIZE, "iomuxc%d", i); | ||
439 | - create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000); | ||
440 | - } | ||
441 | + create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR, | ||
442 | + FSL_IMX6UL_IOMUXC_SIZE); | ||
443 | + create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR, | ||
444 | + FSL_IMX6UL_IOMUXC_GPR_SIZE); | ||
445 | |||
446 | /* | ||
447 | * CCM | ||
448 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
449 | sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); | ||
450 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR); | ||
451 | |||
452 | - /* Initialize all ECSPI */ | ||
453 | + /* | ||
454 | + * ECSPIs | ||
455 | + */ | ||
456 | for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) { | ||
457 | static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = { | ||
458 | FSL_IMX6UL_ECSPI1_ADDR, | ||
459 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
460 | } | ||
461 | |||
462 | /* | ||
463 | - * I2C | ||
464 | + * I2Cs | ||
465 | */ | ||
466 | for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) { | ||
467 | static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = { | ||
468 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
469 | } | ||
470 | |||
471 | /* | ||
472 | - * UART | ||
473 | + * UARTs | ||
474 | */ | ||
475 | for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) { | ||
476 | static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = { | ||
477 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
478 | } | ||
479 | |||
480 | /* | ||
481 | - * Ethernet | ||
482 | + * Ethernets | ||
483 | * | ||
484 | * We must use two loops since phy_connected affects the other interface | ||
485 | * and we have to set all properties before calling sysbus_realize(). | ||
486 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
487 | FSL_IMX6UL_ENETn_TIMER_IRQ[i])); | ||
488 | } | ||
489 | |||
490 | - /* USB */ | ||
491 | + /* | ||
492 | + * USB PHYs | ||
493 | + */ | ||
494 | for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) { | ||
495 | + static const hwaddr | ||
496 | + FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = { | ||
497 | + FSL_IMX6UL_USBPHY1_ADDR, | ||
498 | + FSL_IMX6UL_USBPHY2_ADDR, | ||
499 | + }; | ||
500 | + | ||
501 | sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort); | ||
502 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0, | ||
503 | - FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000); | ||
504 | + FSL_IMX6UL_USB_PHYn_ADDR[i]); | ||
505 | } | ||
506 | |||
507 | + /* | ||
508 | + * USBs | ||
509 | + */ | ||
510 | for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) { | ||
511 | + static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = { | ||
512 | + FSL_IMX6UL_USBO2_USB1_ADDR, | ||
513 | + FSL_IMX6UL_USBO2_USB2_ADDR, | ||
514 | + }; | ||
515 | + | ||
516 | static const int FSL_IMX6UL_USBn_IRQ[] = { | ||
517 | FSL_IMX6UL_USB1_IRQ, | ||
518 | FSL_IMX6UL_USB2_IRQ, | ||
519 | }; | ||
520 | + | ||
521 | sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort); | ||
522 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, | ||
523 | - FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200); | ||
524 | + FSL_IMX6UL_USB02_USBn_ADDR[i]); | ||
525 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, | ||
526 | qdev_get_gpio_in(DEVICE(&s->a7mpcore), | ||
527 | FSL_IMX6UL_USBn_IRQ[i])); | ||
528 | } | ||
529 | |||
530 | /* | ||
531 | - * USDHC | ||
532 | + * USDHCs | ||
533 | */ | ||
534 | for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { | ||
535 | static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = { | ||
536 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
537 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR); | ||
538 | |||
539 | /* | ||
540 | - * Watchdog | ||
541 | + * Watchdogs | ||
542 | */ | ||
543 | for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) { | ||
544 | static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = { | ||
545 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
546 | FSL_IMX6UL_WDOG2_ADDR, | ||
547 | FSL_IMX6UL_WDOG3_ADDR, | ||
548 | }; | ||
549 | + | ||
550 | static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = { | ||
551 | FSL_IMX6UL_WDOG1_IRQ, | ||
552 | FSL_IMX6UL_WDOG2_IRQ, | ||
553 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
554 | /* | ||
555 | * SDMA | ||
556 | */ | ||
557 | - create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000); | ||
558 | + create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, | ||
559 | + FSL_IMX6UL_SDMA_SIZE); | ||
560 | |||
561 | /* | ||
562 | - * SAI (Audio SSI (Synchronous Serial Interface)) | ||
563 | + * SAIs (Audio SSI (Synchronous Serial Interface)) | ||
564 | */ | ||
565 | - create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000); | ||
566 | - create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000); | ||
567 | - create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000); | ||
568 | + for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) { | ||
569 | + static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = { | ||
570 | + FSL_IMX6UL_SAI1_ADDR, | ||
571 | + FSL_IMX6UL_SAI2_ADDR, | ||
572 | + FSL_IMX6UL_SAI3_ADDR, | ||
573 | + }; | ||
574 | + | ||
575 | + snprintf(name, NAME_SIZE, "sai%d", i); | ||
576 | + create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i], | ||
577 | + FSL_IMX6UL_SAIn_SIZE); | ||
578 | + } | ||
579 | |||
580 | /* | ||
581 | - * PWM | ||
582 | + * PWMs | ||
583 | */ | ||
584 | - create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000); | ||
585 | - create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000); | ||
586 | - create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000); | ||
587 | - create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000); | ||
588 | + for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) { | ||
589 | + static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = { | ||
590 | + FSL_IMX6UL_PWM1_ADDR, | ||
591 | + FSL_IMX6UL_PWM2_ADDR, | ||
592 | + FSL_IMX6UL_PWM3_ADDR, | ||
593 | + FSL_IMX6UL_PWM4_ADDR, | ||
594 | + }; | ||
595 | + | ||
596 | + snprintf(name, NAME_SIZE, "pwm%d", i); | ||
597 | + create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i], | ||
598 | + FSL_IMX6UL_PWMn_SIZE); | ||
599 | + } | ||
600 | |||
601 | /* | ||
602 | * Audio ASRC (asynchronous sample rate converter) | ||
603 | */ | ||
604 | - create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000); | ||
605 | + create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, | ||
606 | + FSL_IMX6UL_ASRC_SIZE); | ||
607 | |||
608 | /* | ||
609 | - * CAN | ||
610 | + * CANs | ||
611 | */ | ||
612 | - create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000); | ||
613 | - create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000); | ||
614 | + for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) { | ||
615 | + static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = { | ||
616 | + FSL_IMX6UL_CAN1_ADDR, | ||
617 | + FSL_IMX6UL_CAN2_ADDR, | ||
618 | + }; | ||
619 | + | ||
620 | + snprintf(name, NAME_SIZE, "can%d", i); | ||
621 | + create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i], | ||
622 | + FSL_IMX6UL_CANn_SIZE); | ||
623 | + } | ||
624 | |||
625 | /* | ||
626 | * APHB_DMA | ||
627 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
628 | }; | ||
629 | |||
630 | snprintf(name, NAME_SIZE, "adc%d", i); | ||
631 | - create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000); | ||
632 | + create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], | ||
633 | + FSL_IMX6UL_ADCn_SIZE); | ||
634 | } | ||
635 | |||
636 | /* | ||
637 | * LCD | ||
638 | */ | ||
639 | - create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000); | ||
640 | + create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, | ||
641 | + FSL_IMX6UL_LCDIF_SIZE); | ||
642 | |||
643 | /* | ||
644 | * ROM memory | ||
645 | -- | ||
646 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Max Filippov <jcmvbkbc@gmail.com> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | With multiprocess extensions gdb uses 'vKill' packet instead of 'k' to | 3 | * Add TZASC as unimplemented device. |
4 | kill the inferior. Handle 'vKill' the same way 'k' was handled in the | 4 | - Allow bare metal application to access this (unimplemented) device |
5 | presence of single process. | 5 | * Add CSU as unimplemented device. |
6 | - Allow bare metal application to access this (unimplemented) device | ||
7 | * Add 4 missing PWM devices | ||
6 | 8 | ||
7 | Fixes: 7cf48f6752e5 ("gdbstub: add multiprocess support to | 9 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
8 | (f|s)ThreadInfo and ThreadExtraInfo") | 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | 11 | Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net | |
10 | Cc: Luc Michel <luc.michel@greensocs.com> | ||
11 | Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> | ||
12 | Reviewed-by: Luc Michel <luc.michel@greensocs.com> | ||
13 | Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> | ||
14 | Tested-by: KONRAD Frederic <frederic.konrad@adacore.com> | ||
15 | Message-id: 20190130192403.13754-1-jcmvbkbc@gmail.com | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 13 | --- |
18 | gdbstub.c | 4 ++++ | 14 | include/hw/arm/fsl-imx6ul.h | 2 +- |
19 | 1 file changed, 4 insertions(+) | 15 | hw/arm/fsl-imx6ul.c | 16 ++++++++++++++++ |
16 | 2 files changed, 17 insertions(+), 1 deletion(-) | ||
20 | 17 | ||
21 | diff --git a/gdbstub.c b/gdbstub.c | 18 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h |
22 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/gdbstub.c | 20 | --- a/include/hw/arm/fsl-imx6ul.h |
24 | +++ b/gdbstub.c | 21 | +++ b/include/hw/arm/fsl-imx6ul.h |
25 | @@ -XXX,XX +XXX,XX @@ static int gdb_handle_packet(GDBState *s, const char *line_buf) | 22 | @@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration { |
26 | 23 | FSL_IMX6UL_NUM_USBS = 2, | |
27 | put_packet(s, buf); | 24 | FSL_IMX6UL_NUM_SAIS = 3, |
28 | break; | 25 | FSL_IMX6UL_NUM_CANS = 2, |
29 | + } else if (strncmp(p, "Kill;", 5) == 0) { | 26 | - FSL_IMX6UL_NUM_PWMS = 4, |
30 | + /* Kill the target */ | 27 | + FSL_IMX6UL_NUM_PWMS = 8, |
31 | + error_report("QEMU: Terminated via GDBstub"); | 28 | }; |
32 | + exit(0); | 29 | |
33 | } else { | 30 | struct FslIMX6ULState { |
34 | goto unknown_command; | 31 | diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c |
35 | } | 32 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/hw/arm/fsl-imx6ul.c | ||
34 | +++ b/hw/arm/fsl-imx6ul.c | ||
35 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
36 | FSL_IMX6UL_PWM2_ADDR, | ||
37 | FSL_IMX6UL_PWM3_ADDR, | ||
38 | FSL_IMX6UL_PWM4_ADDR, | ||
39 | + FSL_IMX6UL_PWM5_ADDR, | ||
40 | + FSL_IMX6UL_PWM6_ADDR, | ||
41 | + FSL_IMX6UL_PWM7_ADDR, | ||
42 | + FSL_IMX6UL_PWM8_ADDR, | ||
43 | }; | ||
44 | |||
45 | snprintf(name, NAME_SIZE, "pwm%d", i); | ||
46 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) | ||
47 | create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, | ||
48 | FSL_IMX6UL_LCDIF_SIZE); | ||
49 | |||
50 | + /* | ||
51 | + * CSU | ||
52 | + */ | ||
53 | + create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR, | ||
54 | + FSL_IMX6UL_CSU_SIZE); | ||
55 | + | ||
56 | + /* | ||
57 | + * TZASC | ||
58 | + */ | ||
59 | + create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR, | ||
60 | + FSL_IMX6UL_TZASC_SIZE); | ||
61 | + | ||
62 | /* | ||
63 | * ROM memory | ||
64 | */ | ||
36 | -- | 65 | -- |
37 | 2.20.1 | 66 | 2.34.1 |
38 | 67 | ||
39 | 68 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Place this in its own field within ENV, as that will | 3 | * Add Addr and size definition for all i.MX7 devices in i.MX7 header file. |
4 | make it easier to reset from within TCG generated code. | 4 | * Use those newly defined named constants whenever possible. |
5 | * Standardize the way we init a familly of unimplemented devices | ||
6 | - SAI | ||
7 | - PWM | ||
8 | - CAN | ||
9 | * Add/rework few comments | ||
5 | 10 | ||
6 | With the change to pstate_read/write, exception entry | 11 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
7 | and return are automatically handled. | 12 | Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net |
8 | |||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20190128223118.5255-3-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 15 | --- |
14 | target/arm/cpu.h | 8 ++++++-- | 16 | include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++---------- |
15 | target/arm/translate-a64.c | 3 +++ | 17 | hw/arm/fsl-imx7.c | 130 ++++++++++----- |
16 | 2 files changed, 9 insertions(+), 2 deletions(-) | 18 | 2 files changed, 335 insertions(+), 125 deletions(-) |
17 | 19 | ||
18 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 20 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h |
19 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/cpu.h | 22 | --- a/include/hw/arm/fsl-imx7.h |
21 | +++ b/target/arm/cpu.h | 23 | +++ b/include/hw/arm/fsl-imx7.h |
22 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 24 | @@ -XXX,XX +XXX,XX @@ |
23 | * semantics as for AArch32, as described in the comments on each field) | 25 | #include "hw/misc/imx7_ccm.h" |
24 | * nRW (also known as M[4]) is kept, inverted, in env->aarch64 | 26 | #include "hw/misc/imx7_snvs.h" |
25 | * DAIF (exception masks) are kept in env->daif | 27 | #include "hw/misc/imx7_gpr.h" |
26 | + * BTYPE is kept in env->btype | 28 | -#include "hw/misc/imx6_src.h" |
27 | * all other bits are stored in their correct places in env->pstate | 29 | #include "hw/watchdog/wdt_imx2.h" |
28 | */ | 30 | #include "hw/gpio/imx_gpio.h" |
29 | uint32_t pstate; | 31 | #include "hw/char/imx_serial.h" |
30 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 32 | @@ -XXX,XX +XXX,XX @@ |
31 | uint32_t GE; /* cpsr[19:16] */ | 33 | #include "hw/usb/chipidea.h" |
32 | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */ | 34 | #include "cpu.h" |
33 | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ | 35 | #include "qom/object.h" |
34 | + uint32_t btype; /* BTI branch type. spsr[11:10]. */ | 36 | +#include "qemu/units.h" |
35 | uint64_t daif; /* exception masks, in the bits they are in PSTATE */ | 37 | |
36 | 38 | #define TYPE_FSL_IMX7 "fsl-imx7" | |
37 | uint64_t elr_el[4]; /* AArch64 exception link regs */ | 39 | OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7) |
38 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | 40 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration { |
39 | #define PSTATE_I (1U << 7) | 41 | FSL_IMX7_NUM_ECSPIS = 4, |
40 | #define PSTATE_A (1U << 8) | 42 | FSL_IMX7_NUM_USBS = 3, |
41 | #define PSTATE_D (1U << 9) | 43 | FSL_IMX7_NUM_ADCS = 2, |
42 | +#define PSTATE_BTYPE (3U << 10) | 44 | + FSL_IMX7_NUM_SAIS = 3, |
43 | #define PSTATE_IL (1U << 20) | 45 | + FSL_IMX7_NUM_CANS = 2, |
44 | #define PSTATE_SS (1U << 21) | 46 | + FSL_IMX7_NUM_PWMS = 4, |
45 | #define PSTATE_V (1U << 28) | 47 | }; |
46 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | 48 | |
47 | #define PSTATE_N (1U << 31) | 49 | struct FslIMX7State { |
48 | #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) | 50 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
49 | #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) | 51 | |
50 | -#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF) | 52 | enum FslIMX7MemoryMap { |
51 | +#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) | 53 | FSL_IMX7_MMDC_ADDR = 0x80000000, |
52 | /* Mode values for AArch64 */ | 54 | - FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL, |
53 | #define PSTATE_MODE_EL3h 13 | 55 | + FSL_IMX7_MMDC_SIZE = (2 * GiB), |
54 | #define PSTATE_MODE_EL3t 12 | 56 | |
55 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t pstate_read(CPUARMState *env) | 57 | - FSL_IMX7_GPIO1_ADDR = 0x30200000, |
56 | ZF = (env->ZF == 0); | 58 | - FSL_IMX7_GPIO2_ADDR = 0x30210000, |
57 | return (env->NF & 0x80000000) | (ZF << 30) | 59 | - FSL_IMX7_GPIO3_ADDR = 0x30220000, |
58 | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | 60 | - FSL_IMX7_GPIO4_ADDR = 0x30230000, |
59 | - | env->pstate | env->daif; | 61 | - FSL_IMX7_GPIO5_ADDR = 0x30240000, |
60 | + | env->pstate | env->daif | (env->btype << 10); | 62 | - FSL_IMX7_GPIO6_ADDR = 0x30250000, |
63 | - FSL_IMX7_GPIO7_ADDR = 0x30260000, | ||
64 | + FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000, | ||
65 | + FSL_IMX7_QSPI1_MEM_SIZE = (256 * MiB), | ||
66 | |||
67 | - FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, | ||
68 | + FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000, | ||
69 | + FSL_IMX7_PCIE1_MEM_SIZE = (256 * MiB), | ||
70 | |||
71 | - FSL_IMX7_WDOG1_ADDR = 0x30280000, | ||
72 | - FSL_IMX7_WDOG2_ADDR = 0x30290000, | ||
73 | - FSL_IMX7_WDOG3_ADDR = 0x302A0000, | ||
74 | - FSL_IMX7_WDOG4_ADDR = 0x302B0000, | ||
75 | + FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000, | ||
76 | + FSL_IMX7_QSPI1_RX_BUF_SIZE = (32 * MiB), | ||
77 | |||
78 | - FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, | ||
79 | + /* PCIe Peripherals */ | ||
80 | + FSL_IMX7_PCIE_REG_ADDR = 0x33800000, | ||
81 | |||
82 | - FSL_IMX7_GPT1_ADDR = 0x302D0000, | ||
83 | - FSL_IMX7_GPT2_ADDR = 0x302E0000, | ||
84 | - FSL_IMX7_GPT3_ADDR = 0x302F0000, | ||
85 | - FSL_IMX7_GPT4_ADDR = 0x30300000, | ||
86 | + /* MMAP Peripherals */ | ||
87 | + FSL_IMX7_DMA_APBH_ADDR = 0x33000000, | ||
88 | + FSL_IMX7_DMA_APBH_SIZE = 0x8000, | ||
89 | |||
90 | - FSL_IMX7_IOMUXC_ADDR = 0x30330000, | ||
91 | - FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, | ||
92 | - FSL_IMX7_IOMUXCn_SIZE = 0x1000, | ||
93 | + /* GPV configuration */ | ||
94 | + FSL_IMX7_GPV6_ADDR = 0x32600000, | ||
95 | + FSL_IMX7_GPV5_ADDR = 0x32500000, | ||
96 | + FSL_IMX7_GPV4_ADDR = 0x32400000, | ||
97 | + FSL_IMX7_GPV3_ADDR = 0x32300000, | ||
98 | + FSL_IMX7_GPV2_ADDR = 0x32200000, | ||
99 | + FSL_IMX7_GPV1_ADDR = 0x32100000, | ||
100 | + FSL_IMX7_GPV0_ADDR = 0x32000000, | ||
101 | + FSL_IMX7_GPVn_SIZE = (1 * MiB), | ||
102 | |||
103 | - FSL_IMX7_OCOTP_ADDR = 0x30350000, | ||
104 | - FSL_IMX7_OCOTP_SIZE = 0x10000, | ||
105 | + /* Arm Peripherals */ | ||
106 | + FSL_IMX7_A7MPCORE_ADDR = 0x31000000, | ||
107 | |||
108 | - FSL_IMX7_ANALOG_ADDR = 0x30360000, | ||
109 | - FSL_IMX7_SNVS_ADDR = 0x30370000, | ||
110 | - FSL_IMX7_CCM_ADDR = 0x30380000, | ||
111 | + /* AIPS-3 Begin */ | ||
112 | |||
113 | - FSL_IMX7_SRC_ADDR = 0x30390000, | ||
114 | - FSL_IMX7_SRC_SIZE = 0x1000, | ||
115 | + FSL_IMX7_ENET2_ADDR = 0x30BF0000, | ||
116 | + FSL_IMX7_ENET1_ADDR = 0x30BE0000, | ||
117 | |||
118 | - FSL_IMX7_ADC1_ADDR = 0x30610000, | ||
119 | - FSL_IMX7_ADC2_ADDR = 0x30620000, | ||
120 | - FSL_IMX7_ADCn_SIZE = 0x1000, | ||
121 | + FSL_IMX7_SDMA_ADDR = 0x30BD0000, | ||
122 | + FSL_IMX7_SDMA_SIZE = (4 * KiB), | ||
123 | |||
124 | - FSL_IMX7_PWM1_ADDR = 0x30660000, | ||
125 | - FSL_IMX7_PWM2_ADDR = 0x30670000, | ||
126 | - FSL_IMX7_PWM3_ADDR = 0x30680000, | ||
127 | - FSL_IMX7_PWM4_ADDR = 0x30690000, | ||
128 | - FSL_IMX7_PWMn_SIZE = 0x10000, | ||
129 | + FSL_IMX7_EIM_ADDR = 0x30BC0000, | ||
130 | + FSL_IMX7_EIM_SIZE = (4 * KiB), | ||
131 | |||
132 | - FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, | ||
133 | - FSL_IMX7_PCIE_PHY_SIZE = 0x10000, | ||
134 | + FSL_IMX7_QSPI_ADDR = 0x30BB0000, | ||
135 | + FSL_IMX7_QSPI_SIZE = 0x8000, | ||
136 | |||
137 | - FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
138 | + FSL_IMX7_SIM2_ADDR = 0x30BA0000, | ||
139 | + FSL_IMX7_SIM1_ADDR = 0x30B90000, | ||
140 | + FSL_IMX7_SIMn_SIZE = (4 * KiB), | ||
141 | + | ||
142 | + FSL_IMX7_USDHC3_ADDR = 0x30B60000, | ||
143 | + FSL_IMX7_USDHC2_ADDR = 0x30B50000, | ||
144 | + FSL_IMX7_USDHC1_ADDR = 0x30B40000, | ||
145 | + | ||
146 | + FSL_IMX7_USB3_ADDR = 0x30B30000, | ||
147 | + FSL_IMX7_USBMISC3_ADDR = 0x30B30200, | ||
148 | + FSL_IMX7_USB2_ADDR = 0x30B20000, | ||
149 | + FSL_IMX7_USBMISC2_ADDR = 0x30B20200, | ||
150 | + FSL_IMX7_USB1_ADDR = 0x30B10000, | ||
151 | + FSL_IMX7_USBMISC1_ADDR = 0x30B10200, | ||
152 | + FSL_IMX7_USBMISCn_SIZE = 0x200, | ||
153 | + | ||
154 | + FSL_IMX7_USB_PL301_ADDR = 0x30AD0000, | ||
155 | + FSL_IMX7_USB_PL301_SIZE = (64 * KiB), | ||
156 | + | ||
157 | + FSL_IMX7_SEMAPHORE_HS_ADDR = 0x30AC0000, | ||
158 | + FSL_IMX7_SEMAPHORE_HS_SIZE = (64 * KiB), | ||
159 | + | ||
160 | + FSL_IMX7_MUB_ADDR = 0x30AB0000, | ||
161 | + FSL_IMX7_MUA_ADDR = 0x30AA0000, | ||
162 | + FSL_IMX7_MUn_SIZE = (KiB), | ||
163 | + | ||
164 | + FSL_IMX7_UART7_ADDR = 0x30A90000, | ||
165 | + FSL_IMX7_UART6_ADDR = 0x30A80000, | ||
166 | + FSL_IMX7_UART5_ADDR = 0x30A70000, | ||
167 | + FSL_IMX7_UART4_ADDR = 0x30A60000, | ||
168 | + | ||
169 | + FSL_IMX7_I2C4_ADDR = 0x30A50000, | ||
170 | + FSL_IMX7_I2C3_ADDR = 0x30A40000, | ||
171 | + FSL_IMX7_I2C2_ADDR = 0x30A30000, | ||
172 | + FSL_IMX7_I2C1_ADDR = 0x30A20000, | ||
173 | + | ||
174 | + FSL_IMX7_CAN2_ADDR = 0x30A10000, | ||
175 | + FSL_IMX7_CAN1_ADDR = 0x30A00000, | ||
176 | + FSL_IMX7_CANn_SIZE = (4 * KiB), | ||
177 | + | ||
178 | + FSL_IMX7_AIPS3_CONF_ADDR = 0x309F0000, | ||
179 | + FSL_IMX7_AIPS3_CONF_SIZE = (64 * KiB), | ||
180 | |||
181 | FSL_IMX7_CAAM_ADDR = 0x30900000, | ||
182 | - FSL_IMX7_CAAM_SIZE = 0x40000, | ||
183 | + FSL_IMX7_CAAM_SIZE = (256 * KiB), | ||
184 | |||
185 | - FSL_IMX7_CAN1_ADDR = 0x30A00000, | ||
186 | - FSL_IMX7_CAN2_ADDR = 0x30A10000, | ||
187 | - FSL_IMX7_CANn_SIZE = 0x10000, | ||
188 | + FSL_IMX7_SPBA_ADDR = 0x308F0000, | ||
189 | + FSL_IMX7_SPBA_SIZE = (4 * KiB), | ||
190 | |||
191 | - FSL_IMX7_I2C1_ADDR = 0x30A20000, | ||
192 | - FSL_IMX7_I2C2_ADDR = 0x30A30000, | ||
193 | - FSL_IMX7_I2C3_ADDR = 0x30A40000, | ||
194 | - FSL_IMX7_I2C4_ADDR = 0x30A50000, | ||
195 | + FSL_IMX7_SAI3_ADDR = 0x308C0000, | ||
196 | + FSL_IMX7_SAI2_ADDR = 0x308B0000, | ||
197 | + FSL_IMX7_SAI1_ADDR = 0x308A0000, | ||
198 | + FSL_IMX7_SAIn_SIZE = (4 * KiB), | ||
199 | |||
200 | - FSL_IMX7_ECSPI1_ADDR = 0x30820000, | ||
201 | - FSL_IMX7_ECSPI2_ADDR = 0x30830000, | ||
202 | - FSL_IMX7_ECSPI3_ADDR = 0x30840000, | ||
203 | - FSL_IMX7_ECSPI4_ADDR = 0x30630000, | ||
204 | - | ||
205 | - FSL_IMX7_LCDIF_ADDR = 0x30730000, | ||
206 | - FSL_IMX7_LCDIF_SIZE = 0x1000, | ||
207 | - | ||
208 | - FSL_IMX7_UART1_ADDR = 0x30860000, | ||
209 | + FSL_IMX7_UART3_ADDR = 0x30880000, | ||
210 | /* | ||
211 | * Some versions of the reference manual claim that UART2 is @ | ||
212 | * 0x30870000, but experiments with HW + DT files in upstream | ||
213 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap { | ||
214 | * actually located @ 0x30890000 | ||
215 | */ | ||
216 | FSL_IMX7_UART2_ADDR = 0x30890000, | ||
217 | - FSL_IMX7_UART3_ADDR = 0x30880000, | ||
218 | - FSL_IMX7_UART4_ADDR = 0x30A60000, | ||
219 | - FSL_IMX7_UART5_ADDR = 0x30A70000, | ||
220 | - FSL_IMX7_UART6_ADDR = 0x30A80000, | ||
221 | - FSL_IMX7_UART7_ADDR = 0x30A90000, | ||
222 | + FSL_IMX7_UART1_ADDR = 0x30860000, | ||
223 | |||
224 | - FSL_IMX7_SAI1_ADDR = 0x308A0000, | ||
225 | - FSL_IMX7_SAI2_ADDR = 0x308B0000, | ||
226 | - FSL_IMX7_SAI3_ADDR = 0x308C0000, | ||
227 | - FSL_IMX7_SAIn_SIZE = 0x10000, | ||
228 | + FSL_IMX7_ECSPI3_ADDR = 0x30840000, | ||
229 | + FSL_IMX7_ECSPI2_ADDR = 0x30830000, | ||
230 | + FSL_IMX7_ECSPI1_ADDR = 0x30820000, | ||
231 | + FSL_IMX7_ECSPIn_SIZE = (4 * KiB), | ||
232 | |||
233 | - FSL_IMX7_ENET1_ADDR = 0x30BE0000, | ||
234 | - FSL_IMX7_ENET2_ADDR = 0x30BF0000, | ||
235 | + /* AIPS-3 End */ | ||
236 | |||
237 | - FSL_IMX7_USB1_ADDR = 0x30B10000, | ||
238 | - FSL_IMX7_USBMISC1_ADDR = 0x30B10200, | ||
239 | - FSL_IMX7_USB2_ADDR = 0x30B20000, | ||
240 | - FSL_IMX7_USBMISC2_ADDR = 0x30B20200, | ||
241 | - FSL_IMX7_USB3_ADDR = 0x30B30000, | ||
242 | - FSL_IMX7_USBMISC3_ADDR = 0x30B30200, | ||
243 | - FSL_IMX7_USBMISCn_SIZE = 0x200, | ||
244 | + /* AIPS-2 Begin */ | ||
245 | |||
246 | - FSL_IMX7_USDHC1_ADDR = 0x30B40000, | ||
247 | - FSL_IMX7_USDHC2_ADDR = 0x30B50000, | ||
248 | - FSL_IMX7_USDHC3_ADDR = 0x30B60000, | ||
249 | + FSL_IMX7_AXI_DEBUG_MON_ADDR = 0x307E0000, | ||
250 | + FSL_IMX7_AXI_DEBUG_MON_SIZE = (64 * KiB), | ||
251 | |||
252 | - FSL_IMX7_SDMA_ADDR = 0x30BD0000, | ||
253 | - FSL_IMX7_SDMA_SIZE = 0x1000, | ||
254 | + FSL_IMX7_PERFMON2_ADDR = 0x307D0000, | ||
255 | + FSL_IMX7_PERFMON1_ADDR = 0x307C0000, | ||
256 | + FSL_IMX7_PERFMONn_SIZE = (64 * KiB), | ||
257 | + | ||
258 | + FSL_IMX7_DDRC_ADDR = 0x307A0000, | ||
259 | + FSL_IMX7_DDRC_SIZE = (4 * KiB), | ||
260 | + | ||
261 | + FSL_IMX7_DDRC_PHY_ADDR = 0x30790000, | ||
262 | + FSL_IMX7_DDRC_PHY_SIZE = (4 * KiB), | ||
263 | + | ||
264 | + FSL_IMX7_TZASC_ADDR = 0x30780000, | ||
265 | + FSL_IMX7_TZASC_SIZE = (64 * KiB), | ||
266 | + | ||
267 | + FSL_IMX7_MIPI_DSI_ADDR = 0x30760000, | ||
268 | + FSL_IMX7_MIPI_DSI_SIZE = (4 * KiB), | ||
269 | + | ||
270 | + FSL_IMX7_MIPI_CSI_ADDR = 0x30750000, | ||
271 | + FSL_IMX7_MIPI_CSI_SIZE = 0x4000, | ||
272 | + | ||
273 | + FSL_IMX7_LCDIF_ADDR = 0x30730000, | ||
274 | + FSL_IMX7_LCDIF_SIZE = 0x8000, | ||
275 | + | ||
276 | + FSL_IMX7_CSI_ADDR = 0x30710000, | ||
277 | + FSL_IMX7_CSI_SIZE = (4 * KiB), | ||
278 | + | ||
279 | + FSL_IMX7_PXP_ADDR = 0x30700000, | ||
280 | + FSL_IMX7_PXP_SIZE = 0x4000, | ||
281 | + | ||
282 | + FSL_IMX7_EPDC_ADDR = 0x306F0000, | ||
283 | + FSL_IMX7_EPDC_SIZE = (4 * KiB), | ||
284 | + | ||
285 | + FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000, | ||
286 | + FSL_IMX7_PCIE_PHY_SIZE = (4 * KiB), | ||
287 | + | ||
288 | + FSL_IMX7_SYSCNT_CTRL_ADDR = 0x306C0000, | ||
289 | + FSL_IMX7_SYSCNT_CMP_ADDR = 0x306B0000, | ||
290 | + FSL_IMX7_SYSCNT_RD_ADDR = 0x306A0000, | ||
291 | + | ||
292 | + FSL_IMX7_PWM4_ADDR = 0x30690000, | ||
293 | + FSL_IMX7_PWM3_ADDR = 0x30680000, | ||
294 | + FSL_IMX7_PWM2_ADDR = 0x30670000, | ||
295 | + FSL_IMX7_PWM1_ADDR = 0x30660000, | ||
296 | + FSL_IMX7_PWMn_SIZE = (4 * KiB), | ||
297 | + | ||
298 | + FSL_IMX7_FlEXTIMER2_ADDR = 0x30650000, | ||
299 | + FSL_IMX7_FlEXTIMER1_ADDR = 0x30640000, | ||
300 | + FSL_IMX7_FLEXTIMERn_SIZE = (4 * KiB), | ||
301 | + | ||
302 | + FSL_IMX7_ECSPI4_ADDR = 0x30630000, | ||
303 | + | ||
304 | + FSL_IMX7_ADC2_ADDR = 0x30620000, | ||
305 | + FSL_IMX7_ADC1_ADDR = 0x30610000, | ||
306 | + FSL_IMX7_ADCn_SIZE = (4 * KiB), | ||
307 | + | ||
308 | + FSL_IMX7_AIPS2_CONF_ADDR = 0x305F0000, | ||
309 | + FSL_IMX7_AIPS2_CONF_SIZE = (64 * KiB), | ||
310 | + | ||
311 | + /* AIPS-2 End */ | ||
312 | + | ||
313 | + /* AIPS-1 Begin */ | ||
314 | + | ||
315 | + FSL_IMX7_CSU_ADDR = 0x303E0000, | ||
316 | + FSL_IMX7_CSU_SIZE = (64 * KiB), | ||
317 | + | ||
318 | + FSL_IMX7_RDC_ADDR = 0x303D0000, | ||
319 | + FSL_IMX7_RDC_SIZE = (4 * KiB), | ||
320 | + | ||
321 | + FSL_IMX7_SEMAPHORE2_ADDR = 0x303C0000, | ||
322 | + FSL_IMX7_SEMAPHORE1_ADDR = 0x303B0000, | ||
323 | + FSL_IMX7_SEMAPHOREn_SIZE = (4 * KiB), | ||
324 | + | ||
325 | + FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
326 | + | ||
327 | + FSL_IMX7_SRC_ADDR = 0x30390000, | ||
328 | + FSL_IMX7_SRC_SIZE = (4 * KiB), | ||
329 | + | ||
330 | + FSL_IMX7_CCM_ADDR = 0x30380000, | ||
331 | + | ||
332 | + FSL_IMX7_SNVS_HP_ADDR = 0x30370000, | ||
333 | + | ||
334 | + FSL_IMX7_ANALOG_ADDR = 0x30360000, | ||
335 | + | ||
336 | + FSL_IMX7_OCOTP_ADDR = 0x30350000, | ||
337 | + FSL_IMX7_OCOTP_SIZE = 0x10000, | ||
338 | + | ||
339 | + FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000, | ||
340 | + FSL_IMX7_IOMUXC_GPR_SIZE = (4 * KiB), | ||
341 | + | ||
342 | + FSL_IMX7_IOMUXC_ADDR = 0x30330000, | ||
343 | + FSL_IMX7_IOMUXC_SIZE = (4 * KiB), | ||
344 | + | ||
345 | + FSL_IMX7_KPP_ADDR = 0x30320000, | ||
346 | + FSL_IMX7_KPP_SIZE = (4 * KiB), | ||
347 | + | ||
348 | + FSL_IMX7_ROMCP_ADDR = 0x30310000, | ||
349 | + FSL_IMX7_ROMCP_SIZE = (4 * KiB), | ||
350 | + | ||
351 | + FSL_IMX7_GPT4_ADDR = 0x30300000, | ||
352 | + FSL_IMX7_GPT3_ADDR = 0x302F0000, | ||
353 | + FSL_IMX7_GPT2_ADDR = 0x302E0000, | ||
354 | + FSL_IMX7_GPT1_ADDR = 0x302D0000, | ||
355 | + | ||
356 | + FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000, | ||
357 | + FSL_IMX7_IOMUXC_LPSR_SIZE = (4 * KiB), | ||
358 | + | ||
359 | + FSL_IMX7_WDOG4_ADDR = 0x302B0000, | ||
360 | + FSL_IMX7_WDOG3_ADDR = 0x302A0000, | ||
361 | + FSL_IMX7_WDOG2_ADDR = 0x30290000, | ||
362 | + FSL_IMX7_WDOG1_ADDR = 0x30280000, | ||
363 | + | ||
364 | + FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000, | ||
365 | + | ||
366 | + FSL_IMX7_GPIO7_ADDR = 0x30260000, | ||
367 | + FSL_IMX7_GPIO6_ADDR = 0x30250000, | ||
368 | + FSL_IMX7_GPIO5_ADDR = 0x30240000, | ||
369 | + FSL_IMX7_GPIO4_ADDR = 0x30230000, | ||
370 | + FSL_IMX7_GPIO3_ADDR = 0x30220000, | ||
371 | + FSL_IMX7_GPIO2_ADDR = 0x30210000, | ||
372 | + FSL_IMX7_GPIO1_ADDR = 0x30200000, | ||
373 | + | ||
374 | + FSL_IMX7_AIPS1_CONF_ADDR = 0x301F0000, | ||
375 | + FSL_IMX7_AIPS1_CONF_SIZE = (64 * KiB), | ||
376 | |||
377 | - FSL_IMX7_A7MPCORE_ADDR = 0x31000000, | ||
378 | FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000, | ||
379 | + FSL_IMX7_A7MPCORE_DAP_SIZE = (1 * MiB), | ||
380 | |||
381 | - FSL_IMX7_PCIE_REG_ADDR = 0x33800000, | ||
382 | - FSL_IMX7_PCIE_REG_SIZE = 16 * 1024, | ||
383 | + /* AIPS-1 End */ | ||
384 | |||
385 | - FSL_IMX7_GPR_ADDR = 0x30340000, | ||
386 | + FSL_IMX7_EIM_CS0_ADDR = 0x28000000, | ||
387 | + FSL_IMX7_EIM_CS0_SIZE = (128 * MiB), | ||
388 | |||
389 | - FSL_IMX7_DMA_APBH_ADDR = 0x33000000, | ||
390 | - FSL_IMX7_DMA_APBH_SIZE = 0x2000, | ||
391 | + FSL_IMX7_OCRAM_PXP_ADDR = 0x00940000, | ||
392 | + FSL_IMX7_OCRAM_PXP_SIZE = (32 * KiB), | ||
393 | + | ||
394 | + FSL_IMX7_OCRAM_EPDC_ADDR = 0x00920000, | ||
395 | + FSL_IMX7_OCRAM_EPDC_SIZE = (128 * KiB), | ||
396 | + | ||
397 | + FSL_IMX7_OCRAM_MEM_ADDR = 0x00900000, | ||
398 | + FSL_IMX7_OCRAM_MEM_SIZE = (128 * KiB), | ||
399 | + | ||
400 | + FSL_IMX7_TCMU_ADDR = 0x00800000, | ||
401 | + FSL_IMX7_TCMU_SIZE = (32 * KiB), | ||
402 | + | ||
403 | + FSL_IMX7_TCML_ADDR = 0x007F8000, | ||
404 | + FSL_IMX7_TCML_SIZE = (32 * KiB), | ||
405 | + | ||
406 | + FSL_IMX7_OCRAM_S_ADDR = 0x00180000, | ||
407 | + FSL_IMX7_OCRAM_S_SIZE = (32 * KiB), | ||
408 | + | ||
409 | + FSL_IMX7_CAAM_MEM_ADDR = 0x00100000, | ||
410 | + FSL_IMX7_CAAM_MEM_SIZE = (32 * KiB), | ||
411 | + | ||
412 | + FSL_IMX7_ROM_ADDR = 0x00000000, | ||
413 | + FSL_IMX7_ROM_SIZE = (96 * KiB), | ||
414 | }; | ||
415 | |||
416 | enum FslIMX7IRQs { | ||
417 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c | ||
418 | index XXXXXXX..XXXXXXX 100644 | ||
419 | --- a/hw/arm/fsl-imx7.c | ||
420 | +++ b/hw/arm/fsl-imx7.c | ||
421 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
422 | char name[NAME_SIZE]; | ||
423 | int i; | ||
424 | |||
425 | + /* | ||
426 | + * CPUs | ||
427 | + */ | ||
428 | for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) { | ||
429 | snprintf(name, NAME_SIZE, "cpu%d", i); | ||
430 | object_initialize_child(obj, name, &s->cpu[i], | ||
431 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
432 | TYPE_A15MPCORE_PRIV); | ||
433 | |||
434 | /* | ||
435 | - * GPIOs 1 to 7 | ||
436 | + * GPIOs | ||
437 | */ | ||
438 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { | ||
439 | snprintf(name, NAME_SIZE, "gpio%d", i); | ||
440 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
441 | } | ||
442 | |||
443 | /* | ||
444 | - * GPT1, 2, 3, 4 | ||
445 | + * GPTs | ||
446 | */ | ||
447 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { | ||
448 | snprintf(name, NAME_SIZE, "gpt%d", i); | ||
449 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
450 | */ | ||
451 | object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); | ||
452 | |||
453 | + /* | ||
454 | + * ECSPIs | ||
455 | + */ | ||
456 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { | ||
457 | snprintf(name, NAME_SIZE, "spi%d", i + 1); | ||
458 | object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); | ||
459 | } | ||
460 | |||
461 | - | ||
462 | + /* | ||
463 | + * I2Cs | ||
464 | + */ | ||
465 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { | ||
466 | snprintf(name, NAME_SIZE, "i2c%d", i + 1); | ||
467 | object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C); | ||
468 | } | ||
469 | |||
470 | /* | ||
471 | - * UART | ||
472 | + * UARTs | ||
473 | */ | ||
474 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { | ||
475 | snprintf(name, NAME_SIZE, "uart%d", i); | ||
476 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
477 | } | ||
478 | |||
479 | /* | ||
480 | - * Ethernet | ||
481 | + * Ethernets | ||
482 | */ | ||
483 | for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) { | ||
484 | snprintf(name, NAME_SIZE, "eth%d", i); | ||
485 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
486 | } | ||
487 | |||
488 | /* | ||
489 | - * SDHCI | ||
490 | + * SDHCIs | ||
491 | */ | ||
492 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { | ||
493 | snprintf(name, NAME_SIZE, "usdhc%d", i); | ||
494 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
495 | object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); | ||
496 | |||
497 | /* | ||
498 | - * Watchdog | ||
499 | + * Watchdogs | ||
500 | */ | ||
501 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { | ||
502 | snprintf(name, NAME_SIZE, "wdt%d", i); | ||
503 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
504 | */ | ||
505 | object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR); | ||
506 | |||
507 | + /* | ||
508 | + * PCIE | ||
509 | + */ | ||
510 | object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); | ||
511 | |||
512 | + /* | ||
513 | + * USBs | ||
514 | + */ | ||
515 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { | ||
516 | snprintf(name, NAME_SIZE, "usb%d", i); | ||
517 | object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA); | ||
518 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
519 | return; | ||
520 | } | ||
521 | |||
522 | + /* | ||
523 | + * CPUs | ||
524 | + */ | ||
525 | for (i = 0; i < smp_cpus; i++) { | ||
526 | o = OBJECT(&s->cpu[i]); | ||
527 | |||
528 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
529 | * A7MPCORE DAP | ||
530 | */ | ||
531 | create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR, | ||
532 | - 0x100000); | ||
533 | + FSL_IMX7_A7MPCORE_DAP_SIZE); | ||
534 | |||
535 | /* | ||
536 | - * GPT1, 2, 3, 4 | ||
537 | + * GPTs | ||
538 | */ | ||
539 | for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) { | ||
540 | static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = { | ||
541 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
542 | FSL_IMX7_GPTn_IRQ[i])); | ||
543 | } | ||
544 | |||
545 | + /* | ||
546 | + * GPIOs | ||
547 | + */ | ||
548 | for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) { | ||
549 | static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = { | ||
550 | FSL_IMX7_GPIO1_ADDR, | ||
551 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
552 | /* | ||
553 | * IOMUXC and IOMUXC_LPSR | ||
554 | */ | ||
555 | - for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) { | ||
556 | - static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = { | ||
557 | - FSL_IMX7_IOMUXC_ADDR, | ||
558 | - FSL_IMX7_IOMUXC_LPSR_ADDR, | ||
559 | - }; | ||
560 | - | ||
561 | - snprintf(name, NAME_SIZE, "iomuxc%d", i); | ||
562 | - create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i], | ||
563 | - FSL_IMX7_IOMUXCn_SIZE); | ||
564 | - } | ||
565 | + create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR, | ||
566 | + FSL_IMX7_IOMUXC_SIZE); | ||
567 | + create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR, | ||
568 | + FSL_IMX7_IOMUXC_LPSR_SIZE); | ||
569 | |||
570 | /* | ||
571 | * CCM | ||
572 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
573 | sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort); | ||
574 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR); | ||
575 | |||
576 | - /* Initialize all ECSPI */ | ||
577 | + /* | ||
578 | + * ECSPIs | ||
579 | + */ | ||
580 | for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) { | ||
581 | static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = { | ||
582 | FSL_IMX7_ECSPI1_ADDR, | ||
583 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
584 | FSL_IMX7_SPIn_IRQ[i])); | ||
585 | } | ||
586 | |||
587 | + /* | ||
588 | + * I2Cs | ||
589 | + */ | ||
590 | for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) { | ||
591 | static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = { | ||
592 | FSL_IMX7_I2C1_ADDR, | ||
593 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
594 | } | ||
595 | |||
596 | /* | ||
597 | - * UART | ||
598 | + * UARTs | ||
599 | */ | ||
600 | for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) { | ||
601 | static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = { | ||
602 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
603 | } | ||
604 | |||
605 | /* | ||
606 | - * Ethernet | ||
607 | + * Ethernets | ||
608 | * | ||
609 | * We must use two loops since phy_connected affects the other interface | ||
610 | * and we have to set all properties before calling sysbus_realize(). | ||
611 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
612 | } | ||
613 | |||
614 | /* | ||
615 | - * USDHC | ||
616 | + * USDHCs | ||
617 | */ | ||
618 | for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { | ||
619 | static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = { | ||
620 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
621 | * SNVS | ||
622 | */ | ||
623 | sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort); | ||
624 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR); | ||
625 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR); | ||
626 | |||
627 | /* | ||
628 | * SRC | ||
629 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
630 | create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); | ||
631 | |||
632 | /* | ||
633 | - * Watchdog | ||
634 | + * Watchdogs | ||
635 | */ | ||
636 | for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) { | ||
637 | static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = { | ||
638 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
639 | create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE); | ||
640 | |||
641 | /* | ||
642 | - * PWM | ||
643 | + * PWMs | ||
644 | */ | ||
645 | - create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE); | ||
646 | - create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE); | ||
647 | - create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE); | ||
648 | - create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE); | ||
649 | + for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) { | ||
650 | + static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = { | ||
651 | + FSL_IMX7_PWM1_ADDR, | ||
652 | + FSL_IMX7_PWM2_ADDR, | ||
653 | + FSL_IMX7_PWM3_ADDR, | ||
654 | + FSL_IMX7_PWM4_ADDR, | ||
655 | + }; | ||
656 | + | ||
657 | + snprintf(name, NAME_SIZE, "pwm%d", i); | ||
658 | + create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i], | ||
659 | + FSL_IMX7_PWMn_SIZE); | ||
660 | + } | ||
661 | |||
662 | /* | ||
663 | - * CAN | ||
664 | + * CANs | ||
665 | */ | ||
666 | - create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE); | ||
667 | - create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE); | ||
668 | + for (i = 0; i < FSL_IMX7_NUM_CANS; i++) { | ||
669 | + static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = { | ||
670 | + FSL_IMX7_CAN1_ADDR, | ||
671 | + FSL_IMX7_CAN2_ADDR, | ||
672 | + }; | ||
673 | + | ||
674 | + snprintf(name, NAME_SIZE, "can%d", i); | ||
675 | + create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i], | ||
676 | + FSL_IMX7_CANn_SIZE); | ||
677 | + } | ||
678 | |||
679 | /* | ||
680 | - * SAI (Audio SSI (Synchronous Serial Interface)) | ||
681 | + * SAIs (Audio SSI (Synchronous Serial Interface)) | ||
682 | */ | ||
683 | - create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE); | ||
684 | - create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE); | ||
685 | - create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE); | ||
686 | + for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) { | ||
687 | + static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = { | ||
688 | + FSL_IMX7_SAI1_ADDR, | ||
689 | + FSL_IMX7_SAI2_ADDR, | ||
690 | + FSL_IMX7_SAI3_ADDR, | ||
691 | + }; | ||
692 | + | ||
693 | + snprintf(name, NAME_SIZE, "sai%d", i); | ||
694 | + create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i], | ||
695 | + FSL_IMX7_SAIn_SIZE); | ||
696 | + } | ||
697 | |||
698 | /* | ||
699 | * OCOTP | ||
700 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
701 | create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR, | ||
702 | FSL_IMX7_OCOTP_SIZE); | ||
703 | |||
704 | + /* | ||
705 | + * GPR | ||
706 | + */ | ||
707 | sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort); | ||
708 | - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR); | ||
709 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR); | ||
710 | |||
711 | + /* | ||
712 | + * PCIE | ||
713 | + */ | ||
714 | sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); | ||
715 | sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR); | ||
716 | |||
717 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
718 | irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ); | ||
719 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); | ||
720 | |||
721 | - | ||
722 | + /* | ||
723 | + * USBs | ||
724 | + */ | ||
725 | for (i = 0; i < FSL_IMX7_NUM_USBS; i++) { | ||
726 | static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = { | ||
727 | FSL_IMX7_USBMISC1_ADDR, | ||
728 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
729 | */ | ||
730 | create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, | ||
731 | FSL_IMX7_PCIE_PHY_SIZE); | ||
732 | + | ||
61 | } | 733 | } |
62 | 734 | ||
63 | static inline void pstate_write(CPUARMState *env, uint32_t val) | 735 | static Property fsl_imx7_properties[] = { |
64 | @@ -XXX,XX +XXX,XX @@ static inline void pstate_write(CPUARMState *env, uint32_t val) | ||
65 | env->CF = (val >> 29) & 1; | ||
66 | env->VF = (val << 3) & 0x80000000; | ||
67 | env->daif = val & PSTATE_DAIF; | ||
68 | + env->btype = (val >> 10) & 3; | ||
69 | env->pstate = val & ~CACHED_PSTATE_BITS; | ||
70 | } | ||
71 | |||
72 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
73 | index XXXXXXX..XXXXXXX 100644 | ||
74 | --- a/target/arm/translate-a64.c | ||
75 | +++ b/target/arm/translate-a64.c | ||
76 | @@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | ||
77 | el, | ||
78 | psr & PSTATE_SP ? 'h' : 't'); | ||
79 | |||
80 | + if (cpu_isar_feature(aa64_bti, cpu)) { | ||
81 | + cpu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10); | ||
82 | + } | ||
83 | if (!(flags & CPU_DUMP_FPU)) { | ||
84 | cpu_fprintf(f, "\n"); | ||
85 | return; | ||
86 | -- | 736 | -- |
87 | 2.20.1 | 737 | 2.34.1 |
88 | |||
89 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | The branch target exception for guarded pages has high priority, | 3 | * Add TZASC as unimplemented device. |
4 | and only 8 instructions are valid for that case. Perform this | 4 | - Allow bare metal application to access this (unimplemented) device |
5 | check before doing any other decode. | 5 | * Add CSU as unimplemented device. |
6 | - Allow bare metal application to access this (unimplemented) device | ||
7 | * Add various memory segments | ||
8 | - OCRAM | ||
9 | - OCRAM EPDC | ||
10 | - OCRAM PXP | ||
11 | - OCRAM S | ||
12 | - ROM | ||
13 | - CAAM | ||
6 | 14 | ||
7 | Clear BTYPE after all insns that neither set BTYPE nor exit via | 15 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> |
8 | exception (DISAS_NORETURN). | 16 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
9 | 17 | Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net | |
10 | Not yet handled are insns that exit via DISAS_NORETURN for some | ||
11 | other reason, like direct branches. | ||
12 | |||
13 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
15 | Message-id: 20190128223118.5255-7-richard.henderson@linaro.org | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 19 | --- |
18 | target/arm/internals.h | 6 ++ | 20 | include/hw/arm/fsl-imx7.h | 7 +++++ |
19 | target/arm/translate.h | 9 ++- | 21 | hw/arm/fsl-imx7.c | 63 +++++++++++++++++++++++++++++++++++++++ |
20 | target/arm/translate-a64.c | 139 +++++++++++++++++++++++++++++++++++++ | 22 | 2 files changed, 70 insertions(+) |
21 | 3 files changed, 152 insertions(+), 2 deletions(-) | ||
22 | 23 | ||
23 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 24 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h |
24 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
25 | --- a/target/arm/internals.h | 26 | --- a/include/hw/arm/fsl-imx7.h |
26 | +++ b/target/arm/internals.h | 27 | +++ b/include/hw/arm/fsl-imx7.h |
27 | @@ -XXX,XX +XXX,XX @@ enum arm_exception_class { | 28 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
28 | EC_FPIDTRAP = 0x08, | 29 | IMX7GPRState gpr; |
29 | EC_PACTRAP = 0x09, | 30 | ChipideaState usb[FSL_IMX7_NUM_USBS]; |
30 | EC_CP14RRTTRAP = 0x0c, | 31 | DesignwarePCIEHost pcie; |
31 | + EC_BTITRAP = 0x0d, | 32 | + MemoryRegion rom; |
32 | EC_ILLEGALSTATE = 0x0e, | 33 | + MemoryRegion caam; |
33 | EC_AA32_SVC = 0x11, | 34 | + MemoryRegion ocram; |
34 | EC_AA32_HVC = 0x12, | 35 | + MemoryRegion ocram_epdc; |
35 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_pactrap(void) | 36 | + MemoryRegion ocram_pxp; |
36 | return EC_PACTRAP << ARM_EL_EC_SHIFT; | 37 | + MemoryRegion ocram_s; |
37 | } | ||
38 | |||
39 | +static inline uint32_t syn_btitrap(int btype) | ||
40 | +{ | ||
41 | + return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype; | ||
42 | +} | ||
43 | + | 38 | + |
44 | static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc) | 39 | uint32_t phy_num[FSL_IMX7_NUM_ETHS]; |
45 | { | 40 | bool phy_connected[FSL_IMX7_NUM_ETHS]; |
46 | return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) | 41 | }; |
47 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 42 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c |
48 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
49 | --- a/target/arm/translate.h | 44 | --- a/hw/arm/fsl-imx7.c |
50 | +++ b/target/arm/translate.h | 45 | +++ b/hw/arm/fsl-imx7.c |
51 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 46 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) |
52 | bool pauth_active; | 47 | create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR, |
53 | /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ | 48 | FSL_IMX7_PCIE_PHY_SIZE); |
54 | bool bt; | 49 | |
55 | - /* A copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. */ | ||
56 | - uint8_t btype; | ||
57 | + /* | 50 | + /* |
58 | + * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. | 51 | + * CSU |
59 | + * < 0, set by the current instruction. | ||
60 | + */ | 52 | + */ |
61 | + int8_t btype; | 53 | + create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR, |
62 | + /* True if this page is guarded. */ | 54 | + FSL_IMX7_CSU_SIZE); |
63 | + bool guarded_page; | ||
64 | /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ | ||
65 | int c15_cpar; | ||
66 | /* TCG op of the current insn_start. */ | ||
67 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/target/arm/translate-a64.c | ||
70 | +++ b/target/arm/translate-a64.c | ||
71 | @@ -XXX,XX +XXX,XX @@ static inline int get_a64_user_mem_index(DisasContext *s) | ||
72 | return arm_to_core_mmu_idx(useridx); | ||
73 | } | ||
74 | |||
75 | +static void reset_btype(DisasContext *s) | ||
76 | +{ | ||
77 | + if (s->btype != 0) { | ||
78 | + TCGv_i32 zero = tcg_const_i32(0); | ||
79 | + tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); | ||
80 | + tcg_temp_free_i32(zero); | ||
81 | + s->btype = 0; | ||
82 | + } | ||
83 | +} | ||
84 | + | ||
85 | void aarch64_cpu_dump_state(CPUState *cs, FILE *f, | ||
86 | fprintf_function cpu_fprintf, int flags) | ||
87 | { | ||
88 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) | ||
89 | } | ||
90 | } | ||
91 | |||
92 | +/** | ||
93 | + * is_guarded_page: | ||
94 | + * @env: The cpu environment | ||
95 | + * @s: The DisasContext | ||
96 | + * | ||
97 | + * Return true if the page is guarded. | ||
98 | + */ | ||
99 | +static bool is_guarded_page(CPUARMState *env, DisasContext *s) | ||
100 | +{ | ||
101 | +#ifdef CONFIG_USER_ONLY | ||
102 | + return false; /* FIXME */ | ||
103 | +#else | ||
104 | + uint64_t addr = s->base.pc_first; | ||
105 | + int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); | ||
106 | + unsigned int index = tlb_index(env, mmu_idx, addr); | ||
107 | + CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); | ||
108 | + | 55 | + |
109 | + /* | 56 | + /* |
110 | + * We test this immediately after reading an insn, which means | 57 | + * TZASC |
111 | + * that any normal page must be in the TLB. The only exception | ||
112 | + * would be for executing from flash or device memory, which | ||
113 | + * does not retain the TLB entry. | ||
114 | + * | ||
115 | + * FIXME: Assume false for those, for now. We could use | ||
116 | + * arm_cpu_get_phys_page_attrs_debug to re-read the page | ||
117 | + * table entry even for that case. | ||
118 | + */ | 58 | + */ |
119 | + return (tlb_hit(entry->addr_code, addr) && | 59 | + create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR, |
120 | + env->iotlb[mmu_idx][index].attrs.target_tlb_bit0); | 60 | + FSL_IMX7_TZASC_SIZE); |
121 | +#endif | ||
122 | +} | ||
123 | + | ||
124 | +/** | ||
125 | + * btype_destination_ok: | ||
126 | + * @insn: The instruction at the branch destination | ||
127 | + * @bt: SCTLR_ELx.BT | ||
128 | + * @btype: PSTATE.BTYPE, and is non-zero | ||
129 | + * | ||
130 | + * On a guarded page, there are a limited number of insns | ||
131 | + * that may be present at the branch target: | ||
132 | + * - branch target identifiers, | ||
133 | + * - paciasp, pacibsp, | ||
134 | + * - BRK insn | ||
135 | + * - HLT insn | ||
136 | + * Anything else causes a Branch Target Exception. | ||
137 | + * | ||
138 | + * Return true if the branch is compatible, false to raise BTITRAP. | ||
139 | + */ | ||
140 | +static bool btype_destination_ok(uint32_t insn, bool bt, int btype) | ||
141 | +{ | ||
142 | + if ((insn & 0xfffff01fu) == 0xd503201fu) { | ||
143 | + /* HINT space */ | ||
144 | + switch (extract32(insn, 5, 7)) { | ||
145 | + case 0b011001: /* PACIASP */ | ||
146 | + case 0b011011: /* PACIBSP */ | ||
147 | + /* | ||
148 | + * If SCTLR_ELx.BT, then PACI*SP are not compatible | ||
149 | + * with btype == 3. Otherwise all btype are ok. | ||
150 | + */ | ||
151 | + return !bt || btype != 3; | ||
152 | + case 0b100000: /* BTI */ | ||
153 | + /* Not compatible with any btype. */ | ||
154 | + return false; | ||
155 | + case 0b100010: /* BTI c */ | ||
156 | + /* Not compatible with btype == 3 */ | ||
157 | + return btype != 3; | ||
158 | + case 0b100100: /* BTI j */ | ||
159 | + /* Not compatible with btype == 2 */ | ||
160 | + return btype != 2; | ||
161 | + case 0b100110: /* BTI jc */ | ||
162 | + /* Compatible with any btype. */ | ||
163 | + return true; | ||
164 | + } | ||
165 | + } else { | ||
166 | + switch (insn & 0xffe0001fu) { | ||
167 | + case 0xd4200000u: /* BRK */ | ||
168 | + case 0xd4400000u: /* HLT */ | ||
169 | + /* Give priority to the breakpoint exception. */ | ||
170 | + return true; | ||
171 | + } | ||
172 | + } | ||
173 | + return false; | ||
174 | +} | ||
175 | + | ||
176 | /* C3.1 A64 instruction index by encoding */ | ||
177 | static void disas_a64_insn(CPUARMState *env, DisasContext *s) | ||
178 | { | ||
179 | @@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) | ||
180 | |||
181 | s->fp_access_checked = false; | ||
182 | |||
183 | + if (dc_isar_feature(aa64_bti, s)) { | ||
184 | + if (s->base.num_insns == 1) { | ||
185 | + /* | ||
186 | + * At the first insn of the TB, compute s->guarded_page. | ||
187 | + * We delayed computing this until successfully reading | ||
188 | + * the first insn of the TB, above. This (mostly) ensures | ||
189 | + * that the softmmu tlb entry has been populated, and the | ||
190 | + * page table GP bit is available. | ||
191 | + * | ||
192 | + * Note that we need to compute this even if btype == 0, | ||
193 | + * because this value is used for BR instructions later | ||
194 | + * where ENV is not available. | ||
195 | + */ | ||
196 | + s->guarded_page = is_guarded_page(env, s); | ||
197 | + | ||
198 | + /* First insn can have btype set to non-zero. */ | ||
199 | + tcg_debug_assert(s->btype >= 0); | ||
200 | + | ||
201 | + /* | ||
202 | + * Note that the Branch Target Exception has fairly high | ||
203 | + * priority -- below debugging exceptions but above most | ||
204 | + * everything else. This allows us to handle this now | ||
205 | + * instead of waiting until the insn is otherwise decoded. | ||
206 | + */ | ||
207 | + if (s->btype != 0 | ||
208 | + && s->guarded_page | ||
209 | + && !btype_destination_ok(insn, s->bt, s->btype)) { | ||
210 | + gen_exception_insn(s, 4, EXCP_UDEF, syn_btitrap(s->btype), | ||
211 | + default_exception_el(s)); | ||
212 | + return; | ||
213 | + } | ||
214 | + } else { | ||
215 | + /* Not the first insn: btype must be 0. */ | ||
216 | + tcg_debug_assert(s->btype == 0); | ||
217 | + } | ||
218 | + } | ||
219 | + | ||
220 | switch (extract32(insn, 25, 4)) { | ||
221 | case 0x0: case 0x1: case 0x3: /* UNALLOCATED */ | ||
222 | unallocated_encoding(s); | ||
223 | @@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) | ||
224 | |||
225 | /* if we allocated any temporaries, free them here */ | ||
226 | free_tmp_a64(s); | ||
227 | + | 61 | + |
228 | + /* | 62 | + /* |
229 | + * After execution of most insns, btype is reset to 0. | 63 | + * OCRAM memory |
230 | + * Note that we set btype == -1 when the insn sets btype. | ||
231 | + */ | 64 | + */ |
232 | + if (s->btype > 0 && s->base.is_jmp != DISAS_NORETURN) { | 65 | + memory_region_init_ram(&s->ocram, NULL, "imx7.ocram", |
233 | + reset_btype(s); | 66 | + FSL_IMX7_OCRAM_MEM_SIZE, |
234 | + } | 67 | + &error_abort); |
68 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR, | ||
69 | + &s->ocram); | ||
70 | + | ||
71 | + /* | ||
72 | + * OCRAM EPDC memory | ||
73 | + */ | ||
74 | + memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc", | ||
75 | + FSL_IMX7_OCRAM_EPDC_SIZE, | ||
76 | + &error_abort); | ||
77 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR, | ||
78 | + &s->ocram_epdc); | ||
79 | + | ||
80 | + /* | ||
81 | + * OCRAM PXP memory | ||
82 | + */ | ||
83 | + memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp", | ||
84 | + FSL_IMX7_OCRAM_PXP_SIZE, | ||
85 | + &error_abort); | ||
86 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR, | ||
87 | + &s->ocram_pxp); | ||
88 | + | ||
89 | + /* | ||
90 | + * OCRAM_S memory | ||
91 | + */ | ||
92 | + memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s", | ||
93 | + FSL_IMX7_OCRAM_S_SIZE, | ||
94 | + &error_abort); | ||
95 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR, | ||
96 | + &s->ocram_s); | ||
97 | + | ||
98 | + /* | ||
99 | + * ROM memory | ||
100 | + */ | ||
101 | + memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom", | ||
102 | + FSL_IMX7_ROM_SIZE, &error_abort); | ||
103 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR, | ||
104 | + &s->rom); | ||
105 | + | ||
106 | + /* | ||
107 | + * CAAM memory | ||
108 | + */ | ||
109 | + memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam", | ||
110 | + FSL_IMX7_CAAM_MEM_SIZE, &error_abort); | ||
111 | + memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR, | ||
112 | + &s->caam); | ||
235 | } | 113 | } |
236 | 114 | ||
237 | static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, | 115 | static Property fsl_imx7_properties[] = { |
238 | -- | 116 | -- |
239 | 2.20.1 | 117 | 2.34.1 |
240 | 118 | ||
241 | 119 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Jean-Christophe Dubois <jcd@tribudubois.net> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 3 | The SRC device is normally used to start the secondary CPU. |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | |
5 | Message-id: 20190201195404.30486-3-richard.henderson@linaro.org | 5 | When running Linux directly, QEMU is emulating a PSCI interface that UBOOT |
6 | is installing at boot time and therefore the fact that the SRC device is | ||
7 | unimplemented is hidden as Qemu respond directly to PSCI requets without | ||
8 | using the SRC device. | ||
9 | |||
10 | But if you try to run a more bare metal application (maybe uboot itself), | ||
11 | then it is not possible to start the secondary CPU as the SRC is an | ||
12 | unimplemented device. | ||
13 | |||
14 | This patch adds the ability to start the secondary CPU through the SRC | ||
15 | device so that you can use this feature in bare metal applications. | ||
16 | |||
17 | Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> | ||
18 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
19 | Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 21 | --- |
8 | tests/tcg/aarch64/Makefile.target | 6 +++++- | 22 | include/hw/arm/fsl-imx7.h | 3 +- |
9 | tests/tcg/aarch64/pauth-1.c | 23 +++++++++++++++++++++++ | 23 | include/hw/misc/imx7_src.h | 66 +++++++++ |
10 | 2 files changed, 28 insertions(+), 1 deletion(-) | 24 | hw/arm/fsl-imx7.c | 8 +- |
11 | create mode 100644 tests/tcg/aarch64/pauth-1.c | 25 | hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++++++ |
12 | 26 | hw/misc/meson.build | 1 + | |
13 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target | 27 | hw/misc/trace-events | 4 + |
28 | 6 files changed, 356 insertions(+), 2 deletions(-) | ||
29 | create mode 100644 include/hw/misc/imx7_src.h | ||
30 | create mode 100644 hw/misc/imx7_src.c | ||
31 | |||
32 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/tests/tcg/aarch64/Makefile.target | 34 | --- a/include/hw/arm/fsl-imx7.h |
16 | +++ b/tests/tcg/aarch64/Makefile.target | 35 | +++ b/include/hw/arm/fsl-imx7.h |
17 | @@ -XXX,XX +XXX,XX @@ VPATH += $(AARCH64_SRC) | 36 | @@ -XXX,XX +XXX,XX @@ |
18 | # we don't build any of the ARM tests | 37 | #include "hw/misc/imx7_ccm.h" |
19 | AARCH64_TESTS=$(filter-out $(ARM_TESTS), $(TESTS)) | 38 | #include "hw/misc/imx7_snvs.h" |
20 | AARCH64_TESTS+=fcvt | 39 | #include "hw/misc/imx7_gpr.h" |
21 | -TESTS:=$(AARCH64_TESTS) | 40 | +#include "hw/misc/imx7_src.h" |
22 | 41 | #include "hw/watchdog/wdt_imx2.h" | |
23 | fcvt: LDFLAGS+=-lm | 42 | #include "hw/gpio/imx_gpio.h" |
24 | 43 | #include "hw/char/imx_serial.h" | |
25 | run-fcvt: fcvt | 44 | @@ -XXX,XX +XXX,XX @@ struct FslIMX7State { |
26 | $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") | 45 | IMX7CCMState ccm; |
27 | $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) | 46 | IMX7AnalogState analog; |
28 | + | 47 | IMX7SNVSState snvs; |
29 | +AARCH64_TESTS += pauth-1 | 48 | + IMX7SRCState src; |
30 | +run-pauth-%: QEMU += -cpu max | 49 | IMXGPCv2State gpcv2; |
31 | + | 50 | IMXSPIState spi[FSL_IMX7_NUM_ECSPIS]; |
32 | +TESTS:=$(AARCH64_TESTS) | 51 | IMXI2CState i2c[FSL_IMX7_NUM_I2CS]; |
33 | diff --git a/tests/tcg/aarch64/pauth-1.c b/tests/tcg/aarch64/pauth-1.c | 52 | @@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap { |
53 | FSL_IMX7_GPC_ADDR = 0x303A0000, | ||
54 | |||
55 | FSL_IMX7_SRC_ADDR = 0x30390000, | ||
56 | - FSL_IMX7_SRC_SIZE = (4 * KiB), | ||
57 | |||
58 | FSL_IMX7_CCM_ADDR = 0x30380000, | ||
59 | |||
60 | diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h | ||
34 | new file mode 100644 | 61 | new file mode 100644 |
35 | index XXXXXXX..XXXXXXX | 62 | index XXXXXXX..XXXXXXX |
36 | --- /dev/null | 63 | --- /dev/null |
37 | +++ b/tests/tcg/aarch64/pauth-1.c | 64 | +++ b/include/hw/misc/imx7_src.h |
38 | @@ -XXX,XX +XXX,XX @@ | 65 | @@ -XXX,XX +XXX,XX @@ |
39 | +#include <assert.h> | 66 | +/* |
40 | +#include <sys/prctl.h> | 67 | + * IMX7 System Reset Controller |
41 | + | 68 | + * |
42 | +asm(".arch armv8.4-a"); | 69 | + * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net> |
43 | + | 70 | + * |
44 | +#ifndef PR_PAC_RESET_KEYS | 71 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
45 | +#define PR_PAC_RESET_KEYS 54 | 72 | + * See the COPYING file in the top-level directory. |
46 | +#define PR_PAC_APDAKEY (1 << 2) | 73 | + */ |
47 | +#endif | 74 | + |
48 | + | 75 | +#ifndef IMX7_SRC_H |
49 | +int main() | 76 | +#define IMX7_SRC_H |
50 | +{ | 77 | + |
51 | + int x; | 78 | +#include "hw/sysbus.h" |
52 | + void *p0 = &x, *p1, *p2; | 79 | +#include "qemu/bitops.h" |
53 | + | 80 | +#include "qom/object.h" |
54 | + asm volatile("pacdza %0" : "=r"(p1) : "0"(p0)); | 81 | + |
55 | + prctl(PR_PAC_RESET_KEYS, PR_PAC_APDAKEY, 0, 0, 0); | 82 | +#define SRC_SCR 0 |
56 | + asm volatile("pacdza %0" : "=r"(p2) : "0"(p0)); | 83 | +#define SRC_A7RCR0 1 |
57 | + | 84 | +#define SRC_A7RCR1 2 |
58 | + assert(p1 != p0); | 85 | +#define SRC_M4RCR 3 |
59 | + assert(p1 != p2); | 86 | +#define SRC_ERCR 5 |
60 | + return 0; | 87 | +#define SRC_HSICPHY_RCR 7 |
61 | +} | 88 | +#define SRC_USBOPHY1_RCR 8 |
89 | +#define SRC_USBOPHY2_RCR 9 | ||
90 | +#define SRC_MPIPHY_RCR 10 | ||
91 | +#define SRC_PCIEPHY_RCR 11 | ||
92 | +#define SRC_SBMR1 22 | ||
93 | +#define SRC_SRSR 23 | ||
94 | +#define SRC_SISR 26 | ||
95 | +#define SRC_SIMR 27 | ||
96 | +#define SRC_SBMR2 28 | ||
97 | +#define SRC_GPR1 29 | ||
98 | +#define SRC_GPR2 30 | ||
99 | +#define SRC_GPR3 31 | ||
100 | +#define SRC_GPR4 32 | ||
101 | +#define SRC_GPR5 33 | ||
102 | +#define SRC_GPR6 34 | ||
103 | +#define SRC_GPR7 35 | ||
104 | +#define SRC_GPR8 36 | ||
105 | +#define SRC_GPR9 37 | ||
106 | +#define SRC_GPR10 38 | ||
107 | +#define SRC_MAX 39 | ||
108 | + | ||
109 | +/* SRC_A7SCR1 */ | ||
110 | +#define R_CORE1_ENABLE_SHIFT 1 | ||
111 | +#define R_CORE1_ENABLE_LENGTH 1 | ||
112 | +/* SRC_A7SCR0 */ | ||
113 | +#define R_CORE1_RST_SHIFT 5 | ||
114 | +#define R_CORE1_RST_LENGTH 1 | ||
115 | +#define R_CORE0_RST_SHIFT 4 | ||
116 | +#define R_CORE0_RST_LENGTH 1 | ||
117 | + | ||
118 | +#define TYPE_IMX7_SRC "imx7.src" | ||
119 | +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC) | ||
120 | + | ||
121 | +struct IMX7SRCState { | ||
122 | + /* <private> */ | ||
123 | + SysBusDevice parent_obj; | ||
124 | + | ||
125 | + /* <public> */ | ||
126 | + MemoryRegion iomem; | ||
127 | + | ||
128 | + uint32_t regs[SRC_MAX]; | ||
129 | +}; | ||
130 | + | ||
131 | +#endif /* IMX7_SRC_H */ | ||
132 | diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c | ||
133 | index XXXXXXX..XXXXXXX 100644 | ||
134 | --- a/hw/arm/fsl-imx7.c | ||
135 | +++ b/hw/arm/fsl-imx7.c | ||
136 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj) | ||
137 | */ | ||
138 | object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2); | ||
139 | |||
140 | + /* | ||
141 | + * SRC | ||
142 | + */ | ||
143 | + object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC); | ||
144 | + | ||
145 | /* | ||
146 | * ECSPIs | ||
147 | */ | ||
148 | @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) | ||
149 | /* | ||
150 | * SRC | ||
151 | */ | ||
152 | - create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE); | ||
153 | + sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort); | ||
154 | + sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR); | ||
155 | |||
156 | /* | ||
157 | * Watchdogs | ||
158 | diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c | ||
159 | new file mode 100644 | ||
160 | index XXXXXXX..XXXXXXX | ||
161 | --- /dev/null | ||
162 | +++ b/hw/misc/imx7_src.c | ||
163 | @@ -XXX,XX +XXX,XX @@ | ||
164 | +/* | ||
165 | + * IMX7 System Reset Controller | ||
166 | + * | ||
167 | + * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net> | ||
168 | + * | ||
169 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
170 | + * See the COPYING file in the top-level directory. | ||
171 | + * | ||
172 | + */ | ||
173 | + | ||
174 | +#include "qemu/osdep.h" | ||
175 | +#include "hw/misc/imx7_src.h" | ||
176 | +#include "migration/vmstate.h" | ||
177 | +#include "qemu/bitops.h" | ||
178 | +#include "qemu/log.h" | ||
179 | +#include "qemu/main-loop.h" | ||
180 | +#include "qemu/module.h" | ||
181 | +#include "target/arm/arm-powerctl.h" | ||
182 | +#include "hw/core/cpu.h" | ||
183 | +#include "hw/registerfields.h" | ||
184 | + | ||
185 | +#include "trace.h" | ||
186 | + | ||
187 | +static const char *imx7_src_reg_name(uint32_t reg) | ||
188 | +{ | ||
189 | + static char unknown[20]; | ||
190 | + | ||
191 | + switch (reg) { | ||
192 | + case SRC_SCR: | ||
193 | + return "SRC_SCR"; | ||
194 | + case SRC_A7RCR0: | ||
195 | + return "SRC_A7RCR0"; | ||
196 | + case SRC_A7RCR1: | ||
197 | + return "SRC_A7RCR1"; | ||
198 | + case SRC_M4RCR: | ||
199 | + return "SRC_M4RCR"; | ||
200 | + case SRC_ERCR: | ||
201 | + return "SRC_ERCR"; | ||
202 | + case SRC_HSICPHY_RCR: | ||
203 | + return "SRC_HSICPHY_RCR"; | ||
204 | + case SRC_USBOPHY1_RCR: | ||
205 | + return "SRC_USBOPHY1_RCR"; | ||
206 | + case SRC_USBOPHY2_RCR: | ||
207 | + return "SRC_USBOPHY2_RCR"; | ||
208 | + case SRC_PCIEPHY_RCR: | ||
209 | + return "SRC_PCIEPHY_RCR"; | ||
210 | + case SRC_SBMR1: | ||
211 | + return "SRC_SBMR1"; | ||
212 | + case SRC_SRSR: | ||
213 | + return "SRC_SRSR"; | ||
214 | + case SRC_SISR: | ||
215 | + return "SRC_SISR"; | ||
216 | + case SRC_SIMR: | ||
217 | + return "SRC_SIMR"; | ||
218 | + case SRC_SBMR2: | ||
219 | + return "SRC_SBMR2"; | ||
220 | + case SRC_GPR1: | ||
221 | + return "SRC_GPR1"; | ||
222 | + case SRC_GPR2: | ||
223 | + return "SRC_GPR2"; | ||
224 | + case SRC_GPR3: | ||
225 | + return "SRC_GPR3"; | ||
226 | + case SRC_GPR4: | ||
227 | + return "SRC_GPR4"; | ||
228 | + case SRC_GPR5: | ||
229 | + return "SRC_GPR5"; | ||
230 | + case SRC_GPR6: | ||
231 | + return "SRC_GPR6"; | ||
232 | + case SRC_GPR7: | ||
233 | + return "SRC_GPR7"; | ||
234 | + case SRC_GPR8: | ||
235 | + return "SRC_GPR8"; | ||
236 | + case SRC_GPR9: | ||
237 | + return "SRC_GPR9"; | ||
238 | + case SRC_GPR10: | ||
239 | + return "SRC_GPR10"; | ||
240 | + default: | ||
241 | + sprintf(unknown, "%u ?", reg); | ||
242 | + return unknown; | ||
243 | + } | ||
244 | +} | ||
245 | + | ||
246 | +static const VMStateDescription vmstate_imx7_src = { | ||
247 | + .name = TYPE_IMX7_SRC, | ||
248 | + .version_id = 1, | ||
249 | + .minimum_version_id = 1, | ||
250 | + .fields = (VMStateField[]) { | ||
251 | + VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX), | ||
252 | + VMSTATE_END_OF_LIST() | ||
253 | + }, | ||
254 | +}; | ||
255 | + | ||
256 | +static void imx7_src_reset(DeviceState *dev) | ||
257 | +{ | ||
258 | + IMX7SRCState *s = IMX7_SRC(dev); | ||
259 | + | ||
260 | + memset(s->regs, 0, sizeof(s->regs)); | ||
261 | + | ||
262 | + /* Set reset values */ | ||
263 | + s->regs[SRC_SCR] = 0xA0; | ||
264 | + s->regs[SRC_SRSR] = 0x1; | ||
265 | + s->regs[SRC_SIMR] = 0x1F; | ||
266 | +} | ||
267 | + | ||
268 | +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size) | ||
269 | +{ | ||
270 | + uint32_t value = 0; | ||
271 | + IMX7SRCState *s = (IMX7SRCState *)opaque; | ||
272 | + uint32_t index = offset >> 2; | ||
273 | + | ||
274 | + if (index < SRC_MAX) { | ||
275 | + value = s->regs[index]; | ||
276 | + } else { | ||
277 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" | ||
278 | + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); | ||
279 | + } | ||
280 | + | ||
281 | + trace_imx7_src_read(imx7_src_reg_name(index), value); | ||
282 | + | ||
283 | + return value; | ||
284 | +} | ||
285 | + | ||
286 | + | ||
287 | +/* | ||
288 | + * The reset is asynchronous so we need to defer clearing the reset | ||
289 | + * bit until the work is completed. | ||
290 | + */ | ||
291 | + | ||
292 | +struct SRCSCRResetInfo { | ||
293 | + IMX7SRCState *s; | ||
294 | + uint32_t reset_bit; | ||
295 | +}; | ||
296 | + | ||
297 | +static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data) | ||
298 | +{ | ||
299 | + struct SRCSCRResetInfo *ri = data.host_ptr; | ||
300 | + IMX7SRCState *s = ri->s; | ||
301 | + | ||
302 | + assert(qemu_mutex_iothread_locked()); | ||
303 | + | ||
304 | + s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0); | ||
305 | + | ||
306 | + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); | ||
307 | + | ||
308 | + g_free(ri); | ||
309 | +} | ||
310 | + | ||
311 | +static void imx7_defer_clear_reset_bit(uint32_t cpuid, | ||
312 | + IMX7SRCState *s, | ||
313 | + uint32_t reset_shift) | ||
314 | +{ | ||
315 | + struct SRCSCRResetInfo *ri; | ||
316 | + CPUState *cpu = arm_get_cpu_by_id(cpuid); | ||
317 | + | ||
318 | + if (!cpu) { | ||
319 | + return; | ||
320 | + } | ||
321 | + | ||
322 | + ri = g_new(struct SRCSCRResetInfo, 1); | ||
323 | + ri->s = s; | ||
324 | + ri->reset_bit = reset_shift; | ||
325 | + | ||
326 | + async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri)); | ||
327 | +} | ||
328 | + | ||
329 | + | ||
330 | +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value, | ||
331 | + unsigned size) | ||
332 | +{ | ||
333 | + IMX7SRCState *s = (IMX7SRCState *)opaque; | ||
334 | + uint32_t index = offset >> 2; | ||
335 | + long unsigned int change_mask; | ||
336 | + uint32_t current_value = value; | ||
337 | + | ||
338 | + if (index >= SRC_MAX) { | ||
339 | + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" | ||
340 | + HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); | ||
341 | + return; | ||
342 | + } | ||
343 | + | ||
344 | + trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]); | ||
345 | + | ||
346 | + change_mask = s->regs[index] ^ (uint32_t)current_value; | ||
347 | + | ||
348 | + switch (index) { | ||
349 | + case SRC_A7RCR0: | ||
350 | + if (FIELD_EX32(change_mask, CORE0, RST)) { | ||
351 | + arm_reset_cpu(0); | ||
352 | + imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT); | ||
353 | + } | ||
354 | + if (FIELD_EX32(change_mask, CORE1, RST)) { | ||
355 | + arm_reset_cpu(1); | ||
356 | + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); | ||
357 | + } | ||
358 | + s->regs[index] = current_value; | ||
359 | + break; | ||
360 | + case SRC_A7RCR1: | ||
361 | + /* | ||
362 | + * On real hardware when the system reset controller starts a | ||
363 | + * secondary CPU it runs through some boot ROM code which reads | ||
364 | + * the SRC_GPRX registers controlling the start address and branches | ||
365 | + * to it. | ||
366 | + * Here we are taking a short cut and branching directly to the | ||
367 | + * requested address (we don't want to run the boot ROM code inside | ||
368 | + * QEMU) | ||
369 | + */ | ||
370 | + if (FIELD_EX32(change_mask, CORE1, ENABLE)) { | ||
371 | + if (FIELD_EX32(current_value, CORE1, ENABLE)) { | ||
372 | + /* CORE 1 is brought up */ | ||
373 | + arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4], | ||
374 | + 3, false); | ||
375 | + } else { | ||
376 | + /* CORE 1 is shut down */ | ||
377 | + arm_set_cpu_off(1); | ||
378 | + } | ||
379 | + /* We clear the reset bits as the processor changed state */ | ||
380 | + imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT); | ||
381 | + clear_bit(R_CORE1_RST_SHIFT, &change_mask); | ||
382 | + } | ||
383 | + s->regs[index] = current_value; | ||
384 | + break; | ||
385 | + default: | ||
386 | + s->regs[index] = current_value; | ||
387 | + break; | ||
388 | + } | ||
389 | +} | ||
390 | + | ||
391 | +static const struct MemoryRegionOps imx7_src_ops = { | ||
392 | + .read = imx7_src_read, | ||
393 | + .write = imx7_src_write, | ||
394 | + .endianness = DEVICE_NATIVE_ENDIAN, | ||
395 | + .valid = { | ||
396 | + /* | ||
397 | + * Our device would not work correctly if the guest was doing | ||
398 | + * unaligned access. This might not be a limitation on the real | ||
399 | + * device but in practice there is no reason for a guest to access | ||
400 | + * this device unaligned. | ||
401 | + */ | ||
402 | + .min_access_size = 4, | ||
403 | + .max_access_size = 4, | ||
404 | + .unaligned = false, | ||
405 | + }, | ||
406 | +}; | ||
407 | + | ||
408 | +static void imx7_src_realize(DeviceState *dev, Error **errp) | ||
409 | +{ | ||
410 | + IMX7SRCState *s = IMX7_SRC(dev); | ||
411 | + | ||
412 | + memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s, | ||
413 | + TYPE_IMX7_SRC, 0x1000); | ||
414 | + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); | ||
415 | +} | ||
416 | + | ||
417 | +static void imx7_src_class_init(ObjectClass *klass, void *data) | ||
418 | +{ | ||
419 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
420 | + | ||
421 | + dc->realize = imx7_src_realize; | ||
422 | + dc->reset = imx7_src_reset; | ||
423 | + dc->vmsd = &vmstate_imx7_src; | ||
424 | + dc->desc = "i.MX6 System Reset Controller"; | ||
425 | +} | ||
426 | + | ||
427 | +static const TypeInfo imx7_src_info = { | ||
428 | + .name = TYPE_IMX7_SRC, | ||
429 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
430 | + .instance_size = sizeof(IMX7SRCState), | ||
431 | + .class_init = imx7_src_class_init, | ||
432 | +}; | ||
433 | + | ||
434 | +static void imx7_src_register_types(void) | ||
435 | +{ | ||
436 | + type_register_static(&imx7_src_info); | ||
437 | +} | ||
438 | + | ||
439 | +type_init(imx7_src_register_types) | ||
440 | diff --git a/hw/misc/meson.build b/hw/misc/meson.build | ||
441 | index XXXXXXX..XXXXXXX 100644 | ||
442 | --- a/hw/misc/meson.build | ||
443 | +++ b/hw/misc/meson.build | ||
444 | @@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files( | ||
445 | 'imx6_src.c', | ||
446 | 'imx6ul_ccm.c', | ||
447 | 'imx7_ccm.c', | ||
448 | + 'imx7_src.c', | ||
449 | 'imx7_gpr.c', | ||
450 | 'imx7_snvs.c', | ||
451 | 'imx_ccm.c', | ||
452 | diff --git a/hw/misc/trace-events b/hw/misc/trace-events | ||
453 | index XXXXXXX..XXXXXXX 100644 | ||
454 | --- a/hw/misc/trace-events | ||
455 | +++ b/hw/misc/trace-events | ||
456 | @@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" | ||
457 | ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 | ||
458 | ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 | ||
459 | |||
460 | +# imx7_src.c | ||
461 | +imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 | ||
462 | +imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 | ||
463 | + | ||
464 | # iotkit-sysinfo.c | ||
465 | iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
466 | iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" | ||
62 | -- | 467 | -- |
63 | 2.20.1 | 468 | 2.34.1 |
64 | |||
65 | diff view generated by jsdifflib |
1 | The {IOE, DZE, OFE, UFE, IXE, IDE} bits in the FPSCR/FPCR are for | 1 | The architecture requires (R_TYTWB) that an attempt to return from EL3 |
---|---|---|---|
2 | enabling trapped IEEE floating point exceptions (where IEEE exception | 2 | when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This |
3 | conditions cause a CPU exception rather than updating the FPSR status | 3 | enforces that the CPU can't ever be executing below EL3 with the |
4 | bits). QEMU doesn't implement this (and nor does the hardware we're | 4 | NSE,NS bits indicating an invalid security state.) |
5 | modelling), but for implementations which don't implement trapped | ||
6 | exception handling these control bits are supposed to be RAZ/WI. | ||
7 | This allows guest code to test for whether the feature is present | ||
8 | by trying to write to the bit and checking whether it sticks. | ||
9 | 5 | ||
10 | QEMU is incorrectly making these bits read as written. Make them | 6 | We were missing this check; add it. |
11 | RAZ/WI as the architecture requires. | ||
12 | 7 | ||
13 | In particular this was causing problems for the NetBSD automatic | ||
14 | test suite. | ||
15 | |||
16 | Reported-by: Martin Husemann <martin@netbsd.org> | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
19 | Message-id: 20190131130700.28392-1-peter.maydell@linaro.org | 10 | Message-id: 20230807150618.101357-1-peter.maydell@linaro.org |
20 | --- | 11 | --- |
21 | target/arm/cpu.h | 6 ++++++ | 12 | target/arm/tcg/helper-a64.c | 9 +++++++++ |
22 | target/arm/helper.c | 6 ++++++ | 13 | 1 file changed, 9 insertions(+) |
23 | 2 files changed, 12 insertions(+) | ||
24 | 14 | ||
25 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c |
26 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/tcg/helper-a64.c |
28 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/tcg/helper-a64.c |
29 | @@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); | 19 | @@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) |
30 | #define FPSR_MASK 0xf800009f | 20 | spsr &= ~PSTATE_SS; |
31 | #define FPCR_MASK 0x07ff9f00 | ||
32 | |||
33 | +#define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */ | ||
34 | +#define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */ | ||
35 | +#define FPCR_OFE (1 << 10) /* Overflow exception trap enable */ | ||
36 | +#define FPCR_UFE (1 << 11) /* Underflow exception trap enable */ | ||
37 | +#define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ | ||
38 | +#define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ | ||
39 | #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ | ||
40 | #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ | ||
41 | #define FPCR_DN (1 << 25) /* Default NaN enable bit */ | ||
42 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/helper.c | ||
45 | +++ b/target/arm/helper.c | ||
46 | @@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) | ||
47 | val &= ~FPCR_FZ16; | ||
48 | } | 21 | } |
49 | 22 | ||
50 | + /* | 23 | + /* |
51 | + * We don't implement trapped exception handling, so the | 24 | + * FEAT_RME forbids return from EL3 with an invalid security state. |
52 | + * trap enable bits are all RAZ/WI (not RES0!) | 25 | + * We don't need an explicit check for FEAT_RME here because we enforce |
26 | + * in scr_write() that you can't set the NSE bit without it. | ||
53 | + */ | 27 | + */ |
54 | + val &= ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE); | 28 | + if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) { |
29 | + goto illegal_return; | ||
30 | + } | ||
55 | + | 31 | + |
56 | changed = env->vfp.xregs[ARM_VFP_FPSCR]; | 32 | new_el = el_from_spsr(spsr); |
57 | env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); | 33 | if (new_el == -1) { |
58 | env->vfp.vec_len = (val >> 16) & 7; | 34 | goto illegal_return; |
59 | -- | 35 | -- |
60 | 2.20.1 | 36 | 2.34.1 |
61 | |||
62 | diff view generated by jsdifflib |
1 | The arm_boot_info struct has a skip_dtb_autoload flag: if this is | 1 | In the m48t59 device we almost always use 64-bit arithmetic when |
---|---|---|---|
2 | set to true by the board code then arm_load_kernel() will not | 2 | dealing with time_t deltas. The one exception is in set_alarm(), |
3 | load the DTB itself, but will leave this for the board code to | 3 | which currently uses a plain 'int' to hold the difference between two |
4 | do itself later. However, the check for this is done in a | 4 | time_t values. Switch to int64_t instead to avoid any possible |
5 | code path which is only executed for the case where we load | 5 | overflow issues. |
6 | a kernel image file. If we're taking the "boot via firmware" | ||
7 | code path then the flag isn't honoured and the DTB is never | ||
8 | loaded. | ||
9 | |||
10 | We didn't notice this because the only real user of "boot | ||
11 | via firmware" that cares about the DTB is the virt board | ||
12 | (for UEFI boot), and that always wants skip_dtb_autoload | ||
13 | anyway. But the SBSA reference board model we're planning to | ||
14 | add will want the flag to behave correctly. | ||
15 | |||
16 | Now we've refactored the arm_load_kernel() function, the | ||
17 | fix is simple: drop the early 'return' so we fall into | ||
18 | the same "load the DTB" code the boot-direct-kernel path uses. | ||
19 | 6 | ||
20 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
21 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
22 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
23 | Message-id: 20190131112240.8395-6-peter.maydell@linaro.org | ||
24 | --- | 9 | --- |
25 | hw/arm/boot.c | 1 - | 10 | hw/rtc/m48t59.c | 2 +- |
26 | 1 file changed, 1 deletion(-) | 11 | 1 file changed, 1 insertion(+), 1 deletion(-) |
27 | 12 | ||
28 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 13 | diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c |
29 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
30 | --- a/hw/arm/boot.c | 15 | --- a/hw/rtc/m48t59.c |
31 | +++ b/hw/arm/boot.c | 16 | +++ b/hw/rtc/m48t59.c |
32 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | 17 | @@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque) |
33 | /* Load the kernel. */ | 18 | |
34 | if (!info->kernel_filename || info->firmware_loaded) { | 19 | static void set_alarm(M48t59State *NVRAM) |
35 | arm_setup_firmware_boot(cpu, info); | 20 | { |
36 | - return; | 21 | - int diff; |
37 | } else { | 22 | + int64_t diff; |
38 | arm_setup_direct_kernel_boot(cpu, info); | 23 | if (NVRAM->alrm_timer != NULL) { |
39 | } | 24 | timer_del(NVRAM->alrm_timer); |
25 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; | ||
40 | -- | 26 | -- |
41 | 2.20.1 | 27 | 2.34.1 |
42 | 28 | ||
43 | 29 | diff view generated by jsdifflib |
1 | The code path for booting firmware doesn't set env->boot_info. At | 1 | In the twl92230 device, use int64_t for the two state fields |
---|---|---|---|
2 | first sight this looks odd, so add a comment saying why we don't. | 2 | sec_offset and alm_sec, because we set these to values that |
3 | are either time_t or differences between two time_t values. | ||
4 | |||
5 | These fields aren't saved in vmstate anywhere, so we can | ||
6 | safely widen them. | ||
3 | 7 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
6 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
7 | Message-id: 20190131112240.8395-5-peter.maydell@linaro.org | ||
8 | --- | 10 | --- |
9 | hw/arm/boot.c | 3 ++- | 11 | hw/rtc/twl92230.c | 4 ++-- |
10 | 1 file changed, 2 insertions(+), 1 deletion(-) | 12 | 1 file changed, 2 insertions(+), 2 deletions(-) |
11 | 13 | ||
12 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 14 | diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c |
13 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/arm/boot.c | 16 | --- a/hw/rtc/twl92230.c |
15 | +++ b/hw/arm/boot.c | 17 | +++ b/hw/rtc/twl92230.c |
16 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) | 18 | @@ -XXX,XX +XXX,XX @@ struct MenelausState { |
17 | 19 | struct tm tm; | |
18 | /* | 20 | struct tm new; |
19 | * We will start from address 0 (typically a boot ROM image) in the | 21 | struct tm alm; |
20 | - * same way as hardware. | 22 | - int sec_offset; |
21 | + * same way as hardware. Leave env->boot_info NULL, so that | 23 | - int alm_sec; |
22 | + * do_cpu_reset() knows it does not need to alter the PC on reset. | 24 | + int64_t sec_offset; |
23 | */ | 25 | + int64_t alm_sec; |
24 | } | 26 | int next_comp; |
25 | 27 | } rtc; | |
28 | uint16_t rtc_next_vmstate; | ||
26 | -- | 29 | -- |
27 | 2.20.1 | 30 | 2.34.1 |
28 | 31 | ||
29 | 32 | diff view generated by jsdifflib |
1 | Fix the block comment style in arm_load_kernel() to QEMU's | 1 | In the aspeed_rtc device we store a difference between two time_t |
---|---|---|---|
2 | current style preferences. This will allow us to do some | 2 | values in an 'int'. This is not really correct when time_t could |
3 | refactoring of this function without checkpatch complaining | 3 | be 64 bits. Enlarge the field to 'int64_t'. |
4 | about the code-motion patches. | 4 | |
5 | This is a migration compatibility break for the aspeed boards. | ||
6 | While we are changing the vmstate, remove the accidental | ||
7 | duplicate of the offset field. | ||
5 | 8 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Reviewed-by: Cédric Le Goater <clg@kaod.org> |
8 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
9 | Message-id: 20190131112240.8395-2-peter.maydell@linaro.org | ||
10 | --- | 11 | --- |
11 | hw/arm/boot.c | 30 ++++++++++++++++++++---------- | 12 | include/hw/rtc/aspeed_rtc.h | 2 +- |
12 | 1 file changed, 20 insertions(+), 10 deletions(-) | 13 | hw/rtc/aspeed_rtc.c | 5 ++--- |
14 | 2 files changed, 3 insertions(+), 4 deletions(-) | ||
13 | 15 | ||
14 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 16 | diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h |
15 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/boot.c | 18 | --- a/include/hw/rtc/aspeed_rtc.h |
17 | +++ b/hw/arm/boot.c | 19 | +++ b/include/hw/rtc/aspeed_rtc.h |
18 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | 20 | @@ -XXX,XX +XXX,XX @@ struct AspeedRtcState { |
19 | static const ARMInsnFixup *primary_loader; | 21 | qemu_irq irq; |
20 | AddressSpace *as = arm_boot_address_space(cpu, info); | 22 | |
21 | 23 | uint32_t reg[0x18]; | |
22 | - /* CPU objects (unlike devices) are not automatically reset on system | 24 | - int offset; |
23 | + /* | 25 | + int64_t offset; |
24 | + * CPU objects (unlike devices) are not automatically reset on system | 26 | |
25 | * reset, so we must always register a handler to do so. If we're | 27 | }; |
26 | * actually loading a kernel, the handler is also responsible for | 28 | |
27 | * arranging that we start it correctly. | 29 | diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c |
28 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | 30 | index XXXXXXX..XXXXXXX 100644 |
29 | qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); | 31 | --- a/hw/rtc/aspeed_rtc.c |
32 | +++ b/hw/rtc/aspeed_rtc.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = { | ||
34 | |||
35 | static const VMStateDescription vmstate_aspeed_rtc = { | ||
36 | .name = TYPE_ASPEED_RTC, | ||
37 | - .version_id = 1, | ||
38 | + .version_id = 2, | ||
39 | .fields = (VMStateField[]) { | ||
40 | VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18), | ||
41 | - VMSTATE_INT32(offset, AspeedRtcState), | ||
42 | - VMSTATE_INT32(offset, AspeedRtcState), | ||
43 | + VMSTATE_INT64(offset, AspeedRtcState), | ||
44 | VMSTATE_END_OF_LIST() | ||
30 | } | 45 | } |
31 | 46 | }; | |
32 | - /* The board code is not supposed to set secure_board_setup unless | ||
33 | + /* | ||
34 | + * The board code is not supposed to set secure_board_setup unless | ||
35 | * running its code in secure mode is actually possible, and KVM | ||
36 | * doesn't support secure. | ||
37 | */ | ||
38 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
39 | if (!info->kernel_filename || info->firmware_loaded) { | ||
40 | |||
41 | if (have_dtb(info)) { | ||
42 | - /* If we have a device tree blob, but no kernel to supply it to (or | ||
43 | + /* | ||
44 | + * If we have a device tree blob, but no kernel to supply it to (or | ||
45 | * the kernel is supposed to be loaded by the bootloader), copy the | ||
46 | * DTB to the base of RAM for the bootloader to pick up. | ||
47 | */ | ||
48 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
49 | try_decompressing_kernel = arm_feature(&cpu->env, | ||
50 | ARM_FEATURE_AARCH64); | ||
51 | |||
52 | - /* Expose the kernel, the command line, and the initrd in fw_cfg. | ||
53 | + /* | ||
54 | + * Expose the kernel, the command line, and the initrd in fw_cfg. | ||
55 | * We don't process them here at all, it's all left to the | ||
56 | * firmware. | ||
57 | */ | ||
58 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
59 | } | ||
60 | } | ||
61 | |||
62 | - /* We will start from address 0 (typically a boot ROM image) in the | ||
63 | + /* | ||
64 | + * We will start from address 0 (typically a boot ROM image) in the | ||
65 | * same way as hardware. | ||
66 | */ | ||
67 | return; | ||
68 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
69 | if (info->nb_cpus == 0) | ||
70 | info->nb_cpus = 1; | ||
71 | |||
72 | - /* We want to put the initrd far enough into RAM that when the | ||
73 | + /* | ||
74 | + * We want to put the initrd far enough into RAM that when the | ||
75 | * kernel is uncompressed it will not clobber the initrd. However | ||
76 | * on boards without much RAM we must ensure that we still leave | ||
77 | * enough room for a decent sized initrd, and on boards with large | ||
78 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
79 | kernel_size = arm_load_elf(info, &elf_entry, &elf_low_addr, | ||
80 | &elf_high_addr, elf_machine, as); | ||
81 | if (kernel_size > 0 && have_dtb(info)) { | ||
82 | - /* If there is still some room left at the base of RAM, try and put | ||
83 | + /* | ||
84 | + * If there is still some room left at the base of RAM, try and put | ||
85 | * the DTB there like we do for images loaded with -bios or -pflash. | ||
86 | */ | ||
87 | if (elf_low_addr > info->loader_start | ||
88 | || elf_high_addr < info->loader_start) { | ||
89 | - /* Set elf_low_addr as address limit for arm_load_dtb if it may be | ||
90 | + /* | ||
91 | + * Set elf_low_addr as address limit for arm_load_dtb if it may be | ||
92 | * pointing into RAM, otherwise pass '0' (no limit) | ||
93 | */ | ||
94 | if (elf_low_addr < info->loader_start) { | ||
95 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
96 | fixupcontext[FIXUP_BOARDID] = info->board_id; | ||
97 | fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr; | ||
98 | |||
99 | - /* for device tree boot, we pass the DTB directly in r2. Otherwise | ||
100 | + /* | ||
101 | + * for device tree boot, we pass the DTB directly in r2. Otherwise | ||
102 | * we point to the kernel args. | ||
103 | */ | ||
104 | if (have_dtb(info)) { | ||
105 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | ||
106 | info->write_board_setup(cpu, info); | ||
107 | } | ||
108 | |||
109 | - /* Notify devices which need to fake up firmware initialization | ||
110 | + /* | ||
111 | + * Notify devices which need to fake up firmware initialization | ||
112 | * that we're doing a direct kernel boot. | ||
113 | */ | ||
114 | object_child_foreach_recursive(object_get_root(), | ||
115 | -- | 47 | -- |
116 | 2.20.1 | 48 | 2.34.1 |
117 | 49 | ||
118 | 50 | diff view generated by jsdifflib |
1 | Enables, but does not turn on, TBI for CONFIG_USER_ONLY. | 1 | The functions qemu_get_timedate() and qemu_timedate_diff() take |
---|---|---|---|
2 | and return a time offset as an integer. Coverity points out that | ||
3 | means that when an RTC device implementation holds an offset | ||
4 | as a time_t, as the m48t59 does, the time_t will get truncated. | ||
5 | (CID 1507157, 1517772). | ||
2 | 6 | ||
3 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | The functions work with time_t internally, so make them use that type |
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | in their APIs. |
5 | Message-id: 20190204132126.3255-4-richard.henderson@linaro.org | 9 | |
6 | [PMM: adjusted #ifdeffery to placate clang, which otherwise complains | 10 | Note that this won't help any Y2038 issues where either the device |
7 | about static functions that are unused in the CONFIG_USER_ONLY build] | 11 | model itself is keeping the offset in a 32-bit integer, or where the |
12 | hardware under emulation has Y2038 or other rollover problems. If we | ||
13 | missed any cases of the former then hopefully Coverity will warn us | ||
14 | about them since after this patch we'd be truncating a time_t in | ||
15 | assignments from qemu_timedate_diff().) | ||
16 | |||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
9 | --- | 19 | --- |
10 | target/arm/internals.h | 21 -------------------- | 20 | include/sysemu/rtc.h | 4 ++-- |
11 | target/arm/helper.c | 45 ++++++++++++++++++++++-------------------- | 21 | softmmu/rtc.c | 4 ++-- |
12 | 2 files changed, 24 insertions(+), 42 deletions(-) | 22 | 2 files changed, 4 insertions(+), 4 deletions(-) |
13 | 23 | ||
14 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 24 | diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h |
15 | index XXXXXXX..XXXXXXX 100644 | 25 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/internals.h | 26 | --- a/include/sysemu/rtc.h |
17 | +++ b/target/arm/internals.h | 27 | +++ b/include/sysemu/rtc.h |
18 | @@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters { | 28 | @@ -XXX,XX +XXX,XX @@ |
19 | bool using64k : 1; | 29 | * The behaviour of the clock whose value this function returns will |
20 | } ARMVAParameters; | 30 | * depend on the -rtc command line option passed by the user. |
21 | 31 | */ | |
22 | -#ifdef CONFIG_USER_ONLY | 32 | -void qemu_get_timedate(struct tm *tm, int offset); |
23 | -static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env, | 33 | +void qemu_get_timedate(struct tm *tm, time_t offset); |
24 | - uint64_t va, | 34 | |
25 | - ARMMMUIdx mmu_idx) | 35 | /** |
26 | -{ | 36 | * qemu_timedate_diff: Return difference between a struct tm and the RTC |
27 | - return (ARMVAParameters) { | 37 | @@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset); |
28 | - /* 48-bit address space */ | 38 | * a timestamp one hour further ahead than the current RTC time |
29 | - .tsz = 16, | 39 | * then this function will return 3600. |
30 | - /* We can't handle tagged addresses properly in user-only mode */ | 40 | */ |
31 | - .tbi = false, | 41 | -int qemu_timedate_diff(struct tm *tm); |
32 | - }; | 42 | +time_t qemu_timedate_diff(struct tm *tm); |
33 | -} | ||
34 | - | ||
35 | -static inline ARMVAParameters aa64_va_parameters(CPUARMState *env, | ||
36 | - uint64_t va, | ||
37 | - ARMMMUIdx mmu_idx, bool data) | ||
38 | -{ | ||
39 | - return aa64_va_parameters_both(env, va, mmu_idx); | ||
40 | -} | ||
41 | -#else | ||
42 | ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, | ||
43 | ARMMMUIdx mmu_idx); | ||
44 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
45 | ARMMMUIdx mmu_idx, bool data); | ||
46 | -#endif | ||
47 | 43 | ||
48 | #endif | 44 | #endif |
49 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 45 | diff --git a/softmmu/rtc.c b/softmmu/rtc.c |
50 | index XXXXXXX..XXXXXXX 100644 | 46 | index XXXXXXX..XXXXXXX 100644 |
51 | --- a/target/arm/helper.c | 47 | --- a/softmmu/rtc.c |
52 | +++ b/target/arm/helper.c | 48 | +++ b/softmmu/rtc.c |
53 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rbit)(uint32_t x) | 49 | @@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock) |
54 | return revbit32(x); | 50 | return value; |
55 | } | 51 | } |
56 | 52 | ||
57 | -#if defined(CONFIG_USER_ONLY) | 53 | -void qemu_get_timedate(struct tm *tm, int offset) |
58 | +#ifdef CONFIG_USER_ONLY | 54 | +void qemu_get_timedate(struct tm *tm, time_t offset) |
59 | 55 | { | |
60 | /* These should probably raise undefined insn exceptions. */ | 56 | time_t ti = qemu_ref_timedate(rtc_clock); |
61 | void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) | 57 | |
62 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | 58 | @@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset) |
63 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | ||
64 | } | 59 | } |
65 | } | 60 | } |
66 | +#endif /* !CONFIG_USER_ONLY */ | 61 | |
67 | 62 | -int qemu_timedate_diff(struct tm *tm) | |
68 | /* Return the exception level which controls this address translation regime */ | 63 | +time_t qemu_timedate_diff(struct tm *tm) |
69 | static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
70 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
71 | } | ||
72 | } | ||
73 | |||
74 | +#ifndef CONFIG_USER_ONLY | ||
75 | + | ||
76 | /* Return the SCTLR value which controls this address translation regime */ | ||
77 | static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
78 | { | 64 | { |
79 | @@ -XXX,XX +XXX,XX @@ static inline bool regime_translation_big_endian(CPUARMState *env, | 65 | time_t seconds; |
80 | return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0; | 66 | |
81 | } | ||
82 | |||
83 | +/* Return the TTBR associated with this translation regime */ | ||
84 | +static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | ||
85 | + int ttbrn) | ||
86 | +{ | ||
87 | + if (mmu_idx == ARMMMUIdx_S2NS) { | ||
88 | + return env->cp15.vttbr_el2; | ||
89 | + } | ||
90 | + if (ttbrn == 0) { | ||
91 | + return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | ||
92 | + } else { | ||
93 | + return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | ||
94 | + } | ||
95 | +} | ||
96 | + | ||
97 | +#endif /* !CONFIG_USER_ONLY */ | ||
98 | + | ||
99 | /* Return the TCR controlling this translation regime */ | ||
100 | static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
101 | { | ||
102 | @@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) | ||
103 | return mmu_idx; | ||
104 | } | ||
105 | |||
106 | -/* Return the TTBR associated with this translation regime */ | ||
107 | -static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, | ||
108 | - int ttbrn) | ||
109 | -{ | ||
110 | - if (mmu_idx == ARMMMUIdx_S2NS) { | ||
111 | - return env->cp15.vttbr_el2; | ||
112 | - } | ||
113 | - if (ttbrn == 0) { | ||
114 | - return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; | ||
115 | - } else { | ||
116 | - return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; | ||
117 | - } | ||
118 | -} | ||
119 | - | ||
120 | /* Return true if the translation regime is using LPAE format page tables */ | ||
121 | static inline bool regime_using_lpae_format(CPUARMState *env, | ||
122 | ARMMMUIdx mmu_idx) | ||
123 | @@ -XXX,XX +XXX,XX @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
124 | return regime_using_lpae_format(env, mmu_idx); | ||
125 | } | ||
126 | |||
127 | +#ifndef CONFIG_USER_ONLY | ||
128 | static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) | ||
129 | { | ||
130 | switch (mmu_idx) { | ||
131 | @@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) | ||
132 | |||
133 | return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; | ||
134 | } | ||
135 | +#endif /* !CONFIG_USER_ONLY */ | ||
136 | |||
137 | ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, | ||
138 | ARMMMUIdx mmu_idx) | ||
139 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | ||
140 | return ret; | ||
141 | } | ||
142 | |||
143 | +#ifndef CONFIG_USER_ONLY | ||
144 | static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, | ||
145 | ARMMMUIdx mmu_idx) | ||
146 | { | ||
147 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
148 | *pc = env->pc; | ||
149 | flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); | ||
150 | |||
151 | -#ifndef CONFIG_USER_ONLY | ||
152 | - /* | ||
153 | - * Get control bits for tagged addresses. Note that the | ||
154 | - * translator only uses this for instruction addresses. | ||
155 | - */ | ||
156 | + /* Get control bits for tagged addresses. */ | ||
157 | { | ||
158 | ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); | ||
159 | ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); | ||
160 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
161 | flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); | ||
162 | flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); | ||
163 | } | ||
164 | -#endif | ||
165 | |||
166 | if (cpu_isar_feature(aa64_sve, cpu)) { | ||
167 | int sve_el = sve_exception_el(env, current_el); | ||
168 | -- | 67 | -- |
169 | 2.20.1 | 68 | 2.34.1 |
170 | 69 | ||
171 | 70 | diff view generated by jsdifflib |
1 | Factor out the "direct kernel boot" code path from arm_load_kernel() | 1 | Where architecturally one ARM_FEATURE_X flag implies another |
---|---|---|---|
2 | into its own function; this function is getting long enough that | 2 | ARM_FEATURE_Y, we allow the CPU init function to only set X, and then |
3 | the code flow is a bit confusing. | 3 | set Y for it. Currently we do this in two places -- we set a few |
4 | 4 | flags in arm_cpu_post_init() because we need them to decide which | |
5 | This commit only moves code around; no semantic changes. | 5 | properties to create on the CPU object, and then we do the rest in |
6 | 6 | arm_cpu_realizefn(). However, this is fragile, because it's easy to | |
7 | We leave the "load the dtb" code in arm_load_kernel() -- this | 7 | add a new property and not notice that this means that an X-implies-Y |
8 | is currently only used by the "direct kernel boot" path, but | 8 | check now has to move from realize to post-init. |
9 | this is a bug which we will fix shortly. | 9 | |
10 | As a specific example, the pmsav7-dregion property is conditional | ||
11 | on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear | ||
12 | on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and | ||
13 | rely on V8-implies-V7, which doesn't happen until the realizefn. | ||
14 | |||
15 | Move all of these X-implies-Y checks into a new function, which | ||
16 | we call at the top of arm_cpu_post_init(), so the feature bits | ||
17 | are available at that point. | ||
18 | |||
19 | This does now give us the reverse issue, that if there's a feature | ||
20 | bit which is enabled or disabled by the setting of a property then | ||
21 | then X-implies-Y features that are dependent on that property need to | ||
22 | be in realize, not in this new function. But the only one of those | ||
23 | is the "EL3 implies VBAR" which is already in the right place, so | ||
24 | putting things this way round seems better to me. | ||
10 | 25 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 26 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 27 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | 28 | Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org |
14 | Message-id: 20190131112240.8395-3-peter.maydell@linaro.org | ||
15 | --- | 29 | --- |
16 | hw/arm/boot.c | 150 +++++++++++++++++++++++++++----------------------- | 30 | target/arm/cpu.c | 179 +++++++++++++++++++++++++---------------------- |
17 | 1 file changed, 80 insertions(+), 70 deletions(-) | 31 | 1 file changed, 97 insertions(+), 82 deletions(-) |
18 | 32 | ||
19 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 33 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c |
20 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/hw/arm/boot.c | 35 | --- a/target/arm/cpu.c |
22 | +++ b/hw/arm/boot.c | 36 | +++ b/target/arm/cpu.c |
23 | @@ -XXX,XX +XXX,XX @@ static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base, | 37 | @@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu) |
24 | return size; | 38 | NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1; |
25 | } | 39 | } |
26 | 40 | ||
27 | -void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | 41 | +static void arm_cpu_propagate_feature_implications(ARMCPU *cpu) |
28 | +static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | 42 | +{ |
29 | + struct arm_boot_info *info) | 43 | + CPUARMState *env = &cpu->env; |
44 | + bool no_aa32 = false; | ||
45 | + | ||
46 | + /* | ||
47 | + * Some features automatically imply others: set the feature | ||
48 | + * bits explicitly for these cases. | ||
49 | + */ | ||
50 | + | ||
51 | + if (arm_feature(env, ARM_FEATURE_M)) { | ||
52 | + set_feature(env, ARM_FEATURE_PMSA); | ||
53 | + } | ||
54 | + | ||
55 | + if (arm_feature(env, ARM_FEATURE_V8)) { | ||
56 | + if (arm_feature(env, ARM_FEATURE_M)) { | ||
57 | + set_feature(env, ARM_FEATURE_V7); | ||
58 | + } else { | ||
59 | + set_feature(env, ARM_FEATURE_V7VE); | ||
60 | + } | ||
61 | + } | ||
62 | + | ||
63 | + /* | ||
64 | + * There exist AArch64 cpus without AArch32 support. When KVM | ||
65 | + * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. | ||
66 | + * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. | ||
67 | + * As a general principle, we also do not make ID register | ||
68 | + * consistency checks anywhere unless using TCG, because only | ||
69 | + * for TCG would a consistency-check failure be a QEMU bug. | ||
70 | + */ | ||
71 | + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | ||
72 | + no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); | ||
73 | + } | ||
74 | + | ||
75 | + if (arm_feature(env, ARM_FEATURE_V7VE)) { | ||
76 | + /* | ||
77 | + * v7 Virtualization Extensions. In real hardware this implies | ||
78 | + * EL2 and also the presence of the Security Extensions. | ||
79 | + * For QEMU, for backwards-compatibility we implement some | ||
80 | + * CPUs or CPU configs which have no actual EL2 or EL3 but do | ||
81 | + * include the various other features that V7VE implies. | ||
82 | + * Presence of EL2 itself is ARM_FEATURE_EL2, and of the | ||
83 | + * Security Extensions is ARM_FEATURE_EL3. | ||
84 | + */ | ||
85 | + assert(!tcg_enabled() || no_aa32 || | ||
86 | + cpu_isar_feature(aa32_arm_div, cpu)); | ||
87 | + set_feature(env, ARM_FEATURE_LPAE); | ||
88 | + set_feature(env, ARM_FEATURE_V7); | ||
89 | + } | ||
90 | + if (arm_feature(env, ARM_FEATURE_V7)) { | ||
91 | + set_feature(env, ARM_FEATURE_VAPA); | ||
92 | + set_feature(env, ARM_FEATURE_THUMB2); | ||
93 | + set_feature(env, ARM_FEATURE_MPIDR); | ||
94 | + if (!arm_feature(env, ARM_FEATURE_M)) { | ||
95 | + set_feature(env, ARM_FEATURE_V6K); | ||
96 | + } else { | ||
97 | + set_feature(env, ARM_FEATURE_V6); | ||
98 | + } | ||
99 | + | ||
100 | + /* | ||
101 | + * Always define VBAR for V7 CPUs even if it doesn't exist in | ||
102 | + * non-EL3 configs. This is needed by some legacy boards. | ||
103 | + */ | ||
104 | + set_feature(env, ARM_FEATURE_VBAR); | ||
105 | + } | ||
106 | + if (arm_feature(env, ARM_FEATURE_V6K)) { | ||
107 | + set_feature(env, ARM_FEATURE_V6); | ||
108 | + set_feature(env, ARM_FEATURE_MVFR); | ||
109 | + } | ||
110 | + if (arm_feature(env, ARM_FEATURE_V6)) { | ||
111 | + set_feature(env, ARM_FEATURE_V5); | ||
112 | + if (!arm_feature(env, ARM_FEATURE_M)) { | ||
113 | + assert(!tcg_enabled() || no_aa32 || | ||
114 | + cpu_isar_feature(aa32_jazelle, cpu)); | ||
115 | + set_feature(env, ARM_FEATURE_AUXCR); | ||
116 | + } | ||
117 | + } | ||
118 | + if (arm_feature(env, ARM_FEATURE_V5)) { | ||
119 | + set_feature(env, ARM_FEATURE_V4T); | ||
120 | + } | ||
121 | + if (arm_feature(env, ARM_FEATURE_LPAE)) { | ||
122 | + set_feature(env, ARM_FEATURE_V7MP); | ||
123 | + } | ||
124 | + if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | ||
125 | + set_feature(env, ARM_FEATURE_CBAR); | ||
126 | + } | ||
127 | + if (arm_feature(env, ARM_FEATURE_THUMB2) && | ||
128 | + !arm_feature(env, ARM_FEATURE_M)) { | ||
129 | + set_feature(env, ARM_FEATURE_THUMB_DSP); | ||
130 | + } | ||
131 | +} | ||
132 | + | ||
133 | void arm_cpu_post_init(Object *obj) | ||
30 | { | 134 | { |
31 | + /* Set up for a direct boot of a kernel image file. */ | 135 | ARMCPU *cpu = ARM_CPU(obj); |
32 | CPUState *cs; | 136 | |
33 | + AddressSpace *as = arm_boot_address_space(cpu, info); | 137 | - /* M profile implies PMSA. We have to do this here rather than |
34 | int kernel_size; | 138 | - * in realize with the other feature-implication checks because |
35 | int initrd_size; | 139 | - * we look at the PMSA bit to see if we should add some properties. |
36 | int is_linux = 0; | 140 | + /* |
37 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | 141 | + * Some features imply others. Figure this out now, because we |
38 | int elf_machine; | 142 | + * are going to look at the feature bits in deciding which |
39 | hwaddr entry; | 143 | + * properties to add. |
40 | static const ARMInsnFixup *primary_loader; | 144 | */ |
41 | - AddressSpace *as = arm_boot_address_space(cpu, info); | 145 | - if (arm_feature(&cpu->env, ARM_FEATURE_M)) { |
146 | - set_feature(&cpu->env, ARM_FEATURE_PMSA); | ||
147 | - } | ||
148 | + arm_cpu_propagate_feature_implications(cpu); | ||
149 | |||
150 | if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || | ||
151 | arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { | ||
152 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
153 | CPUARMState *env = &cpu->env; | ||
154 | int pagebits; | ||
155 | Error *local_err = NULL; | ||
156 | - bool no_aa32 = false; | ||
157 | |||
158 | /* Use pc-relative instructions in system-mode */ | ||
159 | #ifndef CONFIG_USER_ONLY | ||
160 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
161 | cpu->isar.id_isar3 = u; | ||
162 | } | ||
163 | |||
164 | - /* Some features automatically imply others: */ | ||
165 | - if (arm_feature(env, ARM_FEATURE_V8)) { | ||
166 | - if (arm_feature(env, ARM_FEATURE_M)) { | ||
167 | - set_feature(env, ARM_FEATURE_V7); | ||
168 | - } else { | ||
169 | - set_feature(env, ARM_FEATURE_V7VE); | ||
170 | - } | ||
171 | - } | ||
42 | - | 172 | - |
43 | - /* | 173 | - /* |
44 | - * CPU objects (unlike devices) are not automatically reset on system | 174 | - * There exist AArch64 cpus without AArch32 support. When KVM |
45 | - * reset, so we must always register a handler to do so. If we're | 175 | - * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN. |
46 | - * actually loading a kernel, the handler is also responsible for | 176 | - * Similarly, we cannot check ID_AA64PFR0 without AArch64 support. |
47 | - * arranging that we start it correctly. | 177 | - * As a general principle, we also do not make ID register |
178 | - * consistency checks anywhere unless using TCG, because only | ||
179 | - * for TCG would a consistency-check failure be a QEMU bug. | ||
48 | - */ | 180 | - */ |
49 | - for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { | 181 | - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { |
50 | - qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); | 182 | - no_aa32 = !cpu_isar_feature(aa64_aa32, cpu); |
51 | - } | 183 | - } |
52 | - | 184 | - |
53 | - /* | 185 | - if (arm_feature(env, ARM_FEATURE_V7VE)) { |
54 | - * The board code is not supposed to set secure_board_setup unless | 186 | - /* v7 Virtualization Extensions. In real hardware this implies |
55 | - * running its code in secure mode is actually possible, and KVM | 187 | - * EL2 and also the presence of the Security Extensions. |
56 | - * doesn't support secure. | 188 | - * For QEMU, for backwards-compatibility we implement some |
57 | - */ | 189 | - * CPUs or CPU configs which have no actual EL2 or EL3 but do |
58 | - assert(!(info->secure_board_setup && kvm_enabled())); | 190 | - * include the various other features that V7VE implies. |
59 | - | 191 | - * Presence of EL2 itself is ARM_FEATURE_EL2, and of the |
60 | - info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); | 192 | - * Security Extensions is ARM_FEATURE_EL3. |
61 | - info->dtb_limit = 0; | 193 | - */ |
62 | - | 194 | - assert(!tcg_enabled() || no_aa32 || |
63 | - /* Load the kernel. */ | 195 | - cpu_isar_feature(aa32_arm_div, cpu)); |
64 | - if (!info->kernel_filename || info->firmware_loaded) { | 196 | - set_feature(env, ARM_FEATURE_LPAE); |
65 | - | 197 | - set_feature(env, ARM_FEATURE_V7); |
66 | - if (have_dtb(info)) { | 198 | - } |
67 | - /* | 199 | - if (arm_feature(env, ARM_FEATURE_V7)) { |
68 | - * If we have a device tree blob, but no kernel to supply it to (or | 200 | - set_feature(env, ARM_FEATURE_VAPA); |
69 | - * the kernel is supposed to be loaded by the bootloader), copy the | 201 | - set_feature(env, ARM_FEATURE_THUMB2); |
70 | - * DTB to the base of RAM for the bootloader to pick up. | 202 | - set_feature(env, ARM_FEATURE_MPIDR); |
71 | - */ | 203 | - if (!arm_feature(env, ARM_FEATURE_M)) { |
72 | - info->dtb_start = info->loader_start; | 204 | - set_feature(env, ARM_FEATURE_V6K); |
205 | - } else { | ||
206 | - set_feature(env, ARM_FEATURE_V6); | ||
73 | - } | 207 | - } |
74 | - | 208 | - |
75 | - if (info->kernel_filename) { | 209 | - /* Always define VBAR for V7 CPUs even if it doesn't exist in |
76 | - FWCfgState *fw_cfg; | 210 | - * non-EL3 configs. This is needed by some legacy boards. |
77 | - bool try_decompressing_kernel; | 211 | - */ |
78 | - | 212 | - set_feature(env, ARM_FEATURE_VBAR); |
79 | - fw_cfg = fw_cfg_find(); | 213 | - } |
80 | - try_decompressing_kernel = arm_feature(&cpu->env, | 214 | - if (arm_feature(env, ARM_FEATURE_V6K)) { |
81 | - ARM_FEATURE_AARCH64); | 215 | - set_feature(env, ARM_FEATURE_V6); |
82 | - | 216 | - set_feature(env, ARM_FEATURE_MVFR); |
83 | - /* | 217 | - } |
84 | - * Expose the kernel, the command line, and the initrd in fw_cfg. | 218 | - if (arm_feature(env, ARM_FEATURE_V6)) { |
85 | - * We don't process them here at all, it's all left to the | 219 | - set_feature(env, ARM_FEATURE_V5); |
86 | - * firmware. | 220 | - if (!arm_feature(env, ARM_FEATURE_M)) { |
87 | - */ | 221 | - assert(!tcg_enabled() || no_aa32 || |
88 | - load_image_to_fw_cfg(fw_cfg, | 222 | - cpu_isar_feature(aa32_jazelle, cpu)); |
89 | - FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, | 223 | - set_feature(env, ARM_FEATURE_AUXCR); |
90 | - info->kernel_filename, | ||
91 | - try_decompressing_kernel); | ||
92 | - load_image_to_fw_cfg(fw_cfg, | ||
93 | - FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, | ||
94 | - info->initrd_filename, false); | ||
95 | - | ||
96 | - if (info->kernel_cmdline) { | ||
97 | - fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | ||
98 | - strlen(info->kernel_cmdline) + 1); | ||
99 | - fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | ||
100 | - info->kernel_cmdline); | ||
101 | - } | ||
102 | - } | 224 | - } |
103 | - | 225 | - } |
104 | - /* | 226 | - if (arm_feature(env, ARM_FEATURE_V5)) { |
105 | - * We will start from address 0 (typically a boot ROM image) in the | 227 | - set_feature(env, ARM_FEATURE_V4T); |
106 | - * same way as hardware. | 228 | - } |
107 | - */ | 229 | - if (arm_feature(env, ARM_FEATURE_LPAE)) { |
108 | - return; | 230 | - set_feature(env, ARM_FEATURE_V7MP); |
109 | - } | 231 | - } |
110 | 232 | - if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { | |
111 | if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { | 233 | - set_feature(env, ARM_FEATURE_CBAR); |
112 | primary_loader = bootloader_aarch64; | 234 | - } |
113 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | 235 | - if (arm_feature(env, ARM_FEATURE_THUMB2) && |
114 | for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { | 236 | - !arm_feature(env, ARM_FEATURE_M)) { |
115 | ARM_CPU(cs)->env.boot_info = info; | 237 | - set_feature(env, ARM_FEATURE_THUMB_DSP); |
116 | } | 238 | - } |
117 | +} | 239 | |
118 | + | 240 | /* |
119 | +void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | 241 | * We rely on no XScale CPU having VFP so we can use the same bits in the |
120 | +{ | ||
121 | + CPUState *cs; | ||
122 | + AddressSpace *as = arm_boot_address_space(cpu, info); | ||
123 | + | ||
124 | + /* | ||
125 | + * CPU objects (unlike devices) are not automatically reset on system | ||
126 | + * reset, so we must always register a handler to do so. If we're | ||
127 | + * actually loading a kernel, the handler is also responsible for | ||
128 | + * arranging that we start it correctly. | ||
129 | + */ | ||
130 | + for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { | ||
131 | + qemu_register_reset(do_cpu_reset, ARM_CPU(cs)); | ||
132 | + } | ||
133 | + | ||
134 | + /* | ||
135 | + * The board code is not supposed to set secure_board_setup unless | ||
136 | + * running its code in secure mode is actually possible, and KVM | ||
137 | + * doesn't support secure. | ||
138 | + */ | ||
139 | + assert(!(info->secure_board_setup && kvm_enabled())); | ||
140 | + | ||
141 | + info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); | ||
142 | + info->dtb_limit = 0; | ||
143 | + | ||
144 | + /* Load the kernel. */ | ||
145 | + if (!info->kernel_filename || info->firmware_loaded) { | ||
146 | + | ||
147 | + if (have_dtb(info)) { | ||
148 | + /* | ||
149 | + * If we have a device tree blob, but no kernel to supply it to (or | ||
150 | + * the kernel is supposed to be loaded by the bootloader), copy the | ||
151 | + * DTB to the base of RAM for the bootloader to pick up. | ||
152 | + */ | ||
153 | + info->dtb_start = info->loader_start; | ||
154 | + } | ||
155 | + | ||
156 | + if (info->kernel_filename) { | ||
157 | + FWCfgState *fw_cfg; | ||
158 | + bool try_decompressing_kernel; | ||
159 | + | ||
160 | + fw_cfg = fw_cfg_find(); | ||
161 | + try_decompressing_kernel = arm_feature(&cpu->env, | ||
162 | + ARM_FEATURE_AARCH64); | ||
163 | + | ||
164 | + /* | ||
165 | + * Expose the kernel, the command line, and the initrd in fw_cfg. | ||
166 | + * We don't process them here at all, it's all left to the | ||
167 | + * firmware. | ||
168 | + */ | ||
169 | + load_image_to_fw_cfg(fw_cfg, | ||
170 | + FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, | ||
171 | + info->kernel_filename, | ||
172 | + try_decompressing_kernel); | ||
173 | + load_image_to_fw_cfg(fw_cfg, | ||
174 | + FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, | ||
175 | + info->initrd_filename, false); | ||
176 | + | ||
177 | + if (info->kernel_cmdline) { | ||
178 | + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | ||
179 | + strlen(info->kernel_cmdline) + 1); | ||
180 | + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | ||
181 | + info->kernel_cmdline); | ||
182 | + } | ||
183 | + } | ||
184 | + | ||
185 | + /* | ||
186 | + * We will start from address 0 (typically a boot ROM image) in the | ||
187 | + * same way as hardware. | ||
188 | + */ | ||
189 | + return; | ||
190 | + } else { | ||
191 | + arm_setup_direct_kernel_boot(cpu, info); | ||
192 | + } | ||
193 | |||
194 | if (!info->skip_dtb_autoload && have_dtb(info)) { | ||
195 | if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) { | ||
196 | -- | 242 | -- |
197 | 2.20.1 | 243 | 2.34.1 |
198 | |||
199 | diff view generated by jsdifflib |
1 | Factor out the "boot via firmware" code path from arm_load_kernel() | 1 | M-profile CPUs generally allow configuration of the number of MPU |
---|---|---|---|
2 | into its own function. | 2 | regions that they have. We don't currently model this, so our |
3 | implementations of some of the board models provide CPUs with the | ||
4 | wrong number of regions. RTOSes like Zephyr that hardcode the | ||
5 | expected number of regions may therefore not run on the model if they | ||
6 | are set up to run on real hardware. | ||
3 | 7 | ||
4 | This commit only moves code around; no semantic changes. | 8 | Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object, |
9 | matching the ability of hardware to configure the number of Secure | ||
10 | and NonSecure regions separately. Our actual CPU implementation | ||
11 | doesn't currently support that, and it happens that none of the MPS | ||
12 | boards we model set the number of regions differently for Secure vs | ||
13 | NonSecure, so we provide an interface to the boards and SoCs that | ||
14 | won't need to change if we ever do add that functionality in future, | ||
15 | but make it an error to configure the two properties to different | ||
16 | values. | ||
17 | |||
18 | (The property name on the CPU is the somewhat misnamed-for-M-profile | ||
19 | "pmsav7-dregion", so we don't follow that naming convention for | ||
20 | the properties here. The TRM doesn't say what the CPU configuration | ||
21 | variable names are, so we pick something, and follow the lowercase | ||
22 | convention we already have for properties here.) | ||
5 | 23 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 24 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 25 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
8 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | 26 | Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org |
9 | Message-id: 20190131112240.8395-4-peter.maydell@linaro.org | ||
10 | --- | 27 | --- |
11 | hw/arm/boot.c | 92 +++++++++++++++++++++++++++------------------------ | 28 | include/hw/arm/armv7m.h | 8 ++++++++ |
12 | 1 file changed, 49 insertions(+), 43 deletions(-) | 29 | hw/arm/armv7m.c | 21 +++++++++++++++++++++ |
30 | 2 files changed, 29 insertions(+) | ||
13 | 31 | ||
14 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 32 | diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h |
15 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/hw/arm/boot.c | 34 | --- a/include/hw/arm/armv7m.h |
17 | +++ b/hw/arm/boot.c | 35 | +++ b/include/hw/arm/armv7m.h |
18 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | 36 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M) |
37 | * + Property "vfp": enable VFP (forwarded to CPU object) | ||
38 | * + Property "dsp": enable DSP (forwarded to CPU object) | ||
39 | * + Property "enable-bitband": expose bitbanded IO | ||
40 | + * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded | ||
41 | + * to CPU object pmsav7-dregion property; default is whatever the default | ||
42 | + * for the CPU is) | ||
43 | + * + Property "mpu-s-regions": number of Secure MPU regions (default is | ||
44 | + * whatever the default for the CPU is; must currently be set to the same | ||
45 | + * value as mpu-ns-regions if the CPU implements the Security Extension) | ||
46 | * + Clock input "refclk" is the external reference clock for the systick timers | ||
47 | * + Clock input "cpuclk" is the main CPU clock | ||
48 | */ | ||
49 | @@ -XXX,XX +XXX,XX @@ struct ARMv7MState { | ||
50 | Object *idau; | ||
51 | uint32_t init_svtor; | ||
52 | uint32_t init_nsvtor; | ||
53 | + uint32_t mpu_ns_regions; | ||
54 | + uint32_t mpu_s_regions; | ||
55 | bool enable_bitband; | ||
56 | bool start_powered_off; | ||
57 | bool vfp; | ||
58 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/hw/arm/armv7m.c | ||
61 | +++ b/hw/arm/armv7m.c | ||
62 | @@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp) | ||
63 | } | ||
19 | } | 64 | } |
20 | } | 65 | |
21 | 66 | + /* | |
22 | +static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info) | 67 | + * Real M-profile hardware can be configured with a different number of |
23 | +{ | 68 | + * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't |
24 | + /* Set up for booting firmware (which might load a kernel via fw_cfg) */ | 69 | + * support that yet, so catch attempts to select that. |
25 | + | 70 | + */ |
26 | + if (have_dtb(info)) { | 71 | + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && |
27 | + /* | 72 | + s->mpu_ns_regions != s->mpu_s_regions) { |
28 | + * If we have a device tree blob, but no kernel to supply it to (or | 73 | + error_setg(errp, |
29 | + * the kernel is supposed to be loaded by the bootloader), copy the | 74 | + "mpu-ns-regions and mpu-s-regions properties must have the same value"); |
30 | + * DTB to the base of RAM for the bootloader to pick up. | 75 | + return; |
31 | + */ | ||
32 | + info->dtb_start = info->loader_start; | ||
33 | + } | 76 | + } |
34 | + | 77 | + if (s->mpu_ns_regions != UINT_MAX && |
35 | + if (info->kernel_filename) { | 78 | + object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) { |
36 | + FWCfgState *fw_cfg; | 79 | + if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion", |
37 | + bool try_decompressing_kernel; | 80 | + s->mpu_ns_regions, errp)) { |
38 | + | 81 | + return; |
39 | + fw_cfg = fw_cfg_find(); | ||
40 | + try_decompressing_kernel = arm_feature(&cpu->env, | ||
41 | + ARM_FEATURE_AARCH64); | ||
42 | + | ||
43 | + /* | ||
44 | + * Expose the kernel, the command line, and the initrd in fw_cfg. | ||
45 | + * We don't process them here at all, it's all left to the | ||
46 | + * firmware. | ||
47 | + */ | ||
48 | + load_image_to_fw_cfg(fw_cfg, | ||
49 | + FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, | ||
50 | + info->kernel_filename, | ||
51 | + try_decompressing_kernel); | ||
52 | + load_image_to_fw_cfg(fw_cfg, | ||
53 | + FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, | ||
54 | + info->initrd_filename, false); | ||
55 | + | ||
56 | + if (info->kernel_cmdline) { | ||
57 | + fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | ||
58 | + strlen(info->kernel_cmdline) + 1); | ||
59 | + fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | ||
60 | + info->kernel_cmdline); | ||
61 | + } | 82 | + } |
62 | + } | 83 | + } |
63 | + | 84 | + |
64 | + /* | 85 | /* |
65 | + * We will start from address 0 (typically a boot ROM image) in the | 86 | * Tell the CPU where the NVIC is; it will fail realize if it doesn't |
66 | + * same way as hardware. | 87 | * have one. Similarly, tell the NVIC where its CPU is. |
67 | + */ | 88 | @@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = { |
68 | +} | 89 | false), |
69 | + | 90 | DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true), |
70 | void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | 91 | DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), |
71 | { | 92 | + DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX), |
72 | CPUState *cs; | 93 | + DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX), |
73 | @@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) | 94 | DEFINE_PROP_END_OF_LIST(), |
74 | 95 | }; | |
75 | /* Load the kernel. */ | 96 | |
76 | if (!info->kernel_filename || info->firmware_loaded) { | ||
77 | - | ||
78 | - if (have_dtb(info)) { | ||
79 | - /* | ||
80 | - * If we have a device tree blob, but no kernel to supply it to (or | ||
81 | - * the kernel is supposed to be loaded by the bootloader), copy the | ||
82 | - * DTB to the base of RAM for the bootloader to pick up. | ||
83 | - */ | ||
84 | - info->dtb_start = info->loader_start; | ||
85 | - } | ||
86 | - | ||
87 | - if (info->kernel_filename) { | ||
88 | - FWCfgState *fw_cfg; | ||
89 | - bool try_decompressing_kernel; | ||
90 | - | ||
91 | - fw_cfg = fw_cfg_find(); | ||
92 | - try_decompressing_kernel = arm_feature(&cpu->env, | ||
93 | - ARM_FEATURE_AARCH64); | ||
94 | - | ||
95 | - /* | ||
96 | - * Expose the kernel, the command line, and the initrd in fw_cfg. | ||
97 | - * We don't process them here at all, it's all left to the | ||
98 | - * firmware. | ||
99 | - */ | ||
100 | - load_image_to_fw_cfg(fw_cfg, | ||
101 | - FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, | ||
102 | - info->kernel_filename, | ||
103 | - try_decompressing_kernel); | ||
104 | - load_image_to_fw_cfg(fw_cfg, | ||
105 | - FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, | ||
106 | - info->initrd_filename, false); | ||
107 | - | ||
108 | - if (info->kernel_cmdline) { | ||
109 | - fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, | ||
110 | - strlen(info->kernel_cmdline) + 1); | ||
111 | - fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, | ||
112 | - info->kernel_cmdline); | ||
113 | - } | ||
114 | - } | ||
115 | - | ||
116 | - /* | ||
117 | - * We will start from address 0 (typically a boot ROM image) in the | ||
118 | - * same way as hardware. | ||
119 | - */ | ||
120 | + arm_setup_firmware_boot(cpu, info); | ||
121 | return; | ||
122 | } else { | ||
123 | arm_setup_direct_kernel_boot(cpu, info); | ||
124 | -- | 97 | -- |
125 | 2.20.1 | 98 | 2.34.1 |
126 | 99 | ||
127 | 100 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The |
---|---|---|---|
2 | 2 | MPS2/MPS3 FPGA images don't override these except in the case of | |
3 | This will allow TBI to be used in user-only mode, as well as | 3 | AN547, which uses 16 MPU regions. |
4 | avoid ping-ponging the softmmu TLB when TBI is in use. It | 4 | |
5 | will also enable other armv8 extensions. | 5 | Define properties on the ARMSSE object for the MPU regions (using the |
6 | 6 | same names as the documented RTL configuration settings, and | |
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 7 | following the pattern we already have for this device of using |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | all-caps names as the RTL does), and set them in the board code. |
9 | Message-id: 20190204132126.3255-3-richard.henderson@linaro.org | 9 | |
10 | We don't actually need to override the default except on AN547, | ||
11 | but it's simpler code to have the board code set them always | ||
12 | rather than tracking which board subtypes want to set them to | ||
13 | a non-default value separately from what that value is. | ||
14 | |||
15 | Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524 | ||
16 | we now correctly use 8 MPU regions, while mps3-an547 stays at its | ||
17 | current 16 regions. | ||
18 | |||
19 | It's possible some guest code wrongly depended on the previous | ||
20 | incorrectly modeled number of memory regions. (Such guest code | ||
21 | should ideally check the number of regions via the MPU_TYPE | ||
22 | register.) The old behaviour can be obtained with additional | ||
23 | -global arguments to QEMU: | ||
24 | |||
25 | For mps2-an521 and mps2-an524: | ||
26 | -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16 | ||
27 | |||
28 | For mps2-an505: | ||
29 | -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 | ||
30 | |||
31 | NB that the way the implementation allows this use of -global | ||
32 | is slightly fragile: if the board code explicitly sets the | ||
33 | properties on the sse-200 object, this overrides the -global | ||
34 | command line option. So we rely on: | ||
35 | - the boards that need fixing all happen to use the SSE defaults | ||
36 | - we can write the board code to only set the property if it | ||
37 | is different from the default, rather than having all boards | ||
38 | explicitly set the property | ||
39 | - the board that does need to use a non-default value happens | ||
40 | to need to set it to the same value (16) we previously used | ||
41 | This works, but there are some kinds of refactoring of the | ||
42 | mps2-tz.c code that would break the support for -global here. | ||
43 | |||
44 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 45 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
46 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
47 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
48 | Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org | ||
11 | --- | 49 | --- |
12 | target/arm/translate-a64.c | 217 ++++++++++++++++++++----------------- | 50 | include/hw/arm/armsse.h | 5 +++++ |
13 | 1 file changed, 116 insertions(+), 101 deletions(-) | 51 | hw/arm/armsse.c | 16 ++++++++++++++++ |
14 | 52 | hw/arm/mps2-tz.c | 29 +++++++++++++++++++++++++++++ | |
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 53 | 3 files changed, 50 insertions(+) |
54 | |||
55 | diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | 56 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.c | 57 | --- a/include/hw/arm/armsse.h |
18 | +++ b/target/arm/translate-a64.c | 58 | +++ b/include/hw/arm/armsse.h |
19 | @@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) | 59 | @@ -XXX,XX +XXX,XX @@ |
20 | gen_top_byte_ignore(s, cpu_pc, src, s->tbii); | 60 | * (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an |
21 | } | 61 | * SSE-200 both are present; CPU0 in an SSE-200 has neither. |
22 | 62 | * Since the IoTKit has only one CPU, it does not have the CPU1_* properties. | |
23 | +/* | 63 | + * + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S" |
24 | + * Return a "clean" address for ADDR according to TBID. | 64 | + * which set the number of MPU regions on the CPUs. If there is only one |
25 | + * This is always a fresh temporary, as we need to be able to | 65 | + * CPU the CPU1 properties are not present. |
26 | + * increment this independently of a dirty write-back address. | 66 | * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, |
27 | + */ | 67 | * which are wired to its NVIC lines 32 .. n+32 |
28 | +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) | 68 | * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for |
29 | +{ | 69 | @@ -XXX,XX +XXX,XX @@ struct ARMSSE { |
30 | + TCGv_i64 clean = new_tmp_a64(s); | 70 | uint32_t exp_numirq; |
31 | + gen_top_byte_ignore(s, clean, addr, s->tbid); | 71 | uint32_t sram_addr_width; |
32 | + return clean; | 72 | uint32_t init_svtor; |
33 | +} | 73 | + uint32_t cpu_mpu_ns[SSE_MAX_CPUS]; |
34 | + | 74 | + uint32_t cpu_mpu_s[SSE_MAX_CPUS]; |
35 | typedef struct DisasCompare64 { | 75 | bool cpu_fpu[SSE_MAX_CPUS]; |
36 | TCGCond cond; | 76 | bool cpu_dsp[SSE_MAX_CPUS]; |
37 | TCGv_i64 value; | 77 | }; |
38 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt, | 78 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c |
39 | TCGv_i64 tcg_rs = cpu_reg(s, rs); | 79 | index XXXXXXX..XXXXXXX 100644 |
40 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | 80 | --- a/hw/arm/armsse.c |
41 | int memidx = get_mem_index(s); | 81 | +++ b/hw/arm/armsse.c |
42 | - TCGv_i64 addr = cpu_reg_sp(s, rn); | 82 | @@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = { |
43 | + TCGv_i64 clean_addr; | 83 | DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), |
44 | 84 | DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), | |
45 | if (rn == 31) { | 85 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), |
46 | gen_check_sp_alignment(s); | 86 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), |
47 | } | 87 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), |
48 | - tcg_gen_atomic_cmpxchg_i64(tcg_rs, addr, tcg_rs, tcg_rt, memidx, | 88 | DEFINE_PROP_END_OF_LIST() |
49 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | 89 | }; |
50 | + tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, | 90 | |
51 | size | MO_ALIGN | s->be_data); | 91 | @@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = { |
52 | } | 92 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false), |
53 | 93 | DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true), | |
54 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | 94 | DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true), |
55 | TCGv_i64 s2 = cpu_reg(s, rs + 1); | 95 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), |
56 | TCGv_i64 t1 = cpu_reg(s, rt); | 96 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), |
57 | TCGv_i64 t2 = cpu_reg(s, rt + 1); | 97 | + DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8), |
58 | - TCGv_i64 addr = cpu_reg_sp(s, rn); | 98 | + DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8), |
59 | + TCGv_i64 clean_addr; | 99 | DEFINE_PROP_END_OF_LIST() |
60 | int memidx = get_mem_index(s); | 100 | }; |
61 | 101 | ||
62 | if (rn == 31) { | 102 | @@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = { |
63 | gen_check_sp_alignment(s); | 103 | DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000), |
64 | } | 104 | DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true), |
65 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | 105 | DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), |
66 | 106 | + DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), | |
67 | if (size == 2) { | 107 | + DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), |
68 | TCGv_i64 cmp = tcg_temp_new_i64(); | 108 | DEFINE_PROP_END_OF_LIST() |
69 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | 109 | }; |
70 | tcg_gen_concat32_i64(cmp, s2, s1); | 110 | |
71 | } | 111 | @@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp) |
72 | 112 | return; | |
73 | - tcg_gen_atomic_cmpxchg_i64(cmp, addr, cmp, val, memidx, | ||
74 | + tcg_gen_atomic_cmpxchg_i64(cmp, clean_addr, cmp, val, memidx, | ||
75 | MO_64 | MO_ALIGN | s->be_data); | ||
76 | tcg_temp_free_i64(val); | ||
77 | |||
78 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
79 | if (HAVE_CMPXCHG128) { | ||
80 | TCGv_i32 tcg_rs = tcg_const_i32(rs); | ||
81 | if (s->be_data == MO_LE) { | ||
82 | - gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2); | ||
83 | + gen_helper_casp_le_parallel(cpu_env, tcg_rs, | ||
84 | + clean_addr, t1, t2); | ||
85 | } else { | ||
86 | - gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2); | ||
87 | + gen_helper_casp_be_parallel(cpu_env, tcg_rs, | ||
88 | + clean_addr, t1, t2); | ||
89 | } | ||
90 | tcg_temp_free_i32(tcg_rs); | ||
91 | } else { | ||
92 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
93 | TCGv_i64 zero = tcg_const_i64(0); | ||
94 | |||
95 | /* Load the two words, in memory order. */ | ||
96 | - tcg_gen_qemu_ld_i64(d1, addr, memidx, | ||
97 | + tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, | ||
98 | MO_64 | MO_ALIGN_16 | s->be_data); | ||
99 | - tcg_gen_addi_i64(a2, addr, 8); | ||
100 | - tcg_gen_qemu_ld_i64(d2, addr, memidx, MO_64 | s->be_data); | ||
101 | + tcg_gen_addi_i64(a2, clean_addr, 8); | ||
102 | + tcg_gen_qemu_ld_i64(d2, clean_addr, memidx, MO_64 | s->be_data); | ||
103 | |||
104 | /* Compare the two words, also in memory order. */ | ||
105 | tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); | ||
106 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | ||
107 | /* If compare equal, write back new data, else write back old data. */ | ||
108 | tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); | ||
109 | tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); | ||
110 | - tcg_gen_qemu_st_i64(c1, addr, memidx, MO_64 | s->be_data); | ||
111 | + tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); | ||
112 | tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); | ||
113 | tcg_temp_free_i64(a2); | ||
114 | tcg_temp_free_i64(c1); | ||
115 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
116 | int is_lasr = extract32(insn, 15, 1); | ||
117 | int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr; | ||
118 | int size = extract32(insn, 30, 2); | ||
119 | - TCGv_i64 tcg_addr; | ||
120 | + TCGv_i64 clean_addr; | ||
121 | |||
122 | switch (o2_L_o1_o0) { | ||
123 | case 0x0: /* STXR */ | ||
124 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
125 | if (is_lasr) { | ||
126 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
127 | } | ||
128 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
129 | - gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, false); | ||
130 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
131 | + gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); | ||
132 | return; | ||
133 | |||
134 | case 0x4: /* LDXR */ | ||
135 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
136 | if (rn == 31) { | ||
137 | gen_check_sp_alignment(s); | ||
138 | } | ||
139 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
140 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
141 | s->is_ldex = true; | ||
142 | - gen_load_exclusive(s, rt, rt2, tcg_addr, size, false); | ||
143 | + gen_load_exclusive(s, rt, rt2, clean_addr, size, false); | ||
144 | if (is_lasr) { | ||
145 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
146 | } | ||
147 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
148 | gen_check_sp_alignment(s); | ||
149 | } | ||
150 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
151 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
152 | - do_gpr_st(s, cpu_reg(s, rt), tcg_addr, size, true, rt, | ||
153 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
154 | + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, | ||
155 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); | ||
156 | return; | ||
157 | |||
158 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
159 | if (rn == 31) { | ||
160 | gen_check_sp_alignment(s); | ||
161 | } | ||
162 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
163 | - do_gpr_ld(s, cpu_reg(s, rt), tcg_addr, size, false, false, true, rt, | ||
164 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
165 | + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, | ||
166 | disas_ldst_compute_iss_sf(size, false, 0), is_lasr); | ||
167 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
168 | return; | ||
169 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
170 | if (is_lasr) { | ||
171 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); | ||
172 | } | ||
173 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
174 | - gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, true); | ||
175 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
176 | + gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); | ||
177 | return; | ||
178 | } | ||
179 | if (rt2 == 31 | ||
180 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) | ||
181 | if (rn == 31) { | ||
182 | gen_check_sp_alignment(s); | ||
183 | } | ||
184 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
185 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
186 | s->is_ldex = true; | ||
187 | - gen_load_exclusive(s, rt, rt2, tcg_addr, size, true); | ||
188 | + gen_load_exclusive(s, rt, rt2, clean_addr, size, true); | ||
189 | if (is_lasr) { | ||
190 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); | ||
191 | } | ||
192 | @@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) | ||
193 | int opc = extract32(insn, 30, 2); | ||
194 | bool is_signed = false; | ||
195 | int size = 2; | ||
196 | - TCGv_i64 tcg_rt, tcg_addr; | ||
197 | + TCGv_i64 tcg_rt, clean_addr; | ||
198 | |||
199 | if (is_vector) { | ||
200 | if (opc == 3) { | ||
201 | @@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) | ||
202 | |||
203 | tcg_rt = cpu_reg(s, rt); | ||
204 | |||
205 | - tcg_addr = tcg_const_i64((s->pc - 4) + imm); | ||
206 | + clean_addr = tcg_const_i64((s->pc - 4) + imm); | ||
207 | if (is_vector) { | ||
208 | - do_fp_ld(s, rt, tcg_addr, size); | ||
209 | + do_fp_ld(s, rt, clean_addr, size); | ||
210 | } else { | ||
211 | /* Only unsigned 32bit loads target 32bit registers. */ | ||
212 | bool iss_sf = opc != 0; | ||
213 | |||
214 | - do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, | ||
215 | + do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false, | ||
216 | true, rt, iss_sf, false); | ||
217 | } | ||
218 | - tcg_temp_free_i64(tcg_addr); | ||
219 | + tcg_temp_free_i64(clean_addr); | ||
220 | } | ||
221 | |||
222 | /* | ||
223 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
224 | bool postindex = false; | ||
225 | bool wback = false; | ||
226 | |||
227 | - TCGv_i64 tcg_addr; /* calculated address */ | ||
228 | + TCGv_i64 clean_addr, dirty_addr; | ||
229 | + | ||
230 | int size; | ||
231 | |||
232 | if (opc == 3) { | ||
233 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
234 | gen_check_sp_alignment(s); | ||
235 | } | ||
236 | |||
237 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
238 | - | ||
239 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
240 | if (!postindex) { | ||
241 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | ||
242 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
243 | } | ||
244 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
245 | |||
246 | if (is_vector) { | ||
247 | if (is_load) { | ||
248 | - do_fp_ld(s, rt, tcg_addr, size); | ||
249 | + do_fp_ld(s, rt, clean_addr, size); | ||
250 | } else { | ||
251 | - do_fp_st(s, rt, tcg_addr, size); | ||
252 | + do_fp_st(s, rt, clean_addr, size); | ||
253 | } | ||
254 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | ||
255 | + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); | ||
256 | if (is_load) { | ||
257 | - do_fp_ld(s, rt2, tcg_addr, size); | ||
258 | + do_fp_ld(s, rt2, clean_addr, size); | ||
259 | } else { | ||
260 | - do_fp_st(s, rt2, tcg_addr, size); | ||
261 | + do_fp_st(s, rt2, clean_addr, size); | ||
262 | } | ||
263 | } else { | ||
264 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
265 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) | ||
266 | /* Do not modify tcg_rt before recognizing any exception | ||
267 | * from the second load. | ||
268 | */ | ||
269 | - do_gpr_ld(s, tmp, tcg_addr, size, is_signed, false, | ||
270 | + do_gpr_ld(s, tmp, clean_addr, size, is_signed, false, | ||
271 | false, 0, false, false); | ||
272 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | ||
273 | - do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false, | ||
274 | + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); | ||
275 | + do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false, | ||
276 | false, 0, false, false); | ||
277 | |||
278 | tcg_gen_mov_i64(tcg_rt, tmp); | ||
279 | tcg_temp_free_i64(tmp); | ||
280 | } else { | ||
281 | - do_gpr_st(s, tcg_rt, tcg_addr, size, | ||
282 | + do_gpr_st(s, tcg_rt, clean_addr, size, | ||
283 | false, 0, false, false); | ||
284 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); | ||
285 | - do_gpr_st(s, tcg_rt2, tcg_addr, size, | ||
286 | + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); | ||
287 | + do_gpr_st(s, tcg_rt2, clean_addr, size, | ||
288 | false, 0, false, false); | ||
289 | } | ||
290 | } | ||
291 | |||
292 | if (wback) { | ||
293 | if (postindex) { | ||
294 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); | ||
295 | - } else { | ||
296 | - tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); | ||
297 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
298 | } | ||
299 | - tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); | ||
300 | + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); | ||
301 | } | ||
302 | } | ||
303 | |||
304 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
305 | bool post_index; | ||
306 | bool writeback; | ||
307 | |||
308 | - TCGv_i64 tcg_addr; | ||
309 | + TCGv_i64 clean_addr, dirty_addr; | ||
310 | |||
311 | if (is_vector) { | ||
312 | size |= (opc & 2) << 1; | ||
313 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
314 | if (rn == 31) { | ||
315 | gen_check_sp_alignment(s); | ||
316 | } | ||
317 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
318 | |||
319 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
320 | if (!post_index) { | ||
321 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | ||
322 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); | ||
323 | } | ||
324 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
325 | |||
326 | if (is_vector) { | ||
327 | if (is_store) { | ||
328 | - do_fp_st(s, rt, tcg_addr, size); | ||
329 | + do_fp_st(s, rt, clean_addr, size); | ||
330 | } else { | ||
331 | - do_fp_ld(s, rt, tcg_addr, size); | ||
332 | + do_fp_ld(s, rt, clean_addr, size); | ||
333 | } | ||
334 | } else { | ||
335 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
336 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
337 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | ||
338 | |||
339 | if (is_store) { | ||
340 | - do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx, | ||
341 | + do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx, | ||
342 | iss_valid, rt, iss_sf, false); | ||
343 | } else { | ||
344 | - do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, | ||
345 | + do_gpr_ld_memidx(s, tcg_rt, clean_addr, size, | ||
346 | is_signed, is_extended, memidx, | ||
347 | iss_valid, rt, iss_sf, false); | ||
348 | } | ||
349 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, | ||
350 | if (writeback) { | ||
351 | TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); | ||
352 | if (post_index) { | ||
353 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); | ||
354 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); | ||
355 | } | ||
356 | - tcg_gen_mov_i64(tcg_rn, tcg_addr); | ||
357 | + tcg_gen_mov_i64(tcg_rn, dirty_addr); | ||
358 | } | ||
359 | } | ||
360 | |||
361 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, | ||
362 | bool is_store = false; | ||
363 | bool is_extended = false; | ||
364 | |||
365 | - TCGv_i64 tcg_rm; | ||
366 | - TCGv_i64 tcg_addr; | ||
367 | + TCGv_i64 tcg_rm, clean_addr, dirty_addr; | ||
368 | |||
369 | if (extract32(opt, 1, 1) == 0) { | ||
370 | unallocated_encoding(s); | ||
371 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, | ||
372 | if (rn == 31) { | ||
373 | gen_check_sp_alignment(s); | ||
374 | } | ||
375 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
376 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
377 | |||
378 | tcg_rm = read_cpu_reg(s, rm, 1); | ||
379 | ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); | ||
380 | |||
381 | - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); | ||
382 | + tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); | ||
383 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
384 | |||
385 | if (is_vector) { | ||
386 | if (is_store) { | ||
387 | - do_fp_st(s, rt, tcg_addr, size); | ||
388 | + do_fp_st(s, rt, clean_addr, size); | ||
389 | } else { | ||
390 | - do_fp_ld(s, rt, tcg_addr, size); | ||
391 | + do_fp_ld(s, rt, clean_addr, size); | ||
392 | } | ||
393 | } else { | ||
394 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
395 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | ||
396 | if (is_store) { | ||
397 | - do_gpr_st(s, tcg_rt, tcg_addr, size, | ||
398 | + do_gpr_st(s, tcg_rt, clean_addr, size, | ||
399 | true, rt, iss_sf, false); | ||
400 | } else { | ||
401 | - do_gpr_ld(s, tcg_rt, tcg_addr, size, | ||
402 | + do_gpr_ld(s, tcg_rt, clean_addr, size, | ||
403 | is_signed, is_extended, | ||
404 | true, rt, iss_sf, false); | ||
405 | } | ||
406 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, | ||
407 | unsigned int imm12 = extract32(insn, 10, 12); | ||
408 | unsigned int offset; | ||
409 | |||
410 | - TCGv_i64 tcg_addr; | ||
411 | + TCGv_i64 clean_addr, dirty_addr; | ||
412 | |||
413 | bool is_store; | ||
414 | bool is_signed = false; | ||
415 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, | ||
416 | if (rn == 31) { | ||
417 | gen_check_sp_alignment(s); | ||
418 | } | ||
419 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
420 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
421 | offset = imm12 << size; | ||
422 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | ||
423 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
424 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
425 | |||
426 | if (is_vector) { | ||
427 | if (is_store) { | ||
428 | - do_fp_st(s, rt, tcg_addr, size); | ||
429 | + do_fp_st(s, rt, clean_addr, size); | ||
430 | } else { | ||
431 | - do_fp_ld(s, rt, tcg_addr, size); | ||
432 | + do_fp_ld(s, rt, clean_addr, size); | ||
433 | } | ||
434 | } else { | ||
435 | TCGv_i64 tcg_rt = cpu_reg(s, rt); | ||
436 | bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); | ||
437 | if (is_store) { | ||
438 | - do_gpr_st(s, tcg_rt, tcg_addr, size, | ||
439 | + do_gpr_st(s, tcg_rt, clean_addr, size, | ||
440 | true, rt, iss_sf, false); | ||
441 | } else { | ||
442 | - do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended, | ||
443 | + do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended, | ||
444 | true, rt, iss_sf, false); | ||
445 | } | ||
446 | } | ||
447 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
448 | int rs = extract32(insn, 16, 5); | ||
449 | int rn = extract32(insn, 5, 5); | ||
450 | int o3_opc = extract32(insn, 12, 4); | ||
451 | - TCGv_i64 tcg_rn, tcg_rs; | ||
452 | + TCGv_i64 tcg_rs, clean_addr; | ||
453 | AtomicThreeOpFn *fn; | ||
454 | |||
455 | if (is_vector || !dc_isar_feature(aa64_atomics, s)) { | ||
456 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
457 | if (rn == 31) { | ||
458 | gen_check_sp_alignment(s); | ||
459 | } | ||
460 | - tcg_rn = cpu_reg_sp(s, rn); | ||
461 | + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); | ||
462 | tcg_rs = read_cpu_reg(s, rs, true); | ||
463 | |||
464 | if (o3_opc == 1) { /* LDCLR */ | ||
465 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, | ||
466 | /* The tcg atomic primitives are all full barriers. Therefore we | ||
467 | * can ignore the Acquire and Release bits of this instruction. | ||
468 | */ | ||
469 | - fn(cpu_reg(s, rt), tcg_rn, tcg_rs, get_mem_index(s), | ||
470 | + fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), | ||
471 | s->be_data | size | MO_ALIGN); | ||
472 | } | ||
473 | |||
474 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, | ||
475 | bool is_wback = extract32(insn, 11, 1); | ||
476 | bool use_key_a = !extract32(insn, 23, 1); | ||
477 | int offset; | ||
478 | - TCGv_i64 tcg_addr, tcg_rt; | ||
479 | + TCGv_i64 clean_addr, dirty_addr, tcg_rt; | ||
480 | |||
481 | if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { | ||
482 | unallocated_encoding(s); | ||
483 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, | ||
484 | if (rn == 31) { | ||
485 | gen_check_sp_alignment(s); | ||
486 | } | ||
487 | - tcg_addr = read_cpu_reg_sp(s, rn, 1); | ||
488 | + dirty_addr = read_cpu_reg_sp(s, rn, 1); | ||
489 | |||
490 | if (s->pauth_active) { | ||
491 | if (use_key_a) { | ||
492 | - gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); | ||
493 | + gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); | ||
494 | } else { | ||
495 | - gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]); | ||
496 | + gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); | ||
497 | } | ||
498 | } | ||
499 | |||
500 | /* Form the 10-bit signed, scaled offset. */ | ||
501 | offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); | ||
502 | offset = sextract32(offset << size, 0, 10 + size); | ||
503 | - tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); | ||
504 | + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); | ||
505 | + | ||
506 | + /* Note that "clean" and "dirty" here refer to TBI not PAC. */ | ||
507 | + clean_addr = clean_data_tbi(s, dirty_addr); | ||
508 | |||
509 | tcg_rt = cpu_reg(s, rt); | ||
510 | - | ||
511 | - do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false, | ||
512 | + do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, | ||
513 | /* extend */ false, /* iss_valid */ !is_wback, | ||
514 | /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); | ||
515 | |||
516 | if (is_wback) { | ||
517 | - tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); | ||
518 | + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); | ||
519 | } | ||
520 | } | ||
521 | |||
522 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
523 | bool is_store = !extract32(insn, 22, 1); | ||
524 | bool is_postidx = extract32(insn, 23, 1); | ||
525 | bool is_q = extract32(insn, 30, 1); | ||
526 | - TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; | ||
527 | + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; | ||
528 | TCGMemOp endian = s->be_data; | ||
529 | |||
530 | int ebytes; /* bytes per element */ | ||
531 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
532 | elements = (is_q ? 16 : 8) / ebytes; | ||
533 | |||
534 | tcg_rn = cpu_reg_sp(s, rn); | ||
535 | - tcg_addr = tcg_temp_new_i64(); | ||
536 | - tcg_gen_mov_i64(tcg_addr, tcg_rn); | ||
537 | + clean_addr = clean_data_tbi(s, tcg_rn); | ||
538 | tcg_ebytes = tcg_const_i64(ebytes); | ||
539 | |||
540 | for (r = 0; r < rpt; r++) { | ||
541 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | ||
542 | for (xs = 0; xs < selem; xs++) { | ||
543 | int tt = (rt + r + xs) % 32; | ||
544 | if (is_store) { | ||
545 | - do_vec_st(s, tt, e, tcg_addr, size, endian); | ||
546 | + do_vec_st(s, tt, e, clean_addr, size, endian); | ||
547 | } else { | ||
548 | - do_vec_ld(s, tt, e, tcg_addr, size, endian); | ||
549 | + do_vec_ld(s, tt, e, clean_addr, size, endian); | ||
550 | } | ||
551 | - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); | ||
552 | + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); | ||
553 | } | 113 | } |
554 | } | 114 | } |
555 | } | 115 | + if (!object_property_set_uint(cpuobj, "mpu-ns-regions", |
556 | + tcg_temp_free_i64(tcg_ebytes); | 116 | + s->cpu_mpu_ns[i], errp)) { |
557 | 117 | + return; | |
558 | if (!is_store) { | 118 | + } |
559 | /* For non-quad operations, setting a slice of the low | 119 | + if (!object_property_set_uint(cpuobj, "mpu-s-regions", |
560 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) | 120 | + s->cpu_mpu_s[i], errp)) { |
561 | 121 | + return; | |
562 | if (is_postidx) { | 122 | + } |
563 | if (rm == 31) { | 123 | |
564 | - tcg_gen_mov_i64(tcg_rn, tcg_addr); | 124 | if (i > 0) { |
565 | + tcg_gen_addi_i64(tcg_rn, tcg_rn, rpt * elements * selem * ebytes); | 125 | memory_region_add_subregion_overlap(&s->cpu_container[i], 0, |
566 | } else { | 126 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c |
567 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | 127 | index XXXXXXX..XXXXXXX 100644 |
568 | } | 128 | --- a/hw/arm/mps2-tz.c |
569 | } | 129 | +++ b/hw/arm/mps2-tz.c |
570 | - tcg_temp_free_i64(tcg_ebytes); | 130 | @@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass { |
571 | - tcg_temp_free_i64(tcg_addr); | 131 | int uart_overflow_irq; /* number of the combined UART overflow IRQ */ |
132 | uint32_t init_svtor; /* init-svtor setting for SSE */ | ||
133 | uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */ | ||
134 | + uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */ | ||
135 | + uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */ | ||
136 | + uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */ | ||
137 | + uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */ | ||
138 | const RAMInfo *raminfo; | ||
139 | const char *armsse_type; | ||
140 | uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */ | ||
141 | @@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) | ||
142 | #define MPS3_DDR_SIZE (2 * GiB) | ||
143 | #endif | ||
144 | |||
145 | +/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */ | ||
146 | +#define MPU_REGION_DEFAULT UINT32_MAX | ||
147 | + | ||
148 | static const uint32_t an505_oscclk[] = { | ||
149 | 40000000, | ||
150 | 24580000, | ||
151 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine) | ||
152 | OBJECT(system_memory), &error_abort); | ||
153 | qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); | ||
154 | qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor); | ||
155 | + if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) { | ||
156 | + qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns); | ||
157 | + } | ||
158 | + if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) { | ||
159 | + qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s); | ||
160 | + } | ||
161 | + if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) { | ||
162 | + if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) { | ||
163 | + qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns); | ||
164 | + } | ||
165 | + if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) { | ||
166 | + qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s); | ||
167 | + } | ||
168 | + } | ||
169 | qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width); | ||
170 | qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); | ||
171 | qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); | ||
172 | @@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data) | ||
173 | { | ||
174 | MachineClass *mc = MACHINE_CLASS(oc); | ||
175 | IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc); | ||
176 | + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); | ||
177 | |||
178 | mc->init = mps2tz_common_init; | ||
179 | mc->reset = mps2_machine_reset; | ||
180 | iic->check = mps2_tz_idau_check; | ||
181 | + | ||
182 | + /* Most machines leave these at the SSE defaults */ | ||
183 | + mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT; | ||
184 | + mmc->cpu0_mpu_s = MPU_REGION_DEFAULT; | ||
185 | + mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT; | ||
186 | + mmc->cpu1_mpu_s = MPU_REGION_DEFAULT; | ||
572 | } | 187 | } |
573 | 188 | ||
574 | /* AdvSIMD load/store single structure | 189 | static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) |
575 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | 190 | @@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data) |
576 | bool replicate = false; | 191 | mmc->numirq = 96; |
577 | int index = is_q << 3 | S << 2 | size; | 192 | mmc->uart_overflow_irq = 48; |
578 | int ebytes, xs; | 193 | mmc->init_svtor = 0x00000000; |
579 | - TCGv_i64 tcg_addr, tcg_rn, tcg_ebytes; | 194 | + mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16; |
580 | + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; | 195 | mmc->sram_addr_width = 21; |
581 | 196 | mmc->raminfo = an547_raminfo; | |
582 | if (extract32(insn, 31, 1)) { | 197 | mmc->armsse_type = TYPE_SSE300; |
583 | unallocated_encoding(s); | ||
584 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | ||
585 | } | ||
586 | |||
587 | tcg_rn = cpu_reg_sp(s, rn); | ||
588 | - tcg_addr = tcg_temp_new_i64(); | ||
589 | - tcg_gen_mov_i64(tcg_addr, tcg_rn); | ||
590 | + clean_addr = clean_data_tbi(s, tcg_rn); | ||
591 | tcg_ebytes = tcg_const_i64(ebytes); | ||
592 | |||
593 | for (xs = 0; xs < selem; xs++) { | ||
594 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | ||
595 | /* Load and replicate to all elements */ | ||
596 | TCGv_i64 tcg_tmp = tcg_temp_new_i64(); | ||
597 | |||
598 | - tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, | ||
599 | + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, | ||
600 | get_mem_index(s), s->be_data + scale); | ||
601 | tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), | ||
602 | (is_q + 1) * 8, vec_full_reg_size(s), | ||
603 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) | ||
604 | } else { | ||
605 | /* Load/store one element per register */ | ||
606 | if (is_load) { | ||
607 | - do_vec_ld(s, rt, index, tcg_addr, scale, s->be_data); | ||
608 | + do_vec_ld(s, rt, index, clean_addr, scale, s->be_data); | ||
609 | } else { | ||
610 | - do_vec_st(s, rt, index, tcg_addr, scale, s->be_data); | ||
611 | + do_vec_st(s, rt, index, clean_addr, scale, s->be_data); | ||
612 | } | ||
613 | } | ||
614 | - tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_ebytes); | ||
615 | + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); | ||
616 | rt = (rt + 1) % 32; | ||
617 | } | ||
618 | + tcg_temp_free_i64(tcg_ebytes); | ||
619 | |||
620 | if (is_postidx) { | ||
621 | if (rm == 31) { | ||
622 | - tcg_gen_mov_i64(tcg_rn, tcg_addr); | ||
623 | + tcg_gen_addi_i64(tcg_rn, tcg_rn, selem * ebytes); | ||
624 | } else { | ||
625 | tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); | ||
626 | } | ||
627 | } | ||
628 | - tcg_temp_free_i64(tcg_ebytes); | ||
629 | - tcg_temp_free_i64(tcg_addr); | ||
630 | } | ||
631 | |||
632 | /* Loads and stores */ | ||
633 | -- | 198 | -- |
634 | 2.20.1 | 199 | 2.34.1 |
635 | 200 | ||
636 | 201 | diff view generated by jsdifflib |