[Qemu-devel] [PATCH v9 00/14] More fully implement ARM PMUv3

Aaron Lindsay posted 14 patches 1 week ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/20181205134243.4791-1-aaron@os.amperecomputing.com
docs/devel/migration.rst    |   9 +-
include/migration/vmstate.h |   1 +
migration/vmstate.c         |  13 +-
target/arm/cpu.c            |  28 +-
target/arm/cpu.h            |  79 +++-
target/arm/cpu64.c          |   4 -
target/arm/helper.c         | 807 ++++++++++++++++++++++++++++++++----
target/arm/machine.c        |  24 ++
8 files changed, 860 insertions(+), 105 deletions(-)

[Qemu-devel] [PATCH v9 00/14] More fully implement ARM PMUv3

Posted by Aaron Lindsay 1 week ago
The ARM PMU implementation currently contains a basic cycle counter, but
it is often useful to gather counts of other events, filter them based
on execution mode, and/or be notified on counter overflow. These patches
flesh out the implementations of various PMU registers including
PM[X]EVCNTR and PM[X]EVTYPER, add a struct definition to represent
arbitrary counter types, implement mode filtering, send interrupts on
counter overflow, and add instruction, cycle, and software increment
events.

Since v8 [1] I have made the following changes:
* Simplified if statements and corrected overflow bit clearing logic in
  counter overflow patch based on Richard's review
* Added FIELDs for ARMv8.1 PMUv3 variant and guard the definition of
  PMCEID2 and PMCEID3 based on ID_DFR0.PerfMon
* Added/fixed up a couple comments

[1] - https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg04037.html

Aaron Lindsay (14):
  migration: Add post_save function to VMStateDescription
  target/arm: Reorganize PMCCNTR accesses
  target/arm: Swap PMU values before/after migrations
  target/arm: Filter cycle counter based on PMCCFILTR_EL0
  target/arm: Allow AArch32 access for PMCCFILTR
  target/arm: Implement PMOVSSET
  target/arm: Define FIELDs for ID_DFR0
  target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
  target/arm: Add array for supported PMU events, generate
    PMCEID[01]_EL0
  target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
  target/arm: PMU: Add instruction and cycle events
  target/arm: PMU: Set PMCR.N to 4
  target/arm: Implement PMSWINC
  target/arm: Send interrupts on PMU counter overflow

 docs/devel/migration.rst    |   9 +-
 include/migration/vmstate.h |   1 +
 migration/vmstate.c         |  13 +-
 target/arm/cpu.c            |  28 +-
 target/arm/cpu.h            |  79 +++-
 target/arm/cpu64.c          |   4 -
 target/arm/helper.c         | 807 ++++++++++++++++++++++++++++++++----
 target/arm/machine.c        |  24 ++
 8 files changed, 860 insertions(+), 105 deletions(-)

-- 
2.19.1