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charset="utf-8" In some cases it may be helpful to modify state before saving it for migration, and then modify the state back after it has been saved. The existing pre_save function provides half of this functionality. This patch adds a post_save function to provide the second half. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Dr. David Alan Gilbert --- docs/devel/migration.rst | 9 +++++++-- include/migration/vmstate.h | 1 + migration/vmstate.c | 13 ++++++++++++- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/docs/devel/migration.rst b/docs/devel/migration.rst index e7658ab050..220059679a 100644 --- a/docs/devel/migration.rst +++ b/docs/devel/migration.rst @@ -419,8 +419,13 @@ The functions to do that are inside a vmstate definiti= on, and are called: =20 This function is called before we save the state of one device. =20 -Example: You can look at hpet.c, that uses the three function to -massage the state that is transferred. +- ``int (*post_save)(void *opaque);`` + + This function is called after we save the state of one device + (even upon failure, unless the call to pre_save returned an error). + +Example: You can look at hpet.c, that uses the first three functions +to massage the state that is transferred. =20 The ``VMSTATE_WITH_TMP`` macro may be useful when the migration data doesn't match the stored device data well; it allows an diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 61bef3ef5c..067b126cf1 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -185,6 +185,7 @@ struct VMStateDescription { int (*pre_load)(void *opaque); int (*post_load)(void *opaque, int version_id); int (*pre_save)(void *opaque); + int (*post_save)(void *opaque); bool (*needed)(void *opaque); const VMStateField *fields; const VMStateDescription **subsections; diff --git a/migration/vmstate.c b/migration/vmstate.c index 80b59009aa..e2bbb7b5f7 100644 --- a/migration/vmstate.c +++ b/migration/vmstate.c @@ -390,6 +390,9 @@ int vmstate_save_state_v(QEMUFile *f, const VMStateDesc= ription *vmsd, if (ret) { error_report("Save of field %s/%s failed", vmsd->name, field->name); + if (vmsd->post_save) { + vmsd->post_save(opaque); + } return ret; } =20 @@ -415,7 +418,15 @@ int vmstate_save_state_v(QEMUFile *f, const VMStateDes= cription *vmsd, json_end_array(vmdesc); } =20 - return vmstate_subsection_save(f, vmsd, opaque, vmdesc); + ret =3D vmstate_subsection_save(f, vmsd, opaque, vmdesc); + + if (vmsd->post_save) { + int ps_ret =3D vmsd->post_save(opaque); + if (!ret) { + ret =3D ps_ret; + } + } + return ret; } =20 static const VMStateDescription * --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=os.amperecomputing.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544017543272658.1237081357732; Wed, 5 Dec 2018 05:45:43 -0800 (PST) Received: from localhost ([::1]:34588 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUXUk-0000eZ-3g for importer@patchew.org; Wed, 05 Dec 2018 08:45:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51536) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUXSc-0007aR-Qz for qemu-devel@nongnu.org; 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d=amperemail.onmicrosoft.com; s=selector1-os-amperecomputing-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=S0bKc7YFDFMvux8SAvgL1W3IUxXyEof1Ht5DF6kfXDM=; b=cwJg2d7ScbHmfNSKgQv8d10Xh3DKrctNLTzHUMv5QwosSLDl6+/yjCSwcOH1mCWlZ7cu+iYjDyo9eGWQlFNrwH7NR/e2i9l8Zn1mSVnHSS3m2MDhLrm4gk2AC9ThYdboX1swSw9dXYIbzur0nrYHsqJ5Np7xES6/gJRfUu/sqtI= From: Aaron Lindsay To: "qemu-arm@nongnu.org" , Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite , Richard Henderson Thread-Topic: [PATCH v9 02/14] target/arm: Reorganize PMCCNTR accesses Thread-Index: AQHUjKB5mKwm963mKkGHrg8dNLNrHw== Date: Wed, 5 Dec 2018 13:43:15 +0000 Message-ID: <20181205134243.4791-3-aaron@os.amperecomputing.com> References: <20181205134243.4791-1-aaron@os.amperecomputing.com> In-Reply-To: <20181205134243.4791-1-aaron@os.amperecomputing.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BN6PR12CA0032.namprd12.prod.outlook.com (2603:10b6:405:70::18) To DM6PR01MB4825.prod.exchangelabs.com (2603:10b6:5:6b::30) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aaron@os.amperecomputing.com; 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charset="utf-8" pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. Consolidate the duplicated code into two functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to c15_ccnt in CPUARMState so that we can simultaneously save both the architectural register value and the last underlying cycle count - this ensures time isn't lost and will also allow us to access the 'old' architectural register value in order to detect overflows in later patches. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/cpu.h | 37 ++++++++++---- target/arm/helper.c | 114 +++++++++++++++++++++++++++----------------- 2 files changed, 98 insertions(+), 53 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2a73fed9a0..61ac458627 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -468,10 +468,20 @@ typedef struct CPUARMState { uint64_t oslsr_el1; /* OS Lock Status */ uint64_t mdcr_el2; uint64_t mdcr_el3; - /* If the counter is enabled, this stores the last time the counter - * was reset. Otherwise it stores the counter value + /* Stores the architectural value of the counter *the last time it= was + * updated* by pmccntr_op_start. Accesses should always be surroun= ded + * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest + * architecturally-correct value is being read/set. */ uint64_t c15_ccnt; + /* Stores the delta between the architectural value and the underl= ying + * cycle count during normal operation. It is used to update c15_c= cnt + * to be the correct architectural value before accesses. During + * accesses, c15_ccnt_delta contains the underlying count being us= ed + * for the access, after which it reverts to the delta value in + * pmccntr_op_finish. + */ + uint64_t c15_ccnt_delta; uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register = */ @@ -956,15 +966,26 @@ int cpu_arm_signal_handler(int host_signum, void *pin= fo, void *puc); =20 /** - * pmccntr_sync + * pmccntr_op_start/finish + * @env: CPUARMState + * + * Convert the counter in the PMCCNTR between its delta form (the typical = mode + * when it's enabled) and the guest-visible value. These two calls must al= ways + * surround any action which might affect the counter. + */ +void pmccntr_op_start(CPUARMState *env); +void pmccntr_op_finish(CPUARMState *env); + +/** + * pmu_op_start/finish * @env: CPUARMState * - * Synchronises the counter in the PMCCNTR. This must always be called twi= ce, - * once before any action that might affect the timer and again afterwards. - * The function is used to swap the state of the register if required. - * This only happens when not in user mode (!CONFIG_USER_ONLY) + * Convert all PMU counters between their delta form (the typical mode when + * they are enabled) and the guest-visible values. These two calls must + * surround any action which might affect the counters. */ -void pmccntr_sync(CPUARMState *env); +void pmu_op_start(CPUARMState *env); +void pmu_op_finish(CPUARMState *env); =20 /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants diff --git a/target/arm/helper.c b/target/arm/helper.c index 0da1424f72..497907fc79 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1085,28 +1085,63 @@ static inline bool arm_ccnt_enabled(CPUARMState *en= v) =20 return true; } - -void pmccntr_sync(CPUARMState *env) +/* + * Ensure c15_ccnt is the guest-visible count so that operations such as + * enabling/disabling the counter or filtering, modifying the count itself, + * etc. can be done logically. This is essentially a no-op if the counter = is + * not enabled at the time of the call. + */ +void pmccntr_op_start(CPUARMState *env) { - uint64_t temp_ticks; - - temp_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + uint64_t cycles =3D 0; + cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); =20 - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - temp_ticks /=3D 64; + if (arm_ccnt_enabled(env)) { + uint64_t eff_cycles =3D cycles; + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + eff_cycles /=3D 64; + } + + env->cp15.c15_ccnt =3D eff_cycles - env->cp15.c15_ccnt_delta; } + env->cp15.c15_ccnt_delta =3D cycles; +} =20 +/* + * If PMCCNTR is enabled, recalculate the delta between the clock and the + * guest-visible count. A call to pmccntr_op_finish should follow every ca= ll to + * pmccntr_op_start. + */ +void pmccntr_op_finish(CPUARMState *env) +{ if (arm_ccnt_enabled(env)) { - env->cp15.c15_ccnt =3D temp_ticks - env->cp15.c15_ccnt; + uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; + + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + prev_cycles /=3D 64; + } + + env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; } } =20 +void pmu_op_start(CPUARMState *env) +{ + pmccntr_op_start(env); +} + +void pmu_op_finish(CPUARMState *env) +{ + pmccntr_op_finish(env); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - pmccntr_sync(env); + pmu_op_start(env); =20 if (value & PMCRC) { /* The counter has been reset */ @@ -1117,26 +1152,16 @@ static void pmcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, env->cp15.c9_pmcr &=3D ~0x39; env->cp15.c9_pmcr |=3D (value & 0x39); =20 - pmccntr_sync(env); + pmu_op_finish(env); } =20 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - uint64_t total_ticks; - - if (!arm_ccnt_enabled(env)) { - /* Counter is disabled, do not change value */ - return env->cp15.c15_ccnt; - } - - total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - total_ticks /=3D 64; - } - return total_ticks - env->cp15.c15_ccnt; + uint64_t ret; + pmccntr_op_start(env); + ret =3D env->cp15.c15_ccnt; + pmccntr_op_finish(env); + return ret; } =20 static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1153,22 +1178,9 @@ static void pmselr_write(CPUARMState *env, const ARM= CPRegInfo *ri, static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - uint64_t total_ticks; - - if (!arm_ccnt_enabled(env)) { - /* Counter is disabled, set the absolute value */ - env->cp15.c15_ccnt =3D value; - return; - } - - total_ticks =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); - - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - total_ticks /=3D 64; - } - env->cp15.c15_ccnt =3D total_ticks - value; + pmccntr_op_start(env); + env->cp15.c15_ccnt =3D value; + pmccntr_op_finish(env); } =20 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1181,7 +1193,19 @@ static void pmccntr_write32(CPUARMState *env, const = ARMCPRegInfo *ri, =20 #else /* CONFIG_USER_ONLY */ =20 -void pmccntr_sync(CPUARMState *env) +void pmccntr_op_start(CPUARMState *env) +{ +} + +void pmccntr_op_finish(CPUARMState *env) +{ +} + +void pmu_op_start(CPUARMState *env) +{ +} + +void pmu_op_finish(CPUARMState *env) { } =20 @@ -1190,9 +1214,9 @@ void pmccntr_sync(CPUARMState *env) static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - pmccntr_sync(env); + pmccntr_op_start(env); env->cp15.pmccfiltr_el0 =3D value & 0xfc000000; - pmccntr_sync(env); + pmccntr_op_finish(env); } =20 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR01MB4700; H:DM6PR01MB4825.prod.exchangelabs.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:0; Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 4iOgCPtHKGauX0nzUu6wDD+Eyau6nwWyZV4/UUmdKSwAegHZ5B1HnIGygHU22FYeisoSrN4Ezp1M+DYBkubCOwigEHnvgW5xp7kZ81K95EdPZfO/GyVXoAFVJ3V4cgoeXyepXNYsRn10Gdmf7ITSMKakqJQUMgYBPidKffgnwiJAH3WGYbd0gNnjm2XFm+M9FxH/7kRSwvF/jdtGEJf8OLxRBd9I0Z/xAQRwuKxK1t7rFo9rXIxZT7JAmPAX5eVuemjSQRKH9C+LAWV78ZRWt6ZEmTiJaX7MaqYCOg9+kj4X77U5fHkHNrIs6sRhOJ4NbglaxkPmgeqCS4/Z4vcjNgQRYhyABZT9DJ2uNaVO97c= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 89da6e76-a2cb-4175-eb3f-08d65ab79c58 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Dec 2018 13:43:17.0279 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB4700 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.70.125 Subject: [Qemu-devel] [PATCH v9 03/14] target/arm: Swap PMU values before/after migrations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Aaron Lindsay , Michael Spradling , "qemu-devel@nongnu.org" , Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Because of the PMU's design, many register accesses have side effects which are inter-related, meaning that the normal method of saving CP registers can result in inconsistent state. These side-effects are largely handled in pmu_op_start/finish functions which can be called before and after the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 6 ++++-- target/arm/machine.c | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 497907fc79..71a5c71e0a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1450,11 +1450,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, .type =3D ARM_CP_IO, - .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, }, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, + .raw_readfn =3D raw_read, .raw_writefn =3D raw_write, }, #endif { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, - .writefn =3D pmccfiltr_write, + .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), diff --git a/target/arm/machine.c b/target/arm/machine.c index 7a22ebc209..b292549614 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -620,6 +620,10 @@ static int cpu_pre_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 + if (!kvm_enabled()) { + pmu_op_start(&cpu->env); + } + if (kvm_enabled()) { if (!write_kvmstate_to_list(cpu)) { /* This should never fail */ @@ -641,6 +645,17 @@ static int cpu_pre_save(void *opaque) return 0; } =20 +static int cpu_post_save(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + if (!kvm_enabled()) { + pmu_op_finish(&cpu->env); + } + + return 0; +} + static int cpu_pre_load(void *opaque) { ARMCPU *cpu =3D opaque; @@ -653,6 +668,10 @@ static int cpu_pre_load(void *opaque) */ env->irq_line_state =3D UINT32_MAX; =20 + if (!kvm_enabled()) { + pmu_op_start(&cpu->env); + } + return 0; } =20 @@ -721,6 +740,10 @@ static int cpu_post_load(void *opaque, int version_id) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); =20 + if (!kvm_enabled()) { + pmu_op_finish(&cpu->env); + } + return 0; } =20 @@ -729,6 +752,7 @@ const VMStateDescription vmstate_arm_cpu =3D { .version_id =3D 22, .minimum_version_id =3D 22, .pre_save =3D cpu_pre_save, + .post_save =3D cpu_post_save, .pre_load =3D cpu_pre_load, .post_load =3D cpu_post_load, .fields =3D (VMStateField[]) { --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only return 'true' if the specified counter is enabled and neither prohibited or filtered. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 ++ target/arm/cpu.h | 10 ++++- target/arm/helper.c | 96 +++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 101 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 60411f6bfe..f7bad04f60 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1020,6 +1020,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) if (!cpu->has_pmu) { unset_feature(env, ARM_FEATURE_PMU); cpu->id_aa64dfr0 &=3D ~0xf00; + } else if (!kvm_enabled()) { + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); + arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 61ac458627..627e5c1995 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -987,6 +987,12 @@ void pmccntr_op_finish(CPUARMState *env); void pmu_op_start(CPUARMState *env); void pmu_op_finish(CPUARMState *env); =20 +/** + * Functions to register as EL change hooks for PMU mode filtering + */ +void pmu_pre_el_change(ARMCPU *cpu, void *ignored); +void pmu_post_el_change(ARMCPU *cpu, void *ignored); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those @@ -1048,7 +1054,8 @@ void pmu_op_finish(CPUARMState *env); =20 #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) -#define MDCR_SPME (1U << 17) +#define MDCR_SPME (1U << 17) /* MDCR_EL3 */ +#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */ #define MDCR_SDD (1U << 16) #define MDCR_SPD (3U << 14) #define MDCR_TDRA (1U << 11) @@ -1058,6 +1065,7 @@ void pmu_op_finish(CPUARMState *env); #define MDCR_HPME (1U << 7) #define MDCR_TPM (1U << 6) #define MDCR_TPMCR (1U << 5) +#define MDCR_HPMN (0x1fU) =20 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */ #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD) diff --git a/target/arm/helper.c b/target/arm/helper.c index 71a5c71e0a..ddb47813d2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -976,10 +976,24 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { /* Definitions for the PMU registers */ #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 +#define PMCRDP 0x10 #define PMCRD 0x8 #define PMCRC 0x4 #define PMCRE 0x1 =20 +#define PMXEVTYPER_P 0x80000000 +#define PMXEVTYPER_U 0x40000000 +#define PMXEVTYPER_NSK 0x20000000 +#define PMXEVTYPER_NSU 0x10000000 +#define PMXEVTYPER_NSH 0x08000000 +#define PMXEVTYPER_M 0x04000000 +#define PMXEVTYPER_MT 0x02000000 +#define PMXEVTYPER_EVTCOUNT 0x0000ffff +#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NS= K | \ + PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ + PMXEVTYPER_M | PMXEVTYPER_MT | \ + PMXEVTYPER_EVTCOUNT) + static inline uint32_t pmu_num_counters(CPUARMState *env) { return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; @@ -1075,16 +1089,66 @@ static CPAccessResult pmreg_access_ccntr(CPUARMStat= e *env, return pmreg_access(env, ri, isread); } =20 -static inline bool arm_ccnt_enabled(CPUARMState *env) +/* Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing + * the current EL, security state, and register configuration. + */ +static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) { - /* This does not support checking PMCCFILTR_EL0 register */ + uint64_t filter; + bool e, p, u, nsk, nsu, nsh, m; + bool enabled, prohibited, filtered; + bool secure =3D arm_is_secure(env); + int el =3D arm_current_el(env); + uint8_t hpmn =3D env->cp15.mdcr_el2 & MDCR_HPMN; =20 - if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31)= )) { - return false; + if (!arm_feature(env, ARM_FEATURE_EL2) || + (counter < hpmn || counter =3D=3D 31)) { + e =3D env->cp15.c9_pmcr & PMCRE; + } else { + e =3D env->cp15.mdcr_el2 & MDCR_HPME; } + enabled =3D e && (env->cp15.c9_pmcnten & (1 << counter)); =20 - return true; + if (!secure) { + if (el =3D=3D 2 && (counter < hpmn || counter =3D=3D 31)) { + prohibited =3D env->cp15.mdcr_el2 & MDCR_HPMD; + } else { + prohibited =3D false; + } + } else { + prohibited =3D arm_feature(env, ARM_FEATURE_EL3) && + (env->cp15.mdcr_el3 & MDCR_SPME); + } + + if (prohibited && counter =3D=3D 31) { + prohibited =3D env->cp15.c9_pmcr & PMCRDP; + } + + /* TODO Remove assert, set filter to correct PMEVTYPER */ + assert(counter =3D=3D 31); + filter =3D env->cp15.pmccfiltr_el0; + + p =3D filter & PMXEVTYPER_P; + u =3D filter & PMXEVTYPER_U; + nsk =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); + nsu =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); + nsh =3D arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); + m =3D arm_el_is_aa64(env, 1) && + arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); + + if (el =3D=3D 0) { + filtered =3D secure ? u : u !=3D nsu; + } else if (el =3D=3D 1) { + filtered =3D secure ? p : p !=3D nsk; + } else if (el =3D=3D 2) { + filtered =3D !nsh; + } else { /* EL3 */ + filtered =3D m !=3D p; + } + + return enabled && !prohibited && !filtered; } + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1097,7 +1161,7 @@ void pmccntr_op_start(CPUARMState *env) cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); =20 - if (arm_ccnt_enabled(env)) { + if (pmu_counter_enabled(env, 31)) { uint64_t eff_cycles =3D cycles; if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ @@ -1116,7 +1180,7 @@ void pmccntr_op_start(CPUARMState *env) */ void pmccntr_op_finish(CPUARMState *env) { - if (arm_ccnt_enabled(env)) { + if (pmu_counter_enabled(env, 31)) { uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; =20 if (env->cp15.c9_pmcr & PMCRD) { @@ -1138,6 +1202,16 @@ void pmu_op_finish(CPUARMState *env) pmccntr_op_finish(env); } =20 +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_start(&cpu->env); +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_finish(&cpu->env); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1209,6 +1283,14 @@ void pmu_op_finish(CPUARMState *env) { } =20 +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ +} + #endif =20 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=os.amperecomputing.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544017747006326.17477586485563; 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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR01MB4700; H:DM6PR01MB4825.prod.exchangelabs.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:0; Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 3mtbD4nXzsgLjdQcXjueUhyOOlvrjuvfaIa8RfdxcnSRV0e71zLsi7ipxFYs/13STQdEqaRMyech950bjxx1mYsmAAESJIYDeZizRr09d6Pi46wNOOlbYVVuMVeBNZhxdcLM4lGdHQIJI2gF9NOKT0q0s4b/oGE/uzdTPVtaLYDXbdcePaZi1m13Vx09LSv7/1V3kU4VLh2FKVsu3GYnMe2ULLiP1WeSJUR60BYY1hn4unOTTUA9CYiXU/Ca/0vraXL3RSc1OQvurrYsZhNEcIyFKQ9CxcBU/nFg+cRToTqtfjZczcI0kdSMcsq7MrC6g4cqMy9xLq6Cjzh9vLKoxv9YmnjrDmxKjoYnCDf1SBY= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: bd7fc919-2838-47da-3c71-08d65ab79dcf X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Dec 2018 13:43:19.4498 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB4700 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.70.117 Subject: [Qemu-devel] [PATCH v9 05/14] target/arm: Allow AArch32 access for PMCCFILTR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , "qemu-devel@nongnu.org" , Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ddb47813d2..0aff261528 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -994,6 +994,10 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { PMXEVTYPER_M | PMXEVTYPER_MT | \ PMXEVTYPER_EVTCOUNT) =20 +#define PMCCFILTR 0xf8000000 +#define PMCCFILTR_M PMXEVTYPER_M +#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) + static inline uint32_t pmu_num_counters(CPUARMState *env) { return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; @@ -1297,10 +1301,26 @@ static void pmccfiltr_write(CPUARMState *env, const= ARMCPRegInfo *ri, uint64_t value) { pmccntr_op_start(env); - env->cp15.pmccfiltr_el0 =3D value & 0xfc000000; + env->cp15.pmccfiltr_el0 =3D value & PMCCFILTR_EL0; + pmccntr_op_finish(env); +} + +static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_op_start(env); + /* M is not accessible from AArch32 */ + env->cp15.pmccfiltr_el0 =3D (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | + (value & PMCCFILTR); pmccntr_op_finish(env); } =20 +static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *r= i) +{ + /* M is not visible in AArch32 */ + return env->cp15.pmccfiltr_el0 & PMCCFILTR; +} + static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1536,6 +1556,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, .raw_readfn =3D raw_read, .raw_writefn =3D raw_write, }, #endif + { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, + .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .resetvalue =3D 0, }, { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Add an array for PMOVSSET so we only define it for v7ve+ platforms Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/helper.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0aff261528..71be6fb578 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1342,6 +1342,13 @@ static void pmovsr_write(CPUARMState *env, const ARM= CPRegInfo *ri, env->cp15.c9_pmovsr &=3D ~value; } =20 +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmovsr |=3D value; +} + static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1709,6 +1716,24 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { + /* PMOVSSET is not implemented in v7 before v7ve */ + { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + REGINFO_SENTINEL +}; + static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5191,6 +5216,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) !arm_feature(env, ARM_FEATURE_PMSA)) { define_arm_cp_regs(cpu, v7mp_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + define_arm_cp_regs(cpu, pmovsset_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor * field as main ID register, and we implement only the cycle --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=os.amperecomputing.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544017895215158.57177680632356; Wed, 5 Dec 2018 05:51:35 -0800 (PST) Received: from localhost ([::1]:34630 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUXaQ-0005As-2r for importer@patchew.org; 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charset="utf-8" This is immediately necessary for the PMUv3 implementation to check ID_DFR0.PerfMon to enable/disable specific features, but defines the full complement of fields for possible future use elsewhere. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/cpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 627e5c1995..304e6e47b3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1586,6 +1586,14 @@ FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) =20 +FIELD(ID_DFR0, COPDBG, 0, 4) +FIELD(ID_DFR0, COPSDBG, 4, 4) +FIELD(ID_DFR0, MMAPDBG, 8, 4) +FIELD(ID_DFR0, COPTRC, 12, 4) +FIELD(ID_DFR0, MMAPTRC, 16, 4) +FIELD(ID_DFR0, MPROFDBG, 20, 4) +FIELD(ID_DFR0, PERFMON, 24, 4) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- target/arm/helper.c | 18 ++++++++++++++++-- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 304e6e47b3..4216fe22db 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -837,8 +837,8 @@ struct ARMCPU { uint32_t id_pfr0; uint32_t id_pfr1; uint32_t id_dfr0; - uint32_t pmceid0; - uint32_t pmceid1; + uint64_t pmceid0; + uint64_t pmceid1; uint32_t id_afr0; uint32_t id_mmfr0; uint32_t id_mmfr1; diff --git a/target/arm/helper.c b/target/arm/helper.c index 71be6fb578..fb6939e99c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5256,6 +5256,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) } else { define_arm_cp_regs(cpu, not_v7_cp_reginfo); } + if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4) { + ARMCPRegInfo v81_pmu_regs[] =3D { + { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, + { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, v81_pmu_regs); + } if (arm_feature(env, ARM_FEATURE_V8)) { /* AArch64 ID registers, which all have impdef reset values. * Note that within the ID register ranges the unused slots @@ -5432,7 +5446,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D cpu->pmceid0 }, + .resetvalue =3D extract64(cpu->pmceid0, 0, 32) }, { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, @@ -5440,7 +5454,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D cpu->pmceid1 }, + .resetvalue =3D extract64(cpu->pmceid1, 0, 32) }, { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Because the value of PMCEID[01] depends upon which events are supported at runtime, generate it dynamically. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/cpu.c | 19 +++++++++------ target/arm/cpu.h | 10 ++++++++ target/arm/cpu64.c | 4 ---- target/arm/helper.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 79 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f7bad04f60..208a08e867 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1019,10 +1019,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) =20 if (!cpu->has_pmu) { unset_feature(env, ARM_FEATURE_PMU); + } + if (arm_feature(env, ARM_FEATURE_PMU)) { + cpu->pmceid0 =3D get_pmceid(&cpu->env, 0); + cpu->pmceid1 =3D get_pmceid(&cpu->env, 1); + + if (!kvm_enabled()) { + arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); + arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); + } + } else { cpu->id_aa64dfr0 &=3D ~0xf00; - } else if (!kvm_enabled()) { - arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); - arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); + cpu->pmceid0 =3D 0; + cpu->pmceid1 =3D 0; } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { @@ -1665,8 +1674,6 @@ static void cortex_a7_initfn(Object *obj) cpu->id_pfr0 =3D 0x00001131; cpu->id_pfr1 =3D 0x00011011; cpu->id_dfr0 =3D 0x02010555; - cpu->pmceid0 =3D 0x00000000; - cpu->pmceid1 =3D 0x00000000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10101105; cpu->id_mmfr1 =3D 0x40000000; @@ -1712,8 +1719,6 @@ static void cortex_a15_initfn(Object *obj) cpu->id_pfr0 =3D 0x00001131; cpu->id_pfr1 =3D 0x00011011; cpu->id_dfr0 =3D 0x02010555; - cpu->pmceid0 =3D 0x0000000; - cpu->pmceid1 =3D 0x00000000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10201105; cpu->id_mmfr1 =3D 0x20000000; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4216fe22db..0255f68bd7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -993,6 +993,16 @@ void pmu_op_finish(CPUARMState *env); void pmu_pre_el_change(ARMCPU *cpu, void *ignored); void pmu_post_el_change(ARMCPU *cpu, void *ignored); =20 +/* + * get_pmceid + * @env: CPUARMState + * @which: which PMCEID register to return (0 or 1) + * + * Return the PMCEID[01]_EL0 register values corresponding to the counters + * which are supported given the current configuration + */ +uint64_t get_pmceid(CPUARMState *env, unsigned which); + /* SCTLR bit meanings. Several bits have been reused in newer * versions of the architecture; in that case we define constants * for both old and new bit meanings. Code which tests against those diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 873f059bf2..a1aad772fa 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -138,8 +138,6 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->id_aa64dfr0 =3D 0x10305106; - cpu->pmceid0 =3D 0x00000000; - cpu->pmceid1 =3D 0x00000000; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->id_aa64mmfr0 =3D 0x00001124; cpu->dbgdidr =3D 0x3516d000; @@ -246,8 +244,6 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_aa64pfr0 =3D 0x00002222; cpu->id_aa64dfr0 =3D 0x10305106; - cpu->pmceid0 =3D 0x00000000; - cpu->pmceid1 =3D 0x00000000; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->id_aa64mmfr0 =3D 0x00001124; cpu->dbgdidr =3D 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index fb6939e99c..b7a1f4c108 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1009,6 +1009,63 @@ static inline uint64_t pmu_counter_mask(CPUARMState = *env) return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); } =20 +typedef struct pm_event { + uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ + /* If the event is supported on this CPU (used to generate PMCEID[01])= */ + bool (*supported)(CPUARMState *); + /* + * Retrieve the current count of the underlying event. The programmed + * counters hold a difference from the return value from this function + */ + uint64_t (*get_count)(CPUARMState *); +} pm_event; + +static const pm_event pm_events[] =3D { +}; + +/* + * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range = of + * events (i.e. the statistical profiling extension), this implementation + * should first be updated to something sparse instead of the current + * supported_event_map[] array. + */ +#define MAX_EVENT_ID 0x0 +#define UNSUPPORTED_EVENT UINT16_MAX +static uint16_t supported_event_map[MAX_EVENT_ID + 1]; + +/* + * Called upon initialization to build PMCEID0_EL0 or PMCEID1_EL0 (indicat= ed by + * 'which'). We also use it to build a map of ARM event numbers to indices= in + * our pm_events array. + * + * Note: Events in the 0x40XX range are not currently supported. + */ +uint64_t get_pmceid(CPUARMState *env, unsigned which) +{ + uint64_t pmceid =3D 0; + unsigned int i; + + assert(which <=3D 1); + + for (i =3D 0; i < ARRAY_SIZE(supported_event_map); i++) { + supported_event_map[i] =3D UNSUPPORTED_EVENT; + } + + for (i =3D 0; i < ARRAY_SIZE(pm_events); i++) { + const pm_event *cnt =3D &pm_events[i]; + assert(cnt->number <=3D MAX_EVENT_ID); + /* We do not currently support events in the 0x40xx range */ + assert(cnt->number <=3D 0x3f); + + if ((cnt->number & 0x20) =3D=3D (which << 6) && + cnt->supported(env)) { + pmceid |=3D (1 << (cnt->number & 0x1f)); + supported_event_map[cnt->number] =3D i; + } + } + return pmceid; +} + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Add arrays to hold the registers, the definitions themselves, access functions, and logic to reset counters when PMCR.P is set. Update filtering code to support counters other than PMCCNTR. Support migration with raw read/write functions. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/cpu.h | 3 + target/arm/helper.c | 296 +++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 282 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0255f68bd7..62987111be 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -482,6 +482,9 @@ typedef struct CPUARMState { * pmccntr_op_finish. */ uint64_t c15_ccnt_delta; + uint64_t c14_pmevcntr[31]; + uint64_t c14_pmevcntr_delta[31]; + uint64_t c14_pmevtyper[31]; uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register = */ diff --git a/target/arm/helper.c b/target/arm/helper.c index b7a1f4c108..c51031d262 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -979,6 +979,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMCRDP 0x10 #define PMCRD 0x8 #define PMCRC 0x4 +#define PMCRP 0x2 #define PMCRE 0x1 =20 #define PMXEVTYPER_P 0x80000000 @@ -1066,6 +1067,17 @@ uint64_t get_pmceid(CPUARMState *env, unsigned which) return pmceid; } =20 +/* + * Check at runtime whether a PMU event is supported for the current machi= ne + */ +static bool event_supported(uint16_t number) +{ + if (number > MAX_EVENT_ID) { + return false; + } + return supported_event_map[number] !=3D UNSUPPORTED_EVENT; +} + static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { @@ -1185,9 +1197,11 @@ static bool pmu_counter_enabled(CPUARMState *env, ui= nt8_t counter) prohibited =3D env->cp15.c9_pmcr & PMCRDP; } =20 - /* TODO Remove assert, set filter to correct PMEVTYPER */ - assert(counter =3D=3D 31); - filter =3D env->cp15.pmccfiltr_el0; + if (counter =3D=3D 31) { + filter =3D env->cp15.pmccfiltr_el0; + } else { + filter =3D env->cp15.c14_pmevtyper[counter]; + } =20 p =3D filter & PMXEVTYPER_P; u =3D filter & PMXEVTYPER_U; @@ -1207,6 +1221,17 @@ static bool pmu_counter_enabled(CPUARMState *env, ui= nt8_t counter) filtered =3D m !=3D p; } =20 + if (counter !=3D 31) { + /* + * If not checking PMCCNTR, ensure the counter is setup to an even= t we + * support + */ + uint16_t event =3D filter & PMXEVTYPER_EVTCOUNT; + if (!event_supported(event)) { + return false; + } + } + return enabled && !prohibited && !filtered; } =20 @@ -1253,14 +1278,47 @@ void pmccntr_op_finish(CPUARMState *env) } } =20 +static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) +{ + + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCO= UNT; + uint64_t count =3D 0; + if (event_supported(event)) { + uint16_t event_idx =3D supported_event_map[event]; + count =3D pm_events[event_idx].get_count(env); + } + + if (pmu_counter_enabled(env, counter)) { + env->cp15.c14_pmevcntr[counter] =3D + count - env->cp15.c14_pmevcntr_delta[counter]; + } + env->cp15.c14_pmevcntr_delta[counter] =3D count; +} + +static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) +{ + if (pmu_counter_enabled(env, counter)) { + env->cp15.c14_pmevcntr_delta[counter] -=3D + env->cp15.c14_pmevcntr[counter]; + } +} + void pmu_op_start(CPUARMState *env) { + unsigned int i; pmccntr_op_start(env); + for (i =3D 0; i < pmu_num_counters(env); i++) { + pmevcntr_op_start(env, i); + } } =20 void pmu_op_finish(CPUARMState *env) { + unsigned int i; pmccntr_op_finish(env); + for (i =3D 0; i < pmu_num_counters(env); i++) { + pmevcntr_op_finish(env, i); + } } =20 void pmu_pre_el_change(ARMCPU *cpu, void *ignored) @@ -1283,6 +1341,13 @@ static void pmcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, env->cp15.c15_ccnt =3D 0; } =20 + if (value & PMCRP) { + unsigned int i; + for (i =3D 0; i < pmu_num_counters(env); i++) { + env->cp15.c14_pmevcntr[i] =3D 0; + } + } + /* only the DP, X, D and E bits are writable */ env->cp15.c9_pmcr &=3D ~0x39; env->cp15.c9_pmcr |=3D (value & 0x39); @@ -1336,6 +1401,14 @@ void pmccntr_op_finish(CPUARMState *env) { } =20 +void pmevcntr_op_start(CPUARMState *env, uint8_t i) +{ +} + +void pmevcntr_op_finish(CPUARMState *env, uint8_t i) +{ +} + void pmu_op_start(CPUARMState *env) { } @@ -1406,30 +1479,174 @@ static void pmovsset_write(CPUARMState *env, const= ARMCPRegInfo *ri, env->cp15.c9_pmovsr |=3D value; } =20 -static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) +static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, const uint8_t counter) { + if (counter =3D=3D 31) { + pmccfiltr_write(env, ri, value); + } else if (counter < pmu_num_counters(env)) { + pmevcntr_op_start(env, counter); + + /* + * If this counter's event type is changing, store the current + * underlying count for the new type in c14_pmevcntr_delta[counter= ] so + * pmevcntr_op_finish has the correct baseline when it converts ba= ck to + * a delta. + */ + uint16_t old_event =3D env->cp15.c14_pmevtyper[counter] & + PMXEVTYPER_EVTCOUNT; + uint16_t new_event =3D value & PMXEVTYPER_EVTCOUNT; + if (old_event !=3D new_event) { + uint64_t count =3D 0; + if (event_supported(new_event)) { + uint16_t event_idx =3D supported_event_map[new_event]; + count =3D pm_events[event_idx].get_count(env); + } + env->cp15.c14_pmevcntr_delta[counter] =3D count; + } + + env->cp15.c14_pmevtyper[counter] =3D value & PMXEVTYPER_MASK; + pmevcntr_op_finish(env, counter); + } /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when * PMSELR value is equal to or greater than the number of implemented * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. */ - if (env->cp15.c9_pmselr =3D=3D 0x1f) { - pmccfiltr_write(env, ri, value); +} + +static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, + const uint8_t counter) +{ + if (counter =3D=3D 31) { + return env->cp15.pmccfiltr_el0; + } else if (counter < pmu_num_counters(env)) { + return env->cp15.c14_pmevtyper[counter]; + } else { + /* + * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER + * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). + */ + return 0; } } =20 +static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevtyper_write(env, ri, value, counter); +} + +static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + env->cp15.c14_pmevtyper[counter] =3D value; + + /* + * pmevtyper_rawwrite is called between a pair of pmu_op_start and + * pmu_op_finish calls when loading saved state for a migration. Becau= se + * we're potentially updating the type of event here, the value writte= n to + * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a + * different counter type. Therefore, we need to set this value to the + * current count for the counter type we're writing so that pmu_op_fin= ish + * has the correct count for its calculation. + */ + uint16_t event =3D value & PMXEVTYPER_EVTCOUNT; + if (event_supported(event)) { + uint16_t event_idx =3D supported_event_map[event]; + env->cp15.c14_pmevcntr_delta[counter] =3D + pm_events[event_idx].get_count(env); + } +} + +static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevtyper_read(env, ri, counter); +} + +static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) { - /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER - * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write(). + return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); +} + +static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, uint8_t counter) +{ + if (counter < pmu_num_counters(env)) { + pmevcntr_op_start(env, counter); + env->cp15.c14_pmevcntr[counter] =3D value; + pmevcntr_op_finish(env, counter); + } + /* + * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. */ - if (env->cp15.c9_pmselr =3D=3D 0x1f) { - return env->cp15.pmccfiltr_el0; +} + +static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint8_t counter) +{ + if (counter < pmu_num_counters(env)) { + uint64_t ret; + pmevcntr_op_start(env, counter); + ret =3D env->cp15.c14_pmevcntr[counter]; + pmevcntr_op_finish(env, counter); + return ret; } else { + /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. */ return 0; } } =20 +static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevcntr_write(env, ri, value, counter); +} + +static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevcntr_read(env, ri, counter); +} + +static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + assert(counter < pmu_num_counters(env)); + env->cp15.c14_pmevcntr[counter] =3D value; + pmevcntr_write(env, ri, value, counter); +} + +static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + assert(counter < pmu_num_counters(env)); + return env->cp15.c14_pmevcntr[counter]; +} + +static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + +static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); +} + static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1633,16 +1850,23 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), .resetvalue =3D 0, }, { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW, .accessfn =3D pmreg_acc= ess, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access, .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, - /* Unimplemented, RAZ/WI. */ { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, - .accessfn =3D pmreg_access_xevcntr }, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access_xevcntr, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, + { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access_xevcntr, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmuserenr), @@ -4429,7 +4653,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { #endif /* The only field of MDCR_EL2 that has a defined architectural reset v= alue * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but= we - * don't impelment any PMU event counters, so using zero as a reset + * don't implement any PMU event counters, so using zero as a reset * value for MDCR_EL2 is okay */ { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, @@ -5281,6 +5505,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) * field as main ID register, and we implement only the cycle * count register. */ + unsigned int i, pmcrn =3D 0; #ifndef CONFIG_USER_ONLY ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, @@ -5301,6 +5526,43 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &pmcr); define_one_arm_cp_reg(cpu, &pmcr64); + for (i =3D 0; i < pmcrn; i++) { + char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); + char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", = i); + char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); + char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0"= , i); + ARMCPRegInfo pmev_regs[] =3D { + { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 15, + .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & = 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, + .accessfn =3D pmreg_access }, + { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA6= 4, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 15, .crm =3D 8 | (3 &= (i >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, + .type =3D ARM_CP_IO, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, + .raw_readfn =3D pmevcntr_rawread, + .raw_writefn =3D pmevcntr_rawwrite }, + { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 15, + .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i &= 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA= 64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 15, .crm =3D 12 | (3 = & (i >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, + .type =3D ARM_CP_IO, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, + .raw_writefn =3D pmevtyper_rawwrite }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, pmev_regs); + g_free(pmevcntr_name); + g_free(pmevcntr_el0_name); + g_free(pmevtyper_name); + g_free(pmevtyper_el0_name); + } #endif ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=os.amperecomputing.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544018192014790.3861385322193; Wed, 5 Dec 2018 05:56:32 -0800 (PST) Received: from localhost ([::1]:34662 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUXfC-00013N-Eo for importer@patchew.org; Wed, 05 Dec 2018 08:56:30 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51926) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUXTG-0008Ca-Jw for qemu-devel@nongnu.org; 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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR01MB4204; H:DM6PR01MB4825.prod.exchangelabs.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:0; Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: tfuOivDAgBYUUyp923FEgPFwXL0TexAS2oGMod3AWaP1aScAzP8I6d0BBaH+3cDzAygT9L5RYJAWb2fpzriHQ8Qr/HhFBxyV9Jf09zCWZMSDxX4RRqzc/ekxzKqv34WxK2q2m5oDj/dXMjqAUKIH+DVRUs7d7HqkPvaGlSl4ihKafdttCFVGO4E3iGggiqAi//mMAFneLPnx24IhaV0mBQxEEZXkmYpH2cGyrkSbsbTMIGRW6imueA2JunxJF9uuwiMidi259K5RlFZtpoU2sY9dThoNikiHIzYkqyFso1MuDfxo37tZgNyECWUXpZ81vD5amxz5phto7RZ93d50lpOil6MHldxlzo22GavjLN4= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 75402772-f9e9-44f0-96ac-08d65ab7a1d7 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Dec 2018 13:43:26.4185 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB4204 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 2a01:111:f400:fe4d::716 Subject: [Qemu-devel] [PATCH v9 11/14] target/arm: PMU: Add instruction and cycle events X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , "qemu-devel@nongnu.org" , Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 90 ++++++++++++++++++++++----------------------- 1 file changed, 44 insertions(+), 46 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c51031d262..a45ab5d9da 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -15,6 +15,7 @@ #include "arm_ldst.h" #include /* For crc32 */ #include "exec/semihost.h" +#include "sysemu/cpus.h" #include "sysemu/kvm.h" #include "fpu/softfloat.h" #include "qemu/range.h" @@ -1021,7 +1022,48 @@ typedef struct pm_event { uint64_t (*get_count)(CPUARMState *); } pm_event; =20 +static bool event_always_supported(CPUARMState *env) +{ + return true; +} + +/* + * Return the underlying cycle count for the PMU cycle counters. If we're = in + * usermode, simply return 0. + */ +static uint64_t cycles_get_count(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#else + return cpu_get_host_ticks(); +#endif +} + +#ifndef CONFIG_USER_ONLY +static bool instructions_supported(CPUARMState *env) +{ + return use_icount =3D=3D 1 /* Precise instruction counting */; +} + +static uint64_t instructions_get_count(CPUARMState *env) +{ + return (uint64_t)cpu_get_icount_raw(); +} +#endif + static const pm_event pm_events[] =3D { +#ifndef CONFIG_USER_ONLY + { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ + .supported =3D instructions_supported, + .get_count =3D instructions_get_count, + }, + { .number =3D 0x011, /* CPU_CYCLES, Cycle */ + .supported =3D event_always_supported, + .get_count =3D cycles_get_count, + } +#endif }; =20 /* @@ -1030,7 +1072,7 @@ static const pm_event pm_events[] =3D { * should first be updated to something sparse instead of the current * supported_event_map[] array. */ -#define MAX_EVENT_ID 0x0 +#define MAX_EVENT_ID 0x11 #define UNSUPPORTED_EVENT UINT16_MAX static uint16_t supported_event_map[MAX_EVENT_ID + 1]; =20 @@ -1131,8 +1173,6 @@ static CPAccessResult pmreg_access_swinc(CPUARMState = *env, return pmreg_access(env, ri, isread); } =20 -#ifndef CONFIG_USER_ONLY - static CPAccessResult pmreg_access_selr(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -1243,9 +1283,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uin= t8_t counter) */ void pmccntr_op_start(CPUARMState *env) { - uint64_t cycles =3D 0; - cycles =3D muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); + uint64_t cycles =3D cycles_get_count(env); =20 if (pmu_counter_enabled(env, 31)) { uint64_t eff_cycles =3D cycles; @@ -1391,42 +1429,6 @@ static void pmccntr_write32(CPUARMState *env, const = ARMCPRegInfo *ri, pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); } =20 -#else /* CONFIG_USER_ONLY */ - -void pmccntr_op_start(CPUARMState *env) -{ -} - -void pmccntr_op_finish(CPUARMState *env) -{ -} - -void pmevcntr_op_start(CPUARMState *env, uint8_t i) -{ -} - -void pmevcntr_op_finish(CPUARMState *env, uint8_t i) -{ -} - -void pmu_op_start(CPUARMState *env) -{ -} - -void pmu_op_finish(CPUARMState *env) -{ -} - -void pmu_pre_el_change(ARMCPU *cpu, void *ignored) -{ -} - -void pmu_post_el_change(ARMCPU *cpu, void *ignored) -{ -} - -#endif - static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1814,7 +1816,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, -#ifndef CONFIG_USER_ONLY { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), @@ -1836,7 +1837,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, .raw_readfn =3D raw_read, .raw_writefn =3D raw_write, }, -#endif { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, .access =3D PL0_RW, .accessfn =3D pmreg_access, @@ -5506,7 +5506,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) * count register. */ unsigned int i, pmcrn =3D 0; -#ifndef CONFIG_USER_ONLY ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_RW, @@ -5563,7 +5562,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) g_free(pmevtyper_name); g_free(pmevtyper_el0_name); } -#endif ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=os.amperecomputing.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544018003037554.7538302289298; Wed, 5 Dec 2018 05:53:23 -0800 (PST) Received: from localhost ([::1]:34636 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUXc9-0006dI-Pg for importer@patchew.org; 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Wed, 5 Dec 2018 13:43:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amperemail.onmicrosoft.com; s=selector1-os-amperecomputing-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cD0dXLk6Nx3D5kve1foUdU7MZ+yNQubSqdHCEbdKesY=; b=WrQ9lOZSnAlfkwkgGORTU9RkSYZ9mwaU/RRbwOPanv6oC5/xGYXIm6XkGPolAu1Atcg/BICKLjHp6h6uEH6RHQfarD6deVliSkHVNQthglCdVA6VTgjAWwd0HcZx8vrPpWN2EHpkyOVPY+iNw83xLJvoT9/vepFKRlOnanfrD8M= From: Aaron Lindsay To: "qemu-arm@nongnu.org" , Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite , Richard Henderson Thread-Topic: [PATCH v9 12/14] target/arm: PMU: Set PMCR.N to 4 Thread-Index: AQHUjKCAKJwfbGi/q0KMNC79KyPw0A== Date: Wed, 5 Dec 2018 13:43:27 +0000 Message-ID: <20181205134243.4791-13-aaron@os.amperecomputing.com> References: <20181205134243.4791-1-aaron@os.amperecomputing.com> In-Reply-To: <20181205134243.4791-1-aaron@os.amperecomputing.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BN6PR12CA0032.namprd12.prod.outlook.com (2603:10b6:405:70::18) To DM6PR01MB4825.prod.exchangelabs.com (2603:10b6:5:6b::30) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aaron@os.amperecomputing.com; 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charset="utf-8" This both advertises that we support four counters and enables them because the pmu_num_counters() reads this value from PMCR. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell --- target/arm/helper.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a45ab5d9da..724c2f1d69 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1768,7 +1768,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_NOP }, /* Performance monitors are implementation defined in v7, * but with an ARM recommended set of registers, which we - * follow (although we don't actually implement any counters) + * follow. * * Performance registers fall into three categories: * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) @@ -5502,10 +5502,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_V7)) { /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement only the cycle - * count register. + * field as main ID register, and we implement four counters in + * addition to the cycle count register. */ - unsigned int i, pmcrn =3D 0; + unsigned int i, pmcrn =3D 4; ARMCPRegInfo pmcr =3D { .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, .access =3D PL0_RW, @@ -5520,7 +5520,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D cpu->midr & 0xff000000, + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHI= FT), .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; define_one_arm_cp_reg(cpu, &pmcr); --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=os.amperecomputing.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 154401832466472.20046591414166; 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Wed, 5 Dec 2018 13:43:49 +0000 Received: from DM6PR01MB4825.prod.exchangelabs.com ([fe80::9c7c:27c7:4cb7:f820]) by DM6PR01MB4825.prod.exchangelabs.com ([fe80::9c7c:27c7:4cb7:f820%2]) with mapi id 15.20.1404.016; Wed, 5 Dec 2018 13:43:49 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amperemail.onmicrosoft.com; s=selector1-os-amperecomputing-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=FDpWp3T9UN4seC2tR1kdKq38DmyqmtAARlYFOKouo1U=; b=R3eT8itmjnGZWuO3ZVbnGQcq1fHcHVPxvSgQxREkof0IKMUnZCRyguOGIT4/gMAvBZ+4ibLcdmdUGoMtUktPqhXcv238jKzSwtWW6eZ4h63om5eIqqnlmy3MnGTsrzATFxQfGFjGWkzSftQKGs4pzlGQLsNAv6g/1MM3vdonI9k= From: Aaron Lindsay To: "qemu-arm@nongnu.org" , Peter Maydell , Alistair Francis , Wei Huang , Peter Crosthwaite , Richard Henderson Thread-Topic: [PATCH v9 13/14] target/arm: Implement PMSWINC Thread-Index: AQHUjKCBhJflNbObxU+OsPiGwNaiOQ== Date: Wed, 5 Dec 2018 13:43:29 +0000 Message-ID: <20181205134243.4791-14-aaron@os.amperecomputing.com> References: <20181205134243.4791-1-aaron@os.amperecomputing.com> In-Reply-To: <20181205134243.4791-1-aaron@os.amperecomputing.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BN6PR12CA0032.namprd12.prod.outlook.com (2603:10b6:405:70::18) To DM6PR01MB4825.prod.exchangelabs.com (2603:10b6:5:6b::30) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aaron@os.amperecomputing.com; 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charset="utf-8" Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson --- target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 724c2f1d69..3906b6c7a4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1027,6 +1027,15 @@ static bool event_always_supported(CPUARMState *env) return true; } =20 +static uint64_t swinc_get_count(CPUARMState *env) +{ + /* + * SW_INCR events are written directly to the pmevcntr's by writes to + * PMSWINC, so there is no underlying count maintained by the PMU itse= lf + */ + return 0; +} + /* * Return the underlying cycle count for the PMU cycle counters. If we're = in * usermode, simply return 0. @@ -1054,6 +1063,10 @@ static uint64_t instructions_get_count(CPUARMState *= env) #endif =20 static const pm_event pm_events[] =3D { + { .number =3D 0x000, /* SW_INCR */ + .supported =3D event_always_supported, + .get_count =3D swinc_get_count, + }, #ifndef CONFIG_USER_ONLY { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ .supported =3D instructions_supported, @@ -1393,6 +1406,24 @@ static void pmcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, pmu_op_finish(env); } =20 +static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + unsigned int i; + for (i =3D 0; i < pmu_num_counters(env); i++) { + /* Increment a counter's count iff: */ + if ((value & (1 << i)) && /* counter's bit is set */ + /* counter is enabled and not filtered */ + pmu_counter_enabled(env, i) && + /* counter is SW_INCR */ + (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { + pmevcntr_op_start(env, i); + env->cp15.c14_pmevcntr[i]++; + pmevcntr_op_finish(env, i); + } + } +} + static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) { uint64_t ret; @@ -1813,9 +1844,13 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsr_write, .raw_writefn =3D raw_write }, - /* Unimplemented so WI. */ { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NOP }, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NO_RAW, + .writefn =3D pmswinc_write }, + { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, .type =3D ARM_C= P_NO_RAW, + .writefn =3D pmswinc_write }, { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), --=20 2.19.1 From nobody Thu Apr 25 00:44:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=os.amperecomputing.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1544018501655882.0137304190148; Wed, 5 Dec 2018 06:01:41 -0800 (PST) Received: from localhost ([::1]:34713 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUXjz-0001id-Gr for importer@patchew.org; Wed, 05 Dec 2018 09:01:27 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51995) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gUXTM-0008JN-P4 for qemu-devel@nongnu.org; Wed, 05 Dec 2018 08:44:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gUXTH-0005iY-Bz for qemu-devel@nongnu.org; Wed, 05 Dec 2018 08:44:16 -0500 Received: from mail-co1nam04on0716.outbound.protection.outlook.com ([2a01:111:f400:fe4d::716]:64512 helo=NAM04-CO1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gUXTC-0005F5-R6; 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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR01MB4204; H:DM6PR01MB4825.prod.exchangelabs.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:0; Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; received-spf: None (protection.outlook.com: os.amperecomputing.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: Xj+rf+XGnq4YQUtHhI+e89Y+gWom8c3w3I/ADGUMwQ/tYT8mQ/1Q+Fq/myH/PQkOIIVNKmKKiHlEH9dnKBy8eyd88oV7sXsJPYEOgnlhoawPrWdb6mh6PlkweoEwYNq+kF5zI+Yj1B/o0mqZdi/xMYyDLwDRu43L1gaiK6bURwavHcLW/91V0OqyFIJ3vJ9PcbArGCpprdRJXuwTNbwiqibDo155lW35aGebAzx0DwLNe6mw84Vm/1ATNopNQVp53lTySfZHbqcUMs8hKzeIw7rI/ycjmCv6UwCazJuu/E5jBLUq0wdEzbI7k9sPF62p11H/eNwdyOk8phEmMDyw27ZuUlK/2nBJmgANgjpG+6M= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: 95135f21-9443-40aa-8e55-08d65ab7a437 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Dec 2018 13:43:30.2779 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB4204 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 2a01:111:f400:fe4d::716 Subject: [Qemu-devel] [PATCH v9 14/14] target/arm: Send interrupts on PMU counter overflow X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aaron Lindsay , Michael Spradling , "qemu-devel@nongnu.org" , Digant Desai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Setup a QEMUTimer to get a callback when we expect counters to next overflow and trigger an interrupt at that time. Signed-off-by: Aaron Lindsay Signed-off-by: Aaron Lindsay --- target/arm/cpu.c | 12 +++++ target/arm/cpu.h | 7 +++ target/arm/helper.c | 126 +++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 139 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 208a08e867..85cec59fc9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -827,6 +827,13 @@ static void arm_cpu_finalizefn(Object *obj) QLIST_REMOVE(hook, node); g_free(hook); } +#ifndef CONFIG_USER_ONLY + if (cpu->pmu_timer) { + timer_del(cpu->pmu_timer); + timer_deinit(cpu->pmu_timer); + timer_free(cpu->pmu_timer); + } +#endif } =20 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) @@ -1028,6 +1035,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); } + +#ifndef CONFIG_USER_ONLY + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_= cb, + cpu); +#endif } else { cpu->id_aa64dfr0 &=3D ~0xf00; cpu->pmceid0 =3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 62987111be..747c3f6be2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -733,6 +733,8 @@ struct ARMCPU { =20 /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; + /* Timer used by the PMU */ + QEMUTimer *pmu_timer; /* GPIO outputs for generic timer */ qemu_irq gt_timer_outputs[NUM_GTIMERS]; /* GPIO output for GICv3 maintenance interrupt signal */ @@ -990,6 +992,11 @@ void pmccntr_op_finish(CPUARMState *env); void pmu_op_start(CPUARMState *env); void pmu_op_finish(CPUARMState *env); =20 +/** + * Called when a PMU counter is due to overflow + */ +void arm_pmu_timer_cb(void *opaque); + /** * Functions to register as EL change hooks for PMU mode filtering */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 3906b6c7a4..0b91ec2c05 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -977,6 +977,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { /* Definitions for the PMU registers */ #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 +#define PMCRLC 0x40 #define PMCRDP 0x10 #define PMCRD 0x8 #define PMCRC 0x4 @@ -996,6 +997,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { PMXEVTYPER_M | PMXEVTYPER_MT | \ PMXEVTYPER_EVTCOUNT) =20 +#define PMEVCNTR_OVERFLOW_MASK ((uint64_t)1 << 31) + #define PMCCFILTR 0xf8000000 #define PMCCFILTR_M PMXEVTYPER_M #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) @@ -1020,6 +1023,11 @@ typedef struct pm_event { * counters hold a difference from the return value from this function */ uint64_t (*get_count)(CPUARMState *); + /* Return how many nanoseconds it will take (at a minimum) for count e= vents + * to occur. A negative value indicates the counter will never overflo= w, or + * that the counter has otherwise arranged for the overflow bit to be = set + * and the PMU interrupt to be raised on overflow. */ + int64_t (*ns_per_count)(uint64_t); } pm_event; =20 static bool event_always_supported(CPUARMState *env) @@ -1036,6 +1044,11 @@ static uint64_t swinc_get_count(CPUARMState *env) return 0; } =20 +static int64_t swinc_ns_per(uint64_t ignored) +{ + return -1; +} + /* * Return the underlying cycle count for the PMU cycle counters. If we're = in * usermode, simply return 0. @@ -1051,6 +1064,11 @@ static uint64_t cycles_get_count(CPUARMState *env) } =20 #ifndef CONFIG_USER_ONLY +static int64_t cycles_ns_per(uint64_t cycles) +{ + return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; +} + static bool instructions_supported(CPUARMState *env) { return use_icount =3D=3D 1 /* Precise instruction counting */; @@ -1060,21 +1078,29 @@ static uint64_t instructions_get_count(CPUARMState = *env) { return (uint64_t)cpu_get_icount_raw(); } + +static int64_t instructions_ns_per(uint64_t icount) +{ + return cpu_icount_to_ns((int64_t)icount); +} #endif =20 static const pm_event pm_events[] =3D { { .number =3D 0x000, /* SW_INCR */ .supported =3D event_always_supported, .get_count =3D swinc_get_count, + .ns_per_count =3D swinc_ns_per, }, #ifndef CONFIG_USER_ONLY { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ .supported =3D instructions_supported, .get_count =3D instructions_get_count, + .ns_per_count =3D instructions_ns_per, }, { .number =3D 0x011, /* CPU_CYCLES, Cycle */ .supported =3D event_always_supported, .get_count =3D cycles_get_count, + .ns_per_count =3D cycles_ns_per, } #endif }; @@ -1288,6 +1314,13 @@ static bool pmu_counter_enabled(CPUARMState *env, ui= nt8_t counter) return enabled && !prohibited && !filtered; } =20 +static void pmu_update_irq(CPUARMState *env) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && + (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); +} + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1305,7 +1338,19 @@ void pmccntr_op_start(CPUARMState *env) eff_cycles /=3D 64; } =20 - env->cp15.c15_ccnt =3D eff_cycles - env->cp15.c15_ccnt_delta; + uint64_t new_pmccntr =3D eff_cycles - env->cp15.c15_ccnt_delta; + + unsigned int overflow_bit =3D (env->cp15.c9_pmcr & PMCRLC) ? 63 : = 31; + uint64_t overflow_mask =3D (uint64_t)1 << overflow_bit; + if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { + env->cp15.c9_pmovsr |=3D (1 << 31); + if (!(env->cp15.c9_pmcr & PMCRLC)) { + new_pmccntr &=3D 0xffffffff; + } + pmu_update_irq(env); + } + + env->cp15.c15_ccnt =3D new_pmccntr; } env->cp15.c15_ccnt_delta =3D cycles; } @@ -1318,13 +1363,27 @@ void pmccntr_op_start(CPUARMState *env) void pmccntr_op_finish(CPUARMState *env) { if (pmu_counter_enabled(env, 31)) { - uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; +#ifndef CONFIG_USER_ONLY + /* Calculate when the counter will next overflow */ + uint64_t delta =3D -env->cp15.c15_ccnt; + if (!(env->cp15.c9_pmcr & PMCRLC)) { + delta =3D (uint32_t)delta; + } + int64_t overflow_in =3D cycles_ns_per(delta); + + if (overflow_in > 0) { + int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + overflow_in; + ARMCPU *cpu =3D arm_env_get_cpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } +#endif =20 + uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; if (env->cp15.c9_pmcr & PMCRD) { /* Increment once every 64 processor clock cycles */ prev_cycles /=3D 64; } - env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; } } @@ -1340,8 +1399,15 @@ static void pmevcntr_op_start(CPUARMState *env, uint= 8_t counter) } =20 if (pmu_counter_enabled(env, counter)) { - env->cp15.c14_pmevcntr[counter] =3D - count - env->cp15.c14_pmevcntr_delta[counter]; + uint64_t new_pmevcntr =3D count - env->cp15.c14_pmevcntr_delta[cou= nter]; + + if (!(new_pmevcntr & PMEVCNTR_OVERFLOW_MASK) && + (env->cp15.c14_pmevcntr[counter] & PMEVCNTR_OVERFLOW_MASK)= ) { + env->cp15.c9_pmovsr |=3D (1 << counter); + new_pmevcntr &=3D ~PMEVCNTR_OVERFLOW_MASK; + pmu_update_irq(env); + } + env->cp15.c14_pmevcntr[counter] =3D new_pmevcntr; } env->cp15.c14_pmevcntr_delta[counter] =3D count; } @@ -1349,6 +1415,21 @@ static void pmevcntr_op_start(CPUARMState *env, uint= 8_t counter) static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) { if (pmu_counter_enabled(env, counter)) { +#ifndef CONFIG_USER_ONLY + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; + uint16_t event_idx =3D supported_event_map[event]; + uint64_t delta =3D UINT32_MAX - + (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; + int64_t overflow_in =3D pm_events[event_idx].ns_per_count(delta); + + if (overflow_in > 0) { + int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + overflow_in; + ARMCPU *cpu =3D arm_env_get_cpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } +#endif + env->cp15.c14_pmevcntr_delta[counter] -=3D env->cp15.c14_pmevcntr[counter]; } @@ -1382,6 +1463,19 @@ void pmu_post_el_change(ARMCPU *cpu, void *ignored) pmu_op_finish(&cpu->env); } =20 +void arm_pmu_timer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + /* Update all the counter values based on the current underlying count= s, + * triggering interrupts to be raised, if necessary. pmu_op_finish() a= lso + * has the effect of setting the cpu->pmu_timer to the next earliest t= ime a + * counter may expire. + */ + pmu_op_start(&cpu->env); + pmu_op_finish(&cpu->env); +} + static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -1418,7 +1512,21 @@ static void pmswinc_write(CPUARMState *env, const AR= MCPRegInfo *ri, /* counter is SW_INCR */ (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { pmevcntr_op_start(env, i); - env->cp15.c14_pmevcntr[i]++; + + /* Detect if this write causes an overflow since we can't pred= ict + * PMSWINC overflows like we can for other events + */ + uint64_t new_pmswinc =3D env->cp15.c14_pmevcntr[i] + 1; + + if (!(new_pmswinc & PMEVCNTR_OVERFLOW_MASK) && + (env->cp15.c14_pmevcntr[i] & PMEVCNTR_OVERFLOW_MASK)) { + env->cp15.c9_pmovsr |=3D (1 << i); + new_pmswinc &=3D ~PMEVCNTR_OVERFLOW_MASK; + pmu_update_irq(env); + } + + env->cp15.c14_pmevcntr[i] =3D new_pmswinc; + pmevcntr_op_finish(env, i); } } @@ -1489,6 +1597,7 @@ static void pmcntenset_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten |=3D value; + pmu_update_irq(env); } =20 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1496,6 +1605,7 @@ static void pmcntenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmcnten &=3D ~value; + pmu_update_irq(env); } =20 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1503,6 +1613,7 @@ static void pmovsr_write(CPUARMState *env, const ARMC= PRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmovsr &=3D ~value; + pmu_update_irq(env); } =20 static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1510,6 +1621,7 @@ static void pmovsset_write(CPUARMState *env, const AR= MCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pmovsr |=3D value; + pmu_update_irq(env); } =20 static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1696,6 +1808,7 @@ static void pmintenset_write(CPUARMState *env, const = ARMCPRegInfo *ri, /* We have no event counters so only the C bit can be changed */ value &=3D pmu_counter_mask(env); env->cp15.c9_pminten |=3D value; + pmu_update_irq(env); } =20 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1703,6 +1816,7 @@ static void pmintenclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, { value &=3D pmu_counter_mask(env); env->cp15.c9_pminten &=3D ~value; + pmu_update_irq(env); } =20 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.19.1