include/hw/arm/xlnx-versal.h | 31 +-

target/arm/cpu-param.h | 2 +-

target/arm/cpu.h | 38 ++-

target/arm/translate-a64.h | 9 -

target/arm/translate.h | 26 ++

target/arm/neon-dp.decode | 86 +++++

target/arm/neon-ls.decode | 52 +++

target/arm/neon-shared.decode | 66 ++++

hw/arm/mps2-tz.c | 2 +-

hw/arm/xlnx-versal-virt.c | 74 ++++-

hw/arm/xlnx-versal.c | 115 +++++--

target/arm/cpu.c | 3 +-

target/arm/cpu64.c | 8 +-

target/arm/helper.c | 183 ++++------

target/arm/translate-a64.c | 17 -

target/arm/translate-neon.inc.c | 714 +++++++++++++++++++++++++++++++++++++++

target/arm/translate-vfp.inc.c | 6 -

target/arm/translate.c | 716 +++-------------------------------------

target/arm/Makefile.objs | 18 +

19 files changed, 1302 insertions(+), 864 deletions(-)

create mode 100644 target/arm/neon-dp.decode

create mode 100644 target/arm/neon-ls.decode

create mode 100644 target/arm/neon-shared.decode

create mode 100644 target/arm/translate-neon.inc.c

From: Fredrik Strupe <fredrik@strupe.net>

According to Arm ARM, VQDMULL is only valid when U=0, while having

U=1 is unallocated.

Signed-off-by: Fredrik Strupe <fredrik@strupe.net>

Fixes: 695272dcb976 ("target-arm: Handle UNDEF cases for Neon 3-regs-different-widths")

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/translate.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)

{0, 0, 0, 0}, /* VMLSL */

{0, 0, 0, 9}, /* VQDMLSL */

{0, 0, 0, 0}, /* Integer VMULL */

- {0, 0, 0, 1}, /* VQDMULL */

+ {0, 0, 0, 9}, /* VQDMULL */

{0, 0, 0, 0xa}, /* Polynomial VMULL */

{0, 0, 0, 7}, /* Reserved: always UNDEF */

};

--

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

By using the TYPE_* definitions for devices, we can:

- quickly find where devices are used with 'git-grep'

- easily rename a device (one-line change).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20200428154650.21991-1-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/mps2-tz.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/mps2-tz.c

+++ b/hw/arm/mps2-tz.c

@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)

exit(EXIT_FAILURE);

}

- sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,

+ sysbus_init_child_obj(OBJECT(machine), TYPE_IOTKIT, &mms->iotkit,

sizeof(mms->iotkit), mmc->armsse_type);

iotkitdev = DEVICE(&mms->iotkit);

object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),

--

2.20.1

The access_type argument to get_phys_addr_lpae() is an MMUAccessType;

use the enum constant MMU_DATA_LOAD rather than a literal 0 when we

call it in S1_ptw_translate().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200330210400.11724-3-peter.maydell@linaro.org

---

target/arm/helper.c | 5 +++--

1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,

pcacheattrs = &cacheattrs;

}

- ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_Stage2, &s2pa,

- &txattrs, &s2prot, &s2size, fi, pcacheattrs);

+ ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,

+ &s2pa, &txattrs, &s2prot, &s2size, fi,

+ pcacheattrs);

if (ret) {

assert(fi->type != ARMFault_None);

fi->s2addr = addr;

--

2.20.1

For ARMv8.2-TTS2UXN, the stage 2 page table walk wants to know

whether the stage 1 access is for EL0 or not, because whether

exec permission is given can depend on whether this is an EL0

or EL1 access. Add a new argument to get_phys_addr_lpae() so

the call sites can pass this information in.

Since get_phys_addr_lpae() doesn't already have a doc comment,

add one so we have a place to put the documentation of the

semantics of the new s1_is_el0 argument.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200330210400.11724-4-peter.maydell@linaro.org

---

target/arm/helper.c | 29 ++++++++++++++++++++++++++++-

1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@

static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

MMUAccessType access_type, ARMMMUIdx mmu_idx,

+ bool s1_is_el0,

hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,

target_ulong *page_size_ptr,

ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs);

@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,

}

ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, ARMMMUIdx_Stage2,

+ false,

&s2pa, &txattrs, &s2prot, &s2size, fi,

pcacheattrs);

if (ret) {

@@ -XXX,XX +XXX,XX @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,

};

}

+/**

+ * get_phys_addr_lpae: perform one stage of page table walk, LPAE format

+ *

+ * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,

+ * prot and page_size may not be filled in, and the populated fsr value provides

+ * information on why the translation aborted, in the format of a long-format

+ * DFSR/IFSR fault register, with the following caveats:

+ * * the WnR bit is never set (the caller must do this).

+ *

+ * @env: CPUARMState

+ * @address: virtual address to get physical address for

+ * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH

+ * @mmu_idx: MMU index indicating required translation regime

+ * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page table

+ * walk), must be true if this is stage 2 of a stage 1+2 walk for an

+ * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ignored.

+ * @phys_ptr: set to the physical address corresponding to the virtual address

+ * @attrs: set to the memory transaction attributes to use

+ * @prot: set to the permissions for the page containing phys_ptr

+ * @page_size_ptr: set to the size of the page containing phys_ptr

+ * @fi: set to fault info if the translation fails

+ * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes

+ */

static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

MMUAccessType access_type, ARMMMUIdx mmu_idx,

+ bool s1_is_el0,

hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,

target_ulong *page_size_ptr,

ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)

@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,

/* S1 is done. Now do S2 translation. */

ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_Stage2,

+ mmu_idx == ARMMMUIdx_E10_0,

phys_ptr, attrs, &s2_prot,

page_size, fi,

cacheattrs != NULL ? &cacheattrs2 : NULL);

@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,

}

if (regime_using_lpae_format(env, mmu_idx)) {

- return get_phys_addr_lpae(env, address, access_type, mmu_idx,

+ return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,

phys_ptr, attrs, prot, page_size,

fi, cacheattrs);

} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {

--

2.20.1

The ARMv8.2-TTS2UXN feature extends the XN field in stage 2

translation table descriptors from just bit [54] to bits [54:53],

allowing stage 2 to control execution permissions separately for EL0

and EL1. Implement the new semantics of the XN field and enable

the feature for our 'max' CPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200330210400.11724-5-peter.maydell@linaro.org

---

target/arm/cpu.h | 15 +++++++++++++++

target/arm/cpu.c | 1 +

target/arm/cpu64.c | 2 ++

target/arm/helper.c | 37 +++++++++++++++++++++++++++++++------

4 files changed, 49 insertions(+), 6 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)

return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;

}

+static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)

+{

+ return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;

+}

+

/*

* 64-bit feature tests via id registers.

*/

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)

return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;

}

+static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)

+{

+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;

+}

+

/*

* Feature tests for "does this exist in either 32-bit or 64-bit?"

*/

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)

return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);

}

+static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)

+{

+ return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);

+}

+

/*

* Forward to the above feature tests given an ARMCPU pointer.

*/

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)

t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */

t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */

t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */

+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */

cpu->isar.id_mmfr4 = t;

}

#endif

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);

t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */

t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */

+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */

cpu->isar.id_aa64mmfr1 = t;

t = cpu->isar.id_aa64mmfr2;

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */

u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */

u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */

+ u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */

cpu->isar.id_mmfr4 = u;

u = cpu->isar.id_aa64dfr0;

diff --git a/target/arm/helper.c b/target/arm/helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper.c

+++ b/target/arm/helper.c

@@ -XXX,XX +XXX,XX @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)

*

* @env: CPUARMState

* @s2ap: The 2-bit stage2 access permissions (S2AP)

- * @xn: XN (execute-never) bit

+ * @xn: XN (execute-never) bits

+ * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0

*/

-static int get_S2prot(CPUARMState *env, int s2ap, int xn)

+static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0)

{

int prot = 0;

@@ -XXX,XX +XXX,XX @@ static int get_S2prot(CPUARMState *env, int s2ap, int xn)

if (s2ap & 2) {

prot |= PAGE_WRITE;

}

- if (!xn) {

- if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {

+

+ if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) {

+ switch (xn) {

+ case 0:

prot |= PAGE_EXEC;

+ break;

+ case 1:

+ if (s1_is_el0) {

+ prot |= PAGE_EXEC;

+ }

+ break;

+ case 2:

+ break;

+ case 3:

+ if (!s1_is_el0) {

+ prot |= PAGE_EXEC;

+ }

+ break;

+ default:

+ g_assert_not_reached();

+ }

+ } else {

+ if (!extract32(xn, 1, 1)) {

+ if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) {

+ prot |= PAGE_EXEC;

+ }

}

}

return prot;

@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,

}

ap = extract32(attrs, 4, 2);

- xn = extract32(attrs, 12, 1);

if (mmu_idx == ARMMMUIdx_Stage2) {

ns = true;

- *prot = get_S2prot(env, ap, xn);

+ xn = extract32(attrs, 11, 2);

+ *prot = get_S2prot(env, ap, xn, s1_is_el0);

} else {

ns = extract32(attrs, 3, 1);

+ xn = extract32(attrs, 12, 1);

pxn = extract32(attrs, 11, 1);

*prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);

}

--

2.20.1

In aarch64_max_initfn() we update both 32-bit and 64-bit ID

registers. The intended pattern is that for 64-bit ID registers we

use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID

registers use FIELD_DP32 and the uint32_t 'u' register. For

ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of

this 64-bit ID register would end up always zero. Luckily at the

moment that's what they should be anyway, so this bug has no visible

effects.

Use the right-sized variable.

Fixes: 3bec78447a958d481991

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20200423110915.10527-1-peter.maydell@linaro.org

---

target/arm/cpu64.c | 6 +++---

1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */

cpu->isar.id_mmfr4 = u;

- u = cpu->isar.id_aa64dfr0;

- u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */

- cpu->isar.id_aa64dfr0 = u;

+ t = cpu->isar.id_aa64dfr0;

+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */

+ cpu->isar.id_aa64dfr0 = t;

u = cpu->isar.id_dfr0;

u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */

--

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

MIDR_EL1 is a 64-bit system register with the top 32-bit being RES0.

Represent it in QEMU's ARMCPU struct with a uint64_t, not a

uint32_t.

This fixes an error when compiling with -Werror=conversion

because we were manipulating the register value using a

local uint64_t variable:

target/arm/cpu64.c: In function ‘aarch64_max_initfn’:

target/arm/cpu64.c:628:21: error: conversion from ‘uint64_t’ {aka ‘long unsigned int’} to ‘uint32_t’ {aka ‘unsigned int’} may change value [-Werror=conversion]

628 | cpu->midr = t;

| ^

and future-proofs us against a possible future architecture

change using some of the top 32 bits.

Suggested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Message-id: 20200428172634.29707-1-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 2 +-

target/arm/cpu.c | 2 +-

2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ struct ARMCPU {

uint64_t id_aa64dfr0;

uint64_t id_aa64dfr1;

} isar;

- uint32_t midr;

+ uint64_t midr;

uint32_t revidr;

uint32_t reset_fpsid;

uint32_t ctr;

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {

static Property arm_cpu_properties[] = {

DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),

DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),

- DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),

+ DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0),

DEFINE_PROP_UINT64("mp-affinity", ARMCPU,

mp_affinity, ARM64_AFFINITY_INVALID),

DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),

--

2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Remove inclusion of arm_gicv3_common.h, this already gets

included via xlnx-versal.h.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20200427181649.26851-2-edgar.iglesias@gmail.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/xlnx-versal.c | 1 -

1 file changed, 1 deletion(-)

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal.c

+++ b/hw/arm/xlnx-versal.c

@@ -XXX,XX +XXX,XX @@

#include "hw/arm/boot.h"

#include "kvm_arm.h"

#include "hw/misc/unimp.h"

-#include "hw/intc/arm_gicv3_common.h"

#include "hw/arm/xlnx-versal.h"

#include "hw/char/pl011.h"

--

2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Move misplaced comment.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20200427181649.26851-3-edgar.iglesias@gmail.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/xlnx-versal.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal.c

+++ b/hw/arm/xlnx-versal.c

@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)

obj = object_new(XLNX_VERSAL_ACPU_TYPE);

if (!obj) {

- /* Secondary CPUs start in PSCI powered-down state */

error_report("Unable to create apu.cpu[%d] of type %s",

i, XLNX_VERSAL_ACPU_TYPE);

exit(EXIT_FAILURE);

@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)

object_property_set_int(obj, s->cfg.psci_conduit,

"psci-conduit", &error_abort);

if (i) {

+ /* Secondary CPUs start in PSCI powered-down state */

object_property_set_bool(obj, true,

"start-powered-off", &error_abort);

}

--

2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Fix typo xlnx-ve -> xlnx-versal.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20200427181649.26851-4-edgar.iglesias@gmail.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/xlnx-versal-virt.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal-virt.c

+++ b/hw/arm/xlnx-versal-virt.c

@@ -XXX,XX +XXX,XX @@ static void versal_virt_init(MachineState *machine)

psci_conduit = QEMU_PSCI_CONDUIT_SMC;

}

- sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc,

+ sysbus_init_child_obj(OBJECT(machine), "xlnx-versal", &s->soc,

sizeof(s->soc), TYPE_XLNX_VERSAL);

object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram),

"ddr", &error_abort);

--

2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the UARTs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20200427181649.26851-5-edgar.iglesias@gmail.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/hw/arm/xlnx-versal.h | 3 ++-

hw/arm/xlnx-versal.c | 12 ++++++------

2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/xlnx-versal.h

+++ b/include/hw/arm/xlnx-versal.h

@@ -XXX,XX +XXX,XX @@

#include "hw/sysbus.h"

#include "hw/arm/boot.h"

#include "hw/intc/arm_gicv3.h"

+#include "hw/char/pl011.h"

#define TYPE_XLNX_VERSAL "xlnx-versal"

#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)

@@ -XXX,XX +XXX,XX @@ typedef struct Versal {

MemoryRegion mr_ocm;

struct {

- SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];

+ PL011State uart[XLNX_VERSAL_NR_UARTS];

SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];

SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];

} iou;

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal.c

+++ b/hw/arm/xlnx-versal.c

@@ -XXX,XX +XXX,XX @@

#include "kvm_arm.h"

#include "hw/misc/unimp.h"

#include "hw/arm/xlnx-versal.h"

-#include "hw/char/pl011.h"

#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")

#define GEM_REVISION 0x40070106

@@ -XXX,XX +XXX,XX @@ static void versal_create_uarts(Versal *s, qemu_irq *pic)

DeviceState *dev;

MemoryRegion *mr;

- dev = qdev_create(NULL, TYPE_PL011);

- s->lpd.iou.uart[i] = SYS_BUS_DEVICE(dev);

+ sysbus_init_child_obj(OBJECT(s), name,

+ &s->lpd.iou.uart[i], sizeof(s->lpd.iou.uart[i]),

+ TYPE_PL011);

+ dev = DEVICE(&s->lpd.iou.uart[i]);

qdev_prop_set_chr(dev, "chardev", serial_hd(i));

- object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);

qdev_init_nofail(dev);

- mr = sysbus_mmio_get_region(s->lpd.iou.uart[i], 0);

+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

memory_region_add_subregion(&s->mr_ps, addrs[i], mr);

- sysbus_connect_irq(s->lpd.iou.uart[i], 0, pic[irqs[i]]);

+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);

g_free(name);

}

}

--

2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the GEMs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20200427181649.26851-6-edgar.iglesias@gmail.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/hw/arm/xlnx-versal.h | 3 ++-

hw/arm/xlnx-versal.c | 15 ++++++++-------

2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/xlnx-versal.h

+++ b/include/hw/arm/xlnx-versal.h

@@ -XXX,XX +XXX,XX @@

#include "hw/arm/boot.h"

#include "hw/intc/arm_gicv3.h"

#include "hw/char/pl011.h"

+#include "hw/net/cadence_gem.h"

#define TYPE_XLNX_VERSAL "xlnx-versal"

#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)

@@ -XXX,XX +XXX,XX @@ typedef struct Versal {

struct {

PL011State uart[XLNX_VERSAL_NR_UARTS];

- SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];

+ CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];

SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];

} iou;

} lpd;

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal.c

+++ b/hw/arm/xlnx-versal.c

@@ -XXX,XX +XXX,XX @@ static void versal_create_gems(Versal *s, qemu_irq *pic)

DeviceState *dev;

MemoryRegion *mr;

- dev = qdev_create(NULL, "cadence_gem");

- s->lpd.iou.gem[i] = SYS_BUS_DEVICE(dev);

- object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);

+ sysbus_init_child_obj(OBJECT(s), name,

+ &s->lpd.iou.gem[i], sizeof(s->lpd.iou.gem[i]),

+ TYPE_CADENCE_GEM);

+ dev = DEVICE(&s->lpd.iou.gem[i]);

if (nd->used) {

qemu_check_nic_model(nd, "cadence_gem");

qdev_set_nic_properties(dev, nd);

}

- object_property_set_int(OBJECT(s->lpd.iou.gem[i]),

+ object_property_set_int(OBJECT(dev),

2, "num-priority-queues",

&error_abort);

- object_property_set_link(OBJECT(s->lpd.iou.gem[i]),

+ object_property_set_link(OBJECT(dev),

OBJECT(&s->mr_ps), "dma",

&error_abort);

qdev_init_nofail(dev);

- mr = sysbus_mmio_get_region(s->lpd.iou.gem[i], 0);

+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

memory_region_add_subregion(&s->mr_ps, addrs[i], mr);

- sysbus_connect_irq(s->lpd.iou.gem[i], 0, pic[irqs[i]]);

+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[irqs[i]]);

g_free(name);

}

}

--

2.20.1

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Embed the ADMAs into the SoC type.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

Message-id: 20200427181649.26851-7-edgar.iglesias@gmail.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/hw/arm/xlnx-versal.h | 3 ++-

hw/arm/xlnx-versal.c | 14 +++++++-------

2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/arm/xlnx-versal.h

+++ b/include/hw/arm/xlnx-versal.h

@@ -XXX,XX +XXX,XX @@

#include "hw/arm/boot.h"

#include "hw/intc/arm_gicv3.h"

#include "hw/char/pl011.h"

+#include "hw/dma/xlnx-zdma.h"

#include "hw/net/cadence_gem.h"

#define TYPE_XLNX_VERSAL "xlnx-versal"

@@ -XXX,XX +XXX,XX @@ typedef struct Versal {

struct {

PL011State uart[XLNX_VERSAL_NR_UARTS];

CadenceGEMState gem[XLNX_VERSAL_NR_GEMS];

- SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];

+ XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS];

} iou;

} lpd;

diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/xlnx-versal.c

+++ b/hw/arm/xlnx-versal.c

@@ -XXX,XX +XXX,XX @@ static void versal_create_admas(Versal *s, qemu_irq *pic)

DeviceState *dev;

MemoryRegion *mr;

- dev = qdev_create(NULL, "xlnx.zdma");

- s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev);

- object_property_set_int(OBJECT(s->lpd.iou.adma[i]), 128, "bus-width",

- &error_abort);

- object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);

+ sysbus_init_child_obj(OBJECT(s), name,

+ &s->lpd.iou.adma[i], sizeof(s->lpd.iou.adma[i]),

+ TYPE_XLNX_ZDMA);

+ dev = DEVICE(&s->lpd.iou.adma[i]);

+ object_property_set_int(OBJECT(dev), 128, "bus-width", &error_abort);

qdev_init_nofail(dev);

- mr = sysbus_mmio_get_region(s->lpd.iou.adma[i], 0);

+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);

memory_region_add_subregion(&s->mr_ps,

MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);

- sysbus_connect_irq(s->lpd.iou.adma[i], 0, pic[VERSAL_ADMA_IRQ_0 + i]);

+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_ADMA_IRQ_0 + i]);

g_free(name);

}

}

--

2.20.1