[Qemu-devel] [PULL 00/17] target-arm queue
[Qemu-devel] [PULL v2 00/47] target-arm queue
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v2: dropped a couple of cadence_gem changes to ID regs that
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v2: dropped USHL/SSHL patch
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caused new clang sanitizer warnings.
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-- PMM
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The following changes since commit 785a602eae7ad97076b9794ebaba072ad4a9f74f:
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The following changes since commit dddb37495b844270088e68e3bf30b764d48d863f:
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Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190613-pull-request' into staging (2019-06-13 13:25:25 +0100)
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Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20181015.0' into staging (2018-10-15 18:44:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181016-1
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190613-1
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for you to fetch changes up to 2ef297af07196c29446556537861f8e7dfeeae7b:
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for you to fetch changes up to 18cf951af9a27ae573a6fa17f9d0c103f7b7679b:
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls (2018-10-16 17:14:55 +0100)
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target/arm: Fix short-vector increment behaviour (2019-06-13 15:14:06 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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* convert aarch32 VFP decoder to decodetree
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* target/arm: Fix aarch64_sve_change_el wrt EL0
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(includes tightening up decode in a few places)
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* target/arm: Define fields of ISAR registers
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* fix minor bugs in VFP short-vector handling
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* target/arm: Align cortex-r5 id_isar0
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* hw/core/bus.c: Only the main system bus can have no parent
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* target/arm: Fix cortex-a7 id_isar0
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* smmuv3: Fix decoding of ID register range
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* net/cadence_gem: Fix various bugs, add support for new
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* Implement NSACR gating of floating point
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features that will be used by the Xilinx Versal board
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* Use tcg_gen_gvec_bitsel
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* target-arm: powerctl: Enable HVC when starting CPUs to EL2
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* target/arm: Add the Cortex-A72
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* target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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* target/arm: Mask PMOVSR writes based on supported counters
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* target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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* coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (2):
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Peter Maydell (44):
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target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO
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target/arm: Implement NSACR gating of floating point
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target/arm: Mask PMOVSR writes based on supported counters
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hw/arm/smmuv3: Fix decoding of ID register range
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hw/core/bus.c: Only the main system bus can have no parent
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target/arm: Add stubs for AArch32 VFP decodetree
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target/arm: Factor out VFP access checking code
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target/arm: Fix Cortex-R5F MVFR values
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target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max
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target/arm: Convert the VSEL instructions to decodetree
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target/arm: Convert VMINNM, VMAXNM to decodetree
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target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree
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target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree
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target/arm: Move the VFP trans_* functions to translate-vfp.inc.c
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target/arm: Add helpers for VFP register loads and stores
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target/arm: Convert "double-precision" register moves to decodetree
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target/arm: Convert "single-precision" register moves to decodetree
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target/arm: Convert VFP two-register transfer insns to decodetree
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target/arm: Convert VFP VLDR and VSTR to decodetree
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target/arm: Convert the VFP load/store multiple insns to decodetree
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target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d
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target/arm: Convert VFP VMLA to decodetree
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target/arm: Convert VFP VMLS to decodetree
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target/arm: Convert VFP VNMLS to decodetree
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target/arm: Convert VFP VNMLA to decodetree
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target/arm: Convert VMUL to decodetree
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target/arm: Convert VNMUL to decodetree
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target/arm: Convert VADD to decodetree
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target/arm: Convert VSUB to decodetree
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target/arm: Convert VDIV to decodetree
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target/arm: Convert VFP fused multiply-add insns to decodetree
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target/arm: Convert VMOV (imm) to decodetree
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target/arm: Convert VABS to decodetree
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target/arm: Convert VNEG to decodetree
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target/arm: Convert VSQRT to decodetree
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target/arm: Convert VMOV (register) to decodetree
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target/arm: Convert VFP comparison insns to decodetree
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target/arm: Convert the VCVT-from-f16 insns to decodetree
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target/arm: Convert the VCVT-to-f16 insns to decodetree
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target/arm: Convert VFP round insns to decodetree
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target/arm: Convert double-single precision conversion insns to decodetree
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target/arm: Convert integer-to-float insns to decodetree
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target/arm: Convert VJCVT to decodetree
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target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree
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target/arm: Convert float-to-integer VCVT insns to decodetree
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target/arm: Fix short-vector increment behaviour
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Edgar E. Iglesias (8):
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Richard Henderson (3):
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net: cadence_gem: Disable TSU feature bit
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target/arm: Use tcg_gen_gvec_bitsel
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net: cadence_gem: Use uint32_t for 32bit descriptor words
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target/arm: Fix output of PAuth Auth
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net: cadence_gem: Add macro with max number of descriptor words
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decodetree: Fix comparison of Field
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net: cadence_gem: Add support for extended descriptors
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net: cadence_gem: Add support for selecting the DMA MemoryRegion
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net: cadence_gem: Implement support for 64bit descriptor addresses
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target-arm: powerctl: Enable HVC when starting CPUs to EL2
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target/arm: Add the Cortex-A72
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Jerome Forissier (1):
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target/arm/Makefile.objs | 13 +
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hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART
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tests/tcg/aarch64/Makefile.target | 2 +-
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target/arm/cpu.h | 11 +
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target/arm/translate-a64.h | 2 +
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target/arm/translate.h | 3 -
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hw/arm/smmuv3.c | 2 +-
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hw/core/bus.c | 21 +-
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target/arm/cpu.c | 6 +
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target/arm/helper.c | 75 +-
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target/arm/pauth_helper.c | 4 +-
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target/arm/translate-a64.c | 15 +-
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target/arm/translate-vfp.inc.c | 2672 +++++++++++++++++++++++++++++++++++++
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target/arm/translate.c | 1581 +---------------------
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tests/tcg/aarch64/pauth-2.c | 61 +
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scripts/decodetree.py | 2 +-
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target/arm/vfp-uncond.decode | 63 +
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target/arm/vfp.decode | 242 ++++
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17 files changed, 3203 insertions(+), 1572 deletions(-)
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create mode 100644 target/arm/translate-vfp.inc.c
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create mode 100644 tests/tcg/aarch64/pauth-2.c
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create mode 100644 target/arm/vfp-uncond.decode
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create mode 100644 target/arm/vfp.decode
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Peter Maydell (2):
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target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write
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coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls
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Richard Henderson (4):
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target/arm: Fix aarch64_sve_change_el wrt EL0
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target/arm: Define fields of ISAR registers
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target/arm: Align cortex-r5 id_isar0
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target/arm: Fix cortex-a7 id_isar0
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include/hw/net/cadence_gem.h | 7 +-
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target/arm/cpu.h | 95 ++++++++++++++-
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hw/arm/virt.c | 4 +
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hw/net/cadence_gem.c | 185 ++++++++++++++++++++---------
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target/arm/arm-powerctl.c | 10 ++
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target/arm/cpu.c | 7 +-
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target/arm/cpu64.c | 66 +++++++++-
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target/arm/helper.c | 27 +++--
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target/arm/op_helper.c | 6 +-
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scripts/coccinelle/inplace-byteswaps.cocci | 65 ++++++++++
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10 files changed, 402 insertions(+), 70 deletions(-)
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create mode 100644 scripts/coccinelle/inplace-byteswaps.cocci
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