1
Less than a day of post-3.0 code review and already enough
1
First arm pullreq for 7.1. The bulk of this is the qemu_split_irq
2
patches for another pullreq :-)
2
removal.
3
4
I have enough stuff in my to-review queue that I expect to do another
5
pullreq early next week, but 31 patches is enough to not hang on to.
3
6
4
thanks
7
thanks
5
-- PMM
8
-- PMM
6
9
7
The following changes since commit c542a9f9794ec8e0bc3fcf5956d3cc8bce667789:
10
The following changes since commit 9c125d17e9402c232c46610802e5931b3639d77b:
8
11
9
Merge remote-tracking branch 'remotes/armbru/tags/pull-tests-2018-08-16' into staging (2018-08-16 09:50:54 +0100)
12
Merge tag 'pull-tcg-20220420' of https://gitlab.com/rth7680/qemu into staging (2022-04-20 16:43:11 -0700)
10
13
11
are available in the Git repository at:
14
are available in the Git repository at:
12
15
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180816
16
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220421
14
17
15
for you to fetch changes up to fcf13ca556f462b52956059bf8fa622bc8575edb:
18
for you to fetch changes up to 5b415dd61bdbf61fb4be0e9f1a7172b8bce682c6:
16
19
17
hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj() (2018-08-16 14:29:58 +0100)
20
hw/arm: Use bit fields for NPCM7XX PWRON STRAPs (2022-04-21 11:37:05 +0100)
18
21
19
----------------------------------------------------------------
22
----------------------------------------------------------------
20
target-arm queue:
23
target-arm queue:
21
* Fixes for various bugs in SVE instructions
24
* hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
22
* Add model of Freescale i.MX6 UltraLite 14x14 EVK Board
25
* versal: Add the Cortex-R5s in the Real-Time Processing Unit (RPU) subsystem
23
* hw/arm: make bitbanded IO optional on ARMv7-M
26
* versal: model enough of the Clock/Reset Low-power domain (CRL) to allow control of the Cortex-R5s
24
* Add model of Cortex-M0 CPU
27
* xlnx-zynqmp: Connect 4 TTC timers
25
* Add support for loading Intel HEX files to the generic loader
28
* exynos4210: Refactor GIC/combiner code to stop using qemu_split_irq
26
* imx_spi: Unset XCH when TX FIFO becomes empty
29
* realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
27
* aspeed_sdmc: fix various bugs
30
* stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
28
* Fix bugs in Arm FP16 instruction support
31
* hw/core/irq: remove unused 'qemu_irq_split' function
29
* Fix aa64 FCADD and FCMLA decode
32
* npcm7xx: use symbolic constants for PWRON STRAP bit fields
30
* softfloat: Fix missing inexact for floating-point add
33
* virt: document impact of gic-version on max CPUs
31
* hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()
32
34
33
----------------------------------------------------------------
35
----------------------------------------------------------------
34
Cédric Le Goater (1):
36
Edgar E. Iglesias (6):
35
aspeed: add a max_ram_size property to the memory controller
37
timer: cadence_ttc: Break out header file to allow embedding
38
hw/arm/xlnx-zynqmp: Connect 4 TTC timers
39
hw/arm: versal: Create an APU CPU Cluster
40
hw/arm: versal: Add the Cortex-R5Fs
41
hw/misc: Add a model of the Xilinx Versal CRL
42
hw/arm: versal: Connect the CRL
36
43
37
Jean-Christophe Dubois (3):
44
Hao Wu (2):
38
i.MX6UL: Add i.MX6UL specific CCM device
45
hw/misc: Add PWRON STRAP bit fields in GCR module
39
i.MX6UL: Add i.MX6UL SOC
46
hw/arm: Use bit fields for NPCM7XX PWRON STRAPs
40
i.MX6UL: Add Freescale i.MX6 UltraLite 14x14 EVK Board
41
47
42
Joel Stanley (5):
48
Heinrich Schuchardt (1):
43
aspeed_sdmc: Extend number of valid registers
49
hw/arm/virt: impact of gic-version on max CPUs
44
aspeed_sdmc: Fix saved values
45
aspeed_sdmc: Set 'cache initial sequence' always true
46
aspeed_sdmc: Init status always idle
47
aspeed_sdmc: Handle ECC training
48
50
49
Richard Henderson (13):
51
Peter Maydell (19):
50
target/arm: Fix typo in helper_sve_ld1hss_r
52
hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF
51
target/arm: Fix sign-extension in sve do_ldr/do_str
53
hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device
52
target/arm: Fix offset for LD1R instructions
54
hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
53
target/arm: Fix offset scaling for LD_zprr and ST_zprr
55
hw/arm/exynos4210: Put a9mpcore device into state struct
54
target/arm: Reformat integer register dump
56
hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct
55
target/arm: Dump SVE state if enabled
57
hw/arm/exynos4210: Coalesce board_irqs and irq_table
56
target/arm: Add sve-max-vq cpu property to -cpu max
58
hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[]
57
target/arm: Adjust FPCR_MASK for FZ16
59
hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c
58
target/arm: Ignore float_flag_input_denormal from fp_status_f16
60
hw/arm/exynos4210: Put external GIC into state struct
59
target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h
61
hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct
60
target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half
62
hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c
61
target/arm: Fix aa64 FCADD and FCMLA decode
63
hw/arm/exynos4210: Delete unused macro definitions
62
softfloat: Fix missing inexact for floating-point add
64
hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs()
65
hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines
66
hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners
67
hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs
68
hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs()
69
hw/arm/exynos4210: Put combiners into state struct
70
hw/arm/exynos4210: Drop Exynos4210Irq struct
63
71
64
Stefan Hajnoczi (4):
72
Zongyuan Li (3):
65
hw/arm: make bitbanded IO optional on ARMv7-M
73
hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
66
target/arm: add "cortex-m0" CPU model
74
hw/arm/stellaris: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ'
67
loader: extract rom_free() function
75
hw/core/irq: remove unused 'qemu_irq_split' function
68
loader: add rom transaction API
69
76
70
Su Hang (2):
77
docs/system/arm/virt.rst | 4 +-
71
loader: Implement .hex file loader
78
include/hw/arm/exynos4210.h | 50 ++--
72
Add QTest testcase for the Intel Hexadecimal
79
include/hw/arm/xlnx-versal.h | 16 ++
73
80
include/hw/arm/xlnx-zynqmp.h | 4 +
74
Thomas Huth (1):
81
include/hw/intc/exynos4210_combiner.h | 57 +++++
75
hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()
82
include/hw/intc/exynos4210_gic.h | 43 ++++
76
83
include/hw/irq.h | 5 -
77
Trent Piepho (1):
84
include/hw/misc/npcm7xx_gcr.h | 30 +++
78
imx_spi: Unset XCH when TX FIFO becomes empty
85
include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++++
79
86
include/hw/timer/cadence_ttc.h | 54 +++++
80
configure | 4 +
87
hw/arm/exynos4210.c | 430 ++++++++++++++++++++++++++++++----
81
hw/arm/Makefile.objs | 1 +
88
hw/arm/npcm7xx_boards.c | 24 +-
82
hw/misc/Makefile.objs | 1 +
89
hw/arm/realview.c | 33 ++-
83
tests/Makefile.include | 2 +
90
hw/arm/stellaris.c | 15 +-
84
include/hw/arm/armv7m.h | 2 +
91
hw/arm/virt.c | 7 +
85
include/hw/arm/fsl-imx6ul.h | 339 ++++++++++++++
92
hw/arm/xlnx-versal-virt.c | 6 +-
86
include/hw/loader.h | 31 ++
93
hw/arm/xlnx-versal.c | 99 +++++++-
87
include/hw/misc/aspeed_sdmc.h | 4 +-
94
hw/arm/xlnx-zynqmp.c | 22 ++
88
include/hw/misc/imx6ul_ccm.h | 226 +++++++++
95
hw/core/irq.c | 15 --
89
target/arm/cpu.h | 5 +-
96
hw/intc/exynos4210_combiner.c | 108 +--------
90
fpu/softfloat.c | 2 +-
97
hw/intc/exynos4210_gic.c | 344 +--------------------------
91
hw/arm/armv7m.c | 37 +-
98
hw/misc/xlnx-versal-crl.c | 421 +++++++++++++++++++++++++++++++++
92
hw/arm/aspeed.c | 31 ++
99
hw/timer/cadence_ttc.c | 32 +--
93
hw/arm/aspeed_soc.c | 2 +
100
MAINTAINERS | 2 +-
94
hw/arm/fsl-imx6ul.c | 617 ++++++++++++++++++++++++
101
hw/misc/meson.build | 1 +
95
hw/arm/mcimx6ul-evk.c | 85 ++++
102
25 files changed, 1457 insertions(+), 600 deletions(-)
96
hw/arm/mps2-tz.c | 32 +-
103
create mode 100644 include/hw/intc/exynos4210_combiner.h
97
hw/arm/mps2.c | 1 +
104
create mode 100644 include/hw/intc/exynos4210_gic.h
98
hw/arm/msf2-soc.c | 1 +
105
create mode 100644 include/hw/misc/xlnx-versal-crl.h
99
hw/arm/stellaris.c | 1 +
106
create mode 100644 include/hw/timer/cadence_ttc.h
100
hw/arm/stm32f205_soc.c | 1 +
107
create mode 100644 hw/misc/xlnx-versal-crl.c
101
hw/core/generic-loader.c | 4 +
102
hw/core/loader.c | 302 +++++++++++-
103
hw/misc/aspeed_sdmc.c | 55 ++-
104
hw/misc/imx6ul_ccm.c | 886 +++++++++++++++++++++++++++++++++++
105
hw/ssi/imx_spi.c | 3 +-
106
linux-user/syscall.c | 19 +-
107
target/arm/cpu.c | 17 +-
108
target/arm/cpu64.c | 29 ++
109
target/arm/helper.c | 18 +-
110
target/arm/sve_helper.c | 4 +-
111
target/arm/translate-a64.c | 120 ++++-
112
target/arm/translate-sve.c | 30 +-
113
tests/hexloader-test.c | 45 ++
114
MAINTAINERS | 6 +
115
default-configs/arm-softmmu.mak | 1 +
116
hw/misc/trace-events | 7 +
117
tests/hex-loader-check-data/test.hex | 18 +
118
38 files changed, 2863 insertions(+), 126 deletions(-)
119
create mode 100644 include/hw/arm/fsl-imx6ul.h
120
create mode 100644 include/hw/misc/imx6ul_ccm.h
121
create mode 100644 hw/arm/fsl-imx6ul.c
122
create mode 100644 hw/arm/mcimx6ul-evk.c
123
create mode 100644 hw/misc/imx6ul_ccm.c
124
create mode 100644 tests/hexloader-test.c
125
create mode 100644 tests/hex-loader-check-data/test.hex
126
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
It's not possible to provide the guest with the Security extensions
2
(TrustZone) when using KVM or HVF, because the hardware
3
virtualization extensions don't permit running EL3 guest code.
4
However, we weren't checking for this combination, with the result
5
that QEMU would assert if you tried it:
2
6
3
When support for FZ16 was added, we failed to include the bit
7
$ qemu-system-aarch64 -enable-kvm -machine virt,secure=on -cpu host -display none
4
within FPCR_MASK, which means that it could never be set.
8
Unexpected error in object_property_find_err() at ../../qom/object.c:1304:
5
Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.
9
qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found
10
Aborted
6
11
7
Fixes: d81ce0ef2c4
12
Check for this combination of options and report an error, in the
8
Cc: qemu-stable@nongnu.org (3.0.1)
13
same way we already do for attempts to give a KVM or HVF guest the
9
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
14
Virtualization or MTE extensions. Now we will report:
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
11
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
16
qemu-system-aarch64: mach-virt: KVM does not support providing Security extensions (TrustZone) to the guest CPU
12
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
17
13
Message-id: 20180810193129.1556-2-richard.henderson@linaro.org
18
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
21
Message-id: 20220404155301.566542-1-peter.maydell@linaro.org
15
---
22
---
16
target/arm/cpu.h | 2 +-
23
hw/arm/virt.c | 7 +++++++
17
target/arm/helper.c | 5 +++++
24
1 file changed, 7 insertions(+)
18
2 files changed, 6 insertions(+), 1 deletion(-)
19
25
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
26
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
21
index XXXXXXX..XXXXXXX 100644
27
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
28
--- a/hw/arm/virt.c
23
+++ b/target/arm/cpu.h
29
+++ b/hw/arm/virt.c
24
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
30
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
25
* we store the underlying state in fpscr and just mask on read/write.
31
exit(1);
26
*/
32
}
27
#define FPSR_MASK 0xf800009f
33
28
-#define FPCR_MASK 0x07f79f00
34
+ if (vms->secure && (kvm_enabled() || hvf_enabled())) {
29
+#define FPCR_MASK 0x07ff9f00
35
+ error_report("mach-virt: %s does not support providing "
30
36
+ "Security extensions (TrustZone) to the guest CPU",
31
#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
37
+ kvm_enabled() ? "KVM" : "HVF");
32
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
38
+ exit(1);
33
diff --git a/target/arm/helper.c b/target/arm/helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper.c
36
+++ b/target/arm/helper.c
37
@@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
38
int i;
39
uint32_t changed;
40
41
+ /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
42
+ if (!arm_feature(env, ARM_FEATURE_V8_FP16)) {
43
+ val &= ~FPCR_FZ16;
44
+ }
39
+ }
45
+
40
+
46
changed = env->vfp.xregs[ARM_VFP_FPSCR];
41
if (vms->virt && (kvm_enabled() || hvf_enabled())) {
47
env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
42
error_report("mach-virt: %s does not support providing "
48
env->vfp.vec_len = (val >> 16) & 7;
43
"Virtualization extensions to the guest CPU",
49
--
44
--
50
2.18.0
45
2.25.1
51
52
diff view generated by jsdifflib
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
2
2
3
Tested by booting linux 4.18 (built using imx_v6_v7_defconfig) on the
3
Break out header file to allow embedding of the the TTC.
4
emulated board.
5
4
6
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
7
Message-id: 3f8eb4300206634dc01e04b12f65b73c0ad2f955.1532984236.git.jcd@tribudubois.net
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
9
Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
hw/arm/Makefile.objs | 2 +-
12
include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++
12
hw/arm/mcimx6ul-evk.c | 85 +++++++++++++++++++++++++++++++++++++++++++
13
hw/timer/cadence_ttc.c | 32 ++------------------
13
2 files changed, 86 insertions(+), 1 deletion(-)
14
2 files changed, 56 insertions(+), 30 deletions(-)
14
create mode 100644 hw/arm/mcimx6ul-evk.c
15
create mode 100644 include/hw/timer/cadence_ttc.h
15
16
16
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
17
diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Makefile.objs
19
+++ b/hw/arm/Makefile.objs
20
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
21
obj-$(CONFIG_IOTKIT) += iotkit.o
22
obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o
23
obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
24
-obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o
25
+obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o mcimx6ul-evk.o
26
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
27
new file mode 100644
18
new file mode 100644
28
index XXXXXXX..XXXXXXX
19
index XXXXXXX..XXXXXXX
29
--- /dev/null
20
--- /dev/null
30
+++ b/hw/arm/mcimx6ul-evk.c
21
+++ b/include/hw/timer/cadence_ttc.h
31
@@ -XXX,XX +XXX,XX @@
22
@@ -XXX,XX +XXX,XX @@
32
+/*
23
+/*
33
+ * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
24
+ * Xilinx Zynq cadence TTC model
34
+ *
25
+ *
35
+ * MCIMX6UL_EVK Board System emulation.
26
+ * Copyright (c) 2011 Xilinx Inc.
27
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
28
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
29
+ * Written By Haibing Ma
30
+ * M. Habib
36
+ *
31
+ *
37
+ * This code is licensed under the GPL, version 2 or later.
32
+ * This program is free software; you can redistribute it and/or
38
+ * See the file `COPYING' in the top level directory.
33
+ * modify it under the terms of the GNU General Public License
34
+ * as published by the Free Software Foundation; either version
35
+ * 2 of the License, or (at your option) any later version.
39
+ *
36
+ *
40
+ * It (partially) emulates a mcimx6ul_evk board, with a Freescale
37
+ * You should have received a copy of the GNU General Public License along
41
+ * i.MX6ul SoC
38
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
42
+ */
39
+ */
40
+#ifndef HW_TIMER_CADENCE_TTC_H
41
+#define HW_TIMER_CADENCE_TTC_H
43
+
42
+
44
+#include "qemu/osdep.h"
43
+#include "hw/sysbus.h"
45
+#include "qapi/error.h"
44
+#include "qemu/timer.h"
46
+#include "qemu-common.h"
47
+#include "hw/arm/fsl-imx6ul.h"
48
+#include "hw/boards.h"
49
+#include "sysemu/sysemu.h"
50
+#include "qemu/error-report.h"
51
+#include "sysemu/qtest.h"
52
+
45
+
53
+typedef struct {
46
+typedef struct {
54
+ FslIMX6ULState soc;
47
+ QEMUTimer *timer;
55
+ MemoryRegion ram;
48
+ int freq;
56
+} MCIMX6ULEVK;
57
+
49
+
58
+static void mcimx6ul_evk_init(MachineState *machine)
50
+ uint32_t reg_clock;
59
+{
51
+ uint32_t reg_count;
60
+ static struct arm_boot_info boot_info;
52
+ uint32_t reg_value;
61
+ MCIMX6ULEVK *s = g_new0(MCIMX6ULEVK, 1);
53
+ uint16_t reg_interval;
62
+ int i;
54
+ uint16_t reg_match[3];
55
+ uint32_t reg_intr;
56
+ uint32_t reg_intr_en;
57
+ uint32_t reg_event_ctrl;
58
+ uint32_t reg_event;
63
+
59
+
64
+ if (machine->ram_size > FSL_IMX6UL_MMDC_SIZE) {
60
+ uint64_t cpu_time;
65
+ error_report("RAM size " RAM_ADDR_FMT " above max supported (%08x)",
61
+ unsigned int cpu_time_valid;
66
+ machine->ram_size, FSL_IMX6UL_MMDC_SIZE);
67
+ exit(1);
68
+ }
69
+
62
+
70
+ boot_info = (struct arm_boot_info) {
63
+ qemu_irq irq;
71
+ .loader_start = FSL_IMX6UL_MMDC_ADDR,
64
+} CadenceTimerState;
72
+ .board_id = -1,
73
+ .ram_size = machine->ram_size,
74
+ .kernel_filename = machine->kernel_filename,
75
+ .kernel_cmdline = machine->kernel_cmdline,
76
+ .initrd_filename = machine->initrd_filename,
77
+ .nb_cpus = smp_cpus,
78
+ };
79
+
65
+
80
+ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
66
+#define TYPE_CADENCE_TTC "cadence_ttc"
81
+ TYPE_FSL_IMX6UL, &error_fatal, NULL);
67
+OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
82
+
68
+
83
+ object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
69
+struct CadenceTTCState {
70
+ SysBusDevice parent_obj;
84
+
71
+
85
+ memory_region_allocate_system_memory(&s->ram, NULL, "mcimx6ul-evk.ram",
72
+ MemoryRegion iomem;
86
+ machine->ram_size);
73
+ CadenceTimerState timer[3];
87
+ memory_region_add_subregion(get_system_memory(),
74
+};
88
+ FSL_IMX6UL_MMDC_ADDR, &s->ram);
89
+
75
+
90
+ for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
76
+#endif
91
+ BusState *bus;
77
diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
92
+ DeviceState *carddev;
78
index XXXXXXX..XXXXXXX 100644
93
+ DriveInfo *di;
79
--- a/hw/timer/cadence_ttc.c
94
+ BlockBackend *blk;
80
+++ b/hw/timer/cadence_ttc.c
81
@@ -XXX,XX +XXX,XX @@
82
#include "qemu/timer.h"
83
#include "qom/object.h"
84
85
+#include "hw/timer/cadence_ttc.h"
95
+
86
+
96
+ di = drive_get_next(IF_SD);
87
#ifdef CADENCE_TTC_ERR_DEBUG
97
+ blk = di ? blk_by_legacy_dinfo(di) : NULL;
88
#define DB_PRINT(...) do { \
98
+ bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus");
89
fprintf(stderr, ": %s: ", __func__); \
99
+ carddev = qdev_create(bus, TYPE_SD_CARD);
90
@@ -XXX,XX +XXX,XX @@
100
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
91
#define CLOCK_CTRL_PS_EN 0x00000001
101
+ object_property_set_bool(OBJECT(carddev), true,
92
#define CLOCK_CTRL_PS_V 0x0000001e
102
+ "realized", &error_fatal);
93
103
+ }
94
-typedef struct {
104
+
95
- QEMUTimer *timer;
105
+ if (!qtest_enabled()) {
96
- int freq;
106
+ arm_load_kernel(&s->soc.cpu[0], &boot_info);
97
-
107
+ }
98
- uint32_t reg_clock;
108
+}
99
- uint32_t reg_count;
109
+
100
- uint32_t reg_value;
110
+static void mcimx6ul_evk_machine_init(MachineClass *mc)
101
- uint16_t reg_interval;
111
+{
102
- uint16_t reg_match[3];
112
+ mc->desc = "Freescale i.MX6UL Evaluation Kit (Cortex A7)";
103
- uint32_t reg_intr;
113
+ mc->init = mcimx6ul_evk_init;
104
- uint32_t reg_intr_en;
114
+ mc->max_cpus = FSL_IMX6UL_NUM_CPUS;
105
- uint32_t reg_event_ctrl;
115
+}
106
- uint32_t reg_event;
116
+DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init)
107
-
108
- uint64_t cpu_time;
109
- unsigned int cpu_time_valid;
110
-
111
- qemu_irq irq;
112
-} CadenceTimerState;
113
-
114
-#define TYPE_CADENCE_TTC "cadence_ttc"
115
-OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
116
-
117
-struct CadenceTTCState {
118
- SysBusDevice parent_obj;
119
-
120
- MemoryRegion iomem;
121
- CadenceTimerState timer[3];
122
-};
123
-
124
static void cadence_timer_update(CadenceTimerState *s)
125
{
126
qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
117
--
127
--
118
2.18.0
128
2.25.1
119
120
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
2
2
3
The ast2500 SDRAM training routine busy waits on the 'init cycle busy
3
Connect the 4 TTC timers on the ZynqMP.
4
state' bit in DDR PHY Control/Status register #1 (MCR60).
5
4
6
This ensures the bit always reads zero, and allows training to
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
7
complete with upstream u-boot on the ast2500-evb.
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
9
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
10
Reviewed-by: Cédric Le Goater <clg@kaod.org>
9
Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com
11
Tested-by: Cédric Le Goater <clg@kaod.org>
12
Message-id: 20180807075757.7242-5-joel@jms.id.au
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
hw/misc/aspeed_sdmc.c | 15 +++++++++++++++
12
include/hw/arm/xlnx-zynqmp.h | 4 ++++
16
1 file changed, 15 insertions(+)
13
hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++
14
2 files changed, 26 insertions(+)
17
15
18
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
16
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/misc/aspeed_sdmc.c
18
--- a/include/hw/arm/xlnx-zynqmp.h
21
+++ b/hw/misc/aspeed_sdmc.c
19
+++ b/include/hw/arm/xlnx-zynqmp.h
22
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
23
/* Configuration Register */
21
#include "hw/or-irq.h"
24
#define R_CONF (0x04 / 4)
22
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
25
23
#include "hw/misc/xlnx-zynqmp-crf.h"
26
+/* Control/Status Register #1 (ast2500) */
24
+#include "hw/timer/cadence_ttc.h"
27
+#define R_STATUS1 (0x60 / 4)
25
28
+#define PHY_BUSY_STATE BIT(0)
26
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
27
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
28
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
29
#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
30
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
31
32
+#define XLNX_ZYNQMP_NUM_TTC 4
29
+
33
+
30
/*
34
/*
31
* Configuration register Ox4 (for Aspeed AST2400 SOC)
35
* Unimplemented mmio regions needed to boot some images.
32
*
36
*/
33
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
37
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
34
g_assert_not_reached();
38
qemu_or_irq qspi_irq_orgate;
35
}
39
XlnxZynqMPAPUCtrl apu_ctrl;
36
}
40
XlnxZynqMPCRF crf;
37
+ if (s->silicon_rev == AST2500_A0_SILICON_REV ||
41
+ CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
38
+ s->silicon_rev == AST2500_A1_SILICON_REV) {
42
39
+ switch (addr) {
43
char *boot_cpu;
40
+ case R_STATUS1:
44
ARMCPU *boot_cpu_ptr;
41
+ /* Will never return 'busy' */
45
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
42
+ data &= ~PHY_BUSY_STATE;
46
index XXXXXXX..XXXXXXX 100644
43
+ break;
47
--- a/hw/arm/xlnx-zynqmp.c
44
+ default:
48
+++ b/hw/arm/xlnx-zynqmp.c
45
+ break;
49
@@ -XXX,XX +XXX,XX @@
50
#define APU_ADDR 0xfd5c0000
51
#define APU_IRQ 153
52
53
+#define TTC0_ADDR 0xFF110000
54
+#define TTC0_IRQ 36
55
+
56
#define IPI_ADDR 0xFF300000
57
#define IPI_IRQ 64
58
59
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
60
sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
61
}
62
63
+static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
64
+{
65
+ SysBusDevice *sbd;
66
+ int i, irq;
67
+
68
+ for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
69
+ object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
70
+ TYPE_CADENCE_TTC);
71
+ sbd = SYS_BUS_DEVICE(&s->ttc[i]);
72
+
73
+ sysbus_realize(sbd, &error_fatal);
74
+ sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
75
+ for (irq = 0; irq < 3; irq++) {
76
+ sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
46
+ }
77
+ }
47
+ }
78
+ }
48
79
+}
49
s->regs[addr] = data;
80
+
50
}
81
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
82
{
83
static const struct UnimpInfo {
84
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
85
xlnx_zynqmp_create_efuse(s, gic_spi);
86
xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
87
xlnx_zynqmp_create_crf(s, gic_spi);
88
+ xlnx_zynqmp_create_ttc(s, gic_spi);
89
xlnx_zynqmp_create_unimp_mmio(s);
90
91
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
51
--
92
--
52
2.18.0
93
2.25.1
53
54
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
2
2
3
For 0x1.0000000000003p+0 + 0x1.ffffffep+14 = 0x1.0001fffp+15
3
Create an APU CPU Cluster. This is in preparation to add the RPU.
4
we dropped the sticky bit and so failed to raise inexact.
5
4
6
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
8
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
7
Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com
9
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Message-id: 20180810193129.1556-7-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
9
---
13
fpu/softfloat.c | 2 +-
10
include/hw/arm/xlnx-versal.h | 2 ++
14
1 file changed, 1 insertion(+), 1 deletion(-)
11
hw/arm/xlnx-versal.c | 9 ++++++++-
12
2 files changed, 10 insertions(+), 1 deletion(-)
15
13
16
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
14
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/fpu/softfloat.c
16
--- a/include/hw/arm/xlnx-versal.h
19
+++ b/fpu/softfloat.c
17
+++ b/include/hw/arm/xlnx-versal.h
20
@@ -XXX,XX +XXX,XX @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract,
18
@@ -XXX,XX +XXX,XX @@
21
}
19
22
a.frac += b.frac;
20
#include "hw/sysbus.h"
23
if (a.frac & DECOMPOSED_OVERFLOW_BIT) {
21
#include "hw/arm/boot.h"
24
- a.frac >>= 1;
22
+#include "hw/cpu/cluster.h"
25
+ shift64RightJamming(a.frac, 1, &a.frac);
23
#include "hw/or-irq.h"
26
a.exp += 1;
24
#include "hw/sd/sdhci.h"
27
}
25
#include "hw/intc/arm_gicv3.h"
28
return a;
26
@@ -XXX,XX +XXX,XX @@ struct Versal {
27
struct {
28
struct {
29
MemoryRegion mr;
30
+ CPUClusterState cluster;
31
ARMCPU cpu[XLNX_VERSAL_NR_ACPUS];
32
GICv3State gic;
33
} apu;
34
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/arm/xlnx-versal.c
37
+++ b/hw/arm/xlnx-versal.c
38
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
39
{
40
int i;
41
42
+ object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster,
43
+ TYPE_CPU_CLUSTER);
44
+ qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0);
45
+
46
for (i = 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) {
47
Object *obj;
48
49
- object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i],
50
+ object_initialize_child(OBJECT(&s->fpd.apu.cluster),
51
+ "apu-cpu[*]", &s->fpd.apu.cpu[i],
52
XLNX_VERSAL_ACPU_TYPE);
53
obj = OBJECT(&s->fpd.apu.cpu[i]);
54
if (i) {
55
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_cpus(Versal *s)
56
&error_abort);
57
qdev_realize(DEVICE(obj), NULL, &error_fatal);
58
}
59
+
60
+ qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal);
61
}
62
63
static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
29
--
64
--
30
2.18.0
65
2.25.1
31
32
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
2
2
3
Also fold the FPCR/FPSR state onto the same line as PSTATE,
3
Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit)
4
and mention but do not dump disabled FPU state.
4
subsystem.
5
5
6
Cc: qemu-stable@nongnu.org (3.0.1)
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/translate-a64.c | 95 +++++++++++++++++++++++++++++++++-----
11
include/hw/arm/xlnx-versal.h | 10 ++++++++++
13
1 file changed, 83 insertions(+), 12 deletions(-)
12
hw/arm/xlnx-versal-virt.c | 6 +++---
13
hw/arm/xlnx-versal.c | 36 ++++++++++++++++++++++++++++++++++++
14
3 files changed, 49 insertions(+), 3 deletions(-)
14
15
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
--- a/include/hw/arm/xlnx-versal.h
18
+++ b/target/arm/translate-a64.c
19
+++ b/include/hw/arm/xlnx-versal.h
19
@@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
20
@@ -XXX,XX +XXX,XX @@
20
} else {
21
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
21
ns_status = "";
22
22
}
23
#define XLNX_VERSAL_NR_ACPUS 2
23
-
24
+#define XLNX_VERSAL_NR_RCPUS 2
24
- cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
25
#define XLNX_VERSAL_NR_UARTS 2
25
+ cpu_fprintf(f, "PSTATE=%08x %c%c%c%c %sEL%d%c",
26
#define XLNX_VERSAL_NR_GEMS 2
26
psr,
27
#define XLNX_VERSAL_NR_ADMAS 8
27
psr & PSTATE_N ? 'N' : '-',
28
@@ -XXX,XX +XXX,XX @@ struct Versal {
28
psr & PSTATE_Z ? 'Z' : '-',
29
VersalUsb2 usb;
29
@@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
30
} iou;
30
el,
31
31
psr & PSTATE_SP ? 'h' : 't');
32
+ /* Real-time Processing Unit. */
32
33
+ struct {
33
- if (flags & CPU_DUMP_FPU) {
34
+ MemoryRegion mr;
34
- int numvfpregs = 32;
35
+ MemoryRegion mr_ps_alias;
35
- for (i = 0; i < numvfpregs; i++) {
36
- uint64_t *q = aa64_vfp_qreg(env, i);
37
- uint64_t vlo = q[0];
38
- uint64_t vhi = q[1];
39
- cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "%c",
40
- i, vhi, vlo, (i & 1 ? '\n' : ' '));
41
+ if (!(flags & CPU_DUMP_FPU)) {
42
+ cpu_fprintf(f, "\n");
43
+ return;
44
+ }
45
+ cpu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
46
+ vfp_get_fpcr(env), vfp_get_fpsr(env));
47
+
36
+
48
+ if (arm_feature(env, ARM_FEATURE_SVE)) {
37
+ CPUClusterState cluster;
49
+ int j, zcr_len = env->vfp.zcr_el[1] & 0xf; /* fix for system mode */
38
+ ARMCPU cpu[XLNX_VERSAL_NR_RCPUS];
39
+ } rpu;
50
+
40
+
51
+ for (i = 0; i <= FFR_PRED_NUM; i++) {
41
struct {
52
+ bool eol;
42
qemu_or_irq irq_orgate;
53
+ if (i == FFR_PRED_NUM) {
43
XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
54
+ cpu_fprintf(f, "FFR=");
44
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
55
+ /* It's last, so end the line. */
45
index XXXXXXX..XXXXXXX 100644
56
+ eol = true;
46
--- a/hw/arm/xlnx-versal-virt.c
57
+ } else {
47
+++ b/hw/arm/xlnx-versal-virt.c
58
+ cpu_fprintf(f, "P%02d=", i);
48
@@ -XXX,XX +XXX,XX @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
59
+ switch (zcr_len) {
49
60
+ case 0:
50
mc->desc = "Xilinx Versal Virtual development board";
61
+ eol = i % 8 == 7;
51
mc->init = versal_virt_init;
62
+ break;
52
- mc->min_cpus = XLNX_VERSAL_NR_ACPUS;
63
+ case 1:
53
- mc->max_cpus = XLNX_VERSAL_NR_ACPUS;
64
+ eol = i % 6 == 5;
54
- mc->default_cpus = XLNX_VERSAL_NR_ACPUS;
65
+ break;
55
+ mc->min_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
66
+ case 2:
56
+ mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
67
+ case 3:
57
+ mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
68
+ eol = i % 3 == 2;
58
mc->no_cdrom = true;
69
+ break;
59
mc->default_ram_id = "ddr";
70
+ default:
60
}
71
+ /* More than one quadword per predicate. */
61
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
72
+ eol = true;
62
index XXXXXXX..XXXXXXX 100644
73
+ break;
63
--- a/hw/arm/xlnx-versal.c
74
+ }
64
+++ b/hw/arm/xlnx-versal.c
75
+ }
65
@@ -XXX,XX +XXX,XX @@
76
+ for (j = zcr_len / 4; j >= 0; j--) {
66
#include "hw/sysbus.h"
77
+ int digits;
67
78
+ if (j * 4 + 4 <= zcr_len + 1) {
68
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
79
+ digits = 16;
69
+#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")
80
+ } else {
70
#define GEM_REVISION 0x40070106
81
+ digits = (zcr_len % 4 + 1) * 4;
71
82
+ }
72
#define VERSAL_NUM_PMC_APB_IRQS 3
83
+ cpu_fprintf(f, "%0*" PRIx64 "%s", digits,
73
@@ -XXX,XX +XXX,XX @@ static void versal_create_apu_gic(Versal *s, qemu_irq *pic)
84
+ env->vfp.pregs[i].p[j],
85
+ j ? ":" : eol ? "\n" : " ");
86
+ }
87
+ }
88
+
89
+ for (i = 0; i < 32; i++) {
90
+ if (zcr_len == 0) {
91
+ cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s",
92
+ i, env->vfp.zregs[i].d[1],
93
+ env->vfp.zregs[i].d[0], i & 1 ? "\n" : " ");
94
+ } else if (zcr_len == 1) {
95
+ cpu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64
96
+ ":%016" PRIx64 ":%016" PRIx64 "\n",
97
+ i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2],
98
+ env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]);
99
+ } else {
100
+ for (j = zcr_len; j >= 0; j--) {
101
+ bool odd = (zcr_len - j) % 2 != 0;
102
+ if (j == zcr_len) {
103
+ cpu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1);
104
+ } else if (!odd) {
105
+ if (j > 0) {
106
+ cpu_fprintf(f, " [%x-%x]=", j, j - 1);
107
+ } else {
108
+ cpu_fprintf(f, " [%x]=", j);
109
+ }
110
+ }
111
+ cpu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s",
112
+ env->vfp.zregs[i].d[j * 2 + 1],
113
+ env->vfp.zregs[i].d[j * 2],
114
+ odd || j == 0 ? "\n" : ":");
115
+ }
116
+ }
117
+ }
118
+ } else {
119
+ for (i = 0; i < 32; i++) {
120
+ uint64_t *q = aa64_vfp_qreg(env, i);
121
+ cpu_fprintf(f, "Q%02d=%016" PRIx64 ":%016" PRIx64 "%s",
122
+ i, q[1], q[0], (i & 1 ? "\n" : " "));
123
}
124
- cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
125
- vfp_get_fpcr(env), vfp_get_fpsr(env));
126
}
74
}
127
}
75
}
128
76
77
+static void versal_create_rpu_cpus(Versal *s)
78
+{
79
+ int i;
80
+
81
+ object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster,
82
+ TYPE_CPU_CLUSTER);
83
+ qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1);
84
+
85
+ for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
86
+ Object *obj;
87
+
88
+ object_initialize_child(OBJECT(&s->lpd.rpu.cluster),
89
+ "rpu-cpu[*]", &s->lpd.rpu.cpu[i],
90
+ XLNX_VERSAL_RCPU_TYPE);
91
+ obj = OBJECT(&s->lpd.rpu.cpu[i]);
92
+ object_property_set_bool(obj, "start-powered-off", true,
93
+ &error_abort);
94
+
95
+ object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abort);
96
+ object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.cpu),
97
+ &error_abort);
98
+ object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr),
99
+ &error_abort);
100
+ qdev_realize(DEVICE(obj), NULL, &error_fatal);
101
+ }
102
+
103
+ qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal);
104
+}
105
+
106
static void versal_create_uarts(Versal *s, qemu_irq *pic)
107
{
108
int i;
109
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
110
111
versal_create_apu_cpus(s);
112
versal_create_apu_gic(s, pic);
113
+ versal_create_rpu_cpus(s);
114
versal_create_uarts(s, pic);
115
versal_create_usbs(s, pic);
116
versal_create_gems(s, pic);
117
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
118
119
memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm, 0);
120
memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0);
121
+ memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0,
122
+ &s->lpd.rpu.mr_ps_alias, 0);
123
}
124
125
static void versal_init(Object *obj)
126
@@ -XXX,XX +XXX,XX @@ static void versal_init(Object *obj)
127
Versal *s = XLNX_VERSAL(obj);
128
129
memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX);
130
+ memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX);
131
memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX);
132
+ memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s),
133
+ "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX);
134
}
135
136
static Property versal_properties[] = {
129
--
137
--
130
2.18.0
138
2.25.1
131
132
diff view generated by jsdifflib
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
2
2
3
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
3
Add a model of the Xilinx Versal CRL.
4
Message-id: 34b6704ceb81b49e35ce1ad162bf758e5141ff87.1532984236.git.jcd@tribudubois.net
4
5
[PMM: fixed some comment typos etc]
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
8
Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
10
---
9
hw/misc/Makefile.objs | 1 +
11
include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++
10
include/hw/misc/imx6ul_ccm.h | 226 +++++++++
12
hw/misc/xlnx-versal-crl.c | 421 ++++++++++++++++++++++++++++++
11
hw/misc/imx6ul_ccm.c | 886 +++++++++++++++++++++++++++++++++++
13
hw/misc/meson.build | 1 +
12
hw/misc/trace-events | 7 +
14
3 files changed, 657 insertions(+)
13
4 files changed, 1120 insertions(+)
15
create mode 100644 include/hw/misc/xlnx-versal-crl.h
14
create mode 100644 include/hw/misc/imx6ul_ccm.h
16
create mode 100644 hw/misc/xlnx-versal-crl.c
15
create mode 100644 hw/misc/imx6ul_ccm.c
16
17
17
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
18
diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/Makefile.objs
20
+++ b/hw/misc/Makefile.objs
21
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IMX) += imx_ccm.o
22
obj-$(CONFIG_IMX) += imx31_ccm.o
23
obj-$(CONFIG_IMX) += imx25_ccm.o
24
obj-$(CONFIG_IMX) += imx6_ccm.o
25
+obj-$(CONFIG_IMX) += imx6ul_ccm.o
26
obj-$(CONFIG_IMX) += imx6_src.o
27
obj-$(CONFIG_IMX) += imx7_ccm.o
28
obj-$(CONFIG_IMX) += imx2_wdt.o
29
diff --git a/include/hw/misc/imx6ul_ccm.h b/include/hw/misc/imx6ul_ccm.h
30
new file mode 100644
19
new file mode 100644
31
index XXXXXXX..XXXXXXX
20
index XXXXXXX..XXXXXXX
32
--- /dev/null
21
--- /dev/null
33
+++ b/include/hw/misc/imx6ul_ccm.h
22
+++ b/include/hw/misc/xlnx-versal-crl.h
34
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
35
+/*
24
+/*
36
+ * IMX6UL Clock Control Module
25
+ * QEMU model of the Clock-Reset-LPD (CRL).
37
+ *
26
+ *
38
+ * Copyright (C) 2018 by Jean-Christophe Dubois <jcd@tribudubois.net>
27
+ * Copyright (c) 2022 Xilinx Inc.
28
+ * SPDX-License-Identifier: GPL-2.0-or-later
39
+ *
29
+ *
40
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
30
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
41
+ * See the COPYING file in the top-level directory.
42
+ */
31
+ */
43
+
32
+#ifndef HW_MISC_XLNX_VERSAL_CRL_H
44
+#ifndef IMX6UL_CCM_H
33
+#define HW_MISC_XLNX_VERSAL_CRL_H
45
+#define IMX6UL_CCM_H
34
+
46
+
35
+#include "hw/sysbus.h"
47
+#include "hw/misc/imx_ccm.h"
36
+#include "hw/register.h"
48
+#include "qemu/bitops.h"
37
+#include "target/arm/cpu.h"
49
+
38
+
50
+#define CCM_CCR 0
39
+#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl"
51
+#define CCM_CCDR 1
40
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)
52
+#define CCM_CSR 2
41
+
53
+#define CCM_CCSR 3
42
+REG32(ERR_CTRL, 0x0)
54
+#define CCM_CACRR 4
43
+ FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
55
+#define CCM_CBCDR 5
44
+REG32(IR_STATUS, 0x4)
56
+#define CCM_CBCMR 6
45
+ FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
57
+#define CCM_CSCMR1 7
46
+REG32(IR_MASK, 0x8)
58
+#define CCM_CSCMR2 8
47
+ FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
59
+#define CCM_CSCDR1 9
48
+REG32(IR_ENABLE, 0xc)
60
+#define CCM_CS1CDR 10
49
+ FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
61
+#define CCM_CS2CDR 11
50
+REG32(IR_DISABLE, 0x10)
62
+#define CCM_CDCDR 12
51
+ FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
63
+#define CCM_CHSCCDR 13
52
+REG32(WPROT, 0x1c)
64
+#define CCM_CSCDR2 14
53
+ FIELD(WPROT, ACTIVE, 0, 1)
65
+#define CCM_CSCDR3 15
54
+REG32(PLL_CLK_OTHER_DMN, 0x20)
66
+#define CCM_CDHIPR 18
55
+ FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
67
+#define CCM_CTOR 20
56
+REG32(RPLL_CTRL, 0x40)
68
+#define CCM_CLPCR 21
57
+ FIELD(RPLL_CTRL, POST_SRC, 24, 3)
69
+#define CCM_CISR 22
58
+ FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
70
+#define CCM_CIMR 23
59
+ FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2)
71
+#define CCM_CCOSR 24
60
+ FIELD(RPLL_CTRL, FBDIV, 8, 8)
72
+#define CCM_CGPR 25
61
+ FIELD(RPLL_CTRL, BYPASS, 3, 1)
73
+#define CCM_CCGR0 26
62
+ FIELD(RPLL_CTRL, RESET, 0, 1)
74
+#define CCM_CCGR1 27
63
+REG32(RPLL_CFG, 0x44)
75
+#define CCM_CCGR2 28
64
+ FIELD(RPLL_CFG, LOCK_DLY, 25, 7)
76
+#define CCM_CCGR3 29
65
+ FIELD(RPLL_CFG, LOCK_CNT, 13, 10)
77
+#define CCM_CCGR4 30
66
+ FIELD(RPLL_CFG, LFHF, 10, 2)
78
+#define CCM_CCGR5 31
67
+ FIELD(RPLL_CFG, CP, 5, 4)
79
+#define CCM_CCGR6 32
68
+ FIELD(RPLL_CFG, RES, 0, 4)
80
+#define CCM_CMEOR 34
69
+REG32(RPLL_FRAC_CFG, 0x48)
81
+#define CCM_MAX 35
70
+ FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1)
82
+
71
+ FIELD(RPLL_FRAC_CFG, SEED, 22, 3)
83
+#define CCM_ANALOG_PLL_ARM 0
72
+ FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1)
84
+#define CCM_ANALOG_PLL_ARM_SET 1
73
+ FIELD(RPLL_FRAC_CFG, ORDER, 18, 1)
85
+#define CCM_ANALOG_PLL_ARM_CLR 2
74
+ FIELD(RPLL_FRAC_CFG, DATA, 0, 16)
86
+#define CCM_ANALOG_PLL_ARM_TOG 3
75
+REG32(PLL_STATUS, 0x50)
87
+#define CCM_ANALOG_PLL_USB1 4
76
+ FIELD(PLL_STATUS, RPLL_STABLE, 2, 1)
88
+#define CCM_ANALOG_PLL_USB1_SET 5
77
+ FIELD(PLL_STATUS, RPLL_LOCK, 0, 1)
89
+#define CCM_ANALOG_PLL_USB1_CLR 6
78
+REG32(RPLL_TO_XPD_CTRL, 0x100)
90
+#define CCM_ANALOG_PLL_USB1_TOG 7
79
+ FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1)
91
+#define CCM_ANALOG_PLL_USB2 8
80
+ FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
92
+#define CCM_ANALOG_PLL_USB2_SET 9
81
+REG32(LPD_TOP_SWITCH_CTRL, 0x104)
93
+#define CCM_ANALOG_PLL_USB2_CLR 10
82
+ FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1)
94
+#define CCM_ANALOG_PLL_USB2_TOG 11
83
+ FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1)
95
+#define CCM_ANALOG_PLL_SYS 12
84
+ FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10)
96
+#define CCM_ANALOG_PLL_SYS_SET 13
85
+ FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
97
+#define CCM_ANALOG_PLL_SYS_CLR 14
86
+REG32(LPD_LSBUS_CTRL, 0x108)
98
+#define CCM_ANALOG_PLL_SYS_TOG 15
87
+ FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1)
99
+#define CCM_ANALOG_PLL_SYS_SS 16
88
+ FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10)
100
+#define CCM_ANALOG_PLL_SYS_NUM 20
89
+ FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3)
101
+#define CCM_ANALOG_PLL_SYS_DENOM 24
90
+REG32(CPU_R5_CTRL, 0x10c)
102
+#define CCM_ANALOG_PLL_AUDIO 28
91
+ FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1)
103
+#define CCM_ANALOG_PLL_AUDIO_SET 29
92
+ FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1)
104
+#define CCM_ANALOG_PLL_AUDIO_CLR 30
93
+ FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1)
105
+#define CCM_ANALOG_PLL_AUDIO_TOG 31
94
+ FIELD(CPU_R5_CTRL, CLKACT, 25, 1)
106
+#define CCM_ANALOG_PLL_AUDIO_NUM 32
95
+ FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10)
107
+#define CCM_ANALOG_PLL_AUDIO_DENOM 36
96
+ FIELD(CPU_R5_CTRL, SRCSEL, 0, 3)
108
+#define CCM_ANALOG_PLL_VIDEO 40
97
+REG32(IOU_SWITCH_CTRL, 0x114)
109
+#define CCM_ANALOG_PLL_VIDEO_SET 41
98
+ FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1)
110
+#define CCM_ANALOG_PLL_VIDEO_CLR 42
99
+ FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10)
111
+#define CCM_ANALOG_PLL_VIDEO_TOG 44
100
+ FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3)
112
+#define CCM_ANALOG_PLL_VIDEO_NUM 46
101
+REG32(GEM0_REF_CTRL, 0x118)
113
+#define CCM_ANALOG_PLL_VIDEO_DENOM 48
102
+ FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1)
114
+#define CCM_ANALOG_PLL_ENET 56
103
+ FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1)
115
+#define CCM_ANALOG_PLL_ENET_SET 57
104
+ FIELD(GEM0_REF_CTRL, CLKACT, 25, 1)
116
+#define CCM_ANALOG_PLL_ENET_CLR 58
105
+ FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10)
117
+#define CCM_ANALOG_PLL_ENET_TOG 59
106
+ FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3)
118
+#define CCM_ANALOG_PFD_480 60
107
+REG32(GEM1_REF_CTRL, 0x11c)
119
+#define CCM_ANALOG_PFD_480_SET 61
108
+ FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1)
120
+#define CCM_ANALOG_PFD_480_CLR 62
109
+ FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1)
121
+#define CCM_ANALOG_PFD_480_TOG 63
110
+ FIELD(GEM1_REF_CTRL, CLKACT, 25, 1)
122
+#define CCM_ANALOG_PFD_528 64
111
+ FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10)
123
+#define CCM_ANALOG_PFD_528_SET 65
112
+ FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3)
124
+#define CCM_ANALOG_PFD_528_CLR 66
113
+REG32(GEM_TSU_REF_CTRL, 0x120)
125
+#define CCM_ANALOG_PFD_528_TOG 67
114
+ FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1)
126
+
115
+ FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10)
127
+/* PMU registers */
116
+ FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3)
128
+#define PMU_REG_1P1 68
117
+REG32(USB0_BUS_REF_CTRL, 0x124)
129
+#define PMU_REG_3P0 72
118
+ FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1)
130
+#define PMU_REG_2P5 76
119
+ FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10)
131
+#define PMU_REG_CORE 80
120
+ FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3)
132
+
121
+REG32(UART0_REF_CTRL, 0x128)
133
+#define CCM_ANALOG_MISC0 84
122
+ FIELD(UART0_REF_CTRL, CLKACT, 25, 1)
134
+#define PMU_MISC0 CCM_ANALOG_MISC0
123
+ FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10)
135
+#define CCM_ANALOG_MISC0_SET 85
124
+ FIELD(UART0_REF_CTRL, SRCSEL, 0, 3)
136
+#define PMU_MISC0_SET CCM_ANALOG_MISC0_SET
125
+REG32(UART1_REF_CTRL, 0x12c)
137
+#define CCM_ANALOG_MISC0_CLR 86
126
+ FIELD(UART1_REF_CTRL, CLKACT, 25, 1)
138
+#define PMU_MISC0_CLR CCM_ANALOG_MISC0_CLR
127
+ FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10)
139
+#define CCM_ANALOG_MISC0_TOG 87
128
+ FIELD(UART1_REF_CTRL, SRCSEL, 0, 3)
140
+#define PMU_MISC0_TOG CCM_ANALOG_MISC0_TOG
129
+REG32(SPI0_REF_CTRL, 0x130)
141
+
130
+ FIELD(SPI0_REF_CTRL, CLKACT, 25, 1)
142
+#define CCM_ANALOG_MISC1 88
131
+ FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10)
143
+#define PMU_MISC1 CCM_ANALOG_MISC1
132
+ FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3)
144
+#define CCM_ANALOG_MISC1_SET 89
133
+REG32(SPI1_REF_CTRL, 0x134)
145
+#define PMU_MISC1_SET CCM_ANALOG_MISC1_SET
134
+ FIELD(SPI1_REF_CTRL, CLKACT, 25, 1)
146
+#define CCM_ANALOG_MISC1_CLR 90
135
+ FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10)
147
+#define PMU_MISC1_CLR CCM_ANALOG_MISC1_CLR
136
+ FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3)
148
+#define CCM_ANALOG_MISC1_TOG 91
137
+REG32(CAN0_REF_CTRL, 0x138)
149
+#define PMU_MISC1_TOG CCM_ANALOG_MISC1_TOG
138
+ FIELD(CAN0_REF_CTRL, CLKACT, 25, 1)
150
+
139
+ FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10)
151
+#define CCM_ANALOG_MISC2 92
140
+ FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3)
152
+#define PMU_MISC2 CCM_ANALOG_MISC2
141
+REG32(CAN1_REF_CTRL, 0x13c)
153
+#define CCM_ANALOG_MISC2_SET 93
142
+ FIELD(CAN1_REF_CTRL, CLKACT, 25, 1)
154
+#define PMU_MISC2_SET CCM_ANALOG_MISC2_SET
143
+ FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10)
155
+#define CCM_ANALOG_MISC2_CLR 94
144
+ FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3)
156
+#define PMU_MISC2_CLR CCM_ANALOG_MISC2_CLR
145
+REG32(I2C0_REF_CTRL, 0x140)
157
+#define CCM_ANALOG_MISC2_TOG 95
146
+ FIELD(I2C0_REF_CTRL, CLKACT, 25, 1)
158
+#define PMU_MISC2_TOG CCM_ANALOG_MISC2_TOG
147
+ FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10)
159
+
148
+ FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3)
160
+#define TEMPMON_TEMPSENSE0 96
149
+REG32(I2C1_REF_CTRL, 0x144)
161
+#define TEMPMON_TEMPSENSE0_SET 97
150
+ FIELD(I2C1_REF_CTRL, CLKACT, 25, 1)
162
+#define TEMPMON_TEMPSENSE0_CLR 98
151
+ FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10)
163
+#define TEMPMON_TEMPSENSE0_TOG 99
152
+ FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3)
164
+#define TEMPMON_TEMPSENSE1 100
153
+REG32(DBG_LPD_CTRL, 0x148)
165
+#define TEMPMON_TEMPSENSE1_SET 101
154
+ FIELD(DBG_LPD_CTRL, CLKACT, 25, 1)
166
+#define TEMPMON_TEMPSENSE1_CLR 102
155
+ FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10)
167
+#define TEMPMON_TEMPSENSE1_TOG 103
156
+ FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3)
168
+#define TEMPMON_TEMPSENSE2 164
157
+REG32(TIMESTAMP_REF_CTRL, 0x14c)
169
+#define TEMPMON_TEMPSENSE2_SET 165
158
+ FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1)
170
+#define TEMPMON_TEMPSENSE2_CLR 166
159
+ FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10)
171
+#define TEMPMON_TEMPSENSE2_TOG 167
160
+ FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3)
172
+
161
+REG32(CRL_SAFETY_CHK, 0x150)
173
+#define PMU_LOWPWR_CTRL 155
162
+REG32(PSM_REF_CTRL, 0x154)
174
+#define PMU_LOWPWR_CTRL_SET 156
163
+ FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10)
175
+#define PMU_LOWPWR_CTRL_CLR 157
164
+ FIELD(PSM_REF_CTRL, SRCSEL, 0, 3)
176
+#define PMU_LOWPWR_CTRL_TOG 158
165
+REG32(DBG_TSTMP_CTRL, 0x158)
177
+
166
+ FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1)
178
+#define USB_ANALOG_USB1_VBUS_DETECT 104
167
+ FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10)
179
+#define USB_ANALOG_USB1_VBUS_DETECT_SET 105
168
+ FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
180
+#define USB_ANALOG_USB1_VBUS_DETECT_CLR 106
169
+REG32(CPM_TOPSW_REF_CTRL, 0x15c)
181
+#define USB_ANALOG_USB1_VBUS_DETECT_TOG 107
170
+ FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1)
182
+#define USB_ANALOG_USB1_CHRG_DETECT 108
171
+ FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10)
183
+#define USB_ANALOG_USB1_CHRG_DETECT_SET 109
172
+ FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3)
184
+#define USB_ANALOG_USB1_CHRG_DETECT_CLR 110
173
+REG32(USB3_DUAL_REF_CTRL, 0x160)
185
+#define USB_ANALOG_USB1_CHRG_DETECT_TOG 111
174
+ FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1)
186
+#define USB_ANALOG_USB1_VBUS_DETECT_STAT 112
175
+ FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10)
187
+#define USB_ANALOG_USB1_CHRG_DETECT_STAT 116
176
+ FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3)
188
+#define USB_ANALOG_USB1_MISC 124
177
+REG32(RST_CPU_R5, 0x300)
189
+#define USB_ANALOG_USB1_MISC_SET 125
178
+ FIELD(RST_CPU_R5, RESET_PGE, 4, 1)
190
+#define USB_ANALOG_USB1_MISC_CLR 126
179
+ FIELD(RST_CPU_R5, RESET_AMBA, 2, 1)
191
+#define USB_ANALOG_USB1_MISC_TOG 127
180
+ FIELD(RST_CPU_R5, RESET_CPU1, 1, 1)
192
+#define USB_ANALOG_USB2_VBUS_DETECT 128
181
+ FIELD(RST_CPU_R5, RESET_CPU0, 0, 1)
193
+#define USB_ANALOG_USB2_VBUS_DETECT_SET 129
182
+REG32(RST_ADMA, 0x304)
194
+#define USB_ANALOG_USB2_VBUS_DETECT_CLR 130
183
+ FIELD(RST_ADMA, RESET, 0, 1)
195
+#define USB_ANALOG_USB2_VBUS_DETECT_TOG 131
184
+REG32(RST_GEM0, 0x308)
196
+#define USB_ANALOG_USB2_CHRG_DETECT 132
185
+ FIELD(RST_GEM0, RESET, 0, 1)
197
+#define USB_ANALOG_USB2_CHRG_DETECT_SET 133
186
+REG32(RST_GEM1, 0x30c)
198
+#define USB_ANALOG_USB2_CHRG_DETECT_CLR 134
187
+ FIELD(RST_GEM1, RESET, 0, 1)
199
+#define USB_ANALOG_USB2_CHRG_DETECT_TOG 135
188
+REG32(RST_SPARE, 0x310)
200
+#define USB_ANALOG_USB2_VBUS_DETECT_STAT 136
189
+ FIELD(RST_SPARE, RESET, 0, 1)
201
+#define USB_ANALOG_USB2_CHRG_DETECT_STAT 140
190
+REG32(RST_USB0, 0x314)
202
+#define USB_ANALOG_USB2_MISC 148
191
+ FIELD(RST_USB0, RESET, 0, 1)
203
+#define USB_ANALOG_USB2_MISC_SET 149
192
+REG32(RST_UART0, 0x318)
204
+#define USB_ANALOG_USB2_MISC_CLR 150
193
+ FIELD(RST_UART0, RESET, 0, 1)
205
+#define USB_ANALOG_USB2_MISC_TOG 151
194
+REG32(RST_UART1, 0x31c)
206
+#define USB_ANALOG_DIGPROG 152
195
+ FIELD(RST_UART1, RESET, 0, 1)
207
+#define CCM_ANALOG_MAX 4096
196
+REG32(RST_SPI0, 0x320)
208
+
197
+ FIELD(RST_SPI0, RESET, 0, 1)
209
+/* CCM_CBCMR */
198
+REG32(RST_SPI1, 0x324)
210
+#define R_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18)
199
+ FIELD(RST_SPI1, RESET, 0, 1)
211
+#define R_CBCMR_PRE_PERIPH_CLK_SEL_LENGTH (2)
200
+REG32(RST_CAN0, 0x328)
212
+#define R_CBCMR_PERIPH_CLK2_SEL_SHIFT (12)
201
+ FIELD(RST_CAN0, RESET, 0, 1)
213
+#define R_CBCMR_PERIPH_CLK2_SEL_LENGTH (2)
202
+REG32(RST_CAN1, 0x32c)
214
+
203
+ FIELD(RST_CAN1, RESET, 0, 1)
215
+/* CCM_CBCDR */
204
+REG32(RST_I2C0, 0x330)
216
+#define R_CBCDR_AHB_PODF_SHIFT (10)
205
+ FIELD(RST_I2C0, RESET, 0, 1)
217
+#define R_CBCDR_AHB_PODF_LENGTH (3)
206
+REG32(RST_I2C1, 0x334)
218
+#define R_CBCDR_IPG_PODF_SHIFT (8)
207
+ FIELD(RST_I2C1, RESET, 0, 1)
219
+#define R_CBCDR_IPG_PODF_LENGTH (2)
208
+REG32(RST_DBG_LPD, 0x338)
220
+#define R_CBCDR_PERIPH_CLK_SEL_SHIFT (25)
209
+ FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1)
221
+#define R_CBCDR_PERIPH_CLK_SEL_LENGTH (1)
210
+ FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1)
222
+#define R_CBCDR_PERIPH_CLK2_PODF_SHIFT (27)
211
+ FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1)
223
+#define R_CBCDR_PERIPH_CLK2_PODF_LENGTH (3)
212
+ FIELD(RST_DBG_LPD, RESET, 0, 1)
224
+
213
+REG32(RST_GPIO, 0x33c)
225
+/* CCM_CSCMR1 */
214
+ FIELD(RST_GPIO, RESET, 0, 1)
226
+#define R_CSCMR1_PERCLK_PODF_SHIFT (0)
215
+REG32(RST_TTC, 0x344)
227
+#define R_CSCMR1_PERCLK_PODF_LENGTH (6)
216
+ FIELD(RST_TTC, TTC3_RESET, 3, 1)
228
+#define R_CSCMR1_PERCLK_CLK_SEL_SHIFT (6)
217
+ FIELD(RST_TTC, TTC2_RESET, 2, 1)
229
+#define R_CSCMR1_PERCLK_CLK_SEL_LENGTH (1)
218
+ FIELD(RST_TTC, TTC1_RESET, 1, 1)
230
+
219
+ FIELD(RST_TTC, TTC0_RESET, 0, 1)
231
+/* CCM_ANALOG_PFD_528 */
220
+REG32(RST_TIMESTAMP, 0x348)
232
+#define R_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0)
221
+ FIELD(RST_TIMESTAMP, RESET, 0, 1)
233
+#define R_ANALOG_PFD_528_PFD0_FRAC_LENGTH (6)
222
+REG32(RST_SWDT, 0x34c)
234
+#define R_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16)
223
+ FIELD(RST_SWDT, RESET, 0, 1)
235
+#define R_ANALOG_PFD_528_PFD2_FRAC_LENGTH (6)
224
+REG32(RST_OCM, 0x350)
236
+
225
+ FIELD(RST_OCM, RESET, 0, 1)
237
+/* CCM_ANALOG_PLL_SYS */
226
+REG32(RST_IPI, 0x354)
238
+#define R_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0)
227
+ FIELD(RST_IPI, RESET, 0, 1)
239
+#define R_ANALOG_PLL_SYS_DIV_SELECT_LENGTH (1)
228
+REG32(RST_SYSMON, 0x358)
240
+
229
+ FIELD(RST_SYSMON, SEQ_RST, 1, 1)
241
+#define CCM_ANALOG_PLL_LOCK (1 << 31);
230
+ FIELD(RST_SYSMON, CFG_RST, 0, 1)
242
+
231
+REG32(RST_FPD, 0x360)
243
+#define TYPE_IMX6UL_CCM "imx6ul.ccm"
232
+ FIELD(RST_FPD, SRST, 1, 1)
244
+#define IMX6UL_CCM(obj) OBJECT_CHECK(IMX6ULCCMState, (obj), TYPE_IMX6UL_CCM)
233
+ FIELD(RST_FPD, POR, 0, 1)
245
+
234
+REG32(PSM_RST_MODE, 0x370)
246
+typedef struct IMX6ULCCMState {
235
+ FIELD(PSM_RST_MODE, WAKEUP, 2, 1)
247
+ /* <private> */
236
+ FIELD(PSM_RST_MODE, RST_MODE, 0, 2)
248
+ IMXCCMState parent_obj;
237
+
249
+
238
+#define CRL_R_MAX (R_PSM_RST_MODE + 1)
250
+ /* <public> */
239
+
251
+ MemoryRegion container;
240
+#define RPU_MAX_CPU 2
252
+ MemoryRegion ioccm;
241
+
253
+ MemoryRegion ioanalog;
242
+struct XlnxVersalCRL {
254
+
243
+ SysBusDevice parent_obj;
255
+ uint32_t ccm[CCM_MAX];
244
+ qemu_irq irq;
256
+ uint32_t analog[CCM_ANALOG_MAX];
245
+
257
+
246
+ struct {
258
+} IMX6ULCCMState;
247
+ ARMCPU *cpu_r5[RPU_MAX_CPU];
259
+
248
+ DeviceState *adma[8];
260
+#endif /* IMX6UL_CCM_H */
249
+ DeviceState *uart[2];
261
diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
250
+ DeviceState *gem[2];
251
+ DeviceState *usb;
252
+ } cfg;
253
+
254
+ RegisterInfoArray *reg_array;
255
+ uint32_t regs[CRL_R_MAX];
256
+ RegisterInfo regs_info[CRL_R_MAX];
257
+};
258
+#endif
259
diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c
262
new file mode 100644
260
new file mode 100644
263
index XXXXXXX..XXXXXXX
261
index XXXXXXX..XXXXXXX
264
--- /dev/null
262
--- /dev/null
265
+++ b/hw/misc/imx6ul_ccm.c
263
+++ b/hw/misc/xlnx-versal-crl.c
266
@@ -XXX,XX +XXX,XX @@
264
@@ -XXX,XX +XXX,XX @@
267
+/*
265
+/*
268
+ * IMX6UL Clock Control Module
266
+ * QEMU model of the Clock-Reset-LPD (CRL).
269
+ *
267
+ *
270
+ * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
268
+ * Copyright (c) 2022 Advanced Micro Devices, Inc.
269
+ * SPDX-License-Identifier: GPL-2.0-or-later
271
+ *
270
+ *
272
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
271
+ * Written by Edgar E. Iglesias <edgar.iglesias@amd.com>
273
+ * See the COPYING file in the top-level directory.
274
+ *
275
+ * To get the timer frequencies right, we need to emulate at least part of
276
+ * the CCM.
277
+ */
272
+ */
278
+
273
+
279
+#include "qemu/osdep.h"
274
+#include "qemu/osdep.h"
280
+#include "hw/registerfields.h"
275
+#include "qapi/error.h"
281
+#include "hw/misc/imx6ul_ccm.h"
282
+#include "qemu/log.h"
276
+#include "qemu/log.h"
283
+
277
+#include "qemu/bitops.h"
284
+#include "trace.h"
278
+#include "migration/vmstate.h"
285
+
279
+#include "hw/qdev-properties.h"
286
+static const char *imx6ul_ccm_reg_name(uint32_t reg)
280
+#include "hw/sysbus.h"
287
+{
281
+#include "hw/irq.h"
288
+ static char unknown[20];
282
+#include "hw/register.h"
289
+
283
+#include "hw/resettable.h"
290
+ switch (reg) {
284
+
291
+ case CCM_CCR:
285
+#include "target/arm/arm-powerctl.h"
292
+ return "CCR";
286
+#include "hw/misc/xlnx-versal-crl.h"
293
+ case CCM_CCDR:
287
+
294
+ return "CCDR";
288
+#ifndef XLNX_VERSAL_CRL_ERR_DEBUG
295
+ case CCM_CSR:
289
+#define XLNX_VERSAL_CRL_ERR_DEBUG 0
296
+ return "CSR";
290
+#endif
297
+ case CCM_CCSR:
291
+
298
+ return "CCSR";
292
+static void crl_update_irq(XlnxVersalCRL *s)
299
+ case CCM_CACRR:
293
+{
300
+ return "CACRR";
294
+ bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
301
+ case CCM_CBCDR:
295
+ qemu_set_irq(s->irq, pending);
302
+ return "CBCDR";
296
+}
303
+ case CCM_CBCMR:
297
+
304
+ return "CBCMR";
298
+static void crl_status_postw(RegisterInfo *reg, uint64_t val64)
305
+ case CCM_CSCMR1:
299
+{
306
+ return "CSCMR1";
300
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
307
+ case CCM_CSCMR2:
301
+ crl_update_irq(s);
308
+ return "CSCMR2";
302
+}
309
+ case CCM_CSCDR1:
303
+
310
+ return "CSCDR1";
304
+static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64)
311
+ case CCM_CS1CDR:
305
+{
312
+ return "CS1CDR";
306
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
313
+ case CCM_CS2CDR:
307
+ uint32_t val = val64;
314
+ return "CS2CDR";
308
+
315
+ case CCM_CDCDR:
309
+ s->regs[R_IR_MASK] &= ~val;
316
+ return "CDCDR";
310
+ crl_update_irq(s);
317
+ case CCM_CHSCCDR:
311
+ return 0;
318
+ return "CHSCCDR";
312
+}
319
+ case CCM_CSCDR2:
313
+
320
+ return "CSCDR2";
314
+static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64)
321
+ case CCM_CSCDR3:
315
+{
322
+ return "CSCDR3";
316
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
323
+ case CCM_CDHIPR:
317
+ uint32_t val = val64;
324
+ return "CDHIPR";
318
+
325
+ case CCM_CTOR:
319
+ s->regs[R_IR_MASK] |= val;
326
+ return "CTOR";
320
+ crl_update_irq(s);
327
+ case CCM_CLPCR:
321
+ return 0;
328
+ return "CLPCR";
322
+}
329
+ case CCM_CISR:
323
+
330
+ return "CISR";
324
+static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev,
331
+ case CCM_CIMR:
325
+ bool rst_old, bool rst_new)
332
+ return "CIMR";
326
+{
333
+ case CCM_CCOSR:
327
+ device_cold_reset(dev);
334
+ return "CCOSR";
328
+}
335
+ case CCM_CGPR:
329
+
336
+ return "CGPR";
330
+static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu,
337
+ case CCM_CCGR0:
331
+ bool rst_old, bool rst_new)
338
+ return "CCGR0";
332
+{
339
+ case CCM_CCGR1:
333
+ if (rst_new) {
340
+ return "CCGR1";
334
+ arm_set_cpu_off(armcpu->mp_affinity);
341
+ case CCM_CCGR2:
335
+ } else {
342
+ return "CCGR2";
336
+ arm_set_cpu_on_and_reset(armcpu->mp_affinity);
343
+ case CCM_CCGR3:
337
+ }
344
+ return "CCGR3";
338
+}
345
+ case CCM_CCGR4:
339
+
346
+ return "CCGR4";
340
+#define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \
347
+ case CCM_CCGR5:
341
+ bool old_f = ARRAY_FIELD_EX32((s)->regs, reg, f); \
348
+ return "CCGR5";
342
+ bool new_f = FIELD_EX32(new_val, reg, f); \
349
+ case CCM_CCGR6:
343
+ \
350
+ return "CCGR6";
344
+ /* Detect edges. */ \
351
+ case CCM_CMEOR:
345
+ if (dev && old_f != new_f) { \
352
+ return "CMEOR";
346
+ crl_reset_ ## type(s, dev, old_f, new_f); \
353
+ default:
347
+ } \
354
+ sprintf(unknown, "%d ?", reg);
348
+}
355
+ return unknown;
349
+
356
+ }
350
+static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64)
357
+}
351
+{
358
+
352
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
359
+static const char *imx6ul_analog_reg_name(uint32_t reg)
353
+
360
+{
354
+ REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]);
361
+ static char unknown[20];
355
+ REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]);
362
+
356
+ return val64;
363
+ switch (reg) {
357
+}
364
+ case CCM_ANALOG_PLL_ARM:
358
+
365
+ return "PLL_ARM";
359
+static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64)
366
+ case CCM_ANALOG_PLL_ARM_SET:
360
+{
367
+ return "PLL_ARM_SET";
361
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
368
+ case CCM_ANALOG_PLL_ARM_CLR:
362
+ int i;
369
+ return "PLL_ARM_CLR";
363
+
370
+ case CCM_ANALOG_PLL_ARM_TOG:
364
+ /* A single register fans out to all ADMA reset inputs. */
371
+ return "PLL_ARM_TOG";
365
+ for (i = 0; i < ARRAY_SIZE(s->cfg.adma); i++) {
372
+ case CCM_ANALOG_PLL_USB1:
366
+ REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]);
373
+ return "PLL_USB1";
367
+ }
374
+ case CCM_ANALOG_PLL_USB1_SET:
368
+ return val64;
375
+ return "PLL_USB1_SET";
369
+}
376
+ case CCM_ANALOG_PLL_USB1_CLR:
370
+
377
+ return "PLL_USB1_CLR";
371
+static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64)
378
+ case CCM_ANALOG_PLL_USB1_TOG:
372
+{
379
+ return "PLL_USB1_TOG";
373
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
380
+ case CCM_ANALOG_PLL_USB2:
374
+
381
+ return "PLL_USB2";
375
+ REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]);
382
+ case CCM_ANALOG_PLL_USB2_SET:
376
+ return val64;
383
+ return "PLL_USB2_SET";
377
+}
384
+ case CCM_ANALOG_PLL_USB2_CLR:
378
+
385
+ return "PLL_USB2_CLR";
379
+static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64)
386
+ case CCM_ANALOG_PLL_USB2_TOG:
380
+{
387
+ return "PLL_USB2_TOG";
381
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
388
+ case CCM_ANALOG_PLL_SYS:
382
+
389
+ return "PLL_SYS";
383
+ REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]);
390
+ case CCM_ANALOG_PLL_SYS_SET:
384
+ return val64;
391
+ return "PLL_SYS_SET";
385
+}
392
+ case CCM_ANALOG_PLL_SYS_CLR:
386
+
393
+ return "PLL_SYS_CLR";
387
+static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64)
394
+ case CCM_ANALOG_PLL_SYS_TOG:
388
+{
395
+ return "PLL_SYS_TOG";
389
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
396
+ case CCM_ANALOG_PLL_SYS_SS:
390
+
397
+ return "PLL_SYS_SS";
391
+ REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]);
398
+ case CCM_ANALOG_PLL_SYS_NUM:
392
+ return val64;
399
+ return "PLL_SYS_NUM";
393
+}
400
+ case CCM_ANALOG_PLL_SYS_DENOM:
394
+
401
+ return "PLL_SYS_DENOM";
395
+static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64)
402
+ case CCM_ANALOG_PLL_AUDIO:
396
+{
403
+ return "PLL_AUDIO";
397
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
404
+ case CCM_ANALOG_PLL_AUDIO_SET:
398
+
405
+ return "PLL_AUDIO_SET";
399
+ REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]);
406
+ case CCM_ANALOG_PLL_AUDIO_CLR:
400
+ return val64;
407
+ return "PLL_AUDIO_CLR";
401
+}
408
+ case CCM_ANALOG_PLL_AUDIO_TOG:
402
+
409
+ return "PLL_AUDIO_TOG";
403
+static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64)
410
+ case CCM_ANALOG_PLL_AUDIO_NUM:
404
+{
411
+ return "PLL_AUDIO_NUM";
405
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(reg->opaque);
412
+ case CCM_ANALOG_PLL_AUDIO_DENOM:
406
+
413
+ return "PLL_AUDIO_DENOM";
407
+ REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb);
414
+ case CCM_ANALOG_PLL_VIDEO:
408
+ return val64;
415
+ return "PLL_VIDEO";
409
+}
416
+ case CCM_ANALOG_PLL_VIDEO_SET:
410
+
417
+ return "PLL_VIDEO_SET";
411
+static const RegisterAccessInfo crl_regs_info[] = {
418
+ case CCM_ANALOG_PLL_VIDEO_CLR:
412
+ { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
419
+ return "PLL_VIDEO_CLR";
413
+ },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
420
+ case CCM_ANALOG_PLL_VIDEO_TOG:
414
+ .w1c = 0x1,
421
+ return "PLL_VIDEO_TOG";
415
+ .post_write = crl_status_postw,
422
+ case CCM_ANALOG_PLL_VIDEO_NUM:
416
+ },{ .name = "IR_MASK", .addr = A_IR_MASK,
423
+ return "PLL_VIDEO_NUM";
417
+ .reset = 0x1,
424
+ case CCM_ANALOG_PLL_VIDEO_DENOM:
418
+ .ro = 0x1,
425
+ return "PLL_VIDEO_DENOM";
419
+ },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
426
+ case CCM_ANALOG_PLL_ENET:
420
+ .pre_write = crl_enable_prew,
427
+ return "PLL_ENET";
421
+ },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
428
+ case CCM_ANALOG_PLL_ENET_SET:
422
+ .pre_write = crl_disable_prew,
429
+ return "PLL_ENET_SET";
423
+ },{ .name = "WPROT", .addr = A_WPROT,
430
+ case CCM_ANALOG_PLL_ENET_CLR:
424
+ },{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN,
431
+ return "PLL_ENET_CLR";
425
+ .reset = 0x1,
432
+ case CCM_ANALOG_PLL_ENET_TOG:
426
+ .rsvd = 0xe,
433
+ return "PLL_ENET_TOG";
427
+ },{ .name = "RPLL_CTRL", .addr = A_RPLL_CTRL,
434
+ case CCM_ANALOG_PFD_480:
428
+ .reset = 0x24809,
435
+ return "PFD_480";
429
+ .rsvd = 0xf88c00f6,
436
+ case CCM_ANALOG_PFD_480_SET:
430
+ },{ .name = "RPLL_CFG", .addr = A_RPLL_CFG,
437
+ return "PFD_480_SET";
431
+ .reset = 0x2000000,
438
+ case CCM_ANALOG_PFD_480_CLR:
432
+ .rsvd = 0x1801210,
439
+ return "PFD_480_CLR";
433
+ },{ .name = "RPLL_FRAC_CFG", .addr = A_RPLL_FRAC_CFG,
440
+ case CCM_ANALOG_PFD_480_TOG:
434
+ .rsvd = 0x7e330000,
441
+ return "PFD_480_TOG";
435
+ },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
442
+ case CCM_ANALOG_PFD_528:
436
+ .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
443
+ return "PFD_528";
437
+ R_PLL_STATUS_RPLL_LOCK_MASK,
444
+ case CCM_ANALOG_PFD_528_SET:
438
+ .rsvd = 0xfa,
445
+ return "PFD_528_SET";
439
+ .ro = 0x5,
446
+ case CCM_ANALOG_PFD_528_CLR:
440
+ },{ .name = "RPLL_TO_XPD_CTRL", .addr = A_RPLL_TO_XPD_CTRL,
447
+ return "PFD_528_CLR";
441
+ .reset = 0x2000100,
448
+ case CCM_ANALOG_PFD_528_TOG:
442
+ .rsvd = 0xfdfc00ff,
449
+ return "PFD_528_TOG";
443
+ },{ .name = "LPD_TOP_SWITCH_CTRL", .addr = A_LPD_TOP_SWITCH_CTRL,
450
+ case CCM_ANALOG_MISC0:
444
+ .reset = 0x6000300,
451
+ return "MISC0";
445
+ .rsvd = 0xf9fc00f8,
452
+ case CCM_ANALOG_MISC0_SET:
446
+ },{ .name = "LPD_LSBUS_CTRL", .addr = A_LPD_LSBUS_CTRL,
453
+ return "MISC0_SET";
447
+ .reset = 0x2000800,
454
+ case CCM_ANALOG_MISC0_CLR:
448
+ .rsvd = 0xfdfc00f8,
455
+ return "MISC0_CLR";
449
+ },{ .name = "CPU_R5_CTRL", .addr = A_CPU_R5_CTRL,
456
+ case CCM_ANALOG_MISC0_TOG:
450
+ .reset = 0xe000300,
457
+ return "MISC0_TOG";
451
+ .rsvd = 0xe1fc00f8,
458
+ case CCM_ANALOG_MISC2:
452
+ },{ .name = "IOU_SWITCH_CTRL", .addr = A_IOU_SWITCH_CTRL,
459
+ return "MISC2";
453
+ .reset = 0x2000500,
460
+ case CCM_ANALOG_MISC2_SET:
454
+ .rsvd = 0xfdfc00f8,
461
+ return "MISC2_SET";
455
+ },{ .name = "GEM0_REF_CTRL", .addr = A_GEM0_REF_CTRL,
462
+ case CCM_ANALOG_MISC2_CLR:
456
+ .reset = 0xe000a00,
463
+ return "MISC2_CLR";
457
+ .rsvd = 0xf1fc00f8,
464
+ case CCM_ANALOG_MISC2_TOG:
458
+ },{ .name = "GEM1_REF_CTRL", .addr = A_GEM1_REF_CTRL,
465
+ return "MISC2_TOG";
459
+ .reset = 0xe000a00,
466
+ case PMU_REG_1P1:
460
+ .rsvd = 0xf1fc00f8,
467
+ return "PMU_REG_1P1";
461
+ },{ .name = "GEM_TSU_REF_CTRL", .addr = A_GEM_TSU_REF_CTRL,
468
+ case PMU_REG_3P0:
462
+ .reset = 0x300,
469
+ return "PMU_REG_3P0";
463
+ .rsvd = 0xfdfc00f8,
470
+ case PMU_REG_2P5:
464
+ },{ .name = "USB0_BUS_REF_CTRL", .addr = A_USB0_BUS_REF_CTRL,
471
+ return "PMU_REG_2P5";
465
+ .reset = 0x2001900,
472
+ case PMU_REG_CORE:
466
+ .rsvd = 0xfdfc00f8,
473
+ return "PMU_REG_CORE";
467
+ },{ .name = "UART0_REF_CTRL", .addr = A_UART0_REF_CTRL,
474
+ case PMU_MISC1:
468
+ .reset = 0xc00,
475
+ return "PMU_MISC1";
469
+ .rsvd = 0xfdfc00f8,
476
+ case PMU_MISC1_SET:
470
+ },{ .name = "UART1_REF_CTRL", .addr = A_UART1_REF_CTRL,
477
+ return "PMU_MISC1_SET";
471
+ .reset = 0xc00,
478
+ case PMU_MISC1_CLR:
472
+ .rsvd = 0xfdfc00f8,
479
+ return "PMU_MISC1_CLR";
473
+ },{ .name = "SPI0_REF_CTRL", .addr = A_SPI0_REF_CTRL,
480
+ case PMU_MISC1_TOG:
474
+ .reset = 0x600,
481
+ return "PMU_MISC1_TOG";
475
+ .rsvd = 0xfdfc00f8,
482
+ case USB_ANALOG_DIGPROG:
476
+ },{ .name = "SPI1_REF_CTRL", .addr = A_SPI1_REF_CTRL,
483
+ return "USB_ANALOG_DIGPROG";
477
+ .reset = 0x600,
484
+ default:
478
+ .rsvd = 0xfdfc00f8,
485
+ sprintf(unknown, "%d ?", reg);
479
+ },{ .name = "CAN0_REF_CTRL", .addr = A_CAN0_REF_CTRL,
486
+ return unknown;
480
+ .reset = 0xc00,
487
+ }
481
+ .rsvd = 0xfdfc00f8,
488
+}
482
+ },{ .name = "CAN1_REF_CTRL", .addr = A_CAN1_REF_CTRL,
489
+
483
+ .reset = 0xc00,
490
+#define CKIH_FREQ 24000000 /* 24MHz crystal input */
484
+ .rsvd = 0xfdfc00f8,
491
+
485
+ },{ .name = "I2C0_REF_CTRL", .addr = A_I2C0_REF_CTRL,
492
+static const VMStateDescription vmstate_imx6ul_ccm = {
486
+ .reset = 0xc00,
493
+ .name = TYPE_IMX6UL_CCM,
487
+ .rsvd = 0xfdfc00f8,
488
+ },{ .name = "I2C1_REF_CTRL", .addr = A_I2C1_REF_CTRL,
489
+ .reset = 0xc00,
490
+ .rsvd = 0xfdfc00f8,
491
+ },{ .name = "DBG_LPD_CTRL", .addr = A_DBG_LPD_CTRL,
492
+ .reset = 0x300,
493
+ .rsvd = 0xfdfc00f8,
494
+ },{ .name = "TIMESTAMP_REF_CTRL", .addr = A_TIMESTAMP_REF_CTRL,
495
+ .reset = 0x2000c00,
496
+ .rsvd = 0xfdfc00f8,
497
+ },{ .name = "CRL_SAFETY_CHK", .addr = A_CRL_SAFETY_CHK,
498
+ },{ .name = "PSM_REF_CTRL", .addr = A_PSM_REF_CTRL,
499
+ .reset = 0xf04,
500
+ .rsvd = 0xfffc00f8,
501
+ },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
502
+ .reset = 0x300,
503
+ .rsvd = 0xfdfc00f8,
504
+ },{ .name = "CPM_TOPSW_REF_CTRL", .addr = A_CPM_TOPSW_REF_CTRL,
505
+ .reset = 0x300,
506
+ .rsvd = 0xfdfc00f8,
507
+ },{ .name = "USB3_DUAL_REF_CTRL", .addr = A_USB3_DUAL_REF_CTRL,
508
+ .reset = 0x3c00,
509
+ .rsvd = 0xfdfc00f8,
510
+ },{ .name = "RST_CPU_R5", .addr = A_RST_CPU_R5,
511
+ .reset = 0x17,
512
+ .rsvd = 0x8,
513
+ .pre_write = crl_rst_r5_prew,
514
+ },{ .name = "RST_ADMA", .addr = A_RST_ADMA,
515
+ .reset = 0x1,
516
+ .pre_write = crl_rst_adma_prew,
517
+ },{ .name = "RST_GEM0", .addr = A_RST_GEM0,
518
+ .reset = 0x1,
519
+ .pre_write = crl_rst_gem0_prew,
520
+ },{ .name = "RST_GEM1", .addr = A_RST_GEM1,
521
+ .reset = 0x1,
522
+ .pre_write = crl_rst_gem1_prew,
523
+ },{ .name = "RST_SPARE", .addr = A_RST_SPARE,
524
+ .reset = 0x1,
525
+ },{ .name = "RST_USB0", .addr = A_RST_USB0,
526
+ .reset = 0x1,
527
+ .pre_write = crl_rst_usb_prew,
528
+ },{ .name = "RST_UART0", .addr = A_RST_UART0,
529
+ .reset = 0x1,
530
+ .pre_write = crl_rst_uart0_prew,
531
+ },{ .name = "RST_UART1", .addr = A_RST_UART1,
532
+ .reset = 0x1,
533
+ .pre_write = crl_rst_uart1_prew,
534
+ },{ .name = "RST_SPI0", .addr = A_RST_SPI0,
535
+ .reset = 0x1,
536
+ },{ .name = "RST_SPI1", .addr = A_RST_SPI1,
537
+ .reset = 0x1,
538
+ },{ .name = "RST_CAN0", .addr = A_RST_CAN0,
539
+ .reset = 0x1,
540
+ },{ .name = "RST_CAN1", .addr = A_RST_CAN1,
541
+ .reset = 0x1,
542
+ },{ .name = "RST_I2C0", .addr = A_RST_I2C0,
543
+ .reset = 0x1,
544
+ },{ .name = "RST_I2C1", .addr = A_RST_I2C1,
545
+ .reset = 0x1,
546
+ },{ .name = "RST_DBG_LPD", .addr = A_RST_DBG_LPD,
547
+ .reset = 0x33,
548
+ .rsvd = 0xcc,
549
+ },{ .name = "RST_GPIO", .addr = A_RST_GPIO,
550
+ .reset = 0x1,
551
+ },{ .name = "RST_TTC", .addr = A_RST_TTC,
552
+ .reset = 0xf,
553
+ },{ .name = "RST_TIMESTAMP", .addr = A_RST_TIMESTAMP,
554
+ .reset = 0x1,
555
+ },{ .name = "RST_SWDT", .addr = A_RST_SWDT,
556
+ .reset = 0x1,
557
+ },{ .name = "RST_OCM", .addr = A_RST_OCM,
558
+ },{ .name = "RST_IPI", .addr = A_RST_IPI,
559
+ },{ .name = "RST_FPD", .addr = A_RST_FPD,
560
+ .reset = 0x3,
561
+ },{ .name = "PSM_RST_MODE", .addr = A_PSM_RST_MODE,
562
+ .reset = 0x1,
563
+ .rsvd = 0xf8,
564
+ }
565
+};
566
+
567
+static void crl_reset_enter(Object *obj, ResetType type)
568
+{
569
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
570
+ unsigned int i;
571
+
572
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
573
+ register_reset(&s->regs_info[i]);
574
+ }
575
+}
576
+
577
+static void crl_reset_hold(Object *obj)
578
+{
579
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
580
+
581
+ crl_update_irq(s);
582
+}
583
+
584
+static const MemoryRegionOps crl_ops = {
585
+ .read = register_read_memory,
586
+ .write = register_write_memory,
587
+ .endianness = DEVICE_LITTLE_ENDIAN,
588
+ .valid = {
589
+ .min_access_size = 4,
590
+ .max_access_size = 4,
591
+ },
592
+};
593
+
594
+static void crl_init(Object *obj)
595
+{
596
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
597
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
598
+ int i;
599
+
600
+ s->reg_array =
601
+ register_init_block32(DEVICE(obj), crl_regs_info,
602
+ ARRAY_SIZE(crl_regs_info),
603
+ s->regs_info, s->regs,
604
+ &crl_ops,
605
+ XLNX_VERSAL_CRL_ERR_DEBUG,
606
+ CRL_R_MAX * 4);
607
+ sysbus_init_mmio(sbd, &s->reg_array->mem);
608
+ sysbus_init_irq(sbd, &s->irq);
609
+
610
+ for (i = 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) {
611
+ object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU,
612
+ (Object **)&s->cfg.cpu_r5[i],
613
+ qdev_prop_allow_set_link_before_realize,
614
+ OBJ_PROP_LINK_STRONG);
615
+ }
616
+
617
+ for (i = 0; i < ARRAY_SIZE(s->cfg.adma); ++i) {
618
+ object_property_add_link(obj, "adma[*]", TYPE_DEVICE,
619
+ (Object **)&s->cfg.adma[i],
620
+ qdev_prop_allow_set_link_before_realize,
621
+ OBJ_PROP_LINK_STRONG);
622
+ }
623
+
624
+ for (i = 0; i < ARRAY_SIZE(s->cfg.uart); ++i) {
625
+ object_property_add_link(obj, "uart[*]", TYPE_DEVICE,
626
+ (Object **)&s->cfg.uart[i],
627
+ qdev_prop_allow_set_link_before_realize,
628
+ OBJ_PROP_LINK_STRONG);
629
+ }
630
+
631
+ for (i = 0; i < ARRAY_SIZE(s->cfg.gem); ++i) {
632
+ object_property_add_link(obj, "gem[*]", TYPE_DEVICE,
633
+ (Object **)&s->cfg.gem[i],
634
+ qdev_prop_allow_set_link_before_realize,
635
+ OBJ_PROP_LINK_STRONG);
636
+ }
637
+
638
+ object_property_add_link(obj, "usb", TYPE_DEVICE,
639
+ (Object **)&s->cfg.gem[i],
640
+ qdev_prop_allow_set_link_before_realize,
641
+ OBJ_PROP_LINK_STRONG);
642
+}
643
+
644
+static void crl_finalize(Object *obj)
645
+{
646
+ XlnxVersalCRL *s = XLNX_VERSAL_CRL(obj);
647
+ register_finalize_block(s->reg_array);
648
+}
649
+
650
+static const VMStateDescription vmstate_crl = {
651
+ .name = TYPE_XLNX_VERSAL_CRL,
494
+ .version_id = 1,
652
+ .version_id = 1,
495
+ .minimum_version_id = 1,
653
+ .minimum_version_id = 1,
496
+ .fields = (VMStateField[]) {
654
+ .fields = (VMStateField[]) {
497
+ VMSTATE_UINT32_ARRAY(ccm, IMX6ULCCMState, CCM_MAX),
655
+ VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX),
498
+ VMSTATE_UINT32_ARRAY(analog, IMX6ULCCMState, CCM_ANALOG_MAX),
656
+ VMSTATE_END_OF_LIST(),
499
+ VMSTATE_END_OF_LIST()
657
+ }
500
+ },
501
+};
658
+};
502
+
659
+
503
+static uint64_t imx6ul_analog_get_osc_clk(IMX6ULCCMState *dev)
660
+static void crl_class_init(ObjectClass *klass, void *data)
504
+{
661
+{
505
+ uint64_t freq = CKIH_FREQ;
662
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
506
+
663
+ DeviceClass *dc = DEVICE_CLASS(klass);
507
+ trace_ccm_freq((uint32_t)freq);
664
+
508
+
665
+ dc->vmsd = &vmstate_crl;
509
+ return freq;
666
+
510
+}
667
+ rc->phases.enter = crl_reset_enter;
511
+
668
+ rc->phases.hold = crl_reset_hold;
512
+static uint64_t imx6ul_analog_get_pll2_clk(IMX6ULCCMState *dev)
669
+}
513
+{
670
+
514
+ uint64_t freq = imx6ul_analog_get_osc_clk(dev);
671
+static const TypeInfo crl_info = {
515
+
672
+ .name = TYPE_XLNX_VERSAL_CRL,
516
+ if (FIELD_EX32(dev->analog[CCM_ANALOG_PLL_SYS],
673
+ .parent = TYPE_SYS_BUS_DEVICE,
517
+ ANALOG_PLL_SYS, DIV_SELECT)) {
674
+ .instance_size = sizeof(XlnxVersalCRL),
518
+ freq *= 22;
675
+ .class_init = crl_class_init,
519
+ } else {
676
+ .instance_init = crl_init,
520
+ freq *= 20;
677
+ .instance_finalize = crl_finalize,
521
+ }
522
+
523
+ trace_ccm_freq((uint32_t)freq);
524
+
525
+ return freq;
526
+}
527
+
528
+static uint64_t imx6ul_analog_get_pll3_clk(IMX6ULCCMState *dev)
529
+{
530
+ uint64_t freq = imx6ul_analog_get_osc_clk(dev) * 20;
531
+
532
+ trace_ccm_freq((uint32_t)freq);
533
+
534
+ return freq;
535
+}
536
+
537
+static uint64_t imx6ul_analog_get_pll2_pfd0_clk(IMX6ULCCMState *dev)
538
+{
539
+ uint64_t freq = 0;
540
+
541
+ freq = imx6ul_analog_get_pll2_clk(dev) * 18
542
+ / FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528],
543
+ ANALOG_PFD_528, PFD0_FRAC);
544
+
545
+ trace_ccm_freq((uint32_t)freq);
546
+
547
+ return freq;
548
+}
549
+
550
+static uint64_t imx6ul_analog_get_pll2_pfd2_clk(IMX6ULCCMState *dev)
551
+{
552
+ uint64_t freq = 0;
553
+
554
+ freq = imx6ul_analog_get_pll2_clk(dev) * 18
555
+ / FIELD_EX32(dev->analog[CCM_ANALOG_PFD_528],
556
+ ANALOG_PFD_528, PFD2_FRAC);
557
+
558
+ trace_ccm_freq((uint32_t)freq);
559
+
560
+ return freq;
561
+}
562
+
563
+static uint64_t imx6ul_analog_pll2_bypass_clk(IMX6ULCCMState *dev)
564
+{
565
+ uint64_t freq = 0;
566
+
567
+ trace_ccm_freq((uint32_t)freq);
568
+
569
+ return freq;
570
+}
571
+
572
+static uint64_t imx6ul_ccm_get_periph_clk2_sel_clk(IMX6ULCCMState *dev)
573
+{
574
+ uint64_t freq = 0;
575
+
576
+ switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PERIPH_CLK2_SEL)) {
577
+ case 0:
578
+ freq = imx6ul_analog_get_pll3_clk(dev);
579
+ break;
580
+ case 1:
581
+ freq = imx6ul_analog_get_osc_clk(dev);
582
+ break;
583
+ case 2:
584
+ freq = imx6ul_analog_pll2_bypass_clk(dev);
585
+ break;
586
+ case 3:
587
+ /* We should never get there as 3 is a reserved value */
588
+ qemu_log_mask(LOG_GUEST_ERROR,
589
+ "[%s]%s: unsupported PERIPH_CLK2_SEL value 3\n",
590
+ TYPE_IMX6UL_CCM, __func__);
591
+ /* freq is set to 0 as we don't know what it should be */
592
+ break;
593
+ default:
594
+ g_assert_not_reached();
595
+ }
596
+
597
+ trace_ccm_freq((uint32_t)freq);
598
+
599
+ return freq;
600
+}
601
+
602
+static uint64_t imx6ul_ccm_get_periph_clk_sel_clk(IMX6ULCCMState *dev)
603
+{
604
+ uint64_t freq = 0;
605
+
606
+ switch (FIELD_EX32(dev->ccm[CCM_CBCMR], CBCMR, PRE_PERIPH_CLK_SEL)) {
607
+ case 0:
608
+ freq = imx6ul_analog_get_pll2_clk(dev);
609
+ break;
610
+ case 1:
611
+ freq = imx6ul_analog_get_pll2_pfd2_clk(dev);
612
+ break;
613
+ case 2:
614
+ freq = imx6ul_analog_get_pll2_pfd0_clk(dev);
615
+ break;
616
+ case 3:
617
+ freq = imx6ul_analog_get_pll2_pfd2_clk(dev) / 2;
618
+ break;
619
+ default:
620
+ g_assert_not_reached();
621
+ }
622
+
623
+ trace_ccm_freq((uint32_t)freq);
624
+
625
+ return freq;
626
+}
627
+
628
+static uint64_t imx6ul_ccm_get_periph_clk2_clk(IMX6ULCCMState *dev)
629
+{
630
+ uint64_t freq = 0;
631
+
632
+ freq = imx6ul_ccm_get_periph_clk2_sel_clk(dev)
633
+ / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK2_PODF));
634
+
635
+ trace_ccm_freq((uint32_t)freq);
636
+
637
+ return freq;
638
+}
639
+
640
+static uint64_t imx6ul_ccm_get_periph_sel_clk(IMX6ULCCMState *dev)
641
+{
642
+ uint64_t freq = 0;
643
+
644
+ switch (FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, PERIPH_CLK_SEL)) {
645
+ case 0:
646
+ freq = imx6ul_ccm_get_periph_clk_sel_clk(dev);
647
+ break;
648
+ case 1:
649
+ freq = imx6ul_ccm_get_periph_clk2_clk(dev);
650
+ break;
651
+ default:
652
+ g_assert_not_reached();
653
+ }
654
+
655
+ trace_ccm_freq((uint32_t)freq);
656
+
657
+ return freq;
658
+}
659
+
660
+static uint64_t imx6ul_ccm_get_ahb_clk(IMX6ULCCMState *dev)
661
+{
662
+ uint64_t freq = 0;
663
+
664
+ freq = imx6ul_ccm_get_periph_sel_clk(dev)
665
+ / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, AHB_PODF));
666
+
667
+ trace_ccm_freq((uint32_t)freq);
668
+
669
+ return freq;
670
+}
671
+
672
+static uint64_t imx6ul_ccm_get_ipg_clk(IMX6ULCCMState *dev)
673
+{
674
+ uint64_t freq = 0;
675
+
676
+ freq = imx6ul_ccm_get_ahb_clk(dev)
677
+ / (1 + FIELD_EX32(dev->ccm[CCM_CBCDR], CBCDR, IPG_PODF));
678
+
679
+ trace_ccm_freq((uint32_t)freq);
680
+
681
+ return freq;
682
+}
683
+
684
+static uint64_t imx6ul_ccm_get_per_sel_clk(IMX6ULCCMState *dev)
685
+{
686
+ uint64_t freq = 0;
687
+
688
+ switch (FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_CLK_SEL)) {
689
+ case 0:
690
+ freq = imx6ul_ccm_get_ipg_clk(dev);
691
+ break;
692
+ case 1:
693
+ freq = imx6ul_analog_get_osc_clk(dev);
694
+ break;
695
+ default:
696
+ g_assert_not_reached();
697
+ }
698
+
699
+ trace_ccm_freq((uint32_t)freq);
700
+
701
+ return freq;
702
+}
703
+
704
+static uint64_t imx6ul_ccm_get_per_clk(IMX6ULCCMState *dev)
705
+{
706
+ uint64_t freq = 0;
707
+
708
+ freq = imx6ul_ccm_get_per_sel_clk(dev)
709
+ / (1 + FIELD_EX32(dev->ccm[CCM_CSCMR1], CSCMR1, PERCLK_PODF));
710
+
711
+ trace_ccm_freq((uint32_t)freq);
712
+
713
+ return freq;
714
+}
715
+
716
+static uint32_t imx6ul_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
717
+{
718
+ uint32_t freq = 0;
719
+ IMX6ULCCMState *s = IMX6UL_CCM(dev);
720
+
721
+ switch (clock) {
722
+ case CLK_NONE:
723
+ break;
724
+ case CLK_IPG:
725
+ freq = imx6ul_ccm_get_ipg_clk(s);
726
+ break;
727
+ case CLK_IPG_HIGH:
728
+ freq = imx6ul_ccm_get_per_clk(s);
729
+ break;
730
+ case CLK_32k:
731
+ freq = CKIL_FREQ;
732
+ break;
733
+ case CLK_HIGH:
734
+ freq = CKIH_FREQ;
735
+ break;
736
+ case CLK_HIGH_DIV:
737
+ freq = CKIH_FREQ / 8;
738
+ break;
739
+ default:
740
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
741
+ TYPE_IMX6UL_CCM, __func__, clock);
742
+ break;
743
+ }
744
+
745
+ trace_ccm_clock_freq(clock, freq);
746
+
747
+ return freq;
748
+}
749
+
750
+static void imx6ul_ccm_reset(DeviceState *dev)
751
+{
752
+ IMX6ULCCMState *s = IMX6UL_CCM(dev);
753
+
754
+ trace_ccm_entry();
755
+
756
+ s->ccm[CCM_CCR] = 0x0401167F;
757
+ s->ccm[CCM_CCDR] = 0x00000000;
758
+ s->ccm[CCM_CSR] = 0x00000010;
759
+ s->ccm[CCM_CCSR] = 0x00000100;
760
+ s->ccm[CCM_CACRR] = 0x00000000;
761
+ s->ccm[CCM_CBCDR] = 0x00018D00;
762
+ s->ccm[CCM_CBCMR] = 0x24860324;
763
+ s->ccm[CCM_CSCMR1] = 0x04900080;
764
+ s->ccm[CCM_CSCMR2] = 0x03192F06;
765
+ s->ccm[CCM_CSCDR1] = 0x00490B00;
766
+ s->ccm[CCM_CS1CDR] = 0x0EC102C1;
767
+ s->ccm[CCM_CS2CDR] = 0x000336C1;
768
+ s->ccm[CCM_CDCDR] = 0x33F71F92;
769
+ s->ccm[CCM_CHSCCDR] = 0x000248A4;
770
+ s->ccm[CCM_CSCDR2] = 0x00029B48;
771
+ s->ccm[CCM_CSCDR3] = 0x00014841;
772
+ s->ccm[CCM_CDHIPR] = 0x00000000;
773
+ s->ccm[CCM_CTOR] = 0x00000000;
774
+ s->ccm[CCM_CLPCR] = 0x00000079;
775
+ s->ccm[CCM_CISR] = 0x00000000;
776
+ s->ccm[CCM_CIMR] = 0xFFFFFFFF;
777
+ s->ccm[CCM_CCOSR] = 0x000A0001;
778
+ s->ccm[CCM_CGPR] = 0x0000FE62;
779
+ s->ccm[CCM_CCGR0] = 0xFFFFFFFF;
780
+ s->ccm[CCM_CCGR1] = 0xFFFFFFFF;
781
+ s->ccm[CCM_CCGR2] = 0xFC3FFFFF;
782
+ s->ccm[CCM_CCGR3] = 0xFFFFFFFF;
783
+ s->ccm[CCM_CCGR4] = 0xFFFFFFFF;
784
+ s->ccm[CCM_CCGR5] = 0xFFFFFFFF;
785
+ s->ccm[CCM_CCGR6] = 0xFFFFFFFF;
786
+ s->ccm[CCM_CMEOR] = 0xFFFFFFFF;
787
+
788
+ s->analog[CCM_ANALOG_PLL_ARM] = 0x00013063;
789
+ s->analog[CCM_ANALOG_PLL_USB1] = 0x00012000;
790
+ s->analog[CCM_ANALOG_PLL_USB2] = 0x00012000;
791
+ s->analog[CCM_ANALOG_PLL_SYS] = 0x00013001;
792
+ s->analog[CCM_ANALOG_PLL_SYS_SS] = 0x00000000;
793
+ s->analog[CCM_ANALOG_PLL_SYS_NUM] = 0x00000000;
794
+ s->analog[CCM_ANALOG_PLL_SYS_DENOM] = 0x00000012;
795
+ s->analog[CCM_ANALOG_PLL_AUDIO] = 0x00011006;
796
+ s->analog[CCM_ANALOG_PLL_AUDIO_NUM] = 0x05F5E100;
797
+ s->analog[CCM_ANALOG_PLL_AUDIO_DENOM] = 0x2964619C;
798
+ s->analog[CCM_ANALOG_PLL_VIDEO] = 0x0001100C;
799
+ s->analog[CCM_ANALOG_PLL_VIDEO_NUM] = 0x05F5E100;
800
+ s->analog[CCM_ANALOG_PLL_VIDEO_DENOM] = 0x10A24447;
801
+ s->analog[CCM_ANALOG_PLL_ENET] = 0x00011001;
802
+ s->analog[CCM_ANALOG_PFD_480] = 0x1311100C;
803
+ s->analog[CCM_ANALOG_PFD_528] = 0x1018101B;
804
+
805
+ s->analog[PMU_REG_1P1] = 0x00001073;
806
+ s->analog[PMU_REG_3P0] = 0x00000F74;
807
+ s->analog[PMU_REG_2P5] = 0x00001073;
808
+ s->analog[PMU_REG_CORE] = 0x00482012;
809
+ s->analog[PMU_MISC0] = 0x04000000;
810
+ s->analog[PMU_MISC1] = 0x00000000;
811
+ s->analog[PMU_MISC2] = 0x00272727;
812
+ s->analog[PMU_LOWPWR_CTRL] = 0x00004009;
813
+
814
+ s->analog[USB_ANALOG_USB1_VBUS_DETECT] = 0x01000004;
815
+ s->analog[USB_ANALOG_USB1_CHRG_DETECT] = 0x00000000;
816
+ s->analog[USB_ANALOG_USB1_VBUS_DETECT_STAT] = 0x00000000;
817
+ s->analog[USB_ANALOG_USB1_CHRG_DETECT_STAT] = 0x00000000;
818
+ s->analog[USB_ANALOG_USB1_MISC] = 0x00000002;
819
+ s->analog[USB_ANALOG_USB2_VBUS_DETECT] = 0x01000004;
820
+ s->analog[USB_ANALOG_USB2_CHRG_DETECT] = 0x00000000;
821
+ s->analog[USB_ANALOG_USB2_MISC] = 0x00000002;
822
+ s->analog[USB_ANALOG_DIGPROG] = 0x00640000;
823
+
824
+ /* all PLLs need to be locked */
825
+ s->analog[CCM_ANALOG_PLL_ARM] |= CCM_ANALOG_PLL_LOCK;
826
+ s->analog[CCM_ANALOG_PLL_USB1] |= CCM_ANALOG_PLL_LOCK;
827
+ s->analog[CCM_ANALOG_PLL_USB2] |= CCM_ANALOG_PLL_LOCK;
828
+ s->analog[CCM_ANALOG_PLL_SYS] |= CCM_ANALOG_PLL_LOCK;
829
+ s->analog[CCM_ANALOG_PLL_AUDIO] |= CCM_ANALOG_PLL_LOCK;
830
+ s->analog[CCM_ANALOG_PLL_VIDEO] |= CCM_ANALOG_PLL_LOCK;
831
+ s->analog[CCM_ANALOG_PLL_ENET] |= CCM_ANALOG_PLL_LOCK;
832
+
833
+ s->analog[TEMPMON_TEMPSENSE0] = 0x00000001;
834
+ s->analog[TEMPMON_TEMPSENSE1] = 0x00000001;
835
+ s->analog[TEMPMON_TEMPSENSE2] = 0x00000000;
836
+}
837
+
838
+static uint64_t imx6ul_ccm_read(void *opaque, hwaddr offset, unsigned size)
839
+{
840
+ uint32_t value = 0;
841
+ uint32_t index = offset >> 2;
842
+ IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
843
+
844
+ assert(index < CCM_MAX);
845
+
846
+ value = s->ccm[index];
847
+
848
+ trace_ccm_read_reg(imx6ul_ccm_reg_name(index), (uint32_t)value);
849
+
850
+ return (uint64_t)value;
851
+}
852
+
853
+static void imx6ul_ccm_write(void *opaque, hwaddr offset, uint64_t value,
854
+ unsigned size)
855
+{
856
+ uint32_t index = offset >> 2;
857
+ IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
858
+
859
+ assert(index < CCM_MAX);
860
+
861
+ trace_ccm_write_reg(imx6ul_ccm_reg_name(index), (uint32_t)value);
862
+
863
+ /*
864
+ * We will do a better implementation later. In particular some bits
865
+ * cannot be written to.
866
+ */
867
+ s->ccm[index] = (uint32_t)value;
868
+}
869
+
870
+static uint64_t imx6ul_analog_read(void *opaque, hwaddr offset, unsigned size)
871
+{
872
+ uint32_t value;
873
+ uint32_t index = offset >> 2;
874
+ IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
875
+
876
+ assert(index < CCM_ANALOG_MAX);
877
+
878
+ switch (index) {
879
+ case CCM_ANALOG_PLL_ARM_SET:
880
+ case CCM_ANALOG_PLL_USB1_SET:
881
+ case CCM_ANALOG_PLL_USB2_SET:
882
+ case CCM_ANALOG_PLL_SYS_SET:
883
+ case CCM_ANALOG_PLL_AUDIO_SET:
884
+ case CCM_ANALOG_PLL_VIDEO_SET:
885
+ case CCM_ANALOG_PLL_ENET_SET:
886
+ case CCM_ANALOG_PFD_480_SET:
887
+ case CCM_ANALOG_PFD_528_SET:
888
+ case CCM_ANALOG_MISC0_SET:
889
+ case PMU_MISC1_SET:
890
+ case CCM_ANALOG_MISC2_SET:
891
+ case USB_ANALOG_USB1_VBUS_DETECT_SET:
892
+ case USB_ANALOG_USB1_CHRG_DETECT_SET:
893
+ case USB_ANALOG_USB1_MISC_SET:
894
+ case USB_ANALOG_USB2_VBUS_DETECT_SET:
895
+ case USB_ANALOG_USB2_CHRG_DETECT_SET:
896
+ case USB_ANALOG_USB2_MISC_SET:
897
+ case TEMPMON_TEMPSENSE0_SET:
898
+ case TEMPMON_TEMPSENSE1_SET:
899
+ case TEMPMON_TEMPSENSE2_SET:
900
+ /*
901
+ * All REG_NAME_SET register access are in fact targeting
902
+ * the REG_NAME register.
903
+ */
904
+ value = s->analog[index - 1];
905
+ break;
906
+ case CCM_ANALOG_PLL_ARM_CLR:
907
+ case CCM_ANALOG_PLL_USB1_CLR:
908
+ case CCM_ANALOG_PLL_USB2_CLR:
909
+ case CCM_ANALOG_PLL_SYS_CLR:
910
+ case CCM_ANALOG_PLL_AUDIO_CLR:
911
+ case CCM_ANALOG_PLL_VIDEO_CLR:
912
+ case CCM_ANALOG_PLL_ENET_CLR:
913
+ case CCM_ANALOG_PFD_480_CLR:
914
+ case CCM_ANALOG_PFD_528_CLR:
915
+ case CCM_ANALOG_MISC0_CLR:
916
+ case PMU_MISC1_CLR:
917
+ case CCM_ANALOG_MISC2_CLR:
918
+ case USB_ANALOG_USB1_VBUS_DETECT_CLR:
919
+ case USB_ANALOG_USB1_CHRG_DETECT_CLR:
920
+ case USB_ANALOG_USB1_MISC_CLR:
921
+ case USB_ANALOG_USB2_VBUS_DETECT_CLR:
922
+ case USB_ANALOG_USB2_CHRG_DETECT_CLR:
923
+ case USB_ANALOG_USB2_MISC_CLR:
924
+ case TEMPMON_TEMPSENSE0_CLR:
925
+ case TEMPMON_TEMPSENSE1_CLR:
926
+ case TEMPMON_TEMPSENSE2_CLR:
927
+ /*
928
+ * All REG_NAME_CLR register access are in fact targeting
929
+ * the REG_NAME register.
930
+ */
931
+ value = s->analog[index - 2];
932
+ break;
933
+ case CCM_ANALOG_PLL_ARM_TOG:
934
+ case CCM_ANALOG_PLL_USB1_TOG:
935
+ case CCM_ANALOG_PLL_USB2_TOG:
936
+ case CCM_ANALOG_PLL_SYS_TOG:
937
+ case CCM_ANALOG_PLL_AUDIO_TOG:
938
+ case CCM_ANALOG_PLL_VIDEO_TOG:
939
+ case CCM_ANALOG_PLL_ENET_TOG:
940
+ case CCM_ANALOG_PFD_480_TOG:
941
+ case CCM_ANALOG_PFD_528_TOG:
942
+ case CCM_ANALOG_MISC0_TOG:
943
+ case PMU_MISC1_TOG:
944
+ case CCM_ANALOG_MISC2_TOG:
945
+ case USB_ANALOG_USB1_VBUS_DETECT_TOG:
946
+ case USB_ANALOG_USB1_CHRG_DETECT_TOG:
947
+ case USB_ANALOG_USB1_MISC_TOG:
948
+ case USB_ANALOG_USB2_VBUS_DETECT_TOG:
949
+ case USB_ANALOG_USB2_CHRG_DETECT_TOG:
950
+ case USB_ANALOG_USB2_MISC_TOG:
951
+ case TEMPMON_TEMPSENSE0_TOG:
952
+ case TEMPMON_TEMPSENSE1_TOG:
953
+ case TEMPMON_TEMPSENSE2_TOG:
954
+ /*
955
+ * All REG_NAME_TOG register access are in fact targeting
956
+ * the REG_NAME register.
957
+ */
958
+ value = s->analog[index - 3];
959
+ break;
960
+ default:
961
+ value = s->analog[index];
962
+ break;
963
+ }
964
+
965
+ trace_ccm_read_reg(imx6ul_analog_reg_name(index), (uint32_t)value);
966
+
967
+ return (uint64_t)value;
968
+}
969
+
970
+static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value,
971
+ unsigned size)
972
+{
973
+ uint32_t index = offset >> 2;
974
+ IMX6ULCCMState *s = (IMX6ULCCMState *)opaque;
975
+
976
+ assert(index < CCM_ANALOG_MAX);
977
+
978
+ trace_ccm_write_reg(imx6ul_analog_reg_name(index), (uint32_t)value);
979
+
980
+ switch (index) {
981
+ case CCM_ANALOG_PLL_ARM_SET:
982
+ case CCM_ANALOG_PLL_USB1_SET:
983
+ case CCM_ANALOG_PLL_USB2_SET:
984
+ case CCM_ANALOG_PLL_SYS_SET:
985
+ case CCM_ANALOG_PLL_AUDIO_SET:
986
+ case CCM_ANALOG_PLL_VIDEO_SET:
987
+ case CCM_ANALOG_PLL_ENET_SET:
988
+ case CCM_ANALOG_PFD_480_SET:
989
+ case CCM_ANALOG_PFD_528_SET:
990
+ case CCM_ANALOG_MISC0_SET:
991
+ case PMU_MISC1_SET:
992
+ case CCM_ANALOG_MISC2_SET:
993
+ case USB_ANALOG_USB1_VBUS_DETECT_SET:
994
+ case USB_ANALOG_USB1_CHRG_DETECT_SET:
995
+ case USB_ANALOG_USB1_MISC_SET:
996
+ case USB_ANALOG_USB2_VBUS_DETECT_SET:
997
+ case USB_ANALOG_USB2_CHRG_DETECT_SET:
998
+ case USB_ANALOG_USB2_MISC_SET:
999
+ /*
1000
+ * All REG_NAME_SET register access are in fact targeting
1001
+ * the REG_NAME register. So we change the value of the
1002
+ * REG_NAME register, setting bits passed in the value.
1003
+ */
1004
+ s->analog[index - 1] |= value;
1005
+ break;
1006
+ case CCM_ANALOG_PLL_ARM_CLR:
1007
+ case CCM_ANALOG_PLL_USB1_CLR:
1008
+ case CCM_ANALOG_PLL_USB2_CLR:
1009
+ case CCM_ANALOG_PLL_SYS_CLR:
1010
+ case CCM_ANALOG_PLL_AUDIO_CLR:
1011
+ case CCM_ANALOG_PLL_VIDEO_CLR:
1012
+ case CCM_ANALOG_PLL_ENET_CLR:
1013
+ case CCM_ANALOG_PFD_480_CLR:
1014
+ case CCM_ANALOG_PFD_528_CLR:
1015
+ case CCM_ANALOG_MISC0_CLR:
1016
+ case PMU_MISC1_CLR:
1017
+ case CCM_ANALOG_MISC2_CLR:
1018
+ case USB_ANALOG_USB1_VBUS_DETECT_CLR:
1019
+ case USB_ANALOG_USB1_CHRG_DETECT_CLR:
1020
+ case USB_ANALOG_USB1_MISC_CLR:
1021
+ case USB_ANALOG_USB2_VBUS_DETECT_CLR:
1022
+ case USB_ANALOG_USB2_CHRG_DETECT_CLR:
1023
+ case USB_ANALOG_USB2_MISC_CLR:
1024
+ /*
1025
+ * All REG_NAME_CLR register access are in fact targeting
1026
+ * the REG_NAME register. So we change the value of the
1027
+ * REG_NAME register, unsetting bits passed in the value.
1028
+ */
1029
+ s->analog[index - 2] &= ~value;
1030
+ break;
1031
+ case CCM_ANALOG_PLL_ARM_TOG:
1032
+ case CCM_ANALOG_PLL_USB1_TOG:
1033
+ case CCM_ANALOG_PLL_USB2_TOG:
1034
+ case CCM_ANALOG_PLL_SYS_TOG:
1035
+ case CCM_ANALOG_PLL_AUDIO_TOG:
1036
+ case CCM_ANALOG_PLL_VIDEO_TOG:
1037
+ case CCM_ANALOG_PLL_ENET_TOG:
1038
+ case CCM_ANALOG_PFD_480_TOG:
1039
+ case CCM_ANALOG_PFD_528_TOG:
1040
+ case CCM_ANALOG_MISC0_TOG:
1041
+ case PMU_MISC1_TOG:
1042
+ case CCM_ANALOG_MISC2_TOG:
1043
+ case USB_ANALOG_USB1_VBUS_DETECT_TOG:
1044
+ case USB_ANALOG_USB1_CHRG_DETECT_TOG:
1045
+ case USB_ANALOG_USB1_MISC_TOG:
1046
+ case USB_ANALOG_USB2_VBUS_DETECT_TOG:
1047
+ case USB_ANALOG_USB2_CHRG_DETECT_TOG:
1048
+ case USB_ANALOG_USB2_MISC_TOG:
1049
+ /*
1050
+ * All REG_NAME_TOG register access are in fact targeting
1051
+ * the REG_NAME register. So we change the value of the
1052
+ * REG_NAME register, toggling bits passed in the value.
1053
+ */
1054
+ s->analog[index - 3] ^= value;
1055
+ break;
1056
+ default:
1057
+ /*
1058
+ * We will do a better implementation later. In particular some bits
1059
+ * cannot be written to.
1060
+ */
1061
+ s->analog[index] = value;
1062
+ break;
1063
+ }
1064
+}
1065
+
1066
+static const struct MemoryRegionOps imx6ul_ccm_ops = {
1067
+ .read = imx6ul_ccm_read,
1068
+ .write = imx6ul_ccm_write,
1069
+ .endianness = DEVICE_NATIVE_ENDIAN,
1070
+ .valid = {
1071
+ /*
1072
+ * Our device would not work correctly if the guest was doing
1073
+ * unaligned access. This might not be a limitation on the real
1074
+ * device but in practice there is no reason for a guest to access
1075
+ * this device unaligned.
1076
+ */
1077
+ .min_access_size = 4,
1078
+ .max_access_size = 4,
1079
+ .unaligned = false,
1080
+ },
1081
+};
678
+};
1082
+
679
+
1083
+static const struct MemoryRegionOps imx6ul_analog_ops = {
680
+static void crl_register_types(void)
1084
+ .read = imx6ul_analog_read,
681
+{
1085
+ .write = imx6ul_analog_write,
682
+ type_register_static(&crl_info);
1086
+ .endianness = DEVICE_NATIVE_ENDIAN,
683
+}
1087
+ .valid = {
684
+
1088
+ /*
685
+type_init(crl_register_types)
1089
+ * Our device would not work correctly if the guest was doing
686
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
1090
+ * unaligned access. This might not be a limitation on the real
1091
+ * device but in practice there is no reason for a guest to access
1092
+ * this device unaligned.
1093
+ */
1094
+ .min_access_size = 4,
1095
+ .max_access_size = 4,
1096
+ .unaligned = false,
1097
+ },
1098
+};
1099
+
1100
+static void imx6ul_ccm_init(Object *obj)
1101
+{
1102
+ DeviceState *dev = DEVICE(obj);
1103
+ SysBusDevice *sd = SYS_BUS_DEVICE(obj);
1104
+ IMX6ULCCMState *s = IMX6UL_CCM(obj);
1105
+
1106
+ /* initialize a container for the all memory range */
1107
+ memory_region_init(&s->container, OBJECT(dev), TYPE_IMX6UL_CCM, 0x8000);
1108
+
1109
+ /* We initialize an IO memory region for the CCM part */
1110
+ memory_region_init_io(&s->ioccm, OBJECT(dev), &imx6ul_ccm_ops, s,
1111
+ TYPE_IMX6UL_CCM ".ccm", CCM_MAX * sizeof(uint32_t));
1112
+
1113
+ /* Add the CCM as a subregion at offset 0 */
1114
+ memory_region_add_subregion(&s->container, 0, &s->ioccm);
1115
+
1116
+ /* We initialize an IO memory region for the ANALOG part */
1117
+ memory_region_init_io(&s->ioanalog, OBJECT(dev), &imx6ul_analog_ops, s,
1118
+ TYPE_IMX6UL_CCM ".analog",
1119
+ CCM_ANALOG_MAX * sizeof(uint32_t));
1120
+
1121
+ /* Add the ANALOG as a subregion at offset 0x4000 */
1122
+ memory_region_add_subregion(&s->container, 0x4000, &s->ioanalog);
1123
+
1124
+ sysbus_init_mmio(sd, &s->container);
1125
+}
1126
+
1127
+static void imx6ul_ccm_class_init(ObjectClass *klass, void *data)
1128
+{
1129
+ DeviceClass *dc = DEVICE_CLASS(klass);
1130
+ IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
1131
+
1132
+ dc->reset = imx6ul_ccm_reset;
1133
+ dc->vmsd = &vmstate_imx6ul_ccm;
1134
+ dc->desc = "i.MX6UL Clock Control Module";
1135
+
1136
+ ccm->get_clock_frequency = imx6ul_ccm_get_clock_frequency;
1137
+}
1138
+
1139
+static const TypeInfo imx6ul_ccm_info = {
1140
+ .name = TYPE_IMX6UL_CCM,
1141
+ .parent = TYPE_IMX_CCM,
1142
+ .instance_size = sizeof(IMX6ULCCMState),
1143
+ .instance_init = imx6ul_ccm_init,
1144
+ .class_init = imx6ul_ccm_class_init,
1145
+};
1146
+
1147
+static void imx6ul_ccm_register_types(void)
1148
+{
1149
+ type_register_static(&imx6ul_ccm_info);
1150
+}
1151
+
1152
+type_init(imx6ul_ccm_register_types)
1153
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
1154
index XXXXXXX..XXXXXXX 100644
687
index XXXXXXX..XXXXXXX 100644
1155
--- a/hw/misc/trace-events
688
--- a/hw/misc/meson.build
1156
+++ b/hw/misc/trace-events
689
+++ b/hw/misc/meson.build
1157
@@ -XXX,XX +XXX,XX @@ iotkit_secctl_s_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit Sec
690
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
1158
iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs read: offset 0x%x data 0x%" PRIx64 " size %u"
691
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
1159
iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u"
692
specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
1160
iotkit_secctl_reset(void) "IoTKit SecCtl: reset"
693
specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
1161
+
694
+specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
1162
+# hw/misc/imx6ul_ccm.c
695
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
1163
+ccm_entry(void) "\n"
696
'xlnx-versal-xramc.c',
1164
+ccm_freq(uint32_t freq) "freq = %d\n"
697
'xlnx-versal-pmc-iou-slcr.c',
1165
+ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d\n"
1166
+ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 "\n"
1167
+ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 "\n"
1168
--
698
--
1169
2.18.0
699
2.25.1
1170
1171
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
2
2
3
Cc: qemu-stable@nongnu.org (3.0.1)
3
Connect the CRL (Clock Reset LPD) to the Versal SoC.
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
6
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
8
Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/sve_helper.c | 2 +-
11
include/hw/arm/xlnx-versal.h | 4 +++
9
1 file changed, 1 insertion(+), 1 deletion(-)
12
hw/arm/xlnx-versal.c | 54 ++++++++++++++++++++++++++++++++++--
13
2 files changed, 56 insertions(+), 2 deletions(-)
10
14
11
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
15
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/sve_helper.c
17
--- a/include/hw/arm/xlnx-versal.h
14
+++ b/target/arm/sve_helper.c
18
+++ b/include/hw/arm/xlnx-versal.h
15
@@ -XXX,XX +XXX,XX @@ DO_LD1(sve_ld1bdu_r, cpu_ldub_data_ra, uint64_t, uint8_t, )
19
@@ -XXX,XX +XXX,XX @@
16
DO_LD1(sve_ld1bds_r, cpu_ldsb_data_ra, uint64_t, int8_t, )
20
#include "hw/nvram/xlnx-versal-efuse.h"
17
21
#include "hw/ssi/xlnx-versal-ospi.h"
18
DO_LD1(sve_ld1hsu_r, cpu_lduw_data_ra, uint32_t, uint16_t, H1_4)
22
#include "hw/dma/xlnx_csu_dma.h"
19
-DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int8_t, H1_4)
23
+#include "hw/misc/xlnx-versal-crl.h"
20
+DO_LD1(sve_ld1hss_r, cpu_ldsw_data_ra, uint32_t, int16_t, H1_4)
24
#include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
21
DO_LD1(sve_ld1hdu_r, cpu_lduw_data_ra, uint64_t, uint16_t, )
25
22
DO_LD1(sve_ld1hds_r, cpu_ldsw_data_ra, uint64_t, int16_t, )
26
#define TYPE_XLNX_VERSAL "xlnx-versal"
27
@@ -XXX,XX +XXX,XX @@ struct Versal {
28
qemu_or_irq irq_orgate;
29
XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
30
} xram;
31
+
32
+ XlnxVersalCRL crl;
33
} lpd;
34
35
/* The Platform Management Controller subsystem. */
36
@@ -XXX,XX +XXX,XX @@ struct Versal {
37
#define VERSAL_TIMER_NS_EL1_IRQ 14
38
#define VERSAL_TIMER_NS_EL2_IRQ 10
39
40
+#define VERSAL_CRL_IRQ 10
41
#define VERSAL_UART0_IRQ_0 18
42
#define VERSAL_UART1_IRQ_0 19
43
#define VERSAL_USB0_IRQ_0 22
44
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/hw/arm/xlnx-versal.c
47
+++ b/hw/arm/xlnx-versal.c
48
@@ -XXX,XX +XXX,XX @@ static void versal_create_ospi(Versal *s, qemu_irq *pic)
49
qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
50
}
51
52
+static void versal_create_crl(Versal *s, qemu_irq *pic)
53
+{
54
+ SysBusDevice *sbd;
55
+ int i;
56
+
57
+ object_initialize_child(OBJECT(s), "crl", &s->lpd.crl,
58
+ TYPE_XLNX_VERSAL_CRL);
59
+ sbd = SYS_BUS_DEVICE(&s->lpd.crl);
60
+
61
+ for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
62
+ g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i);
63
+
64
+ object_property_set_link(OBJECT(&s->lpd.crl),
65
+ name, OBJECT(&s->lpd.rpu.cpu[i]),
66
+ &error_abort);
67
+ }
68
+
69
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
70
+ g_autofree gchar *name = g_strdup_printf("gem[%d]", i);
71
+
72
+ object_property_set_link(OBJECT(&s->lpd.crl),
73
+ name, OBJECT(&s->lpd.iou.gem[i]),
74
+ &error_abort);
75
+ }
76
+
77
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
78
+ g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
79
+
80
+ object_property_set_link(OBJECT(&s->lpd.crl),
81
+ name, OBJECT(&s->lpd.iou.adma[i]),
82
+ &error_abort);
83
+ }
84
+
85
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
86
+ g_autofree gchar *name = g_strdup_printf("uart[%d]", i);
87
+
88
+ object_property_set_link(OBJECT(&s->lpd.crl),
89
+ name, OBJECT(&s->lpd.iou.uart[i]),
90
+ &error_abort);
91
+ }
92
+
93
+ object_property_set_link(OBJECT(&s->lpd.crl),
94
+ "usb", OBJECT(&s->lpd.iou.usb),
95
+ &error_abort);
96
+
97
+ sysbus_realize(sbd, &error_fatal);
98
+ memory_region_add_subregion(&s->mr_ps, MM_CRL,
99
+ sysbus_mmio_get_region(sbd, 0));
100
+ sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]);
101
+}
102
+
103
/* This takes the board allocated linear DDR memory and creates aliases
104
* for each split DDR range/aperture on the Versal address map.
105
*/
106
@@ -XXX,XX +XXX,XX @@ static void versal_unimp(Versal *s)
107
108
versal_unimp_area(s, "psm", &s->mr_ps,
109
MM_PSM_START, MM_PSM_END - MM_PSM_START);
110
- versal_unimp_area(s, "crl", &s->mr_ps,
111
- MM_CRL, MM_CRL_SIZE);
112
versal_unimp_area(s, "crf", &s->mr_ps,
113
MM_FPD_CRF, MM_FPD_CRF_SIZE);
114
versal_unimp_area(s, "apu", &s->mr_ps,
115
@@ -XXX,XX +XXX,XX @@ static void versal_realize(DeviceState *dev, Error **errp)
116
versal_create_efuse(s, pic);
117
versal_create_pmc_iou_slcr(s, pic);
118
versal_create_ospi(s, pic);
119
+ versal_create_crl(s, pic);
120
versal_map_ddr(s);
121
versal_unimp(s);
23
122
24
--
123
--
25
2.18.0
124
2.25.1
26
27
diff view generated by jsdifflib
New patch
1
The Exynos4210 SoC device currently uses a custom device
2
"exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ
3
line. We have a standard TYPE_OR_IRQ device for this now, so use
4
that instead.
1
5
6
(This is a migration compatibility break, but that is OK for this
7
machine type.)
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220404154658.565020-2-peter.maydell@linaro.org
12
---
13
include/hw/arm/exynos4210.h | 1 +
14
hw/arm/exynos4210.c | 31 ++++++++++++++++---------------
15
2 files changed, 17 insertions(+), 15 deletions(-)
16
17
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/exynos4210.h
20
+++ b/include/hw/arm/exynos4210.h
21
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
22
MemoryRegion bootreg_mem;
23
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
24
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
25
+ qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
26
};
27
28
#define TYPE_EXYNOS4210_SOC "exynos4210"
29
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/exynos4210.c
32
+++ b/hw/arm/exynos4210.c
33
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
34
{
35
Exynos4210State *s = EXYNOS4210_SOC(socdev);
36
MemoryRegion *system_mem = get_system_memory();
37
- qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
38
SysBusDevice *busdev;
39
DeviceState *dev, *uart[4], *pl330[3];
40
int i, n;
41
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
42
43
/* IRQ Gate */
44
for (i = 0; i < EXYNOS4210_NCPUS; i++) {
45
- dev = qdev_new("exynos4210.irq_gate");
46
- qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS);
47
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
48
- /* Get IRQ Gate input in gate_irq */
49
- for (n = 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) {
50
- gate_irq[i][n] = qdev_get_gpio_in(dev, n);
51
- }
52
- busdev = SYS_BUS_DEVICE(dev);
53
-
54
- /* Connect IRQ Gate output to CPU's IRQ line */
55
- sysbus_connect_irq(busdev, 0,
56
- qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
57
+ DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
58
+ object_property_set_int(OBJECT(orgate), "num-lines",
59
+ EXYNOS4210_IRQ_GATE_NINPUTS,
60
+ &error_abort);
61
+ qdev_realize(orgate, NULL, &error_abort);
62
+ qdev_connect_gpio_out(orgate, 0,
63
+ qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ));
64
}
65
66
/* Private memory region and Internal GIC */
67
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
68
sysbus_realize_and_unref(busdev, &error_fatal);
69
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
70
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
71
- sysbus_connect_irq(busdev, n, gate_irq[n][0]);
72
+ sysbus_connect_irq(busdev, n,
73
+ qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
74
}
75
for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
76
s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
77
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
78
/* Map Distributer interface */
79
sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR);
80
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
81
- sysbus_connect_irq(busdev, n, gate_irq[n][1]);
82
+ sysbus_connect_irq(busdev, n,
83
+ qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
84
}
85
for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
86
s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
87
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
88
object_initialize_child(obj, name, orgate, TYPE_OR_IRQ);
89
g_free(name);
90
}
91
+
92
+ for (i = 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) {
93
+ g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
94
+ object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
95
+ }
96
}
97
98
static void exynos4210_class_init(ObjectClass *klass, void *data)
99
--
100
2.25.1
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can
2
delete the device entirely.
2
3
3
These insns require u=1; failed to include that in the switch
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
cases. This probably happened during one of the rebases just
5
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
5
before final commit.
6
Message-id: 20220404154658.565020-3-peter.maydell@linaro.org
7
---
8
hw/intc/exynos4210_gic.c | 107 ---------------------------------------
9
1 file changed, 107 deletions(-)
6
10
7
Fixes: d17b7cdcf4e
11
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Message-id: 20180810193129.1556-6-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/translate-a64.c | 12 ++++++------
14
1 file changed, 6 insertions(+), 6 deletions(-)
15
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
13
--- a/hw/intc/exynos4210_gic.c
19
+++ b/target/arm/translate-a64.c
14
+++ b/hw/intc/exynos4210_gic.c
20
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
15
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_register_types(void)
21
}
16
}
22
feature = ARM_FEATURE_V8_DOTPROD;
17
23
break;
18
type_init(exynos4210_gic_register_types)
24
- case 0x8: /* FCMLA, #0 */
19
-
25
- case 0x9: /* FCMLA, #90 */
20
-/* IRQ OR Gate struct.
26
- case 0xa: /* FCMLA, #180 */
21
- *
27
- case 0xb: /* FCMLA, #270 */
22
- * This device models an OR gate. There are n_in input qdev gpio lines and one
28
- case 0xc: /* FCADD, #90 */
23
- * output sysbus IRQ line. The output IRQ level is formed as OR between all
29
- case 0xe: /* FCADD, #270 */
24
- * gpio inputs.
30
+ case 0x18: /* FCMLA, #0 */
25
- */
31
+ case 0x19: /* FCMLA, #90 */
26
-
32
+ case 0x1a: /* FCMLA, #180 */
27
-#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
33
+ case 0x1b: /* FCMLA, #270 */
28
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE)
34
+ case 0x1c: /* FCADD, #90 */
29
-
35
+ case 0x1e: /* FCADD, #270 */
30
-struct Exynos4210IRQGateState {
36
if (size == 0
31
- SysBusDevice parent_obj;
37
|| (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
32
-
38
|| (size == 3 && !is_q)) {
33
- uint32_t n_in; /* inputs amount */
34
- uint32_t *level; /* input levels */
35
- qemu_irq out; /* output IRQ */
36
-};
37
-
38
-static Property exynos4210_irq_gate_properties[] = {
39
- DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
40
- DEFINE_PROP_END_OF_LIST(),
41
-};
42
-
43
-static const VMStateDescription vmstate_exynos4210_irq_gate = {
44
- .name = "exynos4210.irq_gate",
45
- .version_id = 2,
46
- .minimum_version_id = 2,
47
- .fields = (VMStateField[]) {
48
- VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in),
49
- VMSTATE_END_OF_LIST()
50
- }
51
-};
52
-
53
-/* Process a change in IRQ input. */
54
-static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
55
-{
56
- Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque;
57
- uint32_t i;
58
-
59
- assert(irq < s->n_in);
60
-
61
- s->level[irq] = level;
62
-
63
- for (i = 0; i < s->n_in; i++) {
64
- if (s->level[i] >= 1) {
65
- qemu_irq_raise(s->out);
66
- return;
67
- }
68
- }
69
-
70
- qemu_irq_lower(s->out);
71
-}
72
-
73
-static void exynos4210_irq_gate_reset(DeviceState *d)
74
-{
75
- Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);
76
-
77
- memset(s->level, 0, s->n_in * sizeof(*s->level));
78
-}
79
-
80
-/*
81
- * IRQ Gate initialization.
82
- */
83
-static void exynos4210_irq_gate_init(Object *obj)
84
-{
85
- Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj);
86
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
87
-
88
- sysbus_init_irq(sbd, &s->out);
89
-}
90
-
91
-static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp)
92
-{
93
- Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);
94
-
95
- /* Allocate general purpose input signals and connect a handler to each of
96
- * them */
97
- qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);
98
-
99
- s->level = g_malloc0(s->n_in * sizeof(*s->level));
100
-}
101
-
102
-static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
103
-{
104
- DeviceClass *dc = DEVICE_CLASS(klass);
105
-
106
- dc->reset = exynos4210_irq_gate_reset;
107
- dc->vmsd = &vmstate_exynos4210_irq_gate;
108
- device_class_set_props(dc, exynos4210_irq_gate_properties);
109
- dc->realize = exynos4210_irq_gate_realize;
110
-}
111
-
112
-static const TypeInfo exynos4210_irq_gate_info = {
113
- .name = TYPE_EXYNOS4210_IRQ_GATE,
114
- .parent = TYPE_SYS_BUS_DEVICE,
115
- .instance_size = sizeof(Exynos4210IRQGateState),
116
- .instance_init = exynos4210_irq_gate_init,
117
- .class_init = exynos4210_irq_gate_class_init,
118
-};
119
-
120
-static void exynos4210_irq_gate_register_types(void)
121
-{
122
- type_register_static(&exynos4210_irq_gate_info);
123
-}
124
-
125
-type_init(exynos4210_irq_gate_register_types)
39
--
126
--
40
2.18.0
127
2.25.1
41
42
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
The exynos4210 SoC mostly creates its child devices as if it were
2
board code. This includes the a9mpcore object. Switch that to a
3
new-style "embedded in the state struct" creation, because in the
4
next commit we're going to want to refer to the object again further
5
down in the exynos4210_realize() function.
2
6
3
This fixes the intended protection of read-only values in the
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
configuration register. They were being always set to zero by mistake.
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20220404154658.565020-4-peter.maydell@linaro.org
10
---
11
include/hw/arm/exynos4210.h | 2 ++
12
hw/arm/exynos4210.c | 11 ++++++-----
13
2 files changed, 8 insertions(+), 5 deletions(-)
5
14
6
The read-only fields depend on the configured memory size of the system,
15
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
7
so they cannot be fixed at compile time. The most straight forward
8
option was to store them in the state structure.
9
10
Signed-off-by: Joel Stanley <joel@jms.id.au>
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Tested-by: Cédric Le Goater <clg@kaod.org>
13
Message-id: 20180807075757.7242-3-joel@jms.id.au
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/misc/aspeed_sdmc.h | 1 +
17
hw/misc/aspeed_sdmc.c | 27 ++++++++-------------------
18
2 files changed, 9 insertions(+), 19 deletions(-)
19
20
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
21
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/misc/aspeed_sdmc.h
17
--- a/include/hw/arm/exynos4210.h
23
+++ b/include/hw/misc/aspeed_sdmc.h
18
+++ b/include/hw/arm/exynos4210.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDMCState {
19
@@ -XXX,XX +XXX,XX @@
25
uint32_t silicon_rev;
20
26
uint32_t ram_bits;
21
#include "hw/or-irq.h"
27
uint64_t ram_size;
22
#include "hw/sysbus.h"
28
+ uint32_t fixed_conf;
23
+#include "hw/cpu/a9mpcore.h"
29
24
#include "target/arm/cpu-qom.h"
30
} AspeedSDMCState;
25
#include "qom/object.h"
31
26
32
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
27
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
28
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
29
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
30
qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
31
+ A9MPPrivState a9mpcore;
32
};
33
34
#define TYPE_EXYNOS4210_SOC "exynos4210"
35
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
33
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/misc/aspeed_sdmc.c
37
--- a/hw/arm/exynos4210.c
35
+++ b/hw/misc/aspeed_sdmc.c
38
+++ b/hw/arm/exynos4210.c
36
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
39
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
37
case AST2400_A0_SILICON_REV:
40
}
38
case AST2400_A1_SILICON_REV:
41
39
data &= ~ASPEED_SDMC_READONLY_MASK;
42
/* Private memory region and Internal GIC */
40
+ data |= s->fixed_conf;
43
- dev = qdev_new(TYPE_A9MPCORE_PRIV);
41
break;
44
- qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
42
case AST2500_A0_SILICON_REV:
45
- busdev = SYS_BUS_DEVICE(dev);
43
case AST2500_A1_SILICON_REV:
46
- sysbus_realize_and_unref(busdev, &error_fatal);
44
data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
47
+ qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS);
45
+ data |= s->fixed_conf;
48
+ busdev = SYS_BUS_DEVICE(&s->a9mpcore);
46
break;
49
+ sysbus_realize(busdev, &error_fatal);
47
default:
50
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
48
g_assert_not_reached();
51
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
49
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_reset(DeviceState *dev)
52
sysbus_connect_irq(busdev, n,
50
memset(s->regs, 0, sizeof(s->regs));
53
qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
51
54
}
52
/* Set ram size bit and defaults values */
55
for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
53
- switch (s->silicon_rev) {
56
- s->irqs.int_gic_irq[n] = qdev_get_gpio_in(dev, n);
54
- case AST2400_A0_SILICON_REV:
57
+ s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
55
- case AST2400_A1_SILICON_REV:
58
}
56
- s->regs[R_CONF] |=
59
57
- ASPEED_SDMC_VGA_COMPAT |
60
/* Cache controller */
58
- ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
61
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
59
- break;
62
g_autofree char *name = g_strdup_printf("cpu-irq-orgate%d", i);
60
-
63
object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
61
- case AST2500_A0_SILICON_REV:
64
}
62
- case AST2500_A1_SILICON_REV:
65
+
63
- s->regs[R_CONF] |=
66
+ object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
64
- ASPEED_SDMC_HW_VERSION(1) |
65
- ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
66
- ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
67
- break;
68
-
69
- default:
70
- g_assert_not_reached();
71
- }
72
+ s->regs[R_CONF] = s->fixed_conf;
73
}
67
}
74
68
75
static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
69
static void exynos4210_class_init(ObjectClass *klass, void *data)
76
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
77
case AST2400_A0_SILICON_REV:
78
case AST2400_A1_SILICON_REV:
79
s->ram_bits = ast2400_rambits(s);
80
+ s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
81
+ ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
82
break;
83
case AST2500_A0_SILICON_REV:
84
case AST2500_A1_SILICON_REV:
85
s->ram_bits = ast2500_rambits(s);
86
+ s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
87
+ ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
88
+ ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
89
break;
90
default:
91
g_assert_not_reached();
92
--
70
--
93
2.18.0
71
2.25.1
94
95
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The only time we use the int_gic_irq[] array in the Exynos4210Irq
2
struct is in the exynos4210_realize() function: we initialize it with
3
the GPIO inputs of the a9mpcore device, and then a bit later on we
4
connect those to the outputs of the internal combiner. Now that the
5
a9mpcore object is easily accessible as s->a9mpcore we can make the
6
connection directly from one device to the other without going via
7
this array.
2
8
3
This makes float16_muladd correctly use FZ16 not FZ.
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220404154658.565020-5-peter.maydell@linaro.org
12
---
13
include/hw/arm/exynos4210.h | 1 -
14
hw/arm/exynos4210.c | 6 ++----
15
2 files changed, 2 insertions(+), 5 deletions(-)
4
16
5
Fixes: 6ceabaad110
17
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
6
Cc: qemu-stable@nongnu.org (3.0.1)
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20180810193129.1556-4-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/sve_helper.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
18
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/sve_helper.c
19
--- a/include/hw/arm/exynos4210.h
20
+++ b/target/arm/sve_helper.c
20
+++ b/include/hw/arm/exynos4210.h
21
@@ -XXX,XX +XXX,XX @@ static void do_fmla_zpzzz_h(CPUARMState *env, void *vg, uint32_t desc,
21
@@ -XXX,XX +XXX,XX @@
22
e1 = *(uint16_t *)(vn + H1_2(i)) ^ neg1;
22
typedef struct Exynos4210Irq {
23
e2 = *(uint16_t *)(vm + H1_2(i));
23
qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
24
e3 = *(uint16_t *)(va + H1_2(i)) ^ neg3;
24
qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
25
- r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status);
25
- qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
26
+ r = float16_muladd(e1, e2, e3, 0, &env->vfp.fp_status_f16);
26
qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
27
*(uint16_t *)(vd + H1_2(i)) = r;
27
qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
28
}
28
} Exynos4210Irq;
29
} while (i & 63);
29
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/exynos4210.c
32
+++ b/hw/arm/exynos4210.c
33
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
34
sysbus_connect_irq(busdev, n,
35
qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 0));
36
}
37
- for (n = 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
38
- s->irqs.int_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
39
- }
40
41
/* Cache controller */
42
sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
43
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
44
busdev = SYS_BUS_DEVICE(dev);
45
sysbus_realize_and_unref(busdev, &error_fatal);
46
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
47
- sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]);
48
+ sysbus_connect_irq(busdev, n,
49
+ qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
50
}
51
exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
52
sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
30
--
53
--
31
2.18.0
54
2.25.1
32
33
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The exynos4210 code currently has two very similar arrays of IRQs:
2
2
3
When FZ is set, input_denormal exceptions are recognized, but this does
3
* board_irqs is a field of the Exynos4210Irq struct which is filled
4
not happen with FZ16. The softfloat code has no way to distinguish
4
in by exynos4210_init_board_irqs() with the appropriate qemu_irqs
5
these bits and will raise such exceptions into fp_status_f16.flags,
5
for each IRQ the board/SoC can assert
6
so ignore them when computing the accumulated flags.
6
* irq_table is a set of qemu_irqs pointed to from the
7
Exynos4210State struct. It's allocated in exynos4210_init_irq,
8
and the only behaviour these irqs have is that they pass on the
9
level to the equivalent board_irqs[] irq
7
10
8
Cc: qemu-stable@nongnu.org (3.0.1)
11
The extra indirection through irq_table is unnecessary, so coalesce
9
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
12
these into a single irq_table[] array as a direct field in
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Exynos4210State which exynos4210_init_board_irqs() fills in.
11
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
14
12
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
13
Message-id: 20180810193129.1556-3-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20220404154658.565020-6-peter.maydell@linaro.org
15
---
18
---
16
target/arm/helper.c | 6 +++++-
19
include/hw/arm/exynos4210.h | 8 ++------
17
1 file changed, 5 insertions(+), 1 deletion(-)
20
hw/arm/exynos4210.c | 6 +-----
21
hw/intc/exynos4210_gic.c | 32 ++++++++------------------------
22
3 files changed, 11 insertions(+), 35 deletions(-)
18
23
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
24
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
20
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
26
--- a/include/hw/arm/exynos4210.h
22
+++ b/target/arm/helper.c
27
+++ b/include/hw/arm/exynos4210.h
23
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
28
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
24
fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
29
qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
25
| (env->vfp.vec_len << 16)
30
qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
26
| (env->vfp.vec_stride << 20);
31
qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
27
+
32
- qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
28
i = get_float_exception_flags(&env->vfp.fp_status);
33
} Exynos4210Irq;
29
i |= get_float_exception_flags(&env->vfp.standard_fp_status);
34
30
- i |= get_float_exception_flags(&env->vfp.fp_status_f16);
35
struct Exynos4210State {
31
+ /* FZ16 does not generate an input denormal exception. */
36
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
32
+ i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
37
/*< public >*/
33
+ & ~float_flag_input_denormal);
38
ARMCPU *cpu[EXYNOS4210_NCPUS];
34
+
39
Exynos4210Irq irqs;
35
fpscr |= vfp_exceptbits_from_host(i);
40
- qemu_irq *irq_table;
36
return fpscr;
41
+ qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
42
43
MemoryRegion chipid_mem;
44
MemoryRegion iram_mem;
45
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
46
void exynos4210_write_secondary(ARMCPU *cpu,
47
const struct arm_boot_info *info);
48
49
-/* Initialize exynos4210 IRQ subsystem stub */
50
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
51
-
52
/* Initialize board IRQs.
53
* These IRQs contain splitted Int/External Combiner and External Gic IRQs */
54
-void exynos4210_init_board_irqs(Exynos4210Irq *s);
55
+void exynos4210_init_board_irqs(Exynos4210State *s);
56
57
/* Get IRQ number from exynos4210 IRQ subsystem stub.
58
* To identify IRQ source use internal combiner group and bit number
59
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/exynos4210.c
62
+++ b/hw/arm/exynos4210.c
63
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
64
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
65
}
66
67
- /*** IRQs ***/
68
-
69
- s->irq_table = exynos4210_init_irq(&s->irqs);
70
-
71
/* IRQ Gate */
72
for (i = 0; i < EXYNOS4210_NCPUS; i++) {
73
DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
74
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
75
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
76
77
/* Initialize board IRQs. */
78
- exynos4210_init_board_irqs(&s->irqs);
79
+ exynos4210_init_board_irqs(s);
80
81
/*** Memory ***/
82
83
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/hw/intc/exynos4210_gic.c
86
+++ b/hw/intc/exynos4210_gic.c
87
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
88
#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
89
#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
90
91
-static void exynos4210_irq_handler(void *opaque, int irq, int level)
92
-{
93
- Exynos4210Irq *s = (Exynos4210Irq *)opaque;
94
-
95
- /* Bypass */
96
- qemu_set_irq(s->board_irqs[irq], level);
97
-}
98
-
99
-/*
100
- * Initialize exynos4210 IRQ subsystem stub.
101
- */
102
-qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
103
-{
104
- return qemu_allocate_irqs(exynos4210_irq_handler, s,
105
- EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
106
-}
107
-
108
/*
109
* Initialize board IRQs.
110
* These IRQs contain splitted Int/External Combiner and External Gic IRQs.
111
*/
112
-void exynos4210_init_board_irqs(Exynos4210Irq *s)
113
+void exynos4210_init_board_irqs(Exynos4210State *s)
114
{
115
uint32_t grp, bit, irq_id, n;
116
+ Exynos4210Irq *is = &s->irqs;
117
118
for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
119
irq_id = 0;
120
@@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
121
irq_id = EXT_GIC_ID_MCT_G1;
122
}
123
if (irq_id) {
124
- s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
125
- s->ext_gic_irq[irq_id-32]);
126
+ s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
127
+ is->ext_gic_irq[irq_id - 32]);
128
} else {
129
- s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
130
- s->ext_combiner_irq[n]);
131
+ s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
132
+ is->ext_combiner_irq[n]);
133
}
134
}
135
for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
136
@@ -XXX,XX +XXX,XX @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
137
EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
138
139
if (irq_id) {
140
- s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
141
- s->ext_gic_irq[irq_id-32]);
142
+ s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
143
+ is->ext_gic_irq[irq_id - 32]);
144
}
145
}
37
}
146
}
38
--
147
--
39
2.18.0
148
2.25.1
40
41
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
Fix a missing set of spaces around '-' in the definition of
2
combiner_grp_to_gic_id[]. We're about to move this code, so
3
fix the style issue first to keep checkpatch happy with the
4
code-motion patch.
2
5
3
The SDMC on the ast2500 has 170 registers.
4
5
Signed-off-by: Joel Stanley <joel@jms.id.au>
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
7
Tested-by: Cédric Le Goater <clg@kaod.org>
8
Message-id: 20180807075757.7242-2-joel@jms.id.au
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220404154658.565020-7-peter.maydell@linaro.org
10
---
9
---
11
include/hw/misc/aspeed_sdmc.h | 2 +-
10
hw/intc/exynos4210_gic.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
11
1 file changed, 1 insertion(+), 1 deletion(-)
13
12
14
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
13
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/misc/aspeed_sdmc.h
15
--- a/hw/intc/exynos4210_gic.c
17
+++ b/include/hw/misc/aspeed_sdmc.h
16
+++ b/hw/intc/exynos4210_gic.c
18
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ enum ExtInt {
19
#define TYPE_ASPEED_SDMC "aspeed.sdmc"
18
*/
20
#define ASPEED_SDMC(obj) OBJECT_CHECK(AspeedSDMCState, (obj), TYPE_ASPEED_SDMC)
19
21
20
static const uint32_t
22
-#define ASPEED_SDMC_NR_REGS (0x8 >> 2)
21
-combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
23
+#define ASPEED_SDMC_NR_REGS (0x174 >> 2)
22
+combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
24
23
/* int combiner groups 16-19 */
25
typedef struct AspeedSDMCState {
24
{ }, { }, { }, { },
26
/*< private >*/
25
/* int combiner group 20 */
27
--
26
--
28
2.18.0
27
2.25.1
29
30
diff view generated by jsdifflib
1
From: Stefan Hajnoczi <stefanha@redhat.com>
1
The function exynos4210_init_board_irqs() currently lives in
2
exynos4210_gic.c, but it isn't really part of the exynos4210.gic
3
device -- it is a function that implements (some of) the wiring up of
4
interrupts between the SoC's GIC and combiner components. This means
5
it fits better in exynos4210.c, which is the SoC-level code. Move it
6
there. Similarly, exynos4210_git_irq() is used almost only in the
7
SoC-level code, so move it too.
2
8
3
Image file loaders may add a series of roms. If an error occurs partway
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
through loading there is no easy way to drop previously added roms.
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220404154658.565020-8-peter.maydell@linaro.org
12
---
13
include/hw/arm/exynos4210.h | 4 -
14
hw/arm/exynos4210.c | 202 +++++++++++++++++++++++++++++++++++
15
hw/intc/exynos4210_gic.c | 204 ------------------------------------
16
3 files changed, 202 insertions(+), 208 deletions(-)
5
17
6
This patch adds a transaction mechanism that works like this:
18
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
7
8
rom_transaction_begin();
9
...call rom_add_*()...
10
rom_transaction_end(ok);
11
12
If ok is false then roms added in this transaction are dropped.
13
14
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
16
Message-id: 20180814162739.11814-5-stefanha@redhat.com
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
include/hw/loader.h | 19 +++++++++++++++++++
20
hw/core/loader.c | 32 ++++++++++++++++++++++++++++++++
21
2 files changed, 51 insertions(+)
22
23
diff --git a/include/hw/loader.h b/include/hw/loader.h
24
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
25
--- a/include/hw/loader.h
20
--- a/include/hw/arm/exynos4210.h
26
+++ b/include/hw/loader.h
21
+++ b/include/hw/arm/exynos4210.h
27
@@ -XXX,XX +XXX,XX @@ int rom_check_and_register_reset(void);
22
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
28
void rom_set_fw(FWCfgState *f);
23
void exynos4210_write_secondary(ARMCPU *cpu,
29
void rom_set_order_override(int order);
24
const struct arm_boot_info *info);
30
void rom_reset_order_override(void);
25
31
+
26
-/* Initialize board IRQs.
32
+/**
27
- * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
33
+ * rom_transaction_begin:
28
-void exynos4210_init_board_irqs(Exynos4210State *s);
34
+ *
29
-
35
+ * Call this before of a series of rom_add_*() calls. Call
30
/* Get IRQ number from exynos4210 IRQ subsystem stub.
36
+ * rom_transaction_end() afterwards to commit or abort. These functions are
31
* To identify IRQ source use internal combiner group and bit number
37
+ * useful for undoing a series of rom_add_*() calls if image file loading fails
32
* grp - group number
38
+ * partway through.
33
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/exynos4210.c
36
+++ b/hw/arm/exynos4210.c
37
@@ -XXX,XX +XXX,XX @@
38
#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
39
#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
40
41
+enum ExtGicId {
42
+ EXT_GIC_ID_MDMA_LCD0 = 66,
43
+ EXT_GIC_ID_PDMA0,
44
+ EXT_GIC_ID_PDMA1,
45
+ EXT_GIC_ID_TIMER0,
46
+ EXT_GIC_ID_TIMER1,
47
+ EXT_GIC_ID_TIMER2,
48
+ EXT_GIC_ID_TIMER3,
49
+ EXT_GIC_ID_TIMER4,
50
+ EXT_GIC_ID_MCT_L0,
51
+ EXT_GIC_ID_WDT,
52
+ EXT_GIC_ID_RTC_ALARM,
53
+ EXT_GIC_ID_RTC_TIC,
54
+ EXT_GIC_ID_GPIO_XB,
55
+ EXT_GIC_ID_GPIO_XA,
56
+ EXT_GIC_ID_MCT_L1,
57
+ EXT_GIC_ID_IEM_APC,
58
+ EXT_GIC_ID_IEM_IEC,
59
+ EXT_GIC_ID_NFC,
60
+ EXT_GIC_ID_UART0,
61
+ EXT_GIC_ID_UART1,
62
+ EXT_GIC_ID_UART2,
63
+ EXT_GIC_ID_UART3,
64
+ EXT_GIC_ID_UART4,
65
+ EXT_GIC_ID_MCT_G0,
66
+ EXT_GIC_ID_I2C0,
67
+ EXT_GIC_ID_I2C1,
68
+ EXT_GIC_ID_I2C2,
69
+ EXT_GIC_ID_I2C3,
70
+ EXT_GIC_ID_I2C4,
71
+ EXT_GIC_ID_I2C5,
72
+ EXT_GIC_ID_I2C6,
73
+ EXT_GIC_ID_I2C7,
74
+ EXT_GIC_ID_SPI0,
75
+ EXT_GIC_ID_SPI1,
76
+ EXT_GIC_ID_SPI2,
77
+ EXT_GIC_ID_MCT_G1,
78
+ EXT_GIC_ID_USB_HOST,
79
+ EXT_GIC_ID_USB_DEVICE,
80
+ EXT_GIC_ID_MODEMIF,
81
+ EXT_GIC_ID_HSMMC0,
82
+ EXT_GIC_ID_HSMMC1,
83
+ EXT_GIC_ID_HSMMC2,
84
+ EXT_GIC_ID_HSMMC3,
85
+ EXT_GIC_ID_SDMMC,
86
+ EXT_GIC_ID_MIPI_CSI_4LANE,
87
+ EXT_GIC_ID_MIPI_DSI_4LANE,
88
+ EXT_GIC_ID_MIPI_CSI_2LANE,
89
+ EXT_GIC_ID_MIPI_DSI_2LANE,
90
+ EXT_GIC_ID_ONENAND_AUDI,
91
+ EXT_GIC_ID_ROTATOR,
92
+ EXT_GIC_ID_FIMC0,
93
+ EXT_GIC_ID_FIMC1,
94
+ EXT_GIC_ID_FIMC2,
95
+ EXT_GIC_ID_FIMC3,
96
+ EXT_GIC_ID_JPEG,
97
+ EXT_GIC_ID_2D,
98
+ EXT_GIC_ID_PCIe,
99
+ EXT_GIC_ID_MIXER,
100
+ EXT_GIC_ID_HDMI,
101
+ EXT_GIC_ID_HDMI_I2C,
102
+ EXT_GIC_ID_MFC,
103
+ EXT_GIC_ID_TVENC,
104
+};
105
+
106
+enum ExtInt {
107
+ EXT_GIC_ID_EXTINT0 = 48,
108
+ EXT_GIC_ID_EXTINT1,
109
+ EXT_GIC_ID_EXTINT2,
110
+ EXT_GIC_ID_EXTINT3,
111
+ EXT_GIC_ID_EXTINT4,
112
+ EXT_GIC_ID_EXTINT5,
113
+ EXT_GIC_ID_EXTINT6,
114
+ EXT_GIC_ID_EXTINT7,
115
+ EXT_GIC_ID_EXTINT8,
116
+ EXT_GIC_ID_EXTINT9,
117
+ EXT_GIC_ID_EXTINT10,
118
+ EXT_GIC_ID_EXTINT11,
119
+ EXT_GIC_ID_EXTINT12,
120
+ EXT_GIC_ID_EXTINT13,
121
+ EXT_GIC_ID_EXTINT14,
122
+ EXT_GIC_ID_EXTINT15
123
+};
124
+
125
+/*
126
+ * External GIC sources which are not from External Interrupt Combiner or
127
+ * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
128
+ * which is INTG16 in Internal Interrupt Combiner.
39
+ */
129
+ */
40
+void rom_transaction_begin(void);
130
+
41
+
131
+static const uint32_t
42
+/**
132
+combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
43
+ * rom_transaction_end:
133
+ /* int combiner groups 16-19 */
44
+ * @commit: true to commit added roms, false to drop added roms
134
+ { }, { }, { }, { },
45
+ *
135
+ /* int combiner group 20 */
46
+ * Call this after a series of rom_add_*() calls. See rom_transaction_begin().
136
+ { 0, EXT_GIC_ID_MDMA_LCD0 },
137
+ /* int combiner group 21 */
138
+ { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
139
+ /* int combiner group 22 */
140
+ { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
141
+ EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
142
+ /* int combiner group 23 */
143
+ { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
144
+ /* int combiner group 24 */
145
+ { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
146
+ /* int combiner group 25 */
147
+ { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
148
+ /* int combiner group 26 */
149
+ { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
150
+ EXT_GIC_ID_UART4 },
151
+ /* int combiner group 27 */
152
+ { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
153
+ EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
154
+ EXT_GIC_ID_I2C7 },
155
+ /* int combiner group 28 */
156
+ { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
157
+ /* int combiner group 29 */
158
+ { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
159
+ EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
160
+ /* int combiner group 30 */
161
+ { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
162
+ /* int combiner group 31 */
163
+ { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
164
+ /* int combiner group 32 */
165
+ { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
166
+ /* int combiner group 33 */
167
+ { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
168
+ /* int combiner group 34 */
169
+ { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
170
+ /* int combiner group 35 */
171
+ { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
172
+ /* int combiner group 36 */
173
+ { EXT_GIC_ID_MIXER },
174
+ /* int combiner group 37 */
175
+ { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
176
+ EXT_GIC_ID_EXTINT7 },
177
+ /* groups 38-50 */
178
+ { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
179
+ /* int combiner group 51 */
180
+ { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
181
+ /* group 52 */
182
+ { },
183
+ /* int combiner group 53 */
184
+ { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
185
+ /* groups 54-63 */
186
+ { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
187
+};
188
+
189
+/*
190
+ * Initialize board IRQs.
191
+ * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
47
+ */
192
+ */
48
+void rom_transaction_end(bool commit);
193
+static void exynos4210_init_board_irqs(Exynos4210State *s)
49
+
50
int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
51
void *rom_ptr(hwaddr addr, size_t size);
52
void hmp_info_roms(Monitor *mon, const QDict *qdict);
53
diff --git a/hw/core/loader.c b/hw/core/loader.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/core/loader.c
56
+++ b/hw/core/loader.c
57
@@ -XXX,XX +XXX,XX @@ struct Rom {
58
char *fw_dir;
59
char *fw_file;
60
61
+ bool committed;
62
+
63
hwaddr addr;
64
QTAILQ_ENTRY(Rom) next;
65
};
66
@@ -XXX,XX +XXX,XX @@ static void rom_insert(Rom *rom)
67
rom->as = &address_space_memory;
68
}
69
70
+ rom->committed = false;
71
+
72
/* List is ordered by load address in the same address space */
73
QTAILQ_FOREACH(item, &roms, next) {
74
if (rom_order_compare(rom, item)) {
75
@@ -XXX,XX +XXX,XX @@ void rom_reset_order_override(void)
76
fw_cfg_reset_order_override(fw_cfg);
77
}
78
79
+void rom_transaction_begin(void)
80
+{
194
+{
81
+ Rom *rom;
195
+ uint32_t grp, bit, irq_id, n;
82
+
196
+ Exynos4210Irq *is = &s->irqs;
83
+ /* Ignore ROMs added without the transaction API */
197
+
84
+ QTAILQ_FOREACH(rom, &roms, next) {
198
+ for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
85
+ rom->committed = true;
199
+ irq_id = 0;
200
+ if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
201
+ n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
202
+ /* MCT_G0 is passed to External GIC */
203
+ irq_id = EXT_GIC_ID_MCT_G0;
204
+ }
205
+ if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
206
+ n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
207
+ /* MCT_G1 is passed to External and GIC */
208
+ irq_id = EXT_GIC_ID_MCT_G1;
209
+ }
210
+ if (irq_id) {
211
+ s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
212
+ is->ext_gic_irq[irq_id - 32]);
213
+ } else {
214
+ s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
215
+ is->ext_combiner_irq[n]);
216
+ }
86
+ }
217
+ }
87
+}
218
+ for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
88
+
219
+ /* these IDs are passed to Internal Combiner and External GIC */
89
+void rom_transaction_end(bool commit)
220
+ grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
90
+{
221
+ bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
91
+ Rom *rom;
222
+ irq_id = combiner_grp_to_gic_id[grp -
92
+ Rom *tmp;
223
+ EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
93
+
224
+
94
+ QTAILQ_FOREACH_SAFE(rom, &roms, next, tmp) {
225
+ if (irq_id) {
95
+ if (rom->committed) {
226
+ s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
96
+ continue;
227
+ is->ext_gic_irq[irq_id - 32]);
97
+ }
98
+ if (commit) {
99
+ rom->committed = true;
100
+ } else {
101
+ QTAILQ_REMOVE(&roms, rom, next);
102
+ rom_free(rom);
103
+ }
228
+ }
104
+ }
229
+ }
105
+}
230
+}
106
+
231
+
107
static Rom *find_rom(hwaddr addr, size_t size)
232
+/*
108
{
233
+ * Get IRQ number from exynos4210 IRQ subsystem stub.
109
Rom *rom;
234
+ * To identify IRQ source use internal combiner group and bit number
235
+ * grp - group number
236
+ * bit - bit number inside group
237
+ */
238
+uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
239
+{
240
+ return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
241
+}
242
+
243
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
244
0x09, 0x00, 0x00, 0x00 };
245
246
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
247
index XXXXXXX..XXXXXXX 100644
248
--- a/hw/intc/exynos4210_gic.c
249
+++ b/hw/intc/exynos4210_gic.c
250
@@ -XXX,XX +XXX,XX @@
251
#include "hw/arm/exynos4210.h"
252
#include "qom/object.h"
253
254
-enum ExtGicId {
255
- EXT_GIC_ID_MDMA_LCD0 = 66,
256
- EXT_GIC_ID_PDMA0,
257
- EXT_GIC_ID_PDMA1,
258
- EXT_GIC_ID_TIMER0,
259
- EXT_GIC_ID_TIMER1,
260
- EXT_GIC_ID_TIMER2,
261
- EXT_GIC_ID_TIMER3,
262
- EXT_GIC_ID_TIMER4,
263
- EXT_GIC_ID_MCT_L0,
264
- EXT_GIC_ID_WDT,
265
- EXT_GIC_ID_RTC_ALARM,
266
- EXT_GIC_ID_RTC_TIC,
267
- EXT_GIC_ID_GPIO_XB,
268
- EXT_GIC_ID_GPIO_XA,
269
- EXT_GIC_ID_MCT_L1,
270
- EXT_GIC_ID_IEM_APC,
271
- EXT_GIC_ID_IEM_IEC,
272
- EXT_GIC_ID_NFC,
273
- EXT_GIC_ID_UART0,
274
- EXT_GIC_ID_UART1,
275
- EXT_GIC_ID_UART2,
276
- EXT_GIC_ID_UART3,
277
- EXT_GIC_ID_UART4,
278
- EXT_GIC_ID_MCT_G0,
279
- EXT_GIC_ID_I2C0,
280
- EXT_GIC_ID_I2C1,
281
- EXT_GIC_ID_I2C2,
282
- EXT_GIC_ID_I2C3,
283
- EXT_GIC_ID_I2C4,
284
- EXT_GIC_ID_I2C5,
285
- EXT_GIC_ID_I2C6,
286
- EXT_GIC_ID_I2C7,
287
- EXT_GIC_ID_SPI0,
288
- EXT_GIC_ID_SPI1,
289
- EXT_GIC_ID_SPI2,
290
- EXT_GIC_ID_MCT_G1,
291
- EXT_GIC_ID_USB_HOST,
292
- EXT_GIC_ID_USB_DEVICE,
293
- EXT_GIC_ID_MODEMIF,
294
- EXT_GIC_ID_HSMMC0,
295
- EXT_GIC_ID_HSMMC1,
296
- EXT_GIC_ID_HSMMC2,
297
- EXT_GIC_ID_HSMMC3,
298
- EXT_GIC_ID_SDMMC,
299
- EXT_GIC_ID_MIPI_CSI_4LANE,
300
- EXT_GIC_ID_MIPI_DSI_4LANE,
301
- EXT_GIC_ID_MIPI_CSI_2LANE,
302
- EXT_GIC_ID_MIPI_DSI_2LANE,
303
- EXT_GIC_ID_ONENAND_AUDI,
304
- EXT_GIC_ID_ROTATOR,
305
- EXT_GIC_ID_FIMC0,
306
- EXT_GIC_ID_FIMC1,
307
- EXT_GIC_ID_FIMC2,
308
- EXT_GIC_ID_FIMC3,
309
- EXT_GIC_ID_JPEG,
310
- EXT_GIC_ID_2D,
311
- EXT_GIC_ID_PCIe,
312
- EXT_GIC_ID_MIXER,
313
- EXT_GIC_ID_HDMI,
314
- EXT_GIC_ID_HDMI_I2C,
315
- EXT_GIC_ID_MFC,
316
- EXT_GIC_ID_TVENC,
317
-};
318
-
319
-enum ExtInt {
320
- EXT_GIC_ID_EXTINT0 = 48,
321
- EXT_GIC_ID_EXTINT1,
322
- EXT_GIC_ID_EXTINT2,
323
- EXT_GIC_ID_EXTINT3,
324
- EXT_GIC_ID_EXTINT4,
325
- EXT_GIC_ID_EXTINT5,
326
- EXT_GIC_ID_EXTINT6,
327
- EXT_GIC_ID_EXTINT7,
328
- EXT_GIC_ID_EXTINT8,
329
- EXT_GIC_ID_EXTINT9,
330
- EXT_GIC_ID_EXTINT10,
331
- EXT_GIC_ID_EXTINT11,
332
- EXT_GIC_ID_EXTINT12,
333
- EXT_GIC_ID_EXTINT13,
334
- EXT_GIC_ID_EXTINT14,
335
- EXT_GIC_ID_EXTINT15
336
-};
337
-
338
-/*
339
- * External GIC sources which are not from External Interrupt Combiner or
340
- * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
341
- * which is INTG16 in Internal Interrupt Combiner.
342
- */
343
-
344
-static const uint32_t
345
-combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
346
- /* int combiner groups 16-19 */
347
- { }, { }, { }, { },
348
- /* int combiner group 20 */
349
- { 0, EXT_GIC_ID_MDMA_LCD0 },
350
- /* int combiner group 21 */
351
- { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
352
- /* int combiner group 22 */
353
- { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
354
- EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
355
- /* int combiner group 23 */
356
- { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
357
- /* int combiner group 24 */
358
- { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
359
- /* int combiner group 25 */
360
- { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
361
- /* int combiner group 26 */
362
- { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
363
- EXT_GIC_ID_UART4 },
364
- /* int combiner group 27 */
365
- { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
366
- EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
367
- EXT_GIC_ID_I2C7 },
368
- /* int combiner group 28 */
369
- { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_HOST},
370
- /* int combiner group 29 */
371
- { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
372
- EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
373
- /* int combiner group 30 */
374
- { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
375
- /* int combiner group 31 */
376
- { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
377
- /* int combiner group 32 */
378
- { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
379
- /* int combiner group 33 */
380
- { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
381
- /* int combiner group 34 */
382
- { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
383
- /* int combiner group 35 */
384
- { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
385
- /* int combiner group 36 */
386
- { EXT_GIC_ID_MIXER },
387
- /* int combiner group 37 */
388
- { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
389
- EXT_GIC_ID_EXTINT7 },
390
- /* groups 38-50 */
391
- { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
392
- /* int combiner group 51 */
393
- { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
394
- /* group 52 */
395
- { },
396
- /* int combiner group 53 */
397
- { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
398
- /* groups 54-63 */
399
- { }, { }, { }, { }, { }, { }, { }, { }, { }, { }
400
-};
401
-
402
#define EXYNOS4210_GIC_NIRQ 160
403
404
#define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000
405
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
406
#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
407
#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
408
409
-/*
410
- * Initialize board IRQs.
411
- * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
412
- */
413
-void exynos4210_init_board_irqs(Exynos4210State *s)
414
-{
415
- uint32_t grp, bit, irq_id, n;
416
- Exynos4210Irq *is = &s->irqs;
417
-
418
- for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
419
- irq_id = 0;
420
- if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
421
- n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
422
- /* MCT_G0 is passed to External GIC */
423
- irq_id = EXT_GIC_ID_MCT_G0;
424
- }
425
- if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
426
- n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
427
- /* MCT_G1 is passed to External and GIC */
428
- irq_id = EXT_GIC_ID_MCT_G1;
429
- }
430
- if (irq_id) {
431
- s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
432
- is->ext_gic_irq[irq_id - 32]);
433
- } else {
434
- s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
435
- is->ext_combiner_irq[n]);
436
- }
437
- }
438
- for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
439
- /* these IDs are passed to Internal Combiner and External GIC */
440
- grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
441
- bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
442
- irq_id = combiner_grp_to_gic_id[grp -
443
- EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
444
-
445
- if (irq_id) {
446
- s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
447
- is->ext_gic_irq[irq_id - 32]);
448
- }
449
- }
450
-}
451
-
452
-/*
453
- * Get IRQ number from exynos4210 IRQ subsystem stub.
454
- * To identify IRQ source use internal combiner group and bit number
455
- * grp - group number
456
- * bit - bit number inside group
457
- */
458
-uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
459
-{
460
- return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
461
-}
462
-
463
-/********* GIC part *********/
464
-
465
#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
466
OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
467
110
--
468
--
111
2.18.0
469
2.25.1
112
113
diff view generated by jsdifflib
1
From: Su Hang <suhang16@mails.ucas.ac.cn>
1
Switch the creation of the external GIC to the new-style "embedded in
2
state struct" approach, so we can easily refer to the object
3
elsewhere during realize.
2
4
3
'test.hex' file is a memory test pattern stored in Hexadecimal Object
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Format. It loads at 0x10000 in RAM and contains values from 0 through
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
255.
7
Message-id: 20220404154658.565020-9-peter.maydell@linaro.org
8
---
9
include/hw/arm/exynos4210.h | 2 ++
10
include/hw/intc/exynos4210_gic.h | 43 ++++++++++++++++++++++++++++++++
11
hw/arm/exynos4210.c | 10 ++++----
12
hw/intc/exynos4210_gic.c | 17 ++-----------
13
MAINTAINERS | 2 +-
14
5 files changed, 53 insertions(+), 21 deletions(-)
15
create mode 100644 include/hw/intc/exynos4210_gic.h
6
16
7
The test case verifies that the expected memory test pattern was loaded.
17
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
8
9
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
10
Suggested-by: Steffen Gortz <qemu.ml@steffen-goertz.de>
11
Suggested-by: Stefan Hajnoczi <stefanha@redhat.com>
12
Signed-off-by: Su Hang <suhang16@mails.ucas.ac.cn>
13
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15
[PMM: changed qtest_startf() to qtest_initf() to work with
16
current master after the refactoring in commit 88b988c895e3c2]
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
configure | 4 +++
20
tests/Makefile.include | 2 ++
21
tests/hexloader-test.c | 45 ++++++++++++++++++++++++++++
22
MAINTAINERS | 6 ++++
23
tests/hex-loader-check-data/test.hex | 18 +++++++++++
24
5 files changed, 75 insertions(+)
25
create mode 100644 tests/hexloader-test.c
26
create mode 100644 tests/hex-loader-check-data/test.hex
27
28
diff --git a/configure b/configure
29
index XXXXXXX..XXXXXXX 100755
30
--- a/configure
31
+++ b/configure
32
@@ -XXX,XX +XXX,XX @@ for test_file in $(find $source_path/tests/acpi-test-data -type f)
33
do
34
FILES="$FILES tests/acpi-test-data$(echo $test_file | sed -e 's/.*acpi-test-data//')"
35
done
36
+for test_file in $(find $source_path/tests/hex-loader-check-data -type f)
37
+do
38
+ FILES="$FILES tests/hex-loader-check-data$(echo $test_file | sed -e 's/.*hex-loader-check-data//')"
39
+done
40
mkdir -p $DIRS
41
for f in $FILES ; do
42
if [ -e "$source_path/$f" ] && [ "$pwd_is_source_path" != "y" ]; then
43
diff --git a/tests/Makefile.include b/tests/Makefile.include
44
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
45
--- a/tests/Makefile.include
19
--- a/include/hw/arm/exynos4210.h
46
+++ b/tests/Makefile.include
20
+++ b/include/hw/arm/exynos4210.h
47
@@ -XXX,XX +XXX,XX @@ check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF)
21
@@ -XXX,XX +XXX,XX @@
48
gcov-files-arm-y += hw/timer/arm_mptimer.c
22
#include "hw/or-irq.h"
49
check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
23
#include "hw/sysbus.h"
50
check-qtest-arm-y += tests/sdhci-test$(EXESUF)
24
#include "hw/cpu/a9mpcore.h"
51
+check-qtest-arm-y += tests/hexloader-test$(EXESUF)
25
+#include "hw/intc/exynos4210_gic.h"
52
26
#include "target/arm/cpu-qom.h"
53
check-qtest-aarch64-y = tests/numa-test$(EXESUF)
27
#include "qom/object.h"
54
check-qtest-aarch64-y += tests/sdhci-test$(EXESUF)
28
55
@@ -XXX,XX +XXX,XX @@ tests/qmp-test$(EXESUF): tests/qmp-test.o
29
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
56
tests/device-introspect-test$(EXESUF): tests/device-introspect-test.o
30
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
57
tests/rtc-test$(EXESUF): tests/rtc-test.o
31
qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
58
tests/m48t59-test$(EXESUF): tests/m48t59-test.o
32
A9MPPrivState a9mpcore;
59
+tests/hexloader-test$(EXESUF): tests/hexloader-test.o
33
+ Exynos4210GicState ext_gic;
60
tests/endianness-test$(EXESUF): tests/endianness-test.o
34
};
61
tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y)
35
62
tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y)
36
#define TYPE_EXYNOS4210_SOC "exynos4210"
63
diff --git a/tests/hexloader-test.c b/tests/hexloader-test.c
37
diff --git a/include/hw/intc/exynos4210_gic.h b/include/hw/intc/exynos4210_gic.h
64
new file mode 100644
38
new file mode 100644
65
index XXXXXXX..XXXXXXX
39
index XXXXXXX..XXXXXXX
66
--- /dev/null
40
--- /dev/null
67
+++ b/tests/hexloader-test.c
41
+++ b/include/hw/intc/exynos4210_gic.h
68
@@ -XXX,XX +XXX,XX @@
42
@@ -XXX,XX +XXX,XX @@
69
+/*
43
+/*
70
+ * QTest testcase for the Intel Hexadecimal Object File Loader
44
+ * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
71
+ *
45
+ *
72
+ * Authors:
46
+ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
73
+ * Su Hang <suhang16@mails.ucas.ac.cn> 2018
47
+ * All rights reserved.
74
+ *
48
+ *
75
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
49
+ * Evgeny Voevodin <e.voevodin@samsung.com>
76
+ * See the COPYING file in the top-level directory.
77
+ *
50
+ *
51
+ * This program is free software; you can redistribute it and/or modify it
52
+ * under the terms of the GNU General Public License as published by the
53
+ * Free Software Foundation; either version 2 of the License, or (at your
54
+ * option) any later version.
55
+ *
56
+ * This program is distributed in the hope that it will be useful,
57
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
58
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
59
+ * See the GNU General Public License for more details.
60
+ *
61
+ * You should have received a copy of the GNU General Public License along
62
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
78
+ */
63
+ */
64
+#ifndef HW_INTC_EXYNOS4210_GIC_H
65
+#define HW_INTC_EXYNOS4210_GIC_H
79
+
66
+
80
+#include "qemu/osdep.h"
67
+#include "hw/sysbus.h"
81
+#include "libqtest.h"
82
+
68
+
83
+/* Load 'test.hex' and verify that the in-memory contents are as expected.
69
+#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
84
+ * 'test.hex' is a memory test pattern stored in Hexadecimal Object
70
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
85
+ * format. It loads at 0x10000 in RAM and contains values from 0 through
86
+ * 255.
87
+ */
88
+static void hex_loader_test(void)
89
+{
90
+ unsigned int i;
91
+ const unsigned int base_addr = 0x00010000;
92
+
71
+
93
+ QTestState *s = qtest_initf(
72
+#define EXYNOS4210_GIC_NCPUS 2
94
+ "-M vexpress-a9 -nographic -device loader,file=tests/hex-loader-check-data/test.hex");
95
+
73
+
96
+ for (i = 0; i < 256; ++i) {
74
+struct Exynos4210GicState {
97
+ uint8_t val = qtest_readb(s, base_addr + i);
75
+ SysBusDevice parent_obj;
98
+ g_assert_cmpuint(i, ==, val);
99
+ }
100
+ qtest_quit(s);
101
+}
102
+
76
+
103
+int main(int argc, char **argv)
77
+ MemoryRegion cpu_container;
104
+{
78
+ MemoryRegion dist_container;
105
+ int ret;
79
+ MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS];
80
+ MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS];
81
+ uint32_t num_cpu;
82
+ DeviceState *gic;
83
+};
106
+
84
+
107
+ g_test_init(&argc, &argv, NULL);
85
+#endif
108
+
86
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
109
+ qtest_add_func("/tmp/hex_loader", hex_loader_test);
87
index XXXXXXX..XXXXXXX 100644
110
+ ret = g_test_run();
88
--- a/hw/arm/exynos4210.c
111
+
89
+++ b/hw/arm/exynos4210.c
112
+ return ret;
90
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
113
+}
91
sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL);
92
93
/* External GIC */
94
- dev = qdev_new("exynos4210.gic");
95
- qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
96
- busdev = SYS_BUS_DEVICE(dev);
97
- sysbus_realize_and_unref(busdev, &error_fatal);
98
+ qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS);
99
+ busdev = SYS_BUS_DEVICE(&s->ext_gic);
100
+ sysbus_realize(busdev, &error_fatal);
101
/* Map CPU interface */
102
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR);
103
/* Map Distributer interface */
104
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
105
qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
106
}
107
for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
108
- s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(dev, n);
109
+ s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
110
}
111
112
/* Internal Interrupt Combiner */
113
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
114
}
115
116
object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
117
+ object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
118
}
119
120
static void exynos4210_class_init(ObjectClass *klass, void *data)
121
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
122
index XXXXXXX..XXXXXXX 100644
123
--- a/hw/intc/exynos4210_gic.c
124
+++ b/hw/intc/exynos4210_gic.c
125
@@ -XXX,XX +XXX,XX @@
126
#include "qemu/module.h"
127
#include "hw/irq.h"
128
#include "hw/qdev-properties.h"
129
+#include "hw/intc/exynos4210_gic.h"
130
#include "hw/arm/exynos4210.h"
131
#include "qom/object.h"
132
133
@@ -XXX,XX +XXX,XX @@
134
#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
135
#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
136
137
-#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
138
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC)
139
-
140
-struct Exynos4210GicState {
141
- SysBusDevice parent_obj;
142
-
143
- MemoryRegion cpu_container;
144
- MemoryRegion dist_container;
145
- MemoryRegion cpu_alias[EXYNOS4210_NCPUS];
146
- MemoryRegion dist_alias[EXYNOS4210_NCPUS];
147
- uint32_t num_cpu;
148
- DeviceState *gic;
149
-};
150
-
151
static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
152
{
153
Exynos4210GicState *s = (Exynos4210GicState *)opaque;
154
@@ -XXX,XX +XXX,XX @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp)
155
* enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86
156
* doesn't figure this out, otherwise and gives spurious warnings.
157
*/
158
- assert(n <= EXYNOS4210_NCPUS);
159
+ assert(n <= EXYNOS4210_GIC_NCPUS);
160
for (i = 0; i < n; i++) {
161
/* Map CPU interface per SMP Core */
162
sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
114
diff --git a/MAINTAINERS b/MAINTAINERS
163
diff --git a/MAINTAINERS b/MAINTAINERS
115
index XXXXXXX..XXXXXXX 100644
164
index XXXXXXX..XXXXXXX 100644
116
--- a/MAINTAINERS
165
--- a/MAINTAINERS
117
+++ b/MAINTAINERS
166
+++ b/MAINTAINERS
118
@@ -XXX,XX +XXX,XX @@ F: hw/core/generic-loader.c
167
@@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org>
119
F: include/hw/core/generic-loader.h
168
L: qemu-arm@nongnu.org
120
F: docs/generic-loader.txt
169
S: Odd Fixes
121
170
F: hw/*/exynos*
122
+Intel Hexadecimal Object File Loader
171
-F: include/hw/arm/exynos4210.h
123
+M: Su Hang <suhang16@mails.ucas.ac.cn>
172
+F: include/hw/*/exynos*
124
+S: Maintained
173
125
+F: tests/hexloader-test.c
174
Calxeda Highbank
126
+F: tests/hex-loader-check-data/test.hex
175
M: Rob Herring <robh@kernel.org>
127
+
128
CHRP NVRAM
129
M: Thomas Huth <thuth@redhat.com>
130
S: Maintained
131
diff --git a/tests/hex-loader-check-data/test.hex b/tests/hex-loader-check-data/test.hex
132
new file mode 100644
133
index XXXXXXX..XXXXXXX
134
--- /dev/null
135
+++ b/tests/hex-loader-check-data/test.hex
136
@@ -XXX,XX +XXX,XX @@
137
+:020000040001F9
138
+:10000000000102030405060708090a0b0c0d0e0f78
139
+:10001000101112131415161718191a1b1c1d1e1f68
140
+:10002000202122232425262728292a2b2c2d2e2f58
141
+:10003000303132333435363738393a3b3c3d3e3f48
142
+:10004000404142434445464748494a4b4c4d4e4f38
143
+:10005000505152535455565758595a5b5c5d5e5f28
144
+:10006000606162636465666768696a6b6c6d6e6f18
145
+:10007000707172737475767778797a7b7c7d7e7f08
146
+:10008000808182838485868788898a8b8c8d8e8ff8
147
+:10009000909192939495969798999a9b9c9d9e9fe8
148
+:1000a000a0a1a2a3a4a5a6a7a8a9aaabacadaeafd8
149
+:1000b000b0b1b2b3b4b5b6b7b8b9babbbcbdbebfc8
150
+:1000c000c0c1c2c3c4c5c6c7c8c9cacbcccdcecfb8
151
+:1000d000d0d1d2d3d4d5d6d7d8d9dadbdcdddedfa8
152
+:1000e000e0e1e2e3e4e5e6e7e8e9eaebecedeeef98
153
+:1000f000f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff88
154
+:00000001FF
155
--
176
--
156
2.18.0
177
2.25.1
157
158
diff view generated by jsdifflib
1
From: Su Hang <suhang16@mails.ucas.ac.cn>
1
The only time we use the ext_gic_irq[] array in the Exynos4210Irq
2
struct is during realize of the SoC -- we initialize it with the
3
input IRQs of the external GIC device, and then connect those to
4
outputs of other devices further on in realize (including in the
5
exynos4210_init_board_irqs() function). Now that the ext_gic object
6
is easily accessible as s->ext_gic we can make the connections
7
directly from one device to the other without going via this array.
2
8
3
This patch adds Intel Hexadecimal Object File format support to the
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
generic loader device. The file format specification is available here:
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
http://www.piclist.com/techref/fileext/hex/intel.htm
11
Message-id: 20220404154658.565020-10-peter.maydell@linaro.org
12
---
13
include/hw/arm/exynos4210.h | 1 -
14
hw/arm/exynos4210.c | 12 ++++++------
15
2 files changed, 6 insertions(+), 7 deletions(-)
6
16
7
This file format is often used with microcontrollers such as the
17
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
8
micro:bit, Arduino, STM32, etc. Users expect to be able to run .hex
9
files directly with without first converting them to ELF. Most
10
micro:bit code is developed in web-based IDEs without direct user access
11
to binutils so it is important for QEMU to handle this file format
12
natively.
13
14
Signed-off-by: Su Hang <suhang16@mails.ucas.ac.cn>
15
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
16
Acked-by: Alistair Francis <alistair.francis@wdc.com>
17
Message-id: 20180814162739.11814-6-stefanha@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
include/hw/loader.h | 12 ++
21
hw/core/generic-loader.c | 4 +
22
hw/core/loader.c | 249 +++++++++++++++++++++++++++++++++++++++
23
3 files changed, 265 insertions(+)
24
25
diff --git a/include/hw/loader.h b/include/hw/loader.h
26
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/loader.h
19
--- a/include/hw/arm/exynos4210.h
28
+++ b/include/hw/loader.h
20
+++ b/include/hw/arm/exynos4210.h
29
@@ -XXX,XX +XXX,XX @@ ssize_t load_image_size(const char *filename, void *addr, size_t size);
21
@@ -XXX,XX +XXX,XX @@
30
int load_image_targphys_as(const char *filename,
22
typedef struct Exynos4210Irq {
31
hwaddr addr, uint64_t max_sz, AddressSpace *as);
23
qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
32
24
qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
33
+/**load_targphys_hex_as:
25
- qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
34
+ * @filename: Path to the .hex file
26
} Exynos4210Irq;
35
+ * @entry: Store the entry point given by the .hex file
27
36
+ * @as: The AddressSpace to load the .hex file to. The value of
28
struct Exynos4210State {
37
+ * address_space_memory is used if nothing is supplied here.
29
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
38
+ *
39
+ * Load a fixed .hex file into memory.
40
+ *
41
+ * Returns the size of the loaded .hex file on success, -1 otherwise.
42
+ */
43
+int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as);
44
+
45
/** load_image_targphys:
46
* Same as load_image_targphys_as(), but doesn't allow the caller to specify
47
* an AddressSpace.
48
diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c
49
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/core/generic-loader.c
31
--- a/hw/arm/exynos4210.c
51
+++ b/hw/core/generic-loader.c
32
+++ b/hw/arm/exynos4210.c
52
@@ -XXX,XX +XXX,XX @@ static void generic_loader_realize(DeviceState *dev, Error **errp)
33
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
53
size = load_uimage_as(s->file, &entry, NULL, NULL, NULL, NULL,
34
{
54
as);
35
uint32_t grp, bit, irq_id, n;
55
}
36
Exynos4210Irq *is = &s->irqs;
56
+
37
+ DeviceState *extgicdev = DEVICE(&s->ext_gic);
57
+ if (size < 0) {
38
58
+ size = load_targphys_hex_as(s->file, &entry, as);
39
for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
59
+ }
40
irq_id = 0;
41
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
60
}
42
}
61
43
if (irq_id) {
62
if (size < 0 || s->force_raw) {
44
s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
63
diff --git a/hw/core/loader.c b/hw/core/loader.c
45
- is->ext_gic_irq[irq_id - 32]);
64
index XXXXXXX..XXXXXXX 100644
46
+ qdev_get_gpio_in(extgicdev,
65
--- a/hw/core/loader.c
47
+ irq_id - 32));
66
+++ b/hw/core/loader.c
48
} else {
67
@@ -XXX,XX +XXX,XX @@ void hmp_info_roms(Monitor *mon, const QDict *qdict)
49
s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
50
is->ext_combiner_irq[n]);
51
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
52
53
if (irq_id) {
54
s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
55
- is->ext_gic_irq[irq_id - 32]);
56
+ qdev_get_gpio_in(extgicdev,
57
+ irq_id - 32));
68
}
58
}
69
}
59
}
70
}
60
}
71
+
61
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
72
+typedef enum HexRecord HexRecord;
62
sysbus_connect_irq(busdev, n,
73
+enum HexRecord {
63
qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]), 1));
74
+ DATA_RECORD = 0,
64
}
75
+ EOF_RECORD,
65
- for (n = 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) {
76
+ EXT_SEG_ADDR_RECORD,
66
- s->irqs.ext_gic_irq[n] = qdev_get_gpio_in(DEVICE(&s->ext_gic), n);
77
+ START_SEG_ADDR_RECORD,
67
- }
78
+ EXT_LINEAR_ADDR_RECORD,
68
79
+ START_LINEAR_ADDR_RECORD,
69
/* Internal Interrupt Combiner */
80
+};
70
dev = qdev_new("exynos4210.combiner");
81
+
71
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
82
+/* Each record contains a 16-bit address which is combined with the upper 16
72
busdev = SYS_BUS_DEVICE(dev);
83
+ * bits of the implicit "next address" to form a 32-bit address.
73
sysbus_realize_and_unref(busdev, &error_fatal);
84
+ */
74
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
85
+#define NEXT_ADDR_MASK 0xffff0000
75
- sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]);
86
+
76
+ sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
87
+#define DATA_FIELD_MAX_LEN 0xff
77
}
88
+#define LEN_EXCEPT_DATA 0x5
78
exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
89
+/* 0x5 = sizeof(byte_count) + sizeof(address) + sizeof(record_type) +
79
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
90
+ * sizeof(checksum) */
91
+typedef struct {
92
+ uint8_t byte_count;
93
+ uint16_t address;
94
+ uint8_t record_type;
95
+ uint8_t data[DATA_FIELD_MAX_LEN];
96
+ uint8_t checksum;
97
+} HexLine;
98
+
99
+/* return 0 or -1 if error */
100
+static bool parse_record(HexLine *line, uint8_t *our_checksum, const uint8_t c,
101
+ uint32_t *index, const bool in_process)
102
+{
103
+ /* +-------+---------------+-------+---------------------+--------+
104
+ * | byte | |record | | |
105
+ * | count | address | type | data |checksum|
106
+ * +-------+---------------+-------+---------------------+--------+
107
+ * ^ ^ ^ ^ ^ ^
108
+ * |1 byte | 2 bytes |1 byte | 0-255 bytes | 1 byte |
109
+ */
110
+ uint8_t value = 0;
111
+ uint32_t idx = *index;
112
+ /* ignore space */
113
+ if (g_ascii_isspace(c)) {
114
+ return true;
115
+ }
116
+ if (!g_ascii_isxdigit(c) || !in_process) {
117
+ return false;
118
+ }
119
+ value = g_ascii_xdigit_value(c);
120
+ value = (idx & 0x1) ? (value & 0xf) : (value << 4);
121
+ if (idx < 2) {
122
+ line->byte_count |= value;
123
+ } else if (2 <= idx && idx < 6) {
124
+ line->address <<= 4;
125
+ line->address += g_ascii_xdigit_value(c);
126
+ } else if (6 <= idx && idx < 8) {
127
+ line->record_type |= value;
128
+ } else if (8 <= idx && idx < 8 + 2 * line->byte_count) {
129
+ line->data[(idx - 8) >> 1] |= value;
130
+ } else if (8 + 2 * line->byte_count <= idx &&
131
+ idx < 10 + 2 * line->byte_count) {
132
+ line->checksum |= value;
133
+ } else {
134
+ return false;
135
+ }
136
+ *our_checksum += value;
137
+ ++(*index);
138
+ return true;
139
+}
140
+
141
+typedef struct {
142
+ const char *filename;
143
+ HexLine line;
144
+ uint8_t *bin_buf;
145
+ hwaddr *start_addr;
146
+ int total_size;
147
+ uint32_t next_address_to_write;
148
+ uint32_t current_address;
149
+ uint32_t current_rom_index;
150
+ uint32_t rom_start_address;
151
+ AddressSpace *as;
152
+} HexParser;
153
+
154
+/* return size or -1 if error */
155
+static int handle_record_type(HexParser *parser)
156
+{
157
+ HexLine *line = &(parser->line);
158
+ switch (line->record_type) {
159
+ case DATA_RECORD:
160
+ parser->current_address =
161
+ (parser->next_address_to_write & NEXT_ADDR_MASK) | line->address;
162
+ /* verify this is a contiguous block of memory */
163
+ if (parser->current_address != parser->next_address_to_write) {
164
+ if (parser->current_rom_index != 0) {
165
+ rom_add_blob_fixed_as(parser->filename, parser->bin_buf,
166
+ parser->current_rom_index,
167
+ parser->rom_start_address, parser->as);
168
+ }
169
+ parser->rom_start_address = parser->current_address;
170
+ parser->current_rom_index = 0;
171
+ }
172
+
173
+ /* copy from line buffer to output bin_buf */
174
+ memcpy(parser->bin_buf + parser->current_rom_index, line->data,
175
+ line->byte_count);
176
+ parser->current_rom_index += line->byte_count;
177
+ parser->total_size += line->byte_count;
178
+ /* save next address to write */
179
+ parser->next_address_to_write =
180
+ parser->current_address + line->byte_count;
181
+ break;
182
+
183
+ case EOF_RECORD:
184
+ if (parser->current_rom_index != 0) {
185
+ rom_add_blob_fixed_as(parser->filename, parser->bin_buf,
186
+ parser->current_rom_index,
187
+ parser->rom_start_address, parser->as);
188
+ }
189
+ return parser->total_size;
190
+ case EXT_SEG_ADDR_RECORD:
191
+ case EXT_LINEAR_ADDR_RECORD:
192
+ if (line->byte_count != 2 && line->address != 0) {
193
+ return -1;
194
+ }
195
+
196
+ if (parser->current_rom_index != 0) {
197
+ rom_add_blob_fixed_as(parser->filename, parser->bin_buf,
198
+ parser->current_rom_index,
199
+ parser->rom_start_address, parser->as);
200
+ }
201
+
202
+ /* save next address to write,
203
+ * in case of non-contiguous block of memory */
204
+ parser->next_address_to_write = (line->data[0] << 12) |
205
+ (line->data[1] << 4);
206
+ if (line->record_type == EXT_LINEAR_ADDR_RECORD) {
207
+ parser->next_address_to_write <<= 12;
208
+ }
209
+
210
+ parser->rom_start_address = parser->next_address_to_write;
211
+ parser->current_rom_index = 0;
212
+ break;
213
+
214
+ case START_SEG_ADDR_RECORD:
215
+ if (line->byte_count != 4 && line->address != 0) {
216
+ return -1;
217
+ }
218
+
219
+ /* x86 16-bit CS:IP segmented addressing */
220
+ *(parser->start_addr) = (((line->data[0] << 8) | line->data[1]) << 4) +
221
+ ((line->data[2] << 8) | line->data[3]);
222
+ break;
223
+
224
+ case START_LINEAR_ADDR_RECORD:
225
+ if (line->byte_count != 4 && line->address != 0) {
226
+ return -1;
227
+ }
228
+
229
+ *(parser->start_addr) = ldl_be_p(line->data);
230
+ break;
231
+
232
+ default:
233
+ return -1;
234
+ }
235
+
236
+ return parser->total_size;
237
+}
238
+
239
+/* return size or -1 if error */
240
+static int parse_hex_blob(const char *filename, hwaddr *addr, uint8_t *hex_blob,
241
+ size_t hex_blob_size, AddressSpace *as)
242
+{
243
+ bool in_process = false; /* avoid re-enter and
244
+ * check whether record begin with ':' */
245
+ uint8_t *end = hex_blob + hex_blob_size;
246
+ uint8_t our_checksum = 0;
247
+ uint32_t record_index = 0;
248
+ HexParser parser = {
249
+ .filename = filename,
250
+ .bin_buf = g_malloc(hex_blob_size),
251
+ .start_addr = addr,
252
+ .as = as,
253
+ };
254
+
255
+ rom_transaction_begin();
256
+
257
+ for (; hex_blob < end; ++hex_blob) {
258
+ switch (*hex_blob) {
259
+ case '\r':
260
+ case '\n':
261
+ if (!in_process) {
262
+ break;
263
+ }
264
+
265
+ in_process = false;
266
+ if ((LEN_EXCEPT_DATA + parser.line.byte_count) * 2 !=
267
+ record_index ||
268
+ our_checksum != 0) {
269
+ parser.total_size = -1;
270
+ goto out;
271
+ }
272
+
273
+ if (handle_record_type(&parser) == -1) {
274
+ parser.total_size = -1;
275
+ goto out;
276
+ }
277
+ break;
278
+
279
+ /* start of a new record. */
280
+ case ':':
281
+ memset(&parser.line, 0, sizeof(HexLine));
282
+ in_process = true;
283
+ record_index = 0;
284
+ break;
285
+
286
+ /* decoding lines */
287
+ default:
288
+ if (!parse_record(&parser.line, &our_checksum, *hex_blob,
289
+ &record_index, in_process)) {
290
+ parser.total_size = -1;
291
+ goto out;
292
+ }
293
+ break;
294
+ }
295
+ }
296
+
297
+out:
298
+ g_free(parser.bin_buf);
299
+ rom_transaction_end(parser.total_size != -1);
300
+ return parser.total_size;
301
+}
302
+
303
+/* return size or -1 if error */
304
+int load_targphys_hex_as(const char *filename, hwaddr *entry, AddressSpace *as)
305
+{
306
+ gsize hex_blob_size;
307
+ gchar *hex_blob;
308
+ int total_size = 0;
309
+
310
+ if (!g_file_get_contents(filename, &hex_blob, &hex_blob_size, NULL)) {
311
+ return -1;
312
+ }
313
+
314
+ total_size = parse_hex_blob(filename, entry, (uint8_t *)hex_blob,
315
+ hex_blob_size, as);
316
+
317
+ g_free(hex_blob);
318
+ return total_size;
319
+}
320
--
80
--
321
2.18.0
81
2.25.1
322
323
diff view generated by jsdifflib
1
From: Stefan Hajnoczi <stefanha@redhat.com>
1
The function exynos4210_combiner_get_gpioin() currently lives in
2
exynos4210_combiner.c, but it isn't really part of the combiner
3
device itself -- it is a function that implements the wiring up of
4
some interrupt sources to multiple combiner inputs. Move it to live
5
with the other SoC-level code in exynos4210.c, along with a few
6
macros previously defined in exynos4210.h which are now used only
7
in exynos4210.c.
2
8
3
Define a "cortex-m0" ARMv6-M CPU model.
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20220404154658.565020-11-peter.maydell@linaro.org
12
---
13
include/hw/arm/exynos4210.h | 11 -----
14
hw/arm/exynos4210.c | 82 +++++++++++++++++++++++++++++++++++
15
hw/intc/exynos4210_combiner.c | 77 --------------------------------
16
3 files changed, 82 insertions(+), 88 deletions(-)
4
17
5
Most of the register reset values set by other CPU models are not
18
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
6
relevant for the cut-down ARMv6-M architecture.
7
8
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20180814162739.11814-3-stefanha@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.c | 11 +++++++++++
15
1 file changed, 11 insertions(+)
16
17
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
18
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.c
20
--- a/include/hw/arm/exynos4210.h
20
+++ b/target/arm/cpu.c
21
+++ b/include/hw/arm/exynos4210.h
21
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
22
@@ -XXX,XX +XXX,XX @@
22
cpu->reset_auxcr = 1;
23
#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \
24
(EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
25
26
-#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit))
27
-#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8)
28
-#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
29
- ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
30
-
31
/* IRQs number for external and internal GIC */
32
#define EXYNOS4210_EXT_GIC_NIRQ (160-32)
33
#define EXYNOS4210_INT_GIC_NIRQ 64
34
@@ -XXX,XX +XXX,XX @@ void exynos4210_write_secondary(ARMCPU *cpu,
35
* bit - bit number inside group */
36
uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
37
38
-/*
39
- * Get Combiner input GPIO into irqs structure
40
- */
41
-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
42
- int ext);
43
-
44
/*
45
* exynos4210 UART
46
*/
47
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/arm/exynos4210.c
50
+++ b/hw/arm/exynos4210.c
51
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
52
{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }
53
};
54
55
+#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit))
56
+#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8)
57
+#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
58
+ ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
59
+
60
/*
61
* Initialize board IRQs.
62
* These IRQs contain splitted Int/External Combiner and External Gic IRQs.
63
@@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
64
return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
23
}
65
}
24
66
25
+static void cortex_m0_initfn(Object *obj)
67
+/*
68
+ * Get Combiner input GPIO into irqs structure
69
+ */
70
+static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
71
+ DeviceState *dev, int ext)
26
+{
72
+{
27
+ ARMCPU *cpu = ARM_CPU(obj);
73
+ int n;
28
+ set_feature(&cpu->env, ARM_FEATURE_V6);
74
+ int bit;
29
+ set_feature(&cpu->env, ARM_FEATURE_M);
75
+ int max;
30
+
76
+ qemu_irq *irq;
31
+ cpu->midr = 0x410cc200;
77
+
78
+ max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
79
+ EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
80
+ irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
81
+
82
+ /*
83
+ * Some IRQs of Int/External Combiner are going to two Combiners groups,
84
+ * so let split them.
85
+ */
86
+ for (n = 0; n < max; n++) {
87
+
88
+ bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
89
+
90
+ switch (n) {
91
+ /* MDNIE_LCD1 INTG1 */
92
+ case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
93
+ EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
94
+ irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
95
+ irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
96
+ continue;
97
+
98
+ /* TMU INTG3 */
99
+ case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
100
+ irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
101
+ irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
102
+ continue;
103
+
104
+ /* LCD1 INTG12 */
105
+ case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
106
+ EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
107
+ irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
108
+ irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
109
+ continue;
110
+
111
+ /* Multi-Core Timer INTG12 */
112
+ case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
113
+ EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
114
+ irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
115
+ irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
116
+ continue;
117
+
118
+ /* Multi-Core Timer INTG35 */
119
+ case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
120
+ EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
121
+ irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
122
+ irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
123
+ continue;
124
+
125
+ /* Multi-Core Timer INTG51 */
126
+ case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
127
+ EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
128
+ irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
129
+ irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
130
+ continue;
131
+
132
+ /* Multi-Core Timer INTG53 */
133
+ case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
134
+ EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
135
+ irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
136
+ irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
137
+ continue;
138
+ }
139
+
140
+ irq[n] = qdev_get_gpio_in(dev, n);
141
+ }
32
+}
142
+}
33
+
143
+
34
static void cortex_m3_initfn(Object *obj)
144
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
145
0x09, 0x00, 0x00, 0x00 };
146
147
diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
148
index XXXXXXX..XXXXXXX 100644
149
--- a/hw/intc/exynos4210_combiner.c
150
+++ b/hw/intc/exynos4210_combiner.c
151
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_exynos4210_combiner = {
152
}
153
};
154
155
-/*
156
- * Get Combiner input GPIO into irqs structure
157
- */
158
-void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
159
- int ext)
160
-{
161
- int n;
162
- int bit;
163
- int max;
164
- qemu_irq *irq;
165
-
166
- max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
167
- EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
168
- irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
169
-
170
- /*
171
- * Some IRQs of Int/External Combiner are going to two Combiners groups,
172
- * so let split them.
173
- */
174
- for (n = 0; n < max; n++) {
175
-
176
- bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
177
-
178
- switch (n) {
179
- /* MDNIE_LCD1 INTG1 */
180
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
181
- EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
182
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
183
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
184
- continue;
185
-
186
- /* TMU INTG3 */
187
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
188
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
189
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
190
- continue;
191
-
192
- /* LCD1 INTG12 */
193
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
194
- EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
195
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
196
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
197
- continue;
198
-
199
- /* Multi-Core Timer INTG12 */
200
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
201
- EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
202
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
203
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
204
- continue;
205
-
206
- /* Multi-Core Timer INTG35 */
207
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
208
- EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
209
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
210
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
211
- continue;
212
-
213
- /* Multi-Core Timer INTG51 */
214
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
215
- EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
216
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
217
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
218
- continue;
219
-
220
- /* Multi-Core Timer INTG53 */
221
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
222
- EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
223
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
224
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
225
- continue;
226
- }
227
-
228
- irq[n] = qdev_get_gpio_in(dev, n);
229
- }
230
-}
231
-
232
static uint64_t
233
exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size)
35
{
234
{
36
ARMCPU *cpu = ARM_CPU(obj);
37
@@ -XXX,XX +XXX,XX @@ static const ARMCPUInfo arm_cpus[] = {
38
{ .name = "arm1136", .initfn = arm1136_initfn },
39
{ .name = "arm1176", .initfn = arm1176_initfn },
40
{ .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
41
+ { .name = "cortex-m0", .initfn = cortex_m0_initfn,
42
+ .class_init = arm_v7m_class_init },
43
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
44
.class_init = arm_v7m_class_init },
45
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
46
--
235
--
47
2.18.0
236
2.25.1
48
49
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
Delete a couple of #defines which are never used.
2
2
3
The SDRAM training routine sets the 'Enable cache initial' bit, and then
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
waits for the 'cache initial sequence' to be done.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20220404154658.565020-12-peter.maydell@linaro.org
6
---
7
include/hw/arm/exynos4210.h | 4 ----
8
1 file changed, 4 deletions(-)
5
9
6
Have it always return done, as there is no other side effects that the
10
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
7
model needs to implement. This allows the upstream u-boot training to
8
proceed on the ast2500-evb board.
9
10
Signed-off-by: Joel Stanley <joel@jms.id.au>
11
Reviewed-by: Cédric Le Goater <clg@kaod.org>
12
Tested-by: Cédric Le Goater <clg@kaod.org>
13
Message-id: 20180807075757.7242-4-joel@jms.id.au
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/misc/aspeed_sdmc.c | 1 +
17
1 file changed, 1 insertion(+)
18
19
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
20
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/misc/aspeed_sdmc.c
12
--- a/include/hw/arm/exynos4210.h
22
+++ b/hw/misc/aspeed_sdmc.c
13
+++ b/include/hw/arm/exynos4210.h
23
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
14
@@ -XXX,XX +XXX,XX @@
24
s->ram_bits = ast2500_rambits(s);
15
#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \
25
s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
16
(EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
26
ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
17
27
+ ASPEED_SDMC_CACHE_INITIAL_DONE |
18
-/* IRQs number for external and internal GIC */
28
ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
19
-#define EXYNOS4210_EXT_GIC_NIRQ (160-32)
29
break;
20
-#define EXYNOS4210_INT_GIC_NIRQ 64
30
default:
21
-
22
#define EXYNOS4210_I2C_NUMBER 9
23
24
#define EXYNOS4210_NUM_DMA 3
31
--
25
--
32
2.18.0
26
2.25.1
33
34
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device
2
instead of qemu_irq_split().
2
3
3
This allows the default (and maximum) vector length to be set
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
from the command-line. Which is extraordinarily helpful in
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
debugging problems depending on vector length without having to
6
Message-id: 20220404154658.565020-13-peter.maydell@linaro.org
6
bake knowledge of PR_SET_SVE_VL into every guest binary.
7
---
8
include/hw/arm/exynos4210.h | 9 ++++++++
9
hw/arm/exynos4210.c | 41 +++++++++++++++++++++++++++++--------
10
2 files changed, 42 insertions(+), 8 deletions(-)
7
11
8
Cc: qemu-stable@nongnu.org (3.0.1)
12
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
11
Tested-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.h | 3 +++
15
linux-user/syscall.c | 19 +++++++++++++------
16
target/arm/cpu.c | 6 +++---
17
target/arm/cpu64.c | 29 +++++++++++++++++++++++++++++
18
target/arm/helper.c | 7 +++++--
19
5 files changed, 53 insertions(+), 11 deletions(-)
20
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
14
--- a/include/hw/arm/exynos4210.h
24
+++ b/target/arm/cpu.h
15
+++ b/include/hw/arm/exynos4210.h
25
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
16
@@ -XXX,XX +XXX,XX @@
26
17
#include "hw/sysbus.h"
27
/* Used to synchronize KVM and QEMU in-kernel device levels */
18
#include "hw/cpu/a9mpcore.h"
28
uint8_t device_irq_level;
19
#include "hw/intc/exynos4210_gic.h"
20
+#include "hw/core/split-irq.h"
21
#include "target/arm/cpu-qom.h"
22
#include "qom/object.h"
23
24
@@ -XXX,XX +XXX,XX @@
25
26
#define EXYNOS4210_NUM_DMA 3
27
28
+/*
29
+ * We need one splitter for every external combiner input, plus
30
+ * one for every non-zero entry in combiner_grp_to_gic_id[].
31
+ * We'll assert in exynos4210_init_board_irqs() if this is wrong.
32
+ */
33
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
29
+
34
+
30
+ /* Used to set the maximum vector length the cpu will support. */
35
typedef struct Exynos4210Irq {
31
+ uint32_t sve_max_vq;
36
qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
37
qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
38
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
39
qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
40
A9MPPrivState a9mpcore;
41
Exynos4210GicState ext_gic;
42
+ SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
32
};
43
};
33
44
34
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
45
#define TYPE_EXYNOS4210_SOC "exynos4210"
35
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
46
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
36
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
37
--- a/linux-user/syscall.c
48
--- a/hw/arm/exynos4210.c
38
+++ b/linux-user/syscall.c
49
+++ b/hw/arm/exynos4210.c
39
@@ -XXX,XX +XXX,XX @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
50
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
40
#endif
51
uint32_t grp, bit, irq_id, n;
41
#ifdef TARGET_AARCH64
52
Exynos4210Irq *is = &s->irqs;
42
case TARGET_PR_SVE_SET_VL:
53
DeviceState *extgicdev = DEVICE(&s->ext_gic);
43
- /* We cannot support either PR_SVE_SET_VL_ONEXEC
54
+ int splitcount = 0;
44
- or PR_SVE_VL_INHERIT. Therefore, anything above
55
+ DeviceState *splitter;
45
- ARM_MAX_VQ results in EINVAL. */
56
46
+ /*
57
for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
47
+ * We cannot support either PR_SVE_SET_VL_ONEXEC or
58
irq_id = 0;
48
+ * PR_SVE_VL_INHERIT. Note the kernel definition
59
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
49
+ * of sve_vl_valid allows for VQ=512, i.e. VL=8192,
60
/* MCT_G1 is passed to External and GIC */
50
+ * even though the current architectural maximum is VQ=16.
61
irq_id = EXT_GIC_ID_MCT_G1;
51
+ */
62
}
52
ret = -TARGET_EINVAL;
53
if (arm_feature(cpu_env, ARM_FEATURE_SVE)
54
- && arg2 >= 0 && arg2 <= ARM_MAX_VQ * 16 && !(arg2 & 15)) {
55
+ && arg2 >= 0 && arg2 <= 512 * 16 && !(arg2 & 15)) {
56
CPUARMState *env = cpu_env;
57
- int old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
58
- int vq = MAX(arg2 / 16, 1);
59
+ ARMCPU *cpu = arm_env_get_cpu(env);
60
+ uint32_t vq, old_vq;
61
+
63
+
62
+ old_vq = (env->vfp.zcr_el[1] & 0xf) + 1;
64
+ assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
63
+ vq = MAX(arg2 / 16, 1);
65
+ splitter = DEVICE(&s->splitter[splitcount]);
64
+ vq = MIN(vq, cpu->sve_max_vq);
66
+ qdev_prop_set_uint16(splitter, "num-lines", 2);
65
67
+ qdev_realize(splitter, NULL, &error_abort);
66
if (vq < old_vq) {
68
+ splitcount++;
67
aarch64_sve_narrow_vq(env, vq);
69
+ s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
68
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
70
+ qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
69
index XXXXXXX..XXXXXXX 100644
71
if (irq_id) {
70
--- a/target/arm/cpu.c
72
- s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
71
+++ b/target/arm/cpu.c
73
- qdev_get_gpio_in(extgicdev,
72
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
74
- irq_id - 32));
73
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
75
+ qdev_connect_gpio_out(splitter, 1,
74
env->cp15.cptr_el[3] |= CPTR_EZ;
76
+ qdev_get_gpio_in(extgicdev, irq_id - 32));
75
/* with maximum vector length */
77
} else {
76
- env->vfp.zcr_el[1] = ARM_MAX_VQ - 1;
78
- s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
77
- env->vfp.zcr_el[2] = ARM_MAX_VQ - 1;
79
- is->ext_combiner_irq[n]);
78
- env->vfp.zcr_el[3] = ARM_MAX_VQ - 1;
80
+ qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
79
+ env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
81
}
80
+ env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
82
}
81
+ env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
83
for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
82
#else
84
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
83
/* Reset into the highest available EL */
85
EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
84
if (arm_feature(env, ARM_FEATURE_EL3)) {
86
85
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
87
if (irq_id) {
86
index XXXXXXX..XXXXXXX 100644
88
- s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
87
--- a/target/arm/cpu64.c
89
- qdev_get_gpio_in(extgicdev,
88
+++ b/target/arm/cpu64.c
90
- irq_id - 32));
89
@@ -XXX,XX +XXX,XX @@
91
+ assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
90
#include "sysemu/sysemu.h"
92
+ splitter = DEVICE(&s->splitter[splitcount]);
91
#include "sysemu/kvm.h"
93
+ qdev_prop_set_uint16(splitter, "num-lines", 2);
92
#include "kvm_arm.h"
94
+ qdev_realize(splitter, NULL, &error_abort);
93
+#include "qapi/visitor.h"
95
+ splitcount++;
94
96
+ s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
95
static inline void set_feature(CPUARMState *env, int feature)
97
+ qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
96
{
98
+ qdev_connect_gpio_out(splitter, 1,
97
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
99
+ qdev_get_gpio_in(extgicdev, irq_id - 32));
98
define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
100
}
101
}
102
+ /*
103
+ * We check this here to avoid a more obscure assert later when
104
+ * qdev_assert_realized_properly() checks that we realized every
105
+ * child object we initialized.
106
+ */
107
+ assert(splitcount == EXYNOS4210_NUM_SPLITTERS);
99
}
108
}
100
109
101
+static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
110
/*
102
+ void *opaque, Error **errp)
111
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
103
+{
112
object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_IRQ);
104
+ ARMCPU *cpu = ARM_CPU(obj);
113
}
105
+ visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
114
106
+}
115
+ for (i = 0; i < ARRAY_SIZE(s->splitter); i++) {
116
+ g_autofree char *name = g_strdup_printf("irq-splitter%d", i);
117
+ object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ);
118
+ }
107
+
119
+
108
+static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
120
object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
109
+ void *opaque, Error **errp)
121
object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
110
+{
111
+ ARMCPU *cpu = ARM_CPU(obj);
112
+ Error *err = NULL;
113
+
114
+ visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
115
+
116
+ if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
117
+ error_setg(&err, "unsupported SVE vector length");
118
+ error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
119
+ ARM_MAX_VQ);
120
+ }
121
+ error_propagate(errp, err);
122
+}
123
+
124
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
125
* otherwise, a CPU with as many features enabled as our emulation supports.
126
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
127
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
128
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
129
cpu->dcz_blocksize = 7; /* 512 bytes */
130
#endif
131
+
132
+ cpu->sve_max_vq = ARM_MAX_VQ;
133
+ object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
134
+ cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
135
}
136
}
122
}
137
138
@@ -XXX,XX +XXX,XX @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
139
uint64_t pmask;
140
141
assert(vq >= 1 && vq <= ARM_MAX_VQ);
142
+ assert(vq <= arm_env_get_cpu(env)->sve_max_vq);
143
144
/* Zap the high bits of the zregs. */
145
for (i = 0; i < 32; i++) {
146
diff --git a/target/arm/helper.c b/target/arm/helper.c
147
index XXXXXXX..XXXXXXX 100644
148
--- a/target/arm/helper.c
149
+++ b/target/arm/helper.c
150
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
151
zcr_len = 0;
152
} else {
153
int current_el = arm_current_el(env);
154
+ ARMCPU *cpu = arm_env_get_cpu(env);
155
156
- zcr_len = env->vfp.zcr_el[current_el <= 1 ? 1 : current_el];
157
- zcr_len &= 0xf;
158
+ zcr_len = cpu->sve_max_vq - 1;
159
+ if (current_el <= 1) {
160
+ zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]);
161
+ }
162
if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
163
zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]);
164
}
165
--
123
--
166
2.18.0
124
2.25.1
167
168
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In exynos4210_init_board_irqs(), the loop that handles IRQ lines that
2
are in a range that applies to the internal combiner only creates a
3
splitter for those interrupts which go to both the internal combiner
4
and to the external GIC, but it does nothing at all for the
5
interrupts which don't go to the external GIC, leaving the
6
irq_table[] array element empty for those. (This will result in
7
those interrupts simply being lost, not in a QEMU crash.)
2
8
3
The scaling should be solely on the memory operation size; the number
9
I don't have a reliable datasheet for this SoC, but since we do wire
4
of registers being loaded does not come in to the initial computation.
10
up one interrupt line in this category (the HDMI I2C device on
11
interrupt 16,1), this seems like it must be a bug in the existing
12
QEMU code. Fill in the irq_table[] entries where we're not splitting
13
the IRQ to both the internal combiner and the external GIC with the
14
IRQ line of the internal combiner. (That is, these IRQ lines go to
15
just one device, not multiple.)
5
16
6
Cc: qemu-stable@nongnu.org (3.0.1)
17
This bug didn't have any visible guest effects because the only
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
18
implemented device that was affected was the HDMI I2C controller,
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
19
and we never connect any I2C devices to that bus.
9
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
20
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Message-id: 20220404154658.565020-14-peter.maydell@linaro.org
12
---
24
---
13
target/arm/translate-sve.c | 5 ++---
25
hw/arm/exynos4210.c | 2 ++
14
1 file changed, 2 insertions(+), 3 deletions(-)
26
1 file changed, 2 insertions(+)
15
27
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
28
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
17
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-sve.c
30
--- a/hw/arm/exynos4210.c
19
+++ b/target/arm/translate-sve.c
31
+++ b/hw/arm/exynos4210.c
20
@@ -XXX,XX +XXX,XX @@ static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn)
32
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
33
qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
34
qdev_connect_gpio_out(splitter, 1,
35
qdev_get_gpio_in(extgicdev, irq_id - 32));
36
+ } else {
37
+ s->irq_table[n] = is->int_combiner_irq[n];
38
}
21
}
39
}
22
if (sve_access_check(s)) {
40
/*
23
TCGv_i64 addr = new_tmp_a64(s);
24
- tcg_gen_muli_i64(addr, cpu_reg(s, a->rm),
25
- (a->nreg + 1) << dtype_msz(a->dtype));
26
+ tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
27
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
28
do_ld_zpa(s, a->rd, a->pg, addr, a->dtype, a->nreg);
29
}
30
@@ -XXX,XX +XXX,XX @@ static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t insn)
31
}
32
if (sve_access_check(s)) {
33
TCGv_i64 addr = new_tmp_a64(s);
34
- tcg_gen_muli_i64(addr, cpu_reg(s, a->rm), (a->nreg + 1) << a->msz);
35
+ tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->msz);
36
tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn));
37
do_st_zpa(s, a->rd, a->pg, addr, a->msz, a->esz, a->nreg);
38
}
39
--
41
--
40
2.18.0
42
2.25.1
41
42
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Currently for the interrupts MCT_G0 and MCT_G1 which are
2
the only ones in the input range of the external combiner
3
and which are also wired to the external GIC, we connect
4
them only to the internal combiner and the external GIC.
5
This seems likely to be a bug, as all other interrupts
6
which are in the input range of both combiners are
7
connected to both combiners. (The fact that the code in
8
exynos4210_combiner_get_gpioin() is also trying to wire
9
up these inputs on both combiners also suggests this.)
2
10
3
With PC, there are 33 registers. Three per line lines up nicely
11
Wire these interrupts up to both combiners, like the rest.
4
without overflowing 80 columns.
5
12
6
Cc: qemu-stable@nongnu.org (3.0.1)
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220404154658.565020-15-peter.maydell@linaro.org
10
---
16
---
11
target/arm/translate-a64.c | 13 ++++++-------
17
hw/arm/exynos4210.c | 7 +++----
12
1 file changed, 6 insertions(+), 7 deletions(-)
18
1 file changed, 3 insertions(+), 4 deletions(-)
13
19
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
20
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
15
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
22
--- a/hw/arm/exynos4210.c
17
+++ b/target/arm/translate-a64.c
23
+++ b/hw/arm/exynos4210.c
18
@@ -XXX,XX +XXX,XX @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
24
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
19
int el = arm_current_el(env);
25
20
const char *ns_status;
26
assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
21
27
splitter = DEVICE(&s->splitter[splitcount]);
22
- cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
28
- qdev_prop_set_uint16(splitter, "num-lines", 2);
23
- env->pc, env->xregs[31]);
29
+ qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2);
24
- for (i = 0; i < 31; i++) {
30
qdev_realize(splitter, NULL, &error_abort);
25
- cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
31
splitcount++;
26
- if ((i % 4) == 3) {
32
s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
27
- cpu_fprintf(f, "\n");
33
qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
28
+ cpu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
34
+ qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
29
+ for (i = 0; i < 32; i++) {
35
if (irq_id) {
30
+ if (i == 31) {
36
- qdev_connect_gpio_out(splitter, 1,
31
+ cpu_fprintf(f, " SP=%016" PRIx64 "\n", env->xregs[i]);
37
+ qdev_connect_gpio_out(splitter, 2,
32
} else {
38
qdev_get_gpio_in(extgicdev, irq_id - 32));
33
- cpu_fprintf(f, " ");
39
- } else {
34
+ cpu_fprintf(f, "X%02d=%016" PRIx64 "%s", i, env->xregs[i],
40
- qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
35
+ (i + 2) % 3 ? " " : "\n");
36
}
41
}
37
}
42
}
38
43
for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
39
--
44
--
40
2.18.0
45
2.25.1
41
42
diff view generated by jsdifflib
1
From: Joel Stanley <joel@jms.id.au>
1
The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0
2
and EXT_GIC_ID_MCT_G1 multiple times. This means that we will
3
connect multiple IRQs up to the same external GIC input, which
4
is not permitted. We do the same thing in the code in
5
exynos4210_init_board_irqs() because the conditionals selecting
6
an irq_id in the first loop match multiple interrupt IDs.
2
7
3
This is required to ensure u-boot SDRAM training completes.
8
Overall we do this for interrupt IDs
9
(1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0
10
and
11
(1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1
4
12
5
Signed-off-by: Joel Stanley <joel@jms.id.au>
13
These correspond to the cases for the multi-core timer that we are
6
Reviewed-by: Cédric Le Goater <clg@kaod.org>
14
wiring up to multiple inputs on the combiner in
7
Tested-by: Cédric Le Goater <clg@kaod.org>
15
exynos4210_combiner_get_gpioin(). That code already deals with all
8
Message-id: 20180807075757.7242-6-joel@jms.id.au
16
these interrupt IDs being the same input source, so we don't need to
17
connect the external GIC interrupt for any of them except the first
18
(1, 4) and (1, 5). Remove the array entries and conditionals which
19
were incorrectly causing us to wire up extra lines.
20
21
This bug didn't cause any visible effects, because we only connect
22
up a device to the "primary" ID values (1, 4) and (1, 5), so the
23
extra lines would never be set to a level.
24
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Message-id: 20220404154658.565020-16-peter.maydell@linaro.org
10
---
28
---
11
hw/misc/aspeed_sdmc.c | 9 +++++++++
29
include/hw/arm/exynos4210.h | 2 +-
12
1 file changed, 9 insertions(+)
30
hw/arm/exynos4210.c | 12 +++++-------
31
2 files changed, 6 insertions(+), 8 deletions(-)
13
32
14
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
33
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
15
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/misc/aspeed_sdmc.c
35
--- a/include/hw/arm/exynos4210.h
17
+++ b/hw/misc/aspeed_sdmc.c
36
+++ b/include/hw/arm/exynos4210.h
18
@@ -XXX,XX +XXX,XX @@
37
@@ -XXX,XX +XXX,XX @@
19
#define R_STATUS1 (0x60 / 4)
38
* one for every non-zero entry in combiner_grp_to_gic_id[].
20
#define PHY_BUSY_STATE BIT(0)
39
* We'll assert in exynos4210_init_board_irqs() if this is wrong.
21
40
*/
22
+#define R_ECC_TEST_CTRL (0x70 / 4)
41
-#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60)
23
+#define ECC_TEST_FINISHED BIT(12)
42
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
24
+#define ECC_TEST_FAIL BIT(13)
43
25
+
44
typedef struct Exynos4210Irq {
26
/*
45
qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
27
* Configuration register Ox4 (for Aspeed AST2400 SOC)
46
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
28
*
47
index XXXXXXX..XXXXXXX 100644
29
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
48
--- a/hw/arm/exynos4210.c
30
/* Will never return 'busy' */
49
+++ b/hw/arm/exynos4210.c
31
data &= ~PHY_BUSY_STATE;
50
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
32
break;
51
/* int combiner group 34 */
33
+ case R_ECC_TEST_CTRL:
52
{ EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
34
+ /* Always done, always happy */
53
/* int combiner group 35 */
35
+ data |= ECC_TEST_FINISHED;
54
- { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
36
+ data &= ~ECC_TEST_FAIL;
55
+ { 0, 0, 0, EXT_GIC_ID_MCT_L1 },
37
+ break;
56
/* int combiner group 36 */
38
default:
57
{ EXT_GIC_ID_MIXER },
39
break;
58
/* int combiner group 37 */
59
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
60
/* groups 38-50 */
61
{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
62
/* int combiner group 51 */
63
- { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
64
+ { EXT_GIC_ID_MCT_L0 },
65
/* group 52 */
66
{ },
67
/* int combiner group 53 */
68
- { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
69
+ { EXT_GIC_ID_WDT },
70
/* groups 54-63 */
71
{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }
72
};
73
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
74
75
for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
76
irq_id = 0;
77
- if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
78
- n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
79
+ if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) {
80
/* MCT_G0 is passed to External GIC */
81
irq_id = EXT_GIC_ID_MCT_G0;
82
}
83
- if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
84
- n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
85
+ if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) {
86
/* MCT_G1 is passed to External and GIC */
87
irq_id = EXT_GIC_ID_MCT_G1;
40
}
88
}
41
--
89
--
42
2.18.0
90
2.25.1
43
44
diff view generated by jsdifflib
1
From: Cédric Le Goater <clg@kaod.org>
1
At this point, the function exynos4210_init_board_irqs() splits input
2
2
IRQ lines to connect them to the input combiner, output combiner and
3
This will be used to construct a memory region beyond the RAM region
3
external GIC. The function exynos4210_combiner_get_gpioin() splits
4
to let firmwares scan the address space with load/store to guess how
4
some of the combiner input lines further to connect them to multiple
5
much RAM the SoC has.
5
different inputs on the combiner.
6
6
7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7
Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a
8
Signed-off-by: Joel Stanley <joel@jms.id.au>
8
configurable number of outputs, we can do all this in one place, by
9
Tested-by: Cédric Le Goater <clg@kaod.org>
9
making exynos4210_init_board_irqs() add extra outputs to the splitter
10
Message-id: 20180807075757.7242-7-joel@jms.id.au
10
device when it must be connected to more than one input on each
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
combiner.
12
13
We do this with a new data structure, the combinermap, which is an
14
array each of whose elements is a list of the interrupt IDs on the
15
combiner which must be tied together. As we loop through each
16
interrupt ID, if we find that it is the first one in one of these
17
lists, we configure the splitter device with eonugh extra outputs and
18
wire them up to the other interrupt IDs in the list.
19
20
Conveniently, for all the cases where this is necessary, the
21
lowest-numbered interrupt ID in each group is in the range of the
22
external combiner, so we only need to code for this in the first of
23
the two loops in exynos4210_init_board_irqs().
24
25
The old code in exynos4210_combiner_get_gpioin() which is being
26
deleted here had several problems which don't exist in the new code
27
in its handling of the multi-core timer interrupts:
28
(1) the case labels specified bits 4 ... 8, but bit '8' doesn't
29
exist; these should have been 4 ... 7
30
(2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]
31
multiple times as the input of several different splitters,
32
which isn't allowed
33
(3) in an apparent cut-and-paste error, the cases for all the
34
multi-core timer inputs used "bit + 4" even though the
35
bit range for the case was (intended to be) 4 ... 7, which
36
meant it was looking at non-existent bits 8 ... 11.
37
None of these exist in the new code.
38
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
39
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
40
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
41
Message-id: 20220404154658.565020-17-peter.maydell@linaro.org
13
---
42
---
14
include/hw/misc/aspeed_sdmc.h | 1 +
43
include/hw/arm/exynos4210.h | 6 +-
15
hw/arm/aspeed.c | 31 +++++++++++++++++++++++++++++++
44
hw/arm/exynos4210.c | 178 +++++++++++++++++++++++-------------
16
hw/arm/aspeed_soc.c | 2 ++
45
2 files changed, 119 insertions(+), 65 deletions(-)
17
hw/misc/aspeed_sdmc.c | 3 +++
46
18
4 files changed, 37 insertions(+)
47
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
19
20
diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
21
index XXXXXXX..XXXXXXX 100644
48
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/misc/aspeed_sdmc.h
49
--- a/include/hw/arm/exynos4210.h
23
+++ b/include/hw/misc/aspeed_sdmc.h
50
+++ b/include/hw/arm/exynos4210.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedSDMCState {
51
@@ -XXX,XX +XXX,XX @@
25
uint32_t silicon_rev;
52
26
uint32_t ram_bits;
53
/*
27
uint64_t ram_size;
54
* We need one splitter for every external combiner input, plus
28
+ uint64_t max_ram_size;
55
- * one for every non-zero entry in combiner_grp_to_gic_id[].
29
uint32_t fixed_conf;
56
+ * one for every non-zero entry in combiner_grp_to_gic_id[],
30
57
+ * minus one for every external combiner ID in second or later
31
} AspeedSDMCState;
58
+ * places in a combinermap[] line.
32
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
59
* We'll assert in exynos4210_init_board_irqs() if this is wrong.
60
*/
61
-#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
62
+#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
63
64
typedef struct Exynos4210Irq {
65
qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
66
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
33
index XXXXXXX..XXXXXXX 100644
67
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/aspeed.c
68
--- a/hw/arm/exynos4210.c
35
+++ b/hw/arm/aspeed.c
69
+++ b/hw/arm/exynos4210.c
36
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info aspeed_board_binfo = {
70
@@ -XXX,XX +XXX,XX @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
37
typedef struct AspeedBoardState {
71
#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
38
AspeedSoCState soc;
72
((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
39
MemoryRegion ram;
40
+ MemoryRegion max_ram;
41
} AspeedBoardState;
42
43
typedef struct AspeedBoardConfig {
44
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
45
},
46
};
47
73
48
+/*
74
+/*
49
+ * The max ram region is for firmwares that scan the address space
75
+ * Some interrupt lines go to multiple combiner inputs.
50
+ * with load/store to guess how much RAM the SoC has.
76
+ * This data structure defines those: each array element is
77
+ * a list of combiner inputs which are connected together;
78
+ * the one with the smallest interrupt ID value must be first.
79
+ * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being
80
+ * wired to anything so we can use 0 as a terminator.
51
+ */
81
+ */
52
+static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
82
+#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B)
83
+#define IRQNONE 0
84
+
85
+#define COMBINERMAP_SIZE 16
86
+
87
+static const int combinermap[COMBINERMAP_SIZE][6] = {
88
+ /* MDNIE_LCD1 */
89
+ { IRQNO(0, 4), IRQNO(1, 0), IRQNONE },
90
+ { IRQNO(0, 5), IRQNO(1, 1), IRQNONE },
91
+ { IRQNO(0, 6), IRQNO(1, 2), IRQNONE },
92
+ { IRQNO(0, 7), IRQNO(1, 3), IRQNONE },
93
+ /* TMU */
94
+ { IRQNO(2, 4), IRQNO(3, 4), IRQNONE },
95
+ { IRQNO(2, 5), IRQNO(3, 5), IRQNONE },
96
+ { IRQNO(2, 6), IRQNO(3, 6), IRQNONE },
97
+ { IRQNO(2, 7), IRQNO(3, 7), IRQNONE },
98
+ /* LCD1 */
99
+ { IRQNO(11, 4), IRQNO(12, 0), IRQNONE },
100
+ { IRQNO(11, 5), IRQNO(12, 1), IRQNONE },
101
+ { IRQNO(11, 6), IRQNO(12, 2), IRQNONE },
102
+ { IRQNO(11, 7), IRQNO(12, 3), IRQNONE },
103
+ /* Multi-core timer */
104
+ { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4), IRQNONE },
105
+ { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5), IRQNONE },
106
+ { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6), IRQNONE },
107
+ { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7), IRQNONE },
108
+};
109
+
110
+#undef IRQNO
111
+
112
+static const int *combinermap_entry(int irq)
53
+{
113
+{
54
+ return 0;
114
+ /*
115
+ * If the interrupt number passed in is the first entry in some
116
+ * line of the combinermap, return a pointer to that line;
117
+ * otherwise return NULL.
118
+ */
119
+ int i;
120
+ for (i = 0; i < COMBINERMAP_SIZE; i++) {
121
+ if (combinermap[i][0] == irq) {
122
+ return combinermap[i];
123
+ }
124
+ }
125
+ return NULL;
55
+}
126
+}
56
+
127
+
57
+static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
128
+static int mapline_size(const int *mapline)
58
+ unsigned size)
59
+{
129
+{
60
+ /* Discard writes */
130
+ /* Return number of entries in this mapline in total */
131
+ int i = 0;
132
+
133
+ if (!mapline) {
134
+ /* Not in the map? IRQ goes to exactly one combiner input */
135
+ return 1;
136
+ }
137
+ while (*mapline != IRQNONE) {
138
+ mapline++;
139
+ i++;
140
+ }
141
+ return i;
61
+}
142
+}
62
+
143
+
63
+static const MemoryRegionOps max_ram_ops = {
144
/*
64
+ .read = max_ram_read,
145
* Initialize board IRQs.
65
+ .write = max_ram_write,
146
* These IRQs contain splitted Int/External Combiner and External Gic IRQs.
66
+ .endianness = DEVICE_NATIVE_ENDIAN,
147
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
67
+};
148
DeviceState *extgicdev = DEVICE(&s->ext_gic);
68
+
149
int splitcount = 0;
69
#define FIRMWARE_ADDR 0x0
150
DeviceState *splitter;
70
151
+ const int *mapline;
71
static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
152
+ int numlines, splitin, in;
72
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
153
73
AspeedBoardState *bmc;
154
for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
74
AspeedSoCClass *sc;
155
irq_id = 0;
75
DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
156
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
76
+ ram_addr_t max_ram_size;
157
irq_id = EXT_GIC_ID_MCT_G1;
77
158
}
78
bmc = g_new0(AspeedBoardState, 1);
159
79
object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);
160
+ if (s->irq_table[n]) {
80
@@ -XXX,XX +XXX,XX @@ static void aspeed_board_init(MachineState *machine,
161
+ /*
81
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
162
+ * This must be some non-first entry in a combinermap line,
82
&error_abort);
163
+ * and we've already filled it in.
83
164
+ */
84
+ max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
165
+ continue;
85
+ &error_abort);
166
+ }
86
+ memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
167
+ mapline = combinermap_entry(n);
87
+ "max_ram", max_ram_size - ram_size);
168
+ /*
88
+ memory_region_add_subregion(get_system_memory(),
169
+ * We need to connect the IRQ to multiple inputs on both combiners
89
+ sc->info->sdram_base + ram_size,
170
+ * and possibly also to the external GIC.
90
+ &bmc->max_ram);
171
+ */
91
+
172
+ numlines = 2 * mapline_size(mapline);
92
aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
173
+ if (irq_id) {
93
aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
174
+ numlines++;
94
175
+ }
95
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
176
assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
96
index XXXXXXX..XXXXXXX 100644
177
splitter = DEVICE(&s->splitter[splitcount]);
97
--- a/hw/arm/aspeed_soc.c
178
- qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2);
98
+++ b/hw/arm/aspeed_soc.c
179
+ qdev_prop_set_uint16(splitter, "num-lines", numlines);
99
@@ -XXX,XX +XXX,XX @@ static void aspeed_soc_init(Object *obj)
180
qdev_realize(splitter, NULL, &error_abort);
100
sc->info->silicon_rev);
181
splitcount++;
101
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
182
- s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
102
"ram-size", &error_abort);
183
- qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
103
+ object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
184
- qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]);
104
+ "max-ram-size", &error_abort);
185
+
105
186
+ in = n;
106
for (i = 0; i < sc->info->wdts_num; i++) {
187
+ splitin = 0;
107
object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
188
+ for (;;) {
108
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
189
+ s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
109
index XXXXXXX..XXXXXXX 100644
190
+ qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]);
110
--- a/hw/misc/aspeed_sdmc.c
191
+ qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]);
111
+++ b/hw/misc/aspeed_sdmc.c
192
+ splitin += 2;
112
@@ -XXX,XX +XXX,XX @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
193
+ if (!mapline) {
113
case AST2400_A0_SILICON_REV:
194
+ break;
114
case AST2400_A1_SILICON_REV:
195
+ }
115
s->ram_bits = ast2400_rambits(s);
196
+ mapline++;
116
+ s->max_ram_size = 512 << 20;
197
+ in = *mapline;
117
s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
198
+ if (in == IRQNONE) {
118
ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
199
+ break;
119
break;
200
+ }
120
case AST2500_A0_SILICON_REV:
201
+ }
121
case AST2500_A1_SILICON_REV:
202
if (irq_id) {
122
s->ram_bits = ast2500_rambits(s);
203
- qdev_connect_gpio_out(splitter, 2,
123
+ s->max_ram_size = 1024 << 20;
204
+ qdev_connect_gpio_out(splitter, splitin,
124
s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
205
qdev_get_gpio_in(extgicdev, irq_id - 32));
125
ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
206
}
126
ASPEED_SDMC_CACHE_INITIAL_DONE |
207
}
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_aspeed_sdmc = {
208
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
128
static Property aspeed_sdmc_properties[] = {
209
irq_id = combiner_grp_to_gic_id[grp -
129
DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
210
EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
130
DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
211
131
+ DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
212
+ if (s->irq_table[n]) {
132
DEFINE_PROP_END_OF_LIST(),
213
+ /*
133
};
214
+ * This must be some non-first entry in a combinermap line,
134
215
+ * and we've already filled it in.
216
+ */
217
+ continue;
218
+ }
219
+
220
if (irq_id) {
221
assert(splitcount < EXYNOS4210_NUM_SPLITTERS);
222
splitter = DEVICE(&s->splitter[splitcount]);
223
@@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
224
DeviceState *dev, int ext)
225
{
226
int n;
227
- int bit;
228
int max;
229
qemu_irq *irq;
230
231
@@ -XXX,XX +XXX,XX @@ static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
232
EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
233
irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
234
235
- /*
236
- * Some IRQs of Int/External Combiner are going to two Combiners groups,
237
- * so let split them.
238
- */
239
for (n = 0; n < max; n++) {
240
-
241
- bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
242
-
243
- switch (n) {
244
- /* MDNIE_LCD1 INTG1 */
245
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ...
246
- EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3):
247
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
248
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]);
249
- continue;
250
-
251
- /* TMU INTG3 */
252
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4):
253
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
254
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]);
255
- continue;
256
-
257
- /* LCD1 INTG12 */
258
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ...
259
- EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3):
260
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
261
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]);
262
- continue;
263
-
264
- /* Multi-Core Timer INTG12 */
265
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ...
266
- EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8):
267
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
268
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
269
- continue;
270
-
271
- /* Multi-Core Timer INTG35 */
272
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ...
273
- EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8):
274
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
275
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
276
- continue;
277
-
278
- /* Multi-Core Timer INTG51 */
279
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ...
280
- EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8):
281
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
282
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
283
- continue;
284
-
285
- /* Multi-Core Timer INTG53 */
286
- case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ...
287
- EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8):
288
- irq[n] = qemu_irq_split(qdev_get_gpio_in(dev, n),
289
- irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]);
290
- continue;
291
- }
292
-
293
irq[n] = qdev_get_gpio_in(dev, n);
294
}
295
}
135
--
296
--
136
2.18.0
297
2.25.1
137
138
diff view generated by jsdifflib
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
Switch the creation of the combiner devices to the new-style
2
"embedded in state struct" approach, so we can easily refer
3
to the object elsewhere during realize.
2
4
3
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
4
Message-id: 3853ec555d68e7e25d726170833b775796151a07.1532984236.git.jcd@tribudubois.net
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20220404154658.565020-18-peter.maydell@linaro.org
7
---
8
---
8
hw/arm/Makefile.objs | 1 +
9
include/hw/arm/exynos4210.h | 3 ++
9
include/hw/arm/fsl-imx6ul.h | 339 ++++++++++++++++++
10
include/hw/intc/exynos4210_combiner.h | 57 +++++++++++++++++++++++++++
10
hw/arm/fsl-imx6ul.c | 617 ++++++++++++++++++++++++++++++++
11
hw/arm/exynos4210.c | 20 +++++-----
11
default-configs/arm-softmmu.mak | 1 +
12
hw/intc/exynos4210_combiner.c | 31 +--------------
12
4 files changed, 958 insertions(+)
13
4 files changed, 72 insertions(+), 39 deletions(-)
13
create mode 100644 include/hw/arm/fsl-imx6ul.h
14
create mode 100644 include/hw/intc/exynos4210_combiner.h
14
create mode 100644 hw/arm/fsl-imx6ul.c
15
15
16
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
16
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/Makefile.objs
18
--- a/include/hw/arm/exynos4210.h
19
+++ b/hw/arm/Makefile.objs
19
+++ b/include/hw/arm/exynos4210.h
20
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_MSF2) += msf2-soc.o msf2-som.o
20
@@ -XXX,XX +XXX,XX @@
21
obj-$(CONFIG_IOTKIT) += iotkit.o
21
#include "hw/sysbus.h"
22
obj-$(CONFIG_FSL_IMX7) += fsl-imx7.o mcimx7d-sabre.o
22
#include "hw/cpu/a9mpcore.h"
23
obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o smmuv3.o
23
#include "hw/intc/exynos4210_gic.h"
24
+obj-$(CONFIG_FSL_IMX6UL) += fsl-imx6ul.o
24
+#include "hw/intc/exynos4210_combiner.h"
25
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
25
#include "hw/core/split-irq.h"
26
#include "target/arm/cpu-qom.h"
27
#include "qom/object.h"
28
@@ -XXX,XX +XXX,XX @@ struct Exynos4210State {
29
qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
30
A9MPPrivState a9mpcore;
31
Exynos4210GicState ext_gic;
32
+ Exynos4210CombinerState int_combiner;
33
+ Exynos4210CombinerState ext_combiner;
34
SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
35
};
36
37
diff --git a/include/hw/intc/exynos4210_combiner.h b/include/hw/intc/exynos4210_combiner.h
26
new file mode 100644
38
new file mode 100644
27
index XXXXXXX..XXXXXXX
39
index XXXXXXX..XXXXXXX
28
--- /dev/null
40
--- /dev/null
29
+++ b/include/hw/arm/fsl-imx6ul.h
41
+++ b/include/hw/intc/exynos4210_combiner.h
30
@@ -XXX,XX +XXX,XX @@
42
@@ -XXX,XX +XXX,XX @@
31
+/*
43
+/*
32
+ * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
44
+ * Samsung exynos4210 Interrupt Combiner
33
+ *
45
+ *
34
+ * i.MX6ul SoC definitions
46
+ * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
47
+ * All rights reserved.
35
+ *
48
+ *
36
+ * This program is free software; you can redistribute it and/or modify
49
+ * Evgeny Voevodin <e.voevodin@samsung.com>
37
+ * it under the terms of the GNU General Public License as published by
50
+ *
38
+ * the Free Software Foundation; either version 2 of the License, or
51
+ * This program is free software; you can redistribute it and/or modify it
39
+ * (at your option) any later version.
52
+ * under the terms of the GNU General Public License as published by the
53
+ * Free Software Foundation; either version 2 of the License, or (at your
54
+ * option) any later version.
40
+ *
55
+ *
41
+ * This program is distributed in the hope that it will be useful,
56
+ * This program is distributed in the hope that it will be useful,
42
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
57
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
43
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
58
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
44
+ * GNU General Public License for more details.
59
+ * See the GNU General Public License for more details.
60
+ *
61
+ * You should have received a copy of the GNU General Public License along
62
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
45
+ */
63
+ */
46
+
64
+
47
+#ifndef FSL_IMX6UL_H
65
+#ifndef HW_INTC_EXYNOS4210_COMBINER
48
+#define FSL_IMX6UL_H
66
+#define HW_INTC_EXYNOS4210_COMBINER
49
+
67
+
50
+#include "hw/arm/arm.h"
68
+#include "hw/sysbus.h"
51
+#include "hw/cpu/a15mpcore.h"
52
+#include "hw/misc/imx6ul_ccm.h"
53
+#include "hw/misc/imx6_src.h"
54
+#include "hw/misc/imx7_snvs.h"
55
+#include "hw/misc/imx7_gpr.h"
56
+#include "hw/intc/imx_gpcv2.h"
57
+#include "hw/misc/imx2_wdt.h"
58
+#include "hw/gpio/imx_gpio.h"
59
+#include "hw/char/imx_serial.h"
60
+#include "hw/timer/imx_gpt.h"
61
+#include "hw/timer/imx_epit.h"
62
+#include "hw/i2c/imx_i2c.h"
63
+#include "hw/gpio/imx_gpio.h"
64
+#include "hw/sd/sdhci.h"
65
+#include "hw/ssi/imx_spi.h"
66
+#include "hw/net/imx_fec.h"
67
+#include "exec/memory.h"
68
+#include "cpu.h"
69
+
69
+
70
+#define TYPE_FSL_IMX6UL "fsl,imx6ul"
70
+/*
71
+#define FSL_IMX6UL(obj) OBJECT_CHECK(FslIMX6ULState, (obj), TYPE_FSL_IMX6UL)
71
+ * State for each output signal of internal combiner
72
+ */
73
+typedef struct CombinerGroupState {
74
+ uint8_t src_mask; /* 1 - source enabled, 0 - disabled */
75
+ uint8_t src_pending; /* Pending source interrupts before masking */
76
+} CombinerGroupState;
72
+
77
+
73
+enum FslIMX6ULConfiguration {
78
+#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
74
+ FSL_IMX6UL_NUM_CPUS = 1,
79
+OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
75
+ FSL_IMX6UL_NUM_UARTS = 8,
80
+
76
+ FSL_IMX6UL_NUM_ETHS = 2,
81
+/* Number of groups and total number of interrupts for the internal combiner */
77
+ FSL_IMX6UL_ETH_NUM_TX_RINGS = 2,
82
+#define IIC_NGRP 64
78
+ FSL_IMX6UL_NUM_USDHCS = 2,
83
+#define IIC_NIRQ (IIC_NGRP * 8)
79
+ FSL_IMX6UL_NUM_WDTS = 3,
84
+#define IIC_REGSET_SIZE 0x41
80
+ FSL_IMX6UL_NUM_GPTS = 2,
85
+
81
+ FSL_IMX6UL_NUM_EPITS = 2,
86
+struct Exynos4210CombinerState {
82
+ FSL_IMX6UL_NUM_IOMUXCS = 2,
87
+ SysBusDevice parent_obj;
83
+ FSL_IMX6UL_NUM_GPIOS = 5,
88
+
84
+ FSL_IMX6UL_NUM_I2CS = 4,
89
+ MemoryRegion iomem;
85
+ FSL_IMX6UL_NUM_ECSPIS = 4,
90
+
86
+ FSL_IMX6UL_NUM_ADCS = 2,
91
+ struct CombinerGroupState group[IIC_NGRP];
92
+ uint32_t reg_set[IIC_REGSET_SIZE];
93
+ uint32_t icipsr[2];
94
+ uint32_t external; /* 1 means that this combiner is external */
95
+
96
+ qemu_irq output_irq[IIC_NGRP];
87
+};
97
+};
88
+
98
+
89
+typedef struct FslIMX6ULState {
99
+#endif
90
+ /*< private >*/
100
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
91
+ DeviceState parent_obj;
101
index XXXXXXX..XXXXXXX 100644
92
+
102
--- a/hw/arm/exynos4210.c
93
+ /*< public >*/
103
+++ b/hw/arm/exynos4210.c
94
+ ARMCPU cpu[FSL_IMX6UL_NUM_CPUS];
104
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
95
+ A15MPPrivState a7mpcore;
105
}
96
+ IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS];
106
97
+ IMXEPITState epit[FSL_IMX6UL_NUM_EPITS];
107
/* Internal Interrupt Combiner */
98
+ IMXGPIOState gpio[FSL_IMX6UL_NUM_GPIOS];
108
- dev = qdev_new("exynos4210.combiner");
99
+ IMX6ULCCMState ccm;
109
- busdev = SYS_BUS_DEVICE(dev);
100
+ IMX6SRCState src;
110
- sysbus_realize_and_unref(busdev, &error_fatal);
101
+ IMX7SNVSState snvs;
111
+ busdev = SYS_BUS_DEVICE(&s->int_combiner);
102
+ IMXGPCv2State gpcv2;
112
+ sysbus_realize(busdev, &error_fatal);
103
+ IMX7GPRState gpr;
113
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
104
+ IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
114
sysbus_connect_irq(busdev, n,
105
+ IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
115
qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
106
+ IMXSerialState uart[FSL_IMX6UL_NUM_UARTS];
116
}
107
+ IMXFECState eth[FSL_IMX6UL_NUM_ETHS];
117
- exynos4210_combiner_get_gpioin(&s->irqs, dev, 0);
108
+ SDHCIState usdhc[FSL_IMX6UL_NUM_USDHCS];
118
+ exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0);
109
+ IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS];
119
sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
110
+ MemoryRegion rom;
120
111
+ MemoryRegion caam;
121
/* External Interrupt Combiner */
112
+ MemoryRegion ocram;
122
- dev = qdev_new("exynos4210.combiner");
113
+ MemoryRegion ocram_alias;
123
- qdev_prop_set_uint32(dev, "external", 1);
114
+} FslIMX6ULState;
124
- busdev = SYS_BUS_DEVICE(dev);
115
+
125
- sysbus_realize_and_unref(busdev, &error_fatal);
116
+enum FslIMX6ULMemoryMap {
126
+ qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1);
117
+ FSL_IMX6UL_MMDC_ADDR = 0x80000000,
127
+ busdev = SYS_BUS_DEVICE(&s->ext_combiner);
118
+ FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
128
+ sysbus_realize(busdev, &error_fatal);
119
+
129
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
120
+ FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
130
sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
121
+ FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
131
}
122
+ FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
132
- exynos4210_combiner_get_gpioin(&s->irqs, dev, 1);
123
+ FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
133
+ exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1);
124
+ FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
134
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
125
+
135
126
+ /* AIPS-2 */
136
/* Initialize board IRQs. */
127
+ FSL_IMX6UL_UART6_ADDR = 0x021FC000,
137
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init(Object *obj)
128
+ FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
138
129
+ FSL_IMX6UL_UART5_ADDR = 0x021F4000,
139
object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
130
+ FSL_IMX6UL_UART4_ADDR = 0x021F0000,
140
object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_GIC);
131
+ FSL_IMX6UL_UART3_ADDR = 0x021EC000,
141
+ object_initialize_child(obj, "int-combiner", &s->int_combiner,
132
+ FSL_IMX6UL_UART2_ADDR = 0x021E8000,
142
+ TYPE_EXYNOS4210_COMBINER);
133
+ FSL_IMX6UL_WDOG3_ADDR = 0x021E4000,
143
+ object_initialize_child(obj, "ext-combiner", &s->ext_combiner,
134
+ FSL_IMX6UL_QSPI_ADDR = 0x021E0000,
144
+ TYPE_EXYNOS4210_COMBINER);
135
+ FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000,
145
}
136
+ FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000,
146
137
+ FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000,
147
static void exynos4210_class_init(ObjectClass *klass, void *data)
138
+ FSL_IMX6UL_TZASC_ADDR = 0x021D0000,
148
diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
139
+ FSL_IMX6UL_PXP_ADDR = 0x021CC000,
149
index XXXXXXX..XXXXXXX 100644
140
+ FSL_IMX6UL_LCDIF_ADDR = 0x021C8000,
150
--- a/hw/intc/exynos4210_combiner.c
141
+ FSL_IMX6UL_CSI_ADDR = 0x021C4000,
151
+++ b/hw/intc/exynos4210_combiner.c
142
+ FSL_IMX6UL_CSU_ADDR = 0x021C0000,
143
+ FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000,
144
+ FSL_IMX6UL_EIM_ADDR = 0x021B8000,
145
+ FSL_IMX6UL_SIM2_ADDR = 0x021B4000,
146
+ FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000,
147
+ FSL_IMX6UL_ROMCP_ADDR = 0x021AC000,
148
+ FSL_IMX6UL_I2C3_ADDR = 0x021A8000,
149
+ FSL_IMX6UL_I2C2_ADDR = 0x021A4000,
150
+ FSL_IMX6UL_I2C1_ADDR = 0x021A0000,
151
+ FSL_IMX6UL_ADC2_ADDR = 0x0219C000,
152
+ FSL_IMX6UL_ADC1_ADDR = 0x02198000,
153
+ FSL_IMX6UL_USDHC2_ADDR = 0x02194000,
154
+ FSL_IMX6UL_USDHC1_ADDR = 0x02190000,
155
+ FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
156
+ FSL_IMX6UL_ENET1_ADDR = 0x02188000,
157
+ FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
158
+ FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000,
159
+ FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
160
+ FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
161
+ FSL_IMX6UL_CAAM_ADDR = 0x02140000,
162
+ FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
163
+
164
+ /* AIPS-1 */
165
+ FSL_IMX6UL_PWM8_ADDR = 0x020FC000,
166
+ FSL_IMX6UL_PWM7_ADDR = 0x020F8000,
167
+ FSL_IMX6UL_PWM6_ADDR = 0x020F4000,
168
+ FSL_IMX6UL_PWM5_ADDR = 0x020F0000,
169
+ FSL_IMX6UL_SDMA_ADDR = 0x020EC000,
170
+ FSL_IMX6UL_GPT2_ADDR = 0x020E8000,
171
+ FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000,
172
+ FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000,
173
+ FSL_IMX6UL_GPC_ADDR = 0x020DC000,
174
+ FSL_IMX6UL_SRC_ADDR = 0x020D8000,
175
+ FSL_IMX6UL_EPIT2_ADDR = 0x020D4000,
176
+ FSL_IMX6UL_EPIT1_ADDR = 0x020D0000,
177
+ FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000,
178
+ FSL_IMX6UL_ANALOG_ADDR = 0x020C8000,
179
+ FSL_IMX6UL_CCM_ADDR = 0x020C4000,
180
+ FSL_IMX6UL_WDOG2_ADDR = 0x020C0000,
181
+ FSL_IMX6UL_WDOG1_ADDR = 0x020BC000,
182
+ FSL_IMX6UL_KPP_ADDR = 0x020B8000,
183
+ FSL_IMX6UL_ENET2_ADDR = 0x020B4000,
184
+ FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000,
185
+ FSL_IMX6UL_GPIO5_ADDR = 0x020AC000,
186
+ FSL_IMX6UL_GPIO4_ADDR = 0x020A8000,
187
+ FSL_IMX6UL_GPIO3_ADDR = 0x020A4000,
188
+ FSL_IMX6UL_GPIO2_ADDR = 0x020A0000,
189
+ FSL_IMX6UL_GPIO1_ADDR = 0x0209C000,
190
+ FSL_IMX6UL_GPT1_ADDR = 0x02098000,
191
+ FSL_IMX6UL_CAN2_ADDR = 0x02094000,
192
+ FSL_IMX6UL_CAN1_ADDR = 0x02090000,
193
+ FSL_IMX6UL_PWM4_ADDR = 0x0208C000,
194
+ FSL_IMX6UL_PWM3_ADDR = 0x02088000,
195
+ FSL_IMX6UL_PWM2_ADDR = 0x02084000,
196
+ FSL_IMX6UL_PWM1_ADDR = 0x02080000,
197
+ FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000,
198
+ FSL_IMX6UL_BEE_ADDR = 0x02044000,
199
+ FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000,
200
+ FSL_IMX6UL_SPBA_ADDR = 0x0203C000,
201
+ FSL_IMX6UL_ASRC_ADDR = 0x02034000,
202
+ FSL_IMX6UL_SAI3_ADDR = 0x02030000,
203
+ FSL_IMX6UL_SAI2_ADDR = 0x0202C000,
204
+ FSL_IMX6UL_SAI1_ADDR = 0x02028000,
205
+ FSL_IMX6UL_UART8_ADDR = 0x02024000,
206
+ FSL_IMX6UL_UART1_ADDR = 0x02020000,
207
+ FSL_IMX6UL_UART7_ADDR = 0x02018000,
208
+ FSL_IMX6UL_ECSPI4_ADDR = 0x02014000,
209
+ FSL_IMX6UL_ECSPI3_ADDR = 0x02010000,
210
+ FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000,
211
+ FSL_IMX6UL_ECSPI1_ADDR = 0x02008000,
212
+ FSL_IMX6UL_SPDIF_ADDR = 0x02004000,
213
+
214
+ FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000,
215
+ FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024),
216
+
217
+ FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000,
218
+
219
+ FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000,
220
+ FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000,
221
+ FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000,
222
+ FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000,
223
+ FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000,
224
+ FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000,
225
+ FSL_IMX6UL_ROM_ADDR = 0x00000000,
226
+ FSL_IMX6UL_ROM_SIZE = 0x00018000,
227
+};
228
+
229
+enum FslIMX6ULIRQs {
230
+ FSL_IMX6UL_IOMUXC_IRQ = 0,
231
+ FSL_IMX6UL_DAP_IRQ = 1,
232
+ FSL_IMX6UL_SDMA_IRQ = 2,
233
+ FSL_IMX6UL_TSC_IRQ = 3,
234
+ FSL_IMX6UL_SNVS_IRQ = 4,
235
+ FSL_IMX6UL_LCDIF_IRQ = 5,
236
+ FSL_IMX6UL_BEE_IRQ = 6,
237
+ FSL_IMX6UL_CSI_IRQ = 7,
238
+ FSL_IMX6UL_PXP_IRQ = 8,
239
+ FSL_IMX6UL_SCTR1_IRQ = 9,
240
+ FSL_IMX6UL_SCTR2_IRQ = 10,
241
+ FSL_IMX6UL_WDOG3_IRQ = 11,
242
+ FSL_IMX6UL_APBH_DMA_IRQ = 13,
243
+ FSL_IMX6UL_WEIM_IRQ = 14,
244
+ FSL_IMX6UL_RAWNAND1_IRQ = 15,
245
+ FSL_IMX6UL_RAWNAND2_IRQ = 16,
246
+ FSL_IMX6UL_UART6_IRQ = 17,
247
+ FSL_IMX6UL_SRTC_IRQ = 19,
248
+ FSL_IMX6UL_SRTC_SEC_IRQ = 20,
249
+ FSL_IMX6UL_CSU_IRQ = 21,
250
+ FSL_IMX6UL_USDHC1_IRQ = 22,
251
+ FSL_IMX6UL_USDHC2_IRQ = 23,
252
+ FSL_IMX6UL_SAI3_IRQ = 24,
253
+ FSL_IMX6UL_SAI32_IRQ = 25,
254
+
255
+ FSL_IMX6UL_UART1_IRQ = 26,
256
+ FSL_IMX6UL_UART2_IRQ = 27,
257
+ FSL_IMX6UL_UART3_IRQ = 28,
258
+ FSL_IMX6UL_UART4_IRQ = 29,
259
+ FSL_IMX6UL_UART5_IRQ = 30,
260
+
261
+ FSL_IMX6UL_ECSPI1_IRQ = 31,
262
+ FSL_IMX6UL_ECSPI2_IRQ = 32,
263
+ FSL_IMX6UL_ECSPI3_IRQ = 33,
264
+ FSL_IMX6UL_ECSPI4_IRQ = 34,
265
+
266
+ FSL_IMX6UL_I2C4_IRQ = 35,
267
+ FSL_IMX6UL_I2C1_IRQ = 36,
268
+ FSL_IMX6UL_I2C2_IRQ = 37,
269
+ FSL_IMX6UL_I2C3_IRQ = 38,
270
+
271
+ FSL_IMX6UL_UART7_IRQ = 39,
272
+ FSL_IMX6UL_UART8_IRQ = 40,
273
+
274
+ FSL_IMX6UL_USB1_IRQ = 42,
275
+ FSL_IMX6UL_USB2_IRQ = 43,
276
+ FSL_IMX6UL_USB_PHY1_IRQ = 44,
277
+ FSL_IMX6UL_USB_PHY2_IRQ = 44,
278
+
279
+ FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
280
+ FSL_IMX6UL_CAAM_ERR_IRQ = 47,
281
+ FSL_IMX6UL_CAAM_RTIC_IRQ = 48,
282
+ FSL_IMX6UL_TEMP_IRQ = 49,
283
+ FSL_IMX6UL_ASRC_IRQ = 50,
284
+ FSL_IMX6UL_SPDIF_IRQ = 52,
285
+ FSL_IMX6UL_PMU_REG_IRQ = 54,
286
+ FSL_IMX6UL_GPT1_IRQ = 55,
287
+
288
+ FSL_IMX6UL_EPIT1_IRQ = 56,
289
+ FSL_IMX6UL_EPIT2_IRQ = 57,
290
+
291
+ FSL_IMX6UL_GPIO1_INT7_IRQ = 58,
292
+ FSL_IMX6UL_GPIO1_INT6_IRQ = 59,
293
+ FSL_IMX6UL_GPIO1_INT5_IRQ = 60,
294
+ FSL_IMX6UL_GPIO1_INT4_IRQ = 61,
295
+ FSL_IMX6UL_GPIO1_INT3_IRQ = 62,
296
+ FSL_IMX6UL_GPIO1_INT2_IRQ = 63,
297
+ FSL_IMX6UL_GPIO1_INT1_IRQ = 64,
298
+ FSL_IMX6UL_GPIO1_INT0_IRQ = 65,
299
+ FSL_IMX6UL_GPIO1_LOW_IRQ = 66,
300
+ FSL_IMX6UL_GPIO1_HIGH_IRQ = 67,
301
+ FSL_IMX6UL_GPIO2_LOW_IRQ = 68,
302
+ FSL_IMX6UL_GPIO2_HIGH_IRQ = 69,
303
+ FSL_IMX6UL_GPIO3_LOW_IRQ = 70,
304
+ FSL_IMX6UL_GPIO3_HIGH_IRQ = 71,
305
+ FSL_IMX6UL_GPIO4_LOW_IRQ = 72,
306
+ FSL_IMX6UL_GPIO4_HIGH_IRQ = 73,
307
+ FSL_IMX6UL_GPIO5_LOW_IRQ = 74,
308
+ FSL_IMX6UL_GPIO5_HIGH_IRQ = 75,
309
+
310
+ FSL_IMX6UL_WDOG1_IRQ = 80,
311
+ FSL_IMX6UL_WDOG2_IRQ = 81,
312
+
313
+ FSL_IMX6UL_KPP_IRQ = 82,
314
+
315
+ FSL_IMX6UL_PWM1_IRQ = 83,
316
+ FSL_IMX6UL_PWM2_IRQ = 84,
317
+ FSL_IMX6UL_PWM3_IRQ = 85,
318
+ FSL_IMX6UL_PWM4_IRQ = 86,
319
+
320
+ FSL_IMX6UL_CCM1_IRQ = 87,
321
+ FSL_IMX6UL_CCM2_IRQ = 88,
322
+
323
+ FSL_IMX6UL_GPC_IRQ = 89,
324
+
325
+ FSL_IMX6UL_SRC_IRQ = 91,
326
+
327
+ FSL_IMX6UL_CPU_PERF_IRQ = 94,
328
+ FSL_IMX6UL_CPU_CTI_IRQ = 95,
329
+
330
+ FSL_IMX6UL_SRC_WDOG_IRQ = 96,
331
+
332
+ FSL_IMX6UL_SAI1_IRQ = 97,
333
+ FSL_IMX6UL_SAI2_IRQ = 98,
334
+
335
+ FSL_IMX6UL_ADC1_IRQ = 100,
336
+ FSL_IMX6UL_ADC2_IRQ = 101,
337
+
338
+ FSL_IMX6UL_SJC_IRQ = 104,
339
+
340
+ FSL_IMX6UL_CAAM_RING0_IRQ = 105,
341
+ FSL_IMX6UL_CAAM_RING1_IRQ = 106,
342
+
343
+ FSL_IMX6UL_QSPI_IRQ = 107,
344
+
345
+ FSL_IMX6UL_TZASC_IRQ = 108,
346
+
347
+ FSL_IMX6UL_GPT2_IRQ = 109,
348
+
349
+ FSL_IMX6UL_CAN1_IRQ = 110,
350
+ FSL_IMX6UL_CAN2_IRQ = 111,
351
+
352
+ FSL_IMX6UL_SIM1_IRQ = 112,
353
+ FSL_IMX6UL_SIM2_IRQ = 113,
354
+
355
+ FSL_IMX6UL_PWM5_IRQ = 114,
356
+ FSL_IMX6UL_PWM6_IRQ = 115,
357
+ FSL_IMX6UL_PWM7_IRQ = 116,
358
+ FSL_IMX6UL_PWM8_IRQ = 117,
359
+
360
+ FSL_IMX6UL_ENET1_IRQ = 118,
361
+ FSL_IMX6UL_ENET1_TIMER_IRQ = 119,
362
+ FSL_IMX6UL_ENET2_IRQ = 120,
363
+ FSL_IMX6UL_ENET2_TIMER_IRQ = 121,
364
+
365
+ FSL_IMX6UL_PMU_CORE_IRQ = 127,
366
+ FSL_IMX6UL_MAX_IRQ = 128,
367
+};
368
+
369
+#endif /* FSL_IMX6UL_H */
370
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
371
new file mode 100644
372
index XXXXXXX..XXXXXXX
373
--- /dev/null
374
+++ b/hw/arm/fsl-imx6ul.c
375
@@ -XXX,XX +XXX,XX @@
152
@@ -XXX,XX +XXX,XX @@
376
+/*
153
#include "hw/sysbus.h"
377
+ * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
154
#include "migration/vmstate.h"
378
+ *
155
#include "qemu/module.h"
379
+ * i.MX6UL SOC emulation.
156
-
380
+ *
157
+#include "hw/intc/exynos4210_combiner.h"
381
+ * Based on hw/arm/fsl-imx7.c
158
#include "hw/arm/exynos4210.h"
382
+ *
159
#include "hw/hw.h"
383
+ * This program is free software; you can redistribute it and/or modify
160
#include "hw/irq.h"
384
+ * it under the terms of the GNU General Public License as published by
161
@@ -XXX,XX +XXX,XX @@
385
+ * the Free Software Foundation; either version 2 of the License, or
162
#define DPRINTF(fmt, ...) do {} while (0)
386
+ * (at your option) any later version.
163
#endif
387
+ *
164
388
+ * This program is distributed in the hope that it will be useful,
165
-#define IIC_NGRP 64 /* Internal Interrupt Combiner
389
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
166
- Groups number */
390
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
167
-#define IIC_NIRQ (IIC_NGRP * 8)/* Internal Interrupt Combiner
391
+ * GNU General Public License for more details.
168
- Interrupts number */
392
+ */
169
#define IIC_REGION_SIZE 0x108 /* Size of memory mapped region */
393
+
170
-#define IIC_REGSET_SIZE 0x41
394
+#include "qemu/osdep.h"
171
-
395
+#include "qapi/error.h"
172
-/*
396
+#include "qemu-common.h"
173
- * State for each output signal of internal combiner
397
+#include "hw/arm/fsl-imx6ul.h"
174
- */
398
+#include "hw/misc/unimp.h"
175
-typedef struct CombinerGroupState {
399
+#include "sysemu/sysemu.h"
176
- uint8_t src_mask; /* 1 - source enabled, 0 - disabled */
400
+#include "qemu/error-report.h"
177
- uint8_t src_pending; /* Pending source interrupts before masking */
401
+
178
-} CombinerGroupState;
402
+#define NAME_SIZE 20
179
-
403
+
180
-#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
404
+static void fsl_imx6ul_init(Object *obj)
181
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER)
405
+{
182
-
406
+ FslIMX6ULState *s = FSL_IMX6UL(obj);
183
-struct Exynos4210CombinerState {
407
+ char name[NAME_SIZE];
184
- SysBusDevice parent_obj;
408
+ int i;
185
-
409
+
186
- MemoryRegion iomem;
410
+ for (i = 0; i < MIN(smp_cpus, FSL_IMX6UL_NUM_CPUS); i++) {
187
-
411
+ snprintf(name, NAME_SIZE, "cpu%d", i);
188
- struct CombinerGroupState group[IIC_NGRP];
412
+ object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
189
- uint32_t reg_set[IIC_REGSET_SIZE];
413
+ "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
190
- uint32_t icipsr[2];
414
+ }
191
- uint32_t external; /* 1 means that this combiner is external */
415
+
192
-
416
+ /*
193
- qemu_irq output_irq[IIC_NGRP];
417
+ * A7MPCORE
194
-};
418
+ */
195
419
+ sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
196
static const VMStateDescription vmstate_exynos4210_combiner_group_state = {
420
+ TYPE_A15MPCORE_PRIV);
197
.name = "exynos4210.combiner.groupstate",
421
+
422
+ /*
423
+ * CCM
424
+ */
425
+ sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX6UL_CCM);
426
+
427
+ /*
428
+ * SRC
429
+ */
430
+ sysbus_init_child_obj(obj, "src", &s->src, sizeof(s->src), TYPE_IMX6_SRC);
431
+
432
+ /*
433
+ * GPCv2
434
+ */
435
+ sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
436
+ TYPE_IMX_GPCV2);
437
+
438
+ /*
439
+ * SNVS
440
+ */
441
+ sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
442
+ TYPE_IMX7_SNVS);
443
+
444
+ /*
445
+ * GPR
446
+ */
447
+ sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr),
448
+ TYPE_IMX7_GPR);
449
+
450
+ /*
451
+ * GPIOs 1 to 5
452
+ */
453
+ for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
454
+ snprintf(name, NAME_SIZE, "gpio%d", i);
455
+ sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
456
+ TYPE_IMX_GPIO);
457
+ }
458
+
459
+ /*
460
+ * GPT 1, 2
461
+ */
462
+ for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
463
+ snprintf(name, NAME_SIZE, "gpt%d", i);
464
+ sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
465
+ TYPE_IMX7_GPT);
466
+ }
467
+
468
+ /*
469
+ * EPIT 1, 2
470
+ */
471
+ for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
472
+ snprintf(name, NAME_SIZE, "epit%d", i + 1);
473
+ sysbus_init_child_obj(obj, name, &s->epit[i], sizeof(s->epit[i]),
474
+ TYPE_IMX_EPIT);
475
+ }
476
+
477
+ /*
478
+ * eCSPI
479
+ */
480
+ for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
481
+ snprintf(name, NAME_SIZE, "spi%d", i + 1);
482
+ sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
483
+ TYPE_IMX_SPI);
484
+ }
485
+
486
+ /*
487
+ * I2C
488
+ */
489
+ for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
490
+ snprintf(name, NAME_SIZE, "i2c%d", i + 1);
491
+ sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
492
+ TYPE_IMX_I2C);
493
+ }
494
+
495
+ /*
496
+ * UART
497
+ */
498
+ for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
499
+ snprintf(name, NAME_SIZE, "uart%d", i);
500
+ sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
501
+ TYPE_IMX_SERIAL);
502
+ }
503
+
504
+ /*
505
+ * Ethernet
506
+ */
507
+ for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
508
+ snprintf(name, NAME_SIZE, "eth%d", i);
509
+ sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
510
+ TYPE_IMX_ENET);
511
+ }
512
+
513
+ /*
514
+ * SDHCI
515
+ */
516
+ for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
517
+ snprintf(name, NAME_SIZE, "usdhc%d", i);
518
+ sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
519
+ TYPE_IMX_USDHC);
520
+ }
521
+
522
+ /*
523
+ * Watchdog
524
+ */
525
+ for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
526
+ snprintf(name, NAME_SIZE, "wdt%d", i);
527
+ sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
528
+ TYPE_IMX2_WDT);
529
+ }
530
+}
531
+
532
+static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
533
+{
534
+ FslIMX6ULState *s = FSL_IMX6UL(dev);
535
+ int i;
536
+ qemu_irq irq;
537
+ char name[NAME_SIZE];
538
+
539
+ if (smp_cpus > FSL_IMX6UL_NUM_CPUS) {
540
+ error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
541
+ TYPE_FSL_IMX6UL, FSL_IMX6UL_NUM_CPUS, smp_cpus);
542
+ return;
543
+ }
544
+
545
+ for (i = 0; i < smp_cpus; i++) {
546
+ Object *o = OBJECT(&s->cpu[i]);
547
+
548
+ object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
549
+ "psci-conduit", &error_abort);
550
+
551
+ /* On uniprocessor, the CBAR is set to 0 */
552
+ if (smp_cpus > 1) {
553
+ object_property_set_int(o, FSL_IMX6UL_A7MPCORE_ADDR,
554
+ "reset-cbar", &error_abort);
555
+ }
556
+
557
+ if (i) {
558
+ /* Secondary CPUs start in PSCI powered-down state */
559
+ object_property_set_bool(o, true,
560
+ "start-powered-off", &error_abort);
561
+ }
562
+
563
+ object_property_set_bool(o, true, "realized", &error_abort);
564
+ }
565
+
566
+ /*
567
+ * A7MPCORE
568
+ */
569
+ object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
570
+ &error_abort);
571
+ object_property_set_int(OBJECT(&s->a7mpcore),
572
+ FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL,
573
+ "num-irq", &error_abort);
574
+ object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
575
+ &error_abort);
576
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
577
+
578
+ for (i = 0; i < smp_cpus; i++) {
579
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
580
+ DeviceState *d = DEVICE(qemu_get_cpu(i));
581
+
582
+ irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
583
+ sysbus_connect_irq(sbd, i, irq);
584
+ sysbus_connect_irq(sbd, i + smp_cpus, qdev_get_gpio_in(d, ARM_CPU_FIQ));
585
+ }
586
+
587
+ /*
588
+ * A7MPCORE DAP
589
+ */
590
+ create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
591
+ 0x100000);
592
+
593
+ /*
594
+ * GPT 1, 2
595
+ */
596
+ for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
597
+ static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
598
+ FSL_IMX6UL_GPT1_ADDR,
599
+ FSL_IMX6UL_GPT2_ADDR,
600
+ };
601
+
602
+ static const int FSL_IMX6UL_GPTn_IRQ[FSL_IMX6UL_NUM_GPTS] = {
603
+ FSL_IMX6UL_GPT1_IRQ,
604
+ FSL_IMX6UL_GPT2_IRQ,
605
+ };
606
+
607
+ s->gpt[i].ccm = IMX_CCM(&s->ccm);
608
+ object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
609
+ &error_abort);
610
+
611
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0,
612
+ FSL_IMX6UL_GPTn_ADDR[i]);
613
+
614
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
615
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
616
+ FSL_IMX6UL_GPTn_IRQ[i]));
617
+ }
618
+
619
+ /*
620
+ * EPIT 1, 2
621
+ */
622
+ for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
623
+ static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
624
+ FSL_IMX6UL_EPIT1_ADDR,
625
+ FSL_IMX6UL_EPIT2_ADDR,
626
+ };
627
+
628
+ static const int FSL_IMX6UL_EPITn_IRQ[FSL_IMX6UL_NUM_EPITS] = {
629
+ FSL_IMX6UL_EPIT1_IRQ,
630
+ FSL_IMX6UL_EPIT2_IRQ,
631
+ };
632
+
633
+ s->epit[i].ccm = IMX_CCM(&s->ccm);
634
+ object_property_set_bool(OBJECT(&s->epit[i]), true, "realized",
635
+ &error_abort);
636
+
637
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0,
638
+ FSL_IMX6UL_EPITn_ADDR[i]);
639
+
640
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
641
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
642
+ FSL_IMX6UL_EPITn_IRQ[i]));
643
+ }
644
+
645
+ /*
646
+ * GPIO
647
+ */
648
+ for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
649
+ static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
650
+ FSL_IMX6UL_GPIO1_ADDR,
651
+ FSL_IMX6UL_GPIO2_ADDR,
652
+ FSL_IMX6UL_GPIO3_ADDR,
653
+ FSL_IMX6UL_GPIO4_ADDR,
654
+ FSL_IMX6UL_GPIO5_ADDR,
655
+ };
656
+
657
+ static const int FSL_IMX6UL_GPIOn_LOW_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
658
+ FSL_IMX6UL_GPIO1_LOW_IRQ,
659
+ FSL_IMX6UL_GPIO2_LOW_IRQ,
660
+ FSL_IMX6UL_GPIO3_LOW_IRQ,
661
+ FSL_IMX6UL_GPIO4_LOW_IRQ,
662
+ FSL_IMX6UL_GPIO5_LOW_IRQ,
663
+ };
664
+
665
+ static const int FSL_IMX6UL_GPIOn_HIGH_IRQ[FSL_IMX6UL_NUM_GPIOS] = {
666
+ FSL_IMX6UL_GPIO1_HIGH_IRQ,
667
+ FSL_IMX6UL_GPIO2_HIGH_IRQ,
668
+ FSL_IMX6UL_GPIO3_HIGH_IRQ,
669
+ FSL_IMX6UL_GPIO4_HIGH_IRQ,
670
+ FSL_IMX6UL_GPIO5_HIGH_IRQ,
671
+ };
672
+
673
+ object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
674
+ &error_abort);
675
+
676
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
677
+ FSL_IMX6UL_GPIOn_ADDR[i]);
678
+
679
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
680
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
681
+ FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
682
+
683
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
684
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
685
+ FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
686
+ }
687
+
688
+ /*
689
+ * IOMUXC and IOMUXC_GPR
690
+ */
691
+ for (i = 0; i < 1; i++) {
692
+ static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
693
+ FSL_IMX6UL_IOMUXC_ADDR,
694
+ FSL_IMX6UL_IOMUXC_GPR_ADDR,
695
+ };
696
+
697
+ snprintf(name, NAME_SIZE, "iomuxc%d", i);
698
+ create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
699
+ }
700
+
701
+ /*
702
+ * CCM
703
+ */
704
+ object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
705
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX6UL_CCM_ADDR);
706
+
707
+ /*
708
+ * SRC
709
+ */
710
+ object_property_set_bool(OBJECT(&s->src), true, "realized", &error_abort);
711
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX6UL_SRC_ADDR);
712
+
713
+ /*
714
+ * GPCv2
715
+ */
716
+ object_property_set_bool(OBJECT(&s->gpcv2), true,
717
+ "realized", &error_abort);
718
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
719
+
720
+ /* Initialize all ECSPI */
721
+ for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
722
+ static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
723
+ FSL_IMX6UL_ECSPI1_ADDR,
724
+ FSL_IMX6UL_ECSPI2_ADDR,
725
+ FSL_IMX6UL_ECSPI3_ADDR,
726
+ FSL_IMX6UL_ECSPI4_ADDR,
727
+ };
728
+
729
+ static const int FSL_IMX6UL_SPIn_IRQ[FSL_IMX6UL_NUM_ECSPIS] = {
730
+ FSL_IMX6UL_ECSPI1_IRQ,
731
+ FSL_IMX6UL_ECSPI2_IRQ,
732
+ FSL_IMX6UL_ECSPI3_IRQ,
733
+ FSL_IMX6UL_ECSPI4_IRQ,
734
+ };
735
+
736
+ /* Initialize the SPI */
737
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
738
+ &error_abort);
739
+
740
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
741
+ FSL_IMX6UL_SPIn_ADDR[i]);
742
+
743
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
744
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
745
+ FSL_IMX6UL_SPIn_IRQ[i]));
746
+ }
747
+
748
+ /*
749
+ * I2C
750
+ */
751
+ for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
752
+ static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
753
+ FSL_IMX6UL_I2C1_ADDR,
754
+ FSL_IMX6UL_I2C2_ADDR,
755
+ FSL_IMX6UL_I2C3_ADDR,
756
+ FSL_IMX6UL_I2C4_ADDR,
757
+ };
758
+
759
+ static const int FSL_IMX6UL_I2Cn_IRQ[FSL_IMX6UL_NUM_I2CS] = {
760
+ FSL_IMX6UL_I2C1_IRQ,
761
+ FSL_IMX6UL_I2C2_IRQ,
762
+ FSL_IMX6UL_I2C3_IRQ,
763
+ FSL_IMX6UL_I2C4_IRQ,
764
+ };
765
+
766
+ object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
767
+ &error_abort);
768
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
769
+
770
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
771
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
772
+ FSL_IMX6UL_I2Cn_IRQ[i]));
773
+ }
774
+
775
+ /*
776
+ * UART
777
+ */
778
+ for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
779
+ static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
780
+ FSL_IMX6UL_UART1_ADDR,
781
+ FSL_IMX6UL_UART2_ADDR,
782
+ FSL_IMX6UL_UART3_ADDR,
783
+ FSL_IMX6UL_UART4_ADDR,
784
+ FSL_IMX6UL_UART5_ADDR,
785
+ FSL_IMX6UL_UART6_ADDR,
786
+ FSL_IMX6UL_UART7_ADDR,
787
+ FSL_IMX6UL_UART8_ADDR,
788
+ };
789
+
790
+ static const int FSL_IMX6UL_UARTn_IRQ[FSL_IMX6UL_NUM_UARTS] = {
791
+ FSL_IMX6UL_UART1_IRQ,
792
+ FSL_IMX6UL_UART2_IRQ,
793
+ FSL_IMX6UL_UART3_IRQ,
794
+ FSL_IMX6UL_UART4_IRQ,
795
+ FSL_IMX6UL_UART5_IRQ,
796
+ FSL_IMX6UL_UART6_IRQ,
797
+ FSL_IMX6UL_UART7_IRQ,
798
+ FSL_IMX6UL_UART8_IRQ,
799
+ };
800
+
801
+ qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
802
+
803
+ object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
804
+ &error_abort);
805
+
806
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0,
807
+ FSL_IMX6UL_UARTn_ADDR[i]);
808
+
809
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
810
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
811
+ FSL_IMX6UL_UARTn_IRQ[i]));
812
+ }
813
+
814
+ /*
815
+ * Ethernet
816
+ */
817
+ for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
818
+ static const hwaddr FSL_IMX6UL_ENETn_ADDR[FSL_IMX6UL_NUM_ETHS] = {
819
+ FSL_IMX6UL_ENET1_ADDR,
820
+ FSL_IMX6UL_ENET2_ADDR,
821
+ };
822
+
823
+ static const int FSL_IMX6UL_ENETn_IRQ[FSL_IMX6UL_NUM_ETHS] = {
824
+ FSL_IMX6UL_ENET1_IRQ,
825
+ FSL_IMX6UL_ENET2_IRQ,
826
+ };
827
+
828
+ static const int FSL_IMX6UL_ENETn_TIMER_IRQ[FSL_IMX6UL_NUM_ETHS] = {
829
+ FSL_IMX6UL_ENET1_TIMER_IRQ,
830
+ FSL_IMX6UL_ENET2_TIMER_IRQ,
831
+ };
832
+
833
+ object_property_set_uint(OBJECT(&s->eth[i]),
834
+ FSL_IMX6UL_ETH_NUM_TX_RINGS,
835
+ "tx-ring-num", &error_abort);
836
+ qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
837
+ object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
838
+ &error_abort);
839
+
840
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0,
841
+ FSL_IMX6UL_ENETn_ADDR[i]);
842
+
843
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
844
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
845
+ FSL_IMX6UL_ENETn_IRQ[i]));
846
+
847
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
848
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
849
+ FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
850
+ }
851
+
852
+ /*
853
+ * USDHC
854
+ */
855
+ for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
856
+ static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
857
+ FSL_IMX6UL_USDHC1_ADDR,
858
+ FSL_IMX6UL_USDHC2_ADDR,
859
+ };
860
+
861
+ static const int FSL_IMX6UL_USDHCn_IRQ[FSL_IMX6UL_NUM_USDHCS] = {
862
+ FSL_IMX6UL_USDHC1_IRQ,
863
+ FSL_IMX6UL_USDHC2_IRQ,
864
+ };
865
+
866
+ object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
867
+ &error_abort);
868
+
869
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
870
+ FSL_IMX6UL_USDHCn_ADDR[i]);
871
+
872
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
873
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
874
+ FSL_IMX6UL_USDHCn_IRQ[i]));
875
+ }
876
+
877
+ /*
878
+ * SNVS
879
+ */
880
+ object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
881
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
882
+
883
+ /*
884
+ * Watchdog
885
+ */
886
+ for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
887
+ static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
888
+ FSL_IMX6UL_WDOG1_ADDR,
889
+ FSL_IMX6UL_WDOG2_ADDR,
890
+ FSL_IMX6UL_WDOG3_ADDR,
891
+ };
892
+
893
+ object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
894
+ &error_abort);
895
+
896
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
897
+ FSL_IMX6UL_WDOGn_ADDR[i]);
898
+ }
899
+
900
+ /*
901
+ * GPR
902
+ */
903
+ object_property_set_bool(OBJECT(&s->gpr), true, "realized",
904
+ &error_abort);
905
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
906
+
907
+ /*
908
+ * SDMA
909
+ */
910
+ create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
911
+
912
+ /*
913
+ * APHB_DMA
914
+ */
915
+ create_unimplemented_device("aphb_dma", FSL_IMX6UL_APBH_DMA_ADDR,
916
+ FSL_IMX6UL_APBH_DMA_SIZE);
917
+
918
+ /*
919
+ * ADCs
920
+ */
921
+ for (i = 0; i < FSL_IMX6UL_NUM_ADCS; i++) {
922
+ static const hwaddr FSL_IMX6UL_ADCn_ADDR[FSL_IMX6UL_NUM_ADCS] = {
923
+ FSL_IMX6UL_ADC1_ADDR,
924
+ FSL_IMX6UL_ADC2_ADDR,
925
+ };
926
+
927
+ snprintf(name, NAME_SIZE, "adc%d", i);
928
+ create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
929
+ }
930
+
931
+ /*
932
+ * LCD
933
+ */
934
+ create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
935
+
936
+ /*
937
+ * ROM memory
938
+ */
939
+ memory_region_init_rom(&s->rom, NULL, "imx6ul.rom",
940
+ FSL_IMX6UL_ROM_SIZE, &error_abort);
941
+ memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_ROM_ADDR,
942
+ &s->rom);
943
+
944
+ /*
945
+ * CAAM memory
946
+ */
947
+ memory_region_init_rom(&s->caam, NULL, "imx6ul.caam",
948
+ FSL_IMX6UL_CAAM_MEM_SIZE, &error_abort);
949
+ memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_CAAM_MEM_ADDR,
950
+ &s->caam);
951
+
952
+ /*
953
+ * OCRAM memory
954
+ */
955
+ memory_region_init_ram(&s->ocram, NULL, "imx6ul.ocram",
956
+ FSL_IMX6UL_OCRAM_MEM_SIZE,
957
+ &error_abort);
958
+ memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_OCRAM_MEM_ADDR,
959
+ &s->ocram);
960
+
961
+ /*
962
+ * internal OCRAM (128 KB) is aliased over 512 KB
963
+ */
964
+ memory_region_init_alias(&s->ocram_alias, NULL, "imx6ul.ocram_alias",
965
+ &s->ocram, 0, FSL_IMX6UL_OCRAM_ALIAS_SIZE);
966
+ memory_region_add_subregion(get_system_memory(),
967
+ FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
968
+}
969
+
970
+static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
971
+{
972
+ DeviceClass *dc = DEVICE_CLASS(oc);
973
+
974
+ dc->realize = fsl_imx6ul_realize;
975
+ dc->desc = "i.MX6UL SOC";
976
+ /* Reason: Uses serial_hds and nd_table in realize() directly */
977
+ dc->user_creatable = false;
978
+}
979
+
980
+static const TypeInfo fsl_imx6ul_type_info = {
981
+ .name = TYPE_FSL_IMX6UL,
982
+ .parent = TYPE_DEVICE,
983
+ .instance_size = sizeof(FslIMX6ULState),
984
+ .instance_init = fsl_imx6ul_init,
985
+ .class_init = fsl_imx6ul_class_init,
986
+};
987
+
988
+static void fsl_imx6ul_register_types(void)
989
+{
990
+ type_register_static(&fsl_imx6ul_type_info);
991
+}
992
+type_init(fsl_imx6ul_register_types)
993
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
994
index XXXXXXX..XXXXXXX 100644
995
--- a/default-configs/arm-softmmu.mak
996
+++ b/default-configs/arm-softmmu.mak
997
@@ -XXX,XX +XXX,XX @@ CONFIG_FSL_IMX6=y
998
CONFIG_FSL_IMX31=y
999
CONFIG_FSL_IMX25=y
1000
CONFIG_FSL_IMX7=y
1001
+CONFIG_FSL_IMX6UL=y
1002
1003
CONFIG_IMX_I2C=y
1004
1005
--
198
--
1006
2.18.0
199
2.25.1
1007
1008
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The only time we use the int_combiner_irq[] and ext_combiner_irq[]
2
arrays in the Exynos4210Irq struct is during realize of the SoC -- we
3
initialize them with the input IRQs of the combiner devices, and then
4
connect those to outputs of other devices in
5
exynos4210_init_board_irqs(). Now that the combiner objects are
6
easily accessible as s->int_combiner and s->ext_combiner we can make
7
the connections directly from one device to the other without going
8
via these arrays.
2
9
3
The expression (int) imm + (uint32_t) len_align turns into uint32_t
10
Since these are the only two remaining elements of Exynos4210Irq,
4
and thus with negative imm produces a memory operation at the wrong
11
we can remove that struct entirely.
5
offset. None of the numbers involved are particularly large, so
6
change everything to use int.
7
12
8
Cc: qemu-stable@nongnu.org (3.0.1)
9
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220404154658.565020-19-peter.maydell@linaro.org
13
---
16
---
14
target/arm/translate-sve.c | 18 ++++++++----------
17
include/hw/arm/exynos4210.h | 6 ------
15
1 file changed, 8 insertions(+), 10 deletions(-)
18
hw/arm/exynos4210.c | 34 ++++++++--------------------------
19
2 files changed, 8 insertions(+), 32 deletions(-)
16
20
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
21
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
18
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-sve.c
23
--- a/include/hw/arm/exynos4210.h
20
+++ b/target/arm/translate-sve.c
24
+++ b/include/hw/arm/exynos4210.h
21
@@ -XXX,XX +XXX,XX @@ static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
25
@@ -XXX,XX +XXX,XX @@
22
* The load should begin at the address Rn + IMM.
23
*/
26
*/
24
27
#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
25
-static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len,
28
26
- int rn, int imm)
29
-typedef struct Exynos4210Irq {
27
+static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
30
- qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
31
- qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
32
-} Exynos4210Irq;
33
-
34
struct Exynos4210State {
35
/*< private >*/
36
SysBusDevice parent_obj;
37
/*< public >*/
38
ARMCPU *cpu[EXYNOS4210_NCPUS];
39
- Exynos4210Irq irqs;
40
qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
41
42
MemoryRegion chipid_mem;
43
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/exynos4210.c
46
+++ b/hw/arm/exynos4210.c
47
@@ -XXX,XX +XXX,XX @@ static int mapline_size(const int *mapline)
48
static void exynos4210_init_board_irqs(Exynos4210State *s)
28
{
49
{
29
- uint32_t len_align = QEMU_ALIGN_DOWN(len, 8);
50
uint32_t grp, bit, irq_id, n;
30
- uint32_t len_remain = len % 8;
51
- Exynos4210Irq *is = &s->irqs;
31
- uint32_t nparts = len / 8 + ctpop8(len_remain);
52
DeviceState *extgicdev = DEVICE(&s->ext_gic);
32
+ int len_align = QEMU_ALIGN_DOWN(len, 8);
53
+ DeviceState *intcdev = DEVICE(&s->int_combiner);
33
+ int len_remain = len % 8;
54
+ DeviceState *extcdev = DEVICE(&s->ext_combiner);
34
+ int nparts = len / 8 + ctpop8(len_remain);
55
int splitcount = 0;
35
int midx = get_mem_index(s);
56
DeviceState *splitter;
36
TCGv_i64 addr, t0, t1;
57
const int *mapline;
37
58
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
38
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, uint32_t len,
59
splitin = 0;
60
for (;;) {
61
s->irq_table[in] = qdev_get_gpio_in(splitter, 0);
62
- qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[in]);
63
- qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_irq[in]);
64
+ qdev_connect_gpio_out(splitter, splitin,
65
+ qdev_get_gpio_in(intcdev, in));
66
+ qdev_connect_gpio_out(splitter, splitin + 1,
67
+ qdev_get_gpio_in(extcdev, in));
68
splitin += 2;
69
if (!mapline) {
70
break;
71
@@ -XXX,XX +XXX,XX @@ static void exynos4210_init_board_irqs(Exynos4210State *s)
72
qdev_realize(splitter, NULL, &error_abort);
73
splitcount++;
74
s->irq_table[n] = qdev_get_gpio_in(splitter, 0);
75
- qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]);
76
+ qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n));
77
qdev_connect_gpio_out(splitter, 1,
78
qdev_get_gpio_in(extgicdev, irq_id - 32));
79
} else {
80
- s->irq_table[n] = is->int_combiner_irq[n];
81
+ s->irq_table[n] = qdev_get_gpio_in(intcdev, n);
82
}
83
}
84
/*
85
@@ -XXX,XX +XXX,XX @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
86
return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
39
}
87
}
40
88
41
/* Similarly for stores. */
89
-/*
42
-static void do_str(DisasContext *s, uint32_t vofs, uint32_t len,
90
- * Get Combiner input GPIO into irqs structure
43
- int rn, int imm)
91
- */
44
+static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
92
-static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs,
45
{
93
- DeviceState *dev, int ext)
46
- uint32_t len_align = QEMU_ALIGN_DOWN(len, 8);
94
-{
47
- uint32_t len_remain = len % 8;
95
- int n;
48
- uint32_t nparts = len / 8 + ctpop8(len_remain);
96
- int max;
49
+ int len_align = QEMU_ALIGN_DOWN(len, 8);
97
- qemu_irq *irq;
50
+ int len_remain = len % 8;
98
-
51
+ int nparts = len / 8 + ctpop8(len_remain);
99
- max = ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ :
52
int midx = get_mem_index(s);
100
- EXYNOS4210_MAX_INT_COMBINER_IN_IRQ;
53
TCGv_i64 addr, t0;
101
- irq = ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq;
54
102
-
103
- for (n = 0; n < max; n++) {
104
- irq[n] = qdev_get_gpio_in(dev, n);
105
- }
106
-}
107
-
108
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
109
0x09, 0x00, 0x00, 0x00 };
110
111
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
112
sysbus_connect_irq(busdev, n,
113
qdev_get_gpio_in(DEVICE(&s->a9mpcore), n));
114
}
115
- exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0);
116
sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR);
117
118
/* External Interrupt Combiner */
119
@@ -XXX,XX +XXX,XX @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
120
for (n = 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) {
121
sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic), n));
122
}
123
- exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1);
124
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
125
126
/* Initialize board IRQs. */
55
--
127
--
56
2.18.0
128
2.25.1
57
58
diff view generated by jsdifflib
1
From: Stefan Hajnoczi <stefanha@redhat.com>
1
From: Zongyuan Li <zongyuan.li@smartx.com>
2
2
3
The next patch will need to free a rom. There is already code to do
3
Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
4
this in rom_add_file().
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
5
Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com
6
Note that rom_add_file() uses:
7
8
rom = g_malloc0(sizeof(*rom));
9
...
10
if (rom->fw_dir) {
11
g_free(rom->fw_dir);
12
g_free(rom->fw_file);
13
}
14
15
The conditional is unnecessary since g_free(NULL) is a no-op.
16
17
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
18
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 20180814162739.11814-4-stefanha@redhat.com
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
---
7
---
23
hw/core/loader.c | 21 ++++++++++++---------
8
hw/arm/realview.c | 33 ++++++++++++++++++++++++---------
24
1 file changed, 12 insertions(+), 9 deletions(-)
9
1 file changed, 24 insertions(+), 9 deletions(-)
25
10
26
diff --git a/hw/core/loader.c b/hw/core/loader.c
11
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
27
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
28
--- a/hw/core/loader.c
13
--- a/hw/arm/realview.c
29
+++ b/hw/core/loader.c
14
+++ b/hw/arm/realview.c
30
@@ -XXX,XX +XXX,XX @@ struct Rom {
15
@@ -XXX,XX +XXX,XX @@
31
static FWCfgState *fw_cfg;
16
#include "hw/sysbus.h"
32
static QTAILQ_HEAD(, Rom) roms = QTAILQ_HEAD_INITIALIZER(roms);
17
#include "hw/arm/boot.h"
33
18
#include "hw/arm/primecell.h"
34
+/* rom->data must be heap-allocated (do not use with rom_add_elf_program()) */
19
+#include "hw/core/split-irq.h"
35
+static void rom_free(Rom *rom)
20
#include "hw/net/lan9118.h"
36
+{
21
#include "hw/net/smc91c111.h"
37
+ g_free(rom->data);
22
#include "hw/pci/pci.h"
38
+ g_free(rom->path);
23
+#include "hw/qdev-core.h"
39
+ g_free(rom->name);
24
#include "net/net.h"
40
+ g_free(rom->fw_dir);
25
#include "sysemu/sysemu.h"
41
+ g_free(rom->fw_file);
26
#include "hw/boards.h"
42
+ g_free(rom);
27
@@ -XXX,XX +XXX,XX @@ static const int realview_board_id[] = {
28
0x76d
29
};
30
31
+static void split_irq_from_named(DeviceState *src, const char* outname,
32
+ qemu_irq out1, qemu_irq out2) {
33
+ DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
34
+
35
+ qdev_prop_set_uint32(splitter, "num-lines", 2);
36
+
37
+ qdev_realize_and_unref(splitter, NULL, &error_fatal);
38
+
39
+ qdev_connect_gpio_out(splitter, 0, out1);
40
+ qdev_connect_gpio_out(splitter, 1, out2);
41
+ qdev_connect_gpio_out_named(src, outname, 0,
42
+ qdev_get_gpio_in(splitter, 0));
43
+}
43
+}
44
+
44
+
45
static inline bool rom_order_compare(Rom *rom, Rom *item)
45
static void realview_init(MachineState *machine,
46
enum realview_board_type board_type)
46
{
47
{
47
return ((uintptr_t)(void *)rom->as > (uintptr_t)(void *)item->as) ||
48
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
48
@@ -XXX,XX +XXX,XX @@ err:
49
DeviceState *dev, *sysctl, *gpio2, *pl041;
49
if (fd != -1)
50
SysBusDevice *busdev;
50
close(fd);
51
qemu_irq pic[64];
51
52
- qemu_irq mmc_irq[2];
52
- g_free(rom->data);
53
PCIBus *pci_bus = NULL;
53
- g_free(rom->path);
54
NICInfo *nd;
54
- g_free(rom->name);
55
DriveInfo *dinfo;
55
- if (fw_dir) {
56
@@ -XXX,XX +XXX,XX @@ static void realview_init(MachineState *machine,
56
- g_free(rom->fw_dir);
57
* and the PL061 has them the other way about. Also the card
57
- g_free(rom->fw_file);
58
* detect line is inverted.
58
- }
59
*/
59
- g_free(rom);
60
- mmc_irq[0] = qemu_irq_split(
60
-
61
- qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
61
+ rom_free(rom);
62
- qdev_get_gpio_in(gpio2, 1));
62
return -1;
63
- mmc_irq[1] = qemu_irq_split(
63
}
64
- qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
64
65
- qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
66
- qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]);
67
- qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]);
68
+ split_irq_from_named(dev, "card-read-only",
69
+ qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
70
+ qdev_get_gpio_in(gpio2, 1));
71
+
72
+ split_irq_from_named(dev, "card-inserted",
73
+ qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
74
+ qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
75
+
76
dinfo = drive_get(IF_SD, 0, 0);
77
if (dinfo) {
78
DeviceState *card;
65
--
79
--
66
2.18.0
80
2.25.1
67
68
diff view generated by jsdifflib
1
From: Stefan Hajnoczi <stefanha@redhat.com>
1
From: Zongyuan Li <zongyuan.li@smartx.com>
2
2
3
Some ARM CPUs have bitbanded IO, a memory region that allows convenient
3
Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
4
bit access via 32-bit memory loads/stores. This eliminates the need for
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
read-modify-update instruction sequences.
5
Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com
6
7
This patch makes this optional feature an ARMv7MState qdev property,
8
allowing boards to choose whether they want bitbanding or not.
9
10
Status of boards:
11
* iotkit (Cortex M33), no bitband
12
* mps2 (Cortex M3), bitband
13
* msf2 (Cortex M3), bitband
14
* stellaris (Cortex M3), bitband
15
* stm32f205 (Cortex M3), bitband
16
17
As a side-effect of this patch, Peter Maydell noted that the Ethernet
18
controller on mps2 board is now accessible. Previously they were hidden
19
by the bitband region (which does not exist on the real board).
20
21
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
22
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
23
Message-id: 20180814162739.11814-2-stefanha@redhat.com
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
---
7
---
26
include/hw/arm/armv7m.h | 2 ++
8
hw/arm/stellaris.c | 15 +++++++++++++--
27
hw/arm/armv7m.c | 37 ++++++++++++++++++++-----------------
9
1 file changed, 13 insertions(+), 2 deletions(-)
28
hw/arm/mps2.c | 1 +
29
hw/arm/msf2-soc.c | 1 +
30
hw/arm/stellaris.c | 1 +
31
hw/arm/stm32f205_soc.c | 1 +
32
6 files changed, 26 insertions(+), 17 deletions(-)
33
10
34
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/hw/arm/armv7m.h
37
+++ b/include/hw/arm/armv7m.h
38
@@ -XXX,XX +XXX,XX @@ typedef struct {
39
* devices will be automatically layered on top of this view.)
40
* + Property "idau": IDAU interface (forwarded to CPU object)
41
* + Property "init-svtor": secure VTOR reset value (forwarded to CPU object)
42
+ * + Property "enable-bitband": expose bitbanded IO
43
*/
44
typedef struct ARMv7MState {
45
/*< private >*/
46
@@ -XXX,XX +XXX,XX @@ typedef struct ARMv7MState {
47
MemoryRegion *board_memory;
48
Object *idau;
49
uint32_t init_svtor;
50
+ bool enable_bitband;
51
} ARMv7MState;
52
53
#endif
54
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/arm/armv7m.c
57
+++ b/hw/arm/armv7m.c
58
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
59
memory_region_add_subregion(&s->container, 0xe000e000,
60
sysbus_mmio_get_region(sbd, 0));
61
62
- for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
63
- Object *obj = OBJECT(&s->bitband[i]);
64
- SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
65
+ if (s->enable_bitband) {
66
+ for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
67
+ Object *obj = OBJECT(&s->bitband[i]);
68
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->bitband[i]);
69
70
- object_property_set_int(obj, bitband_input_addr[i], "base", &err);
71
- if (err != NULL) {
72
- error_propagate(errp, err);
73
- return;
74
- }
75
- object_property_set_link(obj, OBJECT(s->board_memory),
76
- "source-memory", &error_abort);
77
- object_property_set_bool(obj, true, "realized", &err);
78
- if (err != NULL) {
79
- error_propagate(errp, err);
80
- return;
81
- }
82
+ object_property_set_int(obj, bitband_input_addr[i], "base", &err);
83
+ if (err != NULL) {
84
+ error_propagate(errp, err);
85
+ return;
86
+ }
87
+ object_property_set_link(obj, OBJECT(s->board_memory),
88
+ "source-memory", &error_abort);
89
+ object_property_set_bool(obj, true, "realized", &err);
90
+ if (err != NULL) {
91
+ error_propagate(errp, err);
92
+ return;
93
+ }
94
95
- memory_region_add_subregion(&s->container, bitband_output_addr[i],
96
- sysbus_mmio_get_region(sbd, 0));
97
+ memory_region_add_subregion(&s->container, bitband_output_addr[i],
98
+ sysbus_mmio_get_region(sbd, 0));
99
+ }
100
}
101
}
102
103
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
104
MemoryRegion *),
105
DEFINE_PROP_LINK("idau", ARMv7MState, idau, TYPE_IDAU_INTERFACE, Object *),
106
DEFINE_PROP_UINT32("init-svtor", ARMv7MState, init_svtor, 0),
107
+ DEFINE_PROP_BOOL("enable-bitband", ARMv7MState, enable_bitband, false),
108
DEFINE_PROP_END_OF_LIST(),
109
};
110
111
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
112
index XXXXXXX..XXXXXXX 100644
113
--- a/hw/arm/mps2.c
114
+++ b/hw/arm/mps2.c
115
@@ -XXX,XX +XXX,XX @@ static void mps2_common_init(MachineState *machine)
116
g_assert_not_reached();
117
}
118
qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type);
119
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
120
object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),
121
"memory", &error_abort);
122
object_property_set_bool(OBJECT(&mms->armv7m), true, "realized",
123
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/hw/arm/msf2-soc.c
126
+++ b/hw/arm/msf2-soc.c
127
@@ -XXX,XX +XXX,XX @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
128
armv7m = DEVICE(&s->armv7m);
129
qdev_prop_set_uint32(armv7m, "num-irq", 81);
130
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
131
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
132
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
133
"memory", &error_abort);
134
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
135
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
11
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
136
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
137
--- a/hw/arm/stellaris.c
13
--- a/hw/arm/stellaris.c
138
+++ b/hw/arm/stellaris.c
14
+++ b/hw/arm/stellaris.c
15
@@ -XXX,XX +XXX,XX @@
16
17
#include "qemu/osdep.h"
18
#include "qapi/error.h"
19
+#include "hw/core/split-irq.h"
20
#include "hw/sysbus.h"
21
#include "hw/sd/sd.h"
22
#include "hw/ssi/ssi.h"
139
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
23
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
140
nvic = qdev_create(NULL, TYPE_ARMV7M);
24
DeviceState *ssddev;
141
qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES);
25
DriveInfo *dinfo;
142
qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type);
26
DeviceState *carddev;
143
+ qdev_prop_set_bit(nvic, "enable-bitband", true);
27
+ DeviceState *gpio_d_splitter;
144
object_property_set_link(OBJECT(nvic), OBJECT(get_system_memory()),
28
BlockBackend *blk;
145
"memory", &error_abort);
29
146
/* This will exit with an error if the user passed us a bad cpu_type */
30
/*
147
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
31
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
148
index XXXXXXX..XXXXXXX 100644
32
&error_fatal);
149
--- a/hw/arm/stm32f205_soc.c
33
150
+++ b/hw/arm/stm32f205_soc.c
34
ssddev = ssi_create_peripheral(bus, "ssd0323");
151
@@ -XXX,XX +XXX,XX @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
35
- gpio_out[GPIO_D][0] = qemu_irq_split(
152
armv7m = DEVICE(&s->armv7m);
36
- qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0),
153
qdev_prop_set_uint32(armv7m, "num-irq", 96);
37
+
154
qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
38
+ gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ);
155
+ qdev_prop_set_bit(armv7m, "enable-bitband", true);
39
+ qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2);
156
object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
40
+ qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal);
157
"memory", &error_abort);
41
+ qdev_connect_gpio_out(
158
object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
42
+ gpio_d_splitter, 0,
43
+ qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0));
44
+ qdev_connect_gpio_out(
45
+ gpio_d_splitter, 1,
46
qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0));
47
+ gpio_out[GPIO_D][0] = qdev_get_gpio_in(gpio_d_splitter, 0);
48
+
49
gpio_out[GPIO_C][7] = qdev_get_gpio_in(ssddev, 0);
50
51
/* Make sure the select pin is high. */
159
--
52
--
160
2.18.0
53
2.25.1
161
162
diff view generated by jsdifflib
1
From: Thomas Huth <thuth@redhat.com>
1
From: Zongyuan Li <zongyuan.li@smartx.com>
2
2
3
Now that we've got the common sysbus_init_child_obj() function, we do
3
Signed-off-by: Zongyuan Li <zongyuan.li@smartx.com>
4
not need the local init_sysbus_child() anymore.
5
6
Signed-off-by: Thomas Huth <thuth@redhat.com>
7
Message-id: 1534420566-15799-1-git-send-email-thuth@redhat.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
8
---
11
hw/arm/mps2-tz.c | 32 +++++++++++---------------------
9
include/hw/irq.h | 5 -----
12
1 file changed, 11 insertions(+), 21 deletions(-)
10
hw/core/irq.c | 15 ---------------
11
2 files changed, 20 deletions(-)
13
12
14
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
13
diff --git a/include/hw/irq.h b/include/hw/irq.h
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/mps2-tz.c
15
--- a/include/hw/irq.h
17
+++ b/hw/arm/mps2-tz.c
16
+++ b/include/hw/irq.h
18
@@ -XXX,XX +XXX,XX @@ static void make_ram_alias(MemoryRegion *mr, const char *name,
17
@@ -XXX,XX +XXX,XX @@ void qemu_free_irq(qemu_irq irq);
19
memory_region_add_subregion(get_system_memory(), base, mr);
18
/* Returns a new IRQ with opposite polarity. */
19
qemu_irq qemu_irq_invert(qemu_irq irq);
20
21
-/* Returns a new IRQ which feeds into both the passed IRQs.
22
- * It's probably better to use the TYPE_SPLIT_IRQ device instead.
23
- */
24
-qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
25
-
26
/* For internal use in qtest. Similar to qemu_irq_split, but operating
27
on an existing vector of qemu_irq. */
28
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
29
diff --git a/hw/core/irq.c b/hw/core/irq.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/core/irq.c
32
+++ b/hw/core/irq.c
33
@@ -XXX,XX +XXX,XX @@ qemu_irq qemu_irq_invert(qemu_irq irq)
34
return qemu_allocate_irq(qemu_notirq, irq, 0);
20
}
35
}
21
36
22
-static void init_sysbus_child(Object *parent, const char *childname,
37
-static void qemu_splitirq(void *opaque, int line, int level)
23
- void *child, size_t childsize,
24
- const char *childtype)
25
-{
38
-{
26
- object_initialize(child, childsize, childtype);
39
- struct IRQState **irq = opaque;
27
- object_property_add_child(parent, childname, OBJECT(child), &error_abort);
40
- irq[0]->handler(irq[0]->opaque, irq[0]->n, level);
28
- qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
41
- irq[1]->handler(irq[1]->opaque, irq[1]->n, level);
29
-
30
-}
42
-}
31
-
43
-
32
/* Most of the devices in the AN505 FPGA image sit behind
44
-qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
33
* Peripheral Protection Controllers. These data structures
45
-{
34
* define the layout of which devices sit behind which PPCs.
46
- qemu_irq *s = g_new0(qemu_irq, 2);
35
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms,
47
- s[0] = irq1;
36
*/
48
- s[1] = irq2;
37
UnimplementedDeviceState *uds = opaque;
49
- return qemu_allocate_irq(qemu_splitirq, s, 0);
38
50
-}
39
- init_sysbus_child(OBJECT(mms), name, uds,
51
-
40
- sizeof(UnimplementedDeviceState),
52
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
41
- TYPE_UNIMPLEMENTED_DEVICE);
53
{
42
+ sysbus_init_child_obj(OBJECT(mms), name, uds,
54
int i;
43
+ sizeof(UnimplementedDeviceState),
44
+ TYPE_UNIMPLEMENTED_DEVICE);
45
qdev_prop_set_string(DEVICE(uds), "name", name);
46
qdev_prop_set_uint64(DEVICE(uds), "size", size);
47
object_property_set_bool(OBJECT(uds), true, "realized", &error_fatal);
48
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque,
49
DeviceState *iotkitdev = DEVICE(&mms->iotkit);
50
DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate);
51
52
- init_sysbus_child(OBJECT(mms), name, uart,
53
- sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART);
54
+ sysbus_init_child_obj(OBJECT(mms), name, uart, sizeof(mms->uart[0]),
55
+ TYPE_CMSDK_APB_UART);
56
qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i));
57
qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ);
58
object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal);
59
@@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque,
60
61
memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal);
62
63
- init_sysbus_child(OBJECT(mms), mpcname, mpc,
64
- sizeof(mms->ssram_mpc[0]), TYPE_TZ_MPC);
65
+ sysbus_init_child_obj(OBJECT(mms), mpcname, mpc, sizeof(mms->ssram_mpc[0]),
66
+ TYPE_TZ_MPC);
67
object_property_set_link(OBJECT(mpc), OBJECT(ssram),
68
"downstream", &error_fatal);
69
object_property_set_bool(OBJECT(mpc), true, "realized", &error_fatal);
70
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
71
exit(1);
72
}
73
74
- init_sysbus_child(OBJECT(machine), "iotkit", &mms->iotkit,
75
- sizeof(mms->iotkit), TYPE_IOTKIT);
76
+ sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit,
77
+ sizeof(mms->iotkit), TYPE_IOTKIT);
78
iotkitdev = DEVICE(&mms->iotkit);
79
object_property_set_link(OBJECT(&mms->iotkit), OBJECT(system_memory),
80
"memory", &error_abort);
81
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
82
int port;
83
char *gpioname;
84
85
- init_sysbus_child(OBJECT(machine), ppcinfo->name, ppc,
86
- sizeof(TZPPC), TYPE_TZ_PPC);
87
+ sysbus_init_child_obj(OBJECT(machine), ppcinfo->name, ppc,
88
+ sizeof(TZPPC), TYPE_TZ_PPC);
89
ppcdev = DEVICE(ppc);
90
91
for (port = 0; port < TZ_NUM_PORTS; port++) {
92
--
55
--
93
2.18.0
56
2.25.1
94
95
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2
2
3
We were using the wrong flush-to-zero bit for the non-half input.
3
Describe that the gic-version influences the maximum number of CPUs.
4
4
5
Fixes: 46d33d1e3c9
5
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
6
Cc: qemu-stable@nongnu.org (3.0.1)
6
Message-id: 20220413231456.35811-1-heinrich.schuchardt@canonical.com
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
7
[PMM: minor punctuation tweaks]
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20180810193129.1556-5-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
10
---
14
target/arm/translate-sve.c | 4 ++--
11
docs/system/arm/virt.rst | 4 ++--
15
1 file changed, 2 insertions(+), 2 deletions(-)
12
1 file changed, 2 insertions(+), 2 deletions(-)
16
13
17
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-sve.c
16
--- a/docs/system/arm/virt.rst
20
+++ b/target/arm/translate-sve.c
17
+++ b/docs/system/arm/virt.rst
21
@@ -XXX,XX +XXX,XX @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
18
@@ -XXX,XX +XXX,XX @@ gic-version
22
19
Valid values are:
23
static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
20
24
{
21
``2``
25
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh);
22
- GICv2
26
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh);
23
+ GICv2. Note that this limits the number of CPUs to 8.
27
}
24
``3``
28
25
- GICv3
29
static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
26
+ GICv3. This allows up to 512 CPUs.
30
@@ -XXX,XX +XXX,XX @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
27
``host``
31
28
Use the same GIC version the host provides, when using KVM
32
static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
29
``max``
33
{
34
- return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh);
35
+ return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh);
36
}
37
38
static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
39
--
30
--
40
2.18.0
31
2.25.1
41
42
diff view generated by jsdifflib
1
From: Trent Piepho <tpiepho@impinj.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
The current emulation will clear the XCH bit when a burst finishes.
3
Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
4
This is not quite correct. According to the i.MX7d referemce manual,
4
the PWRON STRAP fields in their corresponding module for NPCM7XX.
5
Rev 0.1, §10.1.7.3:
6
5
7
This bit [XCH] is cleared automatically when all data in the TXFIFO
6
Signed-off-by: Hao Wu <wuhaotsh@google.com>
8
and the shift register has been shifted out.
7
Reviewed-by: Patrick Venture <venture@google.com>
9
8
Message-id: 20220411165842.3912945-2-wuhaotsh@google.com
10
So XCH should be cleared when the FIFO empties, not on completion of a
11
burst. The FIFO is 64 x 32 bits = 2048 bits, while the max burst size
12
is larger at 4096 bits. So it's possible that the burst is not finished
13
after the TXFIFO empties.
14
15
Sending a large block (> 2048 bits) with the Linux driver will use a
16
burst that is larger than the TXFIFO. After the TXFIFO has emptied XCH
17
does not become unset, as the burst is not yet finished.
18
19
What should happen after the TXFIFO empties is the driver will refill it
20
and set XCH. The rising edge of XCH will trigger another transfer to
21
begin. However, since the emulation does not set XCH to 0, there is no
22
rising edge and the next trasfer never begins.
23
24
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
25
Message-id: 20180731201056.29257-1-tpiepho@impinj.com
26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
28
---
11
---
29
hw/ssi/imx_spi.c | 3 +--
12
include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++
30
1 file changed, 1 insertion(+), 2 deletions(-)
13
1 file changed, 30 insertions(+)
31
14
32
diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c
15
diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h
33
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/ssi/imx_spi.c
17
--- a/include/hw/misc/npcm7xx_gcr.h
35
+++ b/hw/ssi/imx_spi.c
18
+++ b/include/hw/misc/npcm7xx_gcr.h
36
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
19
@@ -XXX,XX +XXX,XX @@
37
}
20
#include "exec/memory.h"
38
21
#include "hw/sysbus.h"
39
if (s->burst_length <= 0) {
22
40
- s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
23
+/*
41
-
24
+ * NPCM7XX PWRON STRAP bit fields
42
if (!imx_spi_is_multiple_master_burst(s)) {
25
+ * 12: SPI0 powered by VSBV3 at 1.8V
43
s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
26
+ * 11: System flash attached to BMC
44
break;
27
+ * 10: BSP alternative pins.
45
@@ -XXX,XX +XXX,XX @@ static void imx_spi_flush_txfifo(IMXSPIState *s)
28
+ * 9:8: Flash UART command route enabled.
46
29
+ * 7: Security enabled.
47
if (fifo32_is_empty(&s->tx_fifo)) {
30
+ * 6: HI-Z state control.
48
s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
31
+ * 5: ECC disabled.
49
+ s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
32
+ * 4: Reserved
50
}
33
+ * 3: JTAG2 enabled.
51
34
+ * 2:0: CPU and DRAM clock frequency.
52
/* TODO: We should also use TDR and RDR bits */
35
+ */
36
+#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12)
37
+#define NPCM7XX_PWRON_STRAP_SFAB BIT(11)
38
+#define NPCM7XX_PWRON_STRAP_BSPA BIT(10)
39
+#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8)
40
+#define FUP_NORM_UART2 3
41
+#define FUP_PROG_UART3 2
42
+#define FUP_PROG_UART2 1
43
+#define FUP_NORM_UART3 0
44
+#define NPCM7XX_PWRON_STRAP_SECEN BIT(7)
45
+#define NPCM7XX_PWRON_STRAP_HIZ BIT(6)
46
+#define NPCM7XX_PWRON_STRAP_ECC BIT(5)
47
+#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4)
48
+#define NPCM7XX_PWRON_STRAP_J2EN BIT(3)
49
+#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x)
50
+#define CKFRQ_SKIPINIT 0x000
51
+#define CKFRQ_DEFAULT 0x111
52
+
53
/*
54
* Number of registers in our device state structure. Don't change this without
55
* incrementing the version_id in the vmstate.
53
--
56
--
54
2.18.0
57
2.25.1
55
56
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
The immediate should be scaled by the size of the memory reference,
3
This patch uses the defined fields to describe PWRON STRAPs for
4
not the size of the elements into which it is loaded.
4
better readability.
5
5
6
Cc: qemu-stable@nongnu.org (3.0.1)
6
Signed-off-by: Hao Wu <wuhaotsh@google.com>
7
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
7
Reviewed-by: Patrick Venture <venture@google.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20220411165842.3912945-3-wuhaotsh@google.com
9
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
target/arm/translate-sve.c | 3 ++-
12
hw/arm/npcm7xx_boards.c | 24 +++++++++++++++++++-----
14
1 file changed, 2 insertions(+), 1 deletion(-)
13
1 file changed, 19 insertions(+), 5 deletions(-)
15
14
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-sve.c
17
--- a/hw/arm/npcm7xx_boards.c
19
+++ b/target/arm/translate-sve.c
18
+++ b/hw/arm/npcm7xx_boards.c
20
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@
21
unsigned vsz = vec_full_reg_size(s);
20
#include "sysemu/sysemu.h"
22
unsigned psz = pred_full_reg_size(s);
21
#include "sysemu/block-backend.h"
23
unsigned esz = dtype_esz[a->dtype];
22
24
+ unsigned msz = dtype_msz(a->dtype);
23
-#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7
25
TCGLabel *over = gen_new_label();
24
-#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff
26
TCGv_i64 temp;
25
-#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff
27
26
-#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff
28
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn)
27
-#define MORI_BMC_POWER_ON_STRAPS 0x00001fff
29
28
+#define NPCM7XX_POWER_ON_STRAPS_DEFAULT ( \
30
/* Load the data. */
29
+ NPCM7XX_PWRON_STRAP_SPI0F18 | \
31
temp = tcg_temp_new_i64();
30
+ NPCM7XX_PWRON_STRAP_SFAB | \
32
- tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz);
31
+ NPCM7XX_PWRON_STRAP_BSPA | \
33
+ tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz);
32
+ NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) | \
34
tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s),
33
+ NPCM7XX_PWRON_STRAP_SECEN | \
35
s->be_data | dtype_mop[a->dtype]);
34
+ NPCM7XX_PWRON_STRAP_HIZ | \
35
+ NPCM7XX_PWRON_STRAP_ECC | \
36
+ NPCM7XX_PWRON_STRAP_RESERVE1 | \
37
+ NPCM7XX_PWRON_STRAP_J2EN | \
38
+ NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT))
39
+
40
+#define NPCM750_EVB_POWER_ON_STRAPS ( \
41
+ NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN)
42
+#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
43
+#define QUANTA_GBS_POWER_ON_STRAPS ( \
44
+ NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB)
45
+#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
46
+#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT
47
48
static const char npcm7xx_default_bootrom[] = "npcm7xx_bootrom.bin";
36
49
37
--
50
--
38
2.18.0
51
2.25.1
39
40
diff view generated by jsdifflib