target/openrisc: Fix writes to interrupt mask register

[Qemu-devel] [PATCH] target/openrisc: Fix writes to interrupt mask register

Stafford Horne posted 1 patch 7 years, 4 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20180701081245.14357-1-shorne@gmail.com

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target/openrisc/sys_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

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[Qemu-devel] [PATCH] target/openrisc: Fix writes to interrupt mask register

Posted by Stafford Horne 7 years, 4 months ago

The interrupt controller mask register (PICMR) allows writing any value
to any of the 32 interrupt mask bits.  Writing a 0 masks the interrupt
writing a 1 unmasks (enables) the the interrupt.

For some reason the old code was or'ing the write values to the PICMR
meaning it was not possible to ever mask a interrupt once it was
enabled.

I have tested this by running linux 4.18 and my regular checks, I don't
see any issues.

Reported-by: Davidson Francis <davidsondfgl@gmail.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 target/openrisc/sys_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 541615bfb3..b66a45c1e0 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -142,7 +142,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
         }
         break;
     case TO_SPR(9, 0):  /* PICMR */
-        env->picmr |= rb;
+        env->picmr = rb;
         break;
     case TO_SPR(9, 2):  /* PICSR */
         env->picsr &= ~rb;
-- 
2.17.0

Re: [Qemu-devel] [PATCH] target/openrisc: Fix writes to interrupt mask register

Posted by Richard Henderson 7 years, 4 months ago

On 07/01/2018 01:12 AM, Stafford Horne wrote:
> The interrupt controller mask register (PICMR) allows writing any value
> to any of the 32 interrupt mask bits.  Writing a 0 masks the interrupt
> writing a 1 unmasks (enables) the the interrupt.
> 
> For some reason the old code was or'ing the write values to the PICMR
> meaning it was not possible to ever mask a interrupt once it was
> enabled.
> 
> I have tested this by running linux 4.18 and my regular checks, I don't
> see any issues.
> 
> Reported-by: Davidson Francis <davidsondfgl@gmail.com>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>  target/openrisc/sys_helper.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~