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[124.44.6.90]) by smtp.gmail.com with ESMTPSA id e189-v6sm4209075pfe.52.2018.07.01.01.12.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 01 Jul 2018 01:12:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=aiqhQs8WYnU+ERnMFSkODTYaMwM3d8ruWvQEbizV+us=; b=AHPNThM5aDH18K6X3FJzbakJtdiRY9qohC5tr0IWuOFvr692MzLicoqcKcgBAZujUk IXJowgyG44BlFTD8Jtu8TUVfBGN5o1C6BDRubgIGfMKLAtjFPFkpR/M7NcjxsD1UfLIv NlpCwaBkpLTHRL/ZwzzeVqH38KG9XveHmrvboAb9GWB/GIvfsnvUKXhkPz2haqGZ+EYA 8Rb+22jCzzU37106LKg6ZaajbABQtIPNujsxWa97BIWPCNmQRVoid9i8JR4yuy4a8DQ1 4XEgFxoCT3TSkE9gOUTmJw8VEfo4v2UYnwwYZ7XGGeqlDhJBEprdlKGUUIBmIm11zp15 gAwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=aiqhQs8WYnU+ERnMFSkODTYaMwM3d8ruWvQEbizV+us=; b=ONbnEKNUUKcPtMd8fXzGM/Ct7jlkOL/5zrBAEwy4CgqXR2I7KMlDq5Ow2a5mpa1PtJ hbRO/rmPPgT3zr8s/L0cQjH5ImLbPqWk93xqq0iBMD1hvpCAUpPn50zuTcTyaPc7+nRf spuErSYP+YU07m6m2kJmvIRtN5eXQXLy0ZLIdCxyy6PZk6bc0Hvwt7tPkV+9NRhU6kaX 1sng8/PN2X6vFVPwUdaiYtn/pt8ktSdvAIVPL15XECeJdVwHAeUPjnqfj65HSavw+x+n xViZ0rS/oFWaFIISnbcyv9a2t1SPcGqW+1f3oAd8eOCDFfwaHps62anGTdNFPrp0nLge ZRPw== X-Gm-Message-State: APt69E0UBEgczMYPJAAe6eOoCa783EL+Ab35rrHrh/pf0NYGicBIptSS BYSRRE/QVvE/FB+v3LhqhVrbMH9I X-Google-Smtp-Source: ADUXVKKed0M5wdZUwFViFhPDqErNCUzeKrL0kg7mdlXQhpGnpmuSMWPGJm8UjT63KHvRImdIrasa8w== X-Received: by 2002:a63:8c5:: with SMTP id 188-v6mr17681715pgi.97.1530432772353; Sun, 01 Jul 2018 01:12:52 -0700 (PDT) From: Stafford Horne To: QEMU Development Date: Sun, 1 Jul 2018 17:12:45 +0900 Message-Id: <20180701081245.14357-1-shorne@gmail.com> X-Mailer: git-send-email 2.17.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH] target/openrisc: Fix writes to interrupt mask register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: davidsondfgl@gmail.com, Stafford Horne , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The interrupt controller mask register (PICMR) allows writing any value to any of the 32 interrupt mask bits. Writing a 0 masks the interrupt writing a 1 unmasks (enables) the the interrupt. For some reason the old code was or'ing the write values to the PICMR meaning it was not possible to ever mask a interrupt once it was enabled. I have tested this by running linux 4.18 and my regular checks, I don't see any issues. Reported-by: Davidson Francis Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- target/openrisc/sys_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 541615bfb3..b66a45c1e0 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -142,7 +142,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong = spr, target_ulong rb) } break; case TO_SPR(9, 0): /* PICMR */ - env->picmr |=3D rb; + env->picmr =3D rb; break; case TO_SPR(9, 2): /* PICSR */ env->picsr &=3D ~rb; --=20 2.17.0