[Qemu-devel] [PULL 00/16] target-arm queue
[PULL 00/24] target-arm queue
1
The following changes since commit ad1b4ec39caa5b3f17cbd8160283a03a3dcfe2ae:
1
Hi; here's the latest round of arm patches. I have included also
2
my patchset for the RTC devices to avoid keeping time_t and
3
time_t diffs in 32-bit variables.
2
4
3
Merge remote-tracking branch 'remotes/kraxel/tags/input-20180515-pull-request' into staging (2018-05-15 12:50:06 +0100)
5
thanks
6
-- PMM
7
8
The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:
9
10
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)
4
11
5
are available in the Git repository at:
12
are available in the Git repository at:
6
13
7
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180515
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831
8
15
9
for you to fetch changes up to ae7651804748c6b479d5ae09aeac4edb9c44f76e:
16
for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:
10
17
11
tcg: Optionally log FPU state in TCG -d cpu logging (2018-05-15 14:58:44 +0100)
18
hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
target-arm queue:
21
target-arm queue:
15
* Fix coverity nit in int_to_float code
22
* Some of the preliminary patches for Cortex-A710 support
16
* Don't set Invalid for float-to-int(MAXINT)
23
* i.MX7 and i.MX6UL refactoring
17
* Fix fp_status_f16 tininess before rounding
24
* Implement SRC device for i.MX7
18
* Add various missing insns from the v8.2-FP16 extension
25
* Catch illegal-exception-return from EL3 with bad NSE/NS
19
* Fix sqrt_f16 exception raising
26
* Use 64-bit offsets for holding time_t differences in RTC devices
20
* sdcard: Correct CRC16 offset in sd_function_switch()
27
* Model correct number of MPU regions for an505, an521, an524 boards
21
* tcg: Optionally log FPU state in TCG -d cpu logging
22
28
23
----------------------------------------------------------------
29
----------------------------------------------------------------
24
Alex Bennée (5):
30
Alex Bennée (1):
25
fpu/softfloat: int_to_float ensure r fully initialised
31
target/arm: properly document FEAT_CRC32
26
target/arm: Implement FCMP for fp16
27
target/arm: Implement FCSEL for fp16
28
target/arm: Implement FMOV (immediate) for fp16
29
target/arm: Fix sqrt_f16 exception raising
30
32
31
Peter Maydell (3):
33
Jean-Christophe Dubois (6):
32
fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
34
Remove i.MX7 IOMUX GPR device from i.MX6UL
33
target/arm: Fix fp_status_f16 tininess before rounding
35
Refactor i.MX6UL processor code
34
tcg: Optionally log FPU state in TCG -d cpu logging
36
Add i.MX6UL missing devices.
37
Refactor i.MX7 processor code
38
Add i.MX7 missing TZ devices and memory regions
39
Add i.MX7 SRC device implementation
35
40
36
Philippe Mathieu-Daudé (1):
41
Peter Maydell (8):
37
sdcard: Correct CRC16 offset in sd_function_switch()
42
target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
43
hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
44
hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
45
hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
46
rtc: Use time_t for passing and returning time offsets
47
target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
48
hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
49
hw/arm: Set number of MPU regions correctly for an505, an521, an524
38
50
39
Richard Henderson (7):
51
Richard Henderson (9):
40
target/arm: Implement FMOV (general) for fp16
52
target/arm: Reduce dcz_blocksize to uint8_t
41
target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
53
target/arm: Allow cpu to configure GM blocksize
42
target/arm: Implement FCVT (scalar, integer) for fp16
54
target/arm: Support more GM blocksizes
43
target/arm: Implement FCVT (scalar, fixed-point) for fp16
55
target/arm: When tag memory is not present, set MTE=1
44
target/arm: Introduce and use read_fp_hreg
56
target/arm: Introduce make_ccsidr64
45
target/arm: Implement FP data-processing (2 source) for fp16
57
target/arm: Apply access checks to neoverse-n1 special registers
46
target/arm: Implement FP data-processing (3 source) for fp16
58
target/arm: Apply access checks to neoverse-v1 special registers
59
target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
60
target/arm: Implement FEAT_HPDS2 as a no-op
47
61
48
include/qemu/log.h | 1 +
62
docs/system/arm/emulation.rst | 2 +
49
target/arm/helper-a64.h | 2 +
63
include/hw/arm/armsse.h | 5 +
50
target/arm/helper.h | 6 +
64
include/hw/arm/armv7m.h | 8 +
51
accel/tcg/cpu-exec.c | 9 +-
65
include/hw/arm/fsl-imx6ul.h | 158 ++++++++++++++++---
52
fpu/softfloat.c | 6 +-
66
include/hw/arm/fsl-imx7.h | 338 ++++++++++++++++++++++++++++++-----------
53
hw/sd/sd.c | 2 +-
67
include/hw/misc/imx7_src.h | 66 ++++++++
54
target/arm/cpu.c | 2 +
68
include/hw/rtc/aspeed_rtc.h | 2 +-
55
target/arm/helper-a64.c | 10 ++
69
include/sysemu/rtc.h | 4 +-
56
target/arm/helper.c | 38 +++-
70
target/arm/cpregs.h | 2 +
57
target/arm/translate-a64.c | 421 ++++++++++++++++++++++++++++++++++++++-------
71
target/arm/cpu.h | 5 +-
58
util/log.c | 2 +
72
target/arm/internals.h | 6 -
59
11 files changed, 428 insertions(+), 71 deletions(-)
73
target/arm/tcg/translate.h | 2 +
74
hw/arm/armsse.c | 16 ++
75
hw/arm/armv7m.c | 21 +++
76
hw/arm/fsl-imx6ul.c | 174 +++++++++++++--------
77
hw/arm/fsl-imx7.c | 201 +++++++++++++++++++-----
78
hw/arm/mps2-tz.c | 29 ++++
79
hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++
80
hw/rtc/aspeed_rtc.c | 5 +-
81
hw/rtc/m48t59.c | 2 +-
82
hw/rtc/twl92230.c | 4 +-
83
softmmu/rtc.c | 4 +-
84
target/arm/cpu.c | 207 ++++++++++++++-----------
85
target/arm/helper.c | 15 +-
86
target/arm/tcg/cpu32.c | 2 +-
87
target/arm/tcg/cpu64.c | 102 +++++++++----
88
target/arm/tcg/helper-a64.c | 9 ++
89
target/arm/tcg/mte_helper.c | 90 ++++++++---
90
target/arm/tcg/translate-a64.c | 5 +-
91
hw/misc/meson.build | 1 +
92
hw/misc/trace-events | 4 +
93
31 files changed, 1393 insertions(+), 372 deletions(-)
94
create mode 100644 include/hw/misc/imx7_src.h
95
create mode 100644 hw/misc/imx7_src.c
60
96
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16
[PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Adding the fp16 moves to/from general registers.
3
This value is only 4 bits wide.
4
4
5
Cc: qemu-stable@nongnu.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20180512003217.9105-2-richard.henderson@linaro.org
8
Message-id: 20230811214031.171020-2-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/translate-a64.c | 21 +++++++++++++++++++++
11
target/arm/cpu.h | 3 ++-
13
1 file changed, 21 insertions(+)
12
1 file changed, 2 insertions(+), 1 deletion(-)
14
13
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
16
--- a/target/arm/cpu.h
18
+++ b/target/arm/translate-a64.c
17
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
18
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
20
tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
19
bool prop_lpa2;
21
clear_vec_high(s, true, rd);
20
22
break;
21
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
23
+ case 3:
22
- uint32_t dcz_blocksize;
24
+ /* 16 bit */
23
+ uint8_t dcz_blocksize;
25
+ tmp = tcg_temp_new_i64();
24
+
26
+ tcg_gen_ext16u_i64(tmp, tcg_rn);
25
uint64_t rvbar_prop; /* Property/input signals. */
27
+ write_fp_dreg(s, rd, tmp);
26
28
+ tcg_temp_free_i64(tmp);
27
/* Configurable aspects of GIC cpu interface (which is part of the CPU) */
29
+ break;
30
+ default:
31
+ g_assert_not_reached();
32
}
33
} else {
34
TCGv_i64 tcg_rd = cpu_reg(s, rd);
35
@@ -XXX,XX +XXX,XX @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
36
/* 64 bits from top half */
37
tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
38
break;
39
+ case 3:
40
+ /* 16 bit */
41
+ tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
42
+ break;
43
+ default:
44
+ g_assert_not_reached();
45
}
46
}
47
}
48
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
49
case 0xa: /* 64 bit */
50
case 0xd: /* 64 bit to top half of quad */
51
break;
52
+ case 0x6: /* 16-bit float, 32-bit int */
53
+ case 0xe: /* 16-bit float, 64-bit int */
54
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
55
+ break;
56
+ }
57
+ /* fallthru */
58
default:
59
/* all other sf/type/rmode combinations are invalid */
60
unallocated_encoding(s);
61
--
28
--
62
2.17.0
29
2.34.1
63
30
64
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16
[PULL 02/24] target/arm: Allow cpu to configure GM blocksize
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We missed all of the scalar fp16 binary operations.
3
Previously we hard-coded the blocksize with GMID_EL1_BS.
4
4
But the value we choose for -cpu max does not match the
5
Cc: qemu-stable@nongnu.org
5
value that cortex-a710 uses.
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
7
Mirror the way we handle dcz_blocksize.
8
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
9
Message-id: 20180512003217.9105-7-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
14
target/arm/cpu.h | 2 ++
13
1 file changed, 65 insertions(+)
15
target/arm/internals.h | 6 -----
14
16
target/arm/tcg/translate.h | 2 ++
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
target/arm/helper.c | 11 +++++---
16
index XXXXXXX..XXXXXXX 100644
18
target/arm/tcg/cpu64.c | 1 +
17
--- a/target/arm/translate-a64.c
19
target/arm/tcg/mte_helper.c | 46 ++++++++++++++++++++++------------
18
+++ b/target/arm/translate-a64.c
20
target/arm/tcg/translate-a64.c | 5 ++--
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
21
7 files changed, 45 insertions(+), 28 deletions(-)
20
tcg_temp_free_i64(tcg_res);
22
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.h
26
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
28
29
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
30
uint8_t dcz_blocksize;
31
+ /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
32
+ uint8_t gm_blocksize;
33
34
uint64_t rvbar_prop; /* Property/input signals. */
35
36
diff --git a/target/arm/internals.h b/target/arm/internals.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/internals.h
39
+++ b/target/arm/internals.h
40
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
41
42
#endif /* !CONFIG_USER_ONLY */
43
44
-/*
45
- * The log2 of the words in the tag block, for GMID_EL1.BS.
46
- * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
47
- */
48
-#define GMID_EL1_BS 6
49
-
50
/*
51
* SVE predicates are 1/8 the size of SVE vectors, and cannot use
52
* the same simd_desc() encoding due to restrictions on size.
53
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
54
index XXXXXXX..XXXXXXX 100644
55
--- a/target/arm/tcg/translate.h
56
+++ b/target/arm/tcg/translate.h
57
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
58
int8_t btype;
59
/* A copy of cpu->dcz_blocksize. */
60
uint8_t dcz_blocksize;
61
+ /* A copy of cpu->gm_blocksize. */
62
+ uint8_t gm_blocksize;
63
/* True if this page is guarded. */
64
bool guarded_page;
65
/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
66
diff --git a/target/arm/helper.c b/target/arm/helper.c
67
index XXXXXXX..XXXXXXX 100644
68
--- a/target/arm/helper.c
69
+++ b/target/arm/helper.c
70
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
71
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
72
.access = PL1_RW, .accessfn = access_mte,
73
.fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
74
- { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
75
- .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
76
- .access = PL1_R, .accessfn = access_aa64_tid5,
77
- .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
78
{ .name = "TCO", .state = ARM_CP_STATE_AA64,
79
.opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
80
.type = ARM_CP_NO_RAW,
81
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
82
* then define only a RAZ/WI version of PSTATE.TCO.
83
*/
84
if (cpu_isar_feature(aa64_mte, cpu)) {
85
+ ARMCPRegInfo gmid_reginfo = {
86
+ .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
87
+ .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
88
+ .access = PL1_R, .accessfn = access_aa64_tid5,
89
+ .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
90
+ };
91
+ define_one_arm_cp_reg(cpu, &gmid_reginfo);
92
define_arm_cp_regs(cpu, mte_reginfo);
93
define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
94
} else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
95
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
96
index XXXXXXX..XXXXXXX 100644
97
--- a/target/arm/tcg/cpu64.c
98
+++ b/target/arm/tcg/cpu64.c
99
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
100
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
101
cpu->dcz_blocksize = 7; /* 512 bytes */
102
#endif
103
+ cpu->gm_blocksize = 6; /* 256 bytes */
104
105
cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
106
cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
107
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/tcg/mte_helper.c
110
+++ b/target/arm/tcg/mte_helper.c
111
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
112
}
21
}
113
}
22
114
23
+/* Floating-point data-processing (2 source) - half precision */
115
-#define LDGM_STGM_SIZE (4 << GMID_EL1_BS)
24
+static void handle_fp_2src_half(DisasContext *s, int opcode,
116
-
25
+ int rd, int rn, int rm)
117
uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
26
+{
118
{
27
+ TCGv_i32 tcg_op1;
119
int mmu_idx = cpu_mmu_index(env, false);
28
+ TCGv_i32 tcg_op2;
120
uintptr_t ra = GETPC();
29
+ TCGv_i32 tcg_res;
121
+ int gm_bs = env_archcpu(env)->gm_blocksize;
30
+ TCGv_ptr fpst;
122
+ int gm_bs_bytes = 4 << gm_bs;
31
+
123
void *tag_mem;
32
+ tcg_res = tcg_temp_new_i32();
124
33
+ fpst = get_fpstatus_ptr(true);
125
- ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
34
+ tcg_op1 = read_fp_hreg(s, rn);
126
+ ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
35
+ tcg_op2 = read_fp_hreg(s, rm);
127
36
+
128
/* Trap if accessing an invalid page. */
37
+ switch (opcode) {
129
tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
38
+ case 0x0: /* FMUL */
130
- LDGM_STGM_SIZE, MMU_DATA_LOAD,
39
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
131
- LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
40
+ break;
132
+ gm_bs_bytes, MMU_DATA_LOAD,
41
+ case 0x1: /* FDIV */
133
+ gm_bs_bytes / (2 * TAG_GRANULE), ra);
42
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
134
43
+ break;
135
/* The tag is squashed to zero if the page does not support tags. */
44
+ case 0x2: /* FADD */
136
if (!tag_mem) {
45
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
137
return 0;
46
+ break;
138
}
47
+ case 0x3: /* FSUB */
139
48
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
140
- QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
49
+ break;
141
/*
50
+ case 0x4: /* FMAX */
142
- * We are loading 64-bits worth of tags. The ordering of elements
51
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
143
- * within the word corresponds to a 64-bit little-endian operation.
52
+ break;
144
+ * The ordering of elements within the word corresponds to
53
+ case 0x5: /* FMIN */
145
+ * a little-endian operation.
54
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
146
*/
55
+ break;
147
- return ldq_le_p(tag_mem);
56
+ case 0x6: /* FMAXNM */
148
+ switch (gm_bs) {
57
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
149
+ case 6:
58
+ break;
150
+ /* 256 bytes -> 16 tags -> 64 result bits */
59
+ case 0x7: /* FMINNM */
151
+ return ldq_le_p(tag_mem);
60
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
152
+ default:
61
+ break;
153
+ /* cpu configured with unsupported gm blocksize. */
62
+ case 0x8: /* FNMUL */
154
+ g_assert_not_reached();
63
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
155
+ }
64
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
156
}
157
158
void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
159
{
160
int mmu_idx = cpu_mmu_index(env, false);
161
uintptr_t ra = GETPC();
162
+ int gm_bs = env_archcpu(env)->gm_blocksize;
163
+ int gm_bs_bytes = 4 << gm_bs;
164
void *tag_mem;
165
166
- ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
167
+ ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
168
169
/* Trap if accessing an invalid page. */
170
tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
171
- LDGM_STGM_SIZE, MMU_DATA_LOAD,
172
- LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
173
+ gm_bs_bytes, MMU_DATA_LOAD,
174
+ gm_bs_bytes / (2 * TAG_GRANULE), ra);
175
176
/*
177
* Tag store only happens if the page support tags,
178
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
179
return;
180
}
181
182
- QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
183
/*
184
- * We are storing 64-bits worth of tags. The ordering of elements
185
- * within the word corresponds to a 64-bit little-endian operation.
186
+ * The ordering of elements within the word corresponds to
187
+ * a little-endian operation.
188
*/
189
- stq_le_p(tag_mem, val);
190
+ switch (gm_bs) {
191
+ case 6:
192
+ stq_le_p(tag_mem, val);
65
+ break;
193
+ break;
66
+ default:
194
+ default:
195
+ /* cpu configured with unsupported gm blocksize. */
67
+ g_assert_not_reached();
196
+ g_assert_not_reached();
68
+ }
197
+ }
69
+
198
}
70
+ write_fp_sreg(s, rd, tcg_res);
199
71
+
200
void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
72
+ tcg_temp_free_ptr(fpst);
201
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
73
+ tcg_temp_free_i32(tcg_op1);
202
index XXXXXXX..XXXXXXX 100644
74
+ tcg_temp_free_i32(tcg_op2);
203
--- a/target/arm/tcg/translate-a64.c
75
+ tcg_temp_free_i32(tcg_res);
204
+++ b/target/arm/tcg/translate-a64.c
76
+}
205
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
77
+
206
gen_helper_stgm(cpu_env, addr, tcg_rt);
78
/* Floating point data-processing (2 source)
207
} else {
79
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
208
MMUAccessType acc = MMU_DATA_STORE;
80
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
209
- int size = 4 << GMID_EL1_BS;
81
@@ -XXX,XX +XXX,XX @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
210
+ int size = 4 << s->gm_blocksize;
82
}
211
83
handle_fp_2src_double(s, opcode, rd, rn, rm);
212
clean_addr = clean_data_tbi(s, addr);
84
break;
213
tcg_gen_andi_i64(clean_addr, clean_addr, -size);
85
+ case 3:
214
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
86
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
215
gen_helper_ldgm(tcg_rt, cpu_env, addr);
87
+ unallocated_encoding(s);
216
} else {
88
+ return;
217
MMUAccessType acc = MMU_DATA_LOAD;
89
+ }
218
- int size = 4 << GMID_EL1_BS;
90
+ if (!fp_access_check(s)) {
219
+ int size = 4 << s->gm_blocksize;
91
+ return;
220
92
+ }
221
clean_addr = clean_data_tbi(s, addr);
93
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
222
tcg_gen_andi_i64(clean_addr, clean_addr, -size);
94
+ break;
223
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
95
default:
224
dc->cp_regs = arm_cpu->cp_regs;
96
unallocated_encoding(s);
225
dc->features = env->features;
97
}
226
dc->dcz_blocksize = arm_cpu->dcz_blocksize;
227
+ dc->gm_blocksize = arm_cpu->gm_blocksize;
228
229
#ifdef CONFIG_USER_ONLY
230
/* In sve_probe_page, we assume TBI is enabled. */
98
--
231
--
99
2.17.0
232
2.34.1
100
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg
[PULL 03/24] target/arm: Support more GM blocksizes
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Cc: qemu-stable@nongnu.org
3
Support all of the easy GM block sizes.
4
Use direct memory operations, since the pointers are aligned.
5
6
While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
7
an atomic store of one nibble. This is not difficult, but there
8
is also no point in supporting it until required.
9
10
Note that cortex-a710 sets GM blocksize to match its cacheline
11
size of 64 bytes. I expect many implementations will also
12
match the cacheline, which makes 16 bytes very unlikely.
13
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180512003217.9105-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
18
---
10
target/arm/translate-a64.c | 30 ++++++++++++++----------------
19
target/arm/cpu.c | 18 +++++++++---
11
1 file changed, 14 insertions(+), 16 deletions(-)
20
target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
21
2 files changed, 62 insertions(+), 12 deletions(-)
12
22
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
23
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
14
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
25
--- a/target/arm/cpu.c
16
+++ b/target/arm/translate-a64.c
26
+++ b/target/arm/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
27
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
18
return v;
28
ID_PFR1, VIRTUALIZATION, 0);
29
}
30
31
+ if (cpu_isar_feature(aa64_mte, cpu)) {
32
+ /*
33
+ * The architectural range of GM blocksize is 2-6, however qemu
34
+ * doesn't support blocksize of 2 (see HELPER(ldgm)).
35
+ */
36
+ if (tcg_enabled()) {
37
+ assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
38
+ }
39
+
40
#ifndef CONFIG_USER_ONLY
41
- if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
42
/*
43
* Disable the MTE feature bits if we do not have tag-memory
44
* provided by the machine.
45
*/
46
- cpu->isar.id_aa64pfr1 =
47
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
48
- }
49
+ if (cpu->tag_memory == NULL) {
50
+ cpu->isar.id_aa64pfr1 =
51
+ FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
52
+ }
53
#endif
54
+ }
55
56
if (tcg_enabled()) {
57
/*
58
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/arm/tcg/mte_helper.c
61
+++ b/target/arm/tcg/mte_helper.c
62
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
63
int gm_bs = env_archcpu(env)->gm_blocksize;
64
int gm_bs_bytes = 4 << gm_bs;
65
void *tag_mem;
66
+ uint64_t ret;
67
+ int shift;
68
69
ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
70
71
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
72
73
/*
74
* The ordering of elements within the word corresponds to
75
- * a little-endian operation.
76
+ * a little-endian operation. Computation of shift comes from
77
+ *
78
+ * index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
79
+ * data<index*4+3:index*4> = tag
80
+ *
81
+ * Because of the alignment of ptr above, BS=6 has shift=0.
82
+ * All memory operations are aligned. Defer support for BS=2,
83
+ * requiring insertion or extraction of a nibble, until we
84
+ * support a cpu that requires it.
85
*/
86
switch (gm_bs) {
87
+ case 3:
88
+ /* 32 bytes -> 2 tags -> 8 result bits */
89
+ ret = *(uint8_t *)tag_mem;
90
+ break;
91
+ case 4:
92
+ /* 64 bytes -> 4 tags -> 16 result bits */
93
+ ret = cpu_to_le16(*(uint16_t *)tag_mem);
94
+ break;
95
+ case 5:
96
+ /* 128 bytes -> 8 tags -> 32 result bits */
97
+ ret = cpu_to_le32(*(uint32_t *)tag_mem);
98
+ break;
99
case 6:
100
/* 256 bytes -> 16 tags -> 64 result bits */
101
- return ldq_le_p(tag_mem);
102
+ return cpu_to_le64(*(uint64_t *)tag_mem);
103
default:
104
- /* cpu configured with unsupported gm blocksize. */
105
+ /*
106
+ * CPU configured with unsupported/invalid gm blocksize.
107
+ * This is detected early in arm_cpu_realizefn.
108
+ */
109
g_assert_not_reached();
110
}
111
+ shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
112
+ return ret << shift;
19
}
113
}
20
114
21
+static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
115
void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
22
+{
116
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
23
+ TCGv_i32 v = tcg_temp_new_i32();
117
int gm_bs = env_archcpu(env)->gm_blocksize;
24
+
118
int gm_bs_bytes = 4 << gm_bs;
25
+ tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
119
void *tag_mem;
26
+ return v;
120
+ int shift;
27
+}
121
28
+
122
ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
29
/* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
123
30
* If SVE is not enabled, then there are only 128 bits in the vector.
124
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
31
*/
125
return;
32
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
33
static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
34
{
35
TCGv_ptr fpst = NULL;
36
- TCGv_i32 tcg_op = tcg_temp_new_i32();
37
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
38
TCGv_i32 tcg_res = tcg_temp_new_i32();
39
40
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
41
-
42
switch (opcode) {
43
case 0x0: /* FMOV */
44
tcg_gen_mov_i32(tcg_res, tcg_op);
45
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
46
tcg_temp_free_i64(tcg_op2);
47
tcg_temp_free_i64(tcg_res);
48
} else {
49
- TCGv_i32 tcg_op1 = tcg_temp_new_i32();
50
- TCGv_i32 tcg_op2 = tcg_temp_new_i32();
51
+ TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
52
+ TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
53
TCGv_i64 tcg_res = tcg_temp_new_i64();
54
55
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
56
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
57
-
58
gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
59
gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
60
61
@@ -XXX,XX +XXX,XX @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
62
63
fpst = get_fpstatus_ptr(true);
64
65
- tcg_op1 = tcg_temp_new_i32();
66
- tcg_op2 = tcg_temp_new_i32();
67
+ tcg_op1 = read_fp_hreg(s, rn);
68
+ tcg_op2 = read_fp_hreg(s, rm);
69
tcg_res = tcg_temp_new_i32();
70
71
- read_vec_element_i32(s, tcg_op1, rn, 0, MO_16);
72
- read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
73
-
74
switch (fpopcode) {
75
case 0x03: /* FMULX */
76
gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
77
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
78
}
126
}
79
127
80
if (is_scalar) {
128
- /*
81
- TCGv_i32 tcg_op = tcg_temp_new_i32();
129
- * The ordering of elements within the word corresponds to
82
+ TCGv_i32 tcg_op = read_fp_hreg(s, rn);
130
- * a little-endian operation.
83
TCGv_i32 tcg_res = tcg_temp_new_i32();
131
- */
84
132
+ /* See LDGM for comments on BS and on shift. */
85
- read_vec_element_i32(s, tcg_op, rn, 0, MO_16);
133
+ shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
86
-
134
+ val >>= shift;
87
switch (fpop) {
135
switch (gm_bs) {
88
case 0x1a: /* FCVTNS */
136
+ case 3:
89
case 0x1b: /* FCVTMS */
137
+ /* 32 bytes -> 2 tags -> 8 result bits */
138
+ *(uint8_t *)tag_mem = val;
139
+ break;
140
+ case 4:
141
+ /* 64 bytes -> 4 tags -> 16 result bits */
142
+ *(uint16_t *)tag_mem = cpu_to_le16(val);
143
+ break;
144
+ case 5:
145
+ /* 128 bytes -> 8 tags -> 32 result bits */
146
+ *(uint32_t *)tag_mem = cpu_to_le32(val);
147
+ break;
148
case 6:
149
- stq_le_p(tag_mem, val);
150
+ /* 256 bytes -> 16 tags -> 64 result bits */
151
+ *(uint64_t *)tag_mem = cpu_to_le64(val);
152
break;
153
default:
154
/* cpu configured with unsupported gm blocksize. */
90
--
155
--
91
2.17.0
156
2.34.1
92
93
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16
[PULL 04/24] target/arm: When tag memory is not present, set MTE=1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Cc: qemu-stable@nongnu.org
3
When the cpu support MTE, but the system does not, reduce cpu
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
support to user instructions at EL0 instead of completely
5
disabling MTE. If we encounter a cpu implementation which does
6
something else, we can revisit this setting.
7
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20180512003217.9105-5-richard.henderson@linaro.org
10
Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/translate-a64.c | 17 +++++++++++++++--
13
target/arm/cpu.c | 7 ++++---
11
1 file changed, 15 insertions(+), 2 deletions(-)
14
1 file changed, 4 insertions(+), 3 deletions(-)
12
15
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
18
--- a/target/arm/cpu.c
16
+++ b/target/arm/translate-a64.c
19
+++ b/target/arm/cpu.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
20
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
18
bool sf = extract32(insn, 31, 1);
21
19
bool itof;
22
#ifndef CONFIG_USER_ONLY
20
23
/*
21
- if (sbit || (type > 1)
24
- * Disable the MTE feature bits if we do not have tag-memory
22
- || (!sf && scale < 32)) {
25
- * provided by the machine.
23
+ if (sbit || (!sf && scale < 32)) {
26
+ * If we do not have tag-memory provided by the machine,
24
+ unallocated_encoding(s);
27
+ * reduce MTE support to instructions enabled at EL0.
25
+ return;
28
+ * This matches Cortex-A710 BROADCASTMTE input being LOW.
26
+ }
29
*/
27
+
30
if (cpu->tag_memory == NULL) {
28
+ switch (type) {
31
cpu->isar.id_aa64pfr1 =
29
+ case 0: /* float32 */
32
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
30
+ case 1: /* float64 */
33
+ FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
31
+ break;
34
}
32
+ case 3: /* float16 */
35
#endif
33
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
34
+ break;
35
+ }
36
+ /* fallthru */
37
+ default:
38
unallocated_encoding(s);
39
return;
40
}
36
}
41
--
37
--
42
2.17.0
38
2.34.1
43
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16
[PULL 05/24] target/arm: Introduce make_ccsidr64
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We missed all of the scalar fp16 fma operations.
3
Do not hard-code the constants for Neoverse V1.
4
4
5
Cc: qemu-stable@nongnu.org
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20180512003217.9105-8-richard.henderson@linaro.org
7
Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
9
---
12
target/arm/translate-a64.c | 48 ++++++++++++++++++++++++++++++++++++++
10
target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
13
1 file changed, 48 insertions(+)
11
1 file changed, 32 insertions(+), 16 deletions(-)
14
12
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
13
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
15
--- a/target/arm/tcg/cpu64.c
18
+++ b/target/arm/translate-a64.c
16
+++ b/target/arm/tcg/cpu64.c
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
17
@@ -XXX,XX +XXX,XX @@
20
tcg_temp_free_i64(tcg_res);
18
#include "qemu/module.h"
21
}
19
#include "qapi/visitor.h"
22
20
#include "hw/qdev-properties.h"
23
+/* Floating-point data-processing (3 source) - half precision */
21
+#include "qemu/units.h"
24
+static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
22
#include "internals.h"
25
+ int rd, int rn, int rm, int ra)
23
#include "cpregs.h"
24
25
+static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
26
+ unsigned cachesize)
26
+{
27
+{
27
+ TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
28
+ unsigned lg_linesize = ctz32(linesize);
28
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
29
+ unsigned sets;
29
+ TCGv_ptr fpst = get_fpstatus_ptr(true);
30
+
30
+
31
+ tcg_op1 = read_fp_hreg(s, rn);
31
+ /*
32
+ tcg_op2 = read_fp_hreg(s, rm);
32
+ * The 64-bit CCSIDR_EL1 format is:
33
+ tcg_op3 = read_fp_hreg(s, ra);
33
+ * [55:32] number of sets - 1
34
+ * [23:3] associativity - 1
35
+ * [2:0] log2(linesize) - 4
36
+ * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
37
+ */
38
+ assert(assoc != 0);
39
+ assert(is_power_of_2(linesize));
40
+ assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
34
+
41
+
35
+ /* These are fused multiply-add, and must be done as one
42
+ /* sets * associativity * linesize == cachesize. */
36
+ * floating point operation with no rounding between the
43
+ sets = cachesize / (assoc * linesize);
37
+ * multiplication and addition steps.
44
+ assert(cachesize % (assoc * linesize) == 0);
38
+ * NB that doing the negations here as separate steps is
39
+ * correct : an input NaN should come out with its sign bit
40
+ * flipped if it is a negated-input.
41
+ */
42
+ if (o1 == true) {
43
+ tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
44
+ }
45
+
45
+
46
+ if (o0 != o1) {
46
+ return ((uint64_t)(sets - 1) << 32)
47
+ tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
47
+ | ((assoc - 1) << 3)
48
+ }
48
+ | (lg_linesize - 4);
49
+
50
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
51
+
52
+ write_fp_sreg(s, rd, tcg_res);
53
+
54
+ tcg_temp_free_ptr(fpst);
55
+ tcg_temp_free_i32(tcg_op1);
56
+ tcg_temp_free_i32(tcg_op2);
57
+ tcg_temp_free_i32(tcg_op3);
58
+ tcg_temp_free_i32(tcg_res);
59
+}
49
+}
60
+
50
+
61
/* Floating point data-processing (3 source)
51
static void aarch64_a35_initfn(Object *obj)
62
* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
52
{
63
* +---+---+---+-----------+------+----+------+----+------+------+------+
53
ARMCPU *cpu = ARM_CPU(obj);
64
@@ -XXX,XX +XXX,XX @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
54
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
65
}
55
* The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
66
handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
56
* but also says it implements CCIDX, which means they should be
67
break;
57
* 64-bit format. So we here use values which are based on the textual
68
+ case 3:
58
- * information in chapter 2 of the TRM (and on the fact that
69
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
59
- * sets * associativity * linesize == cachesize).
70
+ unallocated_encoding(s);
60
- *
71
+ return;
61
- * The 64-bit CCSIDR_EL1 format is:
72
+ }
62
- * [55:32] number of sets - 1
73
+ if (!fp_access_check(s)) {
63
- * [23:3] associativity - 1
74
+ return;
64
- * [2:0] log2(linesize) - 4
75
+ }
65
- * so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
76
+ handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
66
- *
77
+ break;
67
- * L1: 4-way set associative 64-byte line size, total size 64K,
78
default:
68
- * so sets is 256.
79
unallocated_encoding(s);
69
+ * information in chapter 2 of the TRM:
80
}
70
*
71
+ * L1: 4-way set associative 64-byte line size, total size 64K.
72
* L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
73
- * We pick 1MB, so this has 2048 sets.
74
- *
75
* L3: No L3 (this matches the CLIDR_EL1 value).
76
*/
77
- cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
78
- cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
79
- cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
80
+ cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
81
+ cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
82
+ cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */
83
84
/* From 3.2.115 SCTLR_EL3 */
85
cpu->reset_sctlr = 0x30c50838;
81
--
86
--
82
2.17.0
87
2.34.1
83
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16
[PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Cc: qemu-stable@nongnu.org
3
Access to many of the special registers is enabled or disabled
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
by ACTLR_EL[23], which we implement as constant 0, which means
5
that all writes outside EL3 should trap.
6
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20180512003217.9105-4-richard.henderson@linaro.org
9
Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/helper.h | 6 +++
12
target/arm/cpregs.h | 2 ++
11
target/arm/helper.c | 38 ++++++++++++++-
13
target/arm/helper.c | 4 ++--
12
target/arm/translate-a64.c | 96 +++++++++++++++++++++++++++++++-------
14
target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
13
3 files changed, 122 insertions(+), 18 deletions(-)
15
3 files changed, 41 insertions(+), 11 deletions(-)
14
16
15
diff --git a/target/arm/helper.h b/target/arm/helper.h
17
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.h
19
--- a/target/arm/cpregs.h
18
+++ b/target/arm/helper.h
20
+++ b/target/arm/cpregs.h
19
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr)
21
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
20
DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr)
22
void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
21
DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr)
23
#endif
22
DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr)
24
23
+DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr)
25
+CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
24
+DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr)
26
+
25
+DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr)
27
#endif /* TARGET_ARM_CPREGS_H */
26
+DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr)
27
DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr)
28
DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr)
29
DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr)
30
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
31
DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr)
32
DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr)
33
DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr)
34
+DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr)
35
+DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr)
36
37
DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr)
38
DEF_HELPER_FLAGS_2(set_neon_rmode, TCG_CALL_NO_RWG, i32, i32, env)
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
29
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
30
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
31
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
32
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
44
#undef VFP_CONV_FIX_A64
45
46
/* Conversion to/from f16 can overflow to infinity before/after scaling.
47
- * Therefore we convert to f64 (which does not round), scale,
48
- * and then convert f64 to f16 (which may round).
49
+ * Therefore we convert to f64, scale, and then convert f64 to f16; or
50
+ * vice versa for conversion to integer.
51
+ *
52
+ * For 16- and 32-bit integers, the conversion to f64 never rounds.
53
+ * For 64-bit integers, any integer that would cause rounding will also
54
+ * overflow to f16 infinity, so there is no double rounding problem.
55
*/
56
57
static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
58
@@ -XXX,XX +XXX,XX @@ float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
59
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
60
}
33
}
61
34
62
+float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
35
/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */
36
-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
37
- bool isread)
38
+CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
39
+ bool isread)
40
{
41
if (arm_current_el(env) == 1) {
42
uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
43
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/tcg/cpu64.c
46
+++ b/target/arm/tcg/cpu64.c
47
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
48
/* TODO: Add A64FX specific HPC extension registers */
49
}
50
51
+static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
52
+ bool read)
63
+{
53
+{
64
+ return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
54
+ if (!read) {
55
+ int el = arm_current_el(env);
56
+
57
+ /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
58
+ if (el < 2 && arm_is_el2_enabled(env)) {
59
+ return CP_ACCESS_TRAP_EL2;
60
+ }
61
+ /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
62
+ if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
63
+ return CP_ACCESS_TRAP_EL3;
64
+ }
65
+ }
66
+ return CP_ACCESS_OK;
65
+}
67
+}
66
+
68
+
67
+float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
69
static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
68
+{
70
{ .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
69
+ return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
71
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
70
+}
72
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
71
+
73
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
72
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
74
+ /* Traps and enables are the same as for TCR_EL1. */
73
{
75
+ .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
74
if (unlikely(float16_is_any_nan(f))) {
76
{ .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
75
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
77
.opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
76
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
78
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
77
}
79
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
78
80
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
79
+uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
81
{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
80
+{
82
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
81
+ return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
83
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
82
+}
84
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
83
+
85
+ .accessfn = access_actlr_w },
84
+uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
86
{ .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
85
+{
87
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
86
+ return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
88
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
87
+}
89
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
88
+
90
+ .accessfn = access_actlr_w },
89
+uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
91
{ .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
90
+{
92
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
91
+ return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
93
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
92
+}
94
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
93
+
95
+ .accessfn = access_actlr_w },
94
+uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
96
/*
95
+{
97
* Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
96
+ return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
98
* (and in particular its system registers).
97
+}
99
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
98
+
100
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
99
/* Set the current fp rounding mode and return the old one.
101
{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
100
* The argument is a softfloat float_round_ value.
102
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
101
*/
103
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
102
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
104
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
103
index XXXXXXX..XXXXXXX 100644
105
+ .accessfn = access_actlr_w },
104
--- a/target/arm/translate-a64.c
106
{ .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
105
+++ b/target/arm/translate-a64.c
107
.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
106
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
108
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
107
bool itof, int rmode, int scale, int sf, int type)
109
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
108
{
110
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
109
bool is_signed = !(opcode & 1);
111
{ .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
110
- bool is_double = type;
112
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
111
TCGv_ptr tcg_fpstatus;
113
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
112
- TCGv_i32 tcg_shift;
114
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
113
+ TCGv_i32 tcg_shift, tcg_single;
115
+ .accessfn = access_actlr_w },
114
+ TCGv_i64 tcg_double;
116
{ .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
115
117
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
116
- tcg_fpstatus = get_fpstatus_ptr(false);
118
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
117
+ tcg_fpstatus = get_fpstatus_ptr(type == 3);
119
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
118
120
+ .accessfn = access_actlr_w },
119
tcg_shift = tcg_const_i32(64 - scale);
121
{ .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
120
122
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
121
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
123
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
122
tcg_int = tcg_extend;
124
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
123
}
125
+ .accessfn = access_actlr_w },
124
126
{ .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
125
- if (is_double) {
127
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
126
- TCGv_i64 tcg_double = tcg_temp_new_i64();
128
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
127
+ switch (type) {
129
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
128
+ case 1: /* float64 */
130
+ .accessfn = access_actlr_w },
129
+ tcg_double = tcg_temp_new_i64();
131
};
130
if (is_signed) {
132
131
gen_helper_vfp_sqtod(tcg_double, tcg_int,
133
static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
132
tcg_shift, tcg_fpstatus);
133
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
134
}
135
write_fp_dreg(s, rd, tcg_double);
136
tcg_temp_free_i64(tcg_double);
137
- } else {
138
- TCGv_i32 tcg_single = tcg_temp_new_i32();
139
+ break;
140
+
141
+ case 0: /* float32 */
142
+ tcg_single = tcg_temp_new_i32();
143
if (is_signed) {
144
gen_helper_vfp_sqtos(tcg_single, tcg_int,
145
tcg_shift, tcg_fpstatus);
146
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
147
}
148
write_fp_sreg(s, rd, tcg_single);
149
tcg_temp_free_i32(tcg_single);
150
+ break;
151
+
152
+ case 3: /* float16 */
153
+ tcg_single = tcg_temp_new_i32();
154
+ if (is_signed) {
155
+ gen_helper_vfp_sqtoh(tcg_single, tcg_int,
156
+ tcg_shift, tcg_fpstatus);
157
+ } else {
158
+ gen_helper_vfp_uqtoh(tcg_single, tcg_int,
159
+ tcg_shift, tcg_fpstatus);
160
+ }
161
+ write_fp_sreg(s, rd, tcg_single);
162
+ tcg_temp_free_i32(tcg_single);
163
+ break;
164
+
165
+ default:
166
+ g_assert_not_reached();
167
}
168
} else {
169
TCGv_i64 tcg_int = cpu_reg(s, rd);
170
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
171
172
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
173
174
- if (is_double) {
175
- TCGv_i64 tcg_double = read_fp_dreg(s, rn);
176
+ switch (type) {
177
+ case 1: /* float64 */
178
+ tcg_double = read_fp_dreg(s, rn);
179
if (is_signed) {
180
if (!sf) {
181
gen_helper_vfp_tosld(tcg_int, tcg_double,
182
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
183
tcg_shift, tcg_fpstatus);
184
}
185
}
186
+ if (!sf) {
187
+ tcg_gen_ext32u_i64(tcg_int, tcg_int);
188
+ }
189
tcg_temp_free_i64(tcg_double);
190
- } else {
191
- TCGv_i32 tcg_single = read_fp_sreg(s, rn);
192
+ break;
193
+
194
+ case 0: /* float32 */
195
+ tcg_single = read_fp_sreg(s, rn);
196
if (sf) {
197
if (is_signed) {
198
gen_helper_vfp_tosqs(tcg_int, tcg_single,
199
@@ -XXX,XX +XXX,XX @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
200
tcg_temp_free_i32(tcg_dest);
201
}
202
tcg_temp_free_i32(tcg_single);
203
+ break;
204
+
205
+ case 3: /* float16 */
206
+ tcg_single = read_fp_sreg(s, rn);
207
+ if (sf) {
208
+ if (is_signed) {
209
+ gen_helper_vfp_tosqh(tcg_int, tcg_single,
210
+ tcg_shift, tcg_fpstatus);
211
+ } else {
212
+ gen_helper_vfp_touqh(tcg_int, tcg_single,
213
+ tcg_shift, tcg_fpstatus);
214
+ }
215
+ } else {
216
+ TCGv_i32 tcg_dest = tcg_temp_new_i32();
217
+ if (is_signed) {
218
+ gen_helper_vfp_toslh(tcg_dest, tcg_single,
219
+ tcg_shift, tcg_fpstatus);
220
+ } else {
221
+ gen_helper_vfp_toulh(tcg_dest, tcg_single,
222
+ tcg_shift, tcg_fpstatus);
223
+ }
224
+ tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
225
+ tcg_temp_free_i32(tcg_dest);
226
+ }
227
+ tcg_temp_free_i32(tcg_single);
228
+ break;
229
+
230
+ default:
231
+ g_assert_not_reached();
232
}
233
234
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
235
tcg_temp_free_i32(tcg_rmode);
236
-
237
- if (!sf) {
238
- tcg_gen_ext32u_i64(tcg_int, tcg_int);
239
- }
240
}
241
242
tcg_temp_free_ptr(tcg_fpstatus);
243
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
244
/* actual FP conversions */
245
bool itof = extract32(opcode, 1, 1);
246
247
- if (type > 1 || (rmode != 0 && opcode > 1)) {
248
+ if (rmode != 0 && opcode > 1) {
249
+ unallocated_encoding(s);
250
+ return;
251
+ }
252
+ switch (type) {
253
+ case 0: /* float32 */
254
+ case 1: /* float64 */
255
+ break;
256
+ case 3: /* float16 */
257
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
258
+ break;
259
+ }
260
+ /* fallthru */
261
+ default:
262
unallocated_encoding(s);
263
return;
264
}
265
--
134
--
266
2.17.0
135
2.34.1
267
268
diff view generated by jsdifflib
New patch
[PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
There is only one additional EL1 register modeled, which
4
also needs to use access_actlr_w.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/tcg/cpu64.c | 3 ++-
12
1 file changed, 2 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/tcg/cpu64.c
17
+++ b/target/arm/tcg/cpu64.c
18
@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
19
static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
20
{ .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
21
.opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
22
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
23
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
24
+ .accessfn = access_actlr_w },
25
{ .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
26
.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
27
.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
28
--
29
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/24] target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
4
external to the cpu, which is out of scope for QEMU.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.c | 3 +++
12
1 file changed, 3 insertions(+)
13
14
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.c
17
+++ b/target/arm/cpu.c
18
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
19
/* FEAT_SPE (Statistical Profiling Extension) */
20
cpu->isar.id_aa64dfr0 =
21
FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
22
+ /* FEAT_TRBE (Trace Buffer Extension) */
23
+ cpu->isar.id_aa64dfr0 =
24
+ FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
25
/* FEAT_TRF (Self-hosted Trace Extension) */
26
cpu->isar.id_aa64dfr0 =
27
FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
28
--
29
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv
[PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
No sense in emitting code after the exception.
3
This feature allows the operating system to set TCR_ELx.HWU*
4
to allow the implementation to use the PBHA bits from the
5
block and page descriptors for for IMPLEMENTATION DEFINED
6
purposes. Since QEMU has no need to use these bits, we may
7
simply ignore them.
4
8
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20180512003217.9105-3-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
13
---
11
target/arm/translate-a64.c | 2 +-
14
docs/system/arm/emulation.rst | 1 +
12
1 file changed, 1 insertion(+), 1 deletion(-)
15
target/arm/tcg/cpu32.c | 2 +-
16
target/arm/tcg/cpu64.c | 2 +-
17
3 files changed, 3 insertions(+), 2 deletions(-)
13
18
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
15
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
21
--- a/docs/system/arm/emulation.rst
17
+++ b/target/arm/translate-a64.c
22
+++ b/docs/system/arm/emulation.rst
18
@@ -XXX,XX +XXX,XX @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
19
default:
24
- FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
20
/* all other sf/type/rmode combinations are invalid */
25
- FEAT_HCX (Support for the HCRX_EL2 register)
21
unallocated_encoding(s);
26
- FEAT_HPDS (Hierarchical permission disables)
22
- break;
27
+- FEAT_HPDS2 (Translation table page-based hardware attributes)
23
+ return;
28
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
24
}
29
- FEAT_IDST (ID space trap handling)
25
30
- FEAT_IESB (Implicit error synchronization event)
26
if (!fp_access_check(s)) {
31
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/tcg/cpu32.c
34
+++ b/target/arm/tcg/cpu32.c
35
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
36
cpu->isar.id_mmfr3 = t;
37
38
t = cpu->isar.id_mmfr4;
39
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
40
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
41
t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
42
t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
43
t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
44
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/tcg/cpu64.c
47
+++ b/target/arm/tcg/cpu64.c
48
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
49
t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
50
t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
51
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
52
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
53
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2); /* FEAT_HPDS2 */
54
t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
55
t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3); /* FEAT_PAN3 */
56
t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
27
--
57
--
28
2.17.0
58
2.34.1
29
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising
[PULL 10/24] target/arm: properly document FEAT_CRC32
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Alex Bennée <alex.bennee@linaro.org>
2
2
3
We are meant to explicitly pass fpst, not cpu_env.
3
This is a mandatory feature for Armv8.1 architectures but we don't
4
state the feature clearly in our emulation list. Also include
5
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
4
6
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
5
Cc: qemu-stable@nongnu.org
10
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
[PMM: pluralize 'instructions' in docs]
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Message-id: 20180512003217.9105-12-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
14
---
13
target/arm/translate-a64.c | 3 ++-
15
docs/system/arm/emulation.rst | 1 +
14
1 file changed, 2 insertions(+), 1 deletion(-)
16
target/arm/tcg/cpu64.c | 2 +-
17
2 files changed, 2 insertions(+), 1 deletion(-)
15
18
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
17
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
21
--- a/docs/system/arm/emulation.rst
19
+++ b/target/arm/translate-a64.c
22
+++ b/docs/system/arm/emulation.rst
20
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
23
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
21
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
24
- FEAT_BBM at level 2 (Translation table break-before-make levels)
22
break;
25
- FEAT_BF16 (AArch64 BFloat16 instructions)
23
case 0x3: /* FSQRT */
26
- FEAT_BTI (Branch Target Identification)
24
- gen_helper_sqrt_f16(tcg_res, tcg_op, cpu_env);
27
+- FEAT_CRC32 (CRC32 instructions)
25
+ fpst = get_fpstatus_ptr(true);
28
- FEAT_CSV2 (Cache speculation variant 2)
26
+ gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
29
- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
27
break;
30
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
28
case 0x8: /* FRINTN */
31
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
29
case 0x9: /* FRINTP */
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/tcg/cpu64.c
34
+++ b/target/arm/tcg/cpu64.c
35
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
36
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
37
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
38
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
39
- t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
40
+ t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); /* FEAT_CRC32 */
41
t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
42
t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
43
t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
30
--
44
--
31
2.17.0
45
2.34.1
32
46
33
47
diff view generated by jsdifflib
New patch
[PULL 11/24] Remove i.MX7 IOMUX GPR device from i.MX6UL
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
4
In particular, register 22 is not present on i.MX6UL and this is actualy
5
The only register that is really emulated in the i.MX7 IOMUX GPR device.
6
7
Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
8
as an unimplemented device at the same bus adress and the 2 instantiations
9
were actualy colliding. So we go back to the unimplemented device for now.
10
11
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
12
Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/arm/fsl-imx6ul.h | 2 --
17
hw/arm/fsl-imx6ul.c | 11 -----------
18
2 files changed, 13 deletions(-)
19
20
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/fsl-imx6ul.h
23
+++ b/include/hw/arm/fsl-imx6ul.h
24
@@ -XXX,XX +XXX,XX @@
25
#include "hw/misc/imx6ul_ccm.h"
26
#include "hw/misc/imx6_src.h"
27
#include "hw/misc/imx7_snvs.h"
28
-#include "hw/misc/imx7_gpr.h"
29
#include "hw/intc/imx_gpcv2.h"
30
#include "hw/watchdog/wdt_imx2.h"
31
#include "hw/gpio/imx_gpio.h"
32
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
33
IMX6SRCState src;
34
IMX7SNVSState snvs;
35
IMXGPCv2State gpcv2;
36
- IMX7GPRState gpr;
37
IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
38
IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
39
IMXSerialState uart[FSL_IMX6UL_NUM_UARTS];
40
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/fsl-imx6ul.c
43
+++ b/hw/arm/fsl-imx6ul.c
44
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
45
*/
46
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
47
48
- /*
49
- * GPR
50
- */
51
- object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
52
-
53
/*
54
* GPIOs 1 to 5
55
*/
56
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
57
FSL_IMX6UL_WDOGn_IRQ[i]));
58
}
59
60
- /*
61
- * GPR
62
- */
63
- sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
64
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
65
-
66
/*
67
* SDMA
68
*/
69
--
70
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/24] Refactor i.MX6UL processor code
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
4
* Use those newly defined named constants whenever possible.
5
* Standardize the way we init a familly of unimplemented devices
6
- SAI
7
- PWM
8
- CAN
9
* Add/rework few comments
10
11
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
12
Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
17
hw/arm/fsl-imx6ul.c | 147 ++++++++++++++++++++++-----------
18
2 files changed, 232 insertions(+), 71 deletions(-)
19
20
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/fsl-imx6ul.h
23
+++ b/include/hw/arm/fsl-imx6ul.h
24
@@ -XXX,XX +XXX,XX @@
25
#include "exec/memory.h"
26
#include "cpu.h"
27
#include "qom/object.h"
28
+#include "qemu/units.h"
29
30
#define TYPE_FSL_IMX6UL "fsl-imx6ul"
31
OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
32
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
33
FSL_IMX6UL_NUM_ADCS = 2,
34
FSL_IMX6UL_NUM_USB_PHYS = 2,
35
FSL_IMX6UL_NUM_USBS = 2,
36
+ FSL_IMX6UL_NUM_SAIS = 3,
37
+ FSL_IMX6UL_NUM_CANS = 2,
38
+ FSL_IMX6UL_NUM_PWMS = 4,
39
};
40
41
struct FslIMX6ULState {
42
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
43
44
enum FslIMX6ULMemoryMap {
45
FSL_IMX6UL_MMDC_ADDR = 0x80000000,
46
- FSL_IMX6UL_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
47
+ FSL_IMX6UL_MMDC_SIZE = (2 * GiB),
48
49
FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
50
- FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
51
- FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
52
- FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
53
- FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
54
+ FSL_IMX6UL_QSPI1_MEM_SIZE = (256 * MiB),
55
56
- /* AIPS-2 */
57
+ FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
58
+ FSL_IMX6UL_EIM_ALIAS_SIZE = (128 * MiB),
59
+
60
+ FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
61
+ FSL_IMX6UL_EIM_CS_SIZE = (128 * MiB),
62
+
63
+ FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
64
+ FSL_IMX6UL_AES_ENCRYPT_SIZE = (1 * MiB),
65
+
66
+ FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
67
+ FSL_IMX6UL_QSPI1_RX_SIZE = (32 * MiB),
68
+
69
+ /* AIPS-2 Begin */
70
FSL_IMX6UL_UART6_ADDR = 0x021FC000,
71
+
72
FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
73
+
74
FSL_IMX6UL_UART5_ADDR = 0x021F4000,
75
FSL_IMX6UL_UART4_ADDR = 0x021F0000,
76
FSL_IMX6UL_UART3_ADDR = 0x021EC000,
77
FSL_IMX6UL_UART2_ADDR = 0x021E8000,
78
+
79
FSL_IMX6UL_WDOG3_ADDR = 0x021E4000,
80
+
81
FSL_IMX6UL_QSPI_ADDR = 0x021E0000,
82
+ FSL_IMX6UL_QSPI_SIZE = 0x500,
83
+
84
FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000,
85
+ FSL_IMX6UL_SYS_CNT_CTRL_SIZE = (16 * KiB),
86
+
87
FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000,
88
+ FSL_IMX6UL_SYS_CNT_CMP_SIZE = (16 * KiB),
89
+
90
FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000,
91
+ FSL_IMX6UL_SYS_CNT_RD_SIZE = (16 * KiB),
92
+
93
FSL_IMX6UL_TZASC_ADDR = 0x021D0000,
94
+ FSL_IMX6UL_TZASC_SIZE = (16 * KiB),
95
+
96
FSL_IMX6UL_PXP_ADDR = 0x021CC000,
97
+ FSL_IMX6UL_PXP_SIZE = (16 * KiB),
98
+
99
FSL_IMX6UL_LCDIF_ADDR = 0x021C8000,
100
+ FSL_IMX6UL_LCDIF_SIZE = 0x100,
101
+
102
FSL_IMX6UL_CSI_ADDR = 0x021C4000,
103
+ FSL_IMX6UL_CSI_SIZE = 0x100,
104
+
105
FSL_IMX6UL_CSU_ADDR = 0x021C0000,
106
+ FSL_IMX6UL_CSU_SIZE = (16 * KiB),
107
+
108
FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000,
109
+ FSL_IMX6UL_OCOTP_CTRL_SIZE = (4 * KiB),
110
+
111
FSL_IMX6UL_EIM_ADDR = 0x021B8000,
112
+ FSL_IMX6UL_EIM_SIZE = 0x100,
113
+
114
FSL_IMX6UL_SIM2_ADDR = 0x021B4000,
115
+
116
FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000,
117
+ FSL_IMX6UL_MMDC_CFG_SIZE = (4 * KiB),
118
+
119
FSL_IMX6UL_ROMCP_ADDR = 0x021AC000,
120
+ FSL_IMX6UL_ROMCP_SIZE = 0x300,
121
+
122
FSL_IMX6UL_I2C3_ADDR = 0x021A8000,
123
FSL_IMX6UL_I2C2_ADDR = 0x021A4000,
124
FSL_IMX6UL_I2C1_ADDR = 0x021A0000,
125
+
126
FSL_IMX6UL_ADC2_ADDR = 0x0219C000,
127
FSL_IMX6UL_ADC1_ADDR = 0x02198000,
128
+ FSL_IMX6UL_ADCn_SIZE = 0x100,
129
+
130
FSL_IMX6UL_USDHC2_ADDR = 0x02194000,
131
FSL_IMX6UL_USDHC1_ADDR = 0x02190000,
132
- FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
133
- FSL_IMX6UL_ENET1_ADDR = 0x02188000,
134
- FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
135
- FSL_IMX6UL_USBO2_USB_ADDR = 0x02184000,
136
- FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
137
- FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
138
- FSL_IMX6UL_CAAM_ADDR = 0x02140000,
139
- FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
140
141
- /* AIPS-1 */
142
+ FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
143
+ FSL_IMX6UL_SIMn_SIZE = (16 * KiB),
144
+
145
+ FSL_IMX6UL_ENET1_ADDR = 0x02188000,
146
+
147
+ FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
148
+ FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000,
149
+ FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200,
150
+
151
+ FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
152
+ FSL_IMX6UL_USBO2_PL301_SIZE = (16 * KiB),
153
+
154
+ FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
155
+ FSL_IMX6UL_AIPS2_CFG_SIZE = 0x100,
156
+
157
+ FSL_IMX6UL_CAAM_ADDR = 0x02140000,
158
+ FSL_IMX6UL_CAAM_SIZE = (16 * KiB),
159
+
160
+ FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
161
+ FSL_IMX6UL_A7MPCORE_DAP_SIZE = (4 * KiB),
162
+ /* AIPS-2 End */
163
+
164
+ /* AIPS-1 Begin */
165
FSL_IMX6UL_PWM8_ADDR = 0x020FC000,
166
FSL_IMX6UL_PWM7_ADDR = 0x020F8000,
167
FSL_IMX6UL_PWM6_ADDR = 0x020F4000,
168
FSL_IMX6UL_PWM5_ADDR = 0x020F0000,
169
+
170
FSL_IMX6UL_SDMA_ADDR = 0x020EC000,
171
+ FSL_IMX6UL_SDMA_SIZE = 0x300,
172
+
173
FSL_IMX6UL_GPT2_ADDR = 0x020E8000,
174
+
175
FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000,
176
+ FSL_IMX6UL_IOMUXC_GPR_SIZE = 0x40,
177
+
178
FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000,
179
+ FSL_IMX6UL_IOMUXC_SIZE = 0x700,
180
+
181
FSL_IMX6UL_GPC_ADDR = 0x020DC000,
182
+
183
FSL_IMX6UL_SRC_ADDR = 0x020D8000,
184
+
185
FSL_IMX6UL_EPIT2_ADDR = 0x020D4000,
186
FSL_IMX6UL_EPIT1_ADDR = 0x020D0000,
187
+
188
FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000,
189
+
190
FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000,
191
- FSL_IMX6UL_USBPHY2_SIZE = (4 * 1024),
192
FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000,
193
- FSL_IMX6UL_USBPHY1_SIZE = (4 * 1024),
194
+
195
FSL_IMX6UL_ANALOG_ADDR = 0x020C8000,
196
+ FSL_IMX6UL_ANALOG_SIZE = 0x300,
197
+
198
FSL_IMX6UL_CCM_ADDR = 0x020C4000,
199
+
200
FSL_IMX6UL_WDOG2_ADDR = 0x020C0000,
201
FSL_IMX6UL_WDOG1_ADDR = 0x020BC000,
202
+
203
FSL_IMX6UL_KPP_ADDR = 0x020B8000,
204
+ FSL_IMX6UL_KPP_SIZE = 0x10,
205
+
206
FSL_IMX6UL_ENET2_ADDR = 0x020B4000,
207
+
208
FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000,
209
+ FSL_IMX6UL_SNVS_LP_SIZE = (16 * KiB),
210
+
211
FSL_IMX6UL_GPIO5_ADDR = 0x020AC000,
212
FSL_IMX6UL_GPIO4_ADDR = 0x020A8000,
213
FSL_IMX6UL_GPIO3_ADDR = 0x020A4000,
214
FSL_IMX6UL_GPIO2_ADDR = 0x020A0000,
215
FSL_IMX6UL_GPIO1_ADDR = 0x0209C000,
216
+
217
FSL_IMX6UL_GPT1_ADDR = 0x02098000,
218
+
219
FSL_IMX6UL_CAN2_ADDR = 0x02094000,
220
FSL_IMX6UL_CAN1_ADDR = 0x02090000,
221
+ FSL_IMX6UL_CANn_SIZE = (4 * KiB),
222
+
223
FSL_IMX6UL_PWM4_ADDR = 0x0208C000,
224
FSL_IMX6UL_PWM3_ADDR = 0x02088000,
225
FSL_IMX6UL_PWM2_ADDR = 0x02084000,
226
FSL_IMX6UL_PWM1_ADDR = 0x02080000,
227
+ FSL_IMX6UL_PWMn_SIZE = 0x20,
228
+
229
FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000,
230
+ FSL_IMX6UL_AIPS1_CFG_SIZE = (16 * KiB),
231
+
232
FSL_IMX6UL_BEE_ADDR = 0x02044000,
233
+ FSL_IMX6UL_BEE_SIZE = (16 * KiB),
234
+
235
FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000,
236
+ FSL_IMX6UL_TOUCH_CTRL_SIZE = 0x100,
237
+
238
FSL_IMX6UL_SPBA_ADDR = 0x0203C000,
239
+ FSL_IMX6UL_SPBA_SIZE = 0x100,
240
+
241
FSL_IMX6UL_ASRC_ADDR = 0x02034000,
242
+ FSL_IMX6UL_ASRC_SIZE = 0x100,
243
+
244
FSL_IMX6UL_SAI3_ADDR = 0x02030000,
245
FSL_IMX6UL_SAI2_ADDR = 0x0202C000,
246
FSL_IMX6UL_SAI1_ADDR = 0x02028000,
247
+ FSL_IMX6UL_SAIn_SIZE = 0x200,
248
+
249
FSL_IMX6UL_UART8_ADDR = 0x02024000,
250
FSL_IMX6UL_UART1_ADDR = 0x02020000,
251
FSL_IMX6UL_UART7_ADDR = 0x02018000,
252
+
253
FSL_IMX6UL_ECSPI4_ADDR = 0x02014000,
254
FSL_IMX6UL_ECSPI3_ADDR = 0x02010000,
255
FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000,
256
FSL_IMX6UL_ECSPI1_ADDR = 0x02008000,
257
+
258
FSL_IMX6UL_SPDIF_ADDR = 0x02004000,
259
+ FSL_IMX6UL_SPDIF_SIZE = 0x100,
260
+ /* AIPS-1 End */
261
+
262
+ FSL_IMX6UL_BCH_ADDR = 0x01808000,
263
+ FSL_IMX6UL_BCH_SIZE = 0x200,
264
+
265
+ FSL_IMX6UL_GPMI_ADDR = 0x01806000,
266
+ FSL_IMX6UL_GPMI_SIZE = 0x200,
267
268
FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000,
269
- FSL_IMX6UL_APBH_DMA_SIZE = (32 * 1024),
270
+ FSL_IMX6UL_APBH_DMA_SIZE = (4 * KiB),
271
272
FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000,
273
274
FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000,
275
- FSL_IMX6UL_OCRAM_ALIAS_SIZE = 0x00060000,
276
+ FSL_IMX6UL_OCRAM_ALIAS_SIZE = (384 * KiB),
277
+
278
FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000,
279
- FSL_IMX6UL_OCRAM_MEM_SIZE = 0x00020000,
280
+ FSL_IMX6UL_OCRAM_MEM_SIZE = (128 * KiB),
281
+
282
FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000,
283
- FSL_IMX6UL_CAAM_MEM_SIZE = 0x00008000,
284
+ FSL_IMX6UL_CAAM_MEM_SIZE = (32 * KiB),
285
+
286
FSL_IMX6UL_ROM_ADDR = 0x00000000,
287
- FSL_IMX6UL_ROM_SIZE = 0x00018000,
288
+ FSL_IMX6UL_ROM_SIZE = (96 * KiB),
289
};
290
291
enum FslIMX6ULIRQs {
292
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
293
index XXXXXXX..XXXXXXX 100644
294
--- a/hw/arm/fsl-imx6ul.c
295
+++ b/hw/arm/fsl-imx6ul.c
296
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
297
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
298
299
/*
300
- * GPIOs 1 to 5
301
+ * GPIOs
302
*/
303
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
304
snprintf(name, NAME_SIZE, "gpio%d", i);
305
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
306
}
307
308
/*
309
- * GPT 1, 2
310
+ * GPTs
311
*/
312
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
313
snprintf(name, NAME_SIZE, "gpt%d", i);
314
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
315
}
316
317
/*
318
- * EPIT 1, 2
319
+ * EPITs
320
*/
321
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
322
snprintf(name, NAME_SIZE, "epit%d", i + 1);
323
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
324
}
325
326
/*
327
- * eCSPI
328
+ * eCSPIs
329
*/
330
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
331
snprintf(name, NAME_SIZE, "spi%d", i + 1);
332
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
333
}
334
335
/*
336
- * I2C
337
+ * I2Cs
338
*/
339
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
340
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
341
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
342
}
343
344
/*
345
- * UART
346
+ * UARTs
347
*/
348
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
349
snprintf(name, NAME_SIZE, "uart%d", i);
350
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
351
}
352
353
/*
354
- * Ethernet
355
+ * Ethernets
356
*/
357
for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
358
snprintf(name, NAME_SIZE, "eth%d", i);
359
object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
360
}
361
362
- /* USB */
363
+ /*
364
+ * USB PHYs
365
+ */
366
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
367
snprintf(name, NAME_SIZE, "usbphy%d", i);
368
object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
369
}
370
+
371
+ /*
372
+ * USBs
373
+ */
374
for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
375
snprintf(name, NAME_SIZE, "usb%d", i);
376
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
377
}
378
379
/*
380
- * SDHCI
381
+ * SDHCIs
382
*/
383
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
384
snprintf(name, NAME_SIZE, "usdhc%d", i);
385
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
386
}
387
388
/*
389
- * Watchdog
390
+ * Watchdogs
391
*/
392
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
393
snprintf(name, NAME_SIZE, "wdt%d", i);
394
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
395
* A7MPCORE DAP
396
*/
397
create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
398
- 0x100000);
399
+ FSL_IMX6UL_A7MPCORE_DAP_SIZE);
400
401
/*
402
- * GPT 1, 2
403
+ * GPTs
404
*/
405
for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
406
static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
407
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
408
}
409
410
/*
411
- * EPIT 1, 2
412
+ * EPITs
413
*/
414
for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
415
static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
416
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
417
}
418
419
/*
420
- * GPIO
421
+ * GPIOs
422
*/
423
for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
424
static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
425
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
426
}
427
428
/*
429
- * IOMUXC and IOMUXC_GPR
430
+ * IOMUXC
431
*/
432
- for (i = 0; i < 1; i++) {
433
- static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
434
- FSL_IMX6UL_IOMUXC_ADDR,
435
- FSL_IMX6UL_IOMUXC_GPR_ADDR,
436
- };
437
-
438
- snprintf(name, NAME_SIZE, "iomuxc%d", i);
439
- create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
440
- }
441
+ create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
442
+ FSL_IMX6UL_IOMUXC_SIZE);
443
+ create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
444
+ FSL_IMX6UL_IOMUXC_GPR_SIZE);
445
446
/*
447
* CCM
448
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
449
sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
450
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
451
452
- /* Initialize all ECSPI */
453
+ /*
454
+ * ECSPIs
455
+ */
456
for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
457
static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
458
FSL_IMX6UL_ECSPI1_ADDR,
459
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
460
}
461
462
/*
463
- * I2C
464
+ * I2Cs
465
*/
466
for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
467
static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
468
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
469
}
470
471
/*
472
- * UART
473
+ * UARTs
474
*/
475
for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
476
static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
477
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
478
}
479
480
/*
481
- * Ethernet
482
+ * Ethernets
483
*
484
* We must use two loops since phy_connected affects the other interface
485
* and we have to set all properties before calling sysbus_realize().
486
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
487
FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
488
}
489
490
- /* USB */
491
+ /*
492
+ * USB PHYs
493
+ */
494
for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
495
+ static const hwaddr
496
+ FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
497
+ FSL_IMX6UL_USBPHY1_ADDR,
498
+ FSL_IMX6UL_USBPHY2_ADDR,
499
+ };
500
+
501
sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
502
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
503
- FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
504
+ FSL_IMX6UL_USB_PHYn_ADDR[i]);
505
}
506
507
+ /*
508
+ * USBs
509
+ */
510
for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
511
+ static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
512
+ FSL_IMX6UL_USBO2_USB1_ADDR,
513
+ FSL_IMX6UL_USBO2_USB2_ADDR,
514
+ };
515
+
516
static const int FSL_IMX6UL_USBn_IRQ[] = {
517
FSL_IMX6UL_USB1_IRQ,
518
FSL_IMX6UL_USB2_IRQ,
519
};
520
+
521
sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
522
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
523
- FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
524
+ FSL_IMX6UL_USB02_USBn_ADDR[i]);
525
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
526
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
527
FSL_IMX6UL_USBn_IRQ[i]));
528
}
529
530
/*
531
- * USDHC
532
+ * USDHCs
533
*/
534
for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
535
static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
536
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
537
sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
538
539
/*
540
- * Watchdog
541
+ * Watchdogs
542
*/
543
for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
544
static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
545
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
546
FSL_IMX6UL_WDOG2_ADDR,
547
FSL_IMX6UL_WDOG3_ADDR,
548
};
549
+
550
static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
551
FSL_IMX6UL_WDOG1_IRQ,
552
FSL_IMX6UL_WDOG2_IRQ,
553
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
554
/*
555
* SDMA
556
*/
557
- create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
558
+ create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
559
+ FSL_IMX6UL_SDMA_SIZE);
560
561
/*
562
- * SAI (Audio SSI (Synchronous Serial Interface))
563
+ * SAIs (Audio SSI (Synchronous Serial Interface))
564
*/
565
- create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
566
- create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
567
- create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
568
+ for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
569
+ static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
570
+ FSL_IMX6UL_SAI1_ADDR,
571
+ FSL_IMX6UL_SAI2_ADDR,
572
+ FSL_IMX6UL_SAI3_ADDR,
573
+ };
574
+
575
+ snprintf(name, NAME_SIZE, "sai%d", i);
576
+ create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
577
+ FSL_IMX6UL_SAIn_SIZE);
578
+ }
579
580
/*
581
- * PWM
582
+ * PWMs
583
*/
584
- create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
585
- create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
586
- create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
587
- create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
588
+ for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
589
+ static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
590
+ FSL_IMX6UL_PWM1_ADDR,
591
+ FSL_IMX6UL_PWM2_ADDR,
592
+ FSL_IMX6UL_PWM3_ADDR,
593
+ FSL_IMX6UL_PWM4_ADDR,
594
+ };
595
+
596
+ snprintf(name, NAME_SIZE, "pwm%d", i);
597
+ create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
598
+ FSL_IMX6UL_PWMn_SIZE);
599
+ }
600
601
/*
602
* Audio ASRC (asynchronous sample rate converter)
603
*/
604
- create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
605
+ create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
606
+ FSL_IMX6UL_ASRC_SIZE);
607
608
/*
609
- * CAN
610
+ * CANs
611
*/
612
- create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
613
- create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
614
+ for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
615
+ static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
616
+ FSL_IMX6UL_CAN1_ADDR,
617
+ FSL_IMX6UL_CAN2_ADDR,
618
+ };
619
+
620
+ snprintf(name, NAME_SIZE, "can%d", i);
621
+ create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
622
+ FSL_IMX6UL_CANn_SIZE);
623
+ }
624
625
/*
626
* APHB_DMA
627
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
628
};
629
630
snprintf(name, NAME_SIZE, "adc%d", i);
631
- create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
632
+ create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
633
+ FSL_IMX6UL_ADCn_SIZE);
634
}
635
636
/*
637
* LCD
638
*/
639
- create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
640
+ create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
641
+ FSL_IMX6UL_LCDIF_SIZE);
642
643
/*
644
* ROM memory
645
--
646
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16
[PULL 13/24] Add i.MX6UL missing devices.
1
From: Alex Bennée <alex.bennee@linaro.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
All the hard work is already done by vfp_expand_imm, we just need to
3
* Add TZASC as unimplemented device.
4
make sure we pick up the correct size.
4
- Allow bare metal application to access this (unimplemented) device
5
* Add CSU as unimplemented device.
6
- Allow bare metal application to access this (unimplemented) device
7
* Add 4 missing PWM devices
5
8
6
Cc: qemu-stable@nongnu.org
9
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
9
Tested-by: Alex Bennée <alex.bennee@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20180512003217.9105-11-richard.henderson@linaro.org
12
[rth: Merge unallocated_encoding check with TCGMemOp conversion.]
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
13
---
16
target/arm/translate-a64.c | 20 +++++++++++++++++---
14
include/hw/arm/fsl-imx6ul.h | 2 +-
17
1 file changed, 17 insertions(+), 3 deletions(-)
15
hw/arm/fsl-imx6ul.c | 16 ++++++++++++++++
16
2 files changed, 17 insertions(+), 1 deletion(-)
18
17
19
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
20
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/translate-a64.c
20
--- a/include/hw/arm/fsl-imx6ul.h
22
+++ b/target/arm/translate-a64.c
21
+++ b/include/hw/arm/fsl-imx6ul.h
23
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
22
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
24
{
23
FSL_IMX6UL_NUM_USBS = 2,
25
int rd = extract32(insn, 0, 5);
24
FSL_IMX6UL_NUM_SAIS = 3,
26
int imm8 = extract32(insn, 13, 8);
25
FSL_IMX6UL_NUM_CANS = 2,
27
- int is_double = extract32(insn, 22, 2);
26
- FSL_IMX6UL_NUM_PWMS = 4,
28
+ int type = extract32(insn, 22, 2);
27
+ FSL_IMX6UL_NUM_PWMS = 8,
29
uint64_t imm;
28
};
30
TCGv_i64 tcg_res;
29
31
+ TCGMemOp sz;
30
struct FslIMX6ULState {
32
31
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
33
- if (is_double > 1) {
32
index XXXXXXX..XXXXXXX 100644
34
+ switch (type) {
33
--- a/hw/arm/fsl-imx6ul.c
35
+ case 0:
34
+++ b/hw/arm/fsl-imx6ul.c
36
+ sz = MO_32;
35
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
37
+ break;
36
FSL_IMX6UL_PWM2_ADDR,
38
+ case 1:
37
FSL_IMX6UL_PWM3_ADDR,
39
+ sz = MO_64;
38
FSL_IMX6UL_PWM4_ADDR,
40
+ break;
39
+ FSL_IMX6UL_PWM5_ADDR,
41
+ case 3:
40
+ FSL_IMX6UL_PWM6_ADDR,
42
+ sz = MO_16;
41
+ FSL_IMX6UL_PWM7_ADDR,
43
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
42
+ FSL_IMX6UL_PWM8_ADDR,
44
+ break;
43
};
45
+ }
44
46
+ /* fallthru */
45
snprintf(name, NAME_SIZE, "pwm%d", i);
47
+ default:
46
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
48
unallocated_encoding(s);
47
create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
49
return;
48
FSL_IMX6UL_LCDIF_SIZE);
50
}
49
51
@@ -XXX,XX +XXX,XX @@ static void disas_fp_imm(DisasContext *s, uint32_t insn)
50
+ /*
52
return;
51
+ * CSU
53
}
52
+ */
54
53
+ create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
55
- imm = vfp_expand_imm(MO_32 + is_double, imm8);
54
+ FSL_IMX6UL_CSU_SIZE);
56
+ imm = vfp_expand_imm(sz, imm8);
55
+
57
56
+ /*
58
tcg_res = tcg_const_i64(imm);
57
+ * TZASC
59
write_fp_dreg(s, rd, tcg_res);
58
+ */
59
+ create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
60
+ FSL_IMX6UL_TZASC_SIZE);
61
+
62
/*
63
* ROM memory
64
*/
60
--
65
--
61
2.17.0
66
2.34.1
62
67
63
68
diff view generated by jsdifflib
New patch
[PULL 14/24] Refactor i.MX7 processor code
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
4
* Use those newly defined named constants whenever possible.
5
* Standardize the way we init a familly of unimplemented devices
6
- SAI
7
- PWM
8
- CAN
9
* Add/rework few comments
10
11
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
12
Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
17
hw/arm/fsl-imx7.c | 130 ++++++++++-----
18
2 files changed, 335 insertions(+), 125 deletions(-)
19
20
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/arm/fsl-imx7.h
23
+++ b/include/hw/arm/fsl-imx7.h
24
@@ -XXX,XX +XXX,XX @@
25
#include "hw/misc/imx7_ccm.h"
26
#include "hw/misc/imx7_snvs.h"
27
#include "hw/misc/imx7_gpr.h"
28
-#include "hw/misc/imx6_src.h"
29
#include "hw/watchdog/wdt_imx2.h"
30
#include "hw/gpio/imx_gpio.h"
31
#include "hw/char/imx_serial.h"
32
@@ -XXX,XX +XXX,XX @@
33
#include "hw/usb/chipidea.h"
34
#include "cpu.h"
35
#include "qom/object.h"
36
+#include "qemu/units.h"
37
38
#define TYPE_FSL_IMX7 "fsl-imx7"
39
OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
40
@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
41
FSL_IMX7_NUM_ECSPIS = 4,
42
FSL_IMX7_NUM_USBS = 3,
43
FSL_IMX7_NUM_ADCS = 2,
44
+ FSL_IMX7_NUM_SAIS = 3,
45
+ FSL_IMX7_NUM_CANS = 2,
46
+ FSL_IMX7_NUM_PWMS = 4,
47
};
48
49
struct FslIMX7State {
50
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
51
52
enum FslIMX7MemoryMap {
53
FSL_IMX7_MMDC_ADDR = 0x80000000,
54
- FSL_IMX7_MMDC_SIZE = 2 * 1024 * 1024 * 1024UL,
55
+ FSL_IMX7_MMDC_SIZE = (2 * GiB),
56
57
- FSL_IMX7_GPIO1_ADDR = 0x30200000,
58
- FSL_IMX7_GPIO2_ADDR = 0x30210000,
59
- FSL_IMX7_GPIO3_ADDR = 0x30220000,
60
- FSL_IMX7_GPIO4_ADDR = 0x30230000,
61
- FSL_IMX7_GPIO5_ADDR = 0x30240000,
62
- FSL_IMX7_GPIO6_ADDR = 0x30250000,
63
- FSL_IMX7_GPIO7_ADDR = 0x30260000,
64
+ FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000,
65
+ FSL_IMX7_QSPI1_MEM_SIZE = (256 * MiB),
66
67
- FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
68
+ FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000,
69
+ FSL_IMX7_PCIE1_MEM_SIZE = (256 * MiB),
70
71
- FSL_IMX7_WDOG1_ADDR = 0x30280000,
72
- FSL_IMX7_WDOG2_ADDR = 0x30290000,
73
- FSL_IMX7_WDOG3_ADDR = 0x302A0000,
74
- FSL_IMX7_WDOG4_ADDR = 0x302B0000,
75
+ FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000,
76
+ FSL_IMX7_QSPI1_RX_BUF_SIZE = (32 * MiB),
77
78
- FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000,
79
+ /* PCIe Peripherals */
80
+ FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
81
82
- FSL_IMX7_GPT1_ADDR = 0x302D0000,
83
- FSL_IMX7_GPT2_ADDR = 0x302E0000,
84
- FSL_IMX7_GPT3_ADDR = 0x302F0000,
85
- FSL_IMX7_GPT4_ADDR = 0x30300000,
86
+ /* MMAP Peripherals */
87
+ FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
88
+ FSL_IMX7_DMA_APBH_SIZE = 0x8000,
89
90
- FSL_IMX7_IOMUXC_ADDR = 0x30330000,
91
- FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
92
- FSL_IMX7_IOMUXCn_SIZE = 0x1000,
93
+ /* GPV configuration */
94
+ FSL_IMX7_GPV6_ADDR = 0x32600000,
95
+ FSL_IMX7_GPV5_ADDR = 0x32500000,
96
+ FSL_IMX7_GPV4_ADDR = 0x32400000,
97
+ FSL_IMX7_GPV3_ADDR = 0x32300000,
98
+ FSL_IMX7_GPV2_ADDR = 0x32200000,
99
+ FSL_IMX7_GPV1_ADDR = 0x32100000,
100
+ FSL_IMX7_GPV0_ADDR = 0x32000000,
101
+ FSL_IMX7_GPVn_SIZE = (1 * MiB),
102
103
- FSL_IMX7_OCOTP_ADDR = 0x30350000,
104
- FSL_IMX7_OCOTP_SIZE = 0x10000,
105
+ /* Arm Peripherals */
106
+ FSL_IMX7_A7MPCORE_ADDR = 0x31000000,
107
108
- FSL_IMX7_ANALOG_ADDR = 0x30360000,
109
- FSL_IMX7_SNVS_ADDR = 0x30370000,
110
- FSL_IMX7_CCM_ADDR = 0x30380000,
111
+ /* AIPS-3 Begin */
112
113
- FSL_IMX7_SRC_ADDR = 0x30390000,
114
- FSL_IMX7_SRC_SIZE = 0x1000,
115
+ FSL_IMX7_ENET2_ADDR = 0x30BF0000,
116
+ FSL_IMX7_ENET1_ADDR = 0x30BE0000,
117
118
- FSL_IMX7_ADC1_ADDR = 0x30610000,
119
- FSL_IMX7_ADC2_ADDR = 0x30620000,
120
- FSL_IMX7_ADCn_SIZE = 0x1000,
121
+ FSL_IMX7_SDMA_ADDR = 0x30BD0000,
122
+ FSL_IMX7_SDMA_SIZE = (4 * KiB),
123
124
- FSL_IMX7_PWM1_ADDR = 0x30660000,
125
- FSL_IMX7_PWM2_ADDR = 0x30670000,
126
- FSL_IMX7_PWM3_ADDR = 0x30680000,
127
- FSL_IMX7_PWM4_ADDR = 0x30690000,
128
- FSL_IMX7_PWMn_SIZE = 0x10000,
129
+ FSL_IMX7_EIM_ADDR = 0x30BC0000,
130
+ FSL_IMX7_EIM_SIZE = (4 * KiB),
131
132
- FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
133
- FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
134
+ FSL_IMX7_QSPI_ADDR = 0x30BB0000,
135
+ FSL_IMX7_QSPI_SIZE = 0x8000,
136
137
- FSL_IMX7_GPC_ADDR = 0x303A0000,
138
+ FSL_IMX7_SIM2_ADDR = 0x30BA0000,
139
+ FSL_IMX7_SIM1_ADDR = 0x30B90000,
140
+ FSL_IMX7_SIMn_SIZE = (4 * KiB),
141
+
142
+ FSL_IMX7_USDHC3_ADDR = 0x30B60000,
143
+ FSL_IMX7_USDHC2_ADDR = 0x30B50000,
144
+ FSL_IMX7_USDHC1_ADDR = 0x30B40000,
145
+
146
+ FSL_IMX7_USB3_ADDR = 0x30B30000,
147
+ FSL_IMX7_USBMISC3_ADDR = 0x30B30200,
148
+ FSL_IMX7_USB2_ADDR = 0x30B20000,
149
+ FSL_IMX7_USBMISC2_ADDR = 0x30B20200,
150
+ FSL_IMX7_USB1_ADDR = 0x30B10000,
151
+ FSL_IMX7_USBMISC1_ADDR = 0x30B10200,
152
+ FSL_IMX7_USBMISCn_SIZE = 0x200,
153
+
154
+ FSL_IMX7_USB_PL301_ADDR = 0x30AD0000,
155
+ FSL_IMX7_USB_PL301_SIZE = (64 * KiB),
156
+
157
+ FSL_IMX7_SEMAPHORE_HS_ADDR = 0x30AC0000,
158
+ FSL_IMX7_SEMAPHORE_HS_SIZE = (64 * KiB),
159
+
160
+ FSL_IMX7_MUB_ADDR = 0x30AB0000,
161
+ FSL_IMX7_MUA_ADDR = 0x30AA0000,
162
+ FSL_IMX7_MUn_SIZE = (KiB),
163
+
164
+ FSL_IMX7_UART7_ADDR = 0x30A90000,
165
+ FSL_IMX7_UART6_ADDR = 0x30A80000,
166
+ FSL_IMX7_UART5_ADDR = 0x30A70000,
167
+ FSL_IMX7_UART4_ADDR = 0x30A60000,
168
+
169
+ FSL_IMX7_I2C4_ADDR = 0x30A50000,
170
+ FSL_IMX7_I2C3_ADDR = 0x30A40000,
171
+ FSL_IMX7_I2C2_ADDR = 0x30A30000,
172
+ FSL_IMX7_I2C1_ADDR = 0x30A20000,
173
+
174
+ FSL_IMX7_CAN2_ADDR = 0x30A10000,
175
+ FSL_IMX7_CAN1_ADDR = 0x30A00000,
176
+ FSL_IMX7_CANn_SIZE = (4 * KiB),
177
+
178
+ FSL_IMX7_AIPS3_CONF_ADDR = 0x309F0000,
179
+ FSL_IMX7_AIPS3_CONF_SIZE = (64 * KiB),
180
181
FSL_IMX7_CAAM_ADDR = 0x30900000,
182
- FSL_IMX7_CAAM_SIZE = 0x40000,
183
+ FSL_IMX7_CAAM_SIZE = (256 * KiB),
184
185
- FSL_IMX7_CAN1_ADDR = 0x30A00000,
186
- FSL_IMX7_CAN2_ADDR = 0x30A10000,
187
- FSL_IMX7_CANn_SIZE = 0x10000,
188
+ FSL_IMX7_SPBA_ADDR = 0x308F0000,
189
+ FSL_IMX7_SPBA_SIZE = (4 * KiB),
190
191
- FSL_IMX7_I2C1_ADDR = 0x30A20000,
192
- FSL_IMX7_I2C2_ADDR = 0x30A30000,
193
- FSL_IMX7_I2C3_ADDR = 0x30A40000,
194
- FSL_IMX7_I2C4_ADDR = 0x30A50000,
195
+ FSL_IMX7_SAI3_ADDR = 0x308C0000,
196
+ FSL_IMX7_SAI2_ADDR = 0x308B0000,
197
+ FSL_IMX7_SAI1_ADDR = 0x308A0000,
198
+ FSL_IMX7_SAIn_SIZE = (4 * KiB),
199
200
- FSL_IMX7_ECSPI1_ADDR = 0x30820000,
201
- FSL_IMX7_ECSPI2_ADDR = 0x30830000,
202
- FSL_IMX7_ECSPI3_ADDR = 0x30840000,
203
- FSL_IMX7_ECSPI4_ADDR = 0x30630000,
204
-
205
- FSL_IMX7_LCDIF_ADDR = 0x30730000,
206
- FSL_IMX7_LCDIF_SIZE = 0x1000,
207
-
208
- FSL_IMX7_UART1_ADDR = 0x30860000,
209
+ FSL_IMX7_UART3_ADDR = 0x30880000,
210
/*
211
* Some versions of the reference manual claim that UART2 is @
212
* 0x30870000, but experiments with HW + DT files in upstream
213
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
214
* actually located @ 0x30890000
215
*/
216
FSL_IMX7_UART2_ADDR = 0x30890000,
217
- FSL_IMX7_UART3_ADDR = 0x30880000,
218
- FSL_IMX7_UART4_ADDR = 0x30A60000,
219
- FSL_IMX7_UART5_ADDR = 0x30A70000,
220
- FSL_IMX7_UART6_ADDR = 0x30A80000,
221
- FSL_IMX7_UART7_ADDR = 0x30A90000,
222
+ FSL_IMX7_UART1_ADDR = 0x30860000,
223
224
- FSL_IMX7_SAI1_ADDR = 0x308A0000,
225
- FSL_IMX7_SAI2_ADDR = 0x308B0000,
226
- FSL_IMX7_SAI3_ADDR = 0x308C0000,
227
- FSL_IMX7_SAIn_SIZE = 0x10000,
228
+ FSL_IMX7_ECSPI3_ADDR = 0x30840000,
229
+ FSL_IMX7_ECSPI2_ADDR = 0x30830000,
230
+ FSL_IMX7_ECSPI1_ADDR = 0x30820000,
231
+ FSL_IMX7_ECSPIn_SIZE = (4 * KiB),
232
233
- FSL_IMX7_ENET1_ADDR = 0x30BE0000,
234
- FSL_IMX7_ENET2_ADDR = 0x30BF0000,
235
+ /* AIPS-3 End */
236
237
- FSL_IMX7_USB1_ADDR = 0x30B10000,
238
- FSL_IMX7_USBMISC1_ADDR = 0x30B10200,
239
- FSL_IMX7_USB2_ADDR = 0x30B20000,
240
- FSL_IMX7_USBMISC2_ADDR = 0x30B20200,
241
- FSL_IMX7_USB3_ADDR = 0x30B30000,
242
- FSL_IMX7_USBMISC3_ADDR = 0x30B30200,
243
- FSL_IMX7_USBMISCn_SIZE = 0x200,
244
+ /* AIPS-2 Begin */
245
246
- FSL_IMX7_USDHC1_ADDR = 0x30B40000,
247
- FSL_IMX7_USDHC2_ADDR = 0x30B50000,
248
- FSL_IMX7_USDHC3_ADDR = 0x30B60000,
249
+ FSL_IMX7_AXI_DEBUG_MON_ADDR = 0x307E0000,
250
+ FSL_IMX7_AXI_DEBUG_MON_SIZE = (64 * KiB),
251
252
- FSL_IMX7_SDMA_ADDR = 0x30BD0000,
253
- FSL_IMX7_SDMA_SIZE = 0x1000,
254
+ FSL_IMX7_PERFMON2_ADDR = 0x307D0000,
255
+ FSL_IMX7_PERFMON1_ADDR = 0x307C0000,
256
+ FSL_IMX7_PERFMONn_SIZE = (64 * KiB),
257
+
258
+ FSL_IMX7_DDRC_ADDR = 0x307A0000,
259
+ FSL_IMX7_DDRC_SIZE = (4 * KiB),
260
+
261
+ FSL_IMX7_DDRC_PHY_ADDR = 0x30790000,
262
+ FSL_IMX7_DDRC_PHY_SIZE = (4 * KiB),
263
+
264
+ FSL_IMX7_TZASC_ADDR = 0x30780000,
265
+ FSL_IMX7_TZASC_SIZE = (64 * KiB),
266
+
267
+ FSL_IMX7_MIPI_DSI_ADDR = 0x30760000,
268
+ FSL_IMX7_MIPI_DSI_SIZE = (4 * KiB),
269
+
270
+ FSL_IMX7_MIPI_CSI_ADDR = 0x30750000,
271
+ FSL_IMX7_MIPI_CSI_SIZE = 0x4000,
272
+
273
+ FSL_IMX7_LCDIF_ADDR = 0x30730000,
274
+ FSL_IMX7_LCDIF_SIZE = 0x8000,
275
+
276
+ FSL_IMX7_CSI_ADDR = 0x30710000,
277
+ FSL_IMX7_CSI_SIZE = (4 * KiB),
278
+
279
+ FSL_IMX7_PXP_ADDR = 0x30700000,
280
+ FSL_IMX7_PXP_SIZE = 0x4000,
281
+
282
+ FSL_IMX7_EPDC_ADDR = 0x306F0000,
283
+ FSL_IMX7_EPDC_SIZE = (4 * KiB),
284
+
285
+ FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
286
+ FSL_IMX7_PCIE_PHY_SIZE = (4 * KiB),
287
+
288
+ FSL_IMX7_SYSCNT_CTRL_ADDR = 0x306C0000,
289
+ FSL_IMX7_SYSCNT_CMP_ADDR = 0x306B0000,
290
+ FSL_IMX7_SYSCNT_RD_ADDR = 0x306A0000,
291
+
292
+ FSL_IMX7_PWM4_ADDR = 0x30690000,
293
+ FSL_IMX7_PWM3_ADDR = 0x30680000,
294
+ FSL_IMX7_PWM2_ADDR = 0x30670000,
295
+ FSL_IMX7_PWM1_ADDR = 0x30660000,
296
+ FSL_IMX7_PWMn_SIZE = (4 * KiB),
297
+
298
+ FSL_IMX7_FlEXTIMER2_ADDR = 0x30650000,
299
+ FSL_IMX7_FlEXTIMER1_ADDR = 0x30640000,
300
+ FSL_IMX7_FLEXTIMERn_SIZE = (4 * KiB),
301
+
302
+ FSL_IMX7_ECSPI4_ADDR = 0x30630000,
303
+
304
+ FSL_IMX7_ADC2_ADDR = 0x30620000,
305
+ FSL_IMX7_ADC1_ADDR = 0x30610000,
306
+ FSL_IMX7_ADCn_SIZE = (4 * KiB),
307
+
308
+ FSL_IMX7_AIPS2_CONF_ADDR = 0x305F0000,
309
+ FSL_IMX7_AIPS2_CONF_SIZE = (64 * KiB),
310
+
311
+ /* AIPS-2 End */
312
+
313
+ /* AIPS-1 Begin */
314
+
315
+ FSL_IMX7_CSU_ADDR = 0x303E0000,
316
+ FSL_IMX7_CSU_SIZE = (64 * KiB),
317
+
318
+ FSL_IMX7_RDC_ADDR = 0x303D0000,
319
+ FSL_IMX7_RDC_SIZE = (4 * KiB),
320
+
321
+ FSL_IMX7_SEMAPHORE2_ADDR = 0x303C0000,
322
+ FSL_IMX7_SEMAPHORE1_ADDR = 0x303B0000,
323
+ FSL_IMX7_SEMAPHOREn_SIZE = (4 * KiB),
324
+
325
+ FSL_IMX7_GPC_ADDR = 0x303A0000,
326
+
327
+ FSL_IMX7_SRC_ADDR = 0x30390000,
328
+ FSL_IMX7_SRC_SIZE = (4 * KiB),
329
+
330
+ FSL_IMX7_CCM_ADDR = 0x30380000,
331
+
332
+ FSL_IMX7_SNVS_HP_ADDR = 0x30370000,
333
+
334
+ FSL_IMX7_ANALOG_ADDR = 0x30360000,
335
+
336
+ FSL_IMX7_OCOTP_ADDR = 0x30350000,
337
+ FSL_IMX7_OCOTP_SIZE = 0x10000,
338
+
339
+ FSL_IMX7_IOMUXC_GPR_ADDR = 0x30340000,
340
+ FSL_IMX7_IOMUXC_GPR_SIZE = (4 * KiB),
341
+
342
+ FSL_IMX7_IOMUXC_ADDR = 0x30330000,
343
+ FSL_IMX7_IOMUXC_SIZE = (4 * KiB),
344
+
345
+ FSL_IMX7_KPP_ADDR = 0x30320000,
346
+ FSL_IMX7_KPP_SIZE = (4 * KiB),
347
+
348
+ FSL_IMX7_ROMCP_ADDR = 0x30310000,
349
+ FSL_IMX7_ROMCP_SIZE = (4 * KiB),
350
+
351
+ FSL_IMX7_GPT4_ADDR = 0x30300000,
352
+ FSL_IMX7_GPT3_ADDR = 0x302F0000,
353
+ FSL_IMX7_GPT2_ADDR = 0x302E0000,
354
+ FSL_IMX7_GPT1_ADDR = 0x302D0000,
355
+
356
+ FSL_IMX7_IOMUXC_LPSR_ADDR = 0x302C0000,
357
+ FSL_IMX7_IOMUXC_LPSR_SIZE = (4 * KiB),
358
+
359
+ FSL_IMX7_WDOG4_ADDR = 0x302B0000,
360
+ FSL_IMX7_WDOG3_ADDR = 0x302A0000,
361
+ FSL_IMX7_WDOG2_ADDR = 0x30290000,
362
+ FSL_IMX7_WDOG1_ADDR = 0x30280000,
363
+
364
+ FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
365
+
366
+ FSL_IMX7_GPIO7_ADDR = 0x30260000,
367
+ FSL_IMX7_GPIO6_ADDR = 0x30250000,
368
+ FSL_IMX7_GPIO5_ADDR = 0x30240000,
369
+ FSL_IMX7_GPIO4_ADDR = 0x30230000,
370
+ FSL_IMX7_GPIO3_ADDR = 0x30220000,
371
+ FSL_IMX7_GPIO2_ADDR = 0x30210000,
372
+ FSL_IMX7_GPIO1_ADDR = 0x30200000,
373
+
374
+ FSL_IMX7_AIPS1_CONF_ADDR = 0x301F0000,
375
+ FSL_IMX7_AIPS1_CONF_SIZE = (64 * KiB),
376
377
- FSL_IMX7_A7MPCORE_ADDR = 0x31000000,
378
FSL_IMX7_A7MPCORE_DAP_ADDR = 0x30000000,
379
+ FSL_IMX7_A7MPCORE_DAP_SIZE = (1 * MiB),
380
381
- FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
382
- FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
383
+ /* AIPS-1 End */
384
385
- FSL_IMX7_GPR_ADDR = 0x30340000,
386
+ FSL_IMX7_EIM_CS0_ADDR = 0x28000000,
387
+ FSL_IMX7_EIM_CS0_SIZE = (128 * MiB),
388
389
- FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
390
- FSL_IMX7_DMA_APBH_SIZE = 0x2000,
391
+ FSL_IMX7_OCRAM_PXP_ADDR = 0x00940000,
392
+ FSL_IMX7_OCRAM_PXP_SIZE = (32 * KiB),
393
+
394
+ FSL_IMX7_OCRAM_EPDC_ADDR = 0x00920000,
395
+ FSL_IMX7_OCRAM_EPDC_SIZE = (128 * KiB),
396
+
397
+ FSL_IMX7_OCRAM_MEM_ADDR = 0x00900000,
398
+ FSL_IMX7_OCRAM_MEM_SIZE = (128 * KiB),
399
+
400
+ FSL_IMX7_TCMU_ADDR = 0x00800000,
401
+ FSL_IMX7_TCMU_SIZE = (32 * KiB),
402
+
403
+ FSL_IMX7_TCML_ADDR = 0x007F8000,
404
+ FSL_IMX7_TCML_SIZE = (32 * KiB),
405
+
406
+ FSL_IMX7_OCRAM_S_ADDR = 0x00180000,
407
+ FSL_IMX7_OCRAM_S_SIZE = (32 * KiB),
408
+
409
+ FSL_IMX7_CAAM_MEM_ADDR = 0x00100000,
410
+ FSL_IMX7_CAAM_MEM_SIZE = (32 * KiB),
411
+
412
+ FSL_IMX7_ROM_ADDR = 0x00000000,
413
+ FSL_IMX7_ROM_SIZE = (96 * KiB),
414
};
415
416
enum FslIMX7IRQs {
417
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
418
index XXXXXXX..XXXXXXX 100644
419
--- a/hw/arm/fsl-imx7.c
420
+++ b/hw/arm/fsl-imx7.c
421
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
422
char name[NAME_SIZE];
423
int i;
424
425
+ /*
426
+ * CPUs
427
+ */
428
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
429
snprintf(name, NAME_SIZE, "cpu%d", i);
430
object_initialize_child(obj, name, &s->cpu[i],
431
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
432
TYPE_A15MPCORE_PRIV);
433
434
/*
435
- * GPIOs 1 to 7
436
+ * GPIOs
437
*/
438
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
439
snprintf(name, NAME_SIZE, "gpio%d", i);
440
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
441
}
442
443
/*
444
- * GPT1, 2, 3, 4
445
+ * GPTs
446
*/
447
for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
448
snprintf(name, NAME_SIZE, "gpt%d", i);
449
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
450
*/
451
object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
452
453
+ /*
454
+ * ECSPIs
455
+ */
456
for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
457
snprintf(name, NAME_SIZE, "spi%d", i + 1);
458
object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
459
}
460
461
-
462
+ /*
463
+ * I2Cs
464
+ */
465
for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
466
snprintf(name, NAME_SIZE, "i2c%d", i + 1);
467
object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
468
}
469
470
/*
471
- * UART
472
+ * UARTs
473
*/
474
for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
475
snprintf(name, NAME_SIZE, "uart%d", i);
476
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
477
}
478
479
/*
480
- * Ethernet
481
+ * Ethernets
482
*/
483
for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
484
snprintf(name, NAME_SIZE, "eth%d", i);
485
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
486
}
487
488
/*
489
- * SDHCI
490
+ * SDHCIs
491
*/
492
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
493
snprintf(name, NAME_SIZE, "usdhc%d", i);
494
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
495
object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
496
497
/*
498
- * Watchdog
499
+ * Watchdogs
500
*/
501
for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
502
snprintf(name, NAME_SIZE, "wdt%d", i);
503
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
504
*/
505
object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
506
507
+ /*
508
+ * PCIE
509
+ */
510
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
511
512
+ /*
513
+ * USBs
514
+ */
515
for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
516
snprintf(name, NAME_SIZE, "usb%d", i);
517
object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
518
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
519
return;
520
}
521
522
+ /*
523
+ * CPUs
524
+ */
525
for (i = 0; i < smp_cpus; i++) {
526
o = OBJECT(&s->cpu[i]);
527
528
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
529
* A7MPCORE DAP
530
*/
531
create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
532
- 0x100000);
533
+ FSL_IMX7_A7MPCORE_DAP_SIZE);
534
535
/*
536
- * GPT1, 2, 3, 4
537
+ * GPTs
538
*/
539
for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
540
static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
541
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
542
FSL_IMX7_GPTn_IRQ[i]));
543
}
544
545
+ /*
546
+ * GPIOs
547
+ */
548
for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
549
static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
550
FSL_IMX7_GPIO1_ADDR,
551
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
552
/*
553
* IOMUXC and IOMUXC_LPSR
554
*/
555
- for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
556
- static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
557
- FSL_IMX7_IOMUXC_ADDR,
558
- FSL_IMX7_IOMUXC_LPSR_ADDR,
559
- };
560
-
561
- snprintf(name, NAME_SIZE, "iomuxc%d", i);
562
- create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
563
- FSL_IMX7_IOMUXCn_SIZE);
564
- }
565
+ create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
566
+ FSL_IMX7_IOMUXC_SIZE);
567
+ create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
568
+ FSL_IMX7_IOMUXC_LPSR_SIZE);
569
570
/*
571
* CCM
572
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
573
sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
574
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
575
576
- /* Initialize all ECSPI */
577
+ /*
578
+ * ECSPIs
579
+ */
580
for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
581
static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
582
FSL_IMX7_ECSPI1_ADDR,
583
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
584
FSL_IMX7_SPIn_IRQ[i]));
585
}
586
587
+ /*
588
+ * I2Cs
589
+ */
590
for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
591
static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
592
FSL_IMX7_I2C1_ADDR,
593
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
594
}
595
596
/*
597
- * UART
598
+ * UARTs
599
*/
600
for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
601
static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
602
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
603
}
604
605
/*
606
- * Ethernet
607
+ * Ethernets
608
*
609
* We must use two loops since phy_connected affects the other interface
610
* and we have to set all properties before calling sysbus_realize().
611
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
612
}
613
614
/*
615
- * USDHC
616
+ * USDHCs
617
*/
618
for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
619
static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
620
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
621
* SNVS
622
*/
623
sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
624
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
625
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
626
627
/*
628
* SRC
629
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
630
create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
631
632
/*
633
- * Watchdog
634
+ * Watchdogs
635
*/
636
for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
637
static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
638
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
639
create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
640
641
/*
642
- * PWM
643
+ * PWMs
644
*/
645
- create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
646
- create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
647
- create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
648
- create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
649
+ for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
650
+ static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
651
+ FSL_IMX7_PWM1_ADDR,
652
+ FSL_IMX7_PWM2_ADDR,
653
+ FSL_IMX7_PWM3_ADDR,
654
+ FSL_IMX7_PWM4_ADDR,
655
+ };
656
+
657
+ snprintf(name, NAME_SIZE, "pwm%d", i);
658
+ create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
659
+ FSL_IMX7_PWMn_SIZE);
660
+ }
661
662
/*
663
- * CAN
664
+ * CANs
665
*/
666
- create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
667
- create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
668
+ for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
669
+ static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
670
+ FSL_IMX7_CAN1_ADDR,
671
+ FSL_IMX7_CAN2_ADDR,
672
+ };
673
+
674
+ snprintf(name, NAME_SIZE, "can%d", i);
675
+ create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
676
+ FSL_IMX7_CANn_SIZE);
677
+ }
678
679
/*
680
- * SAI (Audio SSI (Synchronous Serial Interface))
681
+ * SAIs (Audio SSI (Synchronous Serial Interface))
682
*/
683
- create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
684
- create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
685
- create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
686
+ for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
687
+ static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
688
+ FSL_IMX7_SAI1_ADDR,
689
+ FSL_IMX7_SAI2_ADDR,
690
+ FSL_IMX7_SAI3_ADDR,
691
+ };
692
+
693
+ snprintf(name, NAME_SIZE, "sai%d", i);
694
+ create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
695
+ FSL_IMX7_SAIn_SIZE);
696
+ }
697
698
/*
699
* OCOTP
700
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
701
create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
702
FSL_IMX7_OCOTP_SIZE);
703
704
+ /*
705
+ * GPR
706
+ */
707
sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
708
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
709
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
710
711
+ /*
712
+ * PCIE
713
+ */
714
sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
715
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
716
717
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
718
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
719
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
720
721
-
722
+ /*
723
+ * USBs
724
+ */
725
for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
726
static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
727
FSL_IMX7_USBMISC1_ADDR,
728
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
729
*/
730
create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
731
FSL_IMX7_PCIE_PHY_SIZE);
732
+
733
}
734
735
static Property fsl_imx7_properties[] = {
736
--
737
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch()
[PULL 15/24] Add i.MX7 missing TZ devices and memory regions
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
2
3
Per the Physical Layer Simplified Spec. "4.3.10.4 Switch Function Status":
3
* Add TZASC as unimplemented device.
4
- Allow bare metal application to access this (unimplemented) device
5
* Add CSU as unimplemented device.
6
- Allow bare metal application to access this (unimplemented) device
7
* Add various memory segments
8
- OCRAM
9
- OCRAM EPDC
10
- OCRAM PXP
11
- OCRAM S
12
- ROM
13
- CAAM
4
14
5
The block length is predefined to 512 bits
15
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
6
16
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
and "4.10.2 SD Status":
17
Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
8
9
The SD Status contains status bits that are related to the SD Memory Card
10
proprietary features and may be used for future application-specific usage.
11
The size of the SD Status is one data block of 512 bit. The content of this
12
register is transmitted to the Host over the DAT bus along with a 16-bit CRC.
13
14
Thus the 16-bit CRC goes at offset 64.
15
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20180509060104.4458-3-f4bug@amsat.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
19
---
21
hw/sd/sd.c | 2 +-
20
include/hw/arm/fsl-imx7.h | 7 +++++
22
1 file changed, 1 insertion(+), 1 deletion(-)
21
hw/arm/fsl-imx7.c | 63 +++++++++++++++++++++++++++++++++++++++
22
2 files changed, 70 insertions(+)
23
23
24
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
24
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
25
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/sd/sd.c
26
--- a/include/hw/arm/fsl-imx7.h
27
+++ b/hw/sd/sd.c
27
+++ b/include/hw/arm/fsl-imx7.h
28
@@ -XXX,XX +XXX,XX @@ static void sd_function_switch(SDState *sd, uint32_t arg)
28
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
29
sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
29
IMX7GPRState gpr;
30
}
30
ChipideaState usb[FSL_IMX7_NUM_USBS];
31
memset(&sd->data[17], 0, 47);
31
DesignwarePCIEHost pcie;
32
- stw_be_p(sd->data + 65, sd_crc16(sd->data, 64));
32
+ MemoryRegion rom;
33
+ stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
33
+ MemoryRegion caam;
34
+ MemoryRegion ocram;
35
+ MemoryRegion ocram_epdc;
36
+ MemoryRegion ocram_pxp;
37
+ MemoryRegion ocram_s;
38
+
39
uint32_t phy_num[FSL_IMX7_NUM_ETHS];
40
bool phy_connected[FSL_IMX7_NUM_ETHS];
41
};
42
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/arm/fsl-imx7.c
45
+++ b/hw/arm/fsl-imx7.c
46
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
47
create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
48
FSL_IMX7_PCIE_PHY_SIZE);
49
50
+ /*
51
+ * CSU
52
+ */
53
+ create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
54
+ FSL_IMX7_CSU_SIZE);
55
+
56
+ /*
57
+ * TZASC
58
+ */
59
+ create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
60
+ FSL_IMX7_TZASC_SIZE);
61
+
62
+ /*
63
+ * OCRAM memory
64
+ */
65
+ memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
66
+ FSL_IMX7_OCRAM_MEM_SIZE,
67
+ &error_abort);
68
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
69
+ &s->ocram);
70
+
71
+ /*
72
+ * OCRAM EPDC memory
73
+ */
74
+ memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
75
+ FSL_IMX7_OCRAM_EPDC_SIZE,
76
+ &error_abort);
77
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
78
+ &s->ocram_epdc);
79
+
80
+ /*
81
+ * OCRAM PXP memory
82
+ */
83
+ memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
84
+ FSL_IMX7_OCRAM_PXP_SIZE,
85
+ &error_abort);
86
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
87
+ &s->ocram_pxp);
88
+
89
+ /*
90
+ * OCRAM_S memory
91
+ */
92
+ memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
93
+ FSL_IMX7_OCRAM_S_SIZE,
94
+ &error_abort);
95
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
96
+ &s->ocram_s);
97
+
98
+ /*
99
+ * ROM memory
100
+ */
101
+ memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
102
+ FSL_IMX7_ROM_SIZE, &error_abort);
103
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
104
+ &s->rom);
105
+
106
+ /*
107
+ * CAAM memory
108
+ */
109
+ memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
110
+ FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
111
+ memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
112
+ &s->caam);
34
}
113
}
35
114
36
static inline bool sd_wp_addr(SDState *sd, uint64_t addr)
115
static Property fsl_imx7_properties[] = {
37
--
116
--
38
2.17.0
117
2.34.1
39
118
40
119
diff view generated by jsdifflib
New patch
[PULL 16/24] Add i.MX7 SRC device implementation
1
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
2
3
The SRC device is normally used to start the secondary CPU.
4
5
When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
6
is installing at boot time and therefore the fact that the SRC device is
7
unimplemented is hidden as Qemu respond directly to PSCI requets without
8
using the SRC device.
9
10
But if you try to run a more bare metal application (maybe uboot itself),
11
then it is not possible to start the secondary CPU as the SRC is an
12
unimplemented device.
13
14
This patch adds the ability to start the secondary CPU through the SRC
15
device so that you can use this feature in bare metal applications.
16
17
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
---
22
include/hw/arm/fsl-imx7.h | 3 +-
23
include/hw/misc/imx7_src.h | 66 +++++++++
24
hw/arm/fsl-imx7.c | 8 +-
25
hw/misc/imx7_src.c | 276 +++++++++++++++++++++++++++++++++++++
26
hw/misc/meson.build | 1 +
27
hw/misc/trace-events | 4 +
28
6 files changed, 356 insertions(+), 2 deletions(-)
29
create mode 100644 include/hw/misc/imx7_src.h
30
create mode 100644 hw/misc/imx7_src.c
31
32
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/include/hw/arm/fsl-imx7.h
35
+++ b/include/hw/arm/fsl-imx7.h
36
@@ -XXX,XX +XXX,XX @@
37
#include "hw/misc/imx7_ccm.h"
38
#include "hw/misc/imx7_snvs.h"
39
#include "hw/misc/imx7_gpr.h"
40
+#include "hw/misc/imx7_src.h"
41
#include "hw/watchdog/wdt_imx2.h"
42
#include "hw/gpio/imx_gpio.h"
43
#include "hw/char/imx_serial.h"
44
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
45
IMX7CCMState ccm;
46
IMX7AnalogState analog;
47
IMX7SNVSState snvs;
48
+ IMX7SRCState src;
49
IMXGPCv2State gpcv2;
50
IMXSPIState spi[FSL_IMX7_NUM_ECSPIS];
51
IMXI2CState i2c[FSL_IMX7_NUM_I2CS];
52
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
53
FSL_IMX7_GPC_ADDR = 0x303A0000,
54
55
FSL_IMX7_SRC_ADDR = 0x30390000,
56
- FSL_IMX7_SRC_SIZE = (4 * KiB),
57
58
FSL_IMX7_CCM_ADDR = 0x30380000,
59
60
diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h
61
new file mode 100644
62
index XXXXXXX..XXXXXXX
63
--- /dev/null
64
+++ b/include/hw/misc/imx7_src.h
65
@@ -XXX,XX +XXX,XX @@
66
+/*
67
+ * IMX7 System Reset Controller
68
+ *
69
+ * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
70
+ *
71
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
72
+ * See the COPYING file in the top-level directory.
73
+ */
74
+
75
+#ifndef IMX7_SRC_H
76
+#define IMX7_SRC_H
77
+
78
+#include "hw/sysbus.h"
79
+#include "qemu/bitops.h"
80
+#include "qom/object.h"
81
+
82
+#define SRC_SCR 0
83
+#define SRC_A7RCR0 1
84
+#define SRC_A7RCR1 2
85
+#define SRC_M4RCR 3
86
+#define SRC_ERCR 5
87
+#define SRC_HSICPHY_RCR 7
88
+#define SRC_USBOPHY1_RCR 8
89
+#define SRC_USBOPHY2_RCR 9
90
+#define SRC_MPIPHY_RCR 10
91
+#define SRC_PCIEPHY_RCR 11
92
+#define SRC_SBMR1 22
93
+#define SRC_SRSR 23
94
+#define SRC_SISR 26
95
+#define SRC_SIMR 27
96
+#define SRC_SBMR2 28
97
+#define SRC_GPR1 29
98
+#define SRC_GPR2 30
99
+#define SRC_GPR3 31
100
+#define SRC_GPR4 32
101
+#define SRC_GPR5 33
102
+#define SRC_GPR6 34
103
+#define SRC_GPR7 35
104
+#define SRC_GPR8 36
105
+#define SRC_GPR9 37
106
+#define SRC_GPR10 38
107
+#define SRC_MAX 39
108
+
109
+/* SRC_A7SCR1 */
110
+#define R_CORE1_ENABLE_SHIFT 1
111
+#define R_CORE1_ENABLE_LENGTH 1
112
+/* SRC_A7SCR0 */
113
+#define R_CORE1_RST_SHIFT 5
114
+#define R_CORE1_RST_LENGTH 1
115
+#define R_CORE0_RST_SHIFT 4
116
+#define R_CORE0_RST_LENGTH 1
117
+
118
+#define TYPE_IMX7_SRC "imx7.src"
119
+OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC)
120
+
121
+struct IMX7SRCState {
122
+ /* <private> */
123
+ SysBusDevice parent_obj;
124
+
125
+ /* <public> */
126
+ MemoryRegion iomem;
127
+
128
+ uint32_t regs[SRC_MAX];
129
+};
130
+
131
+#endif /* IMX7_SRC_H */
132
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
133
index XXXXXXX..XXXXXXX 100644
134
--- a/hw/arm/fsl-imx7.c
135
+++ b/hw/arm/fsl-imx7.c
136
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
137
*/
138
object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
139
140
+ /*
141
+ * SRC
142
+ */
143
+ object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC);
144
+
145
/*
146
* ECSPIs
147
*/
148
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
149
/*
150
* SRC
151
*/
152
- create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
153
+ sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
154
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
155
156
/*
157
* Watchdogs
158
diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c
159
new file mode 100644
160
index XXXXXXX..XXXXXXX
161
--- /dev/null
162
+++ b/hw/misc/imx7_src.c
163
@@ -XXX,XX +XXX,XX @@
164
+/*
165
+ * IMX7 System Reset Controller
166
+ *
167
+ * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
168
+ *
169
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
170
+ * See the COPYING file in the top-level directory.
171
+ *
172
+ */
173
+
174
+#include "qemu/osdep.h"
175
+#include "hw/misc/imx7_src.h"
176
+#include "migration/vmstate.h"
177
+#include "qemu/bitops.h"
178
+#include "qemu/log.h"
179
+#include "qemu/main-loop.h"
180
+#include "qemu/module.h"
181
+#include "target/arm/arm-powerctl.h"
182
+#include "hw/core/cpu.h"
183
+#include "hw/registerfields.h"
184
+
185
+#include "trace.h"
186
+
187
+static const char *imx7_src_reg_name(uint32_t reg)
188
+{
189
+ static char unknown[20];
190
+
191
+ switch (reg) {
192
+ case SRC_SCR:
193
+ return "SRC_SCR";
194
+ case SRC_A7RCR0:
195
+ return "SRC_A7RCR0";
196
+ case SRC_A7RCR1:
197
+ return "SRC_A7RCR1";
198
+ case SRC_M4RCR:
199
+ return "SRC_M4RCR";
200
+ case SRC_ERCR:
201
+ return "SRC_ERCR";
202
+ case SRC_HSICPHY_RCR:
203
+ return "SRC_HSICPHY_RCR";
204
+ case SRC_USBOPHY1_RCR:
205
+ return "SRC_USBOPHY1_RCR";
206
+ case SRC_USBOPHY2_RCR:
207
+ return "SRC_USBOPHY2_RCR";
208
+ case SRC_PCIEPHY_RCR:
209
+ return "SRC_PCIEPHY_RCR";
210
+ case SRC_SBMR1:
211
+ return "SRC_SBMR1";
212
+ case SRC_SRSR:
213
+ return "SRC_SRSR";
214
+ case SRC_SISR:
215
+ return "SRC_SISR";
216
+ case SRC_SIMR:
217
+ return "SRC_SIMR";
218
+ case SRC_SBMR2:
219
+ return "SRC_SBMR2";
220
+ case SRC_GPR1:
221
+ return "SRC_GPR1";
222
+ case SRC_GPR2:
223
+ return "SRC_GPR2";
224
+ case SRC_GPR3:
225
+ return "SRC_GPR3";
226
+ case SRC_GPR4:
227
+ return "SRC_GPR4";
228
+ case SRC_GPR5:
229
+ return "SRC_GPR5";
230
+ case SRC_GPR6:
231
+ return "SRC_GPR6";
232
+ case SRC_GPR7:
233
+ return "SRC_GPR7";
234
+ case SRC_GPR8:
235
+ return "SRC_GPR8";
236
+ case SRC_GPR9:
237
+ return "SRC_GPR9";
238
+ case SRC_GPR10:
239
+ return "SRC_GPR10";
240
+ default:
241
+ sprintf(unknown, "%u ?", reg);
242
+ return unknown;
243
+ }
244
+}
245
+
246
+static const VMStateDescription vmstate_imx7_src = {
247
+ .name = TYPE_IMX7_SRC,
248
+ .version_id = 1,
249
+ .minimum_version_id = 1,
250
+ .fields = (VMStateField[]) {
251
+ VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX),
252
+ VMSTATE_END_OF_LIST()
253
+ },
254
+};
255
+
256
+static void imx7_src_reset(DeviceState *dev)
257
+{
258
+ IMX7SRCState *s = IMX7_SRC(dev);
259
+
260
+ memset(s->regs, 0, sizeof(s->regs));
261
+
262
+ /* Set reset values */
263
+ s->regs[SRC_SCR] = 0xA0;
264
+ s->regs[SRC_SRSR] = 0x1;
265
+ s->regs[SRC_SIMR] = 0x1F;
266
+}
267
+
268
+static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size)
269
+{
270
+ uint32_t value = 0;
271
+ IMX7SRCState *s = (IMX7SRCState *)opaque;
272
+ uint32_t index = offset >> 2;
273
+
274
+ if (index < SRC_MAX) {
275
+ value = s->regs[index];
276
+ } else {
277
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
278
+ HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
279
+ }
280
+
281
+ trace_imx7_src_read(imx7_src_reg_name(index), value);
282
+
283
+ return value;
284
+}
285
+
286
+
287
+/*
288
+ * The reset is asynchronous so we need to defer clearing the reset
289
+ * bit until the work is completed.
290
+ */
291
+
292
+struct SRCSCRResetInfo {
293
+ IMX7SRCState *s;
294
+ uint32_t reset_bit;
295
+};
296
+
297
+static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
298
+{
299
+ struct SRCSCRResetInfo *ri = data.host_ptr;
300
+ IMX7SRCState *s = ri->s;
301
+
302
+ assert(qemu_mutex_iothread_locked());
303
+
304
+ s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0);
305
+
306
+ trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
307
+
308
+ g_free(ri);
309
+}
310
+
311
+static void imx7_defer_clear_reset_bit(uint32_t cpuid,
312
+ IMX7SRCState *s,
313
+ uint32_t reset_shift)
314
+{
315
+ struct SRCSCRResetInfo *ri;
316
+ CPUState *cpu = arm_get_cpu_by_id(cpuid);
317
+
318
+ if (!cpu) {
319
+ return;
320
+ }
321
+
322
+ ri = g_new(struct SRCSCRResetInfo, 1);
323
+ ri->s = s;
324
+ ri->reset_bit = reset_shift;
325
+
326
+ async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri));
327
+}
328
+
329
+
330
+static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value,
331
+ unsigned size)
332
+{
333
+ IMX7SRCState *s = (IMX7SRCState *)opaque;
334
+ uint32_t index = offset >> 2;
335
+ long unsigned int change_mask;
336
+ uint32_t current_value = value;
337
+
338
+ if (index >= SRC_MAX) {
339
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
340
+ HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
341
+ return;
342
+ }
343
+
344
+ trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
345
+
346
+ change_mask = s->regs[index] ^ (uint32_t)current_value;
347
+
348
+ switch (index) {
349
+ case SRC_A7RCR0:
350
+ if (FIELD_EX32(change_mask, CORE0, RST)) {
351
+ arm_reset_cpu(0);
352
+ imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT);
353
+ }
354
+ if (FIELD_EX32(change_mask, CORE1, RST)) {
355
+ arm_reset_cpu(1);
356
+ imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
357
+ }
358
+ s->regs[index] = current_value;
359
+ break;
360
+ case SRC_A7RCR1:
361
+ /*
362
+ * On real hardware when the system reset controller starts a
363
+ * secondary CPU it runs through some boot ROM code which reads
364
+ * the SRC_GPRX registers controlling the start address and branches
365
+ * to it.
366
+ * Here we are taking a short cut and branching directly to the
367
+ * requested address (we don't want to run the boot ROM code inside
368
+ * QEMU)
369
+ */
370
+ if (FIELD_EX32(change_mask, CORE1, ENABLE)) {
371
+ if (FIELD_EX32(current_value, CORE1, ENABLE)) {
372
+ /* CORE 1 is brought up */
373
+ arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
374
+ 3, false);
375
+ } else {
376
+ /* CORE 1 is shut down */
377
+ arm_set_cpu_off(1);
378
+ }
379
+ /* We clear the reset bits as the processor changed state */
380
+ imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
381
+ clear_bit(R_CORE1_RST_SHIFT, &change_mask);
382
+ }
383
+ s->regs[index] = current_value;
384
+ break;
385
+ default:
386
+ s->regs[index] = current_value;
387
+ break;
388
+ }
389
+}
390
+
391
+static const struct MemoryRegionOps imx7_src_ops = {
392
+ .read = imx7_src_read,
393
+ .write = imx7_src_write,
394
+ .endianness = DEVICE_NATIVE_ENDIAN,
395
+ .valid = {
396
+ /*
397
+ * Our device would not work correctly if the guest was doing
398
+ * unaligned access. This might not be a limitation on the real
399
+ * device but in practice there is no reason for a guest to access
400
+ * this device unaligned.
401
+ */
402
+ .min_access_size = 4,
403
+ .max_access_size = 4,
404
+ .unaligned = false,
405
+ },
406
+};
407
+
408
+static void imx7_src_realize(DeviceState *dev, Error **errp)
409
+{
410
+ IMX7SRCState *s = IMX7_SRC(dev);
411
+
412
+ memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s,
413
+ TYPE_IMX7_SRC, 0x1000);
414
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
415
+}
416
+
417
+static void imx7_src_class_init(ObjectClass *klass, void *data)
418
+{
419
+ DeviceClass *dc = DEVICE_CLASS(klass);
420
+
421
+ dc->realize = imx7_src_realize;
422
+ dc->reset = imx7_src_reset;
423
+ dc->vmsd = &vmstate_imx7_src;
424
+ dc->desc = "i.MX6 System Reset Controller";
425
+}
426
+
427
+static const TypeInfo imx7_src_info = {
428
+ .name = TYPE_IMX7_SRC,
429
+ .parent = TYPE_SYS_BUS_DEVICE,
430
+ .instance_size = sizeof(IMX7SRCState),
431
+ .class_init = imx7_src_class_init,
432
+};
433
+
434
+static void imx7_src_register_types(void)
435
+{
436
+ type_register_static(&imx7_src_info);
437
+}
438
+
439
+type_init(imx7_src_register_types)
440
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
441
index XXXXXXX..XXXXXXX 100644
442
--- a/hw/misc/meson.build
443
+++ b/hw/misc/meson.build
444
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files(
445
'imx6_src.c',
446
'imx6ul_ccm.c',
447
'imx7_ccm.c',
448
+ 'imx7_src.c',
449
'imx7_gpr.c',
450
'imx7_snvs.c',
451
'imx_ccm.c',
452
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
453
index XXXXXXX..XXXXXXX 100644
454
--- a/hw/misc/trace-events
455
+++ b/hw/misc/trace-events
456
@@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d"
457
ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
458
ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
459
460
+# imx7_src.c
461
+imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
462
+imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
463
+
464
# iotkit-sysinfo.c
465
iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
466
iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
467
--
468
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/24] target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
1
The architecture requires (R_TYTWB) that an attempt to return from EL3
2
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
3
enforces that the CPU can't ever be executing below EL3 with the
4
NSE,NS bits indicating an invalid security state.)
1
5
6
We were missing this check; add it.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
11
---
12
target/arm/tcg/helper-a64.c | 9 +++++++++
13
1 file changed, 9 insertions(+)
14
15
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/tcg/helper-a64.c
18
+++ b/target/arm/tcg/helper-a64.c
19
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
20
spsr &= ~PSTATE_SS;
21
}
22
23
+ /*
24
+ * FEAT_RME forbids return from EL3 with an invalid security state.
25
+ * We don't need an explicit check for FEAT_RME here because we enforce
26
+ * in scr_write() that you can't set the NSE bit without it.
27
+ */
28
+ if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
29
+ goto illegal_return;
30
+ }
31
+
32
new_el = el_from_spsr(spsr);
33
if (new_el == -1) {
34
goto illegal_return;
35
--
36
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised
[PULL 18/24] hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
1
From: Alex Bennée <alex.bennee@linaro.org>
1
In the m48t59 device we almost always use 64-bit arithmetic when
2
dealing with time_t deltas. The one exception is in set_alarm(),
3
which currently uses a plain 'int' to hold the difference between two
4
time_t values. Switch to int64_t instead to avoid any possible
5
overflow issues.
2
6
3
Reported by Coverity (CID1390635). We ensure this for uint_to_float
4
later on so we might as well mirror that.
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
---
9
---
11
fpu/softfloat.c | 2 +-
10
hw/rtc/m48t59.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
11
1 file changed, 1 insertion(+), 1 deletion(-)
13
12
14
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
13
diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/fpu/softfloat.c
15
--- a/hw/rtc/m48t59.c
17
+++ b/fpu/softfloat.c
16
+++ b/hw/rtc/m48t59.c
18
@@ -XXX,XX +XXX,XX @@ FLOAT_TO_UINT(64, 64)
17
@@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque)
19
18
20
static FloatParts int_to_float(int64_t a, float_status *status)
19
static void set_alarm(M48t59State *NVRAM)
21
{
20
{
22
- FloatParts r;
21
- int diff;
23
+ FloatParts r = {};
22
+ int64_t diff;
24
if (a == 0) {
23
if (NVRAM->alrm_timer != NULL) {
25
r.cls = float_class_zero;
24
timer_del(NVRAM->alrm_timer);
26
r.sign = false;
25
diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
27
--
26
--
28
2.17.0
27
2.34.1
29
28
30
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT)
[PULL 19/24] hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
1
In float-to-integer conversion, if the floating point input
1
In the twl92230 device, use int64_t for the two state fields
2
converts exactly to the largest or smallest integer that
2
sec_offset and alm_sec, because we set these to values that
3
fits in to the result type, this is not an overflow.
3
are either time_t or differences between two time_t values.
4
In this situation we were producing the correct result value,
5
but were incorrectly setting the Invalid flag.
6
For example for Arm A64, "FCVTAS w0, d0" on an input of
7
0x41dfffffffc00000 should produce 0x7fffffff and set no flags.
8
4
9
Fix the boundary case to take the right half of the if()
5
These fields aren't saved in vmstate anywhere, so we can
10
statements.
6
safely widen them.
11
7
12
This fixes a regression from 2.11 introduced by the softfloat
13
refactoring.
14
15
Cc: qemu-stable@nongnu.org
16
Fixes: ab52f973a50
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
19
Message-id: 20180510140141.12120-1-peter.maydell@linaro.org
20
---
10
---
21
fpu/softfloat.c | 4 ++--
11
hw/rtc/twl92230.c | 4 ++--
22
1 file changed, 2 insertions(+), 2 deletions(-)
12
1 file changed, 2 insertions(+), 2 deletions(-)
23
13
24
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
14
diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat.c
16
--- a/hw/rtc/twl92230.c
27
+++ b/fpu/softfloat.c
17
+++ b/hw/rtc/twl92230.c
28
@@ -XXX,XX +XXX,XX @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode,
18
@@ -XXX,XX +XXX,XX @@ struct MenelausState {
29
r = UINT64_MAX;
19
struct tm tm;
30
}
20
struct tm new;
31
if (p.sign) {
21
struct tm alm;
32
- if (r < -(uint64_t) min) {
22
- int sec_offset;
33
+ if (r <= -(uint64_t) min) {
23
- int alm_sec;
34
return -r;
24
+ int64_t sec_offset;
35
} else {
25
+ int64_t alm_sec;
36
s->float_exception_flags = orig_flags | float_flag_invalid;
26
int next_comp;
37
return min;
27
} rtc;
38
}
28
uint16_t rtc_next_vmstate;
39
} else {
40
- if (r < max) {
41
+ if (r <= max) {
42
return r;
43
} else {
44
s->float_exception_flags = orig_flags | float_flag_invalid;
45
--
29
--
46
2.17.0
30
2.34.1
47
31
48
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging
[PULL 20/24] hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
1
Usually the logging of the CPU state produced by -d cpu is sufficient
1
In the aspeed_rtc device we store a difference between two time_t
2
to diagnose problems, but sometimes you want to see the state of
2
values in an 'int'. This is not really correct when time_t could
3
the floating point registers as well. We don't want to enable that
3
be 64 bits. Enlarge the field to 'int64_t'.
4
by default as it adds a lot of extra data to the log; instead,
4
5
allow it to be optionally enabled via -d fpu.
5
This is a migration compatibility break for the aspeed boards.
6
While we are changing the vmstate, remove the accidental
7
duplicate of the offset field.
6
8
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Cédric Le Goater <clg@kaod.org>
9
Message-id: 20180510130024.31678-1-peter.maydell@linaro.org
10
---
11
---
11
include/qemu/log.h | 1 +
12
include/hw/rtc/aspeed_rtc.h | 2 +-
12
accel/tcg/cpu-exec.c | 9 ++++++---
13
hw/rtc/aspeed_rtc.c | 5 ++---
13
util/log.c | 2 ++
14
2 files changed, 3 insertions(+), 4 deletions(-)
14
3 files changed, 9 insertions(+), 3 deletions(-)
15
15
16
diff --git a/include/qemu/log.h b/include/qemu/log.h
16
diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/qemu/log.h
18
--- a/include/hw/rtc/aspeed_rtc.h
19
+++ b/include/qemu/log.h
19
+++ b/include/hw/rtc/aspeed_rtc.h
20
@@ -XXX,XX +XXX,XX @@ static inline bool qemu_log_separate(void)
20
@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
21
#define CPU_LOG_PAGE (1 << 14)
21
qemu_irq irq;
22
/* LOG_TRACE (1 << 15) is defined in log-for-trace.h */
22
23
#define CPU_LOG_TB_OP_IND (1 << 16)
23
uint32_t reg[0x18];
24
+#define CPU_LOG_TB_FPU (1 << 17)
24
- int offset;
25
25
+ int64_t offset;
26
/* Lock output for a series of related logs. Since this is not needed
26
27
* for a single qemu_log / qemu_log_mask / qemu_log_mask_and_addr, we
27
};
28
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
28
29
diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
29
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
30
--- a/accel/tcg/cpu-exec.c
31
--- a/hw/rtc/aspeed_rtc.c
31
+++ b/accel/tcg/cpu-exec.c
32
+++ b/hw/rtc/aspeed_rtc.c
32
@@ -XXX,XX +XXX,XX @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, TranslationBlock *itb)
33
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
33
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)
34
34
&& qemu_log_in_addr_range(itb->pc)) {
35
static const VMStateDescription vmstate_aspeed_rtc = {
35
qemu_log_lock();
36
.name = TYPE_ASPEED_RTC,
36
+ int flags = 0;
37
- .version_id = 1,
37
+ if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
38
+ .version_id = 2,
38
+ flags |= CPU_DUMP_FPU;
39
.fields = (VMStateField[]) {
39
+ }
40
VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
40
#if defined(TARGET_I386)
41
- VMSTATE_INT32(offset, AspeedRtcState),
41
- log_cpu_state(cpu, CPU_DUMP_CCOP);
42
- VMSTATE_INT32(offset, AspeedRtcState),
42
-#else
43
+ VMSTATE_INT64(offset, AspeedRtcState),
43
- log_cpu_state(cpu, 0);
44
VMSTATE_END_OF_LIST()
44
+ flags |= CPU_DUMP_CCOP;
45
#endif
46
+ log_cpu_state(cpu, flags);
47
qemu_log_unlock();
48
}
45
}
49
#endif /* DEBUG_DISAS */
46
};
50
diff --git a/util/log.c b/util/log.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/util/log.c
53
+++ b/util/log.c
54
@@ -XXX,XX +XXX,XX @@ const QEMULogItem qemu_log_items[] = {
55
"show trace before each executed TB (lots of logs)" },
56
{ CPU_LOG_TB_CPU, "cpu",
57
"show CPU registers before entering a TB (lots of logs)" },
58
+ { CPU_LOG_TB_FPU, "fpu",
59
+ "include FPU registers in the 'cpu' logging" },
60
{ CPU_LOG_MMU, "mmu",
61
"log MMU-related activities" },
62
{ CPU_LOG_PCALL, "pcall",
63
--
47
--
64
2.17.0
48
2.34.1
65
49
66
50
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16
[PULL 21/24] rtc: Use time_t for passing and returning time offsets
1
From: Alex Bennée <alex.bennee@linaro.org>
1
The functions qemu_get_timedate() and qemu_timedate_diff() take
2
and return a time offset as an integer. Coverity points out that
3
means that when an RTC device implementation holds an offset
4
as a time_t, as the m48t59 does, the time_t will get truncated.
5
(CID 1507157, 1517772).
2
6
3
These where missed out from the rest of the half-precision work.
7
The functions work with time_t internally, so make them use that type
8
in their APIs.
4
9
5
Cc: qemu-stable@nongnu.org
10
Note that this won't help any Y2038 issues where either the device
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
model itself is keeping the offset in a 32-bit integer, or where the
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
12
hardware under emulation has Y2038 or other rollover problems. If we
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
13
missed any cases of the former then hopefully Coverity will warn us
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
about them since after this patch we'd be truncating a time_t in
10
Message-id: 20180512003217.9105-9-richard.henderson@linaro.org
15
assignments from qemu_timedate_diff().)
11
[rth: Diagnose lack of FP16 before fp_access_check]
16
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
14
---
19
---
15
target/arm/helper-a64.h | 2 +
20
include/sysemu/rtc.h | 4 ++--
16
target/arm/helper-a64.c | 10 +++++
21
softmmu/rtc.c | 4 ++--
17
target/arm/translate-a64.c | 88 ++++++++++++++++++++++++++++++--------
22
2 files changed, 4 insertions(+), 4 deletions(-)
18
3 files changed, 83 insertions(+), 17 deletions(-)
19
23
20
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
24
diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
21
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/helper-a64.h
26
--- a/include/sysemu/rtc.h
23
+++ b/target/arm/helper-a64.h
27
+++ b/include/sysemu/rtc.h
24
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@
25
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
29
* The behaviour of the clock whose value this function returns will
26
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
30
* depend on the -rtc command line option passed by the user.
27
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
31
*/
28
+DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
32
-void qemu_get_timedate(struct tm *tm, int offset);
29
+DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
33
+void qemu_get_timedate(struct tm *tm, time_t offset);
30
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
34
31
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
35
/**
32
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
36
* qemu_timedate_diff: Return difference between a struct tm and the RTC
33
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
37
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
38
* a timestamp one hour further ahead than the current RTC time
39
* then this function will return 3600.
40
*/
41
-int qemu_timedate_diff(struct tm *tm);
42
+time_t qemu_timedate_diff(struct tm *tm);
43
44
#endif
45
diff --git a/softmmu/rtc.c b/softmmu/rtc.c
34
index XXXXXXX..XXXXXXX 100644
46
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/helper-a64.c
47
--- a/softmmu/rtc.c
36
+++ b/target/arm/helper-a64.c
48
+++ b/softmmu/rtc.c
37
@@ -XXX,XX +XXX,XX @@ static inline uint32_t float_rel_to_flags(int res)
49
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
38
return flags;
50
return value;
39
}
51
}
40
52
41
+uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
53
-void qemu_get_timedate(struct tm *tm, int offset)
42
+{
54
+void qemu_get_timedate(struct tm *tm, time_t offset)
43
+ return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
44
+}
45
+
46
+uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
47
+{
48
+ return float_rel_to_flags(float16_compare(x, y, fp_status));
49
+}
50
+
51
uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
52
{
55
{
53
return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
56
time_t ti = qemu_ref_timedate(rtc_clock);
54
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
57
55
index XXXXXXX..XXXXXXX 100644
58
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
56
--- a/target/arm/translate-a64.c
57
+++ b/target/arm/translate-a64.c
58
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
59
}
59
}
60
}
60
}
61
61
62
-static void handle_fp_compare(DisasContext *s, bool is_double,
62
-int qemu_timedate_diff(struct tm *tm)
63
+static void handle_fp_compare(DisasContext *s, int size,
63
+time_t qemu_timedate_diff(struct tm *tm)
64
unsigned int rn, unsigned int rm,
65
bool cmp_with_zero, bool signal_all_nans)
66
{
64
{
67
TCGv_i64 tcg_flags = tcg_temp_new_i64();
65
time_t seconds;
68
- TCGv_ptr fpst = get_fpstatus_ptr(false);
66
69
+ TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
70
71
- if (is_double) {
72
+ if (size == MO_64) {
73
TCGv_i64 tcg_vn, tcg_vm;
74
75
tcg_vn = read_fp_dreg(s, rn);
76
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
77
tcg_temp_free_i64(tcg_vn);
78
tcg_temp_free_i64(tcg_vm);
79
} else {
80
- TCGv_i32 tcg_vn, tcg_vm;
81
+ TCGv_i32 tcg_vn = tcg_temp_new_i32();
82
+ TCGv_i32 tcg_vm = tcg_temp_new_i32();
83
84
- tcg_vn = read_fp_sreg(s, rn);
85
+ read_vec_element_i32(s, tcg_vn, rn, 0, size);
86
if (cmp_with_zero) {
87
- tcg_vm = tcg_const_i32(0);
88
+ tcg_gen_movi_i32(tcg_vm, 0);
89
} else {
90
- tcg_vm = read_fp_sreg(s, rm);
91
+ read_vec_element_i32(s, tcg_vm, rm, 0, size);
92
}
93
- if (signal_all_nans) {
94
- gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
95
- } else {
96
- gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
97
+
98
+ switch (size) {
99
+ case MO_32:
100
+ if (signal_all_nans) {
101
+ gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
102
+ } else {
103
+ gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
104
+ }
105
+ break;
106
+ case MO_16:
107
+ if (signal_all_nans) {
108
+ gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
109
+ } else {
110
+ gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
111
+ }
112
+ break;
113
+ default:
114
+ g_assert_not_reached();
115
}
116
+
117
tcg_temp_free_i32(tcg_vn);
118
tcg_temp_free_i32(tcg_vm);
119
}
120
@@ -XXX,XX +XXX,XX @@ static void handle_fp_compare(DisasContext *s, bool is_double,
121
static void disas_fp_compare(DisasContext *s, uint32_t insn)
122
{
123
unsigned int mos, type, rm, op, rn, opc, op2r;
124
+ int size;
125
126
mos = extract32(insn, 29, 3);
127
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
128
+ type = extract32(insn, 22, 2);
129
rm = extract32(insn, 16, 5);
130
op = extract32(insn, 14, 2);
131
rn = extract32(insn, 5, 5);
132
opc = extract32(insn, 3, 2);
133
op2r = extract32(insn, 0, 3);
134
135
- if (mos || op || op2r || type > 1) {
136
+ if (mos || op || op2r) {
137
+ unallocated_encoding(s);
138
+ return;
139
+ }
140
+
141
+ switch (type) {
142
+ case 0:
143
+ size = MO_32;
144
+ break;
145
+ case 1:
146
+ size = MO_64;
147
+ break;
148
+ case 3:
149
+ size = MO_16;
150
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
151
+ break;
152
+ }
153
+ /* fallthru */
154
+ default:
155
unallocated_encoding(s);
156
return;
157
}
158
@@ -XXX,XX +XXX,XX @@ static void disas_fp_compare(DisasContext *s, uint32_t insn)
159
return;
160
}
161
162
- handle_fp_compare(s, type, rn, rm, opc & 1, opc & 2);
163
+ handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
164
}
165
166
/* Floating point conditional compare
167
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
168
unsigned int mos, type, rm, cond, rn, op, nzcv;
169
TCGv_i64 tcg_flags;
170
TCGLabel *label_continue = NULL;
171
+ int size;
172
173
mos = extract32(insn, 29, 3);
174
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
175
+ type = extract32(insn, 22, 2);
176
rm = extract32(insn, 16, 5);
177
cond = extract32(insn, 12, 4);
178
rn = extract32(insn, 5, 5);
179
op = extract32(insn, 4, 1);
180
nzcv = extract32(insn, 0, 4);
181
182
- if (mos || type > 1) {
183
+ if (mos) {
184
+ unallocated_encoding(s);
185
+ return;
186
+ }
187
+
188
+ switch (type) {
189
+ case 0:
190
+ size = MO_32;
191
+ break;
192
+ case 1:
193
+ size = MO_64;
194
+ break;
195
+ case 3:
196
+ size = MO_16;
197
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
198
+ break;
199
+ }
200
+ /* fallthru */
201
+ default:
202
unallocated_encoding(s);
203
return;
204
}
205
@@ -XXX,XX +XXX,XX @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
206
gen_set_label(label_match);
207
}
208
209
- handle_fp_compare(s, type, rn, rm, false, op);
210
+ handle_fp_compare(s, size, rn, rm, false, op);
211
212
if (cond < 0x0e) {
213
gen_set_label(label_continue);
214
--
67
--
215
2.17.0
68
2.34.1
216
69
217
70
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding
[PULL 22/24] target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
1
In commit d81ce0ef2c4f105 we added an extra float_status field
1
Where architecturally one ARM_FEATURE_X flag implies another
2
fp_status_fp16 for Arm, but forgot to initialize it correctly
2
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
3
by setting it to float_tininess_before_rounding. This currently
3
set Y for it. Currently we do this in two places -- we set a few
4
will only cause problems for the new V8_FP16 feature, since the
4
flags in arm_cpu_post_init() because we need them to decide which
5
float-to-float conversion code doesn't use it yet. The effect
5
properties to create on the CPU object, and then we do the rest in
6
would be that we failed to set the Underflow IEEE exception flag
6
arm_cpu_realizefn(). However, this is fragile, because it's easy to
7
in all the cases where we should.
7
add a new property and not notice that this means that an X-implies-Y
8
8
check now has to move from realize to post-init.
9
Add the missing initialization.
9
10
10
As a specific example, the pmsav7-dregion property is conditional
11
Fixes: d81ce0ef2c4f105
11
on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
12
Cc: qemu-stable@nongnu.org
12
on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
13
rely on V8-implies-V7, which doesn't happen until the realizefn.
14
15
Move all of these X-implies-Y checks into a new function, which
16
we call at the top of arm_cpu_post_init(), so the feature bits
17
are available at that point.
18
19
This does now give us the reverse issue, that if there's a feature
20
bit which is enabled or disabled by the setting of a property then
21
then X-implies-Y features that are dependent on that property need to
22
be in realize, not in this new function. But the only one of those
23
is the "EL3 implies VBAR" which is already in the right place, so
24
putting things this way round seems better to me.
25
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
28
Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Message-id: 20180512004311.9299-16-richard.henderson@linaro.org
17
---
29
---
18
target/arm/cpu.c | 2 ++
30
target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
19
1 file changed, 2 insertions(+)
31
1 file changed, 97 insertions(+), 82 deletions(-)
20
32
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
33
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
22
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.c
35
--- a/target/arm/cpu.c
24
+++ b/target/arm/cpu.c
36
+++ b/target/arm/cpu.c
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
37
@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
26
&env->vfp.fp_status);
38
NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
27
set_float_detect_tininess(float_tininess_before_rounding,
39
}
28
&env->vfp.standard_fp_status);
40
29
+ set_float_detect_tininess(float_tininess_before_rounding,
41
+static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
30
+ &env->vfp.fp_status_f16);
42
+{
43
+ CPUARMState *env = &cpu->env;
44
+ bool no_aa32 = false;
45
+
46
+ /*
47
+ * Some features automatically imply others: set the feature
48
+ * bits explicitly for these cases.
49
+ */
50
+
51
+ if (arm_feature(env, ARM_FEATURE_M)) {
52
+ set_feature(env, ARM_FEATURE_PMSA);
53
+ }
54
+
55
+ if (arm_feature(env, ARM_FEATURE_V8)) {
56
+ if (arm_feature(env, ARM_FEATURE_M)) {
57
+ set_feature(env, ARM_FEATURE_V7);
58
+ } else {
59
+ set_feature(env, ARM_FEATURE_V7VE);
60
+ }
61
+ }
62
+
63
+ /*
64
+ * There exist AArch64 cpus without AArch32 support. When KVM
65
+ * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
66
+ * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
67
+ * As a general principle, we also do not make ID register
68
+ * consistency checks anywhere unless using TCG, because only
69
+ * for TCG would a consistency-check failure be a QEMU bug.
70
+ */
71
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
72
+ no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
73
+ }
74
+
75
+ if (arm_feature(env, ARM_FEATURE_V7VE)) {
76
+ /*
77
+ * v7 Virtualization Extensions. In real hardware this implies
78
+ * EL2 and also the presence of the Security Extensions.
79
+ * For QEMU, for backwards-compatibility we implement some
80
+ * CPUs or CPU configs which have no actual EL2 or EL3 but do
81
+ * include the various other features that V7VE implies.
82
+ * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
83
+ * Security Extensions is ARM_FEATURE_EL3.
84
+ */
85
+ assert(!tcg_enabled() || no_aa32 ||
86
+ cpu_isar_feature(aa32_arm_div, cpu));
87
+ set_feature(env, ARM_FEATURE_LPAE);
88
+ set_feature(env, ARM_FEATURE_V7);
89
+ }
90
+ if (arm_feature(env, ARM_FEATURE_V7)) {
91
+ set_feature(env, ARM_FEATURE_VAPA);
92
+ set_feature(env, ARM_FEATURE_THUMB2);
93
+ set_feature(env, ARM_FEATURE_MPIDR);
94
+ if (!arm_feature(env, ARM_FEATURE_M)) {
95
+ set_feature(env, ARM_FEATURE_V6K);
96
+ } else {
97
+ set_feature(env, ARM_FEATURE_V6);
98
+ }
99
+
100
+ /*
101
+ * Always define VBAR for V7 CPUs even if it doesn't exist in
102
+ * non-EL3 configs. This is needed by some legacy boards.
103
+ */
104
+ set_feature(env, ARM_FEATURE_VBAR);
105
+ }
106
+ if (arm_feature(env, ARM_FEATURE_V6K)) {
107
+ set_feature(env, ARM_FEATURE_V6);
108
+ set_feature(env, ARM_FEATURE_MVFR);
109
+ }
110
+ if (arm_feature(env, ARM_FEATURE_V6)) {
111
+ set_feature(env, ARM_FEATURE_V5);
112
+ if (!arm_feature(env, ARM_FEATURE_M)) {
113
+ assert(!tcg_enabled() || no_aa32 ||
114
+ cpu_isar_feature(aa32_jazelle, cpu));
115
+ set_feature(env, ARM_FEATURE_AUXCR);
116
+ }
117
+ }
118
+ if (arm_feature(env, ARM_FEATURE_V5)) {
119
+ set_feature(env, ARM_FEATURE_V4T);
120
+ }
121
+ if (arm_feature(env, ARM_FEATURE_LPAE)) {
122
+ set_feature(env, ARM_FEATURE_V7MP);
123
+ }
124
+ if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
125
+ set_feature(env, ARM_FEATURE_CBAR);
126
+ }
127
+ if (arm_feature(env, ARM_FEATURE_THUMB2) &&
128
+ !arm_feature(env, ARM_FEATURE_M)) {
129
+ set_feature(env, ARM_FEATURE_THUMB_DSP);
130
+ }
131
+}
132
+
133
void arm_cpu_post_init(Object *obj)
134
{
135
ARMCPU *cpu = ARM_CPU(obj);
136
137
- /* M profile implies PMSA. We have to do this here rather than
138
- * in realize with the other feature-implication checks because
139
- * we look at the PMSA bit to see if we should add some properties.
140
+ /*
141
+ * Some features imply others. Figure this out now, because we
142
+ * are going to look at the feature bits in deciding which
143
+ * properties to add.
144
*/
145
- if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
146
- set_feature(&cpu->env, ARM_FEATURE_PMSA);
147
- }
148
+ arm_cpu_propagate_feature_implications(cpu);
149
150
if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
151
arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
152
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
153
CPUARMState *env = &cpu->env;
154
int pagebits;
155
Error *local_err = NULL;
156
- bool no_aa32 = false;
157
158
/* Use pc-relative instructions in system-mode */
31
#ifndef CONFIG_USER_ONLY
159
#ifndef CONFIG_USER_ONLY
32
if (kvm_enabled()) {
160
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
33
kvm_arm_reset_vcpu(cpu);
161
cpu->isar.id_isar3 = u;
162
}
163
164
- /* Some features automatically imply others: */
165
- if (arm_feature(env, ARM_FEATURE_V8)) {
166
- if (arm_feature(env, ARM_FEATURE_M)) {
167
- set_feature(env, ARM_FEATURE_V7);
168
- } else {
169
- set_feature(env, ARM_FEATURE_V7VE);
170
- }
171
- }
172
-
173
- /*
174
- * There exist AArch64 cpus without AArch32 support. When KVM
175
- * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
176
- * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
177
- * As a general principle, we also do not make ID register
178
- * consistency checks anywhere unless using TCG, because only
179
- * for TCG would a consistency-check failure be a QEMU bug.
180
- */
181
- if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
182
- no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
183
- }
184
-
185
- if (arm_feature(env, ARM_FEATURE_V7VE)) {
186
- /* v7 Virtualization Extensions. In real hardware this implies
187
- * EL2 and also the presence of the Security Extensions.
188
- * For QEMU, for backwards-compatibility we implement some
189
- * CPUs or CPU configs which have no actual EL2 or EL3 but do
190
- * include the various other features that V7VE implies.
191
- * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
192
- * Security Extensions is ARM_FEATURE_EL3.
193
- */
194
- assert(!tcg_enabled() || no_aa32 ||
195
- cpu_isar_feature(aa32_arm_div, cpu));
196
- set_feature(env, ARM_FEATURE_LPAE);
197
- set_feature(env, ARM_FEATURE_V7);
198
- }
199
- if (arm_feature(env, ARM_FEATURE_V7)) {
200
- set_feature(env, ARM_FEATURE_VAPA);
201
- set_feature(env, ARM_FEATURE_THUMB2);
202
- set_feature(env, ARM_FEATURE_MPIDR);
203
- if (!arm_feature(env, ARM_FEATURE_M)) {
204
- set_feature(env, ARM_FEATURE_V6K);
205
- } else {
206
- set_feature(env, ARM_FEATURE_V6);
207
- }
208
-
209
- /* Always define VBAR for V7 CPUs even if it doesn't exist in
210
- * non-EL3 configs. This is needed by some legacy boards.
211
- */
212
- set_feature(env, ARM_FEATURE_VBAR);
213
- }
214
- if (arm_feature(env, ARM_FEATURE_V6K)) {
215
- set_feature(env, ARM_FEATURE_V6);
216
- set_feature(env, ARM_FEATURE_MVFR);
217
- }
218
- if (arm_feature(env, ARM_FEATURE_V6)) {
219
- set_feature(env, ARM_FEATURE_V5);
220
- if (!arm_feature(env, ARM_FEATURE_M)) {
221
- assert(!tcg_enabled() || no_aa32 ||
222
- cpu_isar_feature(aa32_jazelle, cpu));
223
- set_feature(env, ARM_FEATURE_AUXCR);
224
- }
225
- }
226
- if (arm_feature(env, ARM_FEATURE_V5)) {
227
- set_feature(env, ARM_FEATURE_V4T);
228
- }
229
- if (arm_feature(env, ARM_FEATURE_LPAE)) {
230
- set_feature(env, ARM_FEATURE_V7MP);
231
- }
232
- if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
233
- set_feature(env, ARM_FEATURE_CBAR);
234
- }
235
- if (arm_feature(env, ARM_FEATURE_THUMB2) &&
236
- !arm_feature(env, ARM_FEATURE_M)) {
237
- set_feature(env, ARM_FEATURE_THUMB_DSP);
238
- }
239
240
/*
241
* We rely on no XScale CPU having VFP so we can use the same bits in the
34
--
242
--
35
2.17.0
243
2.34.1
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
[PULL 23/24] hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
1
From: Alex Bennée <alex.bennee@linaro.org>
1
M-profile CPUs generally allow configuration of the number of MPU
2
regions that they have. We don't currently model this, so our
3
implementations of some of the board models provide CPUs with the
4
wrong number of regions. RTOSes like Zephyr that hardcode the
5
expected number of regions may therefore not run on the model if they
6
are set up to run on real hardware.
2
7
3
These were missed out from the rest of the half-precision work.
8
Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
9
matching the ability of hardware to configure the number of Secure
10
and NonSecure regions separately. Our actual CPU implementation
11
doesn't currently support that, and it happens that none of the MPS
12
boards we model set the number of regions differently for Secure vs
13
NonSecure, so we provide an interface to the boards and SoCs that
14
won't need to change if we ever do add that functionality in future,
15
but make it an error to configure the two properties to different
16
values.
4
17
5
Cc: qemu-stable@nongnu.org
18
(The property name on the CPU is the somewhat misnamed-for-M-profile
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
"pmsav7-dregion", so we don't follow that naming convention for
7
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
20
the properties here. The TRM doesn't say what the CPU configuration
8
Tested-by: Alex Bennée <alex.bennee@linaro.org>
21
variable names are, so we pick something, and follow the lowercase
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
22
convention we already have for properties here.)
10
Message-id: 20180512003217.9105-10-richard.henderson@linaro.org
23
11
[rth: Fix erroneous check vs type]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
26
Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
14
---
27
---
15
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
28
include/hw/arm/armv7m.h | 8 ++++++++
16
1 file changed, 25 insertions(+), 6 deletions(-)
29
hw/arm/armv7m.c | 21 +++++++++++++++++++++
30
2 files changed, 29 insertions(+)
17
31
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
32
diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
19
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/translate-a64.c
34
--- a/include/hw/arm/armv7m.h
21
+++ b/target/arm/translate-a64.c
35
+++ b/include/hw/arm/armv7m.h
22
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
36
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
23
unsigned int mos, type, rm, cond, rn, rd;
37
* + Property "vfp": enable VFP (forwarded to CPU object)
24
TCGv_i64 t_true, t_false, t_zero;
38
* + Property "dsp": enable DSP (forwarded to CPU object)
25
DisasCompare64 c;
39
* + Property "enable-bitband": expose bitbanded IO
26
+ TCGMemOp sz;
40
+ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
27
41
+ * to CPU object pmsav7-dregion property; default is whatever the default
28
mos = extract32(insn, 29, 3);
42
+ * for the CPU is)
29
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
43
+ * + Property "mpu-s-regions": number of Secure MPU regions (default is
30
+ type = extract32(insn, 22, 2);
44
+ * whatever the default for the CPU is; must currently be set to the same
31
rm = extract32(insn, 16, 5);
45
+ * value as mpu-ns-regions if the CPU implements the Security Extension)
32
cond = extract32(insn, 12, 4);
46
* + Clock input "refclk" is the external reference clock for the systick timers
33
rn = extract32(insn, 5, 5);
47
* + Clock input "cpuclk" is the main CPU clock
34
rd = extract32(insn, 0, 5);
48
*/
35
49
@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
36
- if (mos || type > 1) {
50
Object *idau;
37
+ if (mos) {
51
uint32_t init_svtor;
38
+ unallocated_encoding(s);
52
uint32_t init_nsvtor;
53
+ uint32_t mpu_ns_regions;
54
+ uint32_t mpu_s_regions;
55
bool enable_bitband;
56
bool start_powered_off;
57
bool vfp;
58
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
59
index XXXXXXX..XXXXXXX 100644
60
--- a/hw/arm/armv7m.c
61
+++ b/hw/arm/armv7m.c
62
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
63
}
64
}
65
66
+ /*
67
+ * Real M-profile hardware can be configured with a different number of
68
+ * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
69
+ * support that yet, so catch attempts to select that.
70
+ */
71
+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
72
+ s->mpu_ns_regions != s->mpu_s_regions) {
73
+ error_setg(errp,
74
+ "mpu-ns-regions and mpu-s-regions properties must have the same value");
39
+ return;
75
+ return;
40
+ }
76
+ }
77
+ if (s->mpu_ns_regions != UINT_MAX &&
78
+ object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
79
+ if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
80
+ s->mpu_ns_regions, errp)) {
81
+ return;
82
+ }
83
+ }
41
+
84
+
42
+ switch (type) {
85
/*
43
+ case 0:
86
* Tell the CPU where the NVIC is; it will fail realize if it doesn't
44
+ sz = MO_32;
87
* have one. Similarly, tell the NVIC where its CPU is.
45
+ break;
88
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
46
+ case 1:
89
false),
47
+ sz = MO_64;
90
DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
48
+ break;
91
DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
49
+ case 3:
92
+ DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
50
+ sz = MO_16;
93
+ DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
51
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
94
DEFINE_PROP_END_OF_LIST(),
52
+ break;
95
};
53
+ }
96
54
+ /* fallthru */
55
+ default:
56
unallocated_encoding(s);
57
return;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
60
return;
61
}
62
63
- /* Zero extend sreg inputs to 64 bits now. */
64
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
65
t_true = tcg_temp_new_i64();
66
t_false = tcg_temp_new_i64();
67
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
68
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
69
+ read_vec_element(s, t_true, rn, 0, sz);
70
+ read_vec_element(s, t_false, rm, 0, sz);
71
72
a64_test_cc(&c, cond);
73
t_zero = tcg_const_i64(0);
74
@@ -XXX,XX +XXX,XX @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
75
tcg_temp_free_i64(t_false);
76
a64_free_cc(&c);
77
78
- /* Note that sregs write back zeros to the high bits,
79
+ /* Note that sregs & hregs write back zeros to the high bits,
80
and we've already done the zero-extension. */
81
write_fp_dreg(s, rd, t_true);
82
tcg_temp_free_i64(t_true);
83
--
97
--
84
2.17.0
98
2.34.1
85
99
86
100
diff view generated by jsdifflib
New patch
[PULL 24/24] hw/arm: Set number of MPU regions correctly for an505, an521, an524
1
1
The IoTKit, SSE200 and SSE300 all default to 8 MPU regions. The
2
MPS2/MPS3 FPGA images don't override these except in the case of
3
AN547, which uses 16 MPU regions.
4
5
Define properties on the ARMSSE object for the MPU regions (using the
6
same names as the documented RTL configuration settings, and
7
following the pattern we already have for this device of using
8
all-caps names as the RTL does), and set them in the board code.
9
10
We don't actually need to override the default except on AN547,
11
but it's simpler code to have the board code set them always
12
rather than tracking which board subtypes want to set them to
13
a non-default value separately from what that value is.
14
15
Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
16
we now correctly use 8 MPU regions, while mps3-an547 stays at its
17
current 16 regions.
18
19
It's possible some guest code wrongly depended on the previous
20
incorrectly modeled number of memory regions. (Such guest code
21
should ideally check the number of regions via the MPU_TYPE
22
register.) The old behaviour can be obtained with additional
23
-global arguments to QEMU:
24
25
For mps2-an521 and mps2-an524:
26
-global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16
27
28
For mps2-an505:
29
-global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16
30
31
NB that the way the implementation allows this use of -global
32
is slightly fragile: if the board code explicitly sets the
33
properties on the sse-200 object, this overrides the -global
34
command line option. So we rely on:
35
- the boards that need fixing all happen to use the SSE defaults
36
- we can write the board code to only set the property if it
37
is different from the default, rather than having all boards
38
explicitly set the property
39
- the board that does need to use a non-default value happens
40
to need to set it to the same value (16) we previously used
41
This works, but there are some kinds of refactoring of the
42
mps2-tz.c code that would break the support for -global here.
43
44
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
45
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
46
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
47
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
48
Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
49
---
50
include/hw/arm/armsse.h | 5 +++++
51
hw/arm/armsse.c | 16 ++++++++++++++++
52
hw/arm/mps2-tz.c | 29 +++++++++++++++++++++++++++++
53
3 files changed, 50 insertions(+)
54
55
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/include/hw/arm/armsse.h
58
+++ b/include/hw/arm/armsse.h
59
@@ -XXX,XX +XXX,XX @@
60
* (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
61
* SSE-200 both are present; CPU0 in an SSE-200 has neither.
62
* Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
63
+ * + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
64
+ * which set the number of MPU regions on the CPUs. If there is only one
65
+ * CPU the CPU1 properties are not present.
66
* + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
67
* which are wired to its NVIC lines 32 .. n+32
68
* + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
69
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
70
uint32_t exp_numirq;
71
uint32_t sram_addr_width;
72
uint32_t init_svtor;
73
+ uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
74
+ uint32_t cpu_mpu_s[SSE_MAX_CPUS];
75
bool cpu_fpu[SSE_MAX_CPUS];
76
bool cpu_dsp[SSE_MAX_CPUS];
77
};
78
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/arm/armsse.c
81
+++ b/hw/arm/armsse.c
82
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
83
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
84
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
85
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
86
+ DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
87
+ DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
88
DEFINE_PROP_END_OF_LIST()
89
};
90
91
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
92
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
93
DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
94
DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
95
+ DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
96
+ DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
97
+ DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
98
+ DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
99
DEFINE_PROP_END_OF_LIST()
100
};
101
102
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
103
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
104
DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
105
DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
106
+ DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
107
+ DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
108
DEFINE_PROP_END_OF_LIST()
109
};
110
111
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
112
return;
113
}
114
}
115
+ if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
116
+ s->cpu_mpu_ns[i], errp)) {
117
+ return;
118
+ }
119
+ if (!object_property_set_uint(cpuobj, "mpu-s-regions",
120
+ s->cpu_mpu_s[i], errp)) {
121
+ return;
122
+ }
123
124
if (i > 0) {
125
memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
126
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/arm/mps2-tz.c
129
+++ b/hw/arm/mps2-tz.c
130
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
131
int uart_overflow_irq; /* number of the combined UART overflow IRQ */
132
uint32_t init_svtor; /* init-svtor setting for SSE */
133
uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
134
+ uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
135
+ uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
136
+ uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
137
+ uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
138
const RAMInfo *raminfo;
139
const char *armsse_type;
140
uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
141
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
142
#define MPS3_DDR_SIZE (2 * GiB)
143
#endif
144
145
+/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
146
+#define MPU_REGION_DEFAULT UINT32_MAX
147
+
148
static const uint32_t an505_oscclk[] = {
149
40000000,
150
24580000,
151
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
152
OBJECT(system_memory), &error_abort);
153
qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
154
qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
155
+ if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
156
+ qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
157
+ }
158
+ if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
159
+ qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
160
+ }
161
+ if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
162
+ if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
163
+ qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
164
+ }
165
+ if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
166
+ qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
167
+ }
168
+ }
169
qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
170
qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
171
qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
172
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
173
{
174
MachineClass *mc = MACHINE_CLASS(oc);
175
IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
176
+ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
177
178
mc->init = mps2tz_common_init;
179
mc->reset = mps2_machine_reset;
180
iic->check = mps2_tz_idau_check;
181
+
182
+ /* Most machines leave these at the SSE defaults */
183
+ mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
184
+ mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
185
+ mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
186
+ mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
187
}
188
189
static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
190
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
191
mmc->numirq = 96;
192
mmc->uart_overflow_irq = 48;
193
mmc->init_svtor = 0x00000000;
194
+ mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
195
mmc->sram_addr_width = 21;
196
mmc->raminfo = an547_raminfo;
197
mmc->armsse_type = TYPE_SSE300;
198
--
199
2.34.1
200
201
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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