Series comparison

-[Qemu-devel] [PULL 00/12] target-arm queue
+[PULL 00/24] target-arm queue
-Arm patch queue for 2.12 -- a miscellaneous collection
+Hi; here's the latest round of arm patches. I have included also
-of bug fixes.
+my patchset for the RTC devices to avoid keeping time_t and
 time_t diffs in 32-bit variables.
 thanks
 -- PMM
+The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:
-The following changes since commit fb4fe32d5b6290deabe752b51cc1cc2a9e8573db:
+  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)
   Merge remote-tracking branch 'remotes/xtensa/tags/20180409-xtensa' into staging (2018-04-10 10:22:45 +0100)
 are available in the Git repository at:
-  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180410
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831
-for you to fetch changes up to bd49e6027cbc207c87633c7add3ebd7d3474cd35:
+for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:
-  fpu: Fix rounding mode for floatN_to_uintM_round_to_zero (2018-04-10 13:02:26 +0100)
+  hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * fpu: Fix rounding mode for floatN_to_uintM_round_to_zero
+ * Some of the preliminary patches for Cortex-A710 support
- * tcg: Fix guest state corruption when running 64-bit Arm
+ * i.MX7 and i.MX6UL refactoring
-   guests on a 32-bit host (especially when using icount)
+ * Implement SRC device for i.MX7
- * linux-user/signal.c: Ensure AArch64 signal frame isn't too small
+ * Catch illegal-exception-return from EL3 with bad NSE/NS
- * cpus.c: ensure running CPU recalculates icount deadlines on timer expiry
+ * Use 64-bit offsets for holding time_t differences in RTC devices
- * target/arm: Report unsupported MPU region sizes more clearly
+ * Model correct number of MPU regions for an505, an521, an524 boards
  * hw/arm/fsl-imx: Fix introspection problem with fsl-imx6 and fsl-imx7
  * hw/arm/allwinner-a10: Do not use nd_table in instance_init function
  * hw/sd/bcm2835_sdhost: Don't raise spurious interrupts
  * hw/sd/bcm2835_sdhost: Add tracepoints
  * target-arm: Check undefined opcodes for SWP in A32 decoder
  * hw/arm/integratorcp: Don't do things that could be fatal in the instance_init
  * hw/arm: Allow manually specified /psci node
 ----------------------------------------------------------------
-Andrey Smirnov (1):
+Alex Bennée (1):
-      hw/arm: Allow manually specified /psci node
+      target/arm: properly document FEAT_CRC32
-Onur Sahin (1):
+Jean-Christophe Dubois (6):
-      target-arm: Check undefined opcodes for SWP in A32 decoder
+      Remove i.MX7 IOMUX GPR device from i.MX6UL
       Refactor i.MX6UL processor code
       Add i.MX6UL missing devices.
       Refactor i.MX7 processor code
       Add i.MX7 missing TZ devices and memory regions
       Add i.MX7 SRC device implementation
-Peter Maydell (5):
+Peter Maydell (8):
-      hw/sd/bcm2835_sdhost: Add tracepoints
+      target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
-      hw/sd/bcm2835_sdhost: Don't raise spurious interrupts
+      hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
-      target/arm: Report unsupported MPU region sizes more clearly
+      hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
-      cpus.c: ensure running CPU recalculates icount deadlines on timer expiry
+      hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
-      linux-user/signal.c: Ensure AArch64 signal frame isn't too small
+      rtc: Use time_t for passing and returning time offsets
       target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
       hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
       hw/arm: Set number of MPU regions correctly for an505, an521, an524
-Richard Henderson (2):
+Richard Henderson (9):
-      tcg: Introduce tcg_set_insn_start_param
+      target/arm: Reduce dcz_blocksize to uint8_t
-      fpu: Fix rounding mode for floatN_to_uintM_round_to_zero
+      target/arm: Allow cpu to configure GM blocksize
       target/arm: Support more GM blocksizes
       target/arm: When tag memory is not present, set MTE=1
       target/arm: Introduce make_ccsidr64
       target/arm: Apply access checks to neoverse-n1 special registers
       target/arm: Apply access checks to neoverse-v1 special registers
       target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
       target/arm: Implement FEAT_HPDS2 as a no-op
-Thomas Huth (3):
+ docs/system/arm/emulation.rst  |   2 +
-      hw/arm/integratorcp: Don't do things that could be fatal in the instance_init
+ include/hw/arm/armsse.h        |   5 +
-      hw/arm/allwinner-a10: Do not use nd_table in instance_init function
+ include/hw/arm/armv7m.h        |   8 +
-      hw/arm/fsl-imx: Fix introspection problem with fsl-imx6 and fsl-imx7
+ include/hw/arm/fsl-imx6ul.h    | 158 ++++++++++++++++---
  include/hw/arm/fsl-imx7.h      | 338 ++++++++++++++++++++++++++++++-----------
  include/hw/misc/imx7_src.h     |  66 ++++++++
  include/hw/rtc/aspeed_rtc.h    |   2 +-
  include/sysemu/rtc.h           |   4 +-
  target/arm/cpregs.h            |   2 +
  target/arm/cpu.h               |   5 +-
  target/arm/internals.h         |   6 -
  target/arm/tcg/translate.h     |   2 +
  hw/arm/armsse.c                |  16 ++
  hw/arm/armv7m.c                |  21 +++
  hw/arm/fsl-imx6ul.c            | 174 +++++++++++++--------
  hw/arm/fsl-imx7.c              | 201 +++++++++++++++++++-----
  hw/arm/mps2-tz.c               |  29 ++++
  hw/misc/imx7_src.c             | 276 +++++++++++++++++++++++++++++++++
  hw/rtc/aspeed_rtc.c            |   5 +-
  hw/rtc/m48t59.c                |   2 +-
  hw/rtc/twl92230.c              |   4 +-
  softmmu/rtc.c                  |   4 +-
  target/arm/cpu.c               | 207 ++++++++++++++-----------
  target/arm/helper.c            |  15 +-
  target/arm/tcg/cpu32.c         |   2 +-
  target/arm/tcg/cpu64.c         | 102 +++++++++----
  target/arm/tcg/helper-a64.c    |   9 ++
  target/arm/tcg/mte_helper.c    |  90 ++++++++---
  target/arm/tcg/translate-a64.c |   5 +-
  hw/misc/meson.build            |   1 +
  hw/misc/trace-events           |   4 +
 files changed, 1393 insertions(+), 372 deletions(-)
  create mode 100644 include/hw/misc/imx7_src.h
  create mode 100644 hw/misc/imx7_src.c
- target/arm/translate.h |  2 +-
- tcg/tcg.h              | 10 ++++++++++
- cpus.c                 | 10 +++++++++-
- fpu/softfloat.c        |  4 ++--
- hw/arm/allwinner-a10.c | 12 +++++------
- hw/arm/boot.c          | 10 ++++++++++
- hw/arm/fsl-imx6.c      | 14 ++++++-------
- hw/arm/fsl-imx7.c      | 13 ++++++------
- hw/arm/integratorcp.c  | 23 +++++++++++++--------
- hw/sd/bcm2835_sdhost.c | 54 ++++++++++++++++++++++++++++++++------------------
- linux-user/signal.c    |  6 ++++++
- target/arm/helper.c    |  6 +++---
- target/arm/translate.c |  9 +++++++--
- hw/sd/trace-events     |  6 ++++++
-files changed, 124 insertions(+), 55 deletions(-)

-New patch
+[PULL 01/24] target/arm: Reduce dcz_blocksize to uint8_t
+From: Richard Henderson <richard.henderson@linaro.org>
+This value is only 4 bits wide.
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230811214031.171020-2-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.h | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.h
++++ b/target/arm/cpu.h
+@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
+     bool prop_lpa2;
+     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
+-    uint32_t dcz_blocksize;
++    uint8_t dcz_blocksize;
++
+     uint64_t rvbar_prop; /* Property/input signals.  */
+     /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
+--
+.34.1

-New patch
+[PULL 02/24] target/arm: Allow cpu to configure GM blocksize
+From: Richard Henderson <richard.henderson@linaro.org>
 Previously we hard-coded the blocksize with GMID_EL1_BS.
 But the value we choose for -cpu max does not match the
 value that cortex-a710 uses.
 Mirror the way we handle dcz_blocksize.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  target/arm/cpu.h               |  2 ++
  target/arm/internals.h         |  6 -----
  target/arm/tcg/translate.h     |  2 ++
  target/arm/helper.c            | 11 +++++---
  target/arm/tcg/cpu64.c         |  1 +
  target/arm/tcg/mte_helper.c    | 46 ++++++++++++++++++++++------------
  target/arm/tcg/translate-a64.c |  5 ++--
 files changed, 45 insertions(+), 28 deletions(-)
 diff --git a/target/arm/cpu.h b/target/arm/cpu.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.h
 +++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
      /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
      uint8_t dcz_blocksize;
 +    /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
 +    uint8_t gm_blocksize;
      uint64_t rvbar_prop; /* Property/input signals.  */
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
  #endif /* !CONFIG_USER_ONLY */
 -/*
 - * The log2 of the words in the tag block, for GMID_EL1.BS.
 - * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
 - */
 -#define GMID_EL1_BS  6
 -
  /*
   * SVE predicates are 1/8 the size of SVE vectors, and cannot use
   * the same simd_desc() encoding due to restrictions on size.
 diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/translate.h
 +++ b/target/arm/tcg/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
      int8_t btype;
      /* A copy of cpu->dcz_blocksize. */
      uint8_t dcz_blocksize;
 +    /* A copy of cpu->gm_blocksize. */
 +    uint8_t gm_blocksize;
      /* True if this page is guarded.  */
      bool guarded_page;
      /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
        .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
        .access = PL1_RW, .accessfn = access_mte,
        .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
 -    { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
 -      .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
 -      .access = PL1_R, .accessfn = access_aa64_tid5,
 -      .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
      { .name = "TCO", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
        .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
       * then define only a RAZ/WI version of PSTATE.TCO.
       */
      if (cpu_isar_feature(aa64_mte, cpu)) {
 +        ARMCPRegInfo gmid_reginfo = {
 +            .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
 +            .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
 +            .access = PL1_R, .accessfn = access_aa64_tid5,
 +            .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
 +        };
 +        define_one_arm_cp_reg(cpu, &gmid_reginfo);
          define_arm_cp_regs(cpu, mte_reginfo);
          define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
      } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/cpu64.c
 +++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
      cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
      cpu->dcz_blocksize = 7; /*  512 bytes */
  #endif
 +    cpu->gm_blocksize = 6;  /*  256 bytes */
      cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
      cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/mte_helper.c
 +++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
      }
  }
 -#define LDGM_STGM_SIZE  (4 << GMID_EL1_BS)
 -
  uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
  {
      int mmu_idx = cpu_mmu_index(env, false);
      uintptr_t ra = GETPC();
 +    int gm_bs = env_archcpu(env)->gm_blocksize;
 +    int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 -    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
 +    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
      /* Trap if accessing an invalid page.  */
      tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
 +                                 gm_bs_bytes, MMU_DATA_LOAD,
 +                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
      /* The tag is squashed to zero if the page does not support tags.  */
      if (!tag_mem) {
          return 0;
      }
 -    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
      /*
 -     * We are loading 64-bits worth of tags.  The ordering of elements
 -     * within the word corresponds to a 64-bit little-endian operation.
 +     * The ordering of elements within the word corresponds to
 +     * a little-endian operation.
       */
 -    return ldq_le_p(tag_mem);
 +    switch (gm_bs) {
 +    case 6:
 +        /* 256 bytes -> 16 tags -> 64 result bits */
 +        return ldq_le_p(tag_mem);
 +    default:
 +        /* cpu configured with unsupported gm blocksize. */
 +        g_assert_not_reached();
 +    }
  }
  void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
  {
      int mmu_idx = cpu_mmu_index(env, false);
      uintptr_t ra = GETPC();
 +    int gm_bs = env_archcpu(env)->gm_blocksize;
 +    int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 -    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
 +    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
      /* Trap if accessing an invalid page.  */
      tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
 -                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
 -                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
 +                                 gm_bs_bytes, MMU_DATA_LOAD,
 +                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
      /*
       * Tag store only happens if the page support tags,
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
          return;
      }
 -    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
      /*
 -     * We are storing 64-bits worth of tags.  The ordering of elements
 -     * within the word corresponds to a 64-bit little-endian operation.
 +     * The ordering of elements within the word corresponds to
 +     * a little-endian operation.
       */
 -    stq_le_p(tag_mem, val);
 +    switch (gm_bs) {
 +    case 6:
 +        stq_le_p(tag_mem, val);
 +        break;
 +    default:
 +        /* cpu configured with unsupported gm blocksize. */
 +        g_assert_not_reached();
 +    }
  }
  void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/translate-a64.c
 +++ b/target/arm/tcg/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
          gen_helper_stgm(cpu_env, addr, tcg_rt);
      } else {
          MMUAccessType acc = MMU_DATA_STORE;
 -        int size = 4 << GMID_EL1_BS;
 +        int size = 4 << s->gm_blocksize;
          clean_addr = clean_data_tbi(s, addr);
          tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
          gen_helper_ldgm(tcg_rt, cpu_env, addr);
      } else {
          MMUAccessType acc = MMU_DATA_LOAD;
 -        int size = 4 << GMID_EL1_BS;
 +        int size = 4 << s->gm_blocksize;
          clean_addr = clean_data_tbi(s, addr);
          tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
      dc->cp_regs = arm_cpu->cp_regs;
      dc->features = env->features;
      dc->dcz_blocksize = arm_cpu->dcz_blocksize;
 +    dc->gm_blocksize = arm_cpu->gm_blocksize;
  #ifdef CONFIG_USER_ONLY
      /* In sve_probe_page, we assume TBI is enabled. */
 --
 .34.1

-[Qemu-devel] [PULL 12/12] fpu: Fix rounding mode for floatN_to_uintM_round_to_zero
+[PULL 03/24] target/arm: Support more GM blocksizes
 From: Richard Henderson <richard.henderson@linaro.org>
-We incorrectly passed in the current rounding mode
+Support all of the easy GM block sizes.
-instead of float_round_to_zero.
+Use direct memory operations, since the pointers are aligned.
 While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
 an atomic store of one nibble.  This is not difficult, but there
 is also no point in supporting it until required.
 Note that cortex-a710 sets GM blocksize to match its cacheline
 size of 64 bytes.  I expect many implementations will also
 match the cacheline, which makes 16 bytes very unlikely.
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180410055912.934-1-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- fpu/softfloat.c | 4 ++--
+ target/arm/cpu.c            | 18 +++++++++---
-file changed, 2 insertions(+), 2 deletions(-)
+ target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
 files changed, 62 insertions(+), 12 deletions(-)
-diff --git a/fpu/softfloat.c b/fpu/softfloat.c
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/fpu/softfloat.c
+--- a/target/arm/cpu.c
-+++ b/fpu/softfloat.c
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ uint ## isz ## _t float ## fsz ## _to_uint ## isz ## _round_to_zero     \
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-  (float ## fsz a, float_status *s)                                      \
+                                        ID_PFR1, VIRTUALIZATION, 0);
- {                                                                       \
+     }
-     FloatParts p = float ## fsz ## _unpack_canonical(a, s);             \
--    return round_to_uint_and_pack(p, s->float_rounding_mode,            \
++    if (cpu_isar_feature(aa64_mte, cpu)) {
--                                 UINT ## isz ## _MAX, s);               \
++        /*
-+    return round_to_uint_and_pack(p, float_round_to_zero,               \
++         * The architectural range of GM blocksize is 2-6, however qemu
-+                                  UINT ## isz ## _MAX, s);              \
++         * doesn't support blocksize of 2 (see HELPER(ldgm)).
 +         */
 +        if (tcg_enabled()) {
 +            assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
 +        }
 +
  #ifndef CONFIG_USER_ONLY
 -    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
          /*
           * Disable the MTE feature bits if we do not have tag-memory
           * provided by the machine.
           */
 -        cpu->isar.id_aa64pfr1 =
 -            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
 -    }
 +        if (cpu->tag_memory == NULL) {
 +            cpu->isar.id_aa64pfr1 =
 +                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
 +        }
  #endif
 +    }
      if (tcg_enabled()) {
          /*
 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/mte_helper.c
 +++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
      int gm_bs = env_archcpu(env)->gm_blocksize;
      int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 +    uint64_t ret;
 +    int shift;
      ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
      /*
       * The ordering of elements within the word corresponds to
 -     * a little-endian operation.
 +     * a little-endian operation.  Computation of shift comes from
 +     *
 +     *     index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
 +     *     data<index*4+3:index*4> = tag
 +     *
 +     * Because of the alignment of ptr above, BS=6 has shift=0.
 +     * All memory operations are aligned.  Defer support for BS=2,
 +     * requiring insertion or extraction of a nibble, until we
 +     * support a cpu that requires it.
       */
      switch (gm_bs) {
 +    case 3:
 +        /* 32 bytes -> 2 tags -> 8 result bits */
 +        ret = *(uint8_t *)tag_mem;
 +        break;
 +    case 4:
 +        /* 64 bytes -> 4 tags -> 16 result bits */
 +        ret = cpu_to_le16(*(uint16_t *)tag_mem);
 +        break;
 +    case 5:
 +        /* 128 bytes -> 8 tags -> 32 result bits */
 +        ret = cpu_to_le32(*(uint32_t *)tag_mem);
 +        break;
      case 6:
          /* 256 bytes -> 16 tags -> 64 result bits */
 -        return ldq_le_p(tag_mem);
 +        return cpu_to_le64(*(uint64_t *)tag_mem);
      default:
 -        /* cpu configured with unsupported gm blocksize. */
 +        /*
 +         * CPU configured with unsupported/invalid gm blocksize.
 +         * This is detected early in arm_cpu_realizefn.
 +         */
          g_assert_not_reached();
      }
 +    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
 +    return ret << shift;
  }
- FLOAT_TO_UINT(16, 16)
+ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
      int gm_bs = env_archcpu(env)->gm_blocksize;
      int gm_bs_bytes = 4 << gm_bs;
      void *tag_mem;
 +    int shift;
      ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
          return;
      }
 -    /*
 -     * The ordering of elements within the word corresponds to
 -     * a little-endian operation.
 -     */
 +    /* See LDGM for comments on BS and on shift.  */
 +    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
 +    val >>= shift;
      switch (gm_bs) {
 +    case 3:
 +        /* 32 bytes -> 2 tags -> 8 result bits */
 +        *(uint8_t *)tag_mem = val;
 +        break;
 +    case 4:
 +        /* 64 bytes -> 4 tags -> 16 result bits */
 +        *(uint16_t *)tag_mem = cpu_to_le16(val);
 +        break;
 +    case 5:
 +        /* 128 bytes -> 8 tags -> 32 result bits */
 +        *(uint32_t *)tag_mem = cpu_to_le32(val);
 +        break;
      case 6:
 -        stq_le_p(tag_mem, val);
 +        /* 256 bytes -> 16 tags -> 64 result bits */
 +        *(uint64_t *)tag_mem = cpu_to_le64(val);
          break;
      default:
          /* cpu configured with unsupported gm blocksize. */
 --
-.16.2
+.34.1

-New patch
+[PULL 04/24] target/arm: When tag memory is not present, set MTE=1
+From: Richard Henderson <richard.henderson@linaro.org>
+When the cpu support MTE, but the system does not, reduce cpu
+support to user instructions at EL0 instead of completely
+disabling MTE.  If we encounter a cpu implementation which does
+something else, we can revisit this setting.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.c | 7 ++++---
+file changed, 4 insertions(+), 3 deletions(-)
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+ #ifndef CONFIG_USER_ONLY
+         /*
+-         * Disable the MTE feature bits if we do not have tag-memory
+-         * provided by the machine.
++         * If we do not have tag-memory provided by the machine,
++         * reduce MTE support to instructions enabled at EL0.
++         * This matches Cortex-A710 BROADCASTMTE input being LOW.
+          */
+         if (cpu->tag_memory == NULL) {
+             cpu->isar.id_aa64pfr1 =
+-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
++                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
+         }
+ #endif
+     }
+--
+.34.1

-New patch
+[PULL 05/24] target/arm: Introduce make_ccsidr64
+From: Richard Henderson <richard.henderson@linaro.org>
+Do not hard-code the constants for Neoverse V1.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
+file changed, 32 insertions(+), 16 deletions(-)
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu/module.h"
+ #include "qapi/visitor.h"
+ #include "hw/qdev-properties.h"
++#include "qemu/units.h"
+ #include "internals.h"
+ #include "cpregs.h"
++static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
++                              unsigned cachesize)
++{
++    unsigned lg_linesize = ctz32(linesize);
++    unsigned sets;
++
++    /*
++     * The 64-bit CCSIDR_EL1 format is:
++     *   [55:32] number of sets - 1
++     *   [23:3]  associativity - 1
++     *   [2:0]   log2(linesize) - 4
++     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
++     */
++    assert(assoc != 0);
++    assert(is_power_of_2(linesize));
++    assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
++
++    /* sets * associativity * linesize == cachesize. */
++    sets = cachesize / (assoc * linesize);
++    assert(cachesize % (assoc * linesize) == 0);
++
++    return ((uint64_t)(sets - 1) << 32)
++         | ((assoc - 1) << 3)
++         | (lg_linesize - 4);
++}
++
+ static void aarch64_a35_initfn(Object *obj)
+ {
+     ARMCPU *cpu = ARM_CPU(obj);
+@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
+      * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
+      * but also says it implements CCIDX, which means they should be
+      * 64-bit format. So we here use values which are based on the textual
+-     * information in chapter 2 of the TRM (and on the fact that
+-     * sets * associativity * linesize == cachesize).
+-     *
+-     * The 64-bit CCSIDR_EL1 format is:
+-     *   [55:32] number of sets - 1
+-     *   [23:3]  associativity - 1
+-     *   [2:0]   log2(linesize) - 4
+-     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
+-     *
+-     * L1: 4-way set associative 64-byte line size, total size 64K,
+-     * so sets is 256.
++     * information in chapter 2 of the TRM:
+      *
++     * L1: 4-way set associative 64-byte line size, total size 64K.
+      * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
+-     * We pick 1MB, so this has 2048 sets.
+-     *
+      * L3: No L3 (this matches the CLIDR_EL1 value).
+      */
+-    cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
+-    cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
+-    cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
++    cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
++    cpu->ccsidr[1] = cpu->ccsidr[0];                 /* L1 icache */
++    cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB);  /* L2 cache */
+     /* From 3.2.115 SCTLR_EL3 */
+     cpu->reset_sctlr = 0x30c50838;
+--
+.34.1

-[Qemu-devel] [PULL 11/12] tcg: Introduce tcg_set_insn_start_param
+[PULL 06/24] target/arm: Apply access checks to neoverse-n1 special registers
 From: Richard Henderson <richard.henderson@linaro.org>
-The parameters for tcg_gen_insn_start are target_ulong, which may be split
+Access to many of the special registers is enabled or disabled
-into two TCGArg parameters for storage in the opcode on 32-bit hosts.
+by ACTLR_EL[23], which we implement as constant 0, which means
 that all writes outside EL3 should trap.
-Fixes the ARM target and its direct use of tcg_set_insn_param, which would
-set the wrong argument in the 64-on-32 case.
-Cc: qemu-stable@nongnu.org
-Reported-by: alarson@ddci.com
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20180410003558.2470-1-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.h |  2 +-
+ target/arm/cpregs.h    |  2 ++
- tcg/tcg.h              | 10 ++++++++++
+ target/arm/helper.c    |  4 ++--
-files changed, 11 insertions(+), 1 deletion(-)
+ target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
 files changed, 41 insertions(+), 11 deletions(-)
-diff --git a/target/arm/translate.h b/target/arm/translate.h
+diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.h
+--- a/target/arm/cpregs.h
-+++ b/target/arm/translate.h
++++ b/target/arm/cpregs.h
-@@ -XXX,XX +XXX,XX @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
+@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
-     /* We check and clear insn_start_idx to catch multiple updates.  */
+ #endif
-     assert(s->insn_start != NULL);
--    tcg_set_insn_param(s->insn_start, 2, syn);
++CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
-+    tcg_set_insn_start_param(s->insn_start, 2, syn);
++
-     s->insn_start = NULL;
+ #endif /* TARGET_ARM_CPREGS_H */
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
  }
-diff --git a/tcg/tcg.h b/tcg/tcg.h
+ /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM.  */
 -static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
 -                                      bool isread)
 +CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
 +                               bool isread)
  {
      if (arm_current_el(env) == 1) {
          uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
 diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
 index XXXXXXX..XXXXXXX 100644
---- a/tcg/tcg.h
+--- a/target/arm/tcg/cpu64.c
-+++ b/tcg/tcg.h
++++ b/target/arm/tcg/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
+@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
-     op->args[arg] = v;
+     /* TODO:  Add A64FX specific HPC extension registers */
  }
-+static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
++static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
 +                                     bool read)
 +{
-+#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
++    if (!read) {
-+    tcg_set_insn_param(op, arg, v);
++        int el = arm_current_el(env);
-+#else
++
-+    tcg_set_insn_param(op, arg * 2, v);
++        /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
-+    tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
++        if (el < 2 && arm_is_el2_enabled(env)) {
-+#endif
++            return CP_ACCESS_TRAP_EL2;
 +        }
 +        /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
 +        if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
 +            return CP_ACCESS_TRAP_EL3;
 +        }
 +    }
 +    return CP_ACCESS_OK;
 +}
 +
- /* The last op that was emitted.  */
+ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
- static inline TCGOp *tcg_last_op(void)
+     { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
- {
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      /* Traps and enables are the same as for TCR_EL1. */
 +      .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
      { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      /*
       * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
       * (and in particular its system registers).
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
        .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
      { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
 +      .accessfn = access_actlr_w },
      { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
        .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
        .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
      { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
      { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
        .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
 -      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 +      .accessfn = access_actlr_w },
  };
  static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
 --
-.16.2
+.34.1

-New patch
+[PULL 07/24] target/arm: Apply access checks to neoverse-v1 special registers
+From: Richard Henderson <richard.henderson@linaro.org>
+There is only one additional EL1 register modeled, which
+also needs to use access_actlr_w.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/tcg/cpu64.c | 3 ++-
+file changed, 2 insertions(+), 1 deletion(-)
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
+ static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
+     { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
+-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
++      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
++      .accessfn = access_actlr_w },
+     { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
+       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
+       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+--
+.34.1

-New patch
+[PULL 08/24] target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
+From: Richard Henderson <richard.henderson@linaro.org>
+Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
+external to the cpu, which is out of scope for QEMU.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/arm/cpu.c | 3 +++
+file changed, 3 insertions(+)
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/cpu.c
++++ b/target/arm/cpu.c
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+         /* FEAT_SPE (Statistical Profiling Extension) */
+         cpu->isar.id_aa64dfr0 =
+             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
++        /* FEAT_TRBE (Trace Buffer Extension) */
++        cpu->isar.id_aa64dfr0 =
++            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
+         /* FEAT_TRF (Self-hosted Trace Extension) */
+         cpu->isar.id_aa64dfr0 =
+             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
+--
+.34.1

-New patch
+[PULL 09/24] target/arm: Implement FEAT_HPDS2 as a no-op
+From: Richard Henderson <richard.henderson@linaro.org>
+This feature allows the operating system to set TCR_ELx.HWU*
+to allow the implementation to use the PBHA bits from the
+block and page descriptors for for IMPLEMENTATION DEFINED
+purposes.  Since QEMU has no need to use these bits, we may
+simply ignore them.
+Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ docs/system/arm/emulation.rst | 1 +
+ target/arm/tcg/cpu32.c        | 2 +-
+ target/arm/tcg/cpu64.c        | 2 +-
+files changed, 3 insertions(+), 2 deletions(-)
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
+index XXXXXXX..XXXXXXX 100644
+--- a/docs/system/arm/emulation.rst
++++ b/docs/system/arm/emulation.rst
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
+ - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
+ - FEAT_HCX (Support for the HCRX_EL2 register)
+ - FEAT_HPDS (Hierarchical permission disables)
++- FEAT_HPDS2 (Translation table page-based hardware attributes)
+ - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
+ - FEAT_IDST (ID space trap handling)
+ - FEAT_IESB (Implicit error synchronization event)
+diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu32.c
++++ b/target/arm/tcg/cpu32.c
+@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
+     cpu->isar.id_mmfr3 = t;
+     t = cpu->isar.id_mmfr4;
+-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
++    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
+     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
+     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
+     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/cpu64.c
++++ b/target/arm/tcg/cpu64.c
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
+     t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
+     t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
+-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
++    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2);     /* FEAT_HPDS2 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
+     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
+     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
+--
+.34.1

-[Qemu-devel] [PULL 10/12] linux-user/signal.c: Ensure AArch64 signal frame isn't too small
+[PULL 10/24] target/arm: properly document FEAT_CRC32
-The AArch64 signal frame design was extended for SVE in commit
+From: Alex Bennée <alex.bennee@linaro.org>
 c5931de0ac77388096d79ceb, so that instead of having a fixed setup we
 now add various records to the frame, with some of them possibly
 overflowing into an extra space outside the original 4K reserved
 block in the target_sigcontext.  However, we failed to ensure that we
 always at least allocate the 4K reserved block.  This is ABI, and
 some userspace programs rely on it.  In particular the dash shell
 would segfault if the frame wasn't as big enough.
-(Compare the kernel's sigframe_size() function in
+This is a mandatory feature for Armv8.1 architectures but we don't
-arch/arm64/kernel/signal.c.)
+state the feature clearly in our emulation list. Also include
 FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.
-Reported-by: Richard Henwood <richard.henwood@arm.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Laurent Vivier <laurent@vivier.eu>
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
-Message-id: 20180409140714.26841-1-peter.maydell@linaro.org
+Cc: qemu-stable@nongnu.org
-Fixes: https://bugs.launchpad.net/bugs/1761535
+Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
-Fixes: 8c5931de0ac77388096d79ceb
+[PMM: pluralize 'instructions' in docs]
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- linux-user/signal.c | 6 ++++++
+ docs/system/arm/emulation.rst | 1 +
-file changed, 6 insertions(+)
+ target/arm/tcg/cpu64.c        | 2 +-
 files changed, 2 insertions(+), 1 deletion(-)
-diff --git a/linux-user/signal.c b/linux-user/signal.c
+diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/signal.c
+--- a/docs/system/arm/emulation.rst
-+++ b/linux-user/signal.c
++++ b/docs/system/arm/emulation.rst
-@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
+@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
-     fr_ofs = layout.total_size;
+ - FEAT_BBM at level 2 (Translation table break-before-make levels)
-     layout.total_size += sizeof(struct target_rt_frame_record);
+ - FEAT_BF16 (AArch64 BFloat16 instructions)
+ - FEAT_BTI (Branch Target Identification)
-+    /* We must always provide at least the standard 4K reserved space,
++- FEAT_CRC32 (CRC32 instructions)
-+     * even if we don't use all of it (this is part of the ABI)
+ - FEAT_CSV2 (Cache speculation variant 2)
-+     */
+ - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)
-+    layout.total_size = MAX(layout.total_size,
+ - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
-+                            sizeof(struct target_rt_sigframe));
+diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
-+
+index XXXXXXX..XXXXXXX 100644
-     frame_addr = get_sigframe(ka, env, layout.total_size);
+--- a/target/arm/tcg/cpu64.c
-     trace_user_setup_frame(env, frame_addr);
++++ b/target/arm/tcg/cpu64.c
-     if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
+@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
      t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2);      /* FEAT_PMULL */
      t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);     /* FEAT_SHA1 */
      t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2);     /* FEAT_SHA512 */
 -    t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
 +    t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);    /* FEAT_CRC32 */
      t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);   /* FEAT_LSE */
      t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);      /* FEAT_RDM */
      t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);     /* FEAT_SHA3 */
 --
-.16.2
+.34.1

-New patch
+[PULL 11/24] Remove i.MX7 IOMUX GPR device from i.MX6UL
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
+In particular, register 22 is not present on i.MX6UL and this is actualy
+The only register that is really emulated in the i.MX7 IOMUX GPR device.
+Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
+as an unimplemented device at the same bus adress and the 2 instantiations
+were actualy colliding. So we go back to the unimplemented device for now.
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx6ul.h |  2 --
+ hw/arm/fsl-imx6ul.c         | 11 -----------
+files changed, 13 deletions(-)
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@
+ #include "hw/misc/imx6ul_ccm.h"
+ #include "hw/misc/imx6_src.h"
+ #include "hw/misc/imx7_snvs.h"
+-#include "hw/misc/imx7_gpr.h"
+ #include "hw/intc/imx_gpcv2.h"
+ #include "hw/watchdog/wdt_imx2.h"
+ #include "hw/gpio/imx_gpio.h"
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
+     IMX6SRCState       src;
+     IMX7SNVSState      snvs;
+     IMXGPCv2State      gpcv2;
+-    IMX7GPRState       gpr;
+     IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
+     IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
+     IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx6ul.c
++++ b/hw/arm/fsl-imx6ul.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+      */
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
+-    /*
+-     * GPR
+-     */
+-    object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
+-
+     /*
+      * GPIOs 1 to 5
+      */
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX6UL_WDOGn_IRQ[i]));
+     }
+-    /*
+-     * GPR
+-     */
+-    sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
+-
+     /*
+      * SDMA
+      */
+--
+.34.1

-New patch
+[PULL 12/24] Refactor i.MX6UL processor code
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
+* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
+* Use those newly defined named constants whenever possible.
+* Standardize the way we init a familly of unimplemented devices
+  - SAI
+  - PWM
+  - CAN
+* Add/rework few comments
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
+Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
+ hw/arm/fsl-imx6ul.c         | 147 ++++++++++++++++++++++-----------
+files changed, 232 insertions(+), 71 deletions(-)
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/fsl-imx6ul.h
++++ b/include/hw/arm/fsl-imx6ul.h
+@@ -XXX,XX +XXX,XX @@
+ #include "exec/memory.h"
+ #include "cpu.h"
+ #include "qom/object.h"
++#include "qemu/units.h"
+ #define TYPE_FSL_IMX6UL "fsl-imx6ul"
+ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
+     FSL_IMX6UL_NUM_ADCS         = 2,
+     FSL_IMX6UL_NUM_USB_PHYS     = 2,
+     FSL_IMX6UL_NUM_USBS         = 2,
++    FSL_IMX6UL_NUM_SAIS         = 3,
++    FSL_IMX6UL_NUM_CANS         = 2,
++    FSL_IMX6UL_NUM_PWMS         = 4,
+ };
+ struct FslIMX6ULState {
+@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
+ enum FslIMX6ULMemoryMap {
+     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
+-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
++    FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
+     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
+-    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
+-    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
+-    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
+-    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
++    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
+-    /* AIPS-2 */
++    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
++    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
++
++    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
++    FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
++
++    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
++    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
++
++    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
++    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
++
++    /* AIPS-2 Begin */
+     FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
++
+     FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
++
+     FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
+     FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
+     FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
+     FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
++
+     FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
++
+     FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
++    FSL_IMX6UL_QSPI_SIZE            = 0x500,
++
+     FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
++    FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
++
+     FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
++    FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
++
+     FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
++    FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
++
+     FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
++    FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
++
+     FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
++    FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
++    FSL_IMX6UL_LCDIF_SIZE           = 0x100,
++
+     FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
++    FSL_IMX6UL_CSI_SIZE             = 0x100,
++
+     FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
++    FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
++    FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
++
+     FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
++    FSL_IMX6UL_EIM_SIZE             = 0x100,
++
+     FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
++
+     FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
++    FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
++
+     FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
++    FSL_IMX6UL_ROMCP_SIZE           = 0x300,
++
+     FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
+     FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
+     FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
++
+     FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
+     FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
++    FSL_IMX6UL_ADCn_SIZE            = 0x100,
++
+     FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
+     FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
+-    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
+-    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
+-    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
+-    FSL_IMX6UL_USBO2_USB_ADDR       = 0x02184000,
+-    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
+-    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
+-    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
+-    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
+-    /* AIPS-1 */
++    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
++    FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
++
++    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
++
++    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
++    FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
++    FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
++
++    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
++    FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
++
++    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
++    FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
++
++    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
++    FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
++
++    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
++    FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
++    /* AIPS-2 End */
++
++    /* AIPS-1 Begin */
+     FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
+     FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
+     FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
+     FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
++
+     FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
++    FSL_IMX6UL_SDMA_SIZE            = 0x300,
++
+     FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
++
+     FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
++    FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
++
+     FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
++    FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
++
+     FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
++
+     FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
++
+     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
+     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
++
+     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
++
+     FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
+-    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
+     FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
+-    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
++
+     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
++    FSL_IMX6UL_ANALOG_SIZE          = 0x300,
++
+     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
++
+     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
+     FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
++
+     FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
++    FSL_IMX6UL_KPP_SIZE             = 0x10,
++
+     FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
++
+     FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
++    FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
++
+     FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
+     FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
+     FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
+     FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
+     FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
++
+     FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
++
+     FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
+     FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
++    FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
++
+     FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
+     FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
+     FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
+     FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
++    FSL_IMX6UL_PWMn_SIZE            = 0x20,
++
+     FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
++    FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
++
+     FSL_IMX6UL_BEE_ADDR             = 0x02044000,
++    FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
++
+     FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
++    FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
++
+     FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
++    FSL_IMX6UL_SPBA_SIZE            = 0x100,
++
+     FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
++    FSL_IMX6UL_ASRC_SIZE            = 0x100,
++
+     FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
+     FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
+     FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
++    FSL_IMX6UL_SAIn_SIZE            = 0x200,
++
+     FSL_IMX6UL_UART8_ADDR           = 0x02024000,
+     FSL_IMX6UL_UART1_ADDR           = 0x02020000,
+     FSL_IMX6UL_UART7_ADDR           = 0x02018000,
++
+     FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
+     FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
+     FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
+     FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
++
+     FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
++    FSL_IMX6UL_SPDIF_SIZE           = 0x100,
++    /* AIPS-1 End */
++
++    FSL_IMX6UL_BCH_ADDR             = 0x01808000,
++    FSL_IMX6UL_BCH_SIZE             = 0x200,
++
++    FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
++    FSL_IMX6UL_GPMI_SIZE            = 0x200,
+     FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
+-    FSL_IMX6UL_APBH_DMA_SIZE        = (32 * 1024),
++    FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
+     FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
+     FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
+-    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = 0x00060000,
++    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
++
+     FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
+-    FSL_IMX6UL_OCRAM_MEM_SIZE       = 0x00020000,
++    FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
++
+     FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
+-    FSL_IMX6UL_CAAM_MEM_SIZE        = 0x00008000,
++    FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
++
+     FSL_IMX6UL_ROM_ADDR             = 0x00000000,
+-    FSL_IMX6UL_ROM_SIZE             = 0x00018000,
++    FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
+ };
+ enum FslIMX6ULIRQs {
+diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/fsl-imx6ul.c
++++ b/hw/arm/fsl-imx6ul.c
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
+     /*
+-     * GPIOs 1 to 5
++     * GPIOs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
+         snprintf(name, NAME_SIZE, "gpio%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * GPT 1, 2
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
+         snprintf(name, NAME_SIZE, "gpt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * EPIT 1, 2
++     * EPITs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
+         snprintf(name, NAME_SIZE, "epit%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * eCSPI
++     * eCSPIs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
+         snprintf(name, NAME_SIZE, "spi%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * I2C
++     * I2Cs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
+         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
+         snprintf(name, NAME_SIZE, "uart%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
+         snprintf(name, NAME_SIZE, "eth%d", i);
+         object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
+     }
+-    /* USB */
++    /*
++     * USB PHYs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+         snprintf(name, NAME_SIZE, "usbphy%d", i);
+         object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
+     }
++
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+         snprintf(name, NAME_SIZE, "usb%d", i);
+         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
+     }
+     /*
+-     * SDHCI
++     * SDHCIs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+         snprintf(name, NAME_SIZE, "usdhc%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
+     }
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
+         snprintf(name, NAME_SIZE, "wdt%d", i);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+      * A7MPCORE DAP
+      */
+     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
+-                                0x100000);
++                                FSL_IMX6UL_A7MPCORE_DAP_SIZE);
+     /*
+-     * GPT 1, 2
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
+         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * EPIT 1, 2
++     * EPITs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
+         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * GPIO
++     * GPIOs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
+         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * IOMUXC and IOMUXC_GPR
++     * IOMUXC
+      */
+-    for (i = 0; i < 1; i++) {
+-        static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
+-            FSL_IMX6UL_IOMUXC_ADDR,
+-            FSL_IMX6UL_IOMUXC_GPR_ADDR,
+-        };
+-
+-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
+-        create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
+-    }
++    create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
++                                FSL_IMX6UL_IOMUXC_SIZE);
++    create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
++                                FSL_IMX6UL_IOMUXC_GPR_SIZE);
+     /*
+      * CCM
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
+-    /* Initialize all ECSPI */
++    /*
++     * ECSPIs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
+         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
+             FSL_IMX6UL_ECSPI1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * I2C
++     * I2Cs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
+         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
+         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      *
+      * We must use two loops since phy_connected affects the other interface
+      * and we have to set all properties before calling sysbus_realize().
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
+     }
+-    /* USB */
++    /*
++     * USB PHYs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
++        static const hwaddr
++                     FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
++            FSL_IMX6UL_USBPHY1_ADDR,
++            FSL_IMX6UL_USBPHY2_ADDR,
++        };
++
+         sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
+         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
+-                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
++                        FSL_IMX6UL_USB_PHYn_ADDR[i]);
+     }
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
++        static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
++            FSL_IMX6UL_USBO2_USB1_ADDR,
++            FSL_IMX6UL_USBO2_USB2_ADDR,
++        };
++
+         static const int FSL_IMX6UL_USBn_IRQ[] = {
+             FSL_IMX6UL_USB1_IRQ,
+             FSL_IMX6UL_USB2_IRQ,
+         };
++
+         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
+         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
+-                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
++                        FSL_IMX6UL_USB02_USBn_ADDR[i]);
+         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+                                             FSL_IMX6UL_USBn_IRQ[i]));
+     }
+     /*
+-     * USDHC
++     * USDHCs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
+         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
+         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+             FSL_IMX6UL_WDOG2_ADDR,
+             FSL_IMX6UL_WDOG3_ADDR,
+         };
++
+         static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
+             FSL_IMX6UL_WDOG1_IRQ,
+             FSL_IMX6UL_WDOG2_IRQ,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+     /*
+      * SDMA
+      */
+-    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
++    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
++                                FSL_IMX6UL_SDMA_SIZE);
+     /*
+-     * SAI (Audio SSI (Synchronous Serial Interface))
++     * SAIs (Audio SSI (Synchronous Serial Interface))
+      */
+-    create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
+-    create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
+-    create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
++        static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
++            FSL_IMX6UL_SAI1_ADDR,
++            FSL_IMX6UL_SAI2_ADDR,
++            FSL_IMX6UL_SAI3_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "sai%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
++                                    FSL_IMX6UL_SAIn_SIZE);
++    }
+     /*
+-     * PWM
++     * PWMs
+      */
+-    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
+-    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
+-    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
+-    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
++        static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
++            FSL_IMX6UL_PWM1_ADDR,
++            FSL_IMX6UL_PWM2_ADDR,
++            FSL_IMX6UL_PWM3_ADDR,
++            FSL_IMX6UL_PWM4_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "pwm%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
++                                    FSL_IMX6UL_PWMn_SIZE);
++    }
+     /*
+      * Audio ASRC (asynchronous sample rate converter)
+      */
+-    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
++    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
++                                FSL_IMX6UL_ASRC_SIZE);
+     /*
+-     * CAN
++     * CANs
+      */
+-    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
+-    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
++    for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
++        static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
++            FSL_IMX6UL_CAN1_ADDR,
++            FSL_IMX6UL_CAN2_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "can%d", i);
++        create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
++                                    FSL_IMX6UL_CANn_SIZE);
++    }
+     /*
+      * APHB_DMA
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
+         };
+         snprintf(name, NAME_SIZE, "adc%d", i);
+-        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
++        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
++                                    FSL_IMX6UL_ADCn_SIZE);
+     }
+     /*
+      * LCD
+      */
+-    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
++    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
++                                FSL_IMX6UL_LCDIF_SIZE);
+     /*
+      * ROM memory
+--
+.34.1

-[Qemu-devel] [PULL 03/12] target-arm: Check undefined opcodes for SWP in A32 decoder
+[PULL 13/24] Add i.MX6UL missing devices.
-From: Onur Sahin <onursahin08@gmail.com>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-Make sure we are not treating architecturally Undefined instructions
+* Add TZASC as unimplemented device.
-as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A
+  - Allow bare metal application to access this (unimplemented) device
-specification. Bits [21:20] must be zero for this to be a SWP or SWPB.
+* Add CSU as unimplemented device.
-We also choose to UNDEF for the architecturally UNPREDICTABLE case of
+  - Allow bare metal application to access this (unimplemented) device
-bits [11:8] not being zero.
+* Add 4 missing PWM devices
-Signed-off-by: Onur Sahin <onursahin08@gmail.com>
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-[PMM: tweaked commit message]
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.c | 9 +++++++--
+ include/hw/arm/fsl-imx6ul.h |  2 +-
-file changed, 7 insertions(+), 2 deletions(-)
+ hw/arm/fsl-imx6ul.c         | 16 ++++++++++++++++
 files changed, 17 insertions(+), 1 deletion(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/include/hw/arm/fsl-imx6ul.h
-+++ b/target/arm/translate.c
++++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
-                             }
+     FSL_IMX6UL_NUM_USBS         = 2,
-                         }
+     FSL_IMX6UL_NUM_SAIS         = 3,
-                         tcg_temp_free_i32(addr);
+     FSL_IMX6UL_NUM_CANS         = 2,
--                    } else {
+-    FSL_IMX6UL_NUM_PWMS         = 4,
-+                    } else if ((insn & 0x00300f00) == 0) {
++    FSL_IMX6UL_NUM_PWMS         = 8,
-+                        /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
+ };
-+                        *  - SWP, SWPB
-+                        */
+ struct FslIMX6ULState {
 diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx6ul.c
 +++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
              FSL_IMX6UL_PWM2_ADDR,
              FSL_IMX6UL_PWM3_ADDR,
              FSL_IMX6UL_PWM4_ADDR,
 +            FSL_IMX6UL_PWM5_ADDR,
 +            FSL_IMX6UL_PWM6_ADDR,
 +            FSL_IMX6UL_PWM7_ADDR,
 +            FSL_IMX6UL_PWM8_ADDR,
          };
          snprintf(name, NAME_SIZE, "pwm%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
                                  FSL_IMX6UL_LCDIF_SIZE);
 +    /*
 +     * CSU
 +     */
 +    create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
 +                                FSL_IMX6UL_CSU_SIZE);
 +
-                         TCGv taddr;
++    /*
-                         TCGMemOp opc = s->be_data;
++     * TZASC
++     */
--                        /* SWP instruction */
++    create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
-                         rm = (insn) & 0xf;
++                                FSL_IMX6UL_TZASC_SIZE);
++
-                         if (insn & (1 << 22)) {
+     /*
-@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
+      * ROM memory
-                                                 get_mem_index(s), opc);
+      */
                          tcg_temp_free(taddr);
                          store_reg(s, rd, tmp);
 +                    } else {
 +                        goto illegal_op;
                      }
                  }
              } else {
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 07/12] hw/arm/fsl-imx: Fix introspection problem with fsl-imx6 and fsl-imx7
+[PULL 14/24] Refactor i.MX7 processor code
-From: Thomas Huth <thuth@redhat.com>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-QEMU currently exits unexpectedly when trying to introspect the fsl-imx6
+* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
-and fsl-imx7 devices on systems with many SMP CPUs:
+* Use those newly defined named constants whenever possible.
 * Standardize the way we init a familly of unimplemented devices
   - SAI
   - PWM
   - CAN
 * Add/rework few comments
-$ echo "{'execute':'qmp_capabilities'}"\
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-       "{'execute':'device-list-properties',"\
+Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
        " 'arguments':{'typename':'fsl,imx6'}}" \
        | arm-softmmu/qemu-system-arm -M virt,accel=qtest -qmp stdio -smp 8
 {"QMP": {"version": {"qemu": {"micro": 91, "minor": 11, "major": 2},
  "package": "build-all"}, "capabilities": []}}
 {"return": {}}
 fsl,imx6: Only 4 CPUs are supported (8 requested)
 And:
 $ echo "{'execute':'qmp_capabilities'}"\
        "{'execute':'device-list-properties',"\
        " 'arguments':{'typename':'fsl,imx7'}}" \
        | arm-softmmu/qemu-system-arm -M raspi2,accel=qtest -qmp stdio
 {"QMP": {"version": {"qemu": {"micro": 91, "minor": 11, "major": 2},
  "package": "build-all"}, "capabilities": []}}
 {"return": {}}
 fsl,imx7: Only 2 CPUs are supported (4 requested)
 This happens because these devices are doing an exit() from their
 instance_init function - which should never be done since instance_init
 can be called at any time for device introspection! Fix it by moving
 the deadly check into the realize() function instead.
 Signed-off-by: Thomas Huth <thuth@redhat.com>
 Message-id: 1522908551-14885-1-git-send-email-thuth@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/fsl-imx6.c | 14 +++++++-------
+ include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
- hw/arm/fsl-imx7.c | 13 +++++++------
+ hw/arm/fsl-imx7.c         | 130 ++++++++++-----
-files changed, 14 insertions(+), 13 deletions(-)
+files changed, 335 insertions(+), 125 deletions(-)
-diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/fsl-imx6.c
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/hw/arm/fsl-imx6.c
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@
-     char name[NAME_SIZE];
+ #include "hw/misc/imx7_ccm.h"
-     int i;
+ #include "hw/misc/imx7_snvs.h"
+ #include "hw/misc/imx7_gpr.h"
--    if (smp_cpus > FSL_IMX6_NUM_CPUS) {
+-#include "hw/misc/imx6_src.h"
--        error_report("%s: Only %d CPUs are supported (%d requested)",
+ #include "hw/watchdog/wdt_imx2.h"
--                     TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
+ #include "hw/gpio/imx_gpio.h"
--        exit(1);
+ #include "hw/char/imx_serial.h"
--    }
+@@ -XXX,XX +XXX,XX @@
  #include "hw/usb/chipidea.h"
  #include "cpu.h"
  #include "qom/object.h"
 +#include "qemu/units.h"
  #define TYPE_FSL_IMX7 "fsl-imx7"
  OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
      FSL_IMX7_NUM_ECSPIS       = 4,
      FSL_IMX7_NUM_USBS         = 3,
      FSL_IMX7_NUM_ADCS         = 2,
 +    FSL_IMX7_NUM_SAIS         = 3,
 +    FSL_IMX7_NUM_CANS         = 2,
 +    FSL_IMX7_NUM_PWMS         = 4,
  };
  struct FslIMX7State {
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
  enum FslIMX7MemoryMap {
      FSL_IMX7_MMDC_ADDR            = 0x80000000,
 -    FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
 +    FSL_IMX7_MMDC_SIZE            = (2 * GiB),
 -    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
 -    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
 -    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
 -    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
 -    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
 -    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
 -    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
 +    FSL_IMX7_QSPI1_MEM_ADDR       = 0x60000000,
 +    FSL_IMX7_QSPI1_MEM_SIZE       = (256 * MiB),
 -    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
 +    FSL_IMX7_PCIE1_MEM_ADDR       = 0x40000000,
 +    FSL_IMX7_PCIE1_MEM_SIZE       = (256 * MiB),
 -    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
 -    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
 -    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
 -    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
 +    FSL_IMX7_QSPI1_RX_BUF_ADDR    = 0x34000000,
 +    FSL_IMX7_QSPI1_RX_BUF_SIZE    = (32 * MiB),
 -    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
 +    /* PCIe Peripherals */
 +    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 -    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
 -    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
 -    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
 -    FSL_IMX7_GPT4_ADDR            = 0x30300000,
 +    /* MMAP Peripherals */
 +    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
 +    FSL_IMX7_DMA_APBH_SIZE        = 0x8000,
 -    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
 -    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
 -    FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
 +    /* GPV configuration */
 +    FSL_IMX7_GPV6_ADDR            = 0x32600000,
 +    FSL_IMX7_GPV5_ADDR            = 0x32500000,
 +    FSL_IMX7_GPV4_ADDR            = 0x32400000,
 +    FSL_IMX7_GPV3_ADDR            = 0x32300000,
 +    FSL_IMX7_GPV2_ADDR            = 0x32200000,
 +    FSL_IMX7_GPV1_ADDR            = 0x32100000,
 +    FSL_IMX7_GPV0_ADDR            = 0x32000000,
 +    FSL_IMX7_GPVn_SIZE            = (1 * MiB),
 -    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
 -    FSL_IMX7_OCOTP_SIZE           = 0x10000,
 +    /* Arm Peripherals */
 +    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
 -    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
 -    FSL_IMX7_SNVS_ADDR            = 0x30370000,
 -    FSL_IMX7_CCM_ADDR             = 0x30380000,
 +    /* AIPS-3 Begin */
 -    FSL_IMX7_SRC_ADDR             = 0x30390000,
 -    FSL_IMX7_SRC_SIZE             = 0x1000,
 +    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
 +    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 -    FSL_IMX7_ADC1_ADDR            = 0x30610000,
 -    FSL_IMX7_ADC2_ADDR            = 0x30620000,
 -    FSL_IMX7_ADCn_SIZE            = 0x1000,
 +    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
 +    FSL_IMX7_SDMA_SIZE            = (4 * KiB),
 -    FSL_IMX7_PWM1_ADDR            = 0x30660000,
 -    FSL_IMX7_PWM2_ADDR            = 0x30670000,
 -    FSL_IMX7_PWM3_ADDR            = 0x30680000,
 -    FSL_IMX7_PWM4_ADDR            = 0x30690000,
 -    FSL_IMX7_PWMn_SIZE            = 0x10000,
 +    FSL_IMX7_EIM_ADDR             = 0x30BC0000,
 +    FSL_IMX7_EIM_SIZE             = (4 * KiB),
 -    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
 -    FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
 +    FSL_IMX7_QSPI_ADDR            = 0x30BB0000,
 +    FSL_IMX7_QSPI_SIZE            = 0x8000,
 -    FSL_IMX7_GPC_ADDR             = 0x303A0000,
 +    FSL_IMX7_SIM2_ADDR            = 0x30BA0000,
 +    FSL_IMX7_SIM1_ADDR            = 0x30B90000,
 +    FSL_IMX7_SIMn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
 +    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
 +    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
 +
 +    FSL_IMX7_USB3_ADDR            = 0x30B30000,
 +    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
 +    FSL_IMX7_USB2_ADDR            = 0x30B20000,
 +    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
 +    FSL_IMX7_USB1_ADDR            = 0x30B10000,
 +    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
 +    FSL_IMX7_USBMISCn_SIZE        = 0x200,
 +
 +    FSL_IMX7_USB_PL301_ADDR       = 0x30AD0000,
 +    FSL_IMX7_USB_PL301_SIZE       = (64 * KiB),
 +
 +    FSL_IMX7_SEMAPHORE_HS_ADDR    = 0x30AC0000,
 +    FSL_IMX7_SEMAPHORE_HS_SIZE    = (64 * KiB),
 +
 +    FSL_IMX7_MUB_ADDR             = 0x30AB0000,
 +    FSL_IMX7_MUA_ADDR             = 0x30AA0000,
 +    FSL_IMX7_MUn_SIZE             = (KiB),
 +
 +    FSL_IMX7_UART7_ADDR           = 0x30A90000,
 +    FSL_IMX7_UART6_ADDR           = 0x30A80000,
 +    FSL_IMX7_UART5_ADDR           = 0x30A70000,
 +    FSL_IMX7_UART4_ADDR           = 0x30A60000,
 +
 +    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
 +    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
 +    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
 +    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
 +
 +    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
 +    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
 +    FSL_IMX7_CANn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_AIPS3_CONF_ADDR      = 0x309F0000,
 +    FSL_IMX7_AIPS3_CONF_SIZE      = (64 * KiB),
      FSL_IMX7_CAAM_ADDR            = 0x30900000,
 -    FSL_IMX7_CAAM_SIZE            = 0x40000,
 +    FSL_IMX7_CAAM_SIZE            = (256 * KiB),
 -    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
 -    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
 -    FSL_IMX7_CANn_SIZE            = 0x10000,
 +    FSL_IMX7_SPBA_ADDR            = 0x308F0000,
 +    FSL_IMX7_SPBA_SIZE            = (4 * KiB),
 -    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
 -    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
 -    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
 -    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
 +    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
 +    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
 +    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
 +    FSL_IMX7_SAIn_SIZE            = (4 * KiB),
 -    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
 -    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
 -    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
 -    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
 -
--    for (i = 0; i < smp_cpus; i++) {
+-    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
-+    for (i = 0; i < MIN(smp_cpus, FSL_IMX6_NUM_CPUS); i++) {
+-    FSL_IMX7_LCDIF_SIZE           = 0x1000,
-         object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
+-
-                           "cortex-a9-" TYPE_ARM_CPU);
+-    FSL_IMX7_UART1_ADDR           = 0x30860000,
-         snprintf(name, NAME_SIZE, "cpu%d", i);
++    FSL_IMX7_UART3_ADDR           = 0x30880000,
-@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
+     /*
-     uint16_t i;
+      * Some versions of the reference manual claim that UART2 is @
-     Error *err = NULL;
+      * 0x30870000, but experiments with HW + DT files in upstream
+@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
-+    if (smp_cpus > FSL_IMX6_NUM_CPUS) {
+      * actually located @ 0x30890000
-+        error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
+      */
-+                   TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
+     FSL_IMX7_UART2_ADDR           = 0x30890000,
-+        return;
+-    FSL_IMX7_UART3_ADDR           = 0x30880000,
-+    }
+-    FSL_IMX7_UART4_ADDR           = 0x30A60000,
-+
+-    FSL_IMX7_UART5_ADDR           = 0x30A70000,
-     for (i = 0; i < smp_cpus; i++) {
+-    FSL_IMX7_UART6_ADDR           = 0x30A80000,
+-    FSL_IMX7_UART7_ADDR           = 0x30A90000,
-         /* On uniprocessor, the CBAR is set to 0 */
++    FSL_IMX7_UART1_ADDR           = 0x30860000,
 -    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
 -    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
 -    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
 -    FSL_IMX7_SAIn_SIZE            = 0x10000,
 +    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
 +    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
 +    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
 +    FSL_IMX7_ECSPIn_SIZE          = (4 * KiB),
 -    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 -    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
 +    /* AIPS-3 End */
 -    FSL_IMX7_USB1_ADDR            = 0x30B10000,
 -    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
 -    FSL_IMX7_USB2_ADDR            = 0x30B20000,
 -    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
 -    FSL_IMX7_USB3_ADDR            = 0x30B30000,
 -    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
 -    FSL_IMX7_USBMISCn_SIZE        = 0x200,
 +    /* AIPS-2 Begin */
 -    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
 -    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
 -    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
 +    FSL_IMX7_AXI_DEBUG_MON_ADDR   = 0x307E0000,
 +    FSL_IMX7_AXI_DEBUG_MON_SIZE   = (64 * KiB),
 -    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
 -    FSL_IMX7_SDMA_SIZE            = 0x1000,
 +    FSL_IMX7_PERFMON2_ADDR        = 0x307D0000,
 +    FSL_IMX7_PERFMON1_ADDR        = 0x307C0000,
 +    FSL_IMX7_PERFMONn_SIZE        = (64 * KiB),
 +
 +    FSL_IMX7_DDRC_ADDR            = 0x307A0000,
 +    FSL_IMX7_DDRC_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_DDRC_PHY_ADDR        = 0x30790000,
 +    FSL_IMX7_DDRC_PHY_SIZE        = (4 * KiB),
 +
 +    FSL_IMX7_TZASC_ADDR           = 0x30780000,
 +    FSL_IMX7_TZASC_SIZE           = (64 * KiB),
 +
 +    FSL_IMX7_MIPI_DSI_ADDR        = 0x30760000,
 +    FSL_IMX7_MIPI_DSI_SIZE        = (4 * KiB),
 +
 +    FSL_IMX7_MIPI_CSI_ADDR        = 0x30750000,
 +    FSL_IMX7_MIPI_CSI_SIZE        = 0x4000,
 +
 +    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
 +    FSL_IMX7_LCDIF_SIZE           = 0x8000,
 +
 +    FSL_IMX7_CSI_ADDR             = 0x30710000,
 +    FSL_IMX7_CSI_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_PXP_ADDR             = 0x30700000,
 +    FSL_IMX7_PXP_SIZE             = 0x4000,
 +
 +    FSL_IMX7_EPDC_ADDR            = 0x306F0000,
 +    FSL_IMX7_EPDC_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
 +    FSL_IMX7_PCIE_PHY_SIZE        = (4 * KiB),
 +
 +    FSL_IMX7_SYSCNT_CTRL_ADDR     = 0x306C0000,
 +    FSL_IMX7_SYSCNT_CMP_ADDR      = 0x306B0000,
 +    FSL_IMX7_SYSCNT_RD_ADDR       = 0x306A0000,
 +
 +    FSL_IMX7_PWM4_ADDR            = 0x30690000,
 +    FSL_IMX7_PWM3_ADDR            = 0x30680000,
 +    FSL_IMX7_PWM2_ADDR            = 0x30670000,
 +    FSL_IMX7_PWM1_ADDR            = 0x30660000,
 +    FSL_IMX7_PWMn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_FlEXTIMER2_ADDR      = 0x30650000,
 +    FSL_IMX7_FlEXTIMER1_ADDR      = 0x30640000,
 +    FSL_IMX7_FLEXTIMERn_SIZE      = (4 * KiB),
 +
 +    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
 +
 +    FSL_IMX7_ADC2_ADDR            = 0x30620000,
 +    FSL_IMX7_ADC1_ADDR            = 0x30610000,
 +    FSL_IMX7_ADCn_SIZE            = (4 * KiB),
 +
 +    FSL_IMX7_AIPS2_CONF_ADDR      = 0x305F0000,
 +    FSL_IMX7_AIPS2_CONF_SIZE      = (64 * KiB),
 +
 +    /* AIPS-2 End */
 +
 +    /* AIPS-1 Begin */
 +
 +    FSL_IMX7_CSU_ADDR             = 0x303E0000,
 +    FSL_IMX7_CSU_SIZE             = (64 * KiB),
 +
 +    FSL_IMX7_RDC_ADDR             = 0x303D0000,
 +    FSL_IMX7_RDC_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_SEMAPHORE2_ADDR      = 0x303C0000,
 +    FSL_IMX7_SEMAPHORE1_ADDR      = 0x303B0000,
 +    FSL_IMX7_SEMAPHOREn_SIZE      = (4 * KiB),
 +
 +    FSL_IMX7_GPC_ADDR             = 0x303A0000,
 +
 +    FSL_IMX7_SRC_ADDR             = 0x30390000,
 +    FSL_IMX7_SRC_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_CCM_ADDR             = 0x30380000,
 +
 +    FSL_IMX7_SNVS_HP_ADDR         = 0x30370000,
 +
 +    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
 +
 +    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
 +    FSL_IMX7_OCOTP_SIZE           = 0x10000,
 +
 +    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
 +    FSL_IMX7_IOMUXC_GPR_SIZE      = (4 * KiB),
 +
 +    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
 +    FSL_IMX7_IOMUXC_SIZE          = (4 * KiB),
 +
 +    FSL_IMX7_KPP_ADDR             = 0x30320000,
 +    FSL_IMX7_KPP_SIZE             = (4 * KiB),
 +
 +    FSL_IMX7_ROMCP_ADDR           = 0x30310000,
 +    FSL_IMX7_ROMCP_SIZE           = (4 * KiB),
 +
 +    FSL_IMX7_GPT4_ADDR            = 0x30300000,
 +    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
 +    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
 +    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
 +
 +    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
 +    FSL_IMX7_IOMUXC_LPSR_SIZE     = (4 * KiB),
 +
 +    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
 +    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
 +    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
 +    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
 +
 +    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
 +
 +    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
 +    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
 +    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
 +    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
 +    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
 +    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
 +    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
 +
 +    FSL_IMX7_AIPS1_CONF_ADDR      = 0x301F0000,
 +    FSL_IMX7_AIPS1_CONF_SIZE      = (64 * KiB),
 -    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
      FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
 +    FSL_IMX7_A7MPCORE_DAP_SIZE    = (1 * MiB),
 -    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 -    FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
 +    /* AIPS-1 End */
 -    FSL_IMX7_GPR_ADDR             = 0x30340000,
 +    FSL_IMX7_EIM_CS0_ADDR         = 0x28000000,
 +    FSL_IMX7_EIM_CS0_SIZE         = (128 * MiB),
 -    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
 -    FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
 +    FSL_IMX7_OCRAM_PXP_ADDR       = 0x00940000,
 +    FSL_IMX7_OCRAM_PXP_SIZE       = (32 * KiB),
 +
 +    FSL_IMX7_OCRAM_EPDC_ADDR      = 0x00920000,
 +    FSL_IMX7_OCRAM_EPDC_SIZE      = (128 * KiB),
 +
 +    FSL_IMX7_OCRAM_MEM_ADDR       = 0x00900000,
 +    FSL_IMX7_OCRAM_MEM_SIZE       = (128 * KiB),
 +
 +    FSL_IMX7_TCMU_ADDR            = 0x00800000,
 +    FSL_IMX7_TCMU_SIZE            = (32 * KiB),
 +
 +    FSL_IMX7_TCML_ADDR            = 0x007F8000,
 +    FSL_IMX7_TCML_SIZE            = (32 * KiB),
 +
 +    FSL_IMX7_OCRAM_S_ADDR         = 0x00180000,
 +    FSL_IMX7_OCRAM_S_SIZE         = (32 * KiB),
 +
 +    FSL_IMX7_CAAM_MEM_ADDR        = 0x00100000,
 +    FSL_IMX7_CAAM_MEM_SIZE        = (32 * KiB),
 +
 +    FSL_IMX7_ROM_ADDR             = 0x00000000,
 +    FSL_IMX7_ROM_SIZE             = (96 * KiB),
  };
  enum FslIMX7IRQs {
 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx7.c
 +++ b/hw/arm/fsl-imx7.c
 @@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      char name[NAME_SIZE];
      int i;
--    if (smp_cpus > FSL_IMX7_NUM_CPUS) {
++    /*
--        error_report("%s: Only %d CPUs are supported (%d requested)",
++     * CPUs
--                     TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
++     */
--        exit(1);
+     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
 -    }
 -    for (i = 0; i < smp_cpus; i++) {
 +    for (i = 0; i < MIN(smp_cpus, FSL_IMX7_NUM_CPUS); i++) {
          object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
                            ARM_CPU_TYPE_NAME("cortex-a7"));
          snprintf(name, NAME_SIZE, "cpu%d", i);
-@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+         object_initialize_child(obj, name, &s->cpu[i],
-     qemu_irq irq;
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
-     char name[NAME_SIZE];
+                             TYPE_A15MPCORE_PRIV);
-+    if (smp_cpus > FSL_IMX7_NUM_CPUS) {
+     /*
-+        error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
+-     * GPIOs 1 to 7
-+                   TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
++     * GPIOs
-+        return;
+      */
-+    }
+     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
-+
+         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      }
      /*
 -     * GPT1, 2, 3, 4
 +     * GPTs
       */
      for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
          snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
       */
      object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 +    /*
 +     * ECSPIs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
          snprintf(name, NAME_SIZE, "spi%d", i + 1);
          object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
      }
 -
 +    /*
 +     * I2Cs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
          snprintf(name, NAME_SIZE, "i2c%d", i + 1);
          object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
      }
      /*
 -     * UART
 +     * UARTs
       */
      for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
              snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      }
      /*
 -     * Ethernet
 +     * Ethernets
       */
      for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
              snprintf(name, NAME_SIZE, "eth%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      }
      /*
 -     * SDHCI
 +     * SDHCIs
       */
      for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
              snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
      /*
 -     * Watchdog
 +     * Watchdogs
       */
      for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
              snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
       */
      object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
 +    /*
 +     * PCIE
 +     */
      object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 +    /*
 +     * USBs
 +     */
      for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
          snprintf(name, NAME_SIZE, "usb%d", i);
          object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
          return;
      }
 +    /*
 +     * CPUs
 +     */
      for (i = 0; i < smp_cpus; i++) {
          o = OBJECT(&s->cpu[i]);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+      * A7MPCORE DAP
+      */
+     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
+-                                0x100000);
++                                FSL_IMX7_A7MPCORE_DAP_SIZE);
+     /*
+-     * GPT1, 2, 3, 4
++     * GPTs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
+         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX7_GPTn_IRQ[i]));
+     }
++    /*
++     * GPIOs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
+         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
+             FSL_IMX7_GPIO1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     /*
+      * IOMUXC and IOMUXC_LPSR
+      */
+-    for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
+-        static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
+-            FSL_IMX7_IOMUXC_ADDR,
+-            FSL_IMX7_IOMUXC_LPSR_ADDR,
+-        };
+-
+-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
+-        create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
+-                                    FSL_IMX7_IOMUXCn_SIZE);
+-    }
++    create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
++                                FSL_IMX7_IOMUXC_SIZE);
++    create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
++                                FSL_IMX7_IOMUXC_LPSR_SIZE);
+     /*
+      * CCM
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
+-    /* Initialize all ECSPI */
++    /*
++     * ECSPIs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
+         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
+             FSL_IMX7_ECSPI1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+                                             FSL_IMX7_SPIn_IRQ[i]));
+     }
++    /*
++     * I2Cs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
+         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
+             FSL_IMX7_I2C1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * UART
++     * UARTs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
+         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * Ethernet
++     * Ethernets
+      *
+      * We must use two loops since phy_connected affects the other interface
+      * and we have to set all properties before calling sysbus_realize().
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     }
+     /*
+-     * USDHC
++     * USDHCs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
+         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+      * SNVS
+      */
+     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
+     /*
+      * SRC
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
+     /*
+-     * Watchdog
++     * Watchdogs
+      */
+     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
+         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
+     /*
+-     * PWM
++     * PWMs
+      */
+-    create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
+-    create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
+-    create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
+-    create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
++    for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
++        static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
++            FSL_IMX7_PWM1_ADDR,
++            FSL_IMX7_PWM2_ADDR,
++            FSL_IMX7_PWM3_ADDR,
++            FSL_IMX7_PWM4_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "pwm%d", i);
++        create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
++                                    FSL_IMX7_PWMn_SIZE);
++    }
+     /*
+-     * CAN
++     * CANs
+      */
+-    create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
+-    create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
++    for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
++        static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
++            FSL_IMX7_CAN1_ADDR,
++            FSL_IMX7_CAN2_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "can%d", i);
++        create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
++                                    FSL_IMX7_CANn_SIZE);
++    }
+     /*
+-     * SAI (Audio SSI (Synchronous Serial Interface))
++     * SAIs (Audio SSI (Synchronous Serial Interface))
+      */
+-    create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
+-    create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
+-    create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
++    for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
++        static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
++            FSL_IMX7_SAI1_ADDR,
++            FSL_IMX7_SAI2_ADDR,
++            FSL_IMX7_SAI3_ADDR,
++        };
++
++        snprintf(name, NAME_SIZE, "sai%d", i);
++        create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
++                                    FSL_IMX7_SAIn_SIZE);
++    }
+     /*
+      * OCOTP
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
+                                 FSL_IMX7_OCOTP_SIZE);
++    /*
++     * GPR
++     */
+     sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
+-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
++    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
++    /*
++     * PCIE
++     */
+     sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
+     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
+     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
+-
++    /*
++     * USBs
++     */
+     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
+         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
+             FSL_IMX7_USBMISC1_ADDR,
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
+      */
+     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
+                                 FSL_IMX7_PCIE_PHY_SIZE);
++
+ }
+ static Property fsl_imx7_properties[] = {
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 06/12] hw/arm/allwinner-a10: Do not use nd_table in instance_init function
+[PULL 15/24] Add i.MX7 missing TZ devices and memory regions
-From: Thomas Huth <thuth@redhat.com>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-The instance_init function of a device can be called at any time, even
+* Add TZASC as unimplemented device.
-if the device is not going to be used (i.e. not going to be realized).
+  - Allow bare metal application to access this (unimplemented) device
-So a instance_init function must not do things that could cause QEMU
+* Add CSU as unimplemented device.
-to exit, like calling qemu_check_nic_model(&nd_table[0], ...) for example.
+  - Allow bare metal application to access this (unimplemented) device
-But this is what the instance_init function of the allwinner-a10 device
+* Add various memory segments
-is currently doing - and this causes QEMU to quit unexpectedly when
+  - OCRAM
-you run the 'device-list-properties' QMP command for example:
+  - OCRAM EPDC
   - OCRAM PXP
   - OCRAM S
   - ROM
   - CAAM
-$ echo "{'execute':'qmp_capabilities'}"\
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-       "{'execute':'device-list-properties',"\
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-       " 'arguments':{'typename':'allwinner-a10'}}" \
+Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
        | arm-softmmu/qemu-system-arm -M mps2-an505,accel=qtest -qmp stdio
 {"QMP": {"version": {"qemu": {"micro": 91, "minor": 11, "major": 2},
  "package": "build-all"}, "capabilities": []}}
 {"return": {}}
 Unsupported NIC model: lan9118
 ... and QEMU quits after printing the last line (which should not happen
 just because of running 'device-list-properties' here).
 And with the cubieboard, this even causes QEMU to abort():
 $ echo "{'execute':'qmp_capabilities'}"\
        "{'execute':'device-list-properties',"\
        " 'arguments':{'typename':'allwinner-a10'}}" \
        | arm-softmmu/qemu-system-arm -M cubieboard,accel=qtest -qmp stdio
 {"QMP": {"version": {"qemu": {"micro": 91, "minor": 11, "major": 2},
  "package": "build-all"}, "capabilities": []}}
 {"return": {}}
 Unexpected error in error_set_from_qdev_prop_error() at hw/core/qdev-properties.c:1095:
 Property 'allwinner-emac.netdev' can't take value 'hub0port0', it's in use
 Aborted (core dumped)
 To fix the problem we've got to move the offending code to the realize
 function instead.
 Signed-off-by: Thomas Huth <thuth@redhat.com>
 Message-id: 1522862420-7484-1-git-send-email-thuth@redhat.com
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/allwinner-a10.c | 12 ++++++------
+ include/hw/arm/fsl-imx7.h |  7 +++++
-file changed, 6 insertions(+), 6 deletions(-)
+ hw/arm/fsl-imx7.c         | 63 +++++++++++++++++++++++++++++++++++++++
 files changed, 70 insertions(+)
-diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
+diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/allwinner-a10.c
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/hw/arm/allwinner-a10.c
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
+     IMX7GPRState       gpr;
-     object_initialize(&s->emac, sizeof(s->emac), TYPE_AW_EMAC);
+     ChipideaState      usb[FSL_IMX7_NUM_USBS];
-     qdev_set_parent_bus(DEVICE(&s->emac), sysbus_get_default());
+     DesignwarePCIEHost pcie;
--    /* FIXME use qdev NIC properties instead of nd_table[] */
++    MemoryRegion       rom;
--    if (nd_table[0].used) {
++    MemoryRegion       caam;
--        qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
++    MemoryRegion       ocram;
--        qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
++    MemoryRegion       ocram_epdc;
--    }
++    MemoryRegion       ocram_pxp;
++    MemoryRegion       ocram_s;
-     object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI);
++
-     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
+     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
-@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
+     bool               phy_connected[FSL_IMX7_NUM_ETHS];
-     sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
+ };
-     sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
+diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
+index XXXXXXX..XXXXXXX 100644
-+    /* FIXME use qdev NIC properties instead of nd_table[] */
+--- a/hw/arm/fsl-imx7.c
-+    if (nd_table[0].used) {
++++ b/hw/arm/fsl-imx7.c
-+        qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
+@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
-+        qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
+     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
-+    }
+                                 FSL_IMX7_PCIE_PHY_SIZE);
-     object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
-     if (err != NULL) {
++    /*
-         error_propagate(errp, err);
++     * CSU
-@@ -XXX,XX +XXX,XX @@ static void aw_a10_class_init(ObjectClass *oc, void *data)
++     */
-     DeviceClass *dc = DEVICE_CLASS(oc);
++    create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
++                                FSL_IMX7_CSU_SIZE);
-     dc->realize = aw_a10_realize;
++
--    /* Reason: Uses serial_hds in realize and nd_table in instance_init */
++    /*
-+    /* Reason: Uses serial_hds and nd_table in realize function */
++     * TZASC
-     dc->user_creatable = false;
++     */
 +    create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
 +                                FSL_IMX7_TZASC_SIZE);
 +
 +    /*
 +     * OCRAM memory
 +     */
 +    memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
 +                           FSL_IMX7_OCRAM_MEM_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
 +                                &s->ocram);
 +
 +    /*
 +     * OCRAM EPDC memory
 +     */
 +    memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
 +                           FSL_IMX7_OCRAM_EPDC_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
 +                                &s->ocram_epdc);
 +
 +    /*
 +     * OCRAM PXP memory
 +     */
 +    memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
 +                           FSL_IMX7_OCRAM_PXP_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
 +                                &s->ocram_pxp);
 +
 +    /*
 +     * OCRAM_S memory
 +     */
 +    memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
 +                           FSL_IMX7_OCRAM_S_SIZE,
 +                           &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
 +                                &s->ocram_s);
 +
 +    /*
 +     * ROM memory
 +     */
 +    memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
 +                           FSL_IMX7_ROM_SIZE, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
 +                                &s->rom);
 +
 +    /*
 +     * CAAM memory
 +     */
 +    memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
 +                           FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
 +    memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
 +                                &s->caam);
  }
+ static Property fsl_imx7_properties[] = {
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 02/12] hw/arm/integratorcp: Don't do things that could be fatal in the instance_init
+[PULL 16/24] Add i.MX7 SRC device implementation
-From: Thomas Huth <thuth@redhat.com>
+From: Jean-Christophe Dubois <jcd@tribudubois.net>
-An instance_init function must not fail - and might be called multiple times,
+The SRC device is normally used to start the secondary CPU.
-e.g. during device introspection with the 'device-list-properties' QMP
-command. Since the integratorcm device ignores this rule, QEMU currently
+When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
-aborts in this case (though it really should not):
+is installing at boot time and therefore the fact that the SRC device is
+unimplemented is hidden as Qemu respond directly to PSCI requets without
-echo "{'execute':'qmp_capabilities'}"\
+using the SRC device.
-     "{'execute':'device-list-properties',"\
-     "'arguments':{'typename':'integrator_core'}}" \
+But if you try to run a more bare metal application (maybe uboot itself),
-     | arm-softmmu/qemu-system-arm -M integratorcp,accel=qtest -qmp stdio
+then it is not possible to start the secondary CPU as the SRC is an
-{"QMP": {"version": {"qemu": {"micro": 91, "minor": 11, "major": 2},
+unimplemented device.
- "package": "build-all"}, "capabilities": []}}
-{"return": {}}
+This patch adds the ability to start the secondary CPU through the SRC
-RAMBlock "integrator.flash" already registered, abort!
+device so that you can use this feature in bare metal applications.
-Aborted (core dumped)
+Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
-Move the problematic code to the realize() function instead to fix this
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-problem.
+Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
 Reviewed-by: Philippe Mathieu-DaudÃ© <f4bug@amsat.org>
 Signed-off-by: Thomas Huth <thuth@redhat.com>
 Message-id: 1522906473-11252-1-git-send-email-thuth@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/integratorcp.c | 23 +++++++++++++++--------
+ include/hw/arm/fsl-imx7.h  |   3 +-
-file changed, 15 insertions(+), 8 deletions(-)
+ include/hw/misc/imx7_src.h |  66 +++++++++
+ hw/arm/fsl-imx7.c          |   8 +-
-diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
+ hw/misc/imx7_src.c         | 276 +++++++++++++++++++++++++++++++++++++
  hw/misc/meson.build        |   1 +
  hw/misc/trace-events       |   4 +
 files changed, 356 insertions(+), 2 deletions(-)
  create mode 100644 include/hw/misc/imx7_src.h
  create mode 100644 hw/misc/imx7_src.c
 diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/integratorcp.c
+--- a/include/hw/arm/fsl-imx7.h
-+++ b/hw/arm/integratorcp.c
++++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps integratorcm_ops = {
+@@ -XXX,XX +XXX,XX @@
- static void integratorcm_init(Object *obj)
+ #include "hw/misc/imx7_ccm.h"
- {
+ #include "hw/misc/imx7_snvs.h"
-     IntegratorCMState *s = INTEGRATOR_CM(obj);
+ #include "hw/misc/imx7_gpr.h"
--    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
++#include "hw/misc/imx7_src.h"
+ #include "hw/watchdog/wdt_imx2.h"
-     s->cm_osc = 0x01000048;
+ #include "hw/gpio/imx_gpio.h"
-     /* ??? What should the high bits of this value be?  */
+ #include "hw/char/imx_serial.h"
-@@ -XXX,XX +XXX,XX @@ static void integratorcm_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
-     s->cm_init = 0x00000112;
+     IMX7CCMState       ccm;
-     s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
+     IMX7AnalogState    analog;
-);
+     IMX7SNVSState      snvs;
--    memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000,
++    IMX7SRCState       src;
--                           &error_fatal);
+     IMXGPCv2State      gpcv2;
+     IMXSPIState        spi[FSL_IMX7_NUM_ECSPIS];
--    memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s,
+     IMXI2CState        i2c[FSL_IMX7_NUM_I2CS];
--                          "integratorcm", 0x00800000);
+@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
--    sysbus_init_mmio(dev, &s->iomem);
+     FSL_IMX7_GPC_ADDR             = 0x303A0000,
--
--    integratorcm_do_remap(s);
+     FSL_IMX7_SRC_ADDR             = 0x30390000,
-     /* ??? Save/restore.  */
+-    FSL_IMX7_SRC_SIZE             = (4 * KiB),
- }
+     FSL_IMX7_CCM_ADDR             = 0x30380000,
- static void integratorcm_realize(DeviceState *d, Error **errp)
- {
+diff --git a/include/hw/misc/imx7_src.h b/include/hw/misc/imx7_src.h
-     IntegratorCMState *s = INTEGRATOR_CM(d);
+new file mode 100644
-+    SysBusDevice *dev = SYS_BUS_DEVICE(d);
+index XXXXXXX..XXXXXXX
-+    Error *local_err = NULL;
+--- /dev/null
-+
++++ b/include/hw/misc/imx7_src.h
-+    memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000,
+@@ -XXX,XX +XXX,XX @@
-+                           &local_err);
++/*
-+    if (local_err) {
++ * IMX7 System Reset Controller
-+        error_propagate(errp, local_err);
++ *
 + * Copyright (C) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + */
 +
 +#ifndef IMX7_SRC_H
 +#define IMX7_SRC_H
 +
 +#include "hw/sysbus.h"
 +#include "qemu/bitops.h"
 +#include "qom/object.h"
 +
 +#define SRC_SCR 0
 +#define SRC_A7RCR0 1
 +#define SRC_A7RCR1 2
 +#define SRC_M4RCR 3
 +#define SRC_ERCR 5
 +#define SRC_HSICPHY_RCR 7
 +#define SRC_USBOPHY1_RCR 8
 +#define SRC_USBOPHY2_RCR 9
 +#define SRC_MPIPHY_RCR 10
 +#define SRC_PCIEPHY_RCR 11
 +#define SRC_SBMR1 22
 +#define SRC_SRSR 23
 +#define SRC_SISR 26
 +#define SRC_SIMR 27
 +#define SRC_SBMR2 28
 +#define SRC_GPR1 29
 +#define SRC_GPR2 30
 +#define SRC_GPR3 31
 +#define SRC_GPR4 32
 +#define SRC_GPR5 33
 +#define SRC_GPR6 34
 +#define SRC_GPR7 35
 +#define SRC_GPR8 36
 +#define SRC_GPR9 37
 +#define SRC_GPR10 38
 +#define SRC_MAX 39
 +
 +/* SRC_A7SCR1 */
 +#define R_CORE1_ENABLE_SHIFT     1
 +#define R_CORE1_ENABLE_LENGTH    1
 +/* SRC_A7SCR0 */
 +#define R_CORE1_RST_SHIFT        5
 +#define R_CORE1_RST_LENGTH       1
 +#define R_CORE0_RST_SHIFT        4
 +#define R_CORE0_RST_LENGTH       1
 +
 +#define TYPE_IMX7_SRC "imx7.src"
 +OBJECT_DECLARE_SIMPLE_TYPE(IMX7SRCState, IMX7_SRC)
 +
 +struct IMX7SRCState {
 +    /* <private> */
 +    SysBusDevice parent_obj;
 +
 +    /* <public> */
 +    MemoryRegion iomem;
 +
 +    uint32_t regs[SRC_MAX];
 +};
 +
 +#endif /* IMX7_SRC_H */
 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/fsl-imx7.c
 +++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
       */
      object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 +    /*
 +     * SRC
 +     */
 +    object_initialize_child(obj, "src", &s->src, TYPE_IMX7_SRC);
 +
      /*
       * ECSPIs
       */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      /*
       * SRC
       */
 -    create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 +    sysbus_realize(SYS_BUS_DEVICE(&s->src), &error_abort);
 +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->src), 0, FSL_IMX7_SRC_ADDR);
      /*
       * Watchdogs
 diff --git a/hw/misc/imx7_src.c b/hw/misc/imx7_src.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/imx7_src.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * IMX7 System Reset Controller
 + *
 + * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
 + *
 + * This work is licensed under the terms of the GNU GPL, version 2 or later.
 + * See the COPYING file in the top-level directory.
 + *
 + */
 +
 +#include "qemu/osdep.h"
 +#include "hw/misc/imx7_src.h"
 +#include "migration/vmstate.h"
 +#include "qemu/bitops.h"
 +#include "qemu/log.h"
 +#include "qemu/main-loop.h"
 +#include "qemu/module.h"
 +#include "target/arm/arm-powerctl.h"
 +#include "hw/core/cpu.h"
 +#include "hw/registerfields.h"
 +
 +#include "trace.h"
 +
 +static const char *imx7_src_reg_name(uint32_t reg)
 +{
 +    static char unknown[20];
 +
 +    switch (reg) {
 +    case SRC_SCR:
 +        return "SRC_SCR";
 +    case SRC_A7RCR0:
 +        return "SRC_A7RCR0";
 +    case SRC_A7RCR1:
 +        return "SRC_A7RCR1";
 +    case SRC_M4RCR:
 +        return "SRC_M4RCR";
 +    case SRC_ERCR:
 +        return "SRC_ERCR";
 +    case SRC_HSICPHY_RCR:
 +        return "SRC_HSICPHY_RCR";
 +    case SRC_USBOPHY1_RCR:
 +        return "SRC_USBOPHY1_RCR";
 +    case SRC_USBOPHY2_RCR:
 +        return "SRC_USBOPHY2_RCR";
 +    case SRC_PCIEPHY_RCR:
 +        return "SRC_PCIEPHY_RCR";
 +    case SRC_SBMR1:
 +        return "SRC_SBMR1";
 +    case SRC_SRSR:
 +        return "SRC_SRSR";
 +    case SRC_SISR:
 +        return "SRC_SISR";
 +    case SRC_SIMR:
 +        return "SRC_SIMR";
 +    case SRC_SBMR2:
 +        return "SRC_SBMR2";
 +    case SRC_GPR1:
 +        return "SRC_GPR1";
 +    case SRC_GPR2:
 +        return "SRC_GPR2";
 +    case SRC_GPR3:
 +        return "SRC_GPR3";
 +    case SRC_GPR4:
 +        return "SRC_GPR4";
 +    case SRC_GPR5:
 +        return "SRC_GPR5";
 +    case SRC_GPR6:
 +        return "SRC_GPR6";
 +    case SRC_GPR7:
 +        return "SRC_GPR7";
 +    case SRC_GPR8:
 +        return "SRC_GPR8";
 +    case SRC_GPR9:
 +        return "SRC_GPR9";
 +    case SRC_GPR10:
 +        return "SRC_GPR10";
 +    default:
 +        sprintf(unknown, "%u ?", reg);
 +        return unknown;
 +    }
 +}
 +
 +static const VMStateDescription vmstate_imx7_src = {
 +    .name = TYPE_IMX7_SRC,
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +static void imx7_src_reset(DeviceState *dev)
 +{
 +    IMX7SRCState *s = IMX7_SRC(dev);
 +
 +    memset(s->regs, 0, sizeof(s->regs));
 +
 +    /* Set reset values */
 +    s->regs[SRC_SCR] = 0xA0;
 +    s->regs[SRC_SRSR] = 0x1;
 +    s->regs[SRC_SIMR] = 0x1F;
 +}
 +
 +static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    uint32_t value = 0;
 +    IMX7SRCState *s = (IMX7SRCState *)opaque;
 +    uint32_t index = offset >> 2;
 +
 +    if (index < SRC_MAX) {
 +        value = s->regs[index];
 +    } else {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
 +    }
 +
 +    trace_imx7_src_read(imx7_src_reg_name(index), value);
 +
 +    return value;
 +}
 +
 +
 +/*
 + * The reset is asynchronous so we need to defer clearing the reset
 + * bit until the work is completed.
 + */
 +
 +struct SRCSCRResetInfo {
 +    IMX7SRCState *s;
 +    uint32_t reset_bit;
 +};
 +
 +static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
 +{
 +    struct SRCSCRResetInfo *ri = data.host_ptr;
 +    IMX7SRCState *s = ri->s;
 +
 +    assert(qemu_mutex_iothread_locked());
 +
 +    s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0);
 +
 +    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
 +
 +    g_free(ri);
 +}
 +
 +static void imx7_defer_clear_reset_bit(uint32_t cpuid,
 +                                       IMX7SRCState *s,
 +                                       uint32_t reset_shift)
 +{
 +    struct SRCSCRResetInfo *ri;
 +    CPUState *cpu = arm_get_cpu_by_id(cpuid);
 +
 +    if (!cpu) {
 +        return;
 +    }
 +
-+    memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s,
++    ri = g_new(struct SRCSCRResetInfo, 1);
-+                          "integratorcm", 0x00800000);
++    ri->s = s;
-+    sysbus_init_mmio(dev, &s->iomem);
++    ri->reset_bit = reset_shift;
 +
-+    integratorcm_do_remap(s);
++    async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri));
++}
-     if (s->memsz >= 256) {
++
-         integrator_spd[31] = 64;
++
 +static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value,
 +                           unsigned size)
 +{
 +    IMX7SRCState *s = (IMX7SRCState *)opaque;
 +    uint32_t index = offset >> 2;
 +    long unsigned int change_mask;
 +    uint32_t current_value = value;
 +
 +    if (index >= SRC_MAX) {
 +        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 +                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
 +        return;
 +    }
 +
 +    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
 +
 +    change_mask = s->regs[index] ^ (uint32_t)current_value;
 +
 +    switch (index) {
 +    case SRC_A7RCR0:
 +        if (FIELD_EX32(change_mask, CORE0, RST)) {
 +            arm_reset_cpu(0);
 +            imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT);
 +        }
 +        if (FIELD_EX32(change_mask, CORE1, RST)) {
 +            arm_reset_cpu(1);
 +            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
 +        }
 +        s->regs[index] = current_value;
 +        break;
 +    case SRC_A7RCR1:
 +        /*
 +         * On real hardware when the system reset controller starts a
 +         * secondary CPU it runs through some boot ROM code which reads
 +         * the SRC_GPRX registers controlling the start address and branches
 +         * to it.
 +         * Here we are taking a short cut and branching directly to the
 +         * requested address (we don't want to run the boot ROM code inside
 +         * QEMU)
 +         */
 +        if (FIELD_EX32(change_mask, CORE1, ENABLE)) {
 +            if (FIELD_EX32(current_value, CORE1, ENABLE)) {
 +                /* CORE 1 is brought up */
 +                arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
 +                               3, false);
 +            } else {
 +                /* CORE 1 is shut down */
 +                arm_set_cpu_off(1);
 +            }
 +            /* We clear the reset bits as the processor changed state */
 +            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
 +            clear_bit(R_CORE1_RST_SHIFT, &change_mask);
 +        }
 +        s->regs[index] = current_value;
 +        break;
 +    default:
 +        s->regs[index] = current_value;
 +        break;
 +    }
 +}
 +
 +static const struct MemoryRegionOps imx7_src_ops = {
 +    .read = imx7_src_read,
 +    .write = imx7_src_write,
 +    .endianness = DEVICE_NATIVE_ENDIAN,
 +    .valid = {
 +        /*
 +         * Our device would not work correctly if the guest was doing
 +         * unaligned access. This might not be a limitation on the real
 +         * device but in practice there is no reason for a guest to access
 +         * this device unaligned.
 +         */
 +        .min_access_size = 4,
 +        .max_access_size = 4,
 +        .unaligned = false,
 +    },
 +};
 +
 +static void imx7_src_realize(DeviceState *dev, Error **errp)
 +{
 +    IMX7SRCState *s = IMX7_SRC(dev);
 +
 +    memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s,
 +                          TYPE_IMX7_SRC, 0x1000);
 +    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 +}
 +
 +static void imx7_src_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->realize = imx7_src_realize;
 +    dc->reset = imx7_src_reset;
 +    dc->vmsd = &vmstate_imx7_src;
 +    dc->desc = "i.MX6 System Reset Controller";
 +}
 +
 +static const TypeInfo imx7_src_info = {
 +    .name          = TYPE_IMX7_SRC,
 +    .parent        = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(IMX7SRCState),
 +    .class_init    = imx7_src_class_init,
 +};
 +
 +static void imx7_src_register_types(void)
 +{
 +    type_register_static(&imx7_src_info);
 +}
 +
 +type_init(imx7_src_register_types)
 diff --git a/hw/misc/meson.build b/hw/misc/meson.build
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/meson.build
 +++ b/hw/misc/meson.build
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_IMX', if_true: files(
    'imx6_src.c',
    'imx6ul_ccm.c',
    'imx7_ccm.c',
 +  'imx7_src.c',
    'imx7_gpr.c',
    'imx7_snvs.c',
    'imx_ccm.c',
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d"
  ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
  ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
 +# imx7_src.c
 +imx7_src_read(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32
 +imx7_src_write(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32
 +
  # iotkit-sysinfo.c
  iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
  iotkit_sysinfo_write(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 --
-.16.2
+.34.1

-New patch
+[PULL 17/24] target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
+The architecture requires (R_TYTWB) that an attempt to return from EL3
+when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
+enforces that the CPU can't ever be executing below EL3 with the
+NSE,NS bits indicating an invalid security state.)
+We were missing this check; add it.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
+---
+ target/arm/tcg/helper-a64.c | 9 +++++++++
+file changed, 9 insertions(+)
+diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/helper-a64.c
++++ b/target/arm/tcg/helper-a64.c
+@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
+         spsr &= ~PSTATE_SS;
+     }
++    /*
++     * FEAT_RME forbids return from EL3 with an invalid security state.
++     * We don't need an explicit check for FEAT_RME here because we enforce
++     * in scr_write() that you can't set the NSE bit without it.
++     */
++    if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
++        goto illegal_return;
++    }
++
+     new_el = el_from_spsr(spsr);
+     if (new_el == -1) {
+         goto illegal_return;
+--
+.34.1

-New patch
+[PULL 18/24] hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
+In the m48t59 device we almost always use 64-bit arithmetic when
+dealing with time_t deltas.  The one exception is in set_alarm(),
+which currently uses a plain 'int' to hold the difference between two
+time_t values.  Switch to int64_t instead to avoid any possible
+overflow issues.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+---
+ hw/rtc/m48t59.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/rtc/m48t59.c
++++ b/hw/rtc/m48t59.c
+@@ -XXX,XX +XXX,XX @@ static void alarm_cb (void *opaque)
+ static void set_alarm(M48t59State *NVRAM)
+ {
+-    int diff;
++    int64_t diff;
+     if (NVRAM->alrm_timer != NULL) {
+         timer_del(NVRAM->alrm_timer);
+         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
+--
+.34.1

-[Qemu-devel] [PULL 08/12] target/arm: Report unsupported MPU region sizes more clearly
+[PULL 19/24] hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
-Currently our PMSAv7 and ARMv7M MPU implementation cannot handle
+In the twl92230 device, use int64_t for the two state fields
-MPU region sizes smaller than our TARGET_PAGE_SIZE. However we
+sec_offset and alm_sec, because we set these to values that
-report that in a slightly confusing way:
+are either time_t or differences between two time_t values.
- DRSR[3]: No support for MPU (sub)region alignment of 9 bits. Minimum is 10
+These fields aren't saved in vmstate anywhere, so we can
+safely widen them.
 The problem is not the alignment of the region, but its size;
 tweak the error message to say so:
  DRSR[3]: No support for MPU (sub)region size of 512 bytes. Minimum is 1024.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20180405172554.27401-1-peter.maydell@linaro.org
 ---
- target/arm/helper.c | 6 +++---
+ hw/rtc/twl92230.c | 4 ++--
-file changed, 3 insertions(+), 3 deletions(-)
+file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/target/arm/helper.c b/target/arm/helper.c
+diff --git a/hw/rtc/twl92230.c b/hw/rtc/twl92230.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
+--- a/hw/rtc/twl92230.c
-+++ b/target/arm/helper.c
++++ b/hw/rtc/twl92230.c
-@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
+@@ -XXX,XX +XXX,XX @@ struct MenelausState {
-             }
+         struct tm tm;
-             if (rsize < TARGET_PAGE_BITS) {
+         struct tm new;
-                 qemu_log_mask(LOG_UNIMP,
+         struct tm alm;
--                              "DRSR[%d]: No support for MPU (sub)region "
+-        int sec_offset;
--                              "alignment of %" PRIu32 " bits. Minimum is %d\n",
+-        int alm_sec;
--                              n, rsize, TARGET_PAGE_BITS);
++        int64_t sec_offset;
-+                              "DRSR[%d]: No support for MPU (sub)region size of"
++        int64_t alm_sec;
-+                              " %" PRIu32 " bytes. Minimum is %d.\n",
+         int next_comp;
-+                              n, (1 << rsize), TARGET_PAGE_SIZE);
+     } rtc;
-                 continue;
+     uint16_t rtc_next_vmstate;
              }
              if (srdis) {
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 05/12] hw/sd/bcm2835_sdhost: Don't raise spurious interrupts
+[PULL 20/24] hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
-The Linux bcm2835_sdhost driver doesn't work on QEMU, because our
+In the aspeed_rtc device we store a difference between two time_t
-model raises spurious data interrupts.  Our function
+values in an 'int'. This is not really correct when time_t could
-bcm2835_sdhost_fifo_run() will flag an interrupt any time it is
+be 64 bits. Enlarge the field to 'int64_t'.
 called with s->datacnt == 0, even if the host hasn't actually issued
 a data read or write command yet.  This means that the driver gets a
 spurious data interrupt as soon as it enables IRQs and then does
 something else that causes us to call the fifo_run routine, like
 writing to SDHCFG, and before it does the write to SDCMD to issue the
 read.  The driver's IRQ handler then spins forever complaining that
 there's no data and the SD controller isn't in a state where there's
 going to be any data:
-[   41.040738] sdhost-bcm2835 3f202000.mmc: fsm 1, hsts 00000000
+This is a migration compatibility break for the aspeed boards.
-[   41.042059] sdhost-bcm2835 3f202000.mmc: fsm 1, hsts 00000000
+While we are changing the vmstate, remove the accidental
-(continues forever).
+duplicate of the offset field.
 Move the interrupt flag setting to more plausible places:
  * for BUSY, raise this as soon as a BUSYWAIT command has executed
  * for DATA, raise this when the FIFO has any space free (for a write)
    or any data in it (for a read)
  * for BLOCK, raise this when the data count is 0 and we've
    actually done some reading or writing
 This is pure guesswork since the documentation for this hardware is
 not public, but it is sufficient to get the Linux bcm2835_sdhost
 driver to work.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Cédric Le Goater <clg@kaod.org>
 Tested-by: Gerd Hoffmann <kraxel@redhat.com>
 Message-id: 20180319161556.16446-3-peter.maydell@linaro.org
 ---
- hw/sd/bcm2835_sdhost.c | 46 ++++++++++++++++++++++++++--------------------
+ include/hw/rtc/aspeed_rtc.h | 2 +-
-file changed, 26 insertions(+), 20 deletions(-)
+ hw/rtc/aspeed_rtc.c         | 5 ++---
 files changed, 3 insertions(+), 4 deletions(-)
-diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
+diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/sd/bcm2835_sdhost.c
+--- a/include/hw/rtc/aspeed_rtc.h
-+++ b/hw/sd/bcm2835_sdhost.c
++++ b/include/hw/rtc/aspeed_rtc.h
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_send_command(BCM2835SDHostState *s)
+@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
-         }
+     qemu_irq irq;
- #undef RWORD
      uint32_t reg[0x18];
 -    int offset;
 +    int64_t offset;
  };
 diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/rtc/aspeed_rtc.c
 +++ b/hw/rtc/aspeed_rtc.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
  static const VMStateDescription vmstate_aspeed_rtc = {
      .name = TYPE_ASPEED_RTC,
 -    .version_id = 1,
 +    .version_id = 2,
      .fields = (VMStateField[]) {
          VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
 -        VMSTATE_INT32(offset, AspeedRtcState),
 -        VMSTATE_INT32(offset, AspeedRtcState),
 +        VMSTATE_INT64(offset, AspeedRtcState),
          VMSTATE_END_OF_LIST()
      }
-+    /* We never really delay commands, so if this was a 'busywait' command
+ };
 +     * then we've completed it now and can raise the interrupt.
 +     */
 +    if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) {
 +        s->status |= SDHSTS_BUSY_IRPT;
 +    }
      return;
  error:
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
                  n++;
                  if (n == 4) {
                      bcm2835_sdhost_fifo_push(s, value);
 +                    s->status |= SDHSTS_DATA_FLAG;
 +                    if (s->config & SDHCFG_DATA_IRPT_EN) {
 +                        s->status |= SDHSTS_SDIO_IRPT;
 +                    }
                      n = 0;
                      value = 0;
                  }
              }
              if (n != 0) {
                  bcm2835_sdhost_fifo_push(s, value);
 +                s->status |= SDHSTS_DATA_FLAG;
              }
          } else { /* write */
              n = 0;
              while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) {
                  if (n == 0) {
                      value = bcm2835_sdhost_fifo_pop(s);
 +                    s->status |= SDHSTS_DATA_FLAG;
 +                    if (s->config & SDHCFG_DATA_IRPT_EN) {
 +                        s->status |= SDHSTS_SDIO_IRPT;
 +                    }
                      n = 4;
                  }
                  n--;
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
                  value >>= 8;
              }
          }
 +        if (s->datacnt == 0) {
 +            s->edm &= ~SDEDM_FSM_MASK;
 +            s->edm |= SDEDM_FSM_DATAMODE;
 +            trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm);
 +
 +            if ((s->cmd & SDCMD_WRITE_CMD) &&
 +                (s->config & SDHCFG_BLOCK_IRPT_EN)) {
 +                s->status |= SDHSTS_BLOCK_IRPT;
 +            }
 +        }
      }
 -    if (s->datacnt == 0) {
 -        s->status |= SDHSTS_DATA_FLAG;
 -        s->edm &= ~0xf;
 -        s->edm |= SDEDM_FSM_DATAMODE;
 -        trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm);
 -
 -        if (s->config & SDHCFG_DATA_IRPT_EN) {
 -            s->status |= SDHSTS_SDIO_IRPT;
 -        }
 -
 -        if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) {
 -            s->status |= SDHSTS_BUSY_IRPT;
 -        }
 -
 -        if ((s->cmd & SDCMD_WRITE_CMD) && (s->config & SDHCFG_BLOCK_IRPT_EN)) {
 -            s->status |= SDHSTS_BLOCK_IRPT;
 -        }
 -
 -        bcm2835_sdhost_update_irq(s);
 -    }
 +    bcm2835_sdhost_update_irq(s);
      s->edm &= ~(0x1f << 4);
      s->edm |= ((s->fifo_len & 0x1f) << 4);
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 04/12] hw/sd/bcm2835_sdhost: Add tracepoints
+[PULL 21/24] rtc: Use time_t for passing and returning time offsets
-Add some tracepoints to the bcm2835_sdhost driver, to assist
+The functions qemu_get_timedate() and qemu_timedate_diff() take
-debugging.
+and return a time offset as an integer. Coverity points out that
 means that when an RTC device implementation holds an offset
 as a time_t, as the m48t59 does, the time_t will get truncated.
 (CID 1507157, 1517772).
 The functions work with time_t internally, so make them use that type
 in their APIs.
 Note that this won't help any Y2038 issues where either the device
 model itself is keeping the offset in a 32-bit integer, or where the
 hardware under emulation has Y2038 or other rollover problems.  If we
 missed any cases of the former then hopefully Coverity will warn us
 about them since after this patch we'd be truncating a time_t in
 assignments from qemu_timedate_diff().)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Tested-by: Gerd Hoffmann <kraxel@redhat.com>
 Message-id: 20180319161556.16446-2-peter.maydell@linaro.org
 ---
- hw/sd/bcm2835_sdhost.c | 10 ++++++++++
+ include/sysemu/rtc.h | 4 ++--
- hw/sd/trace-events     |  6 ++++++
+ softmmu/rtc.c        | 4 ++--
-files changed, 16 insertions(+)
+files changed, 4 insertions(+), 4 deletions(-)
-diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
+diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/sd/bcm2835_sdhost.c
+--- a/include/sysemu/rtc.h
-+++ b/hw/sd/bcm2835_sdhost.c
++++ b/include/sysemu/rtc.h
 @@ -XXX,XX +XXX,XX @@
- #include "qemu/log.h"
+  * The behaviour of the clock whose value this function returns will
- #include "sysemu/blockdev.h"
+  * depend on the -rtc command line option passed by the user.
- #include "hw/sd/bcm2835_sdhost.h"
+  */
-+#include "trace.h"
+-void qemu_get_timedate(struct tm *tm, int offset);
++void qemu_get_timedate(struct tm *tm, time_t offset);
- #define TYPE_BCM2835_SDHOST_BUS "bcm2835-sdhost-bus"
- #define BCM2835_SDHOST_BUS(obj) \
+ /**
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_update_irq(BCM2835SDHostState *s)
+  * qemu_timedate_diff: Return difference between a struct tm and the RTC
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
   * a timestamp one hour further ahead than the current RTC time
   * then this function will return 3600.
   */
 -int qemu_timedate_diff(struct tm *tm);
 +time_t qemu_timedate_diff(struct tm *tm);
  #endif
 diff --git a/softmmu/rtc.c b/softmmu/rtc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/softmmu/rtc.c
 +++ b/softmmu/rtc.c
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
      return value;
  }
 -void qemu_get_timedate(struct tm *tm, int offset)
 +void qemu_get_timedate(struct tm *tm, time_t offset)
  {
-     uint32_t irq = s->status &
+     time_t ti = qemu_ref_timedate(rtc_clock);
-         (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | SDHSTS_SDIO_IRPT);
-+    trace_bcm2835_sdhost_update_irq(irq);
+@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
-     qemu_set_irq(s->irq, !!irq);
+     }
  }
-@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
+-int qemu_timedate_diff(struct tm *tm)
++time_t qemu_timedate_diff(struct tm *tm)
          s->edm &= ~0xf;
          s->edm |= SDEDM_FSM_DATAMODE;
 +        trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm);
          if (s->config & SDHCFG_DATA_IRPT_EN) {
              s->status |= SDHSTS_SDIO_IRPT;
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
      s->edm &= ~(0x1f << 4);
      s->edm |= ((s->fifo_len & 0x1f) << 4);
 +    trace_bcm2835_sdhost_edm_change("fifo run", s->edm);
  }
  static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset,
@@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset,
          break;
      }
 +    trace_bcm2835_sdhost_read(offset, res, size);
 +
      return res;
  }
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
  {
-     BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
+     time_t seconds;
 +    trace_bcm2835_sdhost_write(offset, value, size);
 +
      switch (offset) {
      case SDCMD:
          s->cmd = value;
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
              value &= ~0xf;
          }
          s->edm = value;
 +        trace_bcm2835_sdhost_edm_change("guest register write", s->edm);
          break;
      case SDHCFG:
          s->config = value;
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_reset(DeviceState *dev)
      s->cmd = 0;
      s->cmdarg = 0;
      s->edm = 0x0000c60f;
 +    trace_bcm2835_sdhost_edm_change("device reset", s->edm);
      s->config = 0;
      s->hbct = 0;
      s->hblc = 0;
 diff --git a/hw/sd/trace-events b/hw/sd/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/sd/trace-events
 +++ b/hw/sd/trace-events
@@ -XXX,XX +XXX,XX @@
  # See docs/devel/tracing.txt for syntax documentation.
 +# hw/sd/bcm2835_sdhost.c
 +bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 +bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 +bcm2835_sdhost_edm_change(const char *why, uint32_t edm) "(%s) EDM now 0x%x"
 +bcm2835_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x\n"
 +
  # hw/sd/core.c
  sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg, uint8_t crc) "@%s CMD%02d arg 0x%08x crc 0x%02x"
  sdbus_read(const char *bus_name, uint8_t value) "@%s value 0x%02x"
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 09/12] cpus.c: ensure running CPU recalculates icount deadlines on timer expiry
+[PULL 22/24] target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
-When we run in TCG icount mode, we calculate the number of instructions
+Where architecturally one ARM_FEATURE_X flag implies another
-to execute using tcg_get_icount_limit(), which ensures that we stop
+ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
-execution at the next timer deadline. However there is a bug where
+set Y for it.  Currently we do this in two places -- we set a few
-currently we do not recalculate that limit if the guest reprograms
+flags in arm_cpu_post_init() because we need them to decide which
-a timer so that the next deadline moves closer, and so we will
+properties to create on the CPU object, and then we do the rest in
-continue execution until the original limit and fire the timer
+arm_cpu_realizefn().  However, this is fragile, because it's easy to
-later than we should.
+add a new property and not notice that this means that an X-implies-Y
+check now has to move from realize to post-init.
-Fix this bug in qemu_timer_notify_cb(): if we are currently running
-a VCPU in icount mode, we simply need to kick it out of the main
+As a specific example, the pmsav7-dregion property is conditional
-loop and back to tcg_cpu_exec(), where it will recalculate the
+on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
-icount limit. If we are not currently running a VCPU, then we
+on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
-retain the existing logic for waking up a halted CPU.
+rely on V8-implies-V7, which doesn't happen until the realizefn.
-Cc: qemu-stable@nongnu.org
+Move all of these X-implies-Y checks into a new function, which
-Fixes: https://bugs.launchpad.net/qemu/+bug/1754038
+we call at the top of arm_cpu_post_init(), so the feature bits
 are available at that point.
 This does now give us the reverse issue, that if there's a feature
 bit which is enabled or disabled by the setting of a property then
 then X-implies-Y features that are dependent on that property need to
 be in realize, not in this new function.  But the only one of those
 is the "EL3 implies VBAR" which is already in the right place, so
 putting things this way round seems better to me.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
 Message-id: 20180406123838.21249-1-peter.maydell@linaro.org
 ---
- cpus.c | 10 +++++++++-
+ target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
-file changed, 9 insertions(+), 1 deletion(-)
+file changed, 97 insertions(+), 82 deletions(-)
-diff --git a/cpus.c b/cpus.c
+diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
---- a/cpus.c
+--- a/target/arm/cpu.c
-+++ b/cpus.c
++++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ void qemu_timer_notify_cb(void *opaque, QEMUClockType type)
+@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
-         return;
+       NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
  }
 +static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
 +{
 +    CPUARMState *env = &cpu->env;
 +    bool no_aa32 = false;
 +
 +    /*
 +     * Some features automatically imply others: set the feature
 +     * bits explicitly for these cases.
 +     */
 +
 +    if (arm_feature(env, ARM_FEATURE_M)) {
 +        set_feature(env, ARM_FEATURE_PMSA);
 +    }
 +
 +    if (arm_feature(env, ARM_FEATURE_V8)) {
 +        if (arm_feature(env, ARM_FEATURE_M)) {
 +            set_feature(env, ARM_FEATURE_V7);
 +        } else {
 +            set_feature(env, ARM_FEATURE_V7VE);
 +        }
 +    }
 +
 +    /*
 +     * There exist AArch64 cpus without AArch32 support.  When KVM
 +     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
 +     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
 +     * As a general principle, we also do not make ID register
 +     * consistency checks anywhere unless using TCG, because only
 +     * for TCG would a consistency-check failure be a QEMU bug.
 +     */
 +    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 +        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 +    }
 +
 +    if (arm_feature(env, ARM_FEATURE_V7VE)) {
 +        /*
 +         * v7 Virtualization Extensions. In real hardware this implies
 +         * EL2 and also the presence of the Security Extensions.
 +         * For QEMU, for backwards-compatibility we implement some
 +         * CPUs or CPU configs which have no actual EL2 or EL3 but do
 +         * include the various other features that V7VE implies.
 +         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 +         * Security Extensions is ARM_FEATURE_EL3.
 +         */
 +        assert(!tcg_enabled() || no_aa32 ||
 +               cpu_isar_feature(aa32_arm_div, cpu));
 +        set_feature(env, ARM_FEATURE_LPAE);
 +        set_feature(env, ARM_FEATURE_V7);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V7)) {
 +        set_feature(env, ARM_FEATURE_VAPA);
 +        set_feature(env, ARM_FEATURE_THUMB2);
 +        set_feature(env, ARM_FEATURE_MPIDR);
 +        if (!arm_feature(env, ARM_FEATURE_M)) {
 +            set_feature(env, ARM_FEATURE_V6K);
 +        } else {
 +            set_feature(env, ARM_FEATURE_V6);
 +        }
 +
 +        /*
 +         * Always define VBAR for V7 CPUs even if it doesn't exist in
 +         * non-EL3 configs. This is needed by some legacy boards.
 +         */
 +        set_feature(env, ARM_FEATURE_VBAR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V6K)) {
 +        set_feature(env, ARM_FEATURE_V6);
 +        set_feature(env, ARM_FEATURE_MVFR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V6)) {
 +        set_feature(env, ARM_FEATURE_V5);
 +        if (!arm_feature(env, ARM_FEATURE_M)) {
 +            assert(!tcg_enabled() || no_aa32 ||
 +                   cpu_isar_feature(aa32_jazelle, cpu));
 +            set_feature(env, ARM_FEATURE_AUXCR);
 +        }
 +    }
 +    if (arm_feature(env, ARM_FEATURE_V5)) {
 +        set_feature(env, ARM_FEATURE_V4T);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_LPAE)) {
 +        set_feature(env, ARM_FEATURE_V7MP);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 +        set_feature(env, ARM_FEATURE_CBAR);
 +    }
 +    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 +        !arm_feature(env, ARM_FEATURE_M)) {
 +        set_feature(env, ARM_FEATURE_THUMB_DSP);
 +    }
 +}
 +
  void arm_cpu_post_init(Object *obj)
  {
      ARMCPU *cpu = ARM_CPU(obj);
 -    /* M profile implies PMSA. We have to do this here rather than
 -     * in realize with the other feature-implication checks because
 -     * we look at the PMSA bit to see if we should add some properties.
 +    /*
 +     * Some features imply others. Figure this out now, because we
 +     * are going to look at the feature bits in deciding which
 +     * properties to add.
       */
 -    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
 -        set_feature(&cpu->env, ARM_FEATURE_PMSA);
 -    }
 +    arm_cpu_propagate_feature_implications(cpu);
      if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
          arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
      CPUARMState *env = &cpu->env;
      int pagebits;
      Error *local_err = NULL;
 -    bool no_aa32 = false;
      /* Use pc-relative instructions in system-mode */
  #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          cpu->isar.id_isar3 = u;
      }
--    if (!qemu_in_vcpu_thread() && first_cpu) {
+-    /* Some features automatically imply others: */
-+    if (qemu_in_vcpu_thread()) {
+-    if (arm_feature(env, ARM_FEATURE_V8)) {
-+        /* A CPU is currently running; kick it back out to the
+-        if (arm_feature(env, ARM_FEATURE_M)) {
-+         * tcg_cpu_exec() loop so it will recalculate its
+-            set_feature(env, ARM_FEATURE_V7);
-+         * icount deadline immediately.
+-        } else {
-+         */
+-            set_feature(env, ARM_FEATURE_V7VE);
-+        qemu_cpu_kick(current_cpu);
+-        }
-+    } else if (first_cpu) {
+-    }
-         /* qemu_cpu_kick is not enough to kick a halted CPU out of
+-
-          * qemu_tcg_wait_io_event.  async_run_on_cpu, instead,
+-    /*
-          * causes cpu_thread_is_idle to return false.  This way,
+-     * There exist AArch64 cpus without AArch32 support.  When KVM
-          * handle_icount_deadline can run.
+-     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
-+         * If we have no CPUs at all for some reason, we don't
+-     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
-+         * need to do anything.
+-     * As a general principle, we also do not make ID register
-          */
+-     * consistency checks anywhere unless using TCG, because only
-         async_run_on_cpu(first_cpu, do_nothing, RUN_ON_CPU_NULL);
+-     * for TCG would a consistency-check failure be a QEMU bug.
-     }
+-     */
 -    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 -        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 -    }
 -
 -    if (arm_feature(env, ARM_FEATURE_V7VE)) {
 -        /* v7 Virtualization Extensions. In real hardware this implies
 -         * EL2 and also the presence of the Security Extensions.
 -         * For QEMU, for backwards-compatibility we implement some
 -         * CPUs or CPU configs which have no actual EL2 or EL3 but do
 -         * include the various other features that V7VE implies.
 -         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 -         * Security Extensions is ARM_FEATURE_EL3.
 -         */
 -        assert(!tcg_enabled() || no_aa32 ||
 -               cpu_isar_feature(aa32_arm_div, cpu));
 -        set_feature(env, ARM_FEATURE_LPAE);
 -        set_feature(env, ARM_FEATURE_V7);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V7)) {
 -        set_feature(env, ARM_FEATURE_VAPA);
 -        set_feature(env, ARM_FEATURE_THUMB2);
 -        set_feature(env, ARM_FEATURE_MPIDR);
 -        if (!arm_feature(env, ARM_FEATURE_M)) {
 -            set_feature(env, ARM_FEATURE_V6K);
 -        } else {
 -            set_feature(env, ARM_FEATURE_V6);
 -        }
 -
 -        /* Always define VBAR for V7 CPUs even if it doesn't exist in
 -         * non-EL3 configs. This is needed by some legacy boards.
 -         */
 -        set_feature(env, ARM_FEATURE_VBAR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V6K)) {
 -        set_feature(env, ARM_FEATURE_V6);
 -        set_feature(env, ARM_FEATURE_MVFR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V6)) {
 -        set_feature(env, ARM_FEATURE_V5);
 -        if (!arm_feature(env, ARM_FEATURE_M)) {
 -            assert(!tcg_enabled() || no_aa32 ||
 -                   cpu_isar_feature(aa32_jazelle, cpu));
 -            set_feature(env, ARM_FEATURE_AUXCR);
 -        }
 -    }
 -    if (arm_feature(env, ARM_FEATURE_V5)) {
 -        set_feature(env, ARM_FEATURE_V4T);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_LPAE)) {
 -        set_feature(env, ARM_FEATURE_V7MP);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 -        set_feature(env, ARM_FEATURE_CBAR);
 -    }
 -    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 -        !arm_feature(env, ARM_FEATURE_M)) {
 -        set_feature(env, ARM_FEATURE_THUMB_DSP);
 -    }
      /*
       * We rely on no XScale CPU having VFP so we can use the same bits in the
 --
-.16.2
+.34.1

-[Qemu-devel] [PULL 01/12] hw/arm: Allow manually specified /psci node
+[PULL 23/24] hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
-From: Andrey Smirnov <andrew.smirnov@gmail.com>
+M-profile CPUs generally allow configuration of the number of MPU
 regions that they have.  We don't currently model this, so our
 implementations of some of the board models provide CPUs with the
 wrong number of regions.  RTOSes like Zephyr that hardcode the
 expected number of regions may therefore not run on the model if they
 are set up to run on real hardware.
-Change the code to avoid exiting QEMU if user provided DTB contains
+Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
-manually specified /psci node and skip any /psci related fixups
+matching the ability of hardware to configure the number of Secure
-instead.
+and NonSecure regions separately.  Our actual CPU implementation
 doesn't currently support that, and it happens that none of the MPS
 boards we model set the number of regions differently for Secure vs
 NonSecure, so we provide an interface to the boards and SoCs that
 won't need to change if we ever do add that functionality in future,
 but make it an error to configure the two properties to different
 values.
-Fixes: 4cbca7d9b4 ("hw/arm: Move virt's PSCI DT fixup code to
+(The property name on the CPU is the somewhat misnamed-for-M-profile
-arm/boot.c")
+"pmsav7-dregion", so we don't follow that naming convention for
 the properties here. The TRM doesn't say what the CPU configuration
 variable names are, so we pick something, and follow the lowercase
 convention we already have for properties here.)
-Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
-Reported-by: Marc Zyngier <marc.zyngier@arm.com>
-Tested-by: Marc Zyngier <marc.zyngier@arm.com>
-Message-id: 20180402205654.14572-1-andrew.smirnov@gmail.com
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
+Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
 ---
- hw/arm/boot.c | 10 ++++++++++
+ include/hw/arm/armv7m.h |  8 ++++++++
-file changed, 10 insertions(+)
+ hw/arm/armv7m.c         | 21 +++++++++++++++++++++
 files changed, 29 insertions(+)
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
+diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
+--- a/include/hw/arm/armv7m.h
-+++ b/hw/arm/boot.c
++++ b/include/hw/arm/armv7m.h
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
+@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
-     ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
+  * + Property "vfp": enable VFP (forwarded to CPU object)
-     const char *psci_method;
+  * + Property "dsp": enable DSP (forwarded to CPU object)
-     int64_t psci_conduit;
+  * + Property "enable-bitband": expose bitbanded IO
-+    int rc;
++ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
++ *   to CPU object pmsav7-dregion property; default is whatever the default
-     psci_conduit = object_property_get_int(OBJECT(armcpu),
++ *   for the CPU is)
-                                            "psci-conduit",
++ * + Property "mpu-s-regions": number of Secure MPU regions (default is
-@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
++ *   whatever the default for the CPU is; must currently be set to the same
-         g_assert_not_reached();
++ *   value as mpu-ns-regions if the CPU implements the Security Extension)
   * + Clock input "refclk" is the external reference clock for the systick timers
   * + Clock input "cpuclk" is the main CPU clock
   */
@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
      Object *idau;
      uint32_t init_svtor;
      uint32_t init_nsvtor;
 +    uint32_t mpu_ns_regions;
 +    uint32_t mpu_s_regions;
      bool enable_bitband;
      bool start_powered_off;
      bool vfp;
 diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/armv7m.c
 +++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
          }
      }
 +    /*
-+     * If /psci node is present in provided DTB, assume that no fixup
++     * Real M-profile hardware can be configured with a different number of
-+     * is necessary and all PSCI configuration should be taken as-is
++     * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
 +     * support that yet, so catch attempts to select that.
 +     */
-+    rc = fdt_path_offset(fdt, "/psci");
++    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
-+    if (rc >= 0) {
++        s->mpu_ns_regions != s->mpu_s_regions) {
 +        error_setg(errp,
 +                   "mpu-ns-regions and mpu-s-regions properties must have the same value");
 +        return;
 +    }
++    if (s->mpu_ns_regions != UINT_MAX &&
++        object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
++        if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
++                                      s->mpu_ns_regions, errp)) {
++            return;
++        }
++    }
 +
-     qemu_fdt_add_subnode(fdt, "/psci");
+     /*
-     if (armcpu->psci_version == 2) {
+      * Tell the CPU where the NVIC is; it will fail realize if it doesn't
-         const char comp[] = "arm,psci-0.2\0arm,psci";
+      * have one. Similarly, tell the NVIC where its CPU is.
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
                       false),
      DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
      DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
 +    DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
 +    DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
      DEFINE_PROP_END_OF_LIST(),
  };
 --
-.16.2
+.34.1

-New patch
+[PULL 24/24] hw/arm: Set number of MPU regions correctly for an505, an521, an524
+The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
 MPS2/MPS3 FPGA images don't override these except in the case of
 AN547, which uses 16 MPU regions.
 Define properties on the ARMSSE object for the MPU regions (using the
 same names as the documented RTL configuration settings, and
 following the pattern we already have for this device of using
 all-caps names as the RTL does), and set them in the board code.
 We don't actually need to override the default except on AN547,
 but it's simpler code to have the board code set them always
 rather than tracking which board subtypes want to set them to
 a non-default value separately from what that value is.
 Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
 we now correctly use 8 MPU regions, while mps3-an547 stays at its
 current 16 regions.
 It's possible some guest code wrongly depended on the previous
 incorrectly modeled number of memory regions. (Such guest code
 should ideally check the number of regions via the MPU_TYPE
 register.) The old behaviour can be obtained with additional
 -global arguments to QEMU:
 For mps2-an521 and mps2-an524:
  -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16
 For mps2-an505:
  -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16
 NB that the way the implementation allows this use of -global
 is slightly fragile: if the board code explicitly sets the
 properties on the sse-200 object, this overrides the -global
 command line option. So we rely on:
  - the boards that need fixing all happen to use the SSE defaults
  - we can write the board code to only set the property if it
    is different from the default, rather than having all boards
    explicitly set the property
  - the board that does need to use a non-default value happens
    to need to set it to the same value (16) we previously used
 This works, but there are some kinds of refactoring of the
 mps2-tz.c code that would break the support for -global here.
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
 ---
  include/hw/arm/armsse.h |  5 +++++
  hw/arm/armsse.c         | 16 ++++++++++++++++
  hw/arm/mps2-tz.c        | 29 +++++++++++++++++++++++++++++
 files changed, 50 insertions(+)
 diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/armsse.h
 +++ b/include/hw/arm/armsse.h
@@ -XXX,XX +XXX,XX @@
   *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
   *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
   *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
 + *  + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
 + *    which set the number of MPU regions on the CPUs. If there is only one
 + *    CPU the CPU1 properties are not present.
   *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
   *    which are wired to its NVIC lines 32 .. n+32
   *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
      uint32_t exp_numirq;
      uint32_t sram_addr_width;
      uint32_t init_svtor;
 +    uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
 +    uint32_t cpu_mpu_s[SSE_MAX_CPUS];
      bool cpu_fpu[SSE_MAX_CPUS];
      bool cpu_dsp[SSE_MAX_CPUS];
  };
 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/armsse.c
 +++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
      DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
      DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
      DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
 +    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
 +    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
      DEFINE_PROP_END_OF_LIST()
  };
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
      DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
      DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
      DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
 +    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
 +    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
 +    DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
 +    DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
      DEFINE_PROP_END_OF_LIST()
  };
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
      DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
      DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
      DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
 +    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
 +    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
      DEFINE_PROP_END_OF_LIST()
  };
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                  return;
              }
          }
 +        if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
 +                                      s->cpu_mpu_ns[i], errp)) {
 +            return;
 +        }
 +        if (!object_property_set_uint(cpuobj, "mpu-s-regions",
 +                                      s->cpu_mpu_s[i], errp)) {
 +            return;
 +        }
          if (i > 0) {
              memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/mps2-tz.c
 +++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
      int uart_overflow_irq; /* number of the combined UART overflow IRQ */
      uint32_t init_svtor; /* init-svtor setting for SSE */
      uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
 +    uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
 +    uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
 +    uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
 +    uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
      const RAMInfo *raminfo;
      const char *armsse_type;
      uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
  #define MPS3_DDR_SIZE (2 * GiB)
  #endif
 +/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
 +#define MPU_REGION_DEFAULT UINT32_MAX
 +
  static const uint32_t an505_oscclk[] = {
      40000000,
      24580000,
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                               OBJECT(system_memory), &error_abort);
      qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
      qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
 +    if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
 +        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
 +    }
 +    if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
 +        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
 +    }
 +    if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
 +        if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
 +            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
 +        }
 +        if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
 +            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
 +        }
 +    }
      qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
      qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
      qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
  {
      MachineClass *mc = MACHINE_CLASS(oc);
      IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
 +    MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
      mc->init = mps2tz_common_init;
      mc->reset = mps2_machine_reset;
      iic->check = mps2_tz_idau_check;
 +
 +    /* Most machines leave these at the SSE defaults */
 +    mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
 +    mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
 +    mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
 +    mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
  }
  static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
      mmc->numirq = 96;
      mmc->uart_overflow_irq = 48;
      mmc->init_svtor = 0x00000000;
 +    mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
      mmc->sram_addr_width = 21;
      mmc->raminfo = an547_raminfo;
      mmc->armsse_type = TYPE_SSE300;
 --
 .34.1

Arm patch queue for 2.12 -- a miscellaneous collection
of bug fixes.

thanks
-- PMM

The following changes since commit fb4fe32d5b6290deabe752b51cc1cc2a9e8573db:

Merge remote-tracking branch 'remotes/xtensa/tags/20180409-xtensa' into staging (2018-04-10 10:22:45 +0100)

are available in the Git repository at:

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180410

for you to fetch changes up to bd49e6027cbc207c87633c7add3ebd7d3474cd35:

fpu: Fix rounding mode for floatN_to_uintM_round_to_zero (2018-04-10 13:02:26 +0100)

----------------------------------------------------------------
target-arm queue:
 * fpu: Fix rounding mode for floatN_to_uintM_round_to_zero
 * tcg: Fix guest state corruption when running 64-bit Arm
   guests on a 32-bit host (especially when using icount)
 * linux-user/signal.c: Ensure AArch64 signal frame isn't too small
 * cpus.c: ensure running CPU recalculates icount deadlines on timer expiry
 * target/arm: Report unsupported MPU region sizes more clearly
 * hw/arm/fsl-imx: Fix introspection problem with fsl-imx6 and fsl-imx7
 * hw/arm/allwinner-a10: Do not use nd_table in instance_init function
 * hw/sd/bcm2835_sdhost: Don't raise spurious interrupts
 * hw/sd/bcm2835_sdhost: Add tracepoints
 * target-arm: Check undefined opcodes for SWP in A32 decoder
 * hw/arm/integratorcp: Don't do things that could be fatal in the instance_init
 * hw/arm: Allow manually specified /psci node

----------------------------------------------------------------
Andrey Smirnov (1):
      hw/arm: Allow manually specified /psci node

Onur Sahin (1):
      target-arm: Check undefined opcodes for SWP in A32 decoder

Peter Maydell (5):
      hw/sd/bcm2835_sdhost: Add tracepoints
      hw/sd/bcm2835_sdhost: Don't raise spurious interrupts
      target/arm: Report unsupported MPU region sizes more clearly
      cpus.c: ensure running CPU recalculates icount deadlines on timer expiry
      linux-user/signal.c: Ensure AArch64 signal frame isn't too small

Richard Henderson (2):
      tcg: Introduce tcg_set_insn_start_param
      fpu: Fix rounding mode for floatN_to_uintM_round_to_zero

Thomas Huth (3):
      hw/arm/integratorcp: Don't do things that could be fatal in the instance_init
      hw/arm/allwinner-a10: Do not use nd_table in instance_init function
      hw/arm/fsl-imx: Fix introspection problem with fsl-imx6 and fsl-imx7

From: Andrey Smirnov <andrew.smirnov@gmail.com>

Change the code to avoid exiting QEMU if user provided DTB contains
manually specified /psci node and skip any /psci related fixups
instead.

Fixes: 4cbca7d9b4 ("hw/arm: Move virt's PSCI DT fixup code to
arm/boot.c")

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reported-by: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Message-id: 20180402205654.14572-1-andrew.smirnov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/boot.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
     ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
     const char *psci_method;
     int64_t psci_conduit;
+    int rc;
 
     psci_conduit = object_property_get_int(OBJECT(armcpu),
                                            "psci-conduit",
@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)
         g_assert_not_reached();
     }
 
+    /*
+     * If /psci node is present in provided DTB, assume that no fixup
+     * is necessary and all PSCI configuration should be taken as-is
+     */
+    rc = fdt_path_offset(fdt, "/psci");
+    if (rc >= 0) {
+        return;
+    }
+
     qemu_fdt_add_subnode(fdt, "/psci");
     if (armcpu->psci_version == 2) {
         const char comp[] = "arm,psci-0.2\0arm,psci";
-- 
2.16.2

From: Thomas Huth <thuth@redhat.com>

An instance_init function must not fail - and might be called multiple times,
e.g. during device introspection with the 'device-list-properties' QMP
command. Since the integratorcm device ignores this rule, QEMU currently
aborts in this case (though it really should not):

echo "{'execute':'qmp_capabilities'}"\
     "{'execute':'device-list-properties',"\
     "'arguments':{'typename':'integrator_core'}}" \
     | arm-softmmu/qemu-system-arm -M integratorcp,accel=qtest -qmp stdio
{"QMP": {"version": {"qemu": {"micro": 91, "minor": 11, "major": 2},
 "package": "build-all"}, "capabilities": []}}
{"return": {}}
RAMBlock "integrator.flash" already registered, abort!
Aborted (core dumped)

Move the problematic code to the realize() function instead to fix this
problem.

Reviewed-by: Philippe Mathieu-DaudÃ© <f4bug@amsat.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-id: 1522906473-11252-1-git-send-email-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/integratorcp.c | 23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps integratorcm_ops = {
 static void integratorcm_init(Object *obj)
 {
     IntegratorCMState *s = INTEGRATOR_CM(obj);
-    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 
     s->cm_osc = 0x01000048;
     /* ??? What should the high bits of this value be?  */
@@ -XXX,XX +XXX,XX @@ static void integratorcm_init(Object *obj)
     s->cm_init = 0x00000112;
     s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
                                    1000);
-    memory_region_init_ram(&s->flash, obj, "integrator.flash", 0x100000,
-                           &error_fatal);
 
-    memory_region_init_io(&s->iomem, obj, &integratorcm_ops, s,
-                          "integratorcm", 0x00800000);
-    sysbus_init_mmio(dev, &s->iomem);
-
-    integratorcm_do_remap(s);
     /* ??? Save/restore.  */
 }
 
 static void integratorcm_realize(DeviceState *d, Error **errp)
 {
     IntegratorCMState *s = INTEGRATOR_CM(d);
+    SysBusDevice *dev = SYS_BUS_DEVICE(d);
+    Error *local_err = NULL;
+
+    memory_region_init_ram(&s->flash, OBJECT(d), "integrator.flash", 0x100000,
+                           &local_err);
+    if (local_err) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+    memory_region_init_io(&s->iomem, OBJECT(d), &integratorcm_ops, s,
+                          "integratorcm", 0x00800000);
+    sysbus_init_mmio(dev, &s->iomem);
+
+    integratorcm_do_remap(s);
 
     if (s->memsz >= 256) {
         integrator_spd[31] = 64;
-- 
2.16.2

From: Onur Sahin <onursahin08@gmail.com>

Make sure we are not treating architecturally Undefined instructions
as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A
specification. Bits [21:20] must be zero for this to be a SWP or SWPB.
We also choose to UNDEF for the architecturally UNPREDICTABLE case of
bits [11:8] not being zero.

Signed-off-by: Onur Sahin <onursahin08@gmail.com>
[PMM: tweaked commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                             }
                         }
                         tcg_temp_free_i32(addr);
-                    } else {
+                    } else if ((insn & 0x00300f00) == 0) {
+                        /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx
+                        *  - SWP, SWPB
+                        */
+
                         TCGv taddr;
                         TCGMemOp opc = s->be_data;
 
-                        /* SWP instruction */
                         rm = (insn) & 0xf;
 
                         if (insn & (1 << 22)) {
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                                                 get_mem_index(s), opc);
                         tcg_temp_free(taddr);
                         store_reg(s, rd, tmp);
+                    } else {
+                        goto illegal_op;
                     }
                 }
             } else {
-- 
2.16.2

Add some tracepoints to the bcm2835_sdhost driver, to assist
debugging.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20180319161556.16446-2-peter.maydell@linaro.org
---
 hw/sd/bcm2835_sdhost.c | 10 ++++++++++
 hw/sd/trace-events     |  6 ++++++
 2 files changed, 16 insertions(+)

diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/bcm2835_sdhost.c
+++ b/hw/sd/bcm2835_sdhost.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/log.h"
 #include "sysemu/blockdev.h"
 #include "hw/sd/bcm2835_sdhost.h"
+#include "trace.h"
 
 #define TYPE_BCM2835_SDHOST_BUS "bcm2835-sdhost-bus"
 #define BCM2835_SDHOST_BUS(obj) \
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_update_irq(BCM2835SDHostState *s)
 {
     uint32_t irq = s->status &
         (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | SDHSTS_SDIO_IRPT);
+    trace_bcm2835_sdhost_update_irq(irq);
     qemu_set_irq(s->irq, !!irq);
 }
 
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
 
         s->edm &= ~0xf;
         s->edm |= SDEDM_FSM_DATAMODE;
+        trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm);
 
         if (s->config & SDHCFG_DATA_IRPT_EN) {
             s->status |= SDHSTS_SDIO_IRPT;
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
 
     s->edm &= ~(0x1f << 4);
     s->edm |= ((s->fifo_len & 0x1f) << 4);
+    trace_bcm2835_sdhost_edm_change("fifo run", s->edm);
 }
 
 static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset,
@@ -XXX,XX +XXX,XX @@ static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset,
         break;
     }
 
+    trace_bcm2835_sdhost_read(offset, res, size);
+
     return res;
 }
 
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
 {
     BCM2835SDHostState *s = (BCM2835SDHostState *)opaque;
 
+    trace_bcm2835_sdhost_write(offset, value, size);
+
     switch (offset) {
     case SDCMD:
         s->cmd = value;
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_write(void *opaque, hwaddr offset,
             value &= ~0xf;
         }
         s->edm = value;
+        trace_bcm2835_sdhost_edm_change("guest register write", s->edm);
         break;
     case SDHCFG:
         s->config = value;
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_reset(DeviceState *dev)
     s->cmd = 0;
     s->cmdarg = 0;
     s->edm = 0x0000c60f;
+    trace_bcm2835_sdhost_edm_change("device reset", s->edm);
     s->config = 0;
     s->hbct = 0;
     s->hblc = 0;
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/trace-events
+++ b/hw/sd/trace-events
@@ -XXX,XX +XXX,XX @@
 # See docs/devel/tracing.txt for syntax documentation.
 
+# hw/sd/bcm2835_sdhost.c
+bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+bcm2835_sdhost_edm_change(const char *why, uint32_t edm) "(%s) EDM now 0x%x"
+bcm2835_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x\n"
+
 # hw/sd/core.c
 sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg, uint8_t crc) "@%s CMD%02d arg 0x%08x crc 0x%02x"
 sdbus_read(const char *bus_name, uint8_t value) "@%s value 0x%02x"
-- 
2.16.2

The Linux bcm2835_sdhost driver doesn't work on QEMU, because our
model raises spurious data interrupts.  Our function
bcm2835_sdhost_fifo_run() will flag an interrupt any time it is
called with s->datacnt == 0, even if the host hasn't actually issued
a data read or write command yet.  This means that the driver gets a
spurious data interrupt as soon as it enables IRQs and then does
something else that causes us to call the fifo_run routine, like
writing to SDHCFG, and before it does the write to SDCMD to issue the
read.  The driver's IRQ handler then spins forever complaining that
there's no data and the SD controller isn't in a state where there's
going to be any data:

[   41.040738] sdhost-bcm2835 3f202000.mmc: fsm 1, hsts 00000000
[   41.042059] sdhost-bcm2835 3f202000.mmc: fsm 1, hsts 00000000
(continues forever).

Move the interrupt flag setting to more plausible places:
 * for BUSY, raise this as soon as a BUSYWAIT command has executed
 * for DATA, raise this when the FIFO has any space free (for a write)
   or any data in it (for a read)
 * for BLOCK, raise this when the data count is 0 and we've
   actually done some reading or writing

This is pure guesswork since the documentation for this hardware is
not public, but it is sufficient to get the Linux bcm2835_sdhost
driver to work.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id: 20180319161556.16446-3-peter.maydell@linaro.org
---
 hw/sd/bcm2835_sdhost.c | 46 ++++++++++++++++++++++++++--------------------
 1 file changed, 26 insertions(+), 20 deletions(-)

diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/sd/bcm2835_sdhost.c
+++ b/hw/sd/bcm2835_sdhost.c
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_send_command(BCM2835SDHostState *s)
         }
 #undef RWORD
     }
+    /* We never really delay commands, so if this was a 'busywait' command
+     * then we've completed it now and can raise the interrupt.
+     */
+    if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) {
+        s->status |= SDHSTS_BUSY_IRPT;
+    }
     return;
 
 error:
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
                 n++;
                 if (n == 4) {
                     bcm2835_sdhost_fifo_push(s, value);
+                    s->status |= SDHSTS_DATA_FLAG;
+                    if (s->config & SDHCFG_DATA_IRPT_EN) {
+                        s->status |= SDHSTS_SDIO_IRPT;
+                    }
                     n = 0;
                     value = 0;
                 }
             }
             if (n != 0) {
                 bcm2835_sdhost_fifo_push(s, value);
+                s->status |= SDHSTS_DATA_FLAG;
             }
         } else { /* write */
             n = 0;
             while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) {
                 if (n == 0) {
                     value = bcm2835_sdhost_fifo_pop(s);
+                    s->status |= SDHSTS_DATA_FLAG;
+                    if (s->config & SDHCFG_DATA_IRPT_EN) {
+                        s->status |= SDHSTS_SDIO_IRPT;
+                    }
                     n = 4;
                 }
                 n--;
@@ -XXX,XX +XXX,XX @@ static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s)
                 value >>= 8;
             }
         }
+        if (s->datacnt == 0) {
+            s->edm &= ~SDEDM_FSM_MASK;
+            s->edm |= SDEDM_FSM_DATAMODE;
+            trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm);
+
+            if ((s->cmd & SDCMD_WRITE_CMD) &&
+                (s->config & SDHCFG_BLOCK_IRPT_EN)) {
+                s->status |= SDHSTS_BLOCK_IRPT;
+            }
+        }
     }
-    if (s->datacnt == 0) {
-        s->status |= SDHSTS_DATA_FLAG;
 
-        s->edm &= ~0xf;
-        s->edm |= SDEDM_FSM_DATAMODE;
-        trace_bcm2835_sdhost_edm_change("datacnt 0", s->edm);
-
-        if (s->config & SDHCFG_DATA_IRPT_EN) {
-            s->status |= SDHSTS_SDIO_IRPT;
-        }
-
-        if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) {
-            s->status |= SDHSTS_BUSY_IRPT;
-        }
-
-        if ((s->cmd & SDCMD_WRITE_CMD) && (s->config & SDHCFG_BLOCK_IRPT_EN)) {
-            s->status |= SDHSTS_BLOCK_IRPT;
-        }
-
-        bcm2835_sdhost_update_irq(s);
-    }
+    bcm2835_sdhost_update_irq(s);
 
     s->edm &= ~(0x1f << 4);
     s->edm |= ((s->fifo_len & 0x1f) << 4);
-- 
2.16.2

From: Thomas Huth <thuth@redhat.com>

The instance_init function of a device can be called at any time, even
if the device is not going to be used (i.e. not going to be realized).
So a instance_init function must not do things that could cause QEMU
to exit, like calling qemu_check_nic_model(&nd_table[0], ...) for example.
But this is what the instance_init function of the allwinner-a10 device
is currently doing - and this causes QEMU to quit unexpectedly when
you run the 'device-list-properties' QMP command for example:

$ echo "{'execute':'qmp_capabilities'}"\
       "{'execute':'device-list-properties',"\
       " 'arguments':{'typename':'allwinner-a10'}}" \
       | arm-softmmu/qemu-system-arm -M mps2-an505,accel=qtest -qmp stdio
{"QMP": {"version": {"qemu": {"micro": 91, "minor": 11, "major": 2},
 "package": "build-all"}, "capabilities": []}}
{"return": {}}
Unsupported NIC model: lan9118

... and QEMU quits after printing the last line (which should not happen
just because of running 'device-list-properties' here).

And with the cubieboard, this even causes QEMU to abort():

$ echo "{'execute':'qmp_capabilities'}"\
       "{'execute':'device-list-properties',"\
       " 'arguments':{'typename':'allwinner-a10'}}" \
       | arm-softmmu/qemu-system-arm -M cubieboard,accel=qtest -qmp stdio
{"QMP": {"version": {"qemu": {"micro": 91, "minor": 11, "major": 2},
 "package": "build-all"}, "capabilities": []}}
{"return": {}}
Unexpected error in error_set_from_qdev_prop_error() at hw/core/qdev-properties.c:1095:
Property 'allwinner-emac.netdev' can't take value 'hub0port0', it's in use
Aborted (core dumped)

To fix the problem we've got to move the offending code to the realize
function instead.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-id: 1522862420-7484-1-git-send-email-thuth@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/allwinner-a10.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -XXX,XX +XXX,XX @@ static void aw_a10_init(Object *obj)
 
     object_initialize(&s->emac, sizeof(s->emac), TYPE_AW_EMAC);
     qdev_set_parent_bus(DEVICE(&s->emac), sysbus_get_default());
-    /* FIXME use qdev NIC properties instead of nd_table[] */
-    if (nd_table[0].used) {
-        qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
-        qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
-    }
 
     object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI);
     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
@@ -XXX,XX +XXX,XX @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
     sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
     sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
 
+    /* FIXME use qdev NIC properties instead of nd_table[] */
+    if (nd_table[0].used) {
+        qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
+        qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
+    }
     object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
     if (err != NULL) {
         error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void aw_a10_class_init(ObjectClass *oc, void *data)
     DeviceClass *dc = DEVICE_CLASS(oc);
 
     dc->realize = aw_a10_realize;
-    /* Reason: Uses serial_hds in realize and nd_table in instance_init */
+    /* Reason: Uses serial_hds and nd_table in realize function */
     dc->user_creatable = false;
 }
 
-- 
2.16.2

From: Thomas Huth <thuth@redhat.com>

QEMU currently exits unexpectedly when trying to introspect the fsl-imx6
and fsl-imx7 devices on systems with many SMP CPUs:

$ echo "{'execute':'qmp_capabilities'}"\
       "{'execute':'device-list-properties',"\
       " 'arguments':{'typename':'fsl,imx6'}}" \
       | arm-softmmu/qemu-system-arm -M virt,accel=qtest -qmp stdio -smp 8
{"QMP": {"version": {"qemu": {"micro": 91, "minor": 11, "major": 2},
 "package": "build-all"}, "capabilities": []}}
{"return": {}}
fsl,imx6: Only 4 CPUs are supported (8 requested)

And:

$ echo "{'execute':'qmp_capabilities'}"\
       "{'execute':'device-list-properties',"\
       " 'arguments':{'typename':'fsl,imx7'}}" \
       | arm-softmmu/qemu-system-arm -M raspi2,accel=qtest -qmp stdio
{"QMP": {"version": {"qemu": {"micro": 91, "minor": 11, "major": 2},
 "package": "build-all"}, "capabilities": []}}
{"return": {}}
fsl,imx7: Only 2 CPUs are supported (4 requested)

This happens because these devices are doing an exit() from their
instance_init function - which should never be done since instance_init
can be called at any time for device introspection! Fix it by moving
the deadly check into the realize() function instead.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-id: 1522908551-14885-1-git-send-email-thuth@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/fsl-imx6.c | 14 +++++++-------
 hw/arm/fsl-imx7.c | 13 +++++++------
 2 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_init(Object *obj)
     char name[NAME_SIZE];
     int i;
 
-    if (smp_cpus > FSL_IMX6_NUM_CPUS) {
-        error_report("%s: Only %d CPUs are supported (%d requested)",
-                     TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
-        exit(1);
-    }
-
-    for (i = 0; i < smp_cpus; i++) {
+    for (i = 0; i < MIN(smp_cpus, FSL_IMX6_NUM_CPUS); i++) {
         object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
                           "cortex-a9-" TYPE_ARM_CPU);
         snprintf(name, NAME_SIZE, "cpu%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
     uint16_t i;
     Error *err = NULL;
 
+    if (smp_cpus > FSL_IMX6_NUM_CPUS) {
+        error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
+                   TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus);
+        return;
+    }
+
     for (i = 0; i < smp_cpus; i++) {
 
         /* On uniprocessor, the CBAR is set to 0 */
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     char name[NAME_SIZE];
     int i;
 
-    if (smp_cpus > FSL_IMX7_NUM_CPUS) {
-        error_report("%s: Only %d CPUs are supported (%d requested)",
-                     TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
-        exit(1);
-    }
 
-    for (i = 0; i < smp_cpus; i++) {
+    for (i = 0; i < MIN(smp_cpus, FSL_IMX7_NUM_CPUS); i++) {
         object_initialize(&s->cpu[i], sizeof(s->cpu[i]),
                           ARM_CPU_TYPE_NAME("cortex-a7"));
         snprintf(name, NAME_SIZE, "cpu%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     qemu_irq irq;
     char name[NAME_SIZE];
 
+    if (smp_cpus > FSL_IMX7_NUM_CPUS) {
+        error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
+                   TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
+        return;
+    }
+
     for (i = 0; i < smp_cpus; i++) {
         o = OBJECT(&s->cpu[i]);
 
-- 
2.16.2

Currently our PMSAv7 and ARMv7M MPU implementation cannot handle
MPU region sizes smaller than our TARGET_PAGE_SIZE. However we
report that in a slightly confusing way:

DRSR[3]: No support for MPU (sub)region alignment of 9 bits. Minimum is 10

The problem is not the alignment of the region, but its size;
tweak the error message to say so:
 DRSR[3]: No support for MPU (sub)region size of 512 bytes. Minimum is 1024.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180405172554.27401-1-peter.maydell@linaro.org
---
 target/arm/helper.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
             }
             if (rsize < TARGET_PAGE_BITS) {
                 qemu_log_mask(LOG_UNIMP,
-                              "DRSR[%d]: No support for MPU (sub)region "
-                              "alignment of %" PRIu32 " bits. Minimum is %d\n",
-                              n, rsize, TARGET_PAGE_BITS);
+                              "DRSR[%d]: No support for MPU (sub)region size of"
+                              " %" PRIu32 " bytes. Minimum is %d.\n",
+                              n, (1 << rsize), TARGET_PAGE_SIZE);
                 continue;
             }
             if (srdis) {
-- 
2.16.2

When we run in TCG icount mode, we calculate the number of instructions
to execute using tcg_get_icount_limit(), which ensures that we stop
execution at the next timer deadline. However there is a bug where
currently we do not recalculate that limit if the guest reprograms
a timer so that the next deadline moves closer, and so we will
continue execution until the original limit and fire the timer
later than we should.

Fix this bug in qemu_timer_notify_cb(): if we are currently running
a VCPU in icount mode, we simply need to kick it out of the main
loop and back to tcg_cpu_exec(), where it will recalculate the
icount limit. If we are not currently running a VCPU, then we
retain the existing logic for waking up a halted CPU.

Cc: qemu-stable@nongnu.org
Fixes: https://bugs.launchpad.net/qemu/+bug/1754038
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180406123838.21249-1-peter.maydell@linaro.org
---
 cpus.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/cpus.c b/cpus.c
index XXXXXXX..XXXXXXX 100644
--- a/cpus.c
+++ b/cpus.c
@@ -XXX,XX +XXX,XX @@ void qemu_timer_notify_cb(void *opaque, QEMUClockType type)
         return;
     }
 
-    if (!qemu_in_vcpu_thread() && first_cpu) {
+    if (qemu_in_vcpu_thread()) {
+        /* A CPU is currently running; kick it back out to the
+         * tcg_cpu_exec() loop so it will recalculate its
+         * icount deadline immediately.
+         */
+        qemu_cpu_kick(current_cpu);
+    } else if (first_cpu) {
         /* qemu_cpu_kick is not enough to kick a halted CPU out of
          * qemu_tcg_wait_io_event.  async_run_on_cpu, instead,
          * causes cpu_thread_is_idle to return false.  This way,
          * handle_icount_deadline can run.
+         * If we have no CPUs at all for some reason, we don't
+         * need to do anything.
          */
         async_run_on_cpu(first_cpu, do_nothing, RUN_ON_CPU_NULL);
     }
-- 
2.16.2

The AArch64 signal frame design was extended for SVE in commit
8c5931de0ac77388096d79ceb, so that instead of having a fixed setup we
now add various records to the frame, with some of them possibly
overflowing into an extra space outside the original 4K reserved
block in the target_sigcontext.  However, we failed to ensure that we
always at least allocate the 4K reserved block.  This is ABI, and
some userspace programs rely on it.  In particular the dash shell
would segfault if the frame wasn't as big enough.

(Compare the kernel's sigframe_size() function in
arch/arm64/kernel/signal.c.)

Reported-by: Richard Henwood <richard.henwood@arm.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180409140714.26841-1-peter.maydell@linaro.org
Fixes: https://bugs.launchpad.net/bugs/1761535
Fixes: 8c5931de0ac77388096d79ceb
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/signal.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/linux-user/signal.c b/linux-user/signal.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -XXX,XX +XXX,XX @@ static void target_setup_frame(int usig, struct target_sigaction *ka,
     fr_ofs = layout.total_size;
     layout.total_size += sizeof(struct target_rt_frame_record);
 
+    /* We must always provide at least the standard 4K reserved space,
+     * even if we don't use all of it (this is part of the ABI)
+     */
+    layout.total_size = MAX(layout.total_size,
+                            sizeof(struct target_rt_sigframe));
+
     frame_addr = get_sigframe(ka, env, layout.total_size);
     trace_user_setup_frame(env, frame_addr);
     if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) {
-- 
2.16.2

From: Richard Henderson <richard.henderson@linaro.org>

The parameters for tcg_gen_insn_start are target_ulong, which may be split
into two TCGArg parameters for storage in the opcode on 32-bit hosts.

Fixes the ARM target and its direct use of tcg_set_insn_param, which would
set the wrong argument in the 64-on-32 case.

Cc: qemu-stable@nongnu.org
Reported-by: alarson@ddci.com
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180410003558.2470-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.h |  2 +-
 tcg/tcg.h              | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -XXX,XX +XXX,XX @@ static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 
     /* We check and clear insn_start_idx to catch multiple updates.  */
     assert(s->insn_start != NULL);
-    tcg_set_insn_param(s->insn_start, 2, syn);
+    tcg_set_insn_start_param(s->insn_start, 2, syn);
     s->insn_start = NULL;
 }
 
diff --git a/tcg/tcg.h b/tcg/tcg.h
index XXXXXXX..XXXXXXX 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -XXX,XX +XXX,XX @@ static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
     op->args[arg] = v;
 }
 
+static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
+{
+#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+    tcg_set_insn_param(op, arg, v);
+#else
+    tcg_set_insn_param(op, arg * 2, v);
+    tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
+#endif
+}
+
 /* The last op that was emitted.  */
 static inline TCGOp *tcg_last_op(void)
 {
-- 
2.16.2

From: Richard Henderson <richard.henderson@linaro.org>

We incorrectly passed in the current rounding mode
instead of float_round_to_zero.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180410055912.934-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 fpu/softfloat.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index XXXXXXX..XXXXXXX 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -XXX,XX +XXX,XX @@ uint ## isz ## _t float ## fsz ## _to_uint ## isz ## _round_to_zero     \
  (float ## fsz a, float_status *s)                                      \
 {                                                                       \
     FloatParts p = float ## fsz ## _unpack_canonical(a, s);             \
-    return round_to_uint_and_pack(p, s->float_rounding_mode,            \
-                                 UINT ## isz ## _MAX, s);               \
+    return round_to_uint_and_pack(p, float_round_to_zero,               \
+                                  UINT ## isz ## _MAX, s);              \
 }
 
 FLOAT_TO_UINT(16, 16)
-- 
2.16.2

Hi; here's the latest round of arm patches. I have included also
my patchset for the RTC devices to avoid keeping time_t and
time_t diffs in 32-bit variables.

thanks
-- PMM

The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:

Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-08-30 09:20:27 -0400)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230831

for you to fetch changes up to e73b8bb8a3e9a162f70e9ffbf922d4fafc96bbfb:

hw/arm: Set number of MPU regions correctly for an505, an521, an524 (2023-08-31 11:07:02 +0100)

----------------------------------------------------------------
target-arm queue:
 * Some of the preliminary patches for Cortex-A710 support
 * i.MX7 and i.MX6UL refactoring
 * Implement SRC device for i.MX7
 * Catch illegal-exception-return from EL3 with bad NSE/NS
 * Use 64-bit offsets for holding time_t differences in RTC devices
 * Model correct number of MPU regions for an505, an521, an524 boards

----------------------------------------------------------------
Alex Bennée (1):
      target/arm: properly document FEAT_CRC32

Jean-Christophe Dubois (6):
      Remove i.MX7 IOMUX GPR device from i.MX6UL
      Refactor i.MX6UL processor code
      Add i.MX6UL missing devices.
      Refactor i.MX7 processor code
      Add i.MX7 missing TZ devices and memory regions
      Add i.MX7 SRC device implementation

Peter Maydell (8):
      target/arm: Catch illegal-exception-return from EL3 with bad NSE/NS
      hw/rtc/m48t59: Use 64-bit arithmetic in set_alarm()
      hw/rtc/twl92230: Use int64_t for sec_offset and alm_sec
      hw/rtc/aspeed_rtc: Use 64-bit offset for holding time_t difference
      rtc: Use time_t for passing and returning time offsets
      target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
      hw/arm/armv7m: Add mpu-ns-regions and mpu-s-regions properties
      hw/arm: Set number of MPU regions correctly for an505, an521, an524

Richard Henderson (9):
      target/arm: Reduce dcz_blocksize to uint8_t
      target/arm: Allow cpu to configure GM blocksize
      target/arm: Support more GM blocksizes
      target/arm: When tag memory is not present, set MTE=1
      target/arm: Introduce make_ccsidr64
      target/arm: Apply access checks to neoverse-n1 special registers
      target/arm: Apply access checks to neoverse-v1 special registers
      target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
      target/arm: Implement FEAT_HPDS2 as a no-op

From: Richard Henderson <richard.henderson@linaro.org>

Previously we hard-coded the blocksize with GMID_EL1_BS.
But the value we choose for -cpu max does not match the
value that cortex-a710 uses.

Mirror the way we handle dcz_blocksize.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230811214031.171020-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h               |  2 ++
 target/arm/internals.h         |  6 -----
 target/arm/tcg/translate.h     |  2 ++
 target/arm/helper.c            | 11 +++++---
 target/arm/tcg/cpu64.c         |  1 +
 target/arm/tcg/mte_helper.c    | 46 ++++++++++++++++++++++------------
 target/arm/tcg/translate-a64.c |  5 ++--
 7 files changed, 45 insertions(+), 28 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
 
     /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
     uint8_t dcz_blocksize;
+    /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
+    uint8_t gm_blocksize;
 
     uint64_t rvbar_prop; /* Property/input signals.  */
 
diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ void arm_log_exception(CPUState *cs);
 
 #endif /* !CONFIG_USER_ONLY */
 
-/*
- * The log2 of the words in the tag block, for GMID_EL1.BS.
- * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
- */
-#define GMID_EL1_BS  6
-
 /*
  * SVE predicates are 1/8 the size of SVE vectors, and cannot use
  * the same simd_desc() encoding due to restrictions on size.
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
     int8_t btype;
     /* A copy of cpu->dcz_blocksize. */
     uint8_t dcz_blocksize;
+    /* A copy of cpu->gm_blocksize. */
+    uint8_t gm_blocksize;
     /* True if this page is guarded.  */
     bool guarded_page;
     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo mte_reginfo[] = {
       .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
       .access = PL1_RW, .accessfn = access_mte,
       .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
-    { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
-      .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
-      .access = PL1_R, .accessfn = access_aa64_tid5,
-      .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
     { .name = "TCO", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
       .type = ARM_CP_NO_RAW,
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
      * then define only a RAZ/WI version of PSTATE.TCO.
      */
     if (cpu_isar_feature(aa64_mte, cpu)) {
+        ARMCPRegInfo gmid_reginfo = {
+            .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
+            .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
+            .access = PL1_R, .accessfn = access_aa64_tid5,
+            .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize,
+        };
+        define_one_arm_cp_reg(cpu, &gmid_reginfo);
         define_arm_cp_regs(cpu, mte_reginfo);
         define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo);
     } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
     cpu->dcz_blocksize = 7; /*  512 bytes */
 #endif
+    cpu->gm_blocksize = 6;  /*  256 bytes */
 
     cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
     cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
     }
 }
 
-#define LDGM_STGM_SIZE  (4 << GMID_EL1_BS)
-
 uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 {
     int mmu_idx = cpu_mmu_index(env, false);
     uintptr_t ra = GETPC();
+    int gm_bs = env_archcpu(env)->gm_blocksize;
+    int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
 
-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
+    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
     /* Trap if accessing an invalid page.  */
     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
+                                 gm_bs_bytes, MMU_DATA_LOAD,
+                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
 
     /* The tag is squashed to zero if the page does not support tags.  */
     if (!tag_mem) {
         return 0;
     }
 
-    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
     /*
-     * We are loading 64-bits worth of tags.  The ordering of elements
-     * within the word corresponds to a 64-bit little-endian operation.
+     * The ordering of elements within the word corresponds to
+     * a little-endian operation.
      */
-    return ldq_le_p(tag_mem);
+    switch (gm_bs) {
+    case 6:
+        /* 256 bytes -> 16 tags -> 64 result bits */
+        return ldq_le_p(tag_mem);
+    default:
+        /* cpu configured with unsupported gm blocksize. */
+        g_assert_not_reached();
+    }
 }
 
 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
 {
     int mmu_idx = cpu_mmu_index(env, false);
     uintptr_t ra = GETPC();
+    int gm_bs = env_archcpu(env)->gm_blocksize;
+    int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
 
-    ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE);
+    ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
     /* Trap if accessing an invalid page.  */
     tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
-                                 LDGM_STGM_SIZE, MMU_DATA_LOAD,
-                                 LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra);
+                                 gm_bs_bytes, MMU_DATA_LOAD,
+                                 gm_bs_bytes / (2 * TAG_GRANULE), ra);
 
     /*
      * Tag store only happens if the page support tags,
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
         return;
     }
 
-    QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6);
     /*
-     * We are storing 64-bits worth of tags.  The ordering of elements
-     * within the word corresponds to a 64-bit little-endian operation.
+     * The ordering of elements within the word corresponds to
+     * a little-endian operation.
      */
-    stq_le_p(tag_mem, val);
+    switch (gm_bs) {
+    case 6:
+        stq_le_p(tag_mem, val);
+        break;
+    default:
+        /* cpu configured with unsupported gm blocksize. */
+        g_assert_not_reached();
+    }
 }
 
 void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a)
         gen_helper_stgm(cpu_env, addr, tcg_rt);
     } else {
         MMUAccessType acc = MMU_DATA_STORE;
-        int size = 4 << GMID_EL1_BS;
+        int size = 4 << s->gm_blocksize;
 
         clean_addr = clean_data_tbi(s, addr);
         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a)
         gen_helper_ldgm(tcg_rt, cpu_env, addr);
     } else {
         MMUAccessType acc = MMU_DATA_LOAD;
-        int size = 4 << GMID_EL1_BS;
+        int size = 4 << s->gm_blocksize;
 
         clean_addr = clean_data_tbi(s, addr);
         tcg_gen_andi_i64(clean_addr, clean_addr, -size);
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
     dc->cp_regs = arm_cpu->cp_regs;
     dc->features = env->features;
     dc->dcz_blocksize = arm_cpu->dcz_blocksize;
+    dc->gm_blocksize = arm_cpu->gm_blocksize;
 
 #ifdef CONFIG_USER_ONLY
     /* In sve_probe_page, we assume TBI is enabled. */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Support all of the easy GM block sizes.
Use direct memory operations, since the pointers are aligned.

While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
an atomic store of one nibble.  This is not difficult, but there
is also no point in supporting it until required.

Note that cortex-a710 sets GM blocksize to match its cacheline
size of 64 bytes.  I expect many implementations will also
match the cacheline, which makes 16 bytes very unlikely.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c            | 18 +++++++++---
 target/arm/tcg/mte_helper.c | 56 +++++++++++++++++++++++++++++++------
 2 files changed, 62 insertions(+), 12 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
                                        ID_PFR1, VIRTUALIZATION, 0);
     }
 
+    if (cpu_isar_feature(aa64_mte, cpu)) {
+        /*
+         * The architectural range of GM blocksize is 2-6, however qemu
+         * doesn't support blocksize of 2 (see HELPER(ldgm)).
+         */
+        if (tcg_enabled()) {
+            assert(cpu->gm_blocksize >= 3 && cpu->gm_blocksize <= 6);
+        }
+
 #ifndef CONFIG_USER_ONLY
-    if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
         /*
          * Disable the MTE feature bits if we do not have tag-memory
          * provided by the machine.
          */
-        cpu->isar.id_aa64pfr1 =
-            FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
-    }
+        if (cpu->tag_memory == NULL) {
+            cpu->isar.id_aa64pfr1 =
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+        }
 #endif
+    }
 
     if (tcg_enabled()) {
         /*
diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/mte_helper.c
+++ b/target/arm/tcg/mte_helper.c
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
     int gm_bs = env_archcpu(env)->gm_blocksize;
     int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
+    uint64_t ret;
+    int shift;
 
     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr)
 
     /*
      * The ordering of elements within the word corresponds to
-     * a little-endian operation.
+     * a little-endian operation.  Computation of shift comes from
+     *
+     *     index = address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>
+     *     data<index*4+3:index*4> = tag
+     *
+     * Because of the alignment of ptr above, BS=6 has shift=0.
+     * All memory operations are aligned.  Defer support for BS=2,
+     * requiring insertion or extraction of a nibble, until we
+     * support a cpu that requires it.
      */
     switch (gm_bs) {
+    case 3:
+        /* 32 bytes -> 2 tags -> 8 result bits */
+        ret = *(uint8_t *)tag_mem;
+        break;
+    case 4:
+        /* 64 bytes -> 4 tags -> 16 result bits */
+        ret = cpu_to_le16(*(uint16_t *)tag_mem);
+        break;
+    case 5:
+        /* 128 bytes -> 8 tags -> 32 result bits */
+        ret = cpu_to_le32(*(uint32_t *)tag_mem);
+        break;
     case 6:
         /* 256 bytes -> 16 tags -> 64 result bits */
-        return ldq_le_p(tag_mem);
+        return cpu_to_le64(*(uint64_t *)tag_mem);
     default:
-        /* cpu configured with unsupported gm blocksize. */
+        /*
+         * CPU configured with unsupported/invalid gm blocksize.
+         * This is detected early in arm_cpu_realizefn.
+         */
         g_assert_not_reached();
     }
+    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
+    return ret << shift;
 }
 
 void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
     int gm_bs = env_archcpu(env)->gm_blocksize;
     int gm_bs_bytes = 4 << gm_bs;
     void *tag_mem;
+    int shift;
 
     ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes);
 
@@ -XXX,XX +XXX,XX @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val)
         return;
     }
 
-    /*
-     * The ordering of elements within the word corresponds to
-     * a little-endian operation.
-     */
+    /* See LDGM for comments on BS and on shift.  */
+    shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4;
+    val >>= shift;
     switch (gm_bs) {
+    case 3:
+        /* 32 bytes -> 2 tags -> 8 result bits */
+        *(uint8_t *)tag_mem = val;
+        break;
+    case 4:
+        /* 64 bytes -> 4 tags -> 16 result bits */
+        *(uint16_t *)tag_mem = cpu_to_le16(val);
+        break;
+    case 5:
+        /* 128 bytes -> 8 tags -> 32 result bits */
+        *(uint32_t *)tag_mem = cpu_to_le32(val);
+        break;
     case 6:
-        stq_le_p(tag_mem, val);
+        /* 256 bytes -> 16 tags -> 64 result bits */
+        *(uint64_t *)tag_mem = cpu_to_le64(val);
         break;
     default:
         /* cpu configured with unsupported gm blocksize. */
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

When the cpu support MTE, but the system does not, reduce cpu
support to user instructions at EL0 instead of completely
disabling MTE.  If we encounter a cpu implementation which does
something else, we can revisit this setting.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 
 #ifndef CONFIG_USER_ONLY
         /*
-         * Disable the MTE feature bits if we do not have tag-memory
-         * provided by the machine.
+         * If we do not have tag-memory provided by the machine,
+         * reduce MTE support to instructions enabled at EL0.
+         * This matches Cortex-A710 BROADCASTMTE input being LOW.
          */
         if (cpu->tag_memory == NULL) {
             cpu->isar.id_aa64pfr1 =
-                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+                FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
         }
 #endif
     }
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Do not hard-code the constants for Neoverse V1.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 48 ++++++++++++++++++++++++++++--------------
 1 file changed, 32 insertions(+), 16 deletions(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/module.h"
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
+#include "qemu/units.h"
 #include "internals.h"
 #include "cpregs.h"
 
+static uint64_t make_ccsidr64(unsigned assoc, unsigned linesize,
+                              unsigned cachesize)
+{
+    unsigned lg_linesize = ctz32(linesize);
+    unsigned sets;
+
+    /*
+     * The 64-bit CCSIDR_EL1 format is:
+     *   [55:32] number of sets - 1
+     *   [23:3]  associativity - 1
+     *   [2:0]   log2(linesize) - 4
+     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
+     */
+    assert(assoc != 0);
+    assert(is_power_of_2(linesize));
+    assert(lg_linesize >= 4 && lg_linesize <= 7 + 4);
+
+    /* sets * associativity * linesize == cachesize. */
+    sets = cachesize / (assoc * linesize);
+    assert(cachesize % (assoc * linesize) == 0);
+
+    return ((uint64_t)(sets - 1) << 32)
+         | ((assoc - 1) << 3)
+         | (lg_linesize - 4);
+}
+
 static void aarch64_a35_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -XXX,XX +XXX,XX @@ static void aarch64_neoverse_v1_initfn(Object *obj)
      * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values,
      * but also says it implements CCIDX, which means they should be
      * 64-bit format. So we here use values which are based on the textual
-     * information in chapter 2 of the TRM (and on the fact that
-     * sets * associativity * linesize == cachesize).
-     *
-     * The 64-bit CCSIDR_EL1 format is:
-     *   [55:32] number of sets - 1
-     *   [23:3]  associativity - 1
-     *   [2:0]   log2(linesize) - 4
-     *           so 0 == 16 bytes, 1 == 32 bytes, 2 == 64 bytes, etc
-     *
-     * L1: 4-way set associative 64-byte line size, total size 64K,
-     * so sets is 256.
+     * information in chapter 2 of the TRM:
      *
+     * L1: 4-way set associative 64-byte line size, total size 64K.
      * L2: 8-way set associative, 64 byte line size, either 512K or 1MB.
-     * We pick 1MB, so this has 2048 sets.
-     *
      * L3: No L3 (this matches the CLIDR_EL1 value).
      */
-    cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */
-    cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */
-    cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 cache */
+    cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
+    cpu->ccsidr[1] = cpu->ccsidr[0];                 /* L1 icache */
+    cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB);  /* L2 cache */
 
     /* From 3.2.115 SCTLR_EL3 */
     cpu->reset_sctlr = 0x30c50838;
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Access to many of the special registers is enabled or disabled
by ACTLR_EL[23], which we implement as constant 0, which means
that all writes outside EL3 should trap.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpregs.h    |  2 ++
 target/arm/helper.c    |  4 ++--
 target/arm/tcg/cpu64.c | 46 +++++++++++++++++++++++++++++++++---------
 3 files changed, 41 insertions(+), 11 deletions(-)

diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -XXX,XX +XXX,XX @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
 #endif
 
+CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool);
+
 #endif /* TARGET_ARM_CPREGS_H */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
 }
 
 /* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM.  */
-static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
-                                      bool isread)
+CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo *ri,
+                               bool isread)
 {
     if (arm_current_el(env) == 1) {
         uint64_t trap = isread ? HCR_TRVM : HCR_TVM;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_a64fx_initfn(Object *obj)
     /* TODO:  Add A64FX specific HPC extension registers */
 }
 
+static CPAccessResult access_actlr_w(CPUARMState *env, const ARMCPRegInfo *r,
+                                     bool read)
+{
+    if (!read) {
+        int el = arm_current_el(env);
+
+        /* Because ACTLR_EL2 is constant 0, writes below EL2 trap to EL2. */
+        if (el < 2 && arm_is_el2_enabled(env)) {
+            return CP_ACCESS_TRAP_EL2;
+        }
+        /* Because ACTLR_EL3 is constant 0, writes below EL3 trap to EL3. */
+        if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
+            return CP_ACCESS_TRAP_EL3;
+        }
+    }
+    return CP_ACCESS_OK;
+}
+
 static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
     { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      /* Traps and enables are the same as for TCR_EL1. */
+      .accessfn = access_tvm_trvm, .fgt = FGT_TCR_EL1, },
     { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     /*
      * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
      * (and in particular its system registers).
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
     { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010,
+      .accessfn = access_actlr_w },
     { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
 };
 
 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

There is only one additional EL1 register modeled, which
also needs to use access_actlr_w.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/cpu64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
 static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = {
     { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5,
-      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+      .accessfn = access_actlr_w },
     { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0,
       .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
external to the cpu, which is out of scope for QEMU.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         /* FEAT_SPE (Statistical Profiling Extension) */
         cpu->isar.id_aa64dfr0 =
             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
+        /* FEAT_TRBE (Trace Buffer Extension) */
+        cpu->isar.id_aa64dfr0 =
+            FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
         /* FEAT_TRF (Self-hosted Trace Extension) */
         cpu->isar.id_aa64dfr0 =
             FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
-- 
2.34.1

From: Richard Henderson <richard.henderson@linaro.org>

This feature allows the operating system to set TCR_ELx.HWU*
to allow the implementation to use the PBHA bits from the
block and page descriptors for for IMPLEMENTATION DEFINED
purposes.  Since QEMU has no need to use these bits, we may
simply ignore them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu32.c        | 2 +-
 target/arm/tcg/cpu64.c        | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index XXXXXXX..XXXXXXX 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
 - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)
 - FEAT_HCX (Support for the HCRX_EL2 register)
 - FEAT_HPDS (Hierarchical permission disables)
+- FEAT_HPDS2 (Translation table page-based hardware attributes)
 - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
 - FEAT_IDST (ID space trap handling)
 - FEAT_IESB (Implicit error synchronization event)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -XXX,XX +XXX,XX @@ void aa32_max_features(ARMCPU *cpu)
     cpu->isar.id_mmfr3 = t;
 
     t = cpu->isar.id_mmfr4;
-    t = FIELD_DP32(t, ID_MMFR4, HPDS, 1);         /* FEAT_AA32HPD */
+    t = FIELD_DP32(t, ID_MMFR4, HPDS, 2);         /* FEAT_HPDS2 */
     t = FIELD_DP32(t, ID_MMFR4, AC2, 1);          /* ACTLR2, HACTLR2 */
     t = FIELD_DP32(t, ID_MMFR4, CNP, 1);          /* FEAT_TTCNP */
     t = FIELD_DP32(t, ID_MMFR4, XNX, 1);          /* FEAT_XNX */
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -XXX,XX +XXX,XX @@ void aarch64_max_tcg_initfn(Object *obj)
     t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2);   /* FEAT_HAFDBS */
     t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
     t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);       /* FEAT_VHE */
-    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1);     /* FEAT_HPDS */
+    t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 2);     /* FEAT_HPDS2 */
     t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);       /* FEAT_LOR */
     t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 3);      /* FEAT_PAN3 */
     t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1);      /* FEAT_XNX */
-- 
2.34.1

From: Alex Bennée <alex.bennee@linaro.org>

This is a mandatory feature for Armv8.1 architectures but we don't
state the feature clearly in our emulation list. Also include
FEAT_CRC32 comment in aarch64_max_tcg_initfn for ease of grepping.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20230824075406.1515566-1-alex.bennee@linaro.org
Cc: qemu-stable@nongnu.org
Message-Id: <20230222110104.3996971-1-alex.bennee@linaro.org>
[PMM: pluralize 'instructions' in docs]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/emulation.rst | 1 +
 target/arm/tcg/cpu64.c        | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

From: Jean-Christophe Dubois <jcd@tribudubois.net>

i.MX7 IOMUX GPR device is not equivalent to i.MX6UL IOMUXC GPR device.
In particular, register 22 is not present on i.MX6UL and this is actualy
The only register that is really emulated in the i.MX7 IOMUX GPR device.

Note: The i.MX6UL code is actually also implementing the IOMUX GPR device
as an unimplemented device at the same bus adress and the 2 instantiations
were actualy colliding. So we go back to the unimplemented device for now.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 48681bf51ee97646479bb261bee19abebbc8074e.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 --
 hw/arm/fsl-imx6ul.c         | 11 -----------
 2 files changed, 13 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx6ul_ccm.h"
 #include "hw/misc/imx6_src.h"
 #include "hw/misc/imx7_snvs.h"
-#include "hw/misc/imx7_gpr.h"
 #include "hw/intc/imx_gpcv2.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "hw/gpio/imx_gpio.h"
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
     IMX6SRCState       src;
     IMX7SNVSState      snvs;
     IMXGPCv2State      gpcv2;
-    IMX7GPRState       gpr;
     IMXSPIState        spi[FSL_IMX6UL_NUM_ECSPIS];
     IMXI2CState        i2c[FSL_IMX6UL_NUM_I2CS];
     IMXSerialState     uart[FSL_IMX6UL_NUM_UARTS];
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
      */
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
-    /*
-     * GPR
-     */
-    object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
-
     /*
      * GPIOs 1 to 5
      */
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_WDOGn_IRQ[i]));
     }
 
-    /*
-     * GPR
-     */
-    sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX6UL_IOMUXC_GPR_ADDR);
-
     /*
      * SDMA
      */
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add Addr and size definition for most i.MX6UL devices in i.MX6UL header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: d579043fbd4e4b490370783fda43fc02c8e9be75.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h | 156 +++++++++++++++++++++++++++++++-----
 hw/arm/fsl-imx6ul.c         | 147 ++++++++++++++++++++++-----------
 2 files changed, 232 insertions(+), 71 deletions(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/memory.h"
 #include "cpu.h"
 #include "qom/object.h"
+#include "qemu/units.h"
 
 #define TYPE_FSL_IMX6UL "fsl-imx6ul"
 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_ADCS         = 2,
     FSL_IMX6UL_NUM_USB_PHYS     = 2,
     FSL_IMX6UL_NUM_USBS         = 2,
+    FSL_IMX6UL_NUM_SAIS         = 3,
+    FSL_IMX6UL_NUM_CANS         = 2,
+    FSL_IMX6UL_NUM_PWMS         = 4,
 };
 
 struct FslIMX6ULState {
@@ -XXX,XX +XXX,XX @@ struct FslIMX6ULState {
 
 enum FslIMX6ULMemoryMap {
     FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX6UL_MMDC_SIZE            = (2 * GiB),
 
     FSL_IMX6UL_QSPI1_MEM_ADDR       = 0x60000000,
-    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
-    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
-    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
-    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * MiB),
 
-    /* AIPS-2 */
+    FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
+    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * MiB),
+
+    FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
+    FSL_IMX6UL_EIM_CS_SIZE          = (128 * MiB),
+
+    FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
+    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1 * MiB),
+
+    FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * MiB),
+
+    /* AIPS-2 Begin */
     FSL_IMX6UL_UART6_ADDR           = 0x021FC000,
+
     FSL_IMX6UL_I2C4_ADDR            = 0x021F8000,
+
     FSL_IMX6UL_UART5_ADDR           = 0x021F4000,
     FSL_IMX6UL_UART4_ADDR           = 0x021F0000,
     FSL_IMX6UL_UART3_ADDR           = 0x021EC000,
     FSL_IMX6UL_UART2_ADDR           = 0x021E8000,
+
     FSL_IMX6UL_WDOG3_ADDR           = 0x021E4000,
+
     FSL_IMX6UL_QSPI_ADDR            = 0x021E0000,
+    FSL_IMX6UL_QSPI_SIZE            = 0x500,
+
     FSL_IMX6UL_SYS_CNT_CTRL_ADDR    = 0x021DC000,
+    FSL_IMX6UL_SYS_CNT_CTRL_SIZE    = (16 * KiB),
+
     FSL_IMX6UL_SYS_CNT_CMP_ADDR     = 0x021D8000,
+    FSL_IMX6UL_SYS_CNT_CMP_SIZE     = (16 * KiB),
+
     FSL_IMX6UL_SYS_CNT_RD_ADDR      = 0x021D4000,
+    FSL_IMX6UL_SYS_CNT_RD_SIZE      = (16 * KiB),
+
     FSL_IMX6UL_TZASC_ADDR           = 0x021D0000,
+    FSL_IMX6UL_TZASC_SIZE           = (16 * KiB),
+
     FSL_IMX6UL_PXP_ADDR             = 0x021CC000,
+    FSL_IMX6UL_PXP_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_LCDIF_ADDR           = 0x021C8000,
+    FSL_IMX6UL_LCDIF_SIZE           = 0x100,
+
     FSL_IMX6UL_CSI_ADDR             = 0x021C4000,
+    FSL_IMX6UL_CSI_SIZE             = 0x100,
+
     FSL_IMX6UL_CSU_ADDR             = 0x021C0000,
+    FSL_IMX6UL_CSU_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_OCOTP_CTRL_ADDR      = 0x021BC000,
+    FSL_IMX6UL_OCOTP_CTRL_SIZE      = (4 * KiB),
+
     FSL_IMX6UL_EIM_ADDR             = 0x021B8000,
+    FSL_IMX6UL_EIM_SIZE             = 0x100,
+
     FSL_IMX6UL_SIM2_ADDR            = 0x021B4000,
+
     FSL_IMX6UL_MMDC_CFG_ADDR        = 0x021B0000,
+    FSL_IMX6UL_MMDC_CFG_SIZE        = (4 * KiB),
+
     FSL_IMX6UL_ROMCP_ADDR           = 0x021AC000,
+    FSL_IMX6UL_ROMCP_SIZE           = 0x300,
+
     FSL_IMX6UL_I2C3_ADDR            = 0x021A8000,
     FSL_IMX6UL_I2C2_ADDR            = 0x021A4000,
     FSL_IMX6UL_I2C1_ADDR            = 0x021A0000,
+
     FSL_IMX6UL_ADC2_ADDR            = 0x0219C000,
     FSL_IMX6UL_ADC1_ADDR            = 0x02198000,
+    FSL_IMX6UL_ADCn_SIZE            = 0x100,
+
     FSL_IMX6UL_USDHC2_ADDR          = 0x02194000,
     FSL_IMX6UL_USDHC1_ADDR          = 0x02190000,
-    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
-    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
-    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
-    FSL_IMX6UL_USBO2_USB_ADDR       = 0x02184000,
-    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
-    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
-    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
-    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
 
-    /* AIPS-1 */
+    FSL_IMX6UL_SIM1_ADDR            = 0x0218C000,
+    FSL_IMX6UL_SIMn_SIZE            = (16 * KiB),
+
+    FSL_IMX6UL_ENET1_ADDR           = 0x02188000,
+
+    FSL_IMX6UL_USBO2_USBMISC_ADDR   = 0x02184800,
+    FSL_IMX6UL_USBO2_USB1_ADDR      = 0x02184000,
+    FSL_IMX6UL_USBO2_USB2_ADDR      = 0x02184200,
+
+    FSL_IMX6UL_USBO2_PL301_ADDR     = 0x02180000,
+    FSL_IMX6UL_USBO2_PL301_SIZE     = (16 * KiB),
+
+    FSL_IMX6UL_AIPS2_CFG_ADDR       = 0x0217C000,
+    FSL_IMX6UL_AIPS2_CFG_SIZE       = 0x100,
+
+    FSL_IMX6UL_CAAM_ADDR            = 0x02140000,
+    FSL_IMX6UL_CAAM_SIZE            = (16 * KiB),
+
+    FSL_IMX6UL_A7MPCORE_DAP_ADDR    = 0x02100000,
+    FSL_IMX6UL_A7MPCORE_DAP_SIZE    = (4 * KiB),
+    /* AIPS-2 End */
+
+    /* AIPS-1 Begin */
     FSL_IMX6UL_PWM8_ADDR            = 0x020FC000,
     FSL_IMX6UL_PWM7_ADDR            = 0x020F8000,
     FSL_IMX6UL_PWM6_ADDR            = 0x020F4000,
     FSL_IMX6UL_PWM5_ADDR            = 0x020F0000,
+
     FSL_IMX6UL_SDMA_ADDR            = 0x020EC000,
+    FSL_IMX6UL_SDMA_SIZE            = 0x300,
+
     FSL_IMX6UL_GPT2_ADDR            = 0x020E8000,
+
     FSL_IMX6UL_IOMUXC_GPR_ADDR      = 0x020E4000,
+    FSL_IMX6UL_IOMUXC_GPR_SIZE      = 0x40,
+
     FSL_IMX6UL_IOMUXC_ADDR          = 0x020E0000,
+    FSL_IMX6UL_IOMUXC_SIZE          = 0x700,
+
     FSL_IMX6UL_GPC_ADDR             = 0x020DC000,
+
     FSL_IMX6UL_SRC_ADDR             = 0x020D8000,
+
     FSL_IMX6UL_EPIT2_ADDR           = 0x020D4000,
     FSL_IMX6UL_EPIT1_ADDR           = 0x020D0000,
+
     FSL_IMX6UL_SNVS_HP_ADDR         = 0x020CC000,
+
     FSL_IMX6UL_USBPHY2_ADDR         = 0x020CA000,
-    FSL_IMX6UL_USBPHY2_SIZE         = (4 * 1024),
     FSL_IMX6UL_USBPHY1_ADDR         = 0x020C9000,
-    FSL_IMX6UL_USBPHY1_SIZE         = (4 * 1024),
+
     FSL_IMX6UL_ANALOG_ADDR          = 0x020C8000,
+    FSL_IMX6UL_ANALOG_SIZE          = 0x300,
+
     FSL_IMX6UL_CCM_ADDR             = 0x020C4000,
+
     FSL_IMX6UL_WDOG2_ADDR           = 0x020C0000,
     FSL_IMX6UL_WDOG1_ADDR           = 0x020BC000,
+
     FSL_IMX6UL_KPP_ADDR             = 0x020B8000,
+    FSL_IMX6UL_KPP_SIZE             = 0x10,
+
     FSL_IMX6UL_ENET2_ADDR           = 0x020B4000,
+
     FSL_IMX6UL_SNVS_LP_ADDR         = 0x020B0000,
+    FSL_IMX6UL_SNVS_LP_SIZE         = (16 * KiB),
+
     FSL_IMX6UL_GPIO5_ADDR           = 0x020AC000,
     FSL_IMX6UL_GPIO4_ADDR           = 0x020A8000,
     FSL_IMX6UL_GPIO3_ADDR           = 0x020A4000,
     FSL_IMX6UL_GPIO2_ADDR           = 0x020A0000,
     FSL_IMX6UL_GPIO1_ADDR           = 0x0209C000,
+
     FSL_IMX6UL_GPT1_ADDR            = 0x02098000,
+
     FSL_IMX6UL_CAN2_ADDR            = 0x02094000,
     FSL_IMX6UL_CAN1_ADDR            = 0x02090000,
+    FSL_IMX6UL_CANn_SIZE            = (4 * KiB),
+
     FSL_IMX6UL_PWM4_ADDR            = 0x0208C000,
     FSL_IMX6UL_PWM3_ADDR            = 0x02088000,
     FSL_IMX6UL_PWM2_ADDR            = 0x02084000,
     FSL_IMX6UL_PWM1_ADDR            = 0x02080000,
+    FSL_IMX6UL_PWMn_SIZE            = 0x20,
+
     FSL_IMX6UL_AIPS1_CFG_ADDR       = 0x0207C000,
+    FSL_IMX6UL_AIPS1_CFG_SIZE       = (16 * KiB),
+
     FSL_IMX6UL_BEE_ADDR             = 0x02044000,
+    FSL_IMX6UL_BEE_SIZE             = (16 * KiB),
+
     FSL_IMX6UL_TOUCH_CTRL_ADDR      = 0x02040000,
+    FSL_IMX6UL_TOUCH_CTRL_SIZE      = 0x100,
+
     FSL_IMX6UL_SPBA_ADDR            = 0x0203C000,
+    FSL_IMX6UL_SPBA_SIZE            = 0x100,
+
     FSL_IMX6UL_ASRC_ADDR            = 0x02034000,
+    FSL_IMX6UL_ASRC_SIZE            = 0x100,
+
     FSL_IMX6UL_SAI3_ADDR            = 0x02030000,
     FSL_IMX6UL_SAI2_ADDR            = 0x0202C000,
     FSL_IMX6UL_SAI1_ADDR            = 0x02028000,
+    FSL_IMX6UL_SAIn_SIZE            = 0x200,
+
     FSL_IMX6UL_UART8_ADDR           = 0x02024000,
     FSL_IMX6UL_UART1_ADDR           = 0x02020000,
     FSL_IMX6UL_UART7_ADDR           = 0x02018000,
+
     FSL_IMX6UL_ECSPI4_ADDR          = 0x02014000,
     FSL_IMX6UL_ECSPI3_ADDR          = 0x02010000,
     FSL_IMX6UL_ECSPI2_ADDR          = 0x0200C000,
     FSL_IMX6UL_ECSPI1_ADDR          = 0x02008000,
+
     FSL_IMX6UL_SPDIF_ADDR           = 0x02004000,
+    FSL_IMX6UL_SPDIF_SIZE           = 0x100,
+    /* AIPS-1 End */
+
+    FSL_IMX6UL_BCH_ADDR             = 0x01808000,
+    FSL_IMX6UL_BCH_SIZE             = 0x200,
+
+    FSL_IMX6UL_GPMI_ADDR            = 0x01806000,
+    FSL_IMX6UL_GPMI_SIZE            = 0x200,
 
     FSL_IMX6UL_APBH_DMA_ADDR        = 0x01804000,
-    FSL_IMX6UL_APBH_DMA_SIZE        = (32 * 1024),
+    FSL_IMX6UL_APBH_DMA_SIZE        = (4 * KiB),
 
     FSL_IMX6UL_A7MPCORE_ADDR        = 0x00A00000,
 
     FSL_IMX6UL_OCRAM_ALIAS_ADDR     = 0x00920000,
-    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = 0x00060000,
+    FSL_IMX6UL_OCRAM_ALIAS_SIZE     = (384 * KiB),
+
     FSL_IMX6UL_OCRAM_MEM_ADDR       = 0x00900000,
-    FSL_IMX6UL_OCRAM_MEM_SIZE       = 0x00020000,
+    FSL_IMX6UL_OCRAM_MEM_SIZE       = (128 * KiB),
+
     FSL_IMX6UL_CAAM_MEM_ADDR        = 0x00100000,
-    FSL_IMX6UL_CAAM_MEM_SIZE        = 0x00008000,
+    FSL_IMX6UL_CAAM_MEM_SIZE        = (32 * KiB),
+
     FSL_IMX6UL_ROM_ADDR             = 0x00000000,
-    FSL_IMX6UL_ROM_SIZE             = 0x00018000,
+    FSL_IMX6UL_ROM_SIZE             = (96 * KiB),
 };
 
 enum FslIMX6ULIRQs {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
     /*
-     * GPIOs 1 to 5
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * GPT 1, 2
+     * GPTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * EPIT 1, 2
+     * EPITs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
         snprintf(name, NAME_SIZE, "epit%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * eCSPI
+     * eCSPIs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * I2C
+     * I2Cs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
         snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      */
     for (i = 0; i < FSL_IMX6UL_NUM_ETHS; i++) {
         snprintf(name, NAME_SIZE, "eth%d", i);
         object_initialize_child(obj, name, &s->eth[i], TYPE_IMX_ENET);
     }
 
-    /* USB */
+    /*
+     * USB PHYs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
         snprintf(name, NAME_SIZE, "usbphy%d", i);
         object_initialize_child(obj, name, &s->usbphy[i], TYPE_IMX_USBPHY);
     }
+
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
         snprintf(name, NAME_SIZE, "usb%d", i);
         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
     }
 
     /*
-     * SDHCI
+     * SDHCIs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
         snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_init(Object *obj)
     }
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
         snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
      * A7MPCORE DAP
      */
     create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
-                                0x100000);
+                                FSL_IMX6UL_A7MPCORE_DAP_SIZE);
 
     /*
-     * GPT 1, 2
+     * GPTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPTS; i++) {
         static const hwaddr FSL_IMX6UL_GPTn_ADDR[FSL_IMX6UL_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * EPIT 1, 2
+     * EPITs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_EPITS; i++) {
         static const hwaddr FSL_IMX6UL_EPITn_ADDR[FSL_IMX6UL_NUM_EPITS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * GPIO
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_GPIOS; i++) {
         static const hwaddr FSL_IMX6UL_GPIOn_ADDR[FSL_IMX6UL_NUM_GPIOS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * IOMUXC and IOMUXC_GPR
+     * IOMUXC
      */
-    for (i = 0; i < 1; i++) {
-        static const hwaddr FSL_IMX6UL_IOMUXCn_ADDR[FSL_IMX6UL_NUM_IOMUXCS] = {
-            FSL_IMX6UL_IOMUXC_ADDR,
-            FSL_IMX6UL_IOMUXC_GPR_ADDR,
-        };
-
-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
-        create_unimplemented_device(name, FSL_IMX6UL_IOMUXCn_ADDR[i], 0x4000);
-    }
+    create_unimplemented_device("iomuxc", FSL_IMX6UL_IOMUXC_ADDR,
+                                FSL_IMX6UL_IOMUXC_SIZE);
+    create_unimplemented_device("iomuxc_gpr", FSL_IMX6UL_IOMUXC_GPR_ADDR,
+                                FSL_IMX6UL_IOMUXC_GPR_SIZE);
 
     /*
      * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX6UL_GPC_ADDR);
 
-    /* Initialize all ECSPI */
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_ECSPIS; i++) {
         static const hwaddr FSL_IMX6UL_SPIn_ADDR[FSL_IMX6UL_NUM_ECSPIS] = {
             FSL_IMX6UL_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * I2C
+     * I2Cs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_I2CS; i++) {
         static const hwaddr FSL_IMX6UL_I2Cn_ADDR[FSL_IMX6UL_NUM_I2CS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_UARTS; i++) {
         static const hwaddr FSL_IMX6UL_UARTn_ADDR[FSL_IMX6UL_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      *
      * We must use two loops since phy_connected affects the other interface
      * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
     }
 
-    /* USB */
+    /*
+     * USB PHYs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USB_PHYS; i++) {
+        static const hwaddr
+                     FSL_IMX6UL_USB_PHYn_ADDR[FSL_IMX6UL_NUM_USB_PHYS] = {
+            FSL_IMX6UL_USBPHY1_ADDR,
+            FSL_IMX6UL_USBPHY2_ADDR,
+        };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->usbphy[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usbphy[i]), 0,
-                        FSL_IMX6UL_USBPHY1_ADDR + i * 0x1000);
+                        FSL_IMX6UL_USB_PHYn_ADDR[i]);
     }
 
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX6UL_NUM_USBS; i++) {
+        static const hwaddr FSL_IMX6UL_USB02_USBn_ADDR[FSL_IMX6UL_NUM_USBS] = {
+            FSL_IMX6UL_USBO2_USB1_ADDR,
+            FSL_IMX6UL_USBO2_USB2_ADDR,
+        };
+
         static const int FSL_IMX6UL_USBn_IRQ[] = {
             FSL_IMX6UL_USB1_IRQ,
             FSL_IMX6UL_USB2_IRQ,
         };
+
         sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), &error_abort);
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
-                        FSL_IMX6UL_USBO2_USB_ADDR + i * 0x200);
+                        FSL_IMX6UL_USB02_USBn_ADDR[i]);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
                                             FSL_IMX6UL_USBn_IRQ[i]));
     }
 
     /*
-     * USDHC
+     * USDHCs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) {
         static const hwaddr FSL_IMX6UL_USDHCn_ADDR[FSL_IMX6UL_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX6UL_SNVS_HP_ADDR);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX6UL_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX6UL_WDOGn_ADDR[FSL_IMX6UL_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_WDOG2_ADDR,
             FSL_IMX6UL_WDOG3_ADDR,
         };
+
         static const int FSL_IMX6UL_WDOGn_IRQ[FSL_IMX6UL_NUM_WDTS] = {
             FSL_IMX6UL_WDOG1_IRQ,
             FSL_IMX6UL_WDOG2_IRQ,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     /*
      * SDMA
      */
-    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR, 0x4000);
+    create_unimplemented_device("sdma", FSL_IMX6UL_SDMA_ADDR,
+                                FSL_IMX6UL_SDMA_SIZE);
 
     /*
-     * SAI (Audio SSI (Synchronous Serial Interface))
+     * SAIs (Audio SSI (Synchronous Serial Interface))
      */
-    create_unimplemented_device("sai1", FSL_IMX6UL_SAI1_ADDR, 0x4000);
-    create_unimplemented_device("sai2", FSL_IMX6UL_SAI2_ADDR, 0x4000);
-    create_unimplemented_device("sai3", FSL_IMX6UL_SAI3_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_SAIS; i++) {
+        static const hwaddr FSL_IMX6UL_SAIn_ADDR[FSL_IMX6UL_NUM_SAIS] = {
+            FSL_IMX6UL_SAI1_ADDR,
+            FSL_IMX6UL_SAI2_ADDR,
+            FSL_IMX6UL_SAI3_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "sai%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_SAIn_ADDR[i],
+                                    FSL_IMX6UL_SAIn_SIZE);
+    }
 
     /*
-     * PWM
+     * PWMs
      */
-    create_unimplemented_device("pwm1", FSL_IMX6UL_PWM1_ADDR, 0x4000);
-    create_unimplemented_device("pwm2", FSL_IMX6UL_PWM2_ADDR, 0x4000);
-    create_unimplemented_device("pwm3", FSL_IMX6UL_PWM3_ADDR, 0x4000);
-    create_unimplemented_device("pwm4", FSL_IMX6UL_PWM4_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_PWMS; i++) {
+        static const hwaddr FSL_IMX6UL_PWMn_ADDR[FSL_IMX6UL_NUM_PWMS] = {
+            FSL_IMX6UL_PWM1_ADDR,
+            FSL_IMX6UL_PWM2_ADDR,
+            FSL_IMX6UL_PWM3_ADDR,
+            FSL_IMX6UL_PWM4_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "pwm%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_PWMn_ADDR[i],
+                                    FSL_IMX6UL_PWMn_SIZE);
+    }
 
     /*
      * Audio ASRC (asynchronous sample rate converter)
      */
-    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR, 0x4000);
+    create_unimplemented_device("asrc", FSL_IMX6UL_ASRC_ADDR,
+                                FSL_IMX6UL_ASRC_SIZE);
 
     /*
-     * CAN
+     * CANs
      */
-    create_unimplemented_device("can1", FSL_IMX6UL_CAN1_ADDR, 0x4000);
-    create_unimplemented_device("can2", FSL_IMX6UL_CAN2_ADDR, 0x4000);
+    for (i = 0; i < FSL_IMX6UL_NUM_CANS; i++) {
+        static const hwaddr FSL_IMX6UL_CANn_ADDR[FSL_IMX6UL_NUM_CANS] = {
+            FSL_IMX6UL_CAN1_ADDR,
+            FSL_IMX6UL_CAN2_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "can%d", i);
+        create_unimplemented_device(name, FSL_IMX6UL_CANn_ADDR[i],
+                                    FSL_IMX6UL_CANn_SIZE);
+    }
 
     /*
      * APHB_DMA
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
         };
 
         snprintf(name, NAME_SIZE, "adc%d", i);
-        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i], 0x4000);
+        create_unimplemented_device(name, FSL_IMX6UL_ADCn_ADDR[i],
+                                    FSL_IMX6UL_ADCn_SIZE);
     }
 
     /*
      * LCD
      */
-    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR, 0x4000);
+    create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
+                                FSL_IMX6UL_LCDIF_SIZE);
 
     /*
      * ROM memory
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add TZASC as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add CSU as unimplemented device.
  - Allow bare metal application to access this (unimplemented) device
* Add 4 missing PWM devices

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 59e4dc56e14eccfefd379275ec19048dff9c10b3.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx6ul.h |  2 +-
 hw/arm/fsl-imx6ul.c         | 16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@ enum FslIMX6ULConfiguration {
     FSL_IMX6UL_NUM_USBS         = 2,
     FSL_IMX6UL_NUM_SAIS         = 3,
     FSL_IMX6UL_NUM_CANS         = 2,
-    FSL_IMX6UL_NUM_PWMS         = 4,
+    FSL_IMX6UL_NUM_PWMS         = 8,
 };
 
 struct FslIMX6ULState {
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
             FSL_IMX6UL_PWM2_ADDR,
             FSL_IMX6UL_PWM3_ADDR,
             FSL_IMX6UL_PWM4_ADDR,
+            FSL_IMX6UL_PWM5_ADDR,
+            FSL_IMX6UL_PWM6_ADDR,
+            FSL_IMX6UL_PWM7_ADDR,
+            FSL_IMX6UL_PWM8_ADDR,
         };
 
         snprintf(name, NAME_SIZE, "pwm%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("lcdif", FSL_IMX6UL_LCDIF_ADDR,
                                 FSL_IMX6UL_LCDIF_SIZE);
 
+    /*
+     * CSU
+     */
+    create_unimplemented_device("csu", FSL_IMX6UL_CSU_ADDR,
+                                FSL_IMX6UL_CSU_SIZE);
+
+    /*
+     * TZASC
+     */
+    create_unimplemented_device("tzasc", FSL_IMX6UL_TZASC_ADDR,
+                                FSL_IMX6UL_TZASC_SIZE);
+
     /*
      * ROM memory
      */
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

* Add Addr and size definition for all i.MX7 devices in i.MX7 header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
  - SAI
  - PWM
  - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 59e195d33e4d486a8d131392acd46633c8c10ed7.1692964892.git.jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h | 330 ++++++++++++++++++++++++++++----------
 hw/arm/fsl-imx7.c         | 130 ++++++++++-----
 2 files changed, 335 insertions(+), 125 deletions(-)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/imx7_ccm.h"
 #include "hw/misc/imx7_snvs.h"
 #include "hw/misc/imx7_gpr.h"
-#include "hw/misc/imx6_src.h"
 #include "hw/watchdog/wdt_imx2.h"
 #include "hw/gpio/imx_gpio.h"
 #include "hw/char/imx_serial.h"
@@ -XXX,XX +XXX,XX @@
 #include "hw/usb/chipidea.h"
 #include "cpu.h"
 #include "qom/object.h"
+#include "qemu/units.h"
 
 #define TYPE_FSL_IMX7 "fsl-imx7"
 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX7State, FSL_IMX7)
@@ -XXX,XX +XXX,XX @@ enum FslIMX7Configuration {
     FSL_IMX7_NUM_ECSPIS       = 4,
     FSL_IMX7_NUM_USBS         = 3,
     FSL_IMX7_NUM_ADCS         = 2,
+    FSL_IMX7_NUM_SAIS         = 3,
+    FSL_IMX7_NUM_CANS         = 2,
+    FSL_IMX7_NUM_PWMS         = 4,
 };
 
 struct FslIMX7State {
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
 
 enum FslIMX7MemoryMap {
     FSL_IMX7_MMDC_ADDR            = 0x80000000,
-    FSL_IMX7_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX7_MMDC_SIZE            = (2 * GiB),
 
-    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
-    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
-    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
-    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
-    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
-    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
-    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
+    FSL_IMX7_QSPI1_MEM_ADDR       = 0x60000000,
+    FSL_IMX7_QSPI1_MEM_SIZE       = (256 * MiB),
 
-    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+    FSL_IMX7_PCIE1_MEM_ADDR       = 0x40000000,
+    FSL_IMX7_PCIE1_MEM_SIZE       = (256 * MiB),
 
-    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
-    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
-    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
-    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
+    FSL_IMX7_QSPI1_RX_BUF_ADDR    = 0x34000000,
+    FSL_IMX7_QSPI1_RX_BUF_SIZE    = (32 * MiB),
 
-    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
+    /* PCIe Peripherals */
+    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
 
-    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
-    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
-    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
-    FSL_IMX7_GPT4_ADDR            = 0x30300000,
+    /* MMAP Peripherals */
+    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
+    FSL_IMX7_DMA_APBH_SIZE        = 0x8000,
 
-    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
-    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
-    FSL_IMX7_IOMUXCn_SIZE         = 0x1000,
+    /* GPV configuration */
+    FSL_IMX7_GPV6_ADDR            = 0x32600000,
+    FSL_IMX7_GPV5_ADDR            = 0x32500000,
+    FSL_IMX7_GPV4_ADDR            = 0x32400000,
+    FSL_IMX7_GPV3_ADDR            = 0x32300000,
+    FSL_IMX7_GPV2_ADDR            = 0x32200000,
+    FSL_IMX7_GPV1_ADDR            = 0x32100000,
+    FSL_IMX7_GPV0_ADDR            = 0x32000000,
+    FSL_IMX7_GPVn_SIZE            = (1 * MiB),
 
-    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
-    FSL_IMX7_OCOTP_SIZE           = 0x10000,
+    /* Arm Peripherals */
+    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
 
-    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
-    FSL_IMX7_SNVS_ADDR            = 0x30370000,
-    FSL_IMX7_CCM_ADDR             = 0x30380000,
+    /* AIPS-3 Begin */
 
-    FSL_IMX7_SRC_ADDR             = 0x30390000,
-    FSL_IMX7_SRC_SIZE             = 0x1000,
+    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
+    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
 
-    FSL_IMX7_ADC1_ADDR            = 0x30610000,
-    FSL_IMX7_ADC2_ADDR            = 0x30620000,
-    FSL_IMX7_ADCn_SIZE            = 0x1000,
+    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
+    FSL_IMX7_SDMA_SIZE            = (4 * KiB),
 
-    FSL_IMX7_PWM1_ADDR            = 0x30660000,
-    FSL_IMX7_PWM2_ADDR            = 0x30670000,
-    FSL_IMX7_PWM3_ADDR            = 0x30680000,
-    FSL_IMX7_PWM4_ADDR            = 0x30690000,
-    FSL_IMX7_PWMn_SIZE            = 0x10000,
+    FSL_IMX7_EIM_ADDR             = 0x30BC0000,
+    FSL_IMX7_EIM_SIZE             = (4 * KiB),
 
-    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
-    FSL_IMX7_PCIE_PHY_SIZE        = 0x10000,
+    FSL_IMX7_QSPI_ADDR            = 0x30BB0000,
+    FSL_IMX7_QSPI_SIZE            = 0x8000,
 
-    FSL_IMX7_GPC_ADDR             = 0x303A0000,
+    FSL_IMX7_SIM2_ADDR            = 0x30BA0000,
+    FSL_IMX7_SIM1_ADDR            = 0x30B90000,
+    FSL_IMX7_SIMn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
+    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
+    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
+
+    FSL_IMX7_USB3_ADDR            = 0x30B30000,
+    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
+    FSL_IMX7_USB2_ADDR            = 0x30B20000,
+    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
+    FSL_IMX7_USB1_ADDR            = 0x30B10000,
+    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
+    FSL_IMX7_USBMISCn_SIZE        = 0x200,
+
+    FSL_IMX7_USB_PL301_ADDR       = 0x30AD0000,
+    FSL_IMX7_USB_PL301_SIZE       = (64 * KiB),
+
+    FSL_IMX7_SEMAPHORE_HS_ADDR    = 0x30AC0000,
+    FSL_IMX7_SEMAPHORE_HS_SIZE    = (64 * KiB),
+
+    FSL_IMX7_MUB_ADDR             = 0x30AB0000,
+    FSL_IMX7_MUA_ADDR             = 0x30AA0000,
+    FSL_IMX7_MUn_SIZE             = (KiB),
+
+    FSL_IMX7_UART7_ADDR           = 0x30A90000,
+    FSL_IMX7_UART6_ADDR           = 0x30A80000,
+    FSL_IMX7_UART5_ADDR           = 0x30A70000,
+    FSL_IMX7_UART4_ADDR           = 0x30A60000,
+
+    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
+    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
+    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
+    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
+
+    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
+    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
+    FSL_IMX7_CANn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_AIPS3_CONF_ADDR      = 0x309F0000,
+    FSL_IMX7_AIPS3_CONF_SIZE      = (64 * KiB),
 
     FSL_IMX7_CAAM_ADDR            = 0x30900000,
-    FSL_IMX7_CAAM_SIZE            = 0x40000,
+    FSL_IMX7_CAAM_SIZE            = (256 * KiB),
 
-    FSL_IMX7_CAN1_ADDR            = 0x30A00000,
-    FSL_IMX7_CAN2_ADDR            = 0x30A10000,
-    FSL_IMX7_CANn_SIZE            = 0x10000,
+    FSL_IMX7_SPBA_ADDR            = 0x308F0000,
+    FSL_IMX7_SPBA_SIZE            = (4 * KiB),
 
-    FSL_IMX7_I2C1_ADDR            = 0x30A20000,
-    FSL_IMX7_I2C2_ADDR            = 0x30A30000,
-    FSL_IMX7_I2C3_ADDR            = 0x30A40000,
-    FSL_IMX7_I2C4_ADDR            = 0x30A50000,
+    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
+    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
+    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
+    FSL_IMX7_SAIn_SIZE            = (4 * KiB),
 
-    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
-    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
-    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
-    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
-
-    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
-    FSL_IMX7_LCDIF_SIZE           = 0x1000,
-
-    FSL_IMX7_UART1_ADDR           = 0x30860000,
+    FSL_IMX7_UART3_ADDR           = 0x30880000,
     /*
      * Some versions of the reference manual claim that UART2 is @
      * 0x30870000, but experiments with HW + DT files in upstream
@@ -XXX,XX +XXX,XX @@ enum FslIMX7MemoryMap {
      * actually located @ 0x30890000
      */
     FSL_IMX7_UART2_ADDR           = 0x30890000,
-    FSL_IMX7_UART3_ADDR           = 0x30880000,
-    FSL_IMX7_UART4_ADDR           = 0x30A60000,
-    FSL_IMX7_UART5_ADDR           = 0x30A70000,
-    FSL_IMX7_UART6_ADDR           = 0x30A80000,
-    FSL_IMX7_UART7_ADDR           = 0x30A90000,
+    FSL_IMX7_UART1_ADDR           = 0x30860000,
 
-    FSL_IMX7_SAI1_ADDR            = 0x308A0000,
-    FSL_IMX7_SAI2_ADDR            = 0x308B0000,
-    FSL_IMX7_SAI3_ADDR            = 0x308C0000,
-    FSL_IMX7_SAIn_SIZE            = 0x10000,
+    FSL_IMX7_ECSPI3_ADDR          = 0x30840000,
+    FSL_IMX7_ECSPI2_ADDR          = 0x30830000,
+    FSL_IMX7_ECSPI1_ADDR          = 0x30820000,
+    FSL_IMX7_ECSPIn_SIZE          = (4 * KiB),
 
-    FSL_IMX7_ENET1_ADDR           = 0x30BE0000,
-    FSL_IMX7_ENET2_ADDR           = 0x30BF0000,
+    /* AIPS-3 End */
 
-    FSL_IMX7_USB1_ADDR            = 0x30B10000,
-    FSL_IMX7_USBMISC1_ADDR        = 0x30B10200,
-    FSL_IMX7_USB2_ADDR            = 0x30B20000,
-    FSL_IMX7_USBMISC2_ADDR        = 0x30B20200,
-    FSL_IMX7_USB3_ADDR            = 0x30B30000,
-    FSL_IMX7_USBMISC3_ADDR        = 0x30B30200,
-    FSL_IMX7_USBMISCn_SIZE        = 0x200,
+    /* AIPS-2 Begin */
 
-    FSL_IMX7_USDHC1_ADDR          = 0x30B40000,
-    FSL_IMX7_USDHC2_ADDR          = 0x30B50000,
-    FSL_IMX7_USDHC3_ADDR          = 0x30B60000,
+    FSL_IMX7_AXI_DEBUG_MON_ADDR   = 0x307E0000,
+    FSL_IMX7_AXI_DEBUG_MON_SIZE   = (64 * KiB),
 
-    FSL_IMX7_SDMA_ADDR            = 0x30BD0000,
-    FSL_IMX7_SDMA_SIZE            = 0x1000,
+    FSL_IMX7_PERFMON2_ADDR        = 0x307D0000,
+    FSL_IMX7_PERFMON1_ADDR        = 0x307C0000,
+    FSL_IMX7_PERFMONn_SIZE        = (64 * KiB),
+
+    FSL_IMX7_DDRC_ADDR            = 0x307A0000,
+    FSL_IMX7_DDRC_SIZE            = (4 * KiB),
+
+    FSL_IMX7_DDRC_PHY_ADDR        = 0x30790000,
+    FSL_IMX7_DDRC_PHY_SIZE        = (4 * KiB),
+
+    FSL_IMX7_TZASC_ADDR           = 0x30780000,
+    FSL_IMX7_TZASC_SIZE           = (64 * KiB),
+
+    FSL_IMX7_MIPI_DSI_ADDR        = 0x30760000,
+    FSL_IMX7_MIPI_DSI_SIZE        = (4 * KiB),
+
+    FSL_IMX7_MIPI_CSI_ADDR        = 0x30750000,
+    FSL_IMX7_MIPI_CSI_SIZE        = 0x4000,
+
+    FSL_IMX7_LCDIF_ADDR           = 0x30730000,
+    FSL_IMX7_LCDIF_SIZE           = 0x8000,
+
+    FSL_IMX7_CSI_ADDR             = 0x30710000,
+    FSL_IMX7_CSI_SIZE             = (4 * KiB),
+
+    FSL_IMX7_PXP_ADDR             = 0x30700000,
+    FSL_IMX7_PXP_SIZE             = 0x4000,
+
+    FSL_IMX7_EPDC_ADDR            = 0x306F0000,
+    FSL_IMX7_EPDC_SIZE            = (4 * KiB),
+
+    FSL_IMX7_PCIE_PHY_ADDR        = 0x306D0000,
+    FSL_IMX7_PCIE_PHY_SIZE        = (4 * KiB),
+
+    FSL_IMX7_SYSCNT_CTRL_ADDR     = 0x306C0000,
+    FSL_IMX7_SYSCNT_CMP_ADDR      = 0x306B0000,
+    FSL_IMX7_SYSCNT_RD_ADDR       = 0x306A0000,
+
+    FSL_IMX7_PWM4_ADDR            = 0x30690000,
+    FSL_IMX7_PWM3_ADDR            = 0x30680000,
+    FSL_IMX7_PWM2_ADDR            = 0x30670000,
+    FSL_IMX7_PWM1_ADDR            = 0x30660000,
+    FSL_IMX7_PWMn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_FlEXTIMER2_ADDR      = 0x30650000,
+    FSL_IMX7_FlEXTIMER1_ADDR      = 0x30640000,
+    FSL_IMX7_FLEXTIMERn_SIZE      = (4 * KiB),
+
+    FSL_IMX7_ECSPI4_ADDR          = 0x30630000,
+
+    FSL_IMX7_ADC2_ADDR            = 0x30620000,
+    FSL_IMX7_ADC1_ADDR            = 0x30610000,
+    FSL_IMX7_ADCn_SIZE            = (4 * KiB),
+
+    FSL_IMX7_AIPS2_CONF_ADDR      = 0x305F0000,
+    FSL_IMX7_AIPS2_CONF_SIZE      = (64 * KiB),
+
+    /* AIPS-2 End */
+
+    /* AIPS-1 Begin */
+
+    FSL_IMX7_CSU_ADDR             = 0x303E0000,
+    FSL_IMX7_CSU_SIZE             = (64 * KiB),
+
+    FSL_IMX7_RDC_ADDR             = 0x303D0000,
+    FSL_IMX7_RDC_SIZE             = (4 * KiB),
+
+    FSL_IMX7_SEMAPHORE2_ADDR      = 0x303C0000,
+    FSL_IMX7_SEMAPHORE1_ADDR      = 0x303B0000,
+    FSL_IMX7_SEMAPHOREn_SIZE      = (4 * KiB),
+
+    FSL_IMX7_GPC_ADDR             = 0x303A0000,
+
+    FSL_IMX7_SRC_ADDR             = 0x30390000,
+    FSL_IMX7_SRC_SIZE             = (4 * KiB),
+
+    FSL_IMX7_CCM_ADDR             = 0x30380000,
+
+    FSL_IMX7_SNVS_HP_ADDR         = 0x30370000,
+
+    FSL_IMX7_ANALOG_ADDR          = 0x30360000,
+
+    FSL_IMX7_OCOTP_ADDR           = 0x30350000,
+    FSL_IMX7_OCOTP_SIZE           = 0x10000,
+
+    FSL_IMX7_IOMUXC_GPR_ADDR      = 0x30340000,
+    FSL_IMX7_IOMUXC_GPR_SIZE      = (4 * KiB),
+
+    FSL_IMX7_IOMUXC_ADDR          = 0x30330000,
+    FSL_IMX7_IOMUXC_SIZE          = (4 * KiB),
+
+    FSL_IMX7_KPP_ADDR             = 0x30320000,
+    FSL_IMX7_KPP_SIZE             = (4 * KiB),
+
+    FSL_IMX7_ROMCP_ADDR           = 0x30310000,
+    FSL_IMX7_ROMCP_SIZE           = (4 * KiB),
+
+    FSL_IMX7_GPT4_ADDR            = 0x30300000,
+    FSL_IMX7_GPT3_ADDR            = 0x302F0000,
+    FSL_IMX7_GPT2_ADDR            = 0x302E0000,
+    FSL_IMX7_GPT1_ADDR            = 0x302D0000,
+
+    FSL_IMX7_IOMUXC_LPSR_ADDR     = 0x302C0000,
+    FSL_IMX7_IOMUXC_LPSR_SIZE     = (4 * KiB),
+
+    FSL_IMX7_WDOG4_ADDR           = 0x302B0000,
+    FSL_IMX7_WDOG3_ADDR           = 0x302A0000,
+    FSL_IMX7_WDOG2_ADDR           = 0x30290000,
+    FSL_IMX7_WDOG1_ADDR           = 0x30280000,
+
+    FSL_IMX7_IOMUXC_LPSR_GPR_ADDR = 0x30270000,
+
+    FSL_IMX7_GPIO7_ADDR           = 0x30260000,
+    FSL_IMX7_GPIO6_ADDR           = 0x30250000,
+    FSL_IMX7_GPIO5_ADDR           = 0x30240000,
+    FSL_IMX7_GPIO4_ADDR           = 0x30230000,
+    FSL_IMX7_GPIO3_ADDR           = 0x30220000,
+    FSL_IMX7_GPIO2_ADDR           = 0x30210000,
+    FSL_IMX7_GPIO1_ADDR           = 0x30200000,
+
+    FSL_IMX7_AIPS1_CONF_ADDR      = 0x301F0000,
+    FSL_IMX7_AIPS1_CONF_SIZE      = (64 * KiB),
 
-    FSL_IMX7_A7MPCORE_ADDR        = 0x31000000,
     FSL_IMX7_A7MPCORE_DAP_ADDR    = 0x30000000,
+    FSL_IMX7_A7MPCORE_DAP_SIZE    = (1 * MiB),
 
-    FSL_IMX7_PCIE_REG_ADDR        = 0x33800000,
-    FSL_IMX7_PCIE_REG_SIZE        = 16 * 1024,
+    /* AIPS-1 End */
 
-    FSL_IMX7_GPR_ADDR             = 0x30340000,
+    FSL_IMX7_EIM_CS0_ADDR         = 0x28000000,
+    FSL_IMX7_EIM_CS0_SIZE         = (128 * MiB),
 
-    FSL_IMX7_DMA_APBH_ADDR        = 0x33000000,
-    FSL_IMX7_DMA_APBH_SIZE        = 0x2000,
+    FSL_IMX7_OCRAM_PXP_ADDR       = 0x00940000,
+    FSL_IMX7_OCRAM_PXP_SIZE       = (32 * KiB),
+
+    FSL_IMX7_OCRAM_EPDC_ADDR      = 0x00920000,
+    FSL_IMX7_OCRAM_EPDC_SIZE      = (128 * KiB),
+
+    FSL_IMX7_OCRAM_MEM_ADDR       = 0x00900000,
+    FSL_IMX7_OCRAM_MEM_SIZE       = (128 * KiB),
+
+    FSL_IMX7_TCMU_ADDR            = 0x00800000,
+    FSL_IMX7_TCMU_SIZE            = (32 * KiB),
+
+    FSL_IMX7_TCML_ADDR            = 0x007F8000,
+    FSL_IMX7_TCML_SIZE            = (32 * KiB),
+
+    FSL_IMX7_OCRAM_S_ADDR         = 0x00180000,
+    FSL_IMX7_OCRAM_S_SIZE         = (32 * KiB),
+
+    FSL_IMX7_CAAM_MEM_ADDR        = 0x00100000,
+    FSL_IMX7_CAAM_MEM_SIZE        = (32 * KiB),
+
+    FSL_IMX7_ROM_ADDR             = 0x00000000,
+    FSL_IMX7_ROM_SIZE             = (96 * KiB),
 };
 
 enum FslIMX7IRQs {
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     char name[NAME_SIZE];
     int i;
 
+    /*
+     * CPUs
+     */
     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
         snprintf(name, NAME_SIZE, "cpu%d", i);
         object_initialize_child(obj, name, &s->cpu[i],
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
                             TYPE_A15MPCORE_PRIV);
 
     /*
-     * GPIOs 1 to 7
+     * GPIOs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
         snprintf(name, NAME_SIZE, "gpio%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * GPT1, 2, 3, 4
+     * GPTs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
         snprintf(name, NAME_SIZE, "gpt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      */
     object_initialize_child(obj, "gpcv2", &s->gpcv2, TYPE_IMX_GPCV2);
 
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
         snprintf(name, NAME_SIZE, "spi%d", i + 1);
         object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
     }
 
-
+    /*
+     * I2Cs
+     */
     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
         object_initialize_child(obj, name, &s->i2c[i], TYPE_IMX_I2C);
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
             snprintf(name, NAME_SIZE, "uart%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      */
     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
             snprintf(name, NAME_SIZE, "eth%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     }
 
     /*
-     * SDHCI
+     * SDHCIs
      */
     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
             snprintf(name, NAME_SIZE, "usdhc%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
     object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
             snprintf(name, NAME_SIZE, "wdt%d", i);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_init(Object *obj)
      */
     object_initialize_child(obj, "gpr", &s->gpr, TYPE_IMX7_GPR);
 
+    /*
+     * PCIE
+     */
     object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
         snprintf(name, NAME_SIZE, "usb%d", i);
         object_initialize_child(obj, name, &s->usb[i], TYPE_CHIPIDEA);
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    /*
+     * CPUs
+     */
     for (i = 0; i < smp_cpus; i++) {
         o = OBJECT(&s->cpu[i]);
 
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      * A7MPCORE DAP
      */
     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
-                                0x100000);
+                                FSL_IMX7_A7MPCORE_DAP_SIZE);
 
     /*
-     * GPT1, 2, 3, 4
+     * GPTs
      */
     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX7_GPTn_IRQ[i]));
     }
 
+    /*
+     * GPIOs
+     */
     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
             FSL_IMX7_GPIO1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     /*
      * IOMUXC and IOMUXC_LPSR
      */
-    for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
-        static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
-            FSL_IMX7_IOMUXC_ADDR,
-            FSL_IMX7_IOMUXC_LPSR_ADDR,
-        };
-
-        snprintf(name, NAME_SIZE, "iomuxc%d", i);
-        create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
-                                    FSL_IMX7_IOMUXCn_SIZE);
-    }
+    create_unimplemented_device("iomuxc", FSL_IMX7_IOMUXC_ADDR,
+                                FSL_IMX7_IOMUXC_SIZE);
+    create_unimplemented_device("iomuxc_lspr", FSL_IMX7_IOMUXC_LPSR_ADDR,
+                                FSL_IMX7_IOMUXC_LPSR_SIZE);
 
     /*
      * CCM
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     sysbus_realize(SYS_BUS_DEVICE(&s->gpcv2), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
 
-    /* Initialize all ECSPI */
+    /*
+     * ECSPIs
+     */
     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
             FSL_IMX7_ECSPI1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
                                             FSL_IMX7_SPIn_IRQ[i]));
     }
 
+    /*
+     * I2Cs
+     */
     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
             FSL_IMX7_I2C1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * UART
+     * UARTs
      */
     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * Ethernet
+     * Ethernets
      *
      * We must use two loops since phy_connected affects the other interface
      * and we have to set all properties before calling sysbus_realize().
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     }
 
     /*
-     * USDHC
+     * USDHCs
      */
     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      * SNVS
      */
     sysbus_realize(SYS_BUS_DEVICE(&s->snvs), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_HP_ADDR);
 
     /*
      * SRC
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 
     /*
-     * Watchdog
+     * Watchdogs
      */
     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("caam", FSL_IMX7_CAAM_ADDR, FSL_IMX7_CAAM_SIZE);
 
     /*
-     * PWM
+     * PWMs
      */
-    create_unimplemented_device("pwm1", FSL_IMX7_PWM1_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm2", FSL_IMX7_PWM2_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm3", FSL_IMX7_PWM3_ADDR, FSL_IMX7_PWMn_SIZE);
-    create_unimplemented_device("pwm4", FSL_IMX7_PWM4_ADDR, FSL_IMX7_PWMn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_PWMS; i++) {
+        static const hwaddr FSL_IMX7_PWMn_ADDR[FSL_IMX7_NUM_PWMS] = {
+            FSL_IMX7_PWM1_ADDR,
+            FSL_IMX7_PWM2_ADDR,
+            FSL_IMX7_PWM3_ADDR,
+            FSL_IMX7_PWM4_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "pwm%d", i);
+        create_unimplemented_device(name, FSL_IMX7_PWMn_ADDR[i],
+                                    FSL_IMX7_PWMn_SIZE);
+    }
 
     /*
-     * CAN
+     * CANs
      */
-    create_unimplemented_device("can1", FSL_IMX7_CAN1_ADDR, FSL_IMX7_CANn_SIZE);
-    create_unimplemented_device("can2", FSL_IMX7_CAN2_ADDR, FSL_IMX7_CANn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_CANS; i++) {
+        static const hwaddr FSL_IMX7_CANn_ADDR[FSL_IMX7_NUM_CANS] = {
+            FSL_IMX7_CAN1_ADDR,
+            FSL_IMX7_CAN2_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "can%d", i);
+        create_unimplemented_device(name, FSL_IMX7_CANn_ADDR[i],
+                                    FSL_IMX7_CANn_SIZE);
+    }
 
     /*
-     * SAI (Audio SSI (Synchronous Serial Interface))
+     * SAIs (Audio SSI (Synchronous Serial Interface))
      */
-    create_unimplemented_device("sai1", FSL_IMX7_SAI1_ADDR, FSL_IMX7_SAIn_SIZE);
-    create_unimplemented_device("sai2", FSL_IMX7_SAI2_ADDR, FSL_IMX7_SAIn_SIZE);
-    create_unimplemented_device("sai2", FSL_IMX7_SAI3_ADDR, FSL_IMX7_SAIn_SIZE);
+    for (i = 0; i < FSL_IMX7_NUM_SAIS; i++) {
+        static const hwaddr FSL_IMX7_SAIn_ADDR[FSL_IMX7_NUM_SAIS] = {
+            FSL_IMX7_SAI1_ADDR,
+            FSL_IMX7_SAI2_ADDR,
+            FSL_IMX7_SAI3_ADDR,
+        };
+
+        snprintf(name, NAME_SIZE, "sai%d", i);
+        create_unimplemented_device(name, FSL_IMX7_SAIn_ADDR[i],
+                                    FSL_IMX7_SAIn_SIZE);
+    }
 
     /*
      * OCOTP
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("ocotp", FSL_IMX7_OCOTP_ADDR,
                                 FSL_IMX7_OCOTP_SIZE);
 
+    /*
+     * GPR
+     */
     sysbus_realize(SYS_BUS_DEVICE(&s->gpr), &error_abort);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_IOMUXC_GPR_ADDR);
 
+    /*
+     * PCIE
+     */
     sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
 
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
 
-
+    /*
+     * USBs
+     */
     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
             FSL_IMX7_USBMISC1_ADDR,
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
      */
     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                 FSL_IMX7_PCIE_PHY_SIZE);
+
 }
 
 static Property fsl_imx7_properties[] = {
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: f887a3483996ba06d40bd62ffdfb0ecf68621987.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h |  7 +++++
 hw/arm/fsl-imx7.c         | 63 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)

diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@ struct FslIMX7State {
     IMX7GPRState       gpr;
     ChipideaState      usb[FSL_IMX7_NUM_USBS];
     DesignwarePCIEHost pcie;
+    MemoryRegion       rom;
+    MemoryRegion       caam;
+    MemoryRegion       ocram;
+    MemoryRegion       ocram_epdc;
+    MemoryRegion       ocram_pxp;
+    MemoryRegion       ocram_s;
+
     uint32_t           phy_num[FSL_IMX7_NUM_ETHS];
     bool               phy_connected[FSL_IMX7_NUM_ETHS];
 };
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -XXX,XX +XXX,XX @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
                                 FSL_IMX7_PCIE_PHY_SIZE);
 
+    /*
+     * CSU
+     */
+    create_unimplemented_device("csu", FSL_IMX7_CSU_ADDR,
+                                FSL_IMX7_CSU_SIZE);
+
+    /*
+     * TZASC
+     */
+    create_unimplemented_device("tzasc", FSL_IMX7_TZASC_ADDR,
+                                FSL_IMX7_TZASC_SIZE);
+
+    /*
+     * OCRAM memory
+     */
+    memory_region_init_ram(&s->ocram, NULL, "imx7.ocram",
+                           FSL_IMX7_OCRAM_MEM_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_MEM_ADDR,
+                                &s->ocram);
+
+    /*
+     * OCRAM EPDC memory
+     */
+    memory_region_init_ram(&s->ocram_epdc, NULL, "imx7.ocram_epdc",
+                           FSL_IMX7_OCRAM_EPDC_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_EPDC_ADDR,
+                                &s->ocram_epdc);
+
+    /*
+     * OCRAM PXP memory
+     */
+    memory_region_init_ram(&s->ocram_pxp, NULL, "imx7.ocram_pxp",
+                           FSL_IMX7_OCRAM_PXP_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_PXP_ADDR,
+                                &s->ocram_pxp);
+
+    /*
+     * OCRAM_S memory
+     */
+    memory_region_init_ram(&s->ocram_s, NULL, "imx7.ocram_s",
+                           FSL_IMX7_OCRAM_S_SIZE,
+                           &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_OCRAM_S_ADDR,
+                                &s->ocram_s);
+
+    /*
+     * ROM memory
+     */
+    memory_region_init_rom(&s->rom, OBJECT(dev), "imx7.rom",
+                           FSL_IMX7_ROM_SIZE, &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_ROM_ADDR,
+                                &s->rom);
+
+    /*
+     * CAAM memory
+     */
+    memory_region_init_rom(&s->caam, OBJECT(dev), "imx7.caam",
+                           FSL_IMX7_CAAM_MEM_SIZE, &error_abort);
+    memory_region_add_subregion(get_system_memory(), FSL_IMX7_CAAM_MEM_ADDR,
+                                &s->caam);
 }
 
 static Property fsl_imx7_properties[] = {
-- 
2.34.1

From: Jean-Christophe Dubois <jcd@tribudubois.net>

The SRC device is normally used to start the secondary CPU.

When running Linux directly, QEMU is emulating a PSCI interface that UBOOT
is installing at boot time and therefore the fact that the SRC device is
unimplemented is hidden as Qemu respond directly to PSCI requets without
using the SRC device.

But if you try to run a more bare metal application (maybe uboot itself),
then it is not possible to start the secondary CPU as the SRC is an
unimplemented device.

This patch adds the ability to start the secondary CPU through the SRC
device so that you can use this feature in bare metal applications.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: ce9a0162defd2acee5dc7f8a674743de0cded569.1692964892.git.jcd@tribudubois.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/fsl-imx7.h  |   3 +-
 include/hw/misc/imx7_src.h |  66 +++++++++
 hw/arm/fsl-imx7.c          |   8 +-
 hw/misc/imx7_src.c         | 276 +++++++++++++++++++++++++++++++++++++
 hw/misc/meson.build        |   1 +
 hw/misc/trace-events       |   4 +
 6 files changed, 356 insertions(+), 2 deletions(-)
 create mode 100644 include/hw/misc/imx7_src.h
 create mode 100644 hw/misc/imx7_src.c

The architecture requires (R_TYTWB) that an attempt to return from EL3
when SCR_EL3.{NSE,NS} are {1,0} is an illegal exception return. (This
enforces that the CPU can't ever be executing below EL3 with the
NSE,NS bits indicating an invalid security state.)

We were missing this check; add it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230807150618.101357-1-peter.maydell@linaro.org
---
 target/arm/tcg/helper-a64.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
         spsr &= ~PSTATE_SS;
     }
 
+    /*
+     * FEAT_RME forbids return from EL3 with an invalid security state.
+     * We don't need an explicit check for FEAT_RME here because we enforce
+     * in scr_write() that you can't set the NSE bit without it.
+     */
+    if (cur_el == 3 && (env->cp15.scr_el3 & (SCR_NS | SCR_NSE)) == SCR_NSE) {
+        goto illegal_return;
+    }
+
     new_el = el_from_spsr(spsr);
     if (new_el == -1) {
         goto illegal_return;
-- 
2.34.1

In the aspeed_rtc device we store a difference between two time_t
values in an 'int'. This is not really correct when time_t could
be 64 bits. Enlarge the field to 'int64_t'.

This is a migration compatibility break for the aspeed boards.
While we are changing the vmstate, remove the accidental
duplicate of the offset field.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/rtc/aspeed_rtc.h | 2 +-
 hw/rtc/aspeed_rtc.c         | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/include/hw/rtc/aspeed_rtc.h b/include/hw/rtc/aspeed_rtc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/rtc/aspeed_rtc.h
+++ b/include/hw/rtc/aspeed_rtc.h
@@ -XXX,XX +XXX,XX @@ struct AspeedRtcState {
     qemu_irq irq;
 
     uint32_t reg[0x18];
-    int offset;
+    int64_t offset;
 
 };
 
diff --git a/hw/rtc/aspeed_rtc.c b/hw/rtc/aspeed_rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/rtc/aspeed_rtc.c
+++ b/hw/rtc/aspeed_rtc.c
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps aspeed_rtc_ops = {
 
 static const VMStateDescription vmstate_aspeed_rtc = {
     .name = TYPE_ASPEED_RTC,
-    .version_id = 1,
+    .version_id = 2,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
-        VMSTATE_INT32(offset, AspeedRtcState),
-        VMSTATE_INT32(offset, AspeedRtcState),
+        VMSTATE_INT64(offset, AspeedRtcState),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
2.34.1

The functions qemu_get_timedate() and qemu_timedate_diff() take
and return a time offset as an integer. Coverity points out that
means that when an RTC device implementation holds an offset
as a time_t, as the m48t59 does, the time_t will get truncated.
(CID 1507157, 1517772).

The functions work with time_t internally, so make them use that type
in their APIs.

Note that this won't help any Y2038 issues where either the device
model itself is keeping the offset in a 32-bit integer, or where the
hardware under emulation has Y2038 or other rollover problems.  If we
missed any cases of the former then hopefully Coverity will warn us
about them since after this patch we'd be truncating a time_t in
assignments from qemu_timedate_diff().)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/sysemu/rtc.h | 4 ++--
 softmmu/rtc.c        | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/sysemu/rtc.h b/include/sysemu/rtc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/sysemu/rtc.h
+++ b/include/sysemu/rtc.h
@@ -XXX,XX +XXX,XX @@
  * The behaviour of the clock whose value this function returns will
  * depend on the -rtc command line option passed by the user.
  */
-void qemu_get_timedate(struct tm *tm, int offset);
+void qemu_get_timedate(struct tm *tm, time_t offset);
 
 /**
  * qemu_timedate_diff: Return difference between a struct tm and the RTC
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset);
  * a timestamp one hour further ahead than the current RTC time
  * then this function will return 3600.
  */
-int qemu_timedate_diff(struct tm *tm);
+time_t qemu_timedate_diff(struct tm *tm);
 
 #endif
diff --git a/softmmu/rtc.c b/softmmu/rtc.c
index XXXXXXX..XXXXXXX 100644
--- a/softmmu/rtc.c
+++ b/softmmu/rtc.c
@@ -XXX,XX +XXX,XX @@ static time_t qemu_ref_timedate(QEMUClockType clock)
     return value;
 }
 
-void qemu_get_timedate(struct tm *tm, int offset)
+void qemu_get_timedate(struct tm *tm, time_t offset)
 {
     time_t ti = qemu_ref_timedate(rtc_clock);
 
@@ -XXX,XX +XXX,XX @@ void qemu_get_timedate(struct tm *tm, int offset)
     }
 }
 
-int qemu_timedate_diff(struct tm *tm)
+time_t qemu_timedate_diff(struct tm *tm)
 {
     time_t seconds;
 
-- 
2.34.1

Where architecturally one ARM_FEATURE_X flag implies another
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
set Y for it.  Currently we do this in two places -- we set a few
flags in arm_cpu_post_init() because we need them to decide which
properties to create on the CPU object, and then we do the rest in
arm_cpu_realizefn().  However, this is fragile, because it's easy to
add a new property and not notice that this means that an X-implies-Y
check now has to move from realize to post-init.

As a specific example, the pmsav7-dregion property is conditional
on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
rely on V8-implies-V7, which doesn't happen until the realizefn.

Move all of these X-implies-Y checks into a new function, which
we call at the top of arm_cpu_post_init(), so the feature bits
are available at that point.

This does now give us the reverse issue, that if there's a feature
bit which is enabled or disabled by the setting of a property then
then X-implies-Y features that are dependent on that property need to
be in realize, not in this new function.  But the only one of those
is the "EL3 implies VBAR" which is already in the right place, so
putting things this way round seems better to me.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
---
 target/arm/cpu.c | 179 +++++++++++++++++++++++++----------------------
 1 file changed, 97 insertions(+), 82 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ unsigned int gt_cntfrq_period_ns(ARMCPU *cpu)
       NANOSECONDS_PER_SECOND / cpu->gt_cntfrq_hz : 1;
 }
 
+static void arm_cpu_propagate_feature_implications(ARMCPU *cpu)
+{
+    CPUARMState *env = &cpu->env;
+    bool no_aa32 = false;
+
+    /*
+     * Some features automatically imply others: set the feature
+     * bits explicitly for these cases.
+     */
+
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_PMSA);
+    }
+
+    if (arm_feature(env, ARM_FEATURE_V8)) {
+        if (arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V7);
+        } else {
+            set_feature(env, ARM_FEATURE_V7VE);
+        }
+    }
+
+    /*
+     * There exist AArch64 cpus without AArch32 support.  When KVM
+     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
+     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
+     * As a general principle, we also do not make ID register
+     * consistency checks anywhere unless using TCG, because only
+     * for TCG would a consistency-check failure be a QEMU bug.
+     */
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
+    }
+
+    if (arm_feature(env, ARM_FEATURE_V7VE)) {
+        /*
+         * v7 Virtualization Extensions. In real hardware this implies
+         * EL2 and also the presence of the Security Extensions.
+         * For QEMU, for backwards-compatibility we implement some
+         * CPUs or CPU configs which have no actual EL2 or EL3 but do
+         * include the various other features that V7VE implies.
+         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
+         * Security Extensions is ARM_FEATURE_EL3.
+         */
+        assert(!tcg_enabled() || no_aa32 ||
+               cpu_isar_feature(aa32_arm_div, cpu));
+        set_feature(env, ARM_FEATURE_LPAE);
+        set_feature(env, ARM_FEATURE_V7);
+    }
+    if (arm_feature(env, ARM_FEATURE_V7)) {
+        set_feature(env, ARM_FEATURE_VAPA);
+        set_feature(env, ARM_FEATURE_THUMB2);
+        set_feature(env, ARM_FEATURE_MPIDR);
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            set_feature(env, ARM_FEATURE_V6K);
+        } else {
+            set_feature(env, ARM_FEATURE_V6);
+        }
+
+        /*
+         * Always define VBAR for V7 CPUs even if it doesn't exist in
+         * non-EL3 configs. This is needed by some legacy boards.
+         */
+        set_feature(env, ARM_FEATURE_VBAR);
+    }
+    if (arm_feature(env, ARM_FEATURE_V6K)) {
+        set_feature(env, ARM_FEATURE_V6);
+        set_feature(env, ARM_FEATURE_MVFR);
+    }
+    if (arm_feature(env, ARM_FEATURE_V6)) {
+        set_feature(env, ARM_FEATURE_V5);
+        if (!arm_feature(env, ARM_FEATURE_M)) {
+            assert(!tcg_enabled() || no_aa32 ||
+                   cpu_isar_feature(aa32_jazelle, cpu));
+            set_feature(env, ARM_FEATURE_AUXCR);
+        }
+    }
+    if (arm_feature(env, ARM_FEATURE_V5)) {
+        set_feature(env, ARM_FEATURE_V4T);
+    }
+    if (arm_feature(env, ARM_FEATURE_LPAE)) {
+        set_feature(env, ARM_FEATURE_V7MP);
+    }
+    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
+        set_feature(env, ARM_FEATURE_CBAR);
+    }
+    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
+        !arm_feature(env, ARM_FEATURE_M)) {
+        set_feature(env, ARM_FEATURE_THUMB_DSP);
+    }
+}
+
 void arm_cpu_post_init(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
 
-    /* M profile implies PMSA. We have to do this here rather than
-     * in realize with the other feature-implication checks because
-     * we look at the PMSA bit to see if we should add some properties.
+    /*
+     * Some features imply others. Figure this out now, because we
+     * are going to look at the feature bits in deciding which
+     * properties to add.
      */
-    if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
-        set_feature(&cpu->env, ARM_FEATURE_PMSA);
-    }
+    arm_cpu_propagate_feature_implications(cpu);
 
     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     CPUARMState *env = &cpu->env;
     int pagebits;
     Error *local_err = NULL;
-    bool no_aa32 = false;
 
     /* Use pc-relative instructions in system-mode */
 #ifndef CONFIG_USER_ONLY
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         cpu->isar.id_isar3 = u;
     }
 
-    /* Some features automatically imply others: */
-    if (arm_feature(env, ARM_FEATURE_V8)) {
-        if (arm_feature(env, ARM_FEATURE_M)) {
-            set_feature(env, ARM_FEATURE_V7);
-        } else {
-            set_feature(env, ARM_FEATURE_V7VE);
-        }
-    }
-
-    /*
-     * There exist AArch64 cpus without AArch32 support.  When KVM
-     * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
-     * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
-     * As a general principle, we also do not make ID register
-     * consistency checks anywhere unless using TCG, because only
-     * for TCG would a consistency-check failure be a QEMU bug.
-     */
-    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
-        no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
-    }
-
-    if (arm_feature(env, ARM_FEATURE_V7VE)) {
-        /* v7 Virtualization Extensions. In real hardware this implies
-         * EL2 and also the presence of the Security Extensions.
-         * For QEMU, for backwards-compatibility we implement some
-         * CPUs or CPU configs which have no actual EL2 or EL3 but do
-         * include the various other features that V7VE implies.
-         * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
-         * Security Extensions is ARM_FEATURE_EL3.
-         */
-        assert(!tcg_enabled() || no_aa32 ||
-               cpu_isar_feature(aa32_arm_div, cpu));
-        set_feature(env, ARM_FEATURE_LPAE);
-        set_feature(env, ARM_FEATURE_V7);
-    }
-    if (arm_feature(env, ARM_FEATURE_V7)) {
-        set_feature(env, ARM_FEATURE_VAPA);
-        set_feature(env, ARM_FEATURE_THUMB2);
-        set_feature(env, ARM_FEATURE_MPIDR);
-        if (!arm_feature(env, ARM_FEATURE_M)) {
-            set_feature(env, ARM_FEATURE_V6K);
-        } else {
-            set_feature(env, ARM_FEATURE_V6);
-        }
-
-        /* Always define VBAR for V7 CPUs even if it doesn't exist in
-         * non-EL3 configs. This is needed by some legacy boards.
-         */
-        set_feature(env, ARM_FEATURE_VBAR);
-    }
-    if (arm_feature(env, ARM_FEATURE_V6K)) {
-        set_feature(env, ARM_FEATURE_V6);
-        set_feature(env, ARM_FEATURE_MVFR);
-    }
-    if (arm_feature(env, ARM_FEATURE_V6)) {
-        set_feature(env, ARM_FEATURE_V5);
-        if (!arm_feature(env, ARM_FEATURE_M)) {
-            assert(!tcg_enabled() || no_aa32 ||
-                   cpu_isar_feature(aa32_jazelle, cpu));
-            set_feature(env, ARM_FEATURE_AUXCR);
-        }
-    }
-    if (arm_feature(env, ARM_FEATURE_V5)) {
-        set_feature(env, ARM_FEATURE_V4T);
-    }
-    if (arm_feature(env, ARM_FEATURE_LPAE)) {
-        set_feature(env, ARM_FEATURE_V7MP);
-    }
-    if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
-        set_feature(env, ARM_FEATURE_CBAR);
-    }
-    if (arm_feature(env, ARM_FEATURE_THUMB2) &&
-        !arm_feature(env, ARM_FEATURE_M)) {
-        set_feature(env, ARM_FEATURE_THUMB_DSP);
-    }
 
     /*
      * We rely on no XScale CPU having VFP so we can use the same bits in the
-- 
2.34.1

M-profile CPUs generally allow configuration of the number of MPU
regions that they have.  We don't currently model this, so our
implementations of some of the board models provide CPUs with the
wrong number of regions.  RTOSes like Zephyr that hardcode the
expected number of regions may therefore not run on the model if they
are set up to run on real hardware.

Add properties mpu-ns-regions and mpu-s-regions to the ARMV7M object,
matching the ability of hardware to configure the number of Secure
and NonSecure regions separately.  Our actual CPU implementation
doesn't currently support that, and it happens that none of the MPS
boards we model set the number of regions differently for Secure vs
NonSecure, so we provide an interface to the boards and SoCs that
won't need to change if we ever do add that functionality in future,
but make it an error to configure the two properties to different
values.

(The property name on the CPU is the somewhat misnamed-for-M-profile
"pmsav7-dregion", so we don't follow that naming convention for
the properties here. The TRM doesn't say what the CPU configuration
variable names are, so we pick something, and follow the lowercase
convention we already have for properties here.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-3-peter.maydell@linaro.org
---
 include/hw/arm/armv7m.h |  8 ++++++++
 hw/arm/armv7m.c         | 21 +++++++++++++++++++++
 2 files changed, 29 insertions(+)

diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armv7m.h
+++ b/include/hw/arm/armv7m.h
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(ARMv7MState, ARMV7M)
  * + Property "vfp": enable VFP (forwarded to CPU object)
  * + Property "dsp": enable DSP (forwarded to CPU object)
  * + Property "enable-bitband": expose bitbanded IO
+ * + Property "mpu-ns-regions": number of Non-Secure MPU regions (forwarded
+ *   to CPU object pmsav7-dregion property; default is whatever the default
+ *   for the CPU is)
+ * + Property "mpu-s-regions": number of Secure MPU regions (default is
+ *   whatever the default for the CPU is; must currently be set to the same
+ *   value as mpu-ns-regions if the CPU implements the Security Extension)
  * + Clock input "refclk" is the external reference clock for the systick timers
  * + Clock input "cpuclk" is the main CPU clock
  */
@@ -XXX,XX +XXX,XX @@ struct ARMv7MState {
     Object *idau;
     uint32_t init_svtor;
     uint32_t init_nsvtor;
+    uint32_t mpu_ns_regions;
+    uint32_t mpu_s_regions;
     bool enable_bitband;
     bool start_powered_off;
     bool vfp;
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
         }
     }
 
+    /*
+     * Real M-profile hardware can be configured with a different number of
+     * MPU regions for Secure vs NonSecure. QEMU's CPU implementation doesn't
+     * support that yet, so catch attempts to select that.
+     */
+    if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
+        s->mpu_ns_regions != s->mpu_s_regions) {
+        error_setg(errp,
+                   "mpu-ns-regions and mpu-s-regions properties must have the same value");
+        return;
+    }
+    if (s->mpu_ns_regions != UINT_MAX &&
+        object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) {
+        if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion",
+                                      s->mpu_ns_regions, errp)) {
+            return;
+        }
+    }
+
     /*
      * Tell the CPU where the NVIC is; it will fail realize if it doesn't
      * have one. Similarly, tell the NVIC where its CPU is.
@@ -XXX,XX +XXX,XX @@ static Property armv7m_properties[] = {
                      false),
     DEFINE_PROP_BOOL("vfp", ARMv7MState, vfp, true),
     DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true),
+    DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX),
+    DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
2.34.1

The IoTKit, SSE200 and SSE300 all default to 8 MPU regions.  The
MPS2/MPS3 FPGA images don't override these except in the case of
AN547, which uses 16 MPU regions.

Define properties on the ARMSSE object for the MPU regions (using the
same names as the documented RTL configuration settings, and
following the pattern we already have for this device of using
all-caps names as the RTL does), and set them in the board code.

We don't actually need to override the default except on AN547,
but it's simpler code to have the board code set them always
rather than tracking which board subtypes want to set them to
a non-default value separately from what that value is.

Tho overall effect is that for mps2-an505, mps2-an521 and mps3-an524
we now correctly use 8 MPU regions, while mps3-an547 stays at its
current 16 regions.

It's possible some guest code wrongly depended on the previous
incorrectly modeled number of memory regions. (Such guest code
should ideally check the number of regions via the MPU_TYPE
register.) The old behaviour can be obtained with additional
-global arguments to QEMU:

For mps2-an521 and mps2-an524:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16 -global sse-200.CPU1_MPU_NS=16 -global sse-200.CPU1_MPU_S=16

For mps2-an505:
 -global sse-200.CPU0_MPU_NS=16 -global sse-200.CPU0_MPU_S=16

NB that the way the implementation allows this use of -global
is slightly fragile: if the board code explicitly sets the
properties on the sse-200 object, this overrides the -global
command line option. So we rely on:
 - the boards that need fixing all happen to use the SSE defaults
 - we can write the board code to only set the property if it
   is different from the default, rather than having all boards
   explicitly set the property
 - the board that does need to use a non-default value happens
   to need to set it to the same value (16) we previously used
This works, but there are some kinds of refactoring of the
mps2-tz.c code that would break the support for -global here.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1772
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230724174335.2150499-4-peter.maydell@linaro.org
---
 include/hw/arm/armsse.h |  5 +++++
 hw/arm/armsse.c         | 16 ++++++++++++++++
 hw/arm/mps2-tz.c        | 29 +++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)

diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -XXX,XX +XXX,XX @@
  *    (matching the hardware) is that for CPU0 in an IoTKit and CPU1 in an
  *    SSE-200 both are present; CPU0 in an SSE-200 has neither.
  *    Since the IoTKit has only one CPU, it does not have the CPU1_* properties.
+ *  + QOM properties "CPU0_MPU_NS", "CPU0_MPU_S", "CPU1_MPU_NS" and "CPU1_MPU_S"
+ *    which set the number of MPU regions on the CPUs. If there is only one
+ *    CPU the CPU1 properties are not present.
  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
  *    which are wired to its NVIC lines 32 .. n+32
  *  + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
@@ -XXX,XX +XXX,XX @@ struct ARMSSE {
     uint32_t exp_numirq;
     uint32_t sram_addr_width;
     uint32_t init_svtor;
+    uint32_t cpu_mpu_ns[SSE_MAX_CPUS];
+    uint32_t cpu_mpu_s[SSE_MAX_CPUS];
     bool cpu_fpu[SSE_MAX_CPUS];
     bool cpu_dsp[SSE_MAX_CPUS];
 };
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static Property iotkit_properties[] = {
     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static Property sse200_properties[] = {
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], false),
     DEFINE_PROP_BOOL("CPU1_FPU", ARMSSE, cpu_fpu[1], true),
     DEFINE_PROP_BOOL("CPU1_DSP", ARMSSE, cpu_dsp[1], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
+    DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8),
+    DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static Property sse300_properties[] = {
     DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
     DEFINE_PROP_BOOL("CPU0_FPU", ARMSSE, cpu_fpu[0], true),
     DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true),
+    DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8),
+    DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8),
     DEFINE_PROP_END_OF_LIST()
 };
 
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                 return;
             }
         }
+        if (!object_property_set_uint(cpuobj, "mpu-ns-regions",
+                                      s->cpu_mpu_ns[i], errp)) {
+            return;
+        }
+        if (!object_property_set_uint(cpuobj, "mpu-s-regions",
+                                      s->cpu_mpu_s[i], errp)) {
+            return;
+        }
 
         if (i > 0) {
             memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@ struct MPS2TZMachineClass {
     int uart_overflow_irq; /* number of the combined UART overflow IRQ */
     uint32_t init_svtor; /* init-svtor setting for SSE */
     uint32_t sram_addr_width; /* SRAM_ADDR_WIDTH setting for SSE */
+    uint32_t cpu0_mpu_ns; /* CPU0_MPU_NS setting for SSE */
+    uint32_t cpu0_mpu_s; /* CPU0_MPU_S setting for SSE */
+    uint32_t cpu1_mpu_ns; /* CPU1_MPU_NS setting for SSE */
+    uint32_t cpu1_mpu_s; /* CPU1_MPU_S setting for SSE */
     const RAMInfo *raminfo;
     const char *armsse_type;
     uint32_t boot_ram_size; /* size of ram at address 0; 0 == find in raminfo */
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE)
 #define MPS3_DDR_SIZE (2 * GiB)
 #endif
 
+/* For cpu{0,1}_mpu_{ns,s}, means "leave at SSE's default value" */
+#define MPU_REGION_DEFAULT UINT32_MAX
+
 static const uint32_t an505_oscclk[] = {
     40000000,
     24580000,
@@ -XXX,XX +XXX,XX @@ static void mps2tz_common_init(MachineState *machine)
                              OBJECT(system_memory), &error_abort);
     qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq);
     qdev_prop_set_uint32(iotkitdev, "init-svtor", mmc->init_svtor);
+    if (mmc->cpu0_mpu_ns != MPU_REGION_DEFAULT) {
+        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_NS", mmc->cpu0_mpu_ns);
+    }
+    if (mmc->cpu0_mpu_s != MPU_REGION_DEFAULT) {
+        qdev_prop_set_uint32(iotkitdev, "CPU0_MPU_S", mmc->cpu0_mpu_s);
+    }
+    if (object_property_find(OBJECT(iotkitdev), "CPU1_MPU_NS")) {
+        if (mmc->cpu1_mpu_ns != MPU_REGION_DEFAULT) {
+            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_NS", mmc->cpu1_mpu_ns);
+        }
+        if (mmc->cpu1_mpu_s != MPU_REGION_DEFAULT) {
+            qdev_prop_set_uint32(iotkitdev, "CPU1_MPU_S", mmc->cpu1_mpu_s);
+        }
+    }
     qdev_prop_set_uint32(iotkitdev, "SRAM_ADDR_WIDTH", mmc->sram_addr_width);
     qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk);
     qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk);
@@ -XXX,XX +XXX,XX @@ static void mps2tz_class_init(ObjectClass *oc, void *data)
 {
     MachineClass *mc = MACHINE_CLASS(oc);
     IDAUInterfaceClass *iic = IDAU_INTERFACE_CLASS(oc);
+    MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc);
 
     mc->init = mps2tz_common_init;
     mc->reset = mps2_machine_reset;
     iic->check = mps2_tz_idau_check;
+
+    /* Most machines leave these at the SSE defaults */
+    mmc->cpu0_mpu_ns = MPU_REGION_DEFAULT;
+    mmc->cpu0_mpu_s = MPU_REGION_DEFAULT;
+    mmc->cpu1_mpu_ns = MPU_REGION_DEFAULT;
+    mmc->cpu1_mpu_s = MPU_REGION_DEFAULT;
 }
 
 static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc)
@@ -XXX,XX +XXX,XX @@ static void mps3tz_an547_class_init(ObjectClass *oc, void *data)
     mmc->numirq = 96;
     mmc->uart_overflow_irq = 48;
     mmc->init_svtor = 0x00000000;
+    mmc->cpu0_mpu_s = mmc->cpu0_mpu_ns = 16;
     mmc->sram_addr_width = 21;
     mmc->raminfo = an547_raminfo;
     mmc->armsse_type = TYPE_SSE300;
-- 
2.34.1